stats.txt (10242:cb4e86c17767) | stats.txt (10352:5f1f92bf76ee) |
---|---|
1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
3sim_seconds 0.000111 # Number of seconds simulated 4sim_ticks 110970500 # Number of ticks simulated 5final_tick 110970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000106 # Number of seconds simulated 4sim_ticks 105639000 # Number of ticks simulated 5final_tick 105639000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 128659 # Simulator instruction rate (inst/s) 8host_op_rate 128659 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 13699808 # Simulator tick rate (ticks/s) 10host_mem_usage 244656 # Number of bytes of host memory used 11host_seconds 8.10 # Real time elapsed on the host 12sim_insts 1042156 # Number of instructions simulated 13sim_ops 1042156 # Number of ops (including micro ops) simulated | 7host_inst_rate 115016 # Simulator instruction rate (inst/s) 8host_op_rate 115016 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 12246117 # Simulator tick rate (ticks/s) 10host_mem_usage 253808 # Number of bytes of host memory used 11host_seconds 8.63 # Real time elapsed on the host 12sim_insts 992165 # Number of instructions simulated 13sim_ops 992165 # Number of ops (including micro ops) simulated |
14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
16system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu0.inst 23104 # Number of bytes read from this memory |
17system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory |
18system.physmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory |
19system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory | 19system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory |
20system.physmem.bytes_read::cpu2.inst 4608 # Number of bytes read from this memory | 20system.physmem.bytes_read::cpu2.inst 4928 # Number of bytes read from this memory |
21system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory | 21system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory |
24system.physmem.bytes_read::total 42176 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 22784 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 832 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu2.inst 4608 # Number of instructions bytes read from this memory | 24system.physmem.bytes_read::total 42752 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 23104 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu2.inst 4928 # Number of instructions bytes read from this memory |
28system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory | 28system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory |
29system.physmem.bytes_inst_read::total 28480 # Number of instructions bytes read from this memory 30system.physmem.num_reads::cpu0.inst 356 # Number of read requests responded to by this memory | 29system.physmem.bytes_inst_read::total 29056 # Number of instructions bytes read from this memory 30system.physmem.num_reads::cpu0.inst 361 # Number of read requests responded to by this memory |
31system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory | 31system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory |
32system.physmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory | 32system.physmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory |
33system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory | 33system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory |
34system.physmem.num_reads::cpu2.inst 72 # Number of read requests responded to by this memory | 34system.physmem.num_reads::cpu2.inst 77 # Number of read requests responded to by this memory |
35system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory | 35system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory |
38system.physmem.num_reads::total 659 # Number of read requests responded to by this memory 39system.physmem.bw_read::cpu0.inst 205315827 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu0.data 96890615 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu1.inst 7497488 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.data 7497488 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu2.inst 41524549 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu2.data 11534597 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu3.inst 2306919 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu3.data 7497488 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::total 380064972 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu0.inst 205315827 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu1.inst 7497488 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::cpu2.inst 41524549 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu3.inst 2306919 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::total 256644784 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_total::cpu0.inst 205315827 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu0.data 96890615 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu1.inst 7497488 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.data 7497488 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu2.inst 41524549 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.data 11534597 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu3.inst 2306919 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.data 7497488 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::total 380064972 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.readReqs 660 # Number of read requests accepted | 38system.physmem.num_reads::total 668 # Number of read requests responded to by this memory 39system.physmem.bw_read::cpu0.inst 218707106 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu0.data 101780592 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu1.inst 7270042 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.data 7875879 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu2.inst 46649438 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu2.data 12116737 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu3.inst 2423347 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu3.data 7875879 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::total 404699022 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu0.inst 218707106 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu1.inst 7270042 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::cpu2.inst 46649438 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu3.inst 2423347 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::total 275049934 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_total::cpu0.inst 218707106 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu0.data 101780592 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu1.inst 7270042 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.data 7875879 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu2.inst 46649438 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.data 12116737 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu3.inst 2423347 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.data 7875879 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::total 404699022 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.readReqs 669 # Number of read requests accepted |
63system.physmem.writeReqs 0 # Number of write requests accepted | 63system.physmem.writeReqs 0 # Number of write requests accepted |
64system.physmem.readBursts 660 # Number of DRAM read bursts, including those serviced by the write queue | 64system.physmem.readBursts 669 # Number of DRAM read bursts, including those serviced by the write queue |
65system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 65system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
66system.physmem.bytesReadDRAM 42240 # Total number of bytes read from DRAM | 66system.physmem.bytesReadDRAM 42816 # Total number of bytes read from DRAM |
67system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 68system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 67system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 68system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
69system.physmem.bytesReadSys 42240 # Total read bytes from the system interface side | 69system.physmem.bytesReadSys 42816 # Total read bytes from the system interface side |
70system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 71system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 72system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 70system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 71system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 72system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
73system.physmem.neitherReadNorWriteReqs 77 # Number of requests that are neither read nor write 74system.physmem.perBankRdBursts::0 115 # Per bank write bursts 75system.physmem.perBankRdBursts::1 39 # Per bank write bursts 76system.physmem.perBankRdBursts::2 29 # Per bank write bursts | 73system.physmem.neitherReadNorWriteReqs 78 # Number of requests that are neither read nor write 74system.physmem.perBankRdBursts::0 114 # Per bank write bursts 75system.physmem.perBankRdBursts::1 42 # Per bank write bursts 76system.physmem.perBankRdBursts::2 30 # Per bank write bursts |
77system.physmem.perBankRdBursts::3 60 # Per bank write bursts 78system.physmem.perBankRdBursts::4 65 # Per bank write bursts | 77system.physmem.perBankRdBursts::3 60 # Per bank write bursts 78system.physmem.perBankRdBursts::4 65 # Per bank write bursts |
79system.physmem.perBankRdBursts::5 27 # Per bank write bursts | 79system.physmem.perBankRdBursts::5 28 # Per bank write bursts |
80system.physmem.perBankRdBursts::6 18 # Per bank write bursts 81system.physmem.perBankRdBursts::7 24 # Per bank write bursts 82system.physmem.perBankRdBursts::8 7 # Per bank write bursts 83system.physmem.perBankRdBursts::9 28 # Per bank write bursts 84system.physmem.perBankRdBursts::10 23 # Per bank write bursts | 80system.physmem.perBankRdBursts::6 18 # Per bank write bursts 81system.physmem.perBankRdBursts::7 24 # Per bank write bursts 82system.physmem.perBankRdBursts::8 7 # Per bank write bursts 83system.physmem.perBankRdBursts::9 28 # Per bank write bursts 84system.physmem.perBankRdBursts::10 23 # Per bank write bursts |
85system.physmem.perBankRdBursts::11 12 # Per bank write bursts 86system.physmem.perBankRdBursts::12 60 # Per bank write bursts | 85system.physmem.perBankRdBursts::11 13 # Per bank write bursts 86system.physmem.perBankRdBursts::12 65 # Per bank write bursts |
87system.physmem.perBankRdBursts::13 38 # Per bank write bursts 88system.physmem.perBankRdBursts::14 17 # Per bank write bursts | 87system.physmem.perBankRdBursts::13 38 # Per bank write bursts 88system.physmem.perBankRdBursts::14 17 # Per bank write bursts |
89system.physmem.perBankRdBursts::15 98 # Per bank write bursts | 89system.physmem.perBankRdBursts::15 97 # Per bank write bursts |
90system.physmem.perBankWrBursts::0 0 # Per bank write bursts 91system.physmem.perBankWrBursts::1 0 # Per bank write bursts 92system.physmem.perBankWrBursts::2 0 # Per bank write bursts 93system.physmem.perBankWrBursts::3 0 # Per bank write bursts 94system.physmem.perBankWrBursts::4 0 # Per bank write bursts 95system.physmem.perBankWrBursts::5 0 # Per bank write bursts 96system.physmem.perBankWrBursts::6 0 # Per bank write bursts 97system.physmem.perBankWrBursts::7 0 # Per bank write bursts 98system.physmem.perBankWrBursts::8 0 # Per bank write bursts 99system.physmem.perBankWrBursts::9 0 # Per bank write bursts 100system.physmem.perBankWrBursts::10 0 # Per bank write bursts 101system.physmem.perBankWrBursts::11 0 # Per bank write bursts 102system.physmem.perBankWrBursts::12 0 # Per bank write bursts 103system.physmem.perBankWrBursts::13 0 # Per bank write bursts 104system.physmem.perBankWrBursts::14 0 # Per bank write bursts 105system.physmem.perBankWrBursts::15 0 # Per bank write bursts 106system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 107system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 90system.physmem.perBankWrBursts::0 0 # Per bank write bursts 91system.physmem.perBankWrBursts::1 0 # Per bank write bursts 92system.physmem.perBankWrBursts::2 0 # Per bank write bursts 93system.physmem.perBankWrBursts::3 0 # Per bank write bursts 94system.physmem.perBankWrBursts::4 0 # Per bank write bursts 95system.physmem.perBankWrBursts::5 0 # Per bank write bursts 96system.physmem.perBankWrBursts::6 0 # Per bank write bursts 97system.physmem.perBankWrBursts::7 0 # Per bank write bursts 98system.physmem.perBankWrBursts::8 0 # Per bank write bursts 99system.physmem.perBankWrBursts::9 0 # Per bank write bursts 100system.physmem.perBankWrBursts::10 0 # Per bank write bursts 101system.physmem.perBankWrBursts::11 0 # Per bank write bursts 102system.physmem.perBankWrBursts::12 0 # Per bank write bursts 103system.physmem.perBankWrBursts::13 0 # Per bank write bursts 104system.physmem.perBankWrBursts::14 0 # Per bank write bursts 105system.physmem.perBankWrBursts::15 0 # Per bank write bursts 106system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 107system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
108system.physmem.totGap 110942500 # Total gap between requests | 108system.physmem.totGap 105611000 # Total gap between requests |
109system.physmem.readPktSize::0 0 # Read request sizes (log2) 110system.physmem.readPktSize::1 0 # Read request sizes (log2) 111system.physmem.readPktSize::2 0 # Read request sizes (log2) 112system.physmem.readPktSize::3 0 # Read request sizes (log2) 113system.physmem.readPktSize::4 0 # Read request sizes (log2) 114system.physmem.readPktSize::5 0 # Read request sizes (log2) | 109system.physmem.readPktSize::0 0 # Read request sizes (log2) 110system.physmem.readPktSize::1 0 # Read request sizes (log2) 111system.physmem.readPktSize::2 0 # Read request sizes (log2) 112system.physmem.readPktSize::3 0 # Read request sizes (log2) 113system.physmem.readPktSize::4 0 # Read request sizes (log2) 114system.physmem.readPktSize::5 0 # Read request sizes (log2) |
115system.physmem.readPktSize::6 660 # Read request sizes (log2) | 115system.physmem.readPktSize::6 669 # Read request sizes (log2) |
116system.physmem.writePktSize::0 0 # Write request sizes (log2) 117system.physmem.writePktSize::1 0 # Write request sizes (log2) 118system.physmem.writePktSize::2 0 # Write request sizes (log2) 119system.physmem.writePktSize::3 0 # Write request sizes (log2) 120system.physmem.writePktSize::4 0 # Write request sizes (log2) 121system.physmem.writePktSize::5 0 # Write request sizes (log2) 122system.physmem.writePktSize::6 0 # Write request sizes (log2) 123system.physmem.rdQLenPdf::0 400 # What read queue length does an incoming req see | 116system.physmem.writePktSize::0 0 # Write request sizes (log2) 117system.physmem.writePktSize::1 0 # Write request sizes (log2) 118system.physmem.writePktSize::2 0 # Write request sizes (log2) 119system.physmem.writePktSize::3 0 # Write request sizes (log2) 120system.physmem.writePktSize::4 0 # Write request sizes (log2) 121system.physmem.writePktSize::5 0 # Write request sizes (log2) 122system.physmem.writePktSize::6 0 # Write request sizes (log2) 123system.physmem.rdQLenPdf::0 400 # What read queue length does an incoming req see |
124system.physmem.rdQLenPdf::1 194 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see | 124system.physmem.rdQLenPdf::1 193 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see |
129system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see --- 74 unchanged lines hidden (view full) --- 211system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 129system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see --- 74 unchanged lines hidden (view full) --- 211system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
219system.physmem.bytesPerActivate::samples 148 # Bytes accessed per row activation 220system.physmem.bytesPerActivate::mean 274.594595 # Bytes accessed per row activation 221system.physmem.bytesPerActivate::gmean 184.768834 # Bytes accessed per row activation 222system.physmem.bytesPerActivate::stdev 255.591879 # Bytes accessed per row activation 223system.physmem.bytesPerActivate::0-127 47 31.76% 31.76% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::128-255 39 26.35% 58.11% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::256-383 23 15.54% 73.65% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::384-511 12 8.11% 81.76% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::512-639 10 6.76% 88.51% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::640-767 5 3.38% 91.89% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::768-895 5 3.38% 95.27% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::896-1023 1 0.68% 95.95% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::1024-1151 6 4.05% 100.00% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::total 148 # Bytes accessed per row activation 233system.physmem.totQLat 5904750 # Total ticks spent queuing 234system.physmem.totMemAccLat 18279750 # Total ticks spent from burst creation until serviced by the DRAM 235system.physmem.totBusLat 3300000 # Total ticks spent in databus transfers 236system.physmem.avgQLat 8946.59 # Average queueing delay per DRAM burst | 219system.physmem.bytesPerActivate::samples 144 # Bytes accessed per row activation 220system.physmem.bytesPerActivate::mean 278.222222 # Bytes accessed per row activation 221system.physmem.bytesPerActivate::gmean 188.203281 # Bytes accessed per row activation 222system.physmem.bytesPerActivate::stdev 257.152031 # Bytes accessed per row activation 223system.physmem.bytesPerActivate::0-127 43 29.86% 29.86% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::128-255 39 27.08% 56.94% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::256-383 24 16.67% 73.61% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::384-511 13 9.03% 82.64% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::512-639 6 4.17% 86.81% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::640-767 6 4.17% 90.97% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::768-895 6 4.17% 95.14% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::896-1023 2 1.39% 96.53% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::1024-1151 5 3.47% 100.00% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::total 144 # Bytes accessed per row activation 233system.physmem.totQLat 6117250 # Total ticks spent queuing 234system.physmem.totMemAccLat 18661000 # Total ticks spent from burst creation until serviced by the DRAM 235system.physmem.totBusLat 3345000 # Total ticks spent in databus transfers 236system.physmem.avgQLat 9143.87 # Average queueing delay per DRAM burst |
237system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 237system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
238system.physmem.avgMemAccLat 27696.59 # Average memory access latency per DRAM burst 239system.physmem.avgRdBW 380.64 # Average DRAM read bandwidth in MiByte/s | 238system.physmem.avgMemAccLat 27893.87 # Average memory access latency per DRAM burst 239system.physmem.avgRdBW 405.30 # Average DRAM read bandwidth in MiByte/s |
240system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 240system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
241system.physmem.avgRdBWSys 380.64 # Average system read bandwidth in MiByte/s | 241system.physmem.avgRdBWSys 405.30 # Average system read bandwidth in MiByte/s |
242system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 243system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 242system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 243system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
244system.physmem.busUtil 2.97 # Data bus utilization in percentage 245system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads | 244system.physmem.busUtil 3.17 # Data bus utilization in percentage 245system.physmem.busUtilRead 3.17 # Data bus utilization in percentage for reads |
246system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 246system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
247system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing | 247system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing |
248system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 248system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
249system.physmem.readRowHits 505 # Number of row buffer hits during reads | 249system.physmem.readRowHits 514 # Number of row buffer hits during reads |
250system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 250system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
251system.physmem.readRowHitRate 76.52 # Row buffer hit rate for reads | 251system.physmem.readRowHitRate 76.83 # Row buffer hit rate for reads |
252system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 252system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
253system.physmem.avgGap 168094.70 # Average gap between requests 254system.physmem.pageHitRate 76.52 # Row buffer hit rate, read and write combined 255system.physmem.memoryStateTime::IDLE 48408000 # Time in different power states 256system.physmem.memoryStateTime::REF 3640000 # Time in different power states | 253system.physmem.avgGap 157863.98 # Average gap between requests 254system.physmem.pageHitRate 76.83 # Row buffer hit rate, read and write combined 255system.physmem.memoryStateTime::IDLE 46009250 # Time in different power states 256system.physmem.memoryStateTime::REF 3380000 # Time in different power states |
257system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 257system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
258system.physmem.memoryStateTime::ACT 57233250 # Time in different power states | 258system.physmem.memoryStateTime::ACT 52645250 # Time in different power states |
259system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 259system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
260system.membus.throughput 380064972 # Throughput (bytes/s) 261system.membus.trans_dist::ReadReq 529 # Transaction distribution 262system.membus.trans_dist::ReadResp 528 # Transaction distribution 263system.membus.trans_dist::UpgradeReq 287 # Transaction distribution 264system.membus.trans_dist::UpgradeResp 77 # Transaction distribution 265system.membus.trans_dist::ReadExReq 162 # Transaction distribution | 260system.membus.throughput 404699022 # Throughput (bytes/s) 261system.membus.trans_dist::ReadReq 538 # Transaction distribution 262system.membus.trans_dist::ReadResp 537 # Transaction distribution 263system.membus.trans_dist::UpgradeReq 272 # Transaction distribution 264system.membus.trans_dist::UpgradeResp 78 # Transaction distribution 265system.membus.trans_dist::ReadExReq 182 # Transaction distribution |
266system.membus.trans_dist::ReadExResp 131 # Transaction distribution | 266system.membus.trans_dist::ReadExResp 131 # Transaction distribution |
267system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes) 268system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes) 269system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42176 # Cumulative packet size per connected master and slave (bytes) 270system.membus.tot_pkt_size::total 42176 # Cumulative packet size per connected master and slave (bytes) 271system.membus.data_through_bus 42176 # Total data (bytes) | 267system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1738 # Packet count per connected master and slave (bytes) 268system.membus.pkt_count::total 1738 # Packet count per connected master and slave (bytes) 269system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42752 # Cumulative packet size per connected master and slave (bytes) 270system.membus.tot_pkt_size::total 42752 # Cumulative packet size per connected master and slave (bytes) 271system.membus.data_through_bus 42752 # Total data (bytes) |
272system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 272system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
273system.membus.reqLayer0.occupancy 921500 # Layer occupancy (ticks) 274system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) 275system.membus.respLayer1.occupancy 6294424 # Layer occupancy (ticks) 276system.membus.respLayer1.utilization 5.7 # Layer utilization (%) | 273system.membus.reqLayer0.occupancy 937500 # Layer occupancy (ticks) 274system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) 275system.membus.respLayer1.occupancy 6389922 # Layer occupancy (ticks) 276system.membus.respLayer1.utilization 6.0 # Layer utilization (%) |
277system.cpu_clk_domain.clock 500 # Clock period in ticks 278system.l2c.tags.replacements 0 # number of replacements | 277system.cpu_clk_domain.clock 500 # Clock period in ticks 278system.l2c.tags.replacements 0 # number of replacements |
279system.l2c.tags.tagsinuse 416.952741 # Cycle average of tags in use 280system.l2c.tags.total_refs 1442 # Total number of references to valid blocks. 281system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks. 282system.l2c.tags.avg_refs 2.741445 # Average number of references to valid blocks. | 279system.l2c.tags.tagsinuse 424.251527 # Cycle average of tags in use 280system.l2c.tags.total_refs 1658 # Total number of references to valid blocks. 281system.l2c.tags.sampled_refs 535 # Sample count of references to valid blocks. 282system.l2c.tags.avg_refs 3.099065 # Average number of references to valid blocks. |
283system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 283system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
284system.l2c.tags.occ_blocks::writebacks 0.799591 # Average occupied blocks per requestor 285system.l2c.tags.occ_blocks::cpu0.inst 285.006820 # Average occupied blocks per requestor 286system.l2c.tags.occ_blocks::cpu0.data 58.406933 # Average occupied blocks per requestor 287system.l2c.tags.occ_blocks::cpu1.inst 8.706163 # Average occupied blocks per requestor 288system.l2c.tags.occ_blocks::cpu1.data 0.731992 # Average occupied blocks per requestor 289system.l2c.tags.occ_blocks::cpu2.inst 54.635838 # Average occupied blocks per requestor 290system.l2c.tags.occ_blocks::cpu2.data 5.407858 # Average occupied blocks per requestor 291system.l2c.tags.occ_blocks::cpu3.inst 2.562888 # Average occupied blocks per requestor 292system.l2c.tags.occ_blocks::cpu3.data 0.694658 # Average occupied blocks per requestor | 284system.l2c.tags.occ_blocks::writebacks 0.793481 # Average occupied blocks per requestor 285system.l2c.tags.occ_blocks::cpu0.inst 289.756161 # Average occupied blocks per requestor 286system.l2c.tags.occ_blocks::cpu0.data 58.232417 # Average occupied blocks per requestor 287system.l2c.tags.occ_blocks::cpu1.inst 9.250622 # Average occupied blocks per requestor 288system.l2c.tags.occ_blocks::cpu1.data 0.723175 # Average occupied blocks per requestor 289system.l2c.tags.occ_blocks::cpu2.inst 57.184063 # Average occupied blocks per requestor 290system.l2c.tags.occ_blocks::cpu2.data 5.359898 # Average occupied blocks per requestor 291system.l2c.tags.occ_blocks::cpu3.inst 2.266069 # Average occupied blocks per requestor 292system.l2c.tags.occ_blocks::cpu3.data 0.685642 # Average occupied blocks per requestor |
293system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy | 293system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy |
294system.l2c.tags.occ_percent::cpu0.inst 0.004349 # Average percentage of cache occupancy 295system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy 296system.l2c.tags.occ_percent::cpu1.inst 0.000133 # Average percentage of cache occupancy | 294system.l2c.tags.occ_percent::cpu0.inst 0.004421 # Average percentage of cache occupancy 295system.l2c.tags.occ_percent::cpu0.data 0.000889 # Average percentage of cache occupancy 296system.l2c.tags.occ_percent::cpu1.inst 0.000141 # Average percentage of cache occupancy |
297system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy | 297system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy |
298system.l2c.tags.occ_percent::cpu2.inst 0.000834 # Average percentage of cache occupancy 299system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy 300system.l2c.tags.occ_percent::cpu3.inst 0.000039 # Average percentage of cache occupancy 301system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy 302system.l2c.tags.occ_percent::total 0.006362 # Average percentage of cache occupancy 303system.l2c.tags.occ_task_id_blocks::1024 526 # Occupied blocks per task id 304system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 305system.l2c.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id 306system.l2c.tags.age_task_id_blocks_1024::2 179 # Occupied blocks per task id 307system.l2c.tags.occ_task_id_percent::1024 0.008026 # Percentage of cache occupancy per task id 308system.l2c.tags.tag_accesses 18236 # Number of tag accesses 309system.l2c.tags.data_accesses 18236 # Number of data accesses 310system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits | 298system.l2c.tags.occ_percent::cpu2.inst 0.000873 # Average percentage of cache occupancy 299system.l2c.tags.occ_percent::cpu2.data 0.000082 # Average percentage of cache occupancy 300system.l2c.tags.occ_percent::cpu3.inst 0.000035 # Average percentage of cache occupancy 301system.l2c.tags.occ_percent::cpu3.data 0.000010 # Average percentage of cache occupancy 302system.l2c.tags.occ_percent::total 0.006474 # Average percentage of cache occupancy 303system.l2c.tags.occ_task_id_blocks::1024 535 # Occupied blocks per task id 304system.l2c.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 305system.l2c.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id 306system.l2c.tags.age_task_id_blocks_1024::2 117 # Occupied blocks per task id 307system.l2c.tags.occ_task_id_percent::1024 0.008163 # Percentage of cache occupancy per task id 308system.l2c.tags.tag_accesses 20037 # Number of tag accesses 309system.l2c.tags.data_accesses 20037 # Number of data accesses 310system.l2c.ReadReq_hits::cpu0.inst 250 # number of ReadReq hits |
311system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits | 311system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits |
312system.l2c.ReadReq_hits::cpu1.inst 409 # number of ReadReq hits | 312system.l2c.ReadReq_hits::cpu1.inst 481 # number of ReadReq hits |
313system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits | 313system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits |
314system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits | 314system.l2c.ReadReq_hits::cpu2.inst 409 # number of ReadReq hits |
315system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits | 315system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits |
316system.l2c.ReadReq_hits::cpu3.inst 423 # number of ReadReq hits | 316system.l2c.ReadReq_hits::cpu3.inst 486 # number of ReadReq hits |
317system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits | 317system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits |
318system.l2c.ReadReq_hits::total 1442 # number of ReadReq hits | 318system.l2c.ReadReq_hits::total 1658 # number of ReadReq hits |
319system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 320system.l2c.Writeback_hits::total 1 # number of Writeback hits 321system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits 322system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits | 319system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 320system.l2c.Writeback_hits::total 1 # number of Writeback hits 321system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits 322system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits |
323system.l2c.demand_hits::cpu0.inst 229 # number of demand (read+write) hits | 323system.l2c.demand_hits::cpu0.inst 250 # number of demand (read+write) hits |
324system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits | 324system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits |
325system.l2c.demand_hits::cpu1.inst 409 # number of demand (read+write) hits | 325system.l2c.demand_hits::cpu1.inst 481 # number of demand (read+write) hits |
326system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits | 326system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits |
327system.l2c.demand_hits::cpu2.inst 349 # number of demand (read+write) hits | 327system.l2c.demand_hits::cpu2.inst 409 # number of demand (read+write) hits |
328system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits | 328system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits |
329system.l2c.demand_hits::cpu3.inst 423 # number of demand (read+write) hits | 329system.l2c.demand_hits::cpu3.inst 486 # number of demand (read+write) hits |
330system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits | 330system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits |
331system.l2c.demand_hits::total 1442 # number of demand (read+write) hits 332system.l2c.overall_hits::cpu0.inst 229 # number of overall hits | 331system.l2c.demand_hits::total 1658 # number of demand (read+write) hits 332system.l2c.overall_hits::cpu0.inst 250 # number of overall hits |
333system.l2c.overall_hits::cpu0.data 5 # number of overall hits | 333system.l2c.overall_hits::cpu0.data 5 # number of overall hits |
334system.l2c.overall_hits::cpu1.inst 409 # number of overall hits | 334system.l2c.overall_hits::cpu1.inst 481 # number of overall hits |
335system.l2c.overall_hits::cpu1.data 11 # number of overall hits | 335system.l2c.overall_hits::cpu1.data 11 # number of overall hits |
336system.l2c.overall_hits::cpu2.inst 349 # number of overall hits | 336system.l2c.overall_hits::cpu2.inst 409 # number of overall hits |
337system.l2c.overall_hits::cpu2.data 5 # number of overall hits | 337system.l2c.overall_hits::cpu2.data 5 # number of overall hits |
338system.l2c.overall_hits::cpu3.inst 423 # number of overall hits | 338system.l2c.overall_hits::cpu3.inst 486 # number of overall hits |
339system.l2c.overall_hits::cpu3.data 11 # number of overall hits | 339system.l2c.overall_hits::cpu3.data 11 # number of overall hits |
340system.l2c.overall_hits::total 1442 # number of overall hits 341system.l2c.ReadReq_misses::cpu0.inst 359 # number of ReadReq misses | 340system.l2c.overall_hits::total 1658 # number of overall hits 341system.l2c.ReadReq_misses::cpu0.inst 363 # number of ReadReq misses |
342system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses | 342system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses |
343system.l2c.ReadReq_misses::cpu1.inst 19 # number of ReadReq misses | 343system.l2c.ReadReq_misses::cpu1.inst 16 # number of ReadReq misses |
344system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses | 344system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses |
345system.l2c.ReadReq_misses::cpu2.inst 75 # number of ReadReq misses | 345system.l2c.ReadReq_misses::cpu2.inst 81 # number of ReadReq misses |
346system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses 347system.l2c.ReadReq_misses::cpu3.inst 7 # number of ReadReq misses 348system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses | 346system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses 347system.l2c.ReadReq_misses::cpu3.inst 7 # number of ReadReq misses 348system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses |
349system.l2c.ReadReq_misses::total 543 # number of ReadReq misses 350system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses 351system.l2c.UpgradeReq_misses::cpu1.data 21 # number of UpgradeReq misses 352system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses 353system.l2c.UpgradeReq_misses::cpu3.data 17 # number of UpgradeReq misses 354system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses | 349system.l2c.ReadReq_misses::total 550 # number of ReadReq misses 350system.l2c.UpgradeReq_misses::cpu0.data 23 # number of UpgradeReq misses 351system.l2c.UpgradeReq_misses::cpu1.data 17 # number of UpgradeReq misses 352system.l2c.UpgradeReq_misses::cpu2.data 18 # number of UpgradeReq misses 353system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses 354system.l2c.UpgradeReq_misses::total 78 # number of UpgradeReq misses |
355system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses 356system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses 357system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses 358system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 359system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses | 355system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses 356system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses 357system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses 358system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 359system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses |
360system.l2c.demand_misses::cpu0.inst 359 # number of demand (read+write) misses | 360system.l2c.demand_misses::cpu0.inst 363 # number of demand (read+write) misses |
361system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses | 361system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses |
362system.l2c.demand_misses::cpu1.inst 19 # number of demand (read+write) misses | 362system.l2c.demand_misses::cpu1.inst 16 # number of demand (read+write) misses |
363system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses | 363system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses |
364system.l2c.demand_misses::cpu2.inst 75 # number of demand (read+write) misses | 364system.l2c.demand_misses::cpu2.inst 81 # number of demand (read+write) misses |
365system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses 366system.l2c.demand_misses::cpu3.inst 7 # number of demand (read+write) misses 367system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses | 365system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses 366system.l2c.demand_misses::cpu3.inst 7 # number of demand (read+write) misses 367system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses |
368system.l2c.demand_misses::total 674 # number of demand (read+write) misses 369system.l2c.overall_misses::cpu0.inst 359 # number of overall misses | 368system.l2c.demand_misses::total 681 # number of demand (read+write) misses 369system.l2c.overall_misses::cpu0.inst 363 # number of overall misses |
370system.l2c.overall_misses::cpu0.data 168 # number of overall misses | 370system.l2c.overall_misses::cpu0.data 168 # number of overall misses |
371system.l2c.overall_misses::cpu1.inst 19 # number of overall misses | 371system.l2c.overall_misses::cpu1.inst 16 # number of overall misses |
372system.l2c.overall_misses::cpu1.data 13 # number of overall misses | 372system.l2c.overall_misses::cpu1.data 13 # number of overall misses |
373system.l2c.overall_misses::cpu2.inst 75 # number of overall misses | 373system.l2c.overall_misses::cpu2.inst 81 # number of overall misses |
374system.l2c.overall_misses::cpu2.data 20 # number of overall misses 375system.l2c.overall_misses::cpu3.inst 7 # number of overall misses 376system.l2c.overall_misses::cpu3.data 13 # number of overall misses | 374system.l2c.overall_misses::cpu2.data 20 # number of overall misses 375system.l2c.overall_misses::cpu3.inst 7 # number of overall misses 376system.l2c.overall_misses::cpu3.data 13 # number of overall misses |
377system.l2c.overall_misses::total 674 # number of overall misses 378system.l2c.ReadReq_miss_latency::cpu0.inst 24479500 # number of ReadReq miss cycles 379system.l2c.ReadReq_miss_latency::cpu0.data 5371500 # number of ReadReq miss cycles 380system.l2c.ReadReq_miss_latency::cpu1.inst 1394250 # number of ReadReq miss cycles 381system.l2c.ReadReq_miss_latency::cpu1.data 74500 # number of ReadReq miss cycles 382system.l2c.ReadReq_miss_latency::cpu2.inst 5296000 # number of ReadReq miss cycles 383system.l2c.ReadReq_miss_latency::cpu2.data 494750 # number of ReadReq miss cycles 384system.l2c.ReadReq_miss_latency::cpu3.inst 438500 # number of ReadReq miss cycles 385system.l2c.ReadReq_miss_latency::cpu3.data 74500 # number of ReadReq miss cycles 386system.l2c.ReadReq_miss_latency::total 37623500 # number of ReadReq miss cycles 387system.l2c.ReadExReq_miss_latency::cpu0.data 7056000 # number of ReadExReq miss cycles 388system.l2c.ReadExReq_miss_latency::cpu1.data 894000 # number of ReadExReq miss cycles 389system.l2c.ReadExReq_miss_latency::cpu2.data 1355500 # number of ReadExReq miss cycles 390system.l2c.ReadExReq_miss_latency::cpu3.data 863500 # number of ReadExReq miss cycles 391system.l2c.ReadExReq_miss_latency::total 10169000 # number of ReadExReq miss cycles 392system.l2c.demand_miss_latency::cpu0.inst 24479500 # number of demand (read+write) miss cycles 393system.l2c.demand_miss_latency::cpu0.data 12427500 # number of demand (read+write) miss cycles 394system.l2c.demand_miss_latency::cpu1.inst 1394250 # number of demand (read+write) miss cycles 395system.l2c.demand_miss_latency::cpu1.data 968500 # number of demand (read+write) miss cycles 396system.l2c.demand_miss_latency::cpu2.inst 5296000 # number of demand (read+write) miss cycles 397system.l2c.demand_miss_latency::cpu2.data 1850250 # number of demand (read+write) miss cycles 398system.l2c.demand_miss_latency::cpu3.inst 438500 # number of demand (read+write) miss cycles 399system.l2c.demand_miss_latency::cpu3.data 938000 # number of demand (read+write) miss cycles 400system.l2c.demand_miss_latency::total 47792500 # number of demand (read+write) miss cycles 401system.l2c.overall_miss_latency::cpu0.inst 24479500 # number of overall miss cycles 402system.l2c.overall_miss_latency::cpu0.data 12427500 # number of overall miss cycles 403system.l2c.overall_miss_latency::cpu1.inst 1394250 # number of overall miss cycles 404system.l2c.overall_miss_latency::cpu1.data 968500 # number of overall miss cycles 405system.l2c.overall_miss_latency::cpu2.inst 5296000 # number of overall miss cycles 406system.l2c.overall_miss_latency::cpu2.data 1850250 # number of overall miss cycles 407system.l2c.overall_miss_latency::cpu3.inst 438500 # number of overall miss cycles 408system.l2c.overall_miss_latency::cpu3.data 938000 # number of overall miss cycles 409system.l2c.overall_miss_latency::total 47792500 # number of overall miss cycles 410system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses) | 377system.l2c.overall_misses::total 681 # number of overall misses 378system.l2c.ReadReq_miss_latency::cpu0.inst 25055500 # number of ReadReq miss cycles 379system.l2c.ReadReq_miss_latency::cpu0.data 5652750 # number of ReadReq miss cycles 380system.l2c.ReadReq_miss_latency::cpu1.inst 1295250 # number of ReadReq miss cycles 381system.l2c.ReadReq_miss_latency::cpu1.data 75000 # number of ReadReq miss cycles 382system.l2c.ReadReq_miss_latency::cpu2.inst 5783750 # number of ReadReq miss cycles 383system.l2c.ReadReq_miss_latency::cpu2.data 523250 # number of ReadReq miss cycles 384system.l2c.ReadReq_miss_latency::cpu3.inst 458000 # number of ReadReq miss cycles 385system.l2c.ReadReq_miss_latency::cpu3.data 75000 # number of ReadReq miss cycles 386system.l2c.ReadReq_miss_latency::total 38918500 # number of ReadReq miss cycles 387system.l2c.ReadExReq_miss_latency::cpu0.data 6921000 # number of ReadExReq miss cycles 388system.l2c.ReadExReq_miss_latency::cpu1.data 852750 # number of ReadExReq miss cycles 389system.l2c.ReadExReq_miss_latency::cpu2.data 1047250 # number of ReadExReq miss cycles 390system.l2c.ReadExReq_miss_latency::cpu3.data 836500 # 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411system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) | 411system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) |
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413system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) | 413system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) |
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415system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) | 415system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) |
416system.l2c.ReadReq_accesses::cpu3.inst 430 # number of ReadReq accesses(hits+misses) | 416system.l2c.ReadReq_accesses::cpu3.inst 493 # number of ReadReq accesses(hits+misses) |
417system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) | 417system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) |
418system.l2c.ReadReq_accesses::total 1985 # number of ReadReq accesses(hits+misses) | 418system.l2c.ReadReq_accesses::total 2208 # number of ReadReq accesses(hits+misses) |
419system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 420system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) | 419system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 420system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) |
421system.l2c.UpgradeReq_accesses::cpu0.data 25 # number of UpgradeReq accesses(hits+misses) 422system.l2c.UpgradeReq_accesses::cpu1.data 21 # number of UpgradeReq accesses(hits+misses) 423system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) 424system.l2c.UpgradeReq_accesses::cpu3.data 17 # number of UpgradeReq accesses(hits+misses) 425system.l2c.UpgradeReq_accesses::total 80 # number of UpgradeReq accesses(hits+misses) | 421system.l2c.UpgradeReq_accesses::cpu0.data 26 # number of UpgradeReq accesses(hits+misses) 422system.l2c.UpgradeReq_accesses::cpu1.data 17 # number of UpgradeReq accesses(hits+misses) 423system.l2c.UpgradeReq_accesses::cpu2.data 18 # number of UpgradeReq accesses(hits+misses) 424system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses) 425system.l2c.UpgradeReq_accesses::total 81 # number of UpgradeReq accesses(hits+misses) |
426system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) 427system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses) 428system.l2c.ReadExReq_accesses::cpu2.data 13 # number of ReadExReq accesses(hits+misses) 429system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 430system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) | 426system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) 427system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses) 428system.l2c.ReadExReq_accesses::cpu2.data 13 # number of ReadExReq accesses(hits+misses) 429system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 430system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) |
431system.l2c.demand_accesses::cpu0.inst 588 # number of demand (read+write) accesses | 431system.l2c.demand_accesses::cpu0.inst 613 # number of demand (read+write) accesses |
432system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses | 432system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses |
433system.l2c.demand_accesses::cpu1.inst 428 # number of demand (read+write) accesses | 433system.l2c.demand_accesses::cpu1.inst 497 # number of demand (read+write) accesses |
434system.l2c.demand_accesses::cpu1.data 24 # number of demand (read+write) accesses | 434system.l2c.demand_accesses::cpu1.data 24 # number of demand (read+write) accesses |
435system.l2c.demand_accesses::cpu2.inst 424 # number of demand (read+write) accesses | 435system.l2c.demand_accesses::cpu2.inst 490 # number of demand (read+write) accesses |
436system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses | 436system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses |
437system.l2c.demand_accesses::cpu3.inst 430 # number of demand (read+write) accesses | 437system.l2c.demand_accesses::cpu3.inst 493 # number of demand (read+write) accesses |
438system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses | 438system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses |
439system.l2c.demand_accesses::total 2116 # number of demand (read+write) accesses 440system.l2c.overall_accesses::cpu0.inst 588 # number of overall (read+write) accesses | 439system.l2c.demand_accesses::total 2339 # number of demand (read+write) accesses 440system.l2c.overall_accesses::cpu0.inst 613 # number of overall (read+write) accesses |
441system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses | 441system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses |
442system.l2c.overall_accesses::cpu1.inst 428 # number of overall (read+write) accesses | 442system.l2c.overall_accesses::cpu1.inst 497 # number of overall (read+write) accesses |
443system.l2c.overall_accesses::cpu1.data 24 # number of overall (read+write) accesses | 443system.l2c.overall_accesses::cpu1.data 24 # number of overall (read+write) accesses |
444system.l2c.overall_accesses::cpu2.inst 424 # number of overall (read+write) accesses | 444system.l2c.overall_accesses::cpu2.inst 490 # number of overall (read+write) accesses |
445system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses | 445system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses |
446system.l2c.overall_accesses::cpu3.inst 430 # number of overall (read+write) accesses | 446system.l2c.overall_accesses::cpu3.inst 493 # number of overall (read+write) accesses |
447system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses | 447system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses |
448system.l2c.overall_accesses::total 2116 # number of overall (read+write) accesses 449system.l2c.ReadReq_miss_rate::cpu0.inst 0.610544 # miss rate for ReadReq accesses | 448system.l2c.overall_accesses::total 2339 # number of overall (read+write) accesses 449system.l2c.ReadReq_miss_rate::cpu0.inst 0.592170 # miss rate for ReadReq accesses |
450system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses | 450system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses |
451system.l2c.ReadReq_miss_rate::cpu1.inst 0.044393 # miss rate for ReadReq accesses | 451system.l2c.ReadReq_miss_rate::cpu1.inst 0.032193 # miss rate for ReadReq accesses |
452system.l2c.ReadReq_miss_rate::cpu1.data 0.083333 # miss rate for ReadReq accesses | 452system.l2c.ReadReq_miss_rate::cpu1.data 0.083333 # miss rate for ReadReq accesses |
453system.l2c.ReadReq_miss_rate::cpu2.inst 0.176887 # miss rate for ReadReq accesses | 453system.l2c.ReadReq_miss_rate::cpu2.inst 0.165306 # miss rate for ReadReq accesses |
454system.l2c.ReadReq_miss_rate::cpu2.data 0.583333 # miss rate for ReadReq accesses | 454system.l2c.ReadReq_miss_rate::cpu2.data 0.583333 # miss rate for ReadReq accesses |
455system.l2c.ReadReq_miss_rate::cpu3.inst 0.016279 # miss rate for ReadReq accesses | 455system.l2c.ReadReq_miss_rate::cpu3.inst 0.014199 # miss rate for ReadReq accesses |
456system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses | 456system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses |
457system.l2c.ReadReq_miss_rate::total 0.273552 # miss rate for ReadReq accesses 458system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses | 457system.l2c.ReadReq_miss_rate::total 0.249094 # miss rate for ReadReq accesses 458system.l2c.UpgradeReq_miss_rate::cpu0.data 0.884615 # miss rate for UpgradeReq accesses |
459system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 460system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 461system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses | 459system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 460system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 461system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses |
462system.l2c.UpgradeReq_miss_rate::total 0.962500 # miss rate for UpgradeReq accesses | 462system.l2c.UpgradeReq_miss_rate::total 0.962963 # miss rate for UpgradeReq accesses |
463system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 464system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 465system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 466system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 467system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses | 463system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 464system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 465system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 466system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 467system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
468system.l2c.demand_miss_rate::cpu0.inst 0.610544 # miss rate for demand accesses | 468system.l2c.demand_miss_rate::cpu0.inst 0.592170 # miss rate for demand accesses |
469system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses | 469system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses |
470system.l2c.demand_miss_rate::cpu1.inst 0.044393 # miss rate for demand accesses | 470system.l2c.demand_miss_rate::cpu1.inst 0.032193 # miss rate for demand accesses |
471system.l2c.demand_miss_rate::cpu1.data 0.541667 # miss rate for demand accesses | 471system.l2c.demand_miss_rate::cpu1.data 0.541667 # miss rate for demand accesses |
472system.l2c.demand_miss_rate::cpu2.inst 0.176887 # miss rate for demand accesses | 472system.l2c.demand_miss_rate::cpu2.inst 0.165306 # miss rate for demand accesses |
473system.l2c.demand_miss_rate::cpu2.data 0.800000 # miss rate for demand accesses | 473system.l2c.demand_miss_rate::cpu2.data 0.800000 # miss rate for demand accesses |
474system.l2c.demand_miss_rate::cpu3.inst 0.016279 # miss rate for demand accesses | 474system.l2c.demand_miss_rate::cpu3.inst 0.014199 # miss rate for demand accesses |
475system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses | 475system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses |
476system.l2c.demand_miss_rate::total 0.318526 # miss rate for demand accesses 477system.l2c.overall_miss_rate::cpu0.inst 0.610544 # miss rate for overall accesses | 476system.l2c.demand_miss_rate::total 0.291150 # miss rate for demand accesses 477system.l2c.overall_miss_rate::cpu0.inst 0.592170 # miss rate for overall accesses |
478system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses | 478system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses |
479system.l2c.overall_miss_rate::cpu1.inst 0.044393 # miss rate for overall accesses | 479system.l2c.overall_miss_rate::cpu1.inst 0.032193 # miss rate for overall accesses |
480system.l2c.overall_miss_rate::cpu1.data 0.541667 # miss rate for overall accesses | 480system.l2c.overall_miss_rate::cpu1.data 0.541667 # miss rate for overall accesses |
481system.l2c.overall_miss_rate::cpu2.inst 0.176887 # miss rate for overall accesses | 481system.l2c.overall_miss_rate::cpu2.inst 0.165306 # miss rate for overall accesses |
482system.l2c.overall_miss_rate::cpu2.data 0.800000 # miss rate for overall accesses | 482system.l2c.overall_miss_rate::cpu2.data 0.800000 # miss rate for overall accesses |
483system.l2c.overall_miss_rate::cpu3.inst 0.016279 # miss rate for overall accesses | 483system.l2c.overall_miss_rate::cpu3.inst 0.014199 # miss rate for overall accesses |
484system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses | 484system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses |
485system.l2c.overall_miss_rate::total 0.318526 # miss rate for overall accesses 486system.l2c.ReadReq_avg_miss_latency::cpu0.inst 68188.022284 # average ReadReq miss latency 487system.l2c.ReadReq_avg_miss_latency::cpu0.data 72587.837838 # average ReadReq miss latency 488system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73381.578947 # average ReadReq miss latency 489system.l2c.ReadReq_avg_miss_latency::cpu1.data 74500 # average ReadReq miss latency 490system.l2c.ReadReq_avg_miss_latency::cpu2.inst 70613.333333 # average ReadReq miss latency 491system.l2c.ReadReq_avg_miss_latency::cpu2.data 70678.571429 # average ReadReq miss latency 492system.l2c.ReadReq_avg_miss_latency::cpu3.inst 62642.857143 # average ReadReq miss latency 493system.l2c.ReadReq_avg_miss_latency::cpu3.data 74500 # average ReadReq miss latency 494system.l2c.ReadReq_avg_miss_latency::total 69288.213628 # average ReadReq miss latency 495system.l2c.ReadExReq_avg_miss_latency::cpu0.data 75063.829787 # average ReadExReq miss latency 496system.l2c.ReadExReq_avg_miss_latency::cpu1.data 74500 # average ReadExReq miss latency 497system.l2c.ReadExReq_avg_miss_latency::cpu2.data 104269.230769 # average ReadExReq miss latency 498system.l2c.ReadExReq_avg_miss_latency::cpu3.data 71958.333333 # average ReadExReq miss latency 499system.l2c.ReadExReq_avg_miss_latency::total 77625.954198 # average ReadExReq miss latency 500system.l2c.demand_avg_miss_latency::cpu0.inst 68188.022284 # average overall miss latency 501system.l2c.demand_avg_miss_latency::cpu0.data 73973.214286 # average overall miss latency 502system.l2c.demand_avg_miss_latency::cpu1.inst 73381.578947 # average overall miss latency 503system.l2c.demand_avg_miss_latency::cpu1.data 74500 # average overall miss latency 504system.l2c.demand_avg_miss_latency::cpu2.inst 70613.333333 # average overall miss latency 505system.l2c.demand_avg_miss_latency::cpu2.data 92512.500000 # average overall miss latency 506system.l2c.demand_avg_miss_latency::cpu3.inst 62642.857143 # average overall miss latency 507system.l2c.demand_avg_miss_latency::cpu3.data 72153.846154 # average overall miss latency 508system.l2c.demand_avg_miss_latency::total 70908.753709 # average overall miss latency 509system.l2c.overall_avg_miss_latency::cpu0.inst 68188.022284 # average overall miss latency 510system.l2c.overall_avg_miss_latency::cpu0.data 73973.214286 # average overall miss latency 511system.l2c.overall_avg_miss_latency::cpu1.inst 73381.578947 # average overall miss latency 512system.l2c.overall_avg_miss_latency::cpu1.data 74500 # average overall miss latency 513system.l2c.overall_avg_miss_latency::cpu2.inst 70613.333333 # average overall miss latency 514system.l2c.overall_avg_miss_latency::cpu2.data 92512.500000 # average overall miss latency 515system.l2c.overall_avg_miss_latency::cpu3.inst 62642.857143 # average overall miss latency 516system.l2c.overall_avg_miss_latency::cpu3.data 72153.846154 # average overall miss latency 517system.l2c.overall_avg_miss_latency::total 70908.753709 # average overall miss latency | 485system.l2c.overall_miss_rate::total 0.291150 # miss rate for overall accesses 486system.l2c.ReadReq_avg_miss_latency::cpu0.inst 69023.415978 # average ReadReq miss latency 487system.l2c.ReadReq_avg_miss_latency::cpu0.data 76388.513514 # average ReadReq miss latency 488system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80953.125000 # average ReadReq miss latency 489system.l2c.ReadReq_avg_miss_latency::cpu1.data 75000 # average ReadReq miss latency 490system.l2c.ReadReq_avg_miss_latency::cpu2.inst 71404.320988 # average ReadReq miss latency 491system.l2c.ReadReq_avg_miss_latency::cpu2.data 74750 # average ReadReq miss latency 492system.l2c.ReadReq_avg_miss_latency::cpu3.inst 65428.571429 # average ReadReq miss latency 493system.l2c.ReadReq_avg_miss_latency::cpu3.data 75000 # average ReadReq miss latency 494system.l2c.ReadReq_avg_miss_latency::total 70760.909091 # average ReadReq miss latency 495system.l2c.ReadExReq_avg_miss_latency::cpu0.data 73627.659574 # average ReadExReq miss latency 496system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71062.500000 # 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average overall miss latency 508system.l2c.demand_avg_miss_latency::total 71330.396476 # average overall miss latency 509system.l2c.overall_avg_miss_latency::cpu0.inst 69023.415978 # average overall miss latency 510system.l2c.overall_avg_miss_latency::cpu0.data 74843.750000 # average overall miss latency 511system.l2c.overall_avg_miss_latency::cpu1.inst 80953.125000 # average overall miss latency 512system.l2c.overall_avg_miss_latency::cpu1.data 71365.384615 # average overall miss latency 513system.l2c.overall_avg_miss_latency::cpu2.inst 71404.320988 # average overall miss latency 514system.l2c.overall_avg_miss_latency::cpu2.data 78525 # average overall miss latency 515system.l2c.overall_avg_miss_latency::cpu3.inst 65428.571429 # average overall miss latency 516system.l2c.overall_avg_miss_latency::cpu3.data 70115.384615 # average overall miss latency 517system.l2c.overall_avg_miss_latency::total 71330.396476 # average overall miss latency |
518system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 519system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 520system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 521system.l2c.blocked::no_targets 0 # number of cycles access was blocked 522system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 523system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 524system.l2c.fast_writes 0 # number of fast writes performed 525system.l2c.cache_copies 0 # number of cache copies performed | 518system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 519system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 520system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 521system.l2c.blocked::no_targets 0 # number of cycles access was blocked 522system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 523system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 524system.l2c.fast_writes 0 # number of fast writes performed 525system.l2c.cache_copies 0 # number of cache copies performed |
526system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits 527system.l2c.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits 528system.l2c.ReadReq_mshr_hits::cpu2.inst 3 # number of ReadReq MSHR hits | 526system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 527system.l2c.ReadReq_mshr_hits::cpu1.inst 4 # number of ReadReq MSHR hits 528system.l2c.ReadReq_mshr_hits::cpu2.inst 4 # number of ReadReq MSHR hits |
529system.l2c.ReadReq_mshr_hits::cpu3.inst 3 # number of ReadReq MSHR hits | 529system.l2c.ReadReq_mshr_hits::cpu3.inst 3 # number of ReadReq MSHR hits |
530system.l2c.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits 531system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits 532system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits 533system.l2c.demand_mshr_hits::cpu2.inst 3 # number of demand (read+write) MSHR hits | 530system.l2c.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits 531system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 532system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits 533system.l2c.demand_mshr_hits::cpu2.inst 4 # number of demand (read+write) MSHR hits |
534system.l2c.demand_mshr_hits::cpu3.inst 3 # number of demand (read+write) MSHR hits | 534system.l2c.demand_mshr_hits::cpu3.inst 3 # number of demand (read+write) MSHR hits |
535system.l2c.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits 536system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits 537system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits 538system.l2c.overall_mshr_hits::cpu2.inst 3 # number of overall MSHR hits | 535system.l2c.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits 536system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 537system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits 538system.l2c.overall_mshr_hits::cpu2.inst 4 # number of overall MSHR hits |
539system.l2c.overall_mshr_hits::cpu3.inst 3 # number of overall MSHR hits | 539system.l2c.overall_mshr_hits::cpu3.inst 3 # number of overall MSHR hits |
540system.l2c.overall_mshr_hits::total 14 # number of overall MSHR hits 541system.l2c.ReadReq_mshr_misses::cpu0.inst 357 # number of ReadReq MSHR misses | 540system.l2c.overall_mshr_hits::total 12 # number of overall MSHR hits 541system.l2c.ReadReq_mshr_misses::cpu0.inst 362 # number of ReadReq MSHR misses |
542system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses | 542system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses |
543system.l2c.ReadReq_mshr_misses::cpu1.inst 13 # number of ReadReq MSHR misses | 543system.l2c.ReadReq_mshr_misses::cpu1.inst 12 # number of ReadReq MSHR misses |
544system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses | 544system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses |
545system.l2c.ReadReq_mshr_misses::cpu2.inst 72 # number of ReadReq MSHR misses | 545system.l2c.ReadReq_mshr_misses::cpu2.inst 77 # number of ReadReq MSHR misses |
546system.l2c.ReadReq_mshr_misses::cpu2.data 7 # number of ReadReq MSHR misses 547system.l2c.ReadReq_mshr_misses::cpu3.inst 4 # number of ReadReq MSHR misses 548system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses | 546system.l2c.ReadReq_mshr_misses::cpu2.data 7 # number of ReadReq MSHR misses 547system.l2c.ReadReq_mshr_misses::cpu3.inst 4 # number of ReadReq MSHR misses 548system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses |
549system.l2c.ReadReq_mshr_misses::total 529 # number of ReadReq MSHR misses 550system.l2c.UpgradeReq_mshr_misses::cpu0.data 22 # number of UpgradeReq MSHR misses 551system.l2c.UpgradeReq_mshr_misses::cpu1.data 21 # number of UpgradeReq MSHR misses 552system.l2c.UpgradeReq_mshr_misses::cpu2.data 17 # number of UpgradeReq MSHR misses 553system.l2c.UpgradeReq_mshr_misses::cpu3.data 17 # number of UpgradeReq MSHR misses 554system.l2c.UpgradeReq_mshr_misses::total 77 # number of UpgradeReq MSHR misses | 549system.l2c.ReadReq_mshr_misses::total 538 # number of ReadReq MSHR misses 550system.l2c.UpgradeReq_mshr_misses::cpu0.data 23 # number of UpgradeReq MSHR misses 551system.l2c.UpgradeReq_mshr_misses::cpu1.data 17 # number of UpgradeReq MSHR misses 552system.l2c.UpgradeReq_mshr_misses::cpu2.data 18 # number of UpgradeReq MSHR misses 553system.l2c.UpgradeReq_mshr_misses::cpu3.data 20 # number of UpgradeReq MSHR misses 554system.l2c.UpgradeReq_mshr_misses::total 78 # number of UpgradeReq MSHR misses |
555system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses 556system.l2c.ReadExReq_mshr_misses::cpu1.data 12 # number of ReadExReq MSHR misses 557system.l2c.ReadExReq_mshr_misses::cpu2.data 13 # number of ReadExReq MSHR misses 558system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses 559system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses | 555system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses 556system.l2c.ReadExReq_mshr_misses::cpu1.data 12 # number of ReadExReq MSHR misses 557system.l2c.ReadExReq_mshr_misses::cpu2.data 13 # number of ReadExReq MSHR misses 558system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses 559system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses |
560system.l2c.demand_mshr_misses::cpu0.inst 357 # number of demand (read+write) MSHR misses | 560system.l2c.demand_mshr_misses::cpu0.inst 362 # number of demand (read+write) MSHR misses |
561system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses | 561system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses |
562system.l2c.demand_mshr_misses::cpu1.inst 13 # number of demand (read+write) MSHR misses | 562system.l2c.demand_mshr_misses::cpu1.inst 12 # number of demand (read+write) MSHR misses |
563system.l2c.demand_mshr_misses::cpu1.data 13 # number of demand (read+write) MSHR misses | 563system.l2c.demand_mshr_misses::cpu1.data 13 # number of demand (read+write) MSHR misses |
564system.l2c.demand_mshr_misses::cpu2.inst 72 # number of demand (read+write) MSHR misses | 564system.l2c.demand_mshr_misses::cpu2.inst 77 # number of demand (read+write) MSHR misses |
565system.l2c.demand_mshr_misses::cpu2.data 20 # number of demand (read+write) MSHR misses 566system.l2c.demand_mshr_misses::cpu3.inst 4 # number of demand (read+write) MSHR misses 567system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses | 565system.l2c.demand_mshr_misses::cpu2.data 20 # number of demand (read+write) MSHR misses 566system.l2c.demand_mshr_misses::cpu3.inst 4 # number of demand (read+write) MSHR misses 567system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses |
568system.l2c.demand_mshr_misses::total 660 # number of demand (read+write) MSHR misses 569system.l2c.overall_mshr_misses::cpu0.inst 357 # number of overall MSHR misses | 568system.l2c.demand_mshr_misses::total 669 # number of demand (read+write) MSHR misses 569system.l2c.overall_mshr_misses::cpu0.inst 362 # number of overall MSHR misses |
570system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses | 570system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses |
571system.l2c.overall_mshr_misses::cpu1.inst 13 # number of overall MSHR misses | 571system.l2c.overall_mshr_misses::cpu1.inst 12 # number of overall MSHR misses |
572system.l2c.overall_mshr_misses::cpu1.data 13 # number of overall MSHR misses | 572system.l2c.overall_mshr_misses::cpu1.data 13 # number of overall MSHR misses |
573system.l2c.overall_mshr_misses::cpu2.inst 72 # number of overall MSHR misses | 573system.l2c.overall_mshr_misses::cpu2.inst 77 # number of overall MSHR misses |
574system.l2c.overall_mshr_misses::cpu2.data 20 # number of overall MSHR misses 575system.l2c.overall_mshr_misses::cpu3.inst 4 # number of overall MSHR misses 576system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses | 574system.l2c.overall_mshr_misses::cpu2.data 20 # number of overall MSHR misses 575system.l2c.overall_mshr_misses::cpu3.inst 4 # number of overall MSHR misses 576system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses |
577system.l2c.overall_mshr_misses::total 660 # number of overall MSHR misses 578system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 19908750 # number of ReadReq MSHR miss cycles 579system.l2c.ReadReq_mshr_miss_latency::cpu0.data 4459500 # number of ReadReq MSHR miss cycles 580system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 858750 # number of ReadReq MSHR miss cycles | 577system.l2c.overall_mshr_misses::total 669 # number of overall MSHR misses 578system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 20468500 # number of ReadReq MSHR miss cycles 579system.l2c.ReadReq_mshr_miss_latency::cpu0.data 4740250 # number of ReadReq MSHR miss cycles 580system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 904000 # number of ReadReq MSHR miss cycles |
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586system.l2c.ReadReq_mshr_miss_latency::total 30254500 # number of ReadReq MSHR miss cycles 587system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 220022 # number of UpgradeReq MSHR miss cycles 588system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 218520 # number of UpgradeReq MSHR miss cycles 589system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 170017 # number of UpgradeReq MSHR miss cycles 590system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 170017 # number of UpgradeReq MSHR miss cycles 591system.l2c.UpgradeReq_mshr_miss_latency::total 778576 # number of UpgradeReq MSHR miss cycles 592system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5892000 # number of ReadExReq MSHR miss cycles 593system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 743000 # number of ReadExReq MSHR miss cycles 594system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1197000 # number of ReadExReq MSHR miss cycles 595system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 713000 # number of ReadExReq MSHR miss cycles 596system.l2c.ReadExReq_mshr_miss_latency::total 8545000 # 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616system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses | 616system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses |
617system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.030374 # mshr miss rate for ReadReq accesses | 617system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.024145 # mshr miss rate for ReadReq accesses |
618system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083333 # mshr miss rate for ReadReq accesses | 618system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083333 # mshr miss rate for ReadReq accesses |
619system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.169811 # mshr miss rate for ReadReq accesses | 619system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.157143 # mshr miss rate for ReadReq accesses |
620system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.583333 # mshr miss rate for ReadReq accesses | 620system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.583333 # mshr miss rate for ReadReq accesses |
621system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.009302 # mshr miss rate for ReadReq accesses | 621system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.008114 # mshr miss rate for ReadReq accesses |
622system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses | 622system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses |
623system.l2c.ReadReq_mshr_miss_rate::total 0.266499 # mshr miss rate for ReadReq accesses 624system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses | 623system.l2c.ReadReq_mshr_miss_rate::total 0.243659 # mshr miss rate for ReadReq accesses 624system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.884615 # mshr miss rate for UpgradeReq accesses |
625system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 626system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 627system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses | 625system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 626system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 627system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses |
628system.l2c.UpgradeReq_mshr_miss_rate::total 0.962500 # mshr miss rate for UpgradeReq accesses | 628system.l2c.UpgradeReq_mshr_miss_rate::total 0.962963 # mshr miss rate for UpgradeReq accesses |
629system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 630system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 631system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 632system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 633system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses | 629system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 630system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 631system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 632system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 633system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
634system.l2c.demand_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for demand accesses | 634system.l2c.demand_mshr_miss_rate::cpu0.inst 0.590538 # mshr miss rate for demand accesses |
635system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses | 635system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses |
636system.l2c.demand_mshr_miss_rate::cpu1.inst 0.030374 # mshr miss rate for demand accesses | 636system.l2c.demand_mshr_miss_rate::cpu1.inst 0.024145 # mshr miss rate for demand accesses |
637system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses | 637system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses |
638system.l2c.demand_mshr_miss_rate::cpu2.inst 0.169811 # mshr miss rate for demand accesses | 638system.l2c.demand_mshr_miss_rate::cpu2.inst 0.157143 # mshr miss rate for demand accesses |
639system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses | 639system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses |
640system.l2c.demand_mshr_miss_rate::cpu3.inst 0.009302 # mshr miss rate for demand accesses | 640system.l2c.demand_mshr_miss_rate::cpu3.inst 0.008114 # mshr miss rate for demand accesses |
641system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses | 641system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses |
642system.l2c.demand_mshr_miss_rate::total 0.311909 # mshr miss rate for demand accesses 643system.l2c.overall_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for overall accesses | 642system.l2c.demand_mshr_miss_rate::total 0.286020 # mshr miss rate for demand accesses 643system.l2c.overall_mshr_miss_rate::cpu0.inst 0.590538 # mshr miss rate for overall accesses |
644system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses | 644system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses |
645system.l2c.overall_mshr_miss_rate::cpu1.inst 0.030374 # mshr miss rate for overall accesses | 645system.l2c.overall_mshr_miss_rate::cpu1.inst 0.024145 # mshr miss rate for overall accesses |
646system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses | 646system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses |
647system.l2c.overall_mshr_miss_rate::cpu2.inst 0.169811 # mshr miss rate for overall accesses | 647system.l2c.overall_mshr_miss_rate::cpu2.inst 0.157143 # mshr miss rate for overall accesses |
648system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses | 648system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses |
649system.l2c.overall_mshr_miss_rate::cpu3.inst 0.009302 # mshr miss rate for overall accesses | 649system.l2c.overall_mshr_miss_rate::cpu3.inst 0.008114 # mshr miss rate for overall accesses |
650system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses | 650system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses |
651system.l2c.overall_mshr_miss_rate::total 0.311909 # mshr miss rate for overall accesses 652system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55766.806723 # average ReadReq mshr miss latency 653system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60263.513514 # average ReadReq mshr miss latency 654system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66057.692308 # average ReadReq mshr miss latency | 651system.l2c.overall_mshr_miss_rate::total 0.286020 # mshr miss rate for overall accesses 652system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56542.817680 # average ReadReq mshr miss latency 653system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64057.432432 # average ReadReq mshr miss latency 654system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 75333.333333 # average ReadReq mshr miss latency |
655system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62500 # average ReadReq mshr miss latency | 655system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62500 # average ReadReq mshr miss latency |
656system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 58822.916667 # average ReadReq mshr miss latency 657system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 58392.857143 # average ReadReq mshr miss latency 658system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 64625 # average ReadReq mshr miss latency | 656system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 59938.311688 # average ReadReq mshr miss latency 657system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62321.428571 # average ReadReq mshr miss latency 658system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 59062.500000 # average ReadReq mshr miss latency |
659system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 62500 # average ReadReq mshr miss latency | 659system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 62500 # average ReadReq mshr miss latency |
660system.l2c.ReadReq_avg_mshr_miss_latency::total 57191.871456 # average ReadReq mshr miss latency | 660system.l2c.ReadReq_avg_mshr_miss_latency::total 58597.583643 # average ReadReq mshr miss latency |
661system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency | 661system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency |
662system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10405.714286 # average UpgradeReq mshr miss latency | 662system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency |
663system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency 664system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency | 663system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency 664system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency |
665system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10111.376623 # average UpgradeReq mshr miss latency 666system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 62680.851064 # average ReadExReq mshr miss latency 667system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61916.666667 # average ReadExReq mshr miss latency 668system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 92076.923077 # average ReadExReq mshr miss latency 669system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 59416.666667 # average ReadExReq mshr miss latency 670system.l2c.ReadExReq_avg_mshr_miss_latency::total 65229.007634 # average ReadExReq mshr miss latency 671system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55766.806723 # average overall mshr miss latency 672system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61616.071429 # average overall mshr miss latency 673system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66057.692308 # average overall mshr miss latency 674system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61961.538462 # average overall mshr miss latency 675system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 58822.916667 # average overall mshr miss latency 676system.l2c.demand_avg_mshr_miss_latency::cpu2.data 80287.500000 # average overall mshr miss latency 677system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 64625 # average overall mshr miss latency 678system.l2c.demand_avg_mshr_miss_latency::cpu3.data 59653.846154 # average overall mshr miss latency 679system.l2c.demand_avg_mshr_miss_latency::total 58787.121212 # average overall mshr miss latency 680system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55766.806723 # average overall mshr miss latency 681system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61616.071429 # average overall mshr miss latency 682system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66057.692308 # average overall mshr miss latency 683system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61961.538462 # average overall mshr miss latency 684system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 58822.916667 # average overall mshr miss latency 685system.l2c.overall_avg_mshr_miss_latency::cpu2.data 80287.500000 # average overall mshr miss latency 686system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 64625 # average overall mshr miss latency 687system.l2c.overall_avg_mshr_miss_latency::cpu3.data 59653.846154 # average overall mshr miss latency 688system.l2c.overall_avg_mshr_miss_latency::total 58787.121212 # average overall mshr miss latency | 665system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 666system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61292.553191 # average ReadExReq mshr miss latency 667system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58437.500000 # average ReadExReq mshr miss latency 668system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 68326.923077 # average ReadExReq mshr miss latency 669system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 57250 # average ReadExReq mshr miss latency 670system.l2c.ReadExReq_avg_mshr_miss_latency::total 61358.778626 # average ReadExReq mshr miss latency 671system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56542.817680 # average overall mshr miss latency 672system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62510.416667 # average overall mshr miss latency 673system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75333.333333 # average overall mshr miss latency 674system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58750 # average overall mshr miss latency 675system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 59938.311688 # average overall mshr miss latency 676system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66225 # average overall mshr miss latency 677system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 59062.500000 # average overall mshr miss latency 678system.l2c.demand_avg_mshr_miss_latency::cpu3.data 57653.846154 # average overall mshr miss latency 679system.l2c.demand_avg_mshr_miss_latency::total 59138.266069 # average overall mshr miss latency 680system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56542.817680 # average overall mshr miss latency 681system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62510.416667 # average overall mshr miss latency 682system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75333.333333 # average overall mshr miss latency 683system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58750 # average overall mshr miss latency 684system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 59938.311688 # average overall mshr miss latency 685system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66225 # average overall mshr miss latency 686system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 59062.500000 # average overall mshr miss latency 687system.l2c.overall_avg_mshr_miss_latency::cpu3.data 57653.846154 # average overall mshr miss latency 688system.l2c.overall_avg_mshr_miss_latency::total 59138.266069 # average overall mshr miss latency |
689system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 689system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
690system.toL2Bus.throughput 1688665006 # Throughput (bytes/s) 691system.toL2Bus.trans_dist::ReadReq 2536 # Transaction distribution 692system.toL2Bus.trans_dist::ReadResp 2535 # Transaction distribution | 690system.toL2Bus.throughput 1921108681 # Throughput (bytes/s) 691system.toL2Bus.trans_dist::ReadReq 2758 # Transaction distribution 692system.toL2Bus.trans_dist::ReadResp 2757 # Transaction distribution |
693system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution | 693system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution |
694system.toL2Bus.trans_dist::UpgradeReq 290 # Transaction distribution 695system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution 696system.toL2Bus.trans_dist::ReadExReq 392 # Transaction distribution 697system.toL2Bus.trans_dist::ReadExResp 392 # Transaction distribution 698system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1175 # Packet count per connected master and slave (bytes) 699system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 586 # Packet count per connected master and slave (bytes) 700system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 856 # Packet count per connected master and slave (bytes) 701system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 364 # Packet count per connected master and slave (bytes) 702system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 848 # Packet count per connected master and slave (bytes) 703system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) 704system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 860 # Packet count per connected master and slave (bytes) 705system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 358 # Packet count per connected master and slave (bytes) 706system.toL2Bus.pkt_count::total 5414 # Packet count per connected master and slave (bytes) 707system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 37568 # Cumulative packet size per connected master and slave (bytes) | 694system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution 695system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution 696system.toL2Bus.trans_dist::ReadExReq 413 # Transaction distribution 697system.toL2Bus.trans_dist::ReadExResp 413 # Transaction distribution 698system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1225 # Packet count per connected master and slave (bytes) 699system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 584 # Packet count per connected master and slave (bytes) 700system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) 701system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 361 # Packet count per connected master and slave (bytes) 702system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 980 # Packet count per connected master and slave (bytes) 703system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) 704system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 986 # Packet count per connected master and slave (bytes) 705system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 371 # Packet count per connected master and slave (bytes) 706system.toL2Bus.pkt_count::total 5866 # Packet count per connected master and slave (bytes) 707system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39168 # Cumulative packet size per connected master and slave (bytes) |
708system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) | 708system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) |
709system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 27392 # Cumulative packet size per connected master and slave (bytes) | 709system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31808 # Cumulative packet size per connected master and slave (bytes) |
710system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) | 710system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) |
711system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 27136 # Cumulative packet size per connected master and slave (bytes) | 711system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31360 # Cumulative packet size per connected master and slave (bytes) |
712system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) | 712system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) |
713system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 27520 # Cumulative packet size per connected master and slave (bytes) | 713system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31552 # Cumulative packet size per connected master and slave (bytes) |
714system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) | 714system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) |
715system.toL2Bus.tot_pkt_size::total 135424 # Cumulative packet size per connected master and slave (bytes) 716system.toL2Bus.data_through_bus 135424 # Total data (bytes) 717system.toL2Bus.snoop_data_through_bus 51968 # Total snoop data (bytes) 718system.toL2Bus.reqLayer0.occupancy 1625975 # Layer occupancy (ticks) 719system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) 720system.toL2Bus.respLayer0.occupancy 2708248 # Layer occupancy (ticks) 721system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) 722system.toL2Bus.respLayer1.occupancy 1463019 # Layer occupancy (ticks) 723system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) 724system.toL2Bus.respLayer2.occupancy 1929745 # Layer occupancy (ticks) 725system.toL2Bus.respLayer2.utilization 1.7 # Layer utilization (%) 726system.toL2Bus.respLayer3.occupancy 1153498 # Layer occupancy (ticks) 727system.toL2Bus.respLayer3.utilization 1.0 # Layer utilization (%) 728system.toL2Bus.respLayer4.occupancy 1921995 # Layer occupancy (ticks) 729system.toL2Bus.respLayer4.utilization 1.7 # Layer utilization (%) 730system.toL2Bus.respLayer5.occupancy 1183735 # Layer occupancy (ticks) | 715system.toL2Bus.tot_pkt_size::total 149696 # Cumulative packet size per connected master and slave (bytes) 716system.toL2Bus.data_through_bus 149696 # Total data (bytes) 717system.toL2Bus.snoop_data_through_bus 53248 # Total snoop data (bytes) 718system.toL2Bus.reqLayer0.occupancy 1733986 # Layer occupancy (ticks) 719system.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) 720system.toL2Bus.respLayer0.occupancy 2820249 # Layer occupancy (ticks) 721system.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) 722system.toL2Bus.respLayer1.occupancy 1469763 # Layer occupancy (ticks) 723system.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) 724system.toL2Bus.respLayer2.occupancy 2240244 # Layer occupancy (ticks) 725system.toL2Bus.respLayer2.utilization 2.1 # Layer utilization (%) 726system.toL2Bus.respLayer3.occupancy 1184253 # Layer occupancy (ticks) 727system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%) 728system.toL2Bus.respLayer4.occupancy 2220245 # Layer occupancy (ticks) 729system.toL2Bus.respLayer4.utilization 2.1 # Layer utilization (%) 730system.toL2Bus.respLayer5.occupancy 1188993 # Layer occupancy (ticks) |
731system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) | 731system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) |
732system.toL2Bus.respLayer6.occupancy 1936494 # Layer occupancy (ticks) 733system.toL2Bus.respLayer6.utilization 1.7 # Layer utilization (%) 734system.toL2Bus.respLayer7.occupancy 1159999 # Layer occupancy (ticks) 735system.toL2Bus.respLayer7.utilization 1.0 # Layer utilization (%) 736system.cpu0.branchPred.lookups 83070 # Number of BP lookups 737system.cpu0.branchPred.condPredicted 80870 # Number of conditional branches predicted 738system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect 739system.cpu0.branchPred.BTBLookups 80399 # Number of BTB lookups 740system.cpu0.branchPred.BTBHits 78350 # Number of BTB hits | 732system.toL2Bus.respLayer6.occupancy 2220246 # Layer occupancy (ticks) 733system.toL2Bus.respLayer6.utilization 2.1 # Layer utilization (%) 734system.toL2Bus.respLayer7.occupancy 1196995 # Layer occupancy (ticks) 735system.toL2Bus.respLayer7.utilization 1.1 # Layer utilization (%) 736system.cpu0.branchPred.lookups 81365 # Number of BP lookups 737system.cpu0.branchPred.condPredicted 78481 # Number of conditional branches predicted 738system.cpu0.branchPred.condIncorrect 1187 # Number of conditional branches incorrect 739system.cpu0.branchPred.BTBLookups 78090 # Number of BTB lookups 740system.cpu0.branchPred.BTBHits 75342 # Number of BTB hits |
741system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 741system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
742system.cpu0.branchPred.BTBHitPct 97.451461 # BTB Hit Percentage 743system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target. 744system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. | 742system.cpu0.branchPred.BTBHitPct 96.480983 # BTB Hit Percentage 743system.cpu0.branchPred.usedRAS 733 # Number of times the RAS was used to get a target. 744system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. |
745system.cpu0.workload.num_syscalls 89 # Number of system calls | 745system.cpu0.workload.num_syscalls 89 # Number of system calls |
746system.cpu0.numCycles 221942 # number of cpu cycles simulated | 746system.cpu0.numCycles 211279 # number of cpu cycles simulated |
747system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 748system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 747system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 748system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
749system.cpu0.fetch.icacheStallCycles 17233 # Number of cycles fetch is stalled on an Icache miss 750system.cpu0.fetch.Insts 493008 # Number of instructions fetch has processed 751system.cpu0.fetch.Branches 83070 # Number of branches that fetch encountered 752system.cpu0.fetch.predictedBranches 78862 # Number of branches that fetch has predicted taken 753system.cpu0.fetch.Cycles 161826 # Number of cycles fetch has run and was not squashing or blocked 754system.cpu0.fetch.SquashCycles 3812 # Number of cycles fetch has spent squashing 755system.cpu0.fetch.BlockedCycles 13755 # Number of cycles fetch has spent blocked 756system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 757system.cpu0.fetch.PendingTrapStallCycles 1482 # Number of stall cycles due to pending traps 758system.cpu0.fetch.CacheLines 5835 # Number of cache lines fetched 759system.cpu0.fetch.IcacheSquashes 491 # Number of outstanding Icache misses that were squashed 760system.cpu0.fetch.rateDist::samples 196747 # Number of instructions fetched each cycle (Total) 761system.cpu0.fetch.rateDist::mean 2.505797 # Number of instructions fetched each cycle (Total) 762system.cpu0.fetch.rateDist::stdev 2.214858 # Number of instructions fetched each cycle (Total) | 749system.cpu0.fetch.icacheStallCycles 20058 # Number of cycles fetch is stalled on an Icache miss 750system.cpu0.fetch.Insts 480743 # Number of instructions fetch has processed 751system.cpu0.fetch.Branches 81365 # Number of branches that fetch encountered 752system.cpu0.fetch.predictedBranches 76075 # Number of branches that fetch has predicted taken 753system.cpu0.fetch.Cycles 164045 # Number of cycles fetch has run and was not squashing or blocked 754system.cpu0.fetch.SquashCycles 2674 # Number of cycles fetch has spent squashing 755system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 756system.cpu0.fetch.PendingTrapStallCycles 1880 # Number of stall cycles due to pending traps 757system.cpu0.fetch.CacheLines 7123 # Number of cache lines fetched 758system.cpu0.fetch.IcacheSquashes 658 # Number of outstanding Icache misses that were squashed 759system.cpu0.fetch.rateDist::samples 187323 # Number of instructions fetched each cycle (Total) 760system.cpu0.fetch.rateDist::mean 2.566385 # Number of instructions fetched each cycle (Total) 761system.cpu0.fetch.rateDist::stdev 2.225399 # Number of instructions fetched each cycle (Total) |
763system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 762system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
764system.cpu0.fetch.rateDist::0 34921 17.75% 17.75% # Number of instructions fetched each cycle (Total) 765system.cpu0.fetch.rateDist::1 80152 40.74% 58.49% # Number of instructions fetched each cycle (Total) 766system.cpu0.fetch.rateDist::2 578 0.29% 58.78% # Number of instructions fetched each cycle (Total) 767system.cpu0.fetch.rateDist::3 974 0.50% 59.28% # Number of instructions fetched each cycle (Total) 768system.cpu0.fetch.rateDist::4 477 0.24% 59.52% # Number of instructions fetched each cycle (Total) 769system.cpu0.fetch.rateDist::5 76267 38.76% 98.28% # Number of instructions fetched each cycle (Total) 770system.cpu0.fetch.rateDist::6 570 0.29% 98.57% # Number of instructions fetched each cycle (Total) 771system.cpu0.fetch.rateDist::7 349 0.18% 98.75% # Number of instructions fetched each cycle (Total) 772system.cpu0.fetch.rateDist::8 2459 1.25% 100.00% # Number of instructions fetched each cycle (Total) | 763system.cpu0.fetch.rateDist::0 30153 16.10% 16.10% # Number of instructions fetched each cycle (Total) 764system.cpu0.fetch.rateDist::1 77599 41.43% 57.52% # Number of instructions fetched each cycle (Total) 765system.cpu0.fetch.rateDist::2 823 0.44% 57.96% # Number of instructions fetched each cycle (Total) 766system.cpu0.fetch.rateDist::3 1078 0.58% 58.54% # Number of instructions fetched each cycle (Total) 767system.cpu0.fetch.rateDist::4 624 0.33% 58.87% # Number of instructions fetched each cycle (Total) 768system.cpu0.fetch.rateDist::5 72927 38.93% 97.80% # Number of instructions fetched each cycle (Total) 769system.cpu0.fetch.rateDist::6 691 0.37% 98.17% # Number of instructions fetched each cycle (Total) 770system.cpu0.fetch.rateDist::7 437 0.23% 98.40% # Number of instructions fetched each cycle (Total) 771system.cpu0.fetch.rateDist::8 2991 1.60% 100.00% # Number of instructions fetched each cycle (Total) |
773system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 774system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 775system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 772system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 773system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 774system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
776system.cpu0.fetch.rateDist::total 196747 # Number of instructions fetched each cycle (Total) 777system.cpu0.fetch.branchRate 0.374287 # Number of branch fetches per cycle 778system.cpu0.fetch.rate 2.221337 # Number of inst fetches per cycle 779system.cpu0.decode.IdleCycles 17711 # Number of cycles decode is idle 780system.cpu0.decode.BlockedCycles 15452 # Number of cycles decode is blocked 781system.cpu0.decode.RunCycles 160920 # Number of cycles decode is running 782system.cpu0.decode.UnblockCycles 218 # Number of cycles decode is unblocking 783system.cpu0.decode.SquashCycles 2446 # Number of cycles decode is squashing 784system.cpu0.decode.DecodedInsts 490118 # Number of instructions handled by decode 785system.cpu0.rename.SquashCycles 2446 # Number of cycles rename is squashing 786system.cpu0.rename.IdleCycles 18323 # Number of cycles rename is idle 787system.cpu0.rename.BlockCycles 441 # Number of cycles rename is blocking 788system.cpu0.rename.serializeStallCycles 14289 # count of cycles rename stalled for serializing inst 789system.cpu0.rename.RunCycles 160585 # Number of cycles rename is running 790system.cpu0.rename.UnblockCycles 663 # Number of cycles rename is unblocking 791system.cpu0.rename.RenamedInsts 487271 # Number of instructions processed by rename 792system.cpu0.rename.SQFullEvents 294 # Number of times rename has blocked due to SQ full 793system.cpu0.rename.RenamedOperands 333181 # Number of destination operands rename has renamed 794system.cpu0.rename.RenameLookups 971741 # Number of register rename lookups that rename has made 795system.cpu0.rename.int_rename_lookups 733988 # Number of integer rename lookups 796system.cpu0.rename.CommittedMaps 320207 # Number of HB maps that are committed 797system.cpu0.rename.UndoneMaps 12974 # Number of HB maps that are undone due to squashing 798system.cpu0.rename.serializingInsts 868 # count of serializing insts renamed 799system.cpu0.rename.tempSerializingInsts 890 # count of temporary serializing insts renamed 800system.cpu0.rename.skidInsts 3239 # count of insts added to the skid buffer 801system.cpu0.memDep0.insertedLoads 155891 # Number of loads inserted to the mem dependence unit. 802system.cpu0.memDep0.insertedStores 78785 # Number of stores inserted to the mem dependence unit. 803system.cpu0.memDep0.conflictingLoads 76033 # Number of conflicting loads. 804system.cpu0.memDep0.conflictingStores 75852 # Number of conflicting stores. 805system.cpu0.iq.iqInstsAdded 407472 # Number of instructions added to the IQ (excludes non-spec) 806system.cpu0.iq.iqNonSpecInstsAdded 912 # Number of non-speculative instructions added to the IQ 807system.cpu0.iq.iqInstsIssued 404753 # Number of instructions issued 808system.cpu0.iq.iqSquashedInstsIssued 136 # Number of squashed instructions issued 809system.cpu0.iq.iqSquashedInstsExamined 10781 # Number of squashed instructions iterated over during squash; mainly for profiling 810system.cpu0.iq.iqSquashedOperandsExamined 9726 # Number of squashed operands that are examined and possibly removed from graph 811system.cpu0.iq.iqSquashedNonSpecRemoved 353 # Number of squashed non-spec instructions that were removed 812system.cpu0.iq.issued_per_cycle::samples 196747 # Number of insts issued each cycle 813system.cpu0.iq.issued_per_cycle::mean 2.057226 # Number of insts issued each cycle 814system.cpu0.iq.issued_per_cycle::stdev 1.098946 # Number of insts issued each cycle | 775system.cpu0.fetch.rateDist::total 187323 # Number of instructions fetched each cycle (Total) 776system.cpu0.fetch.branchRate 0.385107 # Number of branch fetches per cycle 777system.cpu0.fetch.rate 2.275394 # Number of inst fetches per cycle 778system.cpu0.decode.IdleCycles 15731 # Number of cycles decode is idle 779system.cpu0.decode.BlockedCycles 17849 # Number of cycles decode is blocked 780system.cpu0.decode.RunCycles 151731 # Number of cycles decode is running 781system.cpu0.decode.UnblockCycles 675 # Number of cycles decode is unblocking 782system.cpu0.decode.SquashCycles 1337 # Number of cycles decode is squashing 783system.cpu0.decode.DecodedInsts 468882 # Number of instructions handled by decode 784system.cpu0.rename.SquashCycles 1337 # Number of cycles rename is squashing 785system.cpu0.rename.IdleCycles 16349 # Number of cycles rename is idle 786system.cpu0.rename.BlockCycles 2025 # Number of cycles rename is blocking 787system.cpu0.rename.serializeStallCycles 14605 # count of cycles rename stalled for serializing inst 788system.cpu0.rename.RunCycles 151742 # Number of cycles rename is running 789system.cpu0.rename.UnblockCycles 1265 # Number of cycles rename is unblocking 790system.cpu0.rename.RenamedInsts 465427 # Number of instructions processed by rename 791system.cpu0.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full 792system.cpu0.rename.LQFullEvents 18 # Number of times rename has blocked due to LQ full 793system.cpu0.rename.SQFullEvents 756 # Number of times rename has blocked due to SQ full 794system.cpu0.rename.RenamedOperands 318792 # Number of destination operands rename has renamed 795system.cpu0.rename.RenameLookups 928161 # Number of register rename lookups that rename has made 796system.cpu0.rename.int_rename_lookups 701504 # Number of integer rename lookups 797system.cpu0.rename.CommittedMaps 304835 # Number of HB maps that are committed 798system.cpu0.rename.UndoneMaps 13957 # Number of HB maps that are undone due to squashing 799system.cpu0.rename.serializingInsts 896 # count of serializing insts renamed 800system.cpu0.rename.tempSerializingInsts 905 # count of temporary serializing insts renamed 801system.cpu0.rename.skidInsts 4588 # count of insts added to the skid buffer 802system.cpu0.memDep0.insertedLoads 148468 # Number of loads inserted to the mem dependence unit. 803system.cpu0.memDep0.insertedStores 75131 # Number of stores inserted to the mem dependence unit. 804system.cpu0.memDep0.conflictingLoads 72391 # Number of conflicting loads. 805system.cpu0.memDep0.conflictingStores 72142 # Number of conflicting stores. 806system.cpu0.iq.iqInstsAdded 389496 # Number of instructions added to the IQ (excludes non-spec) 807system.cpu0.iq.iqNonSpecInstsAdded 964 # Number of non-speculative instructions added to the IQ 808system.cpu0.iq.iqInstsIssued 386182 # Number of instructions issued 809system.cpu0.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued 810system.cpu0.iq.iqSquashedInstsExamined 12213 # Number of squashed instructions iterated over during squash; mainly for profiling 811system.cpu0.iq.iqSquashedOperandsExamined 11099 # Number of squashed operands that are examined and possibly removed from graph 812system.cpu0.iq.iqSquashedNonSpecRemoved 405 # Number of squashed non-spec instructions that were removed 813system.cpu0.iq.issued_per_cycle::samples 187323 # Number of insts issued each cycle 814system.cpu0.iq.issued_per_cycle::mean 2.061583 # Number of insts issued each cycle 815system.cpu0.iq.issued_per_cycle::stdev 1.125394 # Number of insts issued each cycle |
815system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 816system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
816system.cpu0.iq.issued_per_cycle::0 34174 17.37% 17.37% # Number of insts issued each cycle 817system.cpu0.iq.issued_per_cycle::1 4673 2.38% 19.74% # Number of insts issued each cycle 818system.cpu0.iq.issued_per_cycle::2 77781 39.53% 59.28% # Number of insts issued each cycle 819system.cpu0.iq.issued_per_cycle::3 77469 39.37% 98.65% # Number of insts issued each cycle 820system.cpu0.iq.issued_per_cycle::4 1629 0.83% 99.48% # Number of insts issued each cycle 821system.cpu0.iq.issued_per_cycle::5 654 0.33% 99.81% # Number of insts issued each cycle 822system.cpu0.iq.issued_per_cycle::6 260 0.13% 99.95% # Number of insts issued each cycle 823system.cpu0.iq.issued_per_cycle::7 91 0.05% 99.99% # Number of insts issued each cycle 824system.cpu0.iq.issued_per_cycle::8 16 0.01% 100.00% # Number of insts issued each cycle | 817system.cpu0.iq.issued_per_cycle::0 33109 17.67% 17.67% # Number of insts issued each cycle 818system.cpu0.iq.issued_per_cycle::1 4301 2.30% 19.97% # Number of insts issued each cycle 819system.cpu0.iq.issued_per_cycle::2 73576 39.28% 59.25% # Number of insts issued each cycle 820system.cpu0.iq.issued_per_cycle::3 73130 39.04% 98.29% # Number of insts issued each cycle 821system.cpu0.iq.issued_per_cycle::4 1662 0.89% 99.18% # Number of insts issued each cycle 822system.cpu0.iq.issued_per_cycle::5 894 0.48% 99.65% # Number of insts issued each cycle 823system.cpu0.iq.issued_per_cycle::6 408 0.22% 99.87% # Number of insts issued each cycle 824system.cpu0.iq.issued_per_cycle::7 171 0.09% 99.96% # Number of insts issued each cycle 825system.cpu0.iq.issued_per_cycle::8 72 0.04% 100.00% # Number of insts issued each cycle |
825system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 826system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 827system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 826system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 827system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 828system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
828system.cpu0.iq.issued_per_cycle::total 196747 # Number of insts issued each cycle | 829system.cpu0.iq.issued_per_cycle::total 187323 # Number of insts issued each cycle |
829system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 830system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
830system.cpu0.iq.fu_full::IntAlu 60 26.43% 26.43% # attempts to use FU when none available 831system.cpu0.iq.fu_full::IntMult 0 0.00% 26.43% # attempts to use FU when none available 832system.cpu0.iq.fu_full::IntDiv 0 0.00% 26.43% # attempts to use FU when none available 833system.cpu0.iq.fu_full::FloatAdd 0 0.00% 26.43% # attempts to use FU when none available 834system.cpu0.iq.fu_full::FloatCmp 0 0.00% 26.43% # attempts to use FU when none available 835system.cpu0.iq.fu_full::FloatCvt 0 0.00% 26.43% # attempts to use FU when none available 836system.cpu0.iq.fu_full::FloatMult 0 0.00% 26.43% # attempts to use FU when none available 837system.cpu0.iq.fu_full::FloatDiv 0 0.00% 26.43% # attempts to use FU when none available 838system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 26.43% # attempts to use FU when none available 839system.cpu0.iq.fu_full::SimdAdd 0 0.00% 26.43% # attempts to use FU when none available 840system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 26.43% # attempts to use FU when none available 841system.cpu0.iq.fu_full::SimdAlu 0 0.00% 26.43% # attempts to use FU when none available 842system.cpu0.iq.fu_full::SimdCmp 0 0.00% 26.43% # attempts to use FU when none available 843system.cpu0.iq.fu_full::SimdCvt 0 0.00% 26.43% # attempts to use FU when none available 844system.cpu0.iq.fu_full::SimdMisc 0 0.00% 26.43% # attempts to use FU when none available 845system.cpu0.iq.fu_full::SimdMult 0 0.00% 26.43% # attempts to use FU when none available 846system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 26.43% # attempts to use FU when none available 847system.cpu0.iq.fu_full::SimdShift 0 0.00% 26.43% # attempts to use FU when none available 848system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 26.43% # attempts to use FU when none available 849system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 26.43% # attempts to use FU when none available 850system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 26.43% # attempts to use FU when none available 851system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 26.43% # attempts to use FU when none available 852system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 26.43% # attempts to use FU when none available 853system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 26.43% # attempts to use FU when none available 854system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 26.43% # attempts to use FU when none available 855system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 26.43% # attempts to use FU when none available 856system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 26.43% # attempts to use FU when none available 857system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.43% # attempts to use FU when none available 858system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 26.43% # attempts to use FU when none available 859system.cpu0.iq.fu_full::MemRead 55 24.23% 50.66% # attempts to use FU when none available 860system.cpu0.iq.fu_full::MemWrite 112 49.34% 100.00% # attempts to use FU when none available | 831system.cpu0.iq.fu_full::IntAlu 97 34.15% 34.15% # attempts to use FU when none available 832system.cpu0.iq.fu_full::IntMult 0 0.00% 34.15% # attempts to use FU when none available 833system.cpu0.iq.fu_full::IntDiv 0 0.00% 34.15% # attempts to use FU when none available 834system.cpu0.iq.fu_full::FloatAdd 0 0.00% 34.15% # attempts to use FU when none available 835system.cpu0.iq.fu_full::FloatCmp 0 0.00% 34.15% # attempts to use FU when none available 836system.cpu0.iq.fu_full::FloatCvt 0 0.00% 34.15% # attempts to use FU when none available 837system.cpu0.iq.fu_full::FloatMult 0 0.00% 34.15% # attempts to use FU when none available 838system.cpu0.iq.fu_full::FloatDiv 0 0.00% 34.15% # attempts to use FU when none available 839system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 34.15% # attempts to use FU when none available 840system.cpu0.iq.fu_full::SimdAdd 0 0.00% 34.15% # attempts to use FU when none available 841system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 34.15% # attempts to use FU when none available 842system.cpu0.iq.fu_full::SimdAlu 0 0.00% 34.15% # attempts to use FU when none available 843system.cpu0.iq.fu_full::SimdCmp 0 0.00% 34.15% # attempts to use FU when none available 844system.cpu0.iq.fu_full::SimdCvt 0 0.00% 34.15% # attempts to use FU when none available 845system.cpu0.iq.fu_full::SimdMisc 0 0.00% 34.15% # attempts to use FU when none available 846system.cpu0.iq.fu_full::SimdMult 0 0.00% 34.15% # attempts to use FU when none available 847system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 34.15% # attempts to use FU when none available 848system.cpu0.iq.fu_full::SimdShift 0 0.00% 34.15% # attempts to use FU when none available 849system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 34.15% # attempts to use FU when none available 850system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 34.15% # attempts to use FU when none available 851system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 34.15% # attempts to use FU when none available 852system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 34.15% # attempts to use FU when none available 853system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 34.15% # attempts to use FU when none available 854system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 34.15% # attempts to use FU when none available 855system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 34.15% # attempts to use FU when none available 856system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 34.15% # attempts to use FU when none available 857system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 34.15% # attempts to use FU when none available 858system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.15% # attempts to use FU when none available 859system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 34.15% # attempts to use FU when none available 860system.cpu0.iq.fu_full::MemRead 84 29.58% 63.73% # attempts to use FU when none available 861system.cpu0.iq.fu_full::MemWrite 103 36.27% 100.00% # attempts to use FU when none available |
861system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 862system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 863system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 862system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 863system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 864system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
864system.cpu0.iq.FU_type_0::IntAlu 171127 42.28% 42.28% # Type of FU issued 865system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.28% # Type of FU issued 866system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.28% # Type of FU issued 867system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.28% # Type of FU issued 868system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.28% # Type of FU issued 869system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.28% # Type of FU issued 870system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.28% # Type of FU issued 871system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.28% # Type of FU issued 872system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.28% # Type of FU issued 873system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.28% # Type of FU issued 874system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.28% # Type of FU issued 875system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.28% # Type of FU issued 876system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.28% # Type of FU issued 877system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.28% # Type of FU issued 878system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.28% # Type of FU issued 879system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.28% # Type of FU issued 880system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.28% # Type of FU issued 881system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.28% # Type of FU issued 882system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.28% # Type of FU issued 883system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.28% # Type of FU issued 884system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.28% # Type of FU issued 885system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.28% # Type of FU issued 886system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.28% # Type of FU issued 887system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.28% # Type of FU issued 888system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.28% # Type of FU issued 889system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.28% # Type of FU issued 890system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.28% # Type of FU issued 891system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.28% # Type of FU issued 892system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.28% # Type of FU issued 893system.cpu0.iq.FU_type_0::MemRead 155427 38.40% 80.68% # Type of FU issued 894system.cpu0.iq.FU_type_0::MemWrite 78199 19.32% 100.00% # Type of FU issued | 865system.cpu0.iq.FU_type_0::IntAlu 163788 42.41% 42.41% # Type of FU issued 866system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.41% # Type of FU issued 867system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.41% # Type of FU issued 868system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.41% # Type of FU issued 869system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.41% # Type of FU issued 870system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.41% # Type of FU issued 871system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.41% # Type of FU issued 872system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.41% # Type of FU issued 873system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.41% # Type of FU issued 874system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.41% # Type of FU issued 875system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.41% # Type of FU issued 876system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.41% # Type of FU issued 877system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.41% # Type of FU issued 878system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.41% # Type of FU issued 879system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.41% # Type of FU issued 880system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.41% # Type of FU issued 881system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.41% # Type of FU issued 882system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.41% # Type of FU issued 883system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.41% # Type of FU issued 884system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.41% # Type of FU issued 885system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.41% # Type of FU issued 886system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.41% # Type of FU issued 887system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.41% # Type of FU issued 888system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.41% # Type of FU issued 889system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.41% # Type of FU issued 890system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.41% # Type of FU issued 891system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.41% # Type of FU issued 892system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.41% # Type of FU issued 893system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.41% # Type of FU issued 894system.cpu0.iq.FU_type_0::MemRead 147930 38.31% 80.72% # Type of FU issued 895system.cpu0.iq.FU_type_0::MemWrite 74464 19.28% 100.00% # Type of FU issued |
895system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 896system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 896system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 897system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
897system.cpu0.iq.FU_type_0::total 404753 # Type of FU issued 898system.cpu0.iq.rate 1.823688 # Inst issue rate 899system.cpu0.iq.fu_busy_cnt 227 # FU busy when requested 900system.cpu0.iq.fu_busy_rate 0.000561 # FU busy rate (busy events/executed inst) 901system.cpu0.iq.int_inst_queue_reads 1006616 # Number of integer instruction queue reads 902system.cpu0.iq.int_inst_queue_writes 419219 # Number of integer instruction queue writes 903system.cpu0.iq.int_inst_queue_wakeup_accesses 402934 # Number of integer instruction queue wakeup accesses | 898system.cpu0.iq.FU_type_0::total 386182 # Type of FU issued 899system.cpu0.iq.rate 1.827830 # Inst issue rate 900system.cpu0.iq.fu_busy_cnt 284 # FU busy when requested 901system.cpu0.iq.fu_busy_rate 0.000735 # FU busy rate (busy events/executed inst) 902system.cpu0.iq.int_inst_queue_reads 959994 # Number of integer instruction queue reads 903system.cpu0.iq.int_inst_queue_writes 402726 # Number of integer instruction queue writes 904system.cpu0.iq.int_inst_queue_wakeup_accesses 384333 # Number of integer instruction queue wakeup accesses |
904system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 905system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 906system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 905system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 906system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 907system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
907system.cpu0.iq.int_alu_accesses 404980 # Number of integer alu accesses | 908system.cpu0.iq.int_alu_accesses 386466 # Number of integer alu accesses |
908system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses | 909system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses |
909system.cpu0.iew.lsq.thread0.forwLoads 75562 # Number of loads that had data forwarded from stores | 910system.cpu0.iew.lsq.thread0.forwLoads 71762 # Number of loads that had data forwarded from stores |
910system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 911system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
911system.cpu0.iew.lsq.thread0.squashedLoads 2198 # Number of loads squashed 912system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed | 912system.cpu0.iew.lsq.thread0.squashedLoads 2461 # Number of loads squashed 913system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed |
913system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations | 914system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations |
914system.cpu0.iew.lsq.thread0.squashedStores 1432 # Number of stores squashed | 915system.cpu0.iew.lsq.thread0.squashedStores 1621 # Number of stores squashed |
915system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 916system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 917system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled | 916system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 917system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 918system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled |
918system.cpu0.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked | 919system.cpu0.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked |
919system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 920system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
920system.cpu0.iew.iewSquashCycles 2446 # Number of cycles IEW is squashing 921system.cpu0.iew.iewBlockCycles 397 # Number of cycles IEW is blocking 922system.cpu0.iew.iewUnblockCycles 44 # Number of cycles IEW is unblocking 923system.cpu0.iew.iewDispatchedInsts 484968 # Number of instructions dispatched to IQ 924system.cpu0.iew.iewDispSquashedInsts 314 # Number of squashed instructions skipped by dispatch 925system.cpu0.iew.iewDispLoadInsts 155891 # Number of dispatched load instructions 926system.cpu0.iew.iewDispStoreInsts 78785 # Number of dispatched store instructions 927system.cpu0.iew.iewDispNonSpecInsts 800 # Number of dispatched non-speculative instructions 928system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall 929system.cpu0.iew.iewLSQFullEvents 9 # Number of times the LSQ has become full, causing a stall | 921system.cpu0.iew.iewSquashCycles 1337 # Number of cycles IEW is squashing 922system.cpu0.iew.iewBlockCycles 1986 # Number of cycles IEW is blocking 923system.cpu0.iew.iewUnblockCycles 48 # Number of cycles IEW is unblocking 924system.cpu0.iew.iewDispatchedInsts 463277 # Number of instructions dispatched to IQ 925system.cpu0.iew.iewDispSquashedInsts 160 # Number of squashed instructions skipped by dispatch 926system.cpu0.iew.iewDispLoadInsts 148468 # Number of dispatched load instructions 927system.cpu0.iew.iewDispStoreInsts 75131 # Number of dispatched store instructions 928system.cpu0.iew.iewDispNonSpecInsts 843 # Number of dispatched non-speculative instructions 929system.cpu0.iew.iewIQFullEvents 43 # Number of times the IQ has become full, causing a stall 930system.cpu0.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall |
930system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations | 931system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations |
931system.cpu0.iew.predictedTakenIncorrect 343 # Number of branches that were predicted taken incorrectly 932system.cpu0.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly 933system.cpu0.iew.branchMispredicts 1449 # Number of branch mispredicts detected at execute 934system.cpu0.iew.iewExecutedInsts 403684 # Number of executed instructions 935system.cpu0.iew.iewExecLoadInsts 155095 # Number of load instructions executed 936system.cpu0.iew.iewExecSquashedInsts 1069 # Number of squashed instructions skipped in execute | 932system.cpu0.iew.predictedTakenIncorrect 323 # Number of branches that were predicted taken incorrectly 933system.cpu0.iew.predictedNotTakenIncorrect 1099 # Number of branches that were predicted not taken incorrectly 934system.cpu0.iew.branchMispredicts 1422 # Number of branch mispredicts detected at execute 935system.cpu0.iew.iewExecutedInsts 385174 # Number of executed instructions 936system.cpu0.iew.iewExecLoadInsts 147630 # Number of load instructions executed 937system.cpu0.iew.iewExecSquashedInsts 1008 # Number of squashed instructions skipped in execute |
937system.cpu0.iew.exec_swp 0 # number of swp insts executed | 938system.cpu0.iew.exec_swp 0 # number of swp insts executed |
938system.cpu0.iew.exec_nop 76584 # number of nop insts executed 939system.cpu0.iew.exec_refs 233191 # number of memory reference insts executed 940system.cpu0.iew.exec_branches 80195 # Number of branches executed 941system.cpu0.iew.exec_stores 78096 # Number of stores executed 942system.cpu0.iew.exec_rate 1.818872 # Inst execution rate 943system.cpu0.iew.wb_sent 403263 # cumulative count of insts sent to commit 944system.cpu0.iew.wb_count 402934 # cumulative count of insts written-back 945system.cpu0.iew.wb_producers 238926 # num instructions producing a value 946system.cpu0.iew.wb_consumers 241439 # num instructions consuming a value | 939system.cpu0.iew.exec_nop 72817 # number of nop insts executed 940system.cpu0.iew.exec_refs 221956 # number of memory reference insts executed 941system.cpu0.iew.exec_branches 76403 # Number of branches executed 942system.cpu0.iew.exec_stores 74326 # Number of stores executed 943system.cpu0.iew.exec_rate 1.823059 # Inst execution rate 944system.cpu0.iew.wb_sent 384701 # cumulative count of insts sent to commit 945system.cpu0.iew.wb_count 384333 # cumulative count of insts written-back 946system.cpu0.iew.wb_producers 227933 # num instructions producing a value 947system.cpu0.iew.wb_consumers 231165 # num instructions consuming a value |
947system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 948system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
948system.cpu0.iew.wb_rate 1.815492 # insts written-back per cycle 949system.cpu0.iew.wb_fanout 0.989592 # average fanout of values written-back | 949system.cpu0.iew.wb_rate 1.819078 # insts written-back per cycle 950system.cpu0.iew.wb_fanout 0.986019 # average fanout of values written-back |
950system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 951system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
951system.cpu0.commit.commitSquashedInsts 12279 # The number of squashed insts skipped by commit | 952system.cpu0.commit.commitSquashedInsts 13622 # The number of squashed insts skipped by commit |
952system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards | 953system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards |
953system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted 954system.cpu0.commit.committed_per_cycle::samples 194301 # Number of insts commited each cycle 955system.cpu0.commit.committed_per_cycle::mean 2.432628 # Number of insts commited each cycle 956system.cpu0.commit.committed_per_cycle::stdev 2.139595 # Number of insts commited each cycle | 954system.cpu0.commit.branchMispredicts 1187 # The number of times a branch was mispredicted 955system.cpu0.commit.committed_per_cycle::samples 184699 # Number of insts commited each cycle 956system.cpu0.commit.committed_per_cycle::mean 2.434252 # Number of insts commited each cycle 957system.cpu0.commit.committed_per_cycle::stdev 2.147591 # Number of insts commited each cycle |
957system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 958system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
958system.cpu0.commit.committed_per_cycle::0 34596 17.81% 17.81% # Number of insts commited each cycle 959system.cpu0.commit.committed_per_cycle::1 79813 41.08% 58.88% # Number of insts commited each cycle 960system.cpu0.commit.committed_per_cycle::2 2261 1.16% 60.05% # Number of insts commited each cycle 961system.cpu0.commit.committed_per_cycle::3 671 0.35% 60.39% # Number of insts commited each cycle 962system.cpu0.commit.committed_per_cycle::4 526 0.27% 60.66% # Number of insts commited each cycle 963system.cpu0.commit.committed_per_cycle::5 75370 38.79% 99.45% # Number of insts commited each cycle 964system.cpu0.commit.committed_per_cycle::6 456 0.23% 99.69% # Number of insts commited each cycle 965system.cpu0.commit.committed_per_cycle::7 240 0.12% 99.81% # Number of insts commited each cycle 966system.cpu0.commit.committed_per_cycle::8 368 0.19% 100.00% # Number of insts commited each cycle | 959system.cpu0.commit.committed_per_cycle::0 33306 18.03% 18.03% # Number of insts commited each cycle 960system.cpu0.commit.committed_per_cycle::1 75499 40.88% 58.91% # Number of insts commited each cycle 961system.cpu0.commit.committed_per_cycle::2 2011 1.09% 60.00% # Number of insts commited each cycle 962system.cpu0.commit.committed_per_cycle::3 643 0.35% 60.35% # Number of insts commited each cycle 963system.cpu0.commit.committed_per_cycle::4 527 0.29% 60.63% # Number of insts commited each cycle 964system.cpu0.commit.committed_per_cycle::5 71457 38.69% 99.32% # Number of insts commited each cycle 965system.cpu0.commit.committed_per_cycle::6 519 0.28% 99.60% # Number of insts commited each cycle 966system.cpu0.commit.committed_per_cycle::7 249 0.13% 99.74% # Number of insts commited each cycle 967system.cpu0.commit.committed_per_cycle::8 488 0.26% 100.00% # Number of insts commited each cycle |
967system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 968system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 969system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 968system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 969system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 970system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
970system.cpu0.commit.committed_per_cycle::total 194301 # Number of insts commited each cycle 971system.cpu0.commit.committedInsts 472662 # Number of instructions committed 972system.cpu0.commit.committedOps 472662 # Number of ops (including micro ops) committed | 971system.cpu0.commit.committed_per_cycle::total 184699 # Number of insts commited each cycle 972system.cpu0.commit.committedInsts 449604 # Number of instructions committed 973system.cpu0.commit.committedOps 449604 # Number of ops (including micro ops) committed |
973system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed | 974system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed |
974system.cpu0.commit.refs 231046 # Number of memory references committed 975system.cpu0.commit.loads 153693 # Number of loads committed | 975system.cpu0.commit.refs 219517 # Number of memory references committed 976system.cpu0.commit.loads 146007 # Number of loads committed |
976system.cpu0.commit.membars 84 # Number of memory barriers committed | 977system.cpu0.commit.membars 84 # Number of memory barriers committed |
977system.cpu0.commit.branches 79240 # Number of branches committed | 978system.cpu0.commit.branches 75397 # Number of branches committed |
978system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. | 979system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. |
979system.cpu0.commit.int_insts 318538 # Number of committed integer instructions. | 980system.cpu0.commit.int_insts 303166 # Number of committed integer instructions. |
980system.cpu0.commit.function_calls 223 # Number of function calls committed. | 981system.cpu0.commit.function_calls 223 # Number of function calls committed. |
981system.cpu0.commit.op_class_0::No_OpClass 75972 16.07% 16.07% # Class of committed instruction 982system.cpu0.commit.op_class_0::IntAlu 165560 35.03% 51.10% # Class of committed instruction 983system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.10% # Class of committed instruction 984system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.10% # Class of committed instruction 985system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.10% # Class of committed instruction 986system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.10% # Class of committed instruction 987system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.10% # Class of committed instruction 988system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.10% # Class of committed instruction 989system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.10% # Class of committed instruction 990system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.10% # Class of committed instruction 991system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.10% # Class of committed instruction 992system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.10% # Class of committed instruction 993system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.10% # Class of committed instruction 994system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.10% # Class of committed instruction 995system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.10% # Class of committed instruction 996system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.10% # Class of committed instruction 997system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.10% # Class of committed instruction 998system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.10% # Class of committed instruction 999system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.10% # Class of committed instruction 1000system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.10% # Class of committed instruction 1001system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.10% # Class of committed instruction 1002system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.10% # Class of committed instruction 1003system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.10% # Class of committed instruction 1004system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.10% # Class of committed instruction 1005system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.10% # Class of committed instruction 1006system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.10% # Class of committed instruction 1007system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.10% # Class of committed instruction 1008system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.10% # Class of committed instruction 1009system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.10% # Class of committed instruction 1010system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.10% # Class of committed instruction 1011system.cpu0.commit.op_class_0::MemRead 153777 32.53% 83.63% # Class of committed instruction 1012system.cpu0.commit.op_class_0::MemWrite 77353 16.37% 100.00% # Class of committed instruction | 982system.cpu0.commit.op_class_0::No_OpClass 72129 16.04% 16.04% # Class of committed instruction 983system.cpu0.commit.op_class_0::IntAlu 157874 35.11% 51.16% # Class of committed instruction 984system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.16% # Class of committed instruction 985system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.16% # Class of committed instruction 986system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.16% # Class of committed instruction 987system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.16% # Class of committed instruction 988system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.16% # Class of committed instruction 989system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.16% # Class of committed instruction 990system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.16% # Class of committed instruction 991system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.16% # Class of committed instruction 992system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.16% # Class of committed instruction 993system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.16% # Class of committed instruction 994system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.16% # Class of committed instruction 995system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.16% # Class of committed instruction 996system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.16% # Class of committed instruction 997system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.16% # Class of committed instruction 998system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.16% # Class of committed instruction 999system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.16% # Class of committed instruction 1000system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.16% # Class of committed instruction 1001system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.16% # Class of committed instruction 1002system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.16% # Class of committed instruction 1003system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.16% # Class of committed instruction 1004system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.16% # Class of committed instruction 1005system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.16% # Class of committed instruction 1006system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.16% # Class of committed instruction 1007system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.16% # Class of committed instruction 1008system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.16% # Class of committed instruction 1009system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.16% # Class of committed instruction 1010system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.16% # Class of committed instruction 1011system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.16% # Class of committed instruction 1012system.cpu0.commit.op_class_0::MemRead 146091 32.49% 83.65% # Class of committed instruction 1013system.cpu0.commit.op_class_0::MemWrite 73510 16.35% 100.00% # Class of committed instruction |
1013system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1014system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 1014system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1015system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
1015system.cpu0.commit.op_class_0::total 472662 # Class of committed instruction 1016system.cpu0.commit.bw_lim_events 368 # number cycles where commit BW limit reached | 1016system.cpu0.commit.op_class_0::total 449604 # Class of committed instruction 1017system.cpu0.commit.bw_lim_events 488 # number cycles where commit BW limit reached |
1017system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits | 1018system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits |
1018system.cpu0.rob.rob_reads 677713 # The number of ROB reads 1019system.cpu0.rob.rob_writes 972345 # The number of ROB writes 1020system.cpu0.timesIdled 334 # Number of times that the entire CPU went into an idle state and unscheduled itself 1021system.cpu0.idleCycles 25195 # Total number of cycles that the CPU has spent unscheduled due to idling 1022system.cpu0.committedInsts 396606 # Number of Instructions Simulated 1023system.cpu0.committedOps 396606 # Number of Ops (including micro ops) Simulated 1024system.cpu0.cpi 0.559603 # CPI: Cycles Per Instruction 1025system.cpu0.cpi_total 0.559603 # CPI: Total CPI of All Threads 1026system.cpu0.ipc 1.786980 # IPC: Instructions Per Cycle 1027system.cpu0.ipc_total 1.786980 # IPC: Total IPC of All Threads 1028system.cpu0.int_regfile_reads 722190 # number of integer regfile reads 1029system.cpu0.int_regfile_writes 325483 # number of integer regfile writes | 1019system.cpu0.rob.rob_reads 646276 # The number of ROB reads 1020system.cpu0.rob.rob_writes 929096 # The number of ROB writes 1021system.cpu0.timesIdled 317 # Number of times that the entire CPU went into an idle state and unscheduled itself 1022system.cpu0.idleCycles 23956 # Total number of cycles that the CPU has spent unscheduled due to idling 1023system.cpu0.committedInsts 377391 # Number of Instructions Simulated 1024system.cpu0.committedOps 377391 # Number of Ops (including micro ops) Simulated 1025system.cpu0.cpi 0.559841 # CPI: Cycles Per Instruction 1026system.cpu0.cpi_total 0.559841 # CPI: Total CPI of All Threads 1027system.cpu0.ipc 1.786221 # IPC: Instructions Per Cycle 1028system.cpu0.ipc_total 1.786221 # IPC: Total IPC of All Threads 1029system.cpu0.int_regfile_reads 688854 # number of integer regfile reads 1030system.cpu0.int_regfile_writes 310766 # number of integer regfile writes |
1030system.cpu0.fp_regfile_reads 192 # number of floating regfile reads | 1031system.cpu0.fp_regfile_reads 192 # number of floating regfile reads |
1031system.cpu0.misc_regfile_reads 235015 # number of misc regfile reads | 1032system.cpu0.misc_regfile_reads 223843 # number of misc regfile reads |
1032system.cpu0.misc_regfile_writes 564 # number of misc regfile writes | 1033system.cpu0.misc_regfile_writes 564 # number of misc regfile writes |
1033system.cpu0.icache.tags.replacements 297 # number of replacements 1034system.cpu0.icache.tags.tagsinuse 241.252317 # Cycle average of tags in use 1035system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks. 1036system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks. 1037system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks. | 1034system.cpu0.icache.tags.replacements 322 # number of replacements 1035system.cpu0.icache.tags.tagsinuse 240.566848 # Cycle average of tags in use 1036system.cpu0.icache.tags.total_refs 6326 # Total number of references to valid blocks. 1037system.cpu0.icache.tags.sampled_refs 612 # Sample count of references to valid blocks. 1038system.cpu0.icache.tags.avg_refs 10.336601 # Average number of references to valid blocks. |
1038system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1039system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
1039system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.252317 # Average occupied blocks per requestor 1040system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471196 # Average percentage of cache occupancy 1041system.cpu0.icache.tags.occ_percent::total 0.471196 # Average percentage of cache occupancy | 1040system.cpu0.icache.tags.occ_blocks::cpu0.inst 240.566848 # Average occupied blocks per requestor 1041system.cpu0.icache.tags.occ_percent::cpu0.inst 0.469857 # Average percentage of cache occupancy 1042system.cpu0.icache.tags.occ_percent::total 0.469857 # Average percentage of cache occupancy |
1042system.cpu0.icache.tags.occ_task_id_blocks::1024 290 # Occupied blocks per task id | 1043system.cpu0.icache.tags.occ_task_id_blocks::1024 290 # Occupied blocks per task id |
1043system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id 1044system.cpu0.icache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id 1045system.cpu0.icache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id | 1044system.cpu0.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 1045system.cpu0.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id 1046system.cpu0.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id |
1046system.cpu0.icache.tags.occ_task_id_percent::1024 0.566406 # Percentage of cache occupancy per task id | 1047system.cpu0.icache.tags.occ_task_id_percent::1024 0.566406 # Percentage of cache occupancy per task id |
1047system.cpu0.icache.tags.tag_accesses 6422 # Number of tag accesses 1048system.cpu0.icache.tags.data_accesses 6422 # Number of data accesses 1049system.cpu0.icache.ReadReq_hits::cpu0.inst 5079 # number of ReadReq hits 1050system.cpu0.icache.ReadReq_hits::total 5079 # number of ReadReq hits 1051system.cpu0.icache.demand_hits::cpu0.inst 5079 # number of demand (read+write) hits 1052system.cpu0.icache.demand_hits::total 5079 # number of demand (read+write) hits 1053system.cpu0.icache.overall_hits::cpu0.inst 5079 # number of overall hits 1054system.cpu0.icache.overall_hits::total 5079 # number of overall hits 1055system.cpu0.icache.ReadReq_misses::cpu0.inst 756 # number of ReadReq misses 1056system.cpu0.icache.ReadReq_misses::total 756 # number of ReadReq misses 1057system.cpu0.icache.demand_misses::cpu0.inst 756 # number of demand (read+write) misses 1058system.cpu0.icache.demand_misses::total 756 # number of demand (read+write) misses 1059system.cpu0.icache.overall_misses::cpu0.inst 756 # number of overall misses 1060system.cpu0.icache.overall_misses::total 756 # number of overall misses 1061system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35519995 # number of ReadReq miss cycles 1062system.cpu0.icache.ReadReq_miss_latency::total 35519995 # number of ReadReq miss cycles 1063system.cpu0.icache.demand_miss_latency::cpu0.inst 35519995 # number of demand (read+write) miss cycles 1064system.cpu0.icache.demand_miss_latency::total 35519995 # number of demand (read+write) miss cycles 1065system.cpu0.icache.overall_miss_latency::cpu0.inst 35519995 # number of overall miss cycles 1066system.cpu0.icache.overall_miss_latency::total 35519995 # number of overall miss cycles 1067system.cpu0.icache.ReadReq_accesses::cpu0.inst 5835 # number of ReadReq accesses(hits+misses) 1068system.cpu0.icache.ReadReq_accesses::total 5835 # number of ReadReq accesses(hits+misses) 1069system.cpu0.icache.demand_accesses::cpu0.inst 5835 # number of demand (read+write) accesses 1070system.cpu0.icache.demand_accesses::total 5835 # number of demand (read+write) accesses 1071system.cpu0.icache.overall_accesses::cpu0.inst 5835 # number of overall (read+write) accesses 1072system.cpu0.icache.overall_accesses::total 5835 # number of overall (read+write) accesses 1073system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.129563 # miss rate for ReadReq accesses 1074system.cpu0.icache.ReadReq_miss_rate::total 0.129563 # miss rate for ReadReq accesses 1075system.cpu0.icache.demand_miss_rate::cpu0.inst 0.129563 # miss rate for demand accesses 1076system.cpu0.icache.demand_miss_rate::total 0.129563 # miss rate for demand accesses 1077system.cpu0.icache.overall_miss_rate::cpu0.inst 0.129563 # miss rate for overall accesses 1078system.cpu0.icache.overall_miss_rate::total 0.129563 # miss rate for overall accesses 1079system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46984.120370 # average ReadReq miss latency 1080system.cpu0.icache.ReadReq_avg_miss_latency::total 46984.120370 # average ReadReq miss latency 1081system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46984.120370 # average overall miss latency 1082system.cpu0.icache.demand_avg_miss_latency::total 46984.120370 # average overall miss latency 1083system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46984.120370 # average overall miss latency 1084system.cpu0.icache.overall_avg_miss_latency::total 46984.120370 # average overall miss latency 1085system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 1048system.cpu0.icache.tags.tag_accesses 7735 # Number of tag accesses 1049system.cpu0.icache.tags.data_accesses 7735 # Number of data accesses 1050system.cpu0.icache.ReadReq_hits::cpu0.inst 6326 # number of ReadReq hits 1051system.cpu0.icache.ReadReq_hits::total 6326 # number of ReadReq hits 1052system.cpu0.icache.demand_hits::cpu0.inst 6326 # number of demand (read+write) hits 1053system.cpu0.icache.demand_hits::total 6326 # number of demand (read+write) hits 1054system.cpu0.icache.overall_hits::cpu0.inst 6326 # number of overall hits 1055system.cpu0.icache.overall_hits::total 6326 # number of overall hits 1056system.cpu0.icache.ReadReq_misses::cpu0.inst 797 # number of ReadReq misses 1057system.cpu0.icache.ReadReq_misses::total 797 # number of ReadReq misses 1058system.cpu0.icache.demand_misses::cpu0.inst 797 # number of demand (read+write) misses 1059system.cpu0.icache.demand_misses::total 797 # number of demand (read+write) misses 1060system.cpu0.icache.overall_misses::cpu0.inst 797 # number of overall misses 1061system.cpu0.icache.overall_misses::total 797 # number of overall misses 1062system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 36681496 # number of ReadReq miss cycles 1063system.cpu0.icache.ReadReq_miss_latency::total 36681496 # number of ReadReq miss cycles 1064system.cpu0.icache.demand_miss_latency::cpu0.inst 36681496 # number of demand (read+write) miss cycles 1065system.cpu0.icache.demand_miss_latency::total 36681496 # number of demand (read+write) miss cycles 1066system.cpu0.icache.overall_miss_latency::cpu0.inst 36681496 # number of overall miss cycles 1067system.cpu0.icache.overall_miss_latency::total 36681496 # number of overall miss cycles 1068system.cpu0.icache.ReadReq_accesses::cpu0.inst 7123 # number of ReadReq accesses(hits+misses) 1069system.cpu0.icache.ReadReq_accesses::total 7123 # number of ReadReq accesses(hits+misses) 1070system.cpu0.icache.demand_accesses::cpu0.inst 7123 # number of demand (read+write) accesses 1071system.cpu0.icache.demand_accesses::total 7123 # number of demand (read+write) accesses 1072system.cpu0.icache.overall_accesses::cpu0.inst 7123 # number of overall (read+write) accesses 1073system.cpu0.icache.overall_accesses::total 7123 # number of overall (read+write) accesses 1074system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111891 # miss rate for ReadReq accesses 1075system.cpu0.icache.ReadReq_miss_rate::total 0.111891 # miss rate for ReadReq accesses 1076system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111891 # miss rate for demand accesses 1077system.cpu0.icache.demand_miss_rate::total 0.111891 # miss rate for demand accesses 1078system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111891 # miss rate for overall accesses 1079system.cpu0.icache.overall_miss_rate::total 0.111891 # miss rate for overall accesses 1080system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46024.461731 # average ReadReq miss latency 1081system.cpu0.icache.ReadReq_avg_miss_latency::total 46024.461731 # average ReadReq miss latency 1082system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46024.461731 # average overall miss latency 1083system.cpu0.icache.demand_avg_miss_latency::total 46024.461731 # average overall miss latency 1084system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46024.461731 # average overall miss latency 1085system.cpu0.icache.overall_avg_miss_latency::total 46024.461731 # average overall miss latency 1086system.cpu0.icache.blocked_cycles::no_mshrs 22 # number of cycles access was blocked |
1086system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1087system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
1087system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked | 1088system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked |
1088system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked | 1089system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked |
1089system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 1090system.cpu0.icache.avg_blocked_cycles::no_mshrs 22 # average number of cycles each access was blocked |
1090system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1091system.cpu0.icache.fast_writes 0 # number of fast writes performed 1092system.cpu0.icache.cache_copies 0 # number of cache copies performed | 1091system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1092system.cpu0.icache.fast_writes 0 # number of fast writes performed 1093system.cpu0.icache.cache_copies 0 # number of cache copies performed |
1093system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 168 # number of ReadReq MSHR hits 1094system.cpu0.icache.ReadReq_mshr_hits::total 168 # number of ReadReq MSHR hits 1095system.cpu0.icache.demand_mshr_hits::cpu0.inst 168 # number of demand (read+write) MSHR hits 1096system.cpu0.icache.demand_mshr_hits::total 168 # number of demand (read+write) MSHR hits 1097system.cpu0.icache.overall_mshr_hits::cpu0.inst 168 # number of overall MSHR hits 1098system.cpu0.icache.overall_mshr_hits::total 168 # number of overall MSHR hits 1099system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 588 # number of ReadReq MSHR misses 1100system.cpu0.icache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses 1101system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 # number of demand (read+write) MSHR misses 1102system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses 1103system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses 1104system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses 1105system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27366252 # number of ReadReq MSHR miss cycles 1106system.cpu0.icache.ReadReq_mshr_miss_latency::total 27366252 # number of ReadReq MSHR miss cycles 1107system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27366252 # number of demand (read+write) MSHR miss cycles 1108system.cpu0.icache.demand_mshr_miss_latency::total 27366252 # number of demand (read+write) MSHR miss cycles 1109system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27366252 # number of overall MSHR miss cycles 1110system.cpu0.icache.overall_mshr_miss_latency::total 27366252 # number of overall MSHR miss cycles 1111system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for ReadReq accesses 1112system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100771 # mshr miss rate for ReadReq accesses 1113system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for demand accesses 1114system.cpu0.icache.demand_mshr_miss_rate::total 0.100771 # mshr miss rate for demand accesses 1115system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for overall accesses 1116system.cpu0.icache.overall_mshr_miss_rate::total 0.100771 # mshr miss rate for overall accesses 1117system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46541.244898 # average ReadReq mshr miss latency 1118system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46541.244898 # average ReadReq mshr miss latency 1119system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46541.244898 # average overall mshr miss latency 1120system.cpu0.icache.demand_avg_mshr_miss_latency::total 46541.244898 # average overall mshr miss latency 1121system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46541.244898 # average overall mshr miss latency 1122system.cpu0.icache.overall_avg_mshr_miss_latency::total 46541.244898 # average overall mshr miss latency | 1094system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 184 # number of ReadReq MSHR hits 1095system.cpu0.icache.ReadReq_mshr_hits::total 184 # number of ReadReq MSHR hits 1096system.cpu0.icache.demand_mshr_hits::cpu0.inst 184 # number of demand (read+write) MSHR hits 1097system.cpu0.icache.demand_mshr_hits::total 184 # number of demand (read+write) MSHR hits 1098system.cpu0.icache.overall_mshr_hits::cpu0.inst 184 # number of overall MSHR hits 1099system.cpu0.icache.overall_mshr_hits::total 184 # number of overall MSHR hits 1100system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 613 # number of ReadReq MSHR misses 1101system.cpu0.icache.ReadReq_mshr_misses::total 613 # number of ReadReq MSHR misses 1102system.cpu0.icache.demand_mshr_misses::cpu0.inst 613 # number of demand (read+write) MSHR misses 1103system.cpu0.icache.demand_mshr_misses::total 613 # number of demand (read+write) MSHR misses 1104system.cpu0.icache.overall_mshr_misses::cpu0.inst 613 # number of overall MSHR misses 1105system.cpu0.icache.overall_mshr_misses::total 613 # number of overall MSHR misses 1106system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 28176251 # number of ReadReq MSHR miss cycles 1107system.cpu0.icache.ReadReq_mshr_miss_latency::total 28176251 # number of ReadReq MSHR miss cycles 1108system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 28176251 # number of demand (read+write) MSHR miss cycles 1109system.cpu0.icache.demand_mshr_miss_latency::total 28176251 # number of demand (read+write) MSHR miss cycles 1110system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 28176251 # number of overall MSHR miss cycles 1111system.cpu0.icache.overall_mshr_miss_latency::total 28176251 # number of overall MSHR miss cycles 1112system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for ReadReq accesses 1113system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.086059 # mshr miss rate for ReadReq accesses 1114system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for demand accesses 1115system.cpu0.icache.demand_mshr_miss_rate::total 0.086059 # mshr miss rate for demand accesses 1116system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for overall accesses 1117system.cpu0.icache.overall_mshr_miss_rate::total 0.086059 # mshr miss rate for overall accesses 1118system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 45964.520392 # average ReadReq mshr miss latency 1119system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 45964.520392 # average ReadReq mshr miss latency 1120system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 45964.520392 # average overall mshr miss latency 1121system.cpu0.icache.demand_avg_mshr_miss_latency::total 45964.520392 # average overall mshr miss latency 1122system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 45964.520392 # average overall mshr miss latency 1123system.cpu0.icache.overall_avg_mshr_miss_latency::total 45964.520392 # average overall mshr miss latency |
1123system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1124system.cpu0.dcache.tags.replacements 2 # number of replacements | 1124system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1125system.cpu0.dcache.tags.replacements 2 # number of replacements |
1125system.cpu0.dcache.tags.tagsinuse 141.985956 # Cycle average of tags in use 1126system.cpu0.dcache.tags.total_refs 155741 # Total number of references to valid blocks. | 1126system.cpu0.dcache.tags.tagsinuse 141.515257 # Cycle average of tags in use 1127system.cpu0.dcache.tags.total_refs 148145 # Total number of references to valid blocks. |
1127system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. | 1128system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. |
1128system.cpu0.dcache.tags.avg_refs 916.123529 # Average number of references to valid blocks. | 1129system.cpu0.dcache.tags.avg_refs 871.441176 # Average number of references to valid blocks. |
1129system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1130system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
1130system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.985956 # Average occupied blocks per requestor 1131system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277316 # Average percentage of cache occupancy 1132system.cpu0.dcache.tags.occ_percent::total 0.277316 # Average percentage of cache occupancy | 1131system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.515257 # Average occupied blocks per requestor 1132system.cpu0.dcache.tags.occ_percent::cpu0.data 0.276397 # Average percentage of cache occupancy 1133system.cpu0.dcache.tags.occ_percent::total 0.276397 # Average percentage of cache occupancy |
1133system.cpu0.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id 1134system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id | 1134system.cpu0.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id 1135system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id |
1135system.cpu0.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id 1136system.cpu0.dcache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id | 1136system.cpu0.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id 1137system.cpu0.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id |
1137system.cpu0.dcache.tags.occ_task_id_percent::1024 0.328125 # Percentage of cache occupancy per task id | 1138system.cpu0.dcache.tags.occ_task_id_percent::1024 0.328125 # Percentage of cache occupancy per task id |
1138system.cpu0.dcache.tags.tag_accesses 627612 # Number of tag accesses 1139system.cpu0.dcache.tags.data_accesses 627612 # Number of data accesses 1140system.cpu0.dcache.ReadReq_hits::cpu0.data 79059 # number of ReadReq hits 1141system.cpu0.dcache.ReadReq_hits::total 79059 # number of ReadReq hits 1142system.cpu0.dcache.WriteReq_hits::cpu0.data 76768 # number of WriteReq hits 1143system.cpu0.dcache.WriteReq_hits::total 76768 # number of WriteReq hits 1144system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits 1145system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits 1146system.cpu0.dcache.demand_hits::cpu0.data 155827 # number of demand (read+write) hits 1147system.cpu0.dcache.demand_hits::total 155827 # number of demand (read+write) hits 1148system.cpu0.dcache.overall_hits::cpu0.data 155827 # number of overall hits 1149system.cpu0.dcache.overall_hits::total 155827 # number of overall hits 1150system.cpu0.dcache.ReadReq_misses::cpu0.data 413 # number of ReadReq misses 1151system.cpu0.dcache.ReadReq_misses::total 413 # number of ReadReq misses 1152system.cpu0.dcache.WriteReq_misses::cpu0.data 543 # number of WriteReq misses 1153system.cpu0.dcache.WriteReq_misses::total 543 # number of WriteReq misses 1154system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses 1155system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses 1156system.cpu0.dcache.demand_misses::cpu0.data 956 # number of demand (read+write) misses 1157system.cpu0.dcache.demand_misses::total 956 # number of demand (read+write) misses 1158system.cpu0.dcache.overall_misses::cpu0.data 956 # number of overall misses 1159system.cpu0.dcache.overall_misses::total 956 # number of overall misses 1160system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 12955987 # number of ReadReq miss cycles 1161system.cpu0.dcache.ReadReq_miss_latency::total 12955987 # number of ReadReq miss cycles 1162system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 33432506 # number of WriteReq miss cycles 1163system.cpu0.dcache.WriteReq_miss_latency::total 33432506 # number of WriteReq miss cycles 1164system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 404750 # number of SwapReq miss cycles 1165system.cpu0.dcache.SwapReq_miss_latency::total 404750 # number of SwapReq miss cycles 1166system.cpu0.dcache.demand_miss_latency::cpu0.data 46388493 # number of demand (read+write) miss cycles 1167system.cpu0.dcache.demand_miss_latency::total 46388493 # number of demand (read+write) miss cycles 1168system.cpu0.dcache.overall_miss_latency::cpu0.data 46388493 # number of overall miss cycles 1169system.cpu0.dcache.overall_miss_latency::total 46388493 # number of overall miss cycles 1170system.cpu0.dcache.ReadReq_accesses::cpu0.data 79472 # number of ReadReq accesses(hits+misses) 1171system.cpu0.dcache.ReadReq_accesses::total 79472 # number of ReadReq accesses(hits+misses) 1172system.cpu0.dcache.WriteReq_accesses::cpu0.data 77311 # number of WriteReq accesses(hits+misses) 1173system.cpu0.dcache.WriteReq_accesses::total 77311 # number of WriteReq accesses(hits+misses) | 1139system.cpu0.dcache.tags.tag_accesses 597526 # Number of tag accesses 1140system.cpu0.dcache.tags.data_accesses 597526 # Number of data accesses 1141system.cpu0.dcache.ReadReq_hits::cpu0.data 75309 # number of ReadReq hits 1142system.cpu0.dcache.ReadReq_hits::total 75309 # number of ReadReq hits 1143system.cpu0.dcache.WriteReq_hits::cpu0.data 72924 # number of WriteReq hits 1144system.cpu0.dcache.WriteReq_hits::total 72924 # number of WriteReq hits 1145system.cpu0.dcache.SwapReq_hits::cpu0.data 20 # number of SwapReq hits 1146system.cpu0.dcache.SwapReq_hits::total 20 # number of SwapReq hits 1147system.cpu0.dcache.demand_hits::cpu0.data 148233 # number of demand (read+write) hits 1148system.cpu0.dcache.demand_hits::total 148233 # number of demand (read+write) hits 1149system.cpu0.dcache.overall_hits::cpu0.data 148233 # number of overall hits 1150system.cpu0.dcache.overall_hits::total 148233 # number of overall hits 1151system.cpu0.dcache.ReadReq_misses::cpu0.data 484 # number of ReadReq misses 1152system.cpu0.dcache.ReadReq_misses::total 484 # number of ReadReq misses 1153system.cpu0.dcache.WriteReq_misses::cpu0.data 544 # number of WriteReq misses 1154system.cpu0.dcache.WriteReq_misses::total 544 # number of WriteReq misses 1155system.cpu0.dcache.SwapReq_misses::cpu0.data 22 # number of SwapReq misses 1156system.cpu0.dcache.SwapReq_misses::total 22 # number of SwapReq misses 1157system.cpu0.dcache.demand_misses::cpu0.data 1028 # number of demand (read+write) misses 1158system.cpu0.dcache.demand_misses::total 1028 # number of demand (read+write) misses 1159system.cpu0.dcache.overall_misses::cpu0.data 1028 # number of overall misses 1160system.cpu0.dcache.overall_misses::total 1028 # number of overall misses 1161system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 15258131 # number of ReadReq miss cycles 1162system.cpu0.dcache.ReadReq_miss_latency::total 15258131 # number of ReadReq miss cycles 1163system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32871763 # number of WriteReq miss cycles 1164system.cpu0.dcache.WriteReq_miss_latency::total 32871763 # number of WriteReq miss cycles 1165system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 427750 # number of SwapReq miss cycles 1166system.cpu0.dcache.SwapReq_miss_latency::total 427750 # number of SwapReq miss cycles 1167system.cpu0.dcache.demand_miss_latency::cpu0.data 48129894 # number of demand (read+write) miss cycles 1168system.cpu0.dcache.demand_miss_latency::total 48129894 # number of demand (read+write) miss cycles 1169system.cpu0.dcache.overall_miss_latency::cpu0.data 48129894 # number of overall miss cycles 1170system.cpu0.dcache.overall_miss_latency::total 48129894 # number of overall miss cycles 1171system.cpu0.dcache.ReadReq_accesses::cpu0.data 75793 # number of ReadReq accesses(hits+misses) 1172system.cpu0.dcache.ReadReq_accesses::total 75793 # number of ReadReq accesses(hits+misses) 1173system.cpu0.dcache.WriteReq_accesses::cpu0.data 73468 # number of WriteReq accesses(hits+misses) 1174system.cpu0.dcache.WriteReq_accesses::total 73468 # number of WriteReq accesses(hits+misses) |
1174system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 1175system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) | 1175system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 1176system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) |
1176system.cpu0.dcache.demand_accesses::cpu0.data 156783 # number of demand (read+write) accesses 1177system.cpu0.dcache.demand_accesses::total 156783 # number of demand (read+write) accesses 1178system.cpu0.dcache.overall_accesses::cpu0.data 156783 # number of overall (read+write) accesses 1179system.cpu0.dcache.overall_accesses::total 156783 # number of overall (read+write) accesses 1180system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005197 # miss rate for ReadReq accesses 1181system.cpu0.dcache.ReadReq_miss_rate::total 0.005197 # miss rate for ReadReq accesses 1182system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007024 # miss rate for WriteReq accesses 1183system.cpu0.dcache.WriteReq_miss_rate::total 0.007024 # miss rate for WriteReq accesses 1184system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses 1185system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses 1186system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006098 # miss rate for demand accesses 1187system.cpu0.dcache.demand_miss_rate::total 0.006098 # miss rate for demand accesses 1188system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006098 # miss rate for overall accesses 1189system.cpu0.dcache.overall_miss_rate::total 0.006098 # miss rate for overall accesses 1190system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31370.428571 # average ReadReq miss latency 1191system.cpu0.dcache.ReadReq_avg_miss_latency::total 31370.428571 # average ReadReq miss latency 1192system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 61569.992634 # average WriteReq miss latency 1193system.cpu0.dcache.WriteReq_avg_miss_latency::total 61569.992634 # average WriteReq miss latency 1194system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19273.809524 # average SwapReq miss latency 1195system.cpu0.dcache.SwapReq_avg_miss_latency::total 19273.809524 # average SwapReq miss latency 1196system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 48523.528243 # average overall miss latency 1197system.cpu0.dcache.demand_avg_miss_latency::total 48523.528243 # average overall miss latency 1198system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 48523.528243 # average overall miss latency 1199system.cpu0.dcache.overall_avg_miss_latency::total 48523.528243 # average overall miss latency 1200system.cpu0.dcache.blocked_cycles::no_mshrs 692 # number of cycles access was blocked | 1177system.cpu0.dcache.demand_accesses::cpu0.data 149261 # number of demand (read+write) accesses 1178system.cpu0.dcache.demand_accesses::total 149261 # number of demand (read+write) accesses 1179system.cpu0.dcache.overall_accesses::cpu0.data 149261 # number of overall (read+write) accesses 1180system.cpu0.dcache.overall_accesses::total 149261 # number of overall (read+write) accesses 1181system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006386 # miss rate for ReadReq accesses 1182system.cpu0.dcache.ReadReq_miss_rate::total 0.006386 # miss rate for ReadReq accesses 1183system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007405 # miss rate for WriteReq accesses 1184system.cpu0.dcache.WriteReq_miss_rate::total 0.007405 # miss rate for WriteReq accesses 1185system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.523810 # miss rate for SwapReq accesses 1186system.cpu0.dcache.SwapReq_miss_rate::total 0.523810 # miss rate for SwapReq accesses 1187system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006887 # miss rate for demand accesses 1188system.cpu0.dcache.demand_miss_rate::total 0.006887 # miss rate for demand accesses 1189system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006887 # miss rate for overall accesses 1190system.cpu0.dcache.overall_miss_rate::total 0.006887 # miss rate for overall accesses 1191system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31525.064050 # average ReadReq miss latency 1192system.cpu0.dcache.ReadReq_avg_miss_latency::total 31525.064050 # average ReadReq miss latency 1193system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 60426.034926 # average WriteReq miss latency 1194system.cpu0.dcache.WriteReq_avg_miss_latency::total 60426.034926 # average WriteReq miss latency 1195system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19443.181818 # average SwapReq miss latency 1196system.cpu0.dcache.SwapReq_avg_miss_latency::total 19443.181818 # average SwapReq miss latency 1197system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46818.963035 # average overall miss latency 1198system.cpu0.dcache.demand_avg_miss_latency::total 46818.963035 # average overall miss latency 1199system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46818.963035 # average overall miss latency 1200system.cpu0.dcache.overall_avg_miss_latency::total 46818.963035 # average overall miss latency 1201system.cpu0.dcache.blocked_cycles::no_mshrs 754 # number of cycles access was blocked |
1201system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1202system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
1202system.cpu0.dcache.blocked::no_mshrs 24 # number of cycles access was blocked | 1203system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked |
1203system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked | 1204system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked |
1204system.cpu0.dcache.avg_blocked_cycles::no_mshrs 28.833333 # average number of cycles each access was blocked | 1205system.cpu0.dcache.avg_blocked_cycles::no_mshrs 27.925926 # average number of cycles each access was blocked |
1205system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1206system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1207system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1208system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 1209system.cpu0.dcache.writebacks::total 1 # number of writebacks | 1206system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1207system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1208system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1209system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 1210system.cpu0.dcache.writebacks::total 1 # number of writebacks |
1210system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 226 # number of ReadReq MSHR hits 1211system.cpu0.dcache.ReadReq_mshr_hits::total 226 # number of ReadReq MSHR hits 1212system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 368 # number of WriteReq MSHR hits 1213system.cpu0.dcache.WriteReq_mshr_hits::total 368 # number of WriteReq MSHR hits 1214system.cpu0.dcache.demand_mshr_hits::cpu0.data 594 # number of demand (read+write) MSHR hits 1215system.cpu0.dcache.demand_mshr_hits::total 594 # number of demand (read+write) MSHR hits 1216system.cpu0.dcache.overall_mshr_hits::cpu0.data 594 # number of overall MSHR hits 1217system.cpu0.dcache.overall_mshr_hits::total 594 # number of overall MSHR hits 1218system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 187 # number of ReadReq MSHR misses 1219system.cpu0.dcache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses 1220system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses 1221system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses 1222system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses 1223system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses | 1211system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 301 # number of ReadReq MSHR hits 1212system.cpu0.dcache.ReadReq_mshr_hits::total 301 # number of ReadReq MSHR hits 1213system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 365 # number of WriteReq MSHR hits 1214system.cpu0.dcache.WriteReq_mshr_hits::total 365 # number of WriteReq MSHR hits 1215system.cpu0.dcache.demand_mshr_hits::cpu0.data 666 # number of demand (read+write) MSHR hits 1216system.cpu0.dcache.demand_mshr_hits::total 666 # number of demand (read+write) MSHR hits 1217system.cpu0.dcache.overall_mshr_hits::cpu0.data 666 # number of overall MSHR hits 1218system.cpu0.dcache.overall_mshr_hits::total 666 # number of overall MSHR hits 1219system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 183 # number of ReadReq MSHR misses 1220system.cpu0.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses 1221system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 179 # number of WriteReq MSHR misses 1222system.cpu0.dcache.WriteReq_mshr_misses::total 179 # number of WriteReq MSHR misses 1223system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 22 # number of SwapReq MSHR misses 1224system.cpu0.dcache.SwapReq_mshr_misses::total 22 # number of SwapReq MSHR misses |
1224system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses 1225system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses 1226system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses 1227system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses | 1225system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses 1226system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses 1227system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses 1228system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses |
1228system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5995003 # number of ReadReq MSHR miss cycles 1229system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5995003 # number of ReadReq MSHR miss cycles 1230system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7531728 # number of WriteReq MSHR miss cycles 1231system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7531728 # number of WriteReq MSHR miss cycles 1232system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 361250 # number of SwapReq MSHR miss cycles 1233system.cpu0.dcache.SwapReq_mshr_miss_latency::total 361250 # number of SwapReq MSHR miss cycles 1234system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13526731 # number of demand (read+write) MSHR miss cycles 1235system.cpu0.dcache.demand_mshr_miss_latency::total 13526731 # number of demand (read+write) MSHR miss cycles 1236system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13526731 # number of overall MSHR miss cycles 1237system.cpu0.dcache.overall_mshr_miss_latency::total 13526731 # number of overall MSHR miss cycles 1238system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002353 # mshr miss rate for ReadReq accesses 1239system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002353 # mshr miss rate for ReadReq accesses 1240system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002264 # mshr miss rate for WriteReq accesses 1241system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002264 # mshr miss rate for WriteReq accesses 1242system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses 1243system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses 1244system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002309 # mshr miss rate for demand accesses 1245system.cpu0.dcache.demand_mshr_miss_rate::total 0.002309 # mshr miss rate for demand accesses 1246system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002309 # mshr miss rate for overall accesses 1247system.cpu0.dcache.overall_mshr_miss_rate::total 0.002309 # mshr miss rate for overall accesses 1248system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32058.839572 # average ReadReq mshr miss latency 1249system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32058.839572 # average ReadReq mshr miss latency 1250system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43038.445714 # average WriteReq mshr miss latency 1251system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43038.445714 # average WriteReq mshr miss latency 1252system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17202.380952 # average SwapReq mshr miss latency 1253system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17202.380952 # average SwapReq mshr miss latency 1254system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37366.660221 # average overall mshr miss latency 1255system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37366.660221 # average overall mshr miss latency 1256system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37366.660221 # average overall mshr miss latency 1257system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37366.660221 # average overall mshr miss latency | 1229system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6274260 # number of ReadReq MSHR miss cycles 1230system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6274260 # number of ReadReq MSHR miss cycles 1231system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7393227 # number of WriteReq MSHR miss cycles 1232system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7393227 # number of WriteReq MSHR miss cycles 1233system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 382250 # number of SwapReq MSHR miss cycles 1234system.cpu0.dcache.SwapReq_mshr_miss_latency::total 382250 # number of SwapReq MSHR miss cycles 1235system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13667487 # number of demand (read+write) MSHR miss cycles 1236system.cpu0.dcache.demand_mshr_miss_latency::total 13667487 # number of demand (read+write) MSHR miss cycles 1237system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13667487 # number of overall MSHR miss cycles 1238system.cpu0.dcache.overall_mshr_miss_latency::total 13667487 # number of overall MSHR miss cycles 1239system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002414 # mshr miss rate for ReadReq accesses 1240system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002414 # mshr miss rate for ReadReq accesses 1241system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002436 # mshr miss rate for WriteReq accesses 1242system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002436 # mshr miss rate for WriteReq accesses 1243system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.523810 # mshr miss rate for SwapReq accesses 1244system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.523810 # mshr miss rate for SwapReq accesses 1245system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002425 # mshr miss rate for demand accesses 1246system.cpu0.dcache.demand_mshr_miss_rate::total 0.002425 # mshr miss rate for demand accesses 1247system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002425 # mshr miss rate for overall accesses 1248system.cpu0.dcache.overall_mshr_miss_rate::total 0.002425 # mshr miss rate for overall accesses 1249system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34285.573770 # average ReadReq mshr miss latency 1250system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34285.573770 # average ReadReq mshr miss latency 1251system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41302.944134 # average WriteReq mshr miss latency 1252system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41302.944134 # average WriteReq mshr miss latency 1253system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17375 # average SwapReq mshr miss latency 1254system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17375 # average SwapReq mshr miss latency 1255system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37755.488950 # average overall mshr miss latency 1256system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37755.488950 # average overall mshr miss latency 1257system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37755.488950 # average overall mshr miss latency 1258system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37755.488950 # average overall mshr miss latency |
1258system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1259system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
1259system.cpu1.branchPred.lookups 52187 # Number of BP lookups 1260system.cpu1.branchPred.condPredicted 49510 # Number of conditional branches predicted 1261system.cpu1.branchPred.condIncorrect 1259 # Number of conditional branches incorrect 1262system.cpu1.branchPred.BTBLookups 46153 # Number of BTB lookups 1263system.cpu1.branchPred.BTBHits 45385 # Number of BTB hits | 1260system.cpu1.branchPred.lookups 54588 # Number of BP lookups 1261system.cpu1.branchPred.condPredicted 51200 # Number of conditional branches predicted 1262system.cpu1.branchPred.condIncorrect 1286 # Number of conditional branches incorrect 1263system.cpu1.branchPred.BTBLookups 47257 # Number of BTB lookups 1264system.cpu1.branchPred.BTBHits 46317 # Number of BTB hits |
1264system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1265system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
1265system.cpu1.branchPred.BTBHitPct 98.335969 # BTB Hit Percentage 1266system.cpu1.branchPred.usedRAS 643 # Number of times the RAS was used to get a target. 1267system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. 1268system.cpu1.numCycles 177799 # number of cpu cycles simulated | 1266system.cpu1.branchPred.BTBHitPct 98.010877 # BTB Hit Percentage 1267system.cpu1.branchPred.usedRAS 875 # Number of times the RAS was used to get a target. 1268system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. 1269system.cpu1.numCycles 167979 # number of cpu cycles simulated |
1269system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1270system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1270system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1271system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
1271system.cpu1.fetch.icacheStallCycles 28925 # Number of cycles fetch is stalled on an Icache miss 1272system.cpu1.fetch.Insts 291186 # Number of instructions fetch has processed 1273system.cpu1.fetch.Branches 52187 # Number of branches that fetch encountered 1274system.cpu1.fetch.predictedBranches 46028 # Number of branches that fetch has predicted taken 1275system.cpu1.fetch.Cycles 103264 # Number of cycles fetch has run and was not squashing or blocked 1276system.cpu1.fetch.SquashCycles 3653 # Number of cycles fetch has spent squashing 1277system.cpu1.fetch.BlockedCycles 32544 # Number of cycles fetch has spent blocked 1278system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1279system.cpu1.fetch.NoActiveThreadStallCycles 7803 # Number of stall cycles due to no active thread to fetch from 1280system.cpu1.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps 1281system.cpu1.fetch.CacheLines 20583 # Number of cache lines fetched 1282system.cpu1.fetch.IcacheSquashes 266 # Number of outstanding Icache misses that were squashed 1283system.cpu1.fetch.rateDist::samples 175643 # Number of instructions fetched each cycle (Total) 1284system.cpu1.fetch.rateDist::mean 1.657829 # Number of instructions fetched each cycle (Total) 1285system.cpu1.fetch.rateDist::stdev 2.130344 # Number of instructions fetched each cycle (Total) | 1272system.cpu1.fetch.icacheStallCycles 29917 # Number of cycles fetch is stalled on an Icache miss 1273system.cpu1.fetch.Insts 303462 # Number of instructions fetch has processed 1274system.cpu1.fetch.Branches 54588 # Number of branches that fetch encountered 1275system.cpu1.fetch.predictedBranches 47192 # Number of branches that fetch has predicted taken 1276system.cpu1.fetch.Cycles 126841 # Number of cycles fetch has run and was not squashing or blocked 1277system.cpu1.fetch.SquashCycles 2730 # Number of cycles fetch has spent squashing 1278system.cpu1.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1279system.cpu1.fetch.NoActiveThreadStallCycles 7060 # Number of stall cycles due to no active thread to fetch from 1280system.cpu1.fetch.PendingTrapStallCycles 1096 # Number of stall cycles due to pending traps 1281system.cpu1.fetch.CacheLines 21062 # Number of cache lines fetched 1282system.cpu1.fetch.IcacheSquashes 421 # Number of outstanding Icache misses that were squashed 1283system.cpu1.fetch.rateDist::samples 166282 # Number of instructions fetched each cycle (Total) 1284system.cpu1.fetch.rateDist::mean 1.824984 # Number of instructions fetched each cycle (Total) 1285system.cpu1.fetch.rateDist::stdev 2.191628 # Number of instructions fetched each cycle (Total) |
1286system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1286system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
1287system.cpu1.fetch.rateDist::0 72379 41.21% 41.21% # Number of instructions fetched each cycle (Total) 1288system.cpu1.fetch.rateDist::1 52711 30.01% 71.22% # Number of instructions fetched each cycle (Total) 1289system.cpu1.fetch.rateDist::2 6570 3.74% 74.96% # Number of instructions fetched each cycle (Total) 1290system.cpu1.fetch.rateDist::3 3206 1.83% 76.78% # Number of instructions fetched each cycle (Total) 1291system.cpu1.fetch.rateDist::4 681 0.39% 77.17% # Number of instructions fetched each cycle (Total) 1292system.cpu1.fetch.rateDist::5 34861 19.85% 97.02% # Number of instructions fetched each cycle (Total) 1293system.cpu1.fetch.rateDist::6 1219 0.69% 97.71% # Number of instructions fetched each cycle (Total) 1294system.cpu1.fetch.rateDist::7 754 0.43% 98.14% # Number of instructions fetched each cycle (Total) 1295system.cpu1.fetch.rateDist::8 3262 1.86% 100.00% # Number of instructions fetched each cycle (Total) | 1287system.cpu1.fetch.rateDist::0 60365 36.30% 36.30% # Number of instructions fetched each cycle (Total) 1288system.cpu1.fetch.rateDist::1 53424 32.13% 68.43% # Number of instructions fetched each cycle (Total) 1289system.cpu1.fetch.rateDist::2 6309 3.79% 72.23% # Number of instructions fetched each cycle (Total) 1290system.cpu1.fetch.rateDist::3 3483 2.09% 74.32% # Number of instructions fetched each cycle (Total) 1291system.cpu1.fetch.rateDist::4 1022 0.61% 74.93% # Number of instructions fetched each cycle (Total) 1292system.cpu1.fetch.rateDist::5 35711 21.48% 96.41% # Number of instructions fetched each cycle (Total) 1293system.cpu1.fetch.rateDist::6 1327 0.80% 97.21% # Number of instructions fetched each cycle (Total) 1294system.cpu1.fetch.rateDist::7 762 0.46% 97.67% # Number of instructions fetched each cycle (Total) 1295system.cpu1.fetch.rateDist::8 3879 2.33% 100.00% # Number of instructions fetched each cycle (Total) |
1296system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1297system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1298system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 1296system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1297system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1298system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
1299system.cpu1.fetch.rateDist::total 175643 # Number of instructions fetched each cycle (Total) 1300system.cpu1.fetch.branchRate 0.293517 # Number of branch fetches per cycle 1301system.cpu1.fetch.rate 1.637726 # Number of inst fetches per cycle 1302system.cpu1.decode.IdleCycles 34549 # Number of cycles decode is idle 1303system.cpu1.decode.BlockedCycles 28563 # Number of cycles decode is blocked 1304system.cpu1.decode.RunCycles 96884 # Number of cycles decode is running 1305system.cpu1.decode.UnblockCycles 5527 # Number of cycles decode is unblocking 1306system.cpu1.decode.SquashCycles 2317 # Number of cycles decode is squashing 1307system.cpu1.decode.DecodedInsts 287488 # Number of instructions handled by decode 1308system.cpu1.rename.SquashCycles 2317 # Number of cycles rename is squashing 1309system.cpu1.rename.IdleCycles 35238 # Number of cycles rename is idle 1310system.cpu1.rename.BlockCycles 16093 # Number of cycles rename is blocking 1311system.cpu1.rename.serializeStallCycles 11725 # count of cycles rename stalled for serializing inst 1312system.cpu1.rename.RunCycles 91623 # Number of cycles rename is running 1313system.cpu1.rename.UnblockCycles 10844 # Number of cycles rename is unblocking 1314system.cpu1.rename.RenamedInsts 285400 # Number of instructions processed by rename 1315system.cpu1.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full 1316system.cpu1.rename.RenamedOperands 199084 # Number of destination operands rename has renamed 1317system.cpu1.rename.RenameLookups 545686 # Number of register rename lookups that rename has made 1318system.cpu1.rename.int_rename_lookups 424083 # Number of integer rename lookups 1319system.cpu1.rename.CommittedMaps 186368 # Number of HB maps that are committed 1320system.cpu1.rename.UndoneMaps 12716 # Number of HB maps that are undone due to squashing 1321system.cpu1.rename.serializingInsts 1090 # count of serializing insts renamed 1322system.cpu1.rename.tempSerializingInsts 1211 # count of temporary serializing insts renamed 1323system.cpu1.rename.skidInsts 13408 # count of insts added to the skid buffer 1324system.cpu1.memDep0.insertedLoads 80706 # Number of loads inserted to the mem dependence unit. 1325system.cpu1.memDep0.insertedStores 38119 # Number of stores inserted to the mem dependence unit. 1326system.cpu1.memDep0.conflictingLoads 38742 # Number of conflicting loads. 1327system.cpu1.memDep0.conflictingStores 33075 # Number of conflicting stores. 1328system.cpu1.iq.iqInstsAdded 236041 # Number of instructions added to the IQ (excludes non-spec) 1329system.cpu1.iq.iqNonSpecInstsAdded 6768 # Number of non-speculative instructions added to the IQ 1330system.cpu1.iq.iqInstsIssued 238678 # Number of instructions issued 1331system.cpu1.iq.iqSquashedInstsIssued 59 # Number of squashed instructions issued 1332system.cpu1.iq.iqSquashedInstsExamined 10581 # Number of squashed instructions iterated over during squash; mainly for profiling 1333system.cpu1.iq.iqSquashedOperandsExamined 10451 # Number of squashed operands that are examined and possibly removed from graph 1334system.cpu1.iq.iqSquashedNonSpecRemoved 572 # Number of squashed non-spec instructions that were removed 1335system.cpu1.iq.issued_per_cycle::samples 175643 # Number of insts issued each cycle 1336system.cpu1.iq.issued_per_cycle::mean 1.358881 # Number of insts issued each cycle 1337system.cpu1.iq.issued_per_cycle::stdev 1.308073 # Number of insts issued each cycle | 1299system.cpu1.fetch.rateDist::total 166282 # Number of instructions fetched each cycle (Total) 1300system.cpu1.fetch.branchRate 0.324969 # Number of branch fetches per cycle 1301system.cpu1.fetch.rate 1.806547 # Number of inst fetches per cycle 1302system.cpu1.decode.IdleCycles 17455 # Number of cycles decode is idle 1303system.cpu1.decode.BlockedCycles 52641 # Number of cycles decode is blocked 1304system.cpu1.decode.RunCycles 84496 # Number of cycles decode is running 1305system.cpu1.decode.UnblockCycles 3265 # Number of cycles decode is unblocking 1306system.cpu1.decode.SquashCycles 1365 # Number of cycles decode is squashing 1307system.cpu1.decode.DecodedInsts 289136 # Number of instructions handled by decode 1308system.cpu1.rename.SquashCycles 1365 # Number of cycles rename is squashing 1309system.cpu1.rename.IdleCycles 18178 # Number of cycles rename is idle 1310system.cpu1.rename.BlockCycles 24205 # Number of cycles rename is blocking 1311system.cpu1.rename.serializeStallCycles 12371 # count of cycles rename stalled for serializing inst 1312system.cpu1.rename.RunCycles 85331 # Number of cycles rename is running 1313system.cpu1.rename.UnblockCycles 17772 # Number of cycles rename is unblocking 1314system.cpu1.rename.RenamedInsts 285586 # Number of instructions processed by rename 1315system.cpu1.rename.IQFullEvents 15350 # Number of times rename has blocked due to IQ full 1316system.cpu1.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full 1317system.cpu1.rename.FullRegisterEvents 3 # Number of times there has been no free registers 1318system.cpu1.rename.RenamedOperands 200979 # Number of destination operands rename has renamed 1319system.cpu1.rename.RenameLookups 548958 # Number of register rename lookups that rename has made 1320system.cpu1.rename.int_rename_lookups 426905 # Number of integer rename lookups 1321system.cpu1.rename.CommittedMaps 186309 # Number of HB maps that are committed 1322system.cpu1.rename.UndoneMaps 14670 # Number of HB maps that are undone due to squashing 1323system.cpu1.rename.serializingInsts 1186 # count of serializing insts renamed 1324system.cpu1.rename.tempSerializingInsts 1247 # count of temporary serializing insts renamed 1325system.cpu1.rename.skidInsts 22653 # count of insts added to the skid buffer 1326system.cpu1.memDep0.insertedLoads 80668 # Number of loads inserted to the mem dependence unit. 1327system.cpu1.memDep0.insertedStores 38514 # Number of stores inserted to the mem dependence unit. 1328system.cpu1.memDep0.conflictingLoads 38418 # Number of conflicting loads. 1329system.cpu1.memDep0.conflictingStores 33330 # Number of conflicting stores. 1330system.cpu1.iq.iqInstsAdded 237514 # Number of instructions added to the IQ (excludes non-spec) 1331system.cpu1.iq.iqNonSpecInstsAdded 6089 # Number of non-speculative instructions added to the IQ 1332system.cpu1.iq.iqInstsIssued 238789 # Number of instructions issued 1333system.cpu1.iq.iqSquashedInstsIssued 33 # Number of squashed instructions issued 1334system.cpu1.iq.iqSquashedInstsExamined 12748 # Number of squashed instructions iterated over during squash; mainly for profiling 1335system.cpu1.iq.iqSquashedOperandsExamined 11558 # Number of squashed operands that are examined and possibly removed from graph 1336system.cpu1.iq.iqSquashedNonSpecRemoved 612 # Number of squashed non-spec instructions that were removed 1337system.cpu1.iq.issued_per_cycle::samples 166282 # Number of insts issued each cycle 1338system.cpu1.iq.issued_per_cycle::mean 1.436048 # Number of insts issued each cycle 1339system.cpu1.iq.issued_per_cycle::stdev 1.378738 # Number of insts issued each cycle |
1338system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1340system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
1339system.cpu1.iq.issued_per_cycle::0 69713 39.69% 39.69% # Number of insts issued each cycle 1340system.cpu1.iq.issued_per_cycle::1 23816 13.56% 53.25% # Number of insts issued each cycle 1341system.cpu1.iq.issued_per_cycle::2 38346 21.83% 75.08% # Number of insts issued each cycle 1342system.cpu1.iq.issued_per_cycle::3 38982 22.19% 97.28% # Number of insts issued each cycle 1343system.cpu1.iq.issued_per_cycle::4 3247 1.85% 99.12% # Number of insts issued each cycle 1344system.cpu1.iq.issued_per_cycle::5 1165 0.66% 99.79% # Number of insts issued each cycle 1345system.cpu1.iq.issued_per_cycle::6 266 0.15% 99.94% # Number of insts issued each cycle 1346system.cpu1.iq.issued_per_cycle::7 49 0.03% 99.97% # Number of insts issued each cycle 1347system.cpu1.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle | 1341system.cpu1.iq.issued_per_cycle::0 63923 38.44% 38.44% # Number of insts issued each cycle 1342system.cpu1.iq.issued_per_cycle::1 20825 12.52% 50.97% # Number of insts issued each cycle 1343system.cpu1.iq.issued_per_cycle::2 37813 22.74% 73.71% # Number of insts issued each cycle 1344system.cpu1.iq.issued_per_cycle::3 37389 22.49% 96.19% # Number of insts issued each cycle 1345system.cpu1.iq.issued_per_cycle::4 3420 2.06% 98.25% # Number of insts issued each cycle 1346system.cpu1.iq.issued_per_cycle::5 1614 0.97% 99.22% # Number of insts issued each cycle 1347system.cpu1.iq.issued_per_cycle::6 862 0.52% 99.74% # Number of insts issued each cycle 1348system.cpu1.iq.issued_per_cycle::7 239 0.14% 99.88% # Number of insts issued each cycle 1349system.cpu1.iq.issued_per_cycle::8 197 0.12% 100.00% # Number of insts issued each cycle |
1348system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1349system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1350system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 1350system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1351system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1352system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
1351system.cpu1.iq.issued_per_cycle::total 175643 # Number of insts issued each cycle | 1353system.cpu1.iq.issued_per_cycle::total 166282 # Number of insts issued each cycle |
1352system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1354system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
1353system.cpu1.iq.fu_full::IntAlu 17 6.42% 6.42% # attempts to use FU when none available 1354system.cpu1.iq.fu_full::IntMult 0 0.00% 6.42% # attempts to use FU when none available 1355system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.42% # attempts to use FU when none available 1356system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.42% # attempts to use FU when none available 1357system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.42% # attempts to use FU when none available 1358system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.42% # attempts to use FU when none available 1359system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.42% # attempts to use FU when none available 1360system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.42% # attempts to use FU when none available 1361system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.42% # attempts to use FU when none available 1362system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.42% # attempts to use FU when none available 1363system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.42% # attempts to use FU when none available 1364system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.42% # attempts to use FU when none available 1365system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.42% # attempts to use FU when none available 1366system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.42% # attempts to use FU when none available 1367system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.42% # attempts to use FU when none available 1368system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.42% # attempts to use FU when none available 1369system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.42% # attempts to use FU when none available 1370system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.42% # attempts to use FU when none available 1371system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.42% # attempts to use FU when none available 1372system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.42% # attempts to use FU when none available 1373system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.42% # attempts to use FU when none available 1374system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.42% # attempts to use FU when none available 1375system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.42% # attempts to use FU when none available 1376system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.42% # attempts to use FU when none available 1377system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.42% # attempts to use FU when none available 1378system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.42% # attempts to use FU when none available 1379system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.42% # attempts to use FU when none available 1380system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.42% # attempts to use FU when none available 1381system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.42% # attempts to use FU when none available 1382system.cpu1.iq.fu_full::MemRead 38 14.34% 20.75% # attempts to use FU when none available 1383system.cpu1.iq.fu_full::MemWrite 210 79.25% 100.00% # attempts to use FU when none available | 1355system.cpu1.iq.fu_full::IntAlu 89 25.65% 25.65% # attempts to use FU when none available 1356system.cpu1.iq.fu_full::IntMult 0 0.00% 25.65% # attempts to use FU when none available 1357system.cpu1.iq.fu_full::IntDiv 0 0.00% 25.65% # attempts to use FU when none available 1358system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.65% # attempts to use FU when none available 1359system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.65% # attempts to use FU when none available 1360system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.65% # attempts to use FU when none available 1361system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.65% # attempts to use FU when none available 1362system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.65% # attempts to use FU when none available 1363system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.65% # attempts to use FU when none available 1364system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.65% # attempts to use FU when none available 1365system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.65% # attempts to use FU when none available 1366system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.65% # attempts to use FU when none available 1367system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.65% # attempts to use FU when none available 1368system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.65% # attempts to use FU when none available 1369system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.65% # attempts to use FU when none available 1370system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.65% # attempts to use FU when none available 1371system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.65% # attempts to use FU when none available 1372system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.65% # attempts to use FU when none available 1373system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.65% # attempts to use FU when none available 1374system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.65% # attempts to use FU when none available 1375system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.65% # attempts to use FU when none available 1376system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.65% # attempts to use FU when none available 1377system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.65% # attempts to use FU when none available 1378system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.65% # attempts to use FU when none available 1379system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.65% # attempts to use FU when none available 1380system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 25.65% # attempts to use FU when none available 1381system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.65% # attempts to use FU when none available 1382system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.65% # attempts to use FU when none available 1383system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.65% # attempts to use FU when none available 1384system.cpu1.iq.fu_full::MemRead 49 14.12% 39.77% # attempts to use FU when none available 1385system.cpu1.iq.fu_full::MemWrite 209 60.23% 100.00% # attempts to use FU when none available |
1384system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1385system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1386system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 1386system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1387system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1388system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
1387system.cpu1.iq.FU_type_0::IntAlu 115728 48.49% 48.49% # Type of FU issued 1388system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.49% # Type of FU issued 1389system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.49% # Type of FU issued 1390system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.49% # Type of FU issued 1391system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.49% # Type of FU issued 1392system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.49% # Type of FU issued 1393system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.49% # Type of FU issued 1394system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.49% # Type of FU issued 1395system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.49% # Type of FU issued 1396system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.49% # Type of FU issued 1397system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.49% # Type of FU issued 1398system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.49% # Type of FU issued 1399system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.49% # Type of FU issued 1400system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.49% # Type of FU issued 1401system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.49% # Type of FU issued 1402system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.49% # Type of FU issued 1403system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.49% # Type of FU issued 1404system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.49% # Type of FU issued 1405system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.49% # Type of FU issued 1406system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.49% # Type of FU issued 1407system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.49% # Type of FU issued 1408system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.49% # Type of FU issued 1409system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.49% # Type of FU issued 1410system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.49% # Type of FU issued 1411system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.49% # Type of FU issued 1412system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.49% # Type of FU issued 1413system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.49% # Type of FU issued 1414system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.49% # Type of FU issued 1415system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.49% # Type of FU issued 1416system.cpu1.iq.FU_type_0::MemRead 85517 35.83% 84.32% # Type of FU issued 1417system.cpu1.iq.FU_type_0::MemWrite 37433 15.68% 100.00% # Type of FU issued | 1389system.cpu1.iq.FU_type_0::IntAlu 116312 48.71% 48.71% # Type of FU issued 1390system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.71% # Type of FU issued 1391system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.71% # Type of FU issued 1392system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.71% # Type of FU issued 1393system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.71% # Type of FU issued 1394system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.71% # Type of FU issued 1395system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.71% # Type of FU issued 1396system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.71% # Type of FU issued 1397system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.71% # Type of FU issued 1398system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.71% # Type of FU issued 1399system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.71% # Type of FU issued 1400system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.71% # Type of FU issued 1401system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.71% # Type of FU issued 1402system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.71% # Type of FU issued 1403system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.71% # Type of FU issued 1404system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.71% # Type of FU issued 1405system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.71% # Type of FU issued 1406system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.71% # Type of FU issued 1407system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.71% # Type of FU issued 1408system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.71% # Type of FU issued 1409system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.71% # Type of FU issued 1410system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued 1411system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.71% # Type of FU issued 1412system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.71% # Type of FU issued 1413system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.71% # Type of FU issued 1414system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.71% # Type of FU issued 1415system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.71% # Type of FU issued 1416system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.71% # Type of FU issued 1417system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.71% # Type of FU issued 1418system.cpu1.iq.FU_type_0::MemRead 84679 35.46% 84.17% # Type of FU issued 1419system.cpu1.iq.FU_type_0::MemWrite 37798 15.83% 100.00% # Type of FU issued |
1418system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1419system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1420system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1421system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
1420system.cpu1.iq.FU_type_0::total 238678 # Type of FU issued 1421system.cpu1.iq.rate 1.342404 # Inst issue rate 1422system.cpu1.iq.fu_busy_cnt 265 # FU busy when requested 1423system.cpu1.iq.fu_busy_rate 0.001110 # FU busy rate (busy events/executed inst) 1424system.cpu1.iq.int_inst_queue_reads 653323 # Number of integer instruction queue reads 1425system.cpu1.iq.int_inst_queue_writes 253430 # Number of integer instruction queue writes 1426system.cpu1.iq.int_inst_queue_wakeup_accesses 236861 # Number of integer instruction queue wakeup accesses | 1422system.cpu1.iq.FU_type_0::total 238789 # Type of FU issued 1423system.cpu1.iq.rate 1.421541 # Inst issue rate 1424system.cpu1.iq.fu_busy_cnt 347 # FU busy when requested 1425system.cpu1.iq.fu_busy_rate 0.001453 # FU busy rate (busy events/executed inst) 1426system.cpu1.iq.int_inst_queue_reads 644240 # Number of integer instruction queue reads 1427system.cpu1.iq.int_inst_queue_writes 256392 # Number of integer instruction queue writes 1428system.cpu1.iq.int_inst_queue_wakeup_accesses 237045 # Number of integer instruction queue wakeup accesses |
1427system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1428system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1429system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 1429system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1430system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1431system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
1430system.cpu1.iq.int_alu_accesses 238943 # Number of integer alu accesses | 1432system.cpu1.iq.int_alu_accesses 239136 # Number of integer alu accesses |
1431system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses | 1433system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses |
1432system.cpu1.iew.lsq.thread0.forwLoads 32850 # Number of loads that had data forwarded from stores | 1434system.cpu1.iew.lsq.thread0.forwLoads 33095 # Number of loads that had data forwarded from stores |
1433system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 1435system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
1434system.cpu1.iew.lsq.thread0.squashedLoads 2336 # Number of loads squashed | 1436system.cpu1.iew.lsq.thread0.squashedLoads 2693 # Number of loads squashed |
1435system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed | 1437system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed |
1436system.cpu1.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations 1437system.cpu1.iew.lsq.thread0.squashedStores 1422 # Number of stores squashed | 1438system.cpu1.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations 1439system.cpu1.iew.lsq.thread0.squashedStores 1647 # Number of stores squashed |
1438system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1439system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1440system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1441system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1442system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 1440system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1441system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1442system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1443system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1444system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
1443system.cpu1.iew.iewSquashCycles 2317 # Number of cycles IEW is squashing 1444system.cpu1.iew.iewBlockCycles 666 # Number of cycles IEW is blocking 1445system.cpu1.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking 1446system.cpu1.iew.iewDispatchedInsts 282498 # Number of instructions dispatched to IQ 1447system.cpu1.iew.iewDispSquashedInsts 328 # Number of squashed instructions skipped by dispatch 1448system.cpu1.iew.iewDispLoadInsts 80706 # Number of dispatched load instructions 1449system.cpu1.iew.iewDispStoreInsts 38119 # Number of dispatched store instructions 1450system.cpu1.iew.iewDispNonSpecInsts 1050 # Number of dispatched non-speculative instructions 1451system.cpu1.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall | 1445system.cpu1.iew.iewSquashCycles 1365 # Number of cycles IEW is squashing 1446system.cpu1.iew.iewBlockCycles 6579 # Number of cycles IEW is blocking 1447system.cpu1.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking 1448system.cpu1.iew.iewDispatchedInsts 282823 # Number of instructions dispatched to IQ 1449system.cpu1.iew.iewDispSquashedInsts 167 # Number of squashed instructions skipped by dispatch 1450system.cpu1.iew.iewDispLoadInsts 80668 # Number of dispatched load instructions 1451system.cpu1.iew.iewDispStoreInsts 38514 # Number of dispatched store instructions 1452system.cpu1.iew.iewDispNonSpecInsts 1105 # Number of dispatched non-speculative instructions 1453system.cpu1.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall |
1452system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall | 1454system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall |
1453system.cpu1.iew.memOrderViolationEvents 40 # Number of memory order violations 1454system.cpu1.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly 1455system.cpu1.iew.predictedNotTakenIncorrect 907 # Number of branches that were predicted not taken incorrectly 1456system.cpu1.iew.branchMispredicts 1372 # Number of branch mispredicts detected at execute 1457system.cpu1.iew.iewExecutedInsts 237512 # Number of executed instructions 1458system.cpu1.iew.iewExecLoadInsts 79760 # Number of load instructions executed 1459system.cpu1.iew.iewExecSquashedInsts 1166 # Number of squashed instructions skipped in execute | 1455system.cpu1.iew.memOrderViolationEvents 41 # Number of memory order violations 1456system.cpu1.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly 1457system.cpu1.iew.predictedNotTakenIncorrect 1037 # Number of branches that were predicted not taken incorrectly 1458system.cpu1.iew.branchMispredicts 1507 # Number of branch mispredicts detected at execute 1459system.cpu1.iew.iewExecutedInsts 237631 # Number of executed instructions 1460system.cpu1.iew.iewExecLoadInsts 79596 # Number of load instructions executed 1461system.cpu1.iew.iewExecSquashedInsts 1158 # Number of squashed instructions skipped in execute |
1460system.cpu1.iew.exec_swp 0 # number of swp insts executed | 1462system.cpu1.iew.exec_swp 0 # number of swp insts executed |
1461system.cpu1.iew.exec_nop 39689 # number of nop insts executed 1462system.cpu1.iew.exec_refs 117113 # number of memory reference insts executed 1463system.cpu1.iew.exec_branches 48963 # Number of branches executed 1464system.cpu1.iew.exec_stores 37353 # Number of stores executed 1465system.cpu1.iew.exec_rate 1.335846 # Inst execution rate 1466system.cpu1.iew.wb_sent 237151 # cumulative count of insts sent to commit 1467system.cpu1.iew.wb_count 236861 # cumulative count of insts written-back 1468system.cpu1.iew.wb_producers 133843 # num instructions producing a value 1469system.cpu1.iew.wb_consumers 138503 # num instructions consuming a value | 1463system.cpu1.iew.exec_nop 39220 # number of nop insts executed 1464system.cpu1.iew.exec_refs 117284 # number of memory reference insts executed 1465system.cpu1.iew.exec_branches 48640 # Number of branches executed 1466system.cpu1.iew.exec_stores 37688 # Number of stores executed 1467system.cpu1.iew.exec_rate 1.414647 # Inst execution rate 1468system.cpu1.iew.wb_sent 237349 # cumulative count of insts sent to commit 1469system.cpu1.iew.wb_count 237045 # cumulative count of insts written-back 1470system.cpu1.iew.wb_producers 134973 # num instructions producing a value 1471system.cpu1.iew.wb_consumers 141559 # num instructions consuming a value |
1470system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1472system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
1471system.cpu1.iew.wb_rate 1.332184 # insts written-back per cycle 1472system.cpu1.iew.wb_fanout 0.966355 # average fanout of values written-back | 1473system.cpu1.iew.wb_rate 1.411159 # insts written-back per cycle 1474system.cpu1.iew.wb_fanout 0.953475 # average fanout of values written-back |
1473system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 1475system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
1474system.cpu1.commit.commitSquashedInsts 12124 # The number of squashed insts skipped by commit 1475system.cpu1.commit.commitNonSpecStalls 6196 # The number of times commit has been forced to stall to communicate backwards 1476system.cpu1.commit.branchMispredicts 1259 # The number of times a branch was mispredicted 1477system.cpu1.commit.committed_per_cycle::samples 165523 # Number of insts commited each cycle 1478system.cpu1.commit.committed_per_cycle::mean 1.633344 # Number of insts commited each cycle 1479system.cpu1.commit.committed_per_cycle::stdev 2.016153 # Number of insts commited each cycle | 1476system.cpu1.commit.commitSquashedInsts 14310 # The number of squashed insts skipped by commit 1477system.cpu1.commit.commitNonSpecStalls 5477 # The number of times commit has been forced to stall to communicate backwards 1478system.cpu1.commit.branchMispredicts 1286 # The number of times a branch was mispredicted 1479system.cpu1.commit.committed_per_cycle::samples 156616 # Number of insts commited each cycle 1480system.cpu1.commit.committed_per_cycle::mean 1.714129 # Number of insts commited each cycle 1481system.cpu1.commit.committed_per_cycle::stdev 2.075319 # Number of insts commited each cycle |
1480system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 1482system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
1481system.cpu1.commit.committed_per_cycle::0 67946 41.05% 41.05% # Number of insts commited each cycle 1482system.cpu1.commit.committed_per_cycle::1 47096 28.45% 69.50% # Number of insts commited each cycle 1483system.cpu1.commit.committed_per_cycle::2 6082 3.67% 73.18% # Number of insts commited each cycle 1484system.cpu1.commit.committed_per_cycle::3 7142 4.31% 77.49% # Number of insts commited each cycle 1485system.cpu1.commit.committed_per_cycle::4 1575 0.95% 78.44% # Number of insts commited each cycle 1486system.cpu1.commit.committed_per_cycle::5 33355 20.15% 98.59% # Number of insts commited each cycle 1487system.cpu1.commit.committed_per_cycle::6 510 0.31% 98.90% # Number of insts commited each cycle 1488system.cpu1.commit.committed_per_cycle::7 1001 0.60% 99.51% # Number of insts commited each cycle 1489system.cpu1.commit.committed_per_cycle::8 816 0.49% 100.00% # Number of insts commited each cycle | 1483system.cpu1.commit.committed_per_cycle::0 61979 39.57% 39.57% # Number of insts commited each cycle 1484system.cpu1.commit.committed_per_cycle::1 45369 28.97% 68.54% # Number of insts commited each cycle 1485system.cpu1.commit.committed_per_cycle::2 5243 3.35% 71.89% # Number of insts commited each cycle 1486system.cpu1.commit.committed_per_cycle::3 6285 4.01% 75.90% # Number of insts commited each cycle 1487system.cpu1.commit.committed_per_cycle::4 1549 0.99% 76.89% # Number of insts commited each cycle 1488system.cpu1.commit.committed_per_cycle::5 33128 21.15% 98.04% # Number of insts commited each cycle 1489system.cpu1.commit.committed_per_cycle::6 818 0.52% 98.57% # Number of insts commited each cycle 1490system.cpu1.commit.committed_per_cycle::7 954 0.61% 99.18% # Number of insts commited each cycle 1491system.cpu1.commit.committed_per_cycle::8 1291 0.82% 100.00% # Number of insts commited each cycle |
1490system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1491system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1492system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 1492system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1493system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1494system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
1493system.cpu1.commit.committed_per_cycle::total 165523 # Number of insts commited each cycle 1494system.cpu1.commit.committedInsts 270356 # Number of instructions committed 1495system.cpu1.commit.committedOps 270356 # Number of ops (including micro ops) committed | 1495system.cpu1.commit.committed_per_cycle::total 156616 # Number of insts commited each cycle 1496system.cpu1.commit.committedInsts 268460 # Number of instructions committed 1497system.cpu1.commit.committedOps 268460 # Number of ops (including micro ops) committed |
1496system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed | 1498system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed |
1497system.cpu1.commit.refs 115067 # Number of memory references committed 1498system.cpu1.commit.loads 78370 # Number of loads committed 1499system.cpu1.commit.membars 5484 # Number of memory barriers committed 1500system.cpu1.commit.branches 48146 # Number of branches committed | 1499system.cpu1.commit.refs 114842 # Number of memory references committed 1500system.cpu1.commit.loads 77975 # Number of loads committed 1501system.cpu1.commit.membars 4761 # Number of memory barriers committed 1502system.cpu1.commit.branches 47591 # Number of branches committed |
1501system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. | 1503system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. |
1502system.cpu1.commit.int_insts 185335 # Number of committed integer instructions. | 1504system.cpu1.commit.int_insts 184553 # Number of committed integer instructions. |
1503system.cpu1.commit.function_calls 322 # Number of function calls committed. | 1505system.cpu1.commit.function_calls 322 # Number of function calls committed. |
1504system.cpu1.commit.op_class_0::No_OpClass 38938 14.40% 14.40% # Class of committed instruction 1505system.cpu1.commit.op_class_0::IntAlu 110867 41.01% 55.41% # Class of committed instruction 1506system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.41% # Class of committed instruction 1507system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.41% # Class of committed instruction 1508system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.41% # Class of committed instruction 1509system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.41% # Class of committed instruction 1510system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.41% # Class of committed instruction 1511system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.41% # Class of committed instruction 1512system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.41% # Class of committed instruction 1513system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.41% # Class of committed instruction 1514system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.41% # Class of committed instruction 1515system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.41% # Class of committed instruction 1516system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.41% # Class of committed instruction 1517system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.41% # Class of committed instruction 1518system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.41% # Class of committed instruction 1519system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.41% # Class of committed instruction 1520system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.41% # Class of committed instruction 1521system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.41% # Class of committed instruction 1522system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.41% # Class of committed instruction 1523system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.41% # Class of committed instruction 1524system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.41% # Class of committed instruction 1525system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.41% # Class of committed instruction 1526system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.41% # Class of committed instruction 1527system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.41% # Class of committed instruction 1528system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.41% # Class of committed instruction 1529system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.41% # Class of committed instruction 1530system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.41% # Class of committed instruction 1531system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.41% # Class of committed instruction 1532system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.41% # Class of committed instruction 1533system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.41% # Class of committed instruction 1534system.cpu1.commit.op_class_0::MemRead 83854 31.02% 86.43% # Class of committed instruction 1535system.cpu1.commit.op_class_0::MemWrite 36697 13.57% 100.00% # Class of committed instruction | 1506system.cpu1.commit.op_class_0::No_OpClass 38379 14.30% 14.30% # Class of committed instruction 1507system.cpu1.commit.op_class_0::IntAlu 110478 41.15% 55.45% # Class of committed instruction 1508system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.45% # Class of committed instruction 1509system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.45% # Class of committed instruction 1510system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.45% # Class of committed instruction 1511system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.45% # Class of committed instruction 1512system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.45% # Class of committed instruction 1513system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.45% # Class of committed instruction 1514system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.45% # Class of committed instruction 1515system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.45% # Class of committed instruction 1516system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.45% # Class of committed instruction 1517system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.45% # Class of committed instruction 1518system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.45% # Class of committed instruction 1519system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.45% # Class of committed instruction 1520system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.45% # Class of committed instruction 1521system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.45% # Class of committed instruction 1522system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.45% # Class of committed instruction 1523system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.45% # Class of committed instruction 1524system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.45% # Class of committed instruction 1525system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.45% # Class of committed instruction 1526system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.45% # Class of committed instruction 1527system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.45% # Class of committed instruction 1528system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.45% # Class of committed instruction 1529system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.45% # Class of committed instruction 1530system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.45% # Class of committed instruction 1531system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.45% # Class of committed instruction 1532system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.45% # Class of committed instruction 1533system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.45% # Class of committed instruction 1534system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.45% # Class of committed instruction 1535system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.45% # Class of committed instruction 1536system.cpu1.commit.op_class_0::MemRead 82736 30.82% 86.27% # Class of committed instruction 1537system.cpu1.commit.op_class_0::MemWrite 36867 13.73% 100.00% # Class of committed instruction |
1536system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1537system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 1538system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1539system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
1538system.cpu1.commit.op_class_0::total 270356 # Class of committed instruction 1539system.cpu1.commit.bw_lim_events 816 # number cycles where commit BW limit reached | 1540system.cpu1.commit.op_class_0::total 268460 # Class of committed instruction 1541system.cpu1.commit.bw_lim_events 1291 # number cycles where commit BW limit reached |
1540system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits | 1542system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits |
1541system.cpu1.rob.rob_reads 446600 # The number of ROB reads 1542system.cpu1.rob.rob_writes 567283 # The number of ROB writes 1543system.cpu1.timesIdled 213 # Number of times that the entire CPU went into an idle state and unscheduled itself 1544system.cpu1.idleCycles 2156 # Total number of cycles that the CPU has spent unscheduled due to idling 1545system.cpu1.quiesceCycles 44141 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1546system.cpu1.committedInsts 225934 # Number of Instructions Simulated 1547system.cpu1.committedOps 225934 # Number of Ops (including micro ops) Simulated 1548system.cpu1.cpi 0.786951 # CPI: Cycles Per Instruction 1549system.cpu1.cpi_total 0.786951 # CPI: Total CPI of All Threads 1550system.cpu1.ipc 1.270727 # IPC: Instructions Per Cycle 1551system.cpu1.ipc_total 1.270727 # IPC: Total IPC of All Threads 1552system.cpu1.int_regfile_reads 409872 # number of integer regfile reads 1553system.cpu1.int_regfile_writes 191136 # number of integer regfile writes | 1543system.cpu1.rob.rob_reads 437508 # The number of ROB reads 1544system.cpu1.rob.rob_writes 568153 # The number of ROB writes 1545system.cpu1.timesIdled 207 # Number of times that the entire CPU went into an idle state and unscheduled itself 1546system.cpu1.idleCycles 1697 # Total number of cycles that the CPU has spent unscheduled due to idling 1547system.cpu1.quiesceCycles 43298 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1548system.cpu1.committedInsts 225320 # Number of Instructions Simulated 1549system.cpu1.committedOps 225320 # Number of Ops (including micro ops) Simulated 1550system.cpu1.cpi 0.745513 # CPI: Cycles Per Instruction 1551system.cpu1.cpi_total 0.745513 # CPI: Total CPI of All Threads 1552system.cpu1.ipc 1.341358 # IPC: Instructions Per Cycle 1553system.cpu1.ipc_total 1.341358 # IPC: Total IPC of All Threads 1554system.cpu1.int_regfile_reads 411671 # number of integer regfile reads 1555system.cpu1.int_regfile_writes 192443 # number of integer regfile writes |
1554system.cpu1.fp_regfile_writes 64 # number of floating regfile writes | 1556system.cpu1.fp_regfile_writes 64 # number of floating regfile writes |
1555system.cpu1.misc_regfile_reads 118682 # number of misc regfile reads | 1557system.cpu1.misc_regfile_reads 118908 # number of misc regfile reads |
1556system.cpu1.misc_regfile_writes 648 # number of misc regfile writes | 1558system.cpu1.misc_regfile_writes 648 # number of misc regfile writes |
1557system.cpu1.icache.tags.replacements 318 # number of replacements 1558system.cpu1.icache.tags.tagsinuse 79.885573 # Cycle average of tags in use 1559system.cpu1.icache.tags.total_refs 20107 # Total number of references to valid blocks. 1560system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks. 1561system.cpu1.icache.tags.avg_refs 46.978972 # Average number of references to valid blocks. | 1559system.cpu1.icache.tags.replacements 388 # number of replacements 1560system.cpu1.icache.tags.tagsinuse 78.688259 # Cycle average of tags in use 1561system.cpu1.icache.tags.total_refs 20497 # Total number of references to valid blocks. 1562system.cpu1.icache.tags.sampled_refs 497 # Sample count of references to valid blocks. 1563system.cpu1.icache.tags.avg_refs 41.241449 # Average number of references to valid blocks. |
1562system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1564system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
1563system.cpu1.icache.tags.occ_blocks::cpu1.inst 79.885573 # Average occupied blocks per requestor 1564system.cpu1.icache.tags.occ_percent::cpu1.inst 0.156027 # Average percentage of cache occupancy 1565system.cpu1.icache.tags.occ_percent::total 0.156027 # Average percentage of cache occupancy 1566system.cpu1.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id 1567system.cpu1.icache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id 1568system.cpu1.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id 1569system.cpu1.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id 1570system.cpu1.icache.tags.tag_accesses 21011 # Number of tag accesses 1571system.cpu1.icache.tags.data_accesses 21011 # Number of data accesses 1572system.cpu1.icache.ReadReq_hits::cpu1.inst 20107 # number of ReadReq hits 1573system.cpu1.icache.ReadReq_hits::total 20107 # number of ReadReq hits 1574system.cpu1.icache.demand_hits::cpu1.inst 20107 # number of demand (read+write) hits 1575system.cpu1.icache.demand_hits::total 20107 # number of demand (read+write) hits 1576system.cpu1.icache.overall_hits::cpu1.inst 20107 # number of overall hits 1577system.cpu1.icache.overall_hits::total 20107 # number of overall hits 1578system.cpu1.icache.ReadReq_misses::cpu1.inst 476 # number of ReadReq misses 1579system.cpu1.icache.ReadReq_misses::total 476 # number of ReadReq misses 1580system.cpu1.icache.demand_misses::cpu1.inst 476 # number of demand (read+write) misses 1581system.cpu1.icache.demand_misses::total 476 # number of demand (read+write) misses 1582system.cpu1.icache.overall_misses::cpu1.inst 476 # number of overall misses 1583system.cpu1.icache.overall_misses::total 476 # number of overall misses 1584system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7353244 # number of ReadReq miss cycles 1585system.cpu1.icache.ReadReq_miss_latency::total 7353244 # number of ReadReq miss cycles 1586system.cpu1.icache.demand_miss_latency::cpu1.inst 7353244 # number of demand (read+write) miss cycles 1587system.cpu1.icache.demand_miss_latency::total 7353244 # number of demand (read+write) miss cycles 1588system.cpu1.icache.overall_miss_latency::cpu1.inst 7353244 # number of overall miss cycles 1589system.cpu1.icache.overall_miss_latency::total 7353244 # number of overall miss cycles 1590system.cpu1.icache.ReadReq_accesses::cpu1.inst 20583 # number of ReadReq accesses(hits+misses) 1591system.cpu1.icache.ReadReq_accesses::total 20583 # number of ReadReq accesses(hits+misses) 1592system.cpu1.icache.demand_accesses::cpu1.inst 20583 # number of demand (read+write) accesses 1593system.cpu1.icache.demand_accesses::total 20583 # number of demand (read+write) accesses 1594system.cpu1.icache.overall_accesses::cpu1.inst 20583 # number of overall (read+write) accesses 1595system.cpu1.icache.overall_accesses::total 20583 # number of overall (read+write) accesses 1596system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023126 # miss rate for ReadReq accesses 1597system.cpu1.icache.ReadReq_miss_rate::total 0.023126 # miss rate for ReadReq accesses 1598system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023126 # miss rate for demand accesses 1599system.cpu1.icache.demand_miss_rate::total 0.023126 # miss rate for demand accesses 1600system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023126 # miss rate for overall accesses 1601system.cpu1.icache.overall_miss_rate::total 0.023126 # miss rate for overall accesses 1602system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15447.991597 # average ReadReq miss latency 1603system.cpu1.icache.ReadReq_avg_miss_latency::total 15447.991597 # average ReadReq miss latency 1604system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15447.991597 # average overall miss latency 1605system.cpu1.icache.demand_avg_miss_latency::total 15447.991597 # average overall miss latency 1606system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15447.991597 # average overall miss latency 1607system.cpu1.icache.overall_avg_miss_latency::total 15447.991597 # average overall miss latency 1608system.cpu1.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked | 1565system.cpu1.icache.tags.occ_blocks::cpu1.inst 78.688259 # Average occupied blocks per requestor 1566system.cpu1.icache.tags.occ_percent::cpu1.inst 0.153688 # Average percentage of cache occupancy 1567system.cpu1.icache.tags.occ_percent::total 0.153688 # Average percentage of cache occupancy 1568system.cpu1.icache.tags.occ_task_id_blocks::1024 109 # Occupied blocks per task id 1569system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 1570system.cpu1.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id 1571system.cpu1.icache.tags.occ_task_id_percent::1024 0.212891 # Percentage of cache occupancy per task id 1572system.cpu1.icache.tags.tag_accesses 21559 # Number of tag accesses 1573system.cpu1.icache.tags.data_accesses 21559 # Number of data accesses 1574system.cpu1.icache.ReadReq_hits::cpu1.inst 20497 # number of ReadReq hits 1575system.cpu1.icache.ReadReq_hits::total 20497 # number of ReadReq hits 1576system.cpu1.icache.demand_hits::cpu1.inst 20497 # number of demand (read+write) hits 1577system.cpu1.icache.demand_hits::total 20497 # number of demand (read+write) hits 1578system.cpu1.icache.overall_hits::cpu1.inst 20497 # number of overall hits 1579system.cpu1.icache.overall_hits::total 20497 # number of overall hits 1580system.cpu1.icache.ReadReq_misses::cpu1.inst 565 # number of ReadReq misses 1581system.cpu1.icache.ReadReq_misses::total 565 # number of ReadReq misses 1582system.cpu1.icache.demand_misses::cpu1.inst 565 # number of demand (read+write) misses 1583system.cpu1.icache.demand_misses::total 565 # number of demand (read+write) misses 1584system.cpu1.icache.overall_misses::cpu1.inst 565 # number of overall misses 1585system.cpu1.icache.overall_misses::total 565 # number of overall misses 1586system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8463744 # number of ReadReq miss cycles 1587system.cpu1.icache.ReadReq_miss_latency::total 8463744 # number of ReadReq miss cycles 1588system.cpu1.icache.demand_miss_latency::cpu1.inst 8463744 # number of demand (read+write) miss cycles 1589system.cpu1.icache.demand_miss_latency::total 8463744 # number of demand (read+write) miss cycles 1590system.cpu1.icache.overall_miss_latency::cpu1.inst 8463744 # number of overall miss cycles 1591system.cpu1.icache.overall_miss_latency::total 8463744 # number of overall miss cycles 1592system.cpu1.icache.ReadReq_accesses::cpu1.inst 21062 # number of ReadReq accesses(hits+misses) 1593system.cpu1.icache.ReadReq_accesses::total 21062 # number of ReadReq accesses(hits+misses) 1594system.cpu1.icache.demand_accesses::cpu1.inst 21062 # number of demand (read+write) accesses 1595system.cpu1.icache.demand_accesses::total 21062 # number of demand (read+write) accesses 1596system.cpu1.icache.overall_accesses::cpu1.inst 21062 # number of overall (read+write) accesses 1597system.cpu1.icache.overall_accesses::total 21062 # number of overall (read+write) accesses 1598system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.026826 # miss rate for ReadReq accesses 1599system.cpu1.icache.ReadReq_miss_rate::total 0.026826 # miss rate for ReadReq accesses 1600system.cpu1.icache.demand_miss_rate::cpu1.inst 0.026826 # miss rate for demand accesses 1601system.cpu1.icache.demand_miss_rate::total 0.026826 # miss rate for demand accesses 1602system.cpu1.icache.overall_miss_rate::cpu1.inst 0.026826 # miss rate for overall accesses 1603system.cpu1.icache.overall_miss_rate::total 0.026826 # miss rate for overall accesses 1604system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14980.077876 # average ReadReq miss latency 1605system.cpu1.icache.ReadReq_avg_miss_latency::total 14980.077876 # average ReadReq miss latency 1606system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14980.077876 # average overall miss latency 1607system.cpu1.icache.demand_avg_miss_latency::total 14980.077876 # average overall miss latency 1608system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14980.077876 # average overall miss latency 1609system.cpu1.icache.overall_avg_miss_latency::total 14980.077876 # average overall miss latency 1610system.cpu1.icache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked |
1609system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1611system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
1610system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked | 1612system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked |
1611system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked | 1613system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked |
1612system.cpu1.icache.avg_blocked_cycles::no_mshrs 13 # average number of cycles each access was blocked | 1614system.cpu1.icache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked |
1613system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1614system.cpu1.icache.fast_writes 0 # number of fast writes performed 1615system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1615system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1616system.cpu1.icache.fast_writes 0 # number of fast writes performed 1617system.cpu1.icache.cache_copies 0 # number of cache copies performed |
1616system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 48 # number of ReadReq MSHR hits 1617system.cpu1.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits 1618system.cpu1.icache.demand_mshr_hits::cpu1.inst 48 # number of demand (read+write) MSHR hits 1619system.cpu1.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits 1620system.cpu1.icache.overall_mshr_hits::cpu1.inst 48 # number of overall MSHR hits 1621system.cpu1.icache.overall_mshr_hits::total 48 # number of overall MSHR hits 1622system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 428 # number of ReadReq MSHR misses 1623system.cpu1.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses 1624system.cpu1.icache.demand_mshr_misses::cpu1.inst 428 # number of demand (read+write) MSHR misses 1625system.cpu1.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses 1626system.cpu1.icache.overall_mshr_misses::cpu1.inst 428 # number of overall MSHR misses 1627system.cpu1.icache.overall_mshr_misses::total 428 # number of overall MSHR misses 1628system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5927255 # number of ReadReq MSHR miss cycles 1629system.cpu1.icache.ReadReq_mshr_miss_latency::total 5927255 # number of ReadReq MSHR miss cycles 1630system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5927255 # number of demand (read+write) MSHR miss cycles 1631system.cpu1.icache.demand_mshr_miss_latency::total 5927255 # number of demand (read+write) MSHR miss cycles 1632system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5927255 # number of overall MSHR miss cycles 1633system.cpu1.icache.overall_mshr_miss_latency::total 5927255 # number of overall MSHR miss cycles 1634system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.020794 # mshr miss rate for ReadReq accesses 1635system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.020794 # mshr miss rate for ReadReq accesses 1636system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.020794 # mshr miss rate for demand accesses 1637system.cpu1.icache.demand_mshr_miss_rate::total 0.020794 # mshr miss rate for demand accesses 1638system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.020794 # mshr miss rate for overall accesses 1639system.cpu1.icache.overall_mshr_miss_rate::total 0.020794 # mshr miss rate for overall accesses 1640system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13848.726636 # average ReadReq mshr miss latency 1641system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13848.726636 # average ReadReq mshr miss latency 1642system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13848.726636 # average overall mshr miss latency 1643system.cpu1.icache.demand_avg_mshr_miss_latency::total 13848.726636 # average overall mshr miss latency 1644system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13848.726636 # average overall mshr miss latency 1645system.cpu1.icache.overall_avg_mshr_miss_latency::total 13848.726636 # average overall mshr miss latency | 1618system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 68 # number of ReadReq MSHR hits 1619system.cpu1.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits 1620system.cpu1.icache.demand_mshr_hits::cpu1.inst 68 # number of demand (read+write) MSHR hits 1621system.cpu1.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits 1622system.cpu1.icache.overall_mshr_hits::cpu1.inst 68 # number of overall MSHR hits 1623system.cpu1.icache.overall_mshr_hits::total 68 # number of overall MSHR hits 1624system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 497 # number of ReadReq MSHR misses 1625system.cpu1.icache.ReadReq_mshr_misses::total 497 # number of ReadReq MSHR misses 1626system.cpu1.icache.demand_mshr_misses::cpu1.inst 497 # number of demand (read+write) MSHR misses 1627system.cpu1.icache.demand_mshr_misses::total 497 # number of demand (read+write) MSHR misses 1628system.cpu1.icache.overall_mshr_misses::cpu1.inst 497 # number of overall MSHR misses 1629system.cpu1.icache.overall_mshr_misses::total 497 # number of overall MSHR misses 1630system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6616756 # number of ReadReq MSHR miss cycles 1631system.cpu1.icache.ReadReq_mshr_miss_latency::total 6616756 # number of ReadReq MSHR miss cycles 1632system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6616756 # number of demand (read+write) MSHR miss cycles 1633system.cpu1.icache.demand_mshr_miss_latency::total 6616756 # number of demand (read+write) MSHR miss cycles 1634system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6616756 # number of overall MSHR miss cycles 1635system.cpu1.icache.overall_mshr_miss_latency::total 6616756 # number of overall MSHR miss cycles 1636system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023597 # mshr miss rate for ReadReq accesses 1637system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023597 # mshr miss rate for ReadReq accesses 1638system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023597 # mshr miss rate for demand accesses 1639system.cpu1.icache.demand_mshr_miss_rate::total 0.023597 # mshr miss rate for demand accesses 1640system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023597 # mshr miss rate for overall accesses 1641system.cpu1.icache.overall_mshr_miss_rate::total 0.023597 # mshr miss rate for overall accesses 1642system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13313.392354 # average ReadReq mshr miss latency 1643system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13313.392354 # average ReadReq mshr miss latency 1644system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13313.392354 # average overall mshr miss latency 1645system.cpu1.icache.demand_avg_mshr_miss_latency::total 13313.392354 # average overall mshr miss latency 1646system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13313.392354 # average overall mshr miss latency 1647system.cpu1.icache.overall_avg_mshr_miss_latency::total 13313.392354 # average overall mshr miss latency |
1646system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1647system.cpu1.dcache.tags.replacements 0 # number of replacements | 1648system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1649system.cpu1.dcache.tags.replacements 0 # number of replacements |
1648system.cpu1.dcache.tags.tagsinuse 24.706566 # Cycle average of tags in use 1649system.cpu1.dcache.tags.total_refs 42694 # Total number of references to valid blocks. 1650system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. 1651system.cpu1.dcache.tags.avg_refs 1524.785714 # Average number of references to valid blocks. | 1650system.cpu1.dcache.tags.tagsinuse 24.399537 # Cycle average of tags in use 1651system.cpu1.dcache.tags.total_refs 43036 # Total number of references to valid blocks. 1652system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 1653system.cpu1.dcache.tags.avg_refs 1484 # Average number of references to valid blocks. |
1652system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1654system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
1653system.cpu1.dcache.tags.occ_blocks::cpu1.data 24.706566 # Average occupied blocks per requestor 1654system.cpu1.dcache.tags.occ_percent::cpu1.data 0.048255 # Average percentage of cache occupancy 1655system.cpu1.dcache.tags.occ_percent::total 0.048255 # Average percentage of cache occupancy 1656system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id | 1655system.cpu1.dcache.tags.occ_blocks::cpu1.data 24.399537 # Average occupied blocks per requestor 1656system.cpu1.dcache.tags.occ_percent::cpu1.data 0.047655 # Average percentage of cache occupancy 1657system.cpu1.dcache.tags.occ_percent::total 0.047655 # Average percentage of cache occupancy 1658system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 1659system.cpu1.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id |
1657system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id | 1660system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id |
1658system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id 1659system.cpu1.dcache.tags.tag_accesses 334614 # Number of tag accesses 1660system.cpu1.dcache.tags.data_accesses 334614 # Number of data accesses 1661system.cpu1.dcache.ReadReq_hits::cpu1.data 46543 # number of ReadReq hits 1662system.cpu1.dcache.ReadReq_hits::total 46543 # number of ReadReq hits 1663system.cpu1.dcache.WriteReq_hits::cpu1.data 36491 # number of WriteReq hits 1664system.cpu1.dcache.WriteReq_hits::total 36491 # number of WriteReq hits 1665system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits 1666system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits 1667system.cpu1.dcache.demand_hits::cpu1.data 83034 # number of demand (read+write) hits 1668system.cpu1.dcache.demand_hits::total 83034 # number of demand (read+write) hits 1669system.cpu1.dcache.overall_hits::cpu1.data 83034 # number of overall hits 1670system.cpu1.dcache.overall_hits::total 83034 # number of overall hits 1671system.cpu1.dcache.ReadReq_misses::cpu1.data 352 # number of ReadReq misses 1672system.cpu1.dcache.ReadReq_misses::total 352 # number of ReadReq misses | 1661system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 1662system.cpu1.dcache.tags.tag_accesses 333666 # Number of tag accesses 1663system.cpu1.dcache.tags.data_accesses 333666 # Number of data accesses 1664system.cpu1.dcache.ReadReq_hits::cpu1.data 46059 # number of ReadReq hits 1665system.cpu1.dcache.ReadReq_hits::total 46059 # number of ReadReq hits 1666system.cpu1.dcache.WriteReq_hits::cpu1.data 36657 # number of WriteReq hits 1667system.cpu1.dcache.WriteReq_hits::total 36657 # number of WriteReq hits 1668system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits 1669system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits 1670system.cpu1.dcache.demand_hits::cpu1.data 82716 # number of demand (read+write) hits 1671system.cpu1.dcache.demand_hits::total 82716 # number of demand (read+write) hits 1672system.cpu1.dcache.overall_hits::cpu1.data 82716 # number of overall hits 1673system.cpu1.dcache.overall_hits::total 82716 # number of overall hits 1674system.cpu1.dcache.ReadReq_misses::cpu1.data 427 # number of ReadReq misses 1675system.cpu1.dcache.ReadReq_misses::total 427 # number of ReadReq misses |
1673system.cpu1.dcache.WriteReq_misses::cpu1.data 140 # number of WriteReq misses 1674system.cpu1.dcache.WriteReq_misses::total 140 # number of WriteReq misses | 1676system.cpu1.dcache.WriteReq_misses::cpu1.data 140 # number of WriteReq misses 1677system.cpu1.dcache.WriteReq_misses::total 140 # number of WriteReq misses |
1675system.cpu1.dcache.SwapReq_misses::cpu1.data 54 # number of SwapReq misses 1676system.cpu1.dcache.SwapReq_misses::total 54 # number of SwapReq misses 1677system.cpu1.dcache.demand_misses::cpu1.data 492 # number of demand (read+write) misses 1678system.cpu1.dcache.demand_misses::total 492 # number of demand (read+write) misses 1679system.cpu1.dcache.overall_misses::cpu1.data 492 # number of overall misses 1680system.cpu1.dcache.overall_misses::total 492 # number of overall misses 1681system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4522597 # number of ReadReq miss cycles 1682system.cpu1.dcache.ReadReq_miss_latency::total 4522597 # number of ReadReq miss cycles 1683system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3033762 # number of WriteReq miss cycles 1684system.cpu1.dcache.WriteReq_miss_latency::total 3033762 # number of WriteReq miss cycles 1685system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 535508 # number of SwapReq miss cycles 1686system.cpu1.dcache.SwapReq_miss_latency::total 535508 # number of SwapReq miss cycles 1687system.cpu1.dcache.demand_miss_latency::cpu1.data 7556359 # number of demand (read+write) miss cycles 1688system.cpu1.dcache.demand_miss_latency::total 7556359 # number of demand (read+write) miss cycles 1689system.cpu1.dcache.overall_miss_latency::cpu1.data 7556359 # number of overall miss cycles 1690system.cpu1.dcache.overall_miss_latency::total 7556359 # number of overall miss cycles 1691system.cpu1.dcache.ReadReq_accesses::cpu1.data 46895 # number of ReadReq accesses(hits+misses) 1692system.cpu1.dcache.ReadReq_accesses::total 46895 # number of ReadReq accesses(hits+misses) 1693system.cpu1.dcache.WriteReq_accesses::cpu1.data 36631 # number of WriteReq accesses(hits+misses) 1694system.cpu1.dcache.WriteReq_accesses::total 36631 # number of WriteReq accesses(hits+misses) 1695system.cpu1.dcache.SwapReq_accesses::cpu1.data 66 # number of SwapReq accesses(hits+misses) 1696system.cpu1.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) 1697system.cpu1.dcache.demand_accesses::cpu1.data 83526 # number of demand (read+write) accesses 1698system.cpu1.dcache.demand_accesses::total 83526 # number of demand (read+write) accesses 1699system.cpu1.dcache.overall_accesses::cpu1.data 83526 # number of overall (read+write) accesses 1700system.cpu1.dcache.overall_accesses::total 83526 # number of overall (read+write) accesses 1701system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.007506 # miss rate for ReadReq accesses 1702system.cpu1.dcache.ReadReq_miss_rate::total 0.007506 # miss rate for ReadReq accesses 1703system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003822 # miss rate for WriteReq accesses 1704system.cpu1.dcache.WriteReq_miss_rate::total 0.003822 # miss rate for WriteReq accesses 1705system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.818182 # miss rate for SwapReq accesses 1706system.cpu1.dcache.SwapReq_miss_rate::total 0.818182 # miss rate for SwapReq accesses 1707system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005890 # miss rate for demand accesses 1708system.cpu1.dcache.demand_miss_rate::total 0.005890 # miss rate for demand accesses 1709system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005890 # miss rate for overall accesses 1710system.cpu1.dcache.overall_miss_rate::total 0.005890 # miss rate for overall accesses 1711system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12848.286932 # average ReadReq miss latency 1712system.cpu1.dcache.ReadReq_avg_miss_latency::total 12848.286932 # average ReadReq miss latency 1713system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21669.728571 # average WriteReq miss latency 1714system.cpu1.dcache.WriteReq_avg_miss_latency::total 21669.728571 # average WriteReq miss latency 1715system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9916.814815 # average SwapReq miss latency 1716system.cpu1.dcache.SwapReq_avg_miss_latency::total 9916.814815 # average SwapReq miss latency 1717system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15358.453252 # average overall miss latency 1718system.cpu1.dcache.demand_avg_miss_latency::total 15358.453252 # average overall miss latency 1719system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15358.453252 # average overall miss latency 1720system.cpu1.dcache.overall_avg_miss_latency::total 15358.453252 # average overall miss latency | 1678system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses 1679system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses 1680system.cpu1.dcache.demand_misses::cpu1.data 567 # number of demand (read+write) misses 1681system.cpu1.dcache.demand_misses::total 567 # number of demand (read+write) misses 1682system.cpu1.dcache.overall_misses::cpu1.data 567 # number of overall misses 1683system.cpu1.dcache.overall_misses::total 567 # number of overall misses 1684system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5717104 # number of ReadReq miss cycles 1685system.cpu1.dcache.ReadReq_miss_latency::total 5717104 # number of ReadReq miss cycles 1686system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2840511 # number of WriteReq miss cycles 1687system.cpu1.dcache.WriteReq_miss_latency::total 2840511 # number of WriteReq miss cycles 1688system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 466006 # number of SwapReq miss cycles 1689system.cpu1.dcache.SwapReq_miss_latency::total 466006 # number of SwapReq miss cycles 1690system.cpu1.dcache.demand_miss_latency::cpu1.data 8557615 # number of demand (read+write) miss cycles 1691system.cpu1.dcache.demand_miss_latency::total 8557615 # number of demand (read+write) miss cycles 1692system.cpu1.dcache.overall_miss_latency::cpu1.data 8557615 # number of overall miss cycles 1693system.cpu1.dcache.overall_miss_latency::total 8557615 # number of overall miss cycles 1694system.cpu1.dcache.ReadReq_accesses::cpu1.data 46486 # number of ReadReq accesses(hits+misses) 1695system.cpu1.dcache.ReadReq_accesses::total 46486 # number of ReadReq accesses(hits+misses) 1696system.cpu1.dcache.WriteReq_accesses::cpu1.data 36797 # number of WriteReq accesses(hits+misses) 1697system.cpu1.dcache.WriteReq_accesses::total 36797 # number of WriteReq accesses(hits+misses) 1698system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) 1699system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) 1700system.cpu1.dcache.demand_accesses::cpu1.data 83283 # number of demand (read+write) accesses 1701system.cpu1.dcache.demand_accesses::total 83283 # number of demand (read+write) accesses 1702system.cpu1.dcache.overall_accesses::cpu1.data 83283 # number of overall (read+write) accesses 1703system.cpu1.dcache.overall_accesses::total 83283 # number of overall (read+write) accesses 1704system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009186 # miss rate for ReadReq accesses 1705system.cpu1.dcache.ReadReq_miss_rate::total 0.009186 # miss rate for ReadReq accesses 1706system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003805 # miss rate for WriteReq accesses 1707system.cpu1.dcache.WriteReq_miss_rate::total 0.003805 # miss rate for WriteReq accesses 1708system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.814286 # miss rate for SwapReq accesses 1709system.cpu1.dcache.SwapReq_miss_rate::total 0.814286 # miss rate for SwapReq accesses 1710system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006808 # miss rate for demand accesses 1711system.cpu1.dcache.demand_miss_rate::total 0.006808 # miss rate for demand accesses 1712system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006808 # miss rate for overall accesses 1713system.cpu1.dcache.overall_miss_rate::total 0.006808 # miss rate for overall accesses 1714system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13389.002342 # average ReadReq miss latency 1715system.cpu1.dcache.ReadReq_avg_miss_latency::total 13389.002342 # average ReadReq miss latency 1716system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20289.364286 # average WriteReq miss latency 1717system.cpu1.dcache.WriteReq_avg_miss_latency::total 20289.364286 # average WriteReq miss latency 1718system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 8175.543860 # average SwapReq miss latency 1719system.cpu1.dcache.SwapReq_avg_miss_latency::total 8175.543860 # average SwapReq miss latency 1720system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15092.795414 # average overall miss latency 1721system.cpu1.dcache.demand_avg_miss_latency::total 15092.795414 # average overall miss latency 1722system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15092.795414 # average overall miss latency 1723system.cpu1.dcache.overall_avg_miss_latency::total 15092.795414 # average overall miss latency |
1721system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1722system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1723system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1724system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1725system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1726system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1727system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1728system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1724system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1725system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1726system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1727system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1728system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1729system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1730system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1731system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
1729system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 195 # number of ReadReq MSHR hits 1730system.cpu1.dcache.ReadReq_mshr_hits::total 195 # number of ReadReq MSHR hits 1731system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits 1732system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits 1733system.cpu1.dcache.demand_mshr_hits::cpu1.data 227 # number of demand (read+write) MSHR hits 1734system.cpu1.dcache.demand_mshr_hits::total 227 # number of demand (read+write) MSHR hits 1735system.cpu1.dcache.overall_mshr_hits::cpu1.data 227 # number of overall MSHR hits 1736system.cpu1.dcache.overall_mshr_hits::total 227 # number of overall MSHR hits 1737system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 157 # number of ReadReq MSHR misses 1738system.cpu1.dcache.ReadReq_mshr_misses::total 157 # number of ReadReq MSHR misses 1739system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses 1740system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses 1741system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 54 # number of SwapReq MSHR misses 1742system.cpu1.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses 1743system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses 1744system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses 1745system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses 1746system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses 1747system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1099522 # number of ReadReq MSHR miss cycles 1748system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1099522 # number of ReadReq MSHR miss cycles 1749system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1387488 # number of WriteReq MSHR miss cycles 1750system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1387488 # number of WriteReq MSHR miss cycles 1751system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 427492 # number of SwapReq MSHR miss cycles 1752system.cpu1.dcache.SwapReq_mshr_miss_latency::total 427492 # number of SwapReq MSHR miss cycles 1753system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2487010 # number of demand (read+write) MSHR miss cycles 1754system.cpu1.dcache.demand_mshr_miss_latency::total 2487010 # number of demand (read+write) MSHR miss cycles 1755system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2487010 # number of overall MSHR miss cycles 1756system.cpu1.dcache.overall_mshr_miss_latency::total 2487010 # number of overall MSHR miss cycles 1757system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003348 # mshr miss rate for ReadReq accesses 1758system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003348 # mshr miss rate for ReadReq accesses 1759system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002948 # mshr miss rate for WriteReq accesses 1760system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002948 # mshr miss rate for WriteReq accesses 1761system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.818182 # mshr miss rate for SwapReq accesses 1762system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.818182 # mshr miss rate for SwapReq accesses 1763system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003173 # mshr miss rate for demand accesses 1764system.cpu1.dcache.demand_mshr_miss_rate::total 0.003173 # mshr miss rate for demand accesses 1765system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003173 # mshr miss rate for overall accesses 1766system.cpu1.dcache.overall_mshr_miss_rate::total 0.003173 # mshr miss rate for overall accesses 1767system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 7003.324841 # average ReadReq mshr miss latency 1768system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 7003.324841 # average ReadReq mshr miss latency 1769system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12847.111111 # average WriteReq mshr miss latency 1770system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12847.111111 # average WriteReq mshr miss latency 1771system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7916.518519 # average SwapReq mshr miss latency 1772system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7916.518519 # average SwapReq mshr miss latency 1773system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9384.943396 # average overall mshr miss latency 1774system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9384.943396 # average overall mshr miss latency 1775system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9384.943396 # average overall mshr miss latency 1776system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9384.943396 # average overall mshr miss latency | 1732system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 269 # number of ReadReq MSHR hits 1733system.cpu1.dcache.ReadReq_mshr_hits::total 269 # number of ReadReq MSHR hits 1734system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 35 # number of WriteReq MSHR hits 1735system.cpu1.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits 1736system.cpu1.dcache.demand_mshr_hits::cpu1.data 304 # number of demand (read+write) MSHR hits 1737system.cpu1.dcache.demand_mshr_hits::total 304 # number of demand (read+write) MSHR hits 1738system.cpu1.dcache.overall_mshr_hits::cpu1.data 304 # number of overall MSHR hits 1739system.cpu1.dcache.overall_mshr_hits::total 304 # number of overall MSHR hits 1740system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 158 # number of ReadReq MSHR misses 1741system.cpu1.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses 1742system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses 1743system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 1744system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 57 # number of SwapReq MSHR misses 1745system.cpu1.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses 1746system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses 1747system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses 1748system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses 1749system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses 1750system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1020514 # number of ReadReq MSHR miss cycles 1751system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1020514 # number of ReadReq MSHR miss cycles 1752system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1289239 # number of WriteReq MSHR miss cycles 1753system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1289239 # number of WriteReq MSHR miss cycles 1754system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 351994 # number of SwapReq MSHR miss cycles 1755system.cpu1.dcache.SwapReq_mshr_miss_latency::total 351994 # number of SwapReq MSHR miss cycles 1756system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2309753 # number of demand (read+write) MSHR miss cycles 1757system.cpu1.dcache.demand_mshr_miss_latency::total 2309753 # number of demand (read+write) MSHR miss cycles 1758system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2309753 # number of overall MSHR miss cycles 1759system.cpu1.dcache.overall_mshr_miss_latency::total 2309753 # number of overall MSHR miss cycles 1760system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003399 # mshr miss rate for ReadReq accesses 1761system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003399 # mshr miss rate for ReadReq accesses 1762system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002853 # mshr miss rate for WriteReq accesses 1763system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002853 # mshr miss rate for WriteReq accesses 1764system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.814286 # mshr miss rate for SwapReq accesses 1765system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.814286 # mshr miss rate for SwapReq accesses 1766system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003158 # mshr miss rate for demand accesses 1767system.cpu1.dcache.demand_mshr_miss_rate::total 0.003158 # mshr miss rate for demand accesses 1768system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003158 # mshr miss rate for overall accesses 1769system.cpu1.dcache.overall_mshr_miss_rate::total 0.003158 # mshr miss rate for overall accesses 1770system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6458.949367 # average ReadReq mshr miss latency 1771system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6458.949367 # average ReadReq mshr miss latency 1772system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12278.466667 # average WriteReq mshr miss latency 1773system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12278.466667 # average WriteReq mshr miss latency 1774system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 6175.333333 # average SwapReq mshr miss latency 1775system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 6175.333333 # average SwapReq mshr miss latency 1776system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 8782.330798 # average overall mshr miss latency 1777system.cpu1.dcache.demand_avg_mshr_miss_latency::total 8782.330798 # average overall mshr miss latency 1778system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 8782.330798 # average overall mshr miss latency 1779system.cpu1.dcache.overall_avg_mshr_miss_latency::total 8782.330798 # average overall mshr miss latency |
1777system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1780system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
1778system.cpu2.branchPred.lookups 51191 # Number of BP lookups 1779system.cpu2.branchPred.condPredicted 48468 # Number of conditional branches predicted 1780system.cpu2.branchPred.condIncorrect 1308 # Number of conditional branches incorrect 1781system.cpu2.branchPred.BTBLookups 44993 # Number of BTB lookups 1782system.cpu2.branchPred.BTBHits 44297 # Number of BTB hits | 1781system.cpu2.branchPred.lookups 50591 # Number of BP lookups 1782system.cpu2.branchPred.condPredicted 46824 # Number of conditional branches predicted 1783system.cpu2.branchPred.condIncorrect 1298 # Number of conditional branches incorrect 1784system.cpu2.branchPred.BTBLookups 43166 # Number of BTB lookups 1785system.cpu2.branchPred.BTBHits 41772 # Number of BTB hits |
1783system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1786system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
1784system.cpu2.branchPred.BTBHitPct 98.453093 # BTB Hit Percentage 1785system.cpu2.branchPred.usedRAS 684 # Number of times the RAS was used to get a target. 1786system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. 1787system.cpu2.numCycles 177434 # number of cpu cycles simulated | 1787system.cpu2.branchPred.BTBHitPct 96.770606 # BTB Hit Percentage 1788system.cpu2.branchPred.usedRAS 904 # Number of times the RAS was used to get a target. 1789system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. 1790system.cpu2.numCycles 167617 # number of cpu cycles simulated |
1788system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 1789system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed | 1791system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 1792system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed |
1790system.cpu2.fetch.icacheStallCycles 28865 # Number of cycles fetch is stalled on an Icache miss 1791system.cpu2.fetch.Insts 285908 # Number of instructions fetch has processed 1792system.cpu2.fetch.Branches 51191 # Number of branches that fetch encountered 1793system.cpu2.fetch.predictedBranches 44981 # Number of branches that fetch has predicted taken 1794system.cpu2.fetch.Cycles 100768 # Number of cycles fetch has run and was not squashing or blocked 1795system.cpu2.fetch.SquashCycles 3816 # Number of cycles fetch has spent squashing 1796system.cpu2.fetch.BlockedCycles 31184 # Number of cycles fetch has spent blocked | 1793system.cpu2.fetch.icacheStallCycles 31796 # Number of cycles fetch is stalled on an Icache miss 1794system.cpu2.fetch.Insts 277876 # Number of instructions fetch has processed 1795system.cpu2.fetch.Branches 50591 # Number of branches that fetch encountered 1796system.cpu2.fetch.predictedBranches 42676 # Number of branches that fetch has predicted taken 1797system.cpu2.fetch.Cycles 121192 # Number of cycles fetch has run and was not squashing or blocked 1798system.cpu2.fetch.SquashCycles 2752 # Number of cycles fetch has spent squashing |
1797system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 1799system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
1798system.cpu2.fetch.NoActiveThreadStallCycles 7805 # Number of stall cycles due to no active thread to fetch from 1799system.cpu2.fetch.PendingTrapStallCycles 1366 # Number of stall cycles due to pending traps 1800system.cpu2.fetch.CacheLines 19788 # Number of cache lines fetched 1801system.cpu2.fetch.IcacheSquashes 272 # Number of outstanding Icache misses that were squashed 1802system.cpu2.fetch.rateDist::samples 172424 # Number of instructions fetched each cycle (Total) 1803system.cpu2.fetch.rateDist::mean 1.658168 # Number of instructions fetched each cycle (Total) 1804system.cpu2.fetch.rateDist::stdev 2.138146 # Number of instructions fetched each cycle (Total) | 1800system.cpu2.fetch.NoActiveThreadStallCycles 7062 # Number of stall cycles due to no active thread to fetch from 1801system.cpu2.fetch.PendingTrapStallCycles 1110 # Number of stall cycles due to pending traps 1802system.cpu2.fetch.IcacheWaitRetryStallCycles 3 # Number of stall cycles due to full MSHR 1803system.cpu2.fetch.CacheLines 22366 # Number of cache lines fetched 1804system.cpu2.fetch.IcacheSquashes 459 # Number of outstanding Icache misses that were squashed 1805system.cpu2.fetch.rateDist::samples 162543 # Number of instructions fetched each cycle (Total) 1806system.cpu2.fetch.rateDist::mean 1.709554 # Number of instructions fetched each cycle (Total) 1807system.cpu2.fetch.rateDist::stdev 2.176994 # Number of instructions fetched each cycle (Total) |
1805system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1808system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
1806system.cpu2.fetch.rateDist::0 71656 41.56% 41.56% # Number of instructions fetched each cycle (Total) 1807system.cpu2.fetch.rateDist::1 51257 29.73% 71.29% # Number of instructions fetched each cycle (Total) 1808system.cpu2.fetch.rateDist::2 6128 3.55% 74.84% # Number of instructions fetched each cycle (Total) 1809system.cpu2.fetch.rateDist::3 3186 1.85% 76.69% # Number of instructions fetched each cycle (Total) 1810system.cpu2.fetch.rateDist::4 695 0.40% 77.09% # Number of instructions fetched each cycle (Total) 1811system.cpu2.fetch.rateDist::5 34284 19.88% 96.97% # Number of instructions fetched each cycle (Total) 1812system.cpu2.fetch.rateDist::6 1167 0.68% 97.65% # Number of instructions fetched each cycle (Total) 1813system.cpu2.fetch.rateDist::7 773 0.45% 98.10% # Number of instructions fetched each cycle (Total) 1814system.cpu2.fetch.rateDist::8 3278 1.90% 100.00% # Number of instructions fetched each cycle (Total) | 1809system.cpu2.fetch.rateDist::0 64711 39.81% 39.81% # Number of instructions fetched each cycle (Total) 1810system.cpu2.fetch.rateDist::1 49634 30.54% 70.35% # Number of instructions fetched each cycle (Total) 1811system.cpu2.fetch.rateDist::2 6798 4.18% 74.53% # Number of instructions fetched each cycle (Total) 1812system.cpu2.fetch.rateDist::3 3442 2.12% 76.65% # Number of instructions fetched each cycle (Total) 1813system.cpu2.fetch.rateDist::4 952 0.59% 77.23% # Number of instructions fetched each cycle (Total) 1814system.cpu2.fetch.rateDist::5 30771 18.93% 96.16% # Number of instructions fetched each cycle (Total) 1815system.cpu2.fetch.rateDist::6 1187 0.73% 96.89% # Number of instructions fetched each cycle (Total) 1816system.cpu2.fetch.rateDist::7 849 0.52% 97.42% # Number of instructions fetched each cycle (Total) 1817system.cpu2.fetch.rateDist::8 4199 2.58% 100.00% # Number of instructions fetched each cycle (Total) |
1815system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1816system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1817system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 1818system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1819system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1820system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
1818system.cpu2.fetch.rateDist::total 172424 # Number of instructions fetched each cycle (Total) 1819system.cpu2.fetch.branchRate 0.288507 # Number of branch fetches per cycle 1820system.cpu2.fetch.rate 1.611348 # Number of inst fetches per cycle 1821system.cpu2.decode.IdleCycles 34386 # Number of cycles decode is idle 1822system.cpu2.decode.BlockedCycles 27902 # Number of cycles decode is blocked 1823system.cpu2.decode.RunCycles 94859 # Number of cycles decode is running 1824system.cpu2.decode.UnblockCycles 5040 # Number of cycles decode is unblocking 1825system.cpu2.decode.SquashCycles 2432 # Number of cycles decode is squashing 1826system.cpu2.decode.DecodedInsts 282267 # Number of instructions handled by decode 1827system.cpu2.rename.SquashCycles 2432 # Number of cycles rename is squashing 1828system.cpu2.rename.IdleCycles 35111 # Number of cycles rename is idle 1829system.cpu2.rename.BlockCycles 14773 # Number of cycles rename is blocking 1830system.cpu2.rename.serializeStallCycles 12374 # count of cycles rename stalled for serializing inst 1831system.cpu2.rename.RunCycles 90050 # Number of cycles rename is running 1832system.cpu2.rename.UnblockCycles 9879 # Number of cycles rename is unblocking 1833system.cpu2.rename.RenamedInsts 280008 # Number of instructions processed by rename 1834system.cpu2.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full 1835system.cpu2.rename.RenamedOperands 196247 # Number of destination operands rename has renamed 1836system.cpu2.rename.RenameLookups 536665 # Number of register rename lookups that rename has made 1837system.cpu2.rename.int_rename_lookups 417354 # Number of integer rename lookups 1838system.cpu2.rename.CommittedMaps 183125 # Number of HB maps that are committed 1839system.cpu2.rename.UndoneMaps 13122 # Number of HB maps that are undone due to squashing 1840system.cpu2.rename.serializingInsts 1115 # count of serializing insts renamed 1841system.cpu2.rename.tempSerializingInsts 1240 # count of temporary serializing insts renamed 1842system.cpu2.rename.skidInsts 12503 # count of insts added to the skid buffer 1843system.cpu2.memDep0.insertedLoads 79020 # Number of loads inserted to the mem dependence unit. 1844system.cpu2.memDep0.insertedStores 37489 # Number of stores inserted to the mem dependence unit. 1845system.cpu2.memDep0.conflictingLoads 37725 # Number of conflicting loads. 1846system.cpu2.memDep0.conflictingStores 32426 # Number of conflicting stores. 1847system.cpu2.iq.iqInstsAdded 232155 # Number of instructions added to the IQ (excludes non-spec) 1848system.cpu2.iq.iqNonSpecInstsAdded 6357 # Number of non-speculative instructions added to the IQ 1849system.cpu2.iq.iqInstsIssued 234096 # Number of instructions issued 1850system.cpu2.iq.iqSquashedInstsIssued 107 # Number of squashed instructions issued 1851system.cpu2.iq.iqSquashedInstsExamined 11107 # Number of squashed instructions iterated over during squash; mainly for profiling 1852system.cpu2.iq.iqSquashedOperandsExamined 11056 # Number of squashed operands that are examined and possibly removed from graph 1853system.cpu2.iq.iqSquashedNonSpecRemoved 607 # Number of squashed non-spec instructions that were removed 1854system.cpu2.iq.issued_per_cycle::samples 172424 # Number of insts issued each cycle 1855system.cpu2.iq.issued_per_cycle::mean 1.357676 # Number of insts issued each cycle 1856system.cpu2.iq.issued_per_cycle::stdev 1.313193 # Number of insts issued each cycle | 1821system.cpu2.fetch.rateDist::total 162543 # Number of instructions fetched each cycle (Total) 1822system.cpu2.fetch.branchRate 0.301825 # Number of branch fetches per cycle 1823system.cpu2.fetch.rate 1.657803 # Number of inst fetches per cycle 1824system.cpu2.decode.IdleCycles 17997 # Number of cycles decode is idle 1825system.cpu2.decode.BlockedCycles 57677 # Number of cycles decode is blocked 1826system.cpu2.decode.RunCycles 74910 # Number of cycles decode is running 1827system.cpu2.decode.UnblockCycles 3521 # Number of cycles decode is unblocking 1828system.cpu2.decode.SquashCycles 1376 # Number of cycles decode is squashing 1829system.cpu2.decode.DecodedInsts 262355 # Number of instructions handled by decode 1830system.cpu2.rename.SquashCycles 1376 # Number of cycles rename is squashing 1831system.cpu2.rename.IdleCycles 18679 # Number of cycles rename is idle 1832system.cpu2.rename.BlockCycles 27128 # Number of cycles rename is blocking 1833system.cpu2.rename.serializeStallCycles 12799 # count of cycles rename stalled for serializing inst 1834system.cpu2.rename.RunCycles 76466 # Number of cycles rename is running 1835system.cpu2.rename.UnblockCycles 19033 # Number of cycles rename is unblocking 1836system.cpu2.rename.RenamedInsts 259235 # Number of instructions processed by rename 1837system.cpu2.rename.IQFullEvents 17033 # Number of times rename has blocked due to IQ full 1838system.cpu2.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full 1839system.cpu2.rename.FullRegisterEvents 6 # Number of times there has been no free registers 1840system.cpu2.rename.RenamedOperands 182575 # Number of destination operands rename has renamed 1841system.cpu2.rename.RenameLookups 494395 # Number of register rename lookups that rename has made 1842system.cpu2.rename.int_rename_lookups 386046 # Number of integer rename lookups 1843system.cpu2.rename.CommittedMaps 167620 # Number of HB maps that are committed 1844system.cpu2.rename.UndoneMaps 14955 # Number of HB maps that are undone due to squashing 1845system.cpu2.rename.serializingInsts 1169 # count of serializing insts renamed 1846system.cpu2.rename.tempSerializingInsts 1235 # count of temporary serializing insts renamed 1847system.cpu2.rename.skidInsts 23554 # count of insts added to the skid buffer 1848system.cpu2.memDep0.insertedLoads 71776 # Number of loads inserted to the mem dependence unit. 1849system.cpu2.memDep0.insertedStores 33725 # Number of stores inserted to the mem dependence unit. 1850system.cpu2.memDep0.conflictingLoads 34298 # Number of conflicting loads. 1851system.cpu2.memDep0.conflictingStores 28594 # Number of conflicting stores. 1852system.cpu2.iq.iqInstsAdded 214929 # Number of instructions added to the IQ (excludes non-spec) 1853system.cpu2.iq.iqNonSpecInstsAdded 6621 # Number of non-speculative instructions added to the IQ 1854system.cpu2.iq.iqInstsIssued 216336 # Number of instructions issued 1855system.cpu2.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued 1856system.cpu2.iq.iqSquashedInstsExamined 13228 # Number of squashed instructions iterated over during squash; mainly for profiling 1857system.cpu2.iq.iqSquashedOperandsExamined 12296 # Number of squashed operands that are examined and possibly removed from graph 1858system.cpu2.iq.iqSquashedNonSpecRemoved 674 # Number of squashed non-spec instructions that were removed 1859system.cpu2.iq.issued_per_cycle::samples 162543 # Number of insts issued each cycle 1860system.cpu2.iq.issued_per_cycle::mean 1.330946 # Number of insts issued each cycle 1861system.cpu2.iq.issued_per_cycle::stdev 1.384454 # Number of insts issued each cycle |
1857system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1862system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
1858system.cpu2.iq.issued_per_cycle::0 69134 40.10% 40.10% # Number of insts issued each cycle 1859system.cpu2.iq.issued_per_cycle::1 22467 13.03% 53.13% # Number of insts issued each cycle 1860system.cpu2.iq.issued_per_cycle::2 37714 21.87% 75.00% # Number of insts issued each cycle 1861system.cpu2.iq.issued_per_cycle::3 38330 22.23% 97.23% # Number of insts issued each cycle 1862system.cpu2.iq.issued_per_cycle::4 3239 1.88% 99.11% # Number of insts issued each cycle 1863system.cpu2.iq.issued_per_cycle::5 1151 0.67% 99.77% # Number of insts issued each cycle 1864system.cpu2.iq.issued_per_cycle::6 279 0.16% 99.94% # Number of insts issued each cycle 1865system.cpu2.iq.issued_per_cycle::7 54 0.03% 99.97% # Number of insts issued each cycle 1866system.cpu2.iq.issued_per_cycle::8 56 0.03% 100.00% # Number of insts issued each cycle | 1863system.cpu2.iq.issued_per_cycle::0 68368 42.06% 42.06% # Number of insts issued each cycle 1864system.cpu2.iq.issued_per_cycle::1 22285 13.71% 55.77% # Number of insts issued each cycle 1865system.cpu2.iq.issued_per_cycle::2 32950 20.27% 76.04% # Number of insts issued each cycle 1866system.cpu2.iq.issued_per_cycle::3 32546 20.02% 96.07% # Number of insts issued each cycle 1867system.cpu2.iq.issued_per_cycle::4 3459 2.13% 98.19% # Number of insts issued each cycle 1868system.cpu2.iq.issued_per_cycle::5 1594 0.98% 99.17% # Number of insts issued each cycle 1869system.cpu2.iq.issued_per_cycle::6 888 0.55% 99.72% # Number of insts issued each cycle 1870system.cpu2.iq.issued_per_cycle::7 245 0.15% 99.87% # Number of insts issued each cycle 1871system.cpu2.iq.issued_per_cycle::8 208 0.13% 100.00% # Number of insts issued each cycle |
1867system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1868system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1869system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 1872system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1873system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1874system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
1870system.cpu2.iq.issued_per_cycle::total 172424 # Number of insts issued each cycle | 1875system.cpu2.iq.issued_per_cycle::total 162543 # Number of insts issued each cycle |
1871system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1876system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
1872system.cpu2.iq.fu_full::IntAlu 12 4.40% 4.40% # attempts to use FU when none available 1873system.cpu2.iq.fu_full::IntMult 0 0.00% 4.40% # attempts to use FU when none available 1874system.cpu2.iq.fu_full::IntDiv 0 0.00% 4.40% # attempts to use FU when none available 1875system.cpu2.iq.fu_full::FloatAdd 0 0.00% 4.40% # attempts to use FU when none available 1876system.cpu2.iq.fu_full::FloatCmp 0 0.00% 4.40% # attempts to use FU when none available 1877system.cpu2.iq.fu_full::FloatCvt 0 0.00% 4.40% # attempts to use FU when none available 1878system.cpu2.iq.fu_full::FloatMult 0 0.00% 4.40% # attempts to use FU when none available 1879system.cpu2.iq.fu_full::FloatDiv 0 0.00% 4.40% # attempts to use FU when none available 1880system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 4.40% # attempts to use FU when none available 1881system.cpu2.iq.fu_full::SimdAdd 0 0.00% 4.40% # attempts to use FU when none available 1882system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 4.40% # attempts to use FU when none available 1883system.cpu2.iq.fu_full::SimdAlu 0 0.00% 4.40% # attempts to use FU when none available 1884system.cpu2.iq.fu_full::SimdCmp 0 0.00% 4.40% # attempts to use FU when none available 1885system.cpu2.iq.fu_full::SimdCvt 0 0.00% 4.40% # attempts to use FU when none available 1886system.cpu2.iq.fu_full::SimdMisc 0 0.00% 4.40% # attempts to use FU when none available 1887system.cpu2.iq.fu_full::SimdMult 0 0.00% 4.40% # attempts to use FU when none available 1888system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 4.40% # attempts to use FU when none available 1889system.cpu2.iq.fu_full::SimdShift 0 0.00% 4.40% # attempts to use FU when none available 1890system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 4.40% # attempts to use FU when none available 1891system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 4.40% # attempts to use FU when none available 1892system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 4.40% # attempts to use FU when none available 1893system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 4.40% # attempts to use FU when none available 1894system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 4.40% # attempts to use FU when none available 1895system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 4.40% # attempts to use FU when none available 1896system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 4.40% # attempts to use FU when none available 1897system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 4.40% # attempts to use FU when none available 1898system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 4.40% # attempts to use FU when none available 1899system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.40% # attempts to use FU when none available 1900system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 4.40% # attempts to use FU when none available 1901system.cpu2.iq.fu_full::MemRead 51 18.68% 23.08% # attempts to use FU when none available 1902system.cpu2.iq.fu_full::MemWrite 210 76.92% 100.00% # attempts to use FU when none available | 1877system.cpu2.iq.fu_full::IntAlu 90 24.93% 24.93% # attempts to use FU when none available 1878system.cpu2.iq.fu_full::IntMult 0 0.00% 24.93% # attempts to use FU when none available 1879system.cpu2.iq.fu_full::IntDiv 0 0.00% 24.93% # attempts to use FU when none available 1880system.cpu2.iq.fu_full::FloatAdd 0 0.00% 24.93% # attempts to use FU when none available 1881system.cpu2.iq.fu_full::FloatCmp 0 0.00% 24.93% # attempts to use FU when none available 1882system.cpu2.iq.fu_full::FloatCvt 0 0.00% 24.93% # attempts to use FU when none available 1883system.cpu2.iq.fu_full::FloatMult 0 0.00% 24.93% # attempts to use FU when none available 1884system.cpu2.iq.fu_full::FloatDiv 0 0.00% 24.93% # attempts to use FU when none available 1885system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 24.93% # attempts to use FU when none available 1886system.cpu2.iq.fu_full::SimdAdd 0 0.00% 24.93% # attempts to use FU when none available 1887system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 24.93% # attempts to use FU when none available 1888system.cpu2.iq.fu_full::SimdAlu 0 0.00% 24.93% # attempts to use FU when none available 1889system.cpu2.iq.fu_full::SimdCmp 0 0.00% 24.93% # attempts to use FU when none available 1890system.cpu2.iq.fu_full::SimdCvt 0 0.00% 24.93% # attempts to use FU when none available 1891system.cpu2.iq.fu_full::SimdMisc 0 0.00% 24.93% # attempts to use FU when none available 1892system.cpu2.iq.fu_full::SimdMult 0 0.00% 24.93% # attempts to use FU when none available 1893system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 24.93% # attempts to use FU when none available 1894system.cpu2.iq.fu_full::SimdShift 0 0.00% 24.93% # attempts to use FU when none available 1895system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 24.93% # attempts to use FU when none available 1896system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 24.93% # attempts to use FU when none available 1897system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 24.93% # attempts to use FU when none available 1898system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 24.93% # attempts to use FU when none available 1899system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 24.93% # attempts to use FU when none available 1900system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 24.93% # attempts to use FU when none available 1901system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 24.93% # attempts to use FU when none available 1902system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 24.93% # attempts to use FU when none available 1903system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 24.93% # attempts to use FU when none available 1904system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.93% # attempts to use FU when none available 1905system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 24.93% # attempts to use FU when none available 1906system.cpu2.iq.fu_full::MemRead 62 17.17% 42.11% # attempts to use FU when none available 1907system.cpu2.iq.fu_full::MemWrite 209 57.89% 100.00% # attempts to use FU when none available |
1903system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1904system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1905system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 1908system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1909system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1910system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
1906system.cpu2.iq.FU_type_0::IntAlu 114033 48.71% 48.71% # Type of FU issued 1907system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.71% # Type of FU issued 1908system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.71% # Type of FU issued 1909system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.71% # Type of FU issued 1910system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.71% # Type of FU issued 1911system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.71% # Type of FU issued 1912system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.71% # Type of FU issued 1913system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.71% # Type of FU issued 1914system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.71% # Type of FU issued 1915system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.71% # Type of FU issued 1916system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.71% # Type of FU issued 1917system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.71% # Type of FU issued 1918system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.71% # Type of FU issued 1919system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.71% # Type of FU issued 1920system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.71% # Type of FU issued 1921system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.71% # Type of FU issued 1922system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.71% # Type of FU issued 1923system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.71% # Type of FU issued 1924system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.71% # Type of FU issued 1925system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.71% # Type of FU issued 1926system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.71% # Type of FU issued 1927system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued 1928system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.71% # Type of FU issued 1929system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.71% # Type of FU issued 1930system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.71% # Type of FU issued 1931system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.71% # Type of FU issued 1932system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.71% # Type of FU issued 1933system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.71% # Type of FU issued 1934system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.71% # Type of FU issued 1935system.cpu2.iq.FU_type_0::MemRead 83276 35.57% 84.29% # Type of FU issued 1936system.cpu2.iq.FU_type_0::MemWrite 36787 15.71% 100.00% # Type of FU issued | 1911system.cpu2.iq.FU_type_0::IntAlu 107190 49.55% 49.55% # Type of FU issued 1912system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.55% # Type of FU issued 1913system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.55% # Type of FU issued 1914system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.55% # Type of FU issued 1915system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.55% # Type of FU issued 1916system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.55% # Type of FU issued 1917system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.55% # Type of FU issued 1918system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.55% # Type of FU issued 1919system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.55% # Type of FU issued 1920system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.55% # Type of FU issued 1921system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.55% # Type of FU issued 1922system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.55% # Type of FU issued 1923system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.55% # Type of FU issued 1924system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.55% # Type of FU issued 1925system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.55% # Type of FU issued 1926system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.55% # Type of FU issued 1927system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.55% # Type of FU issued 1928system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.55% # Type of FU issued 1929system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.55% # Type of FU issued 1930system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.55% # Type of FU issued 1931system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.55% # Type of FU issued 1932system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.55% # Type of FU issued 1933system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.55% # Type of FU issued 1934system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.55% # Type of FU issued 1935system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.55% # Type of FU issued 1936system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.55% # Type of FU issued 1937system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.55% # Type of FU issued 1938system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.55% # Type of FU issued 1939system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.55% # Type of FU issued 1940system.cpu2.iq.FU_type_0::MemRead 76124 35.19% 84.74% # Type of FU issued 1941system.cpu2.iq.FU_type_0::MemWrite 33022 15.26% 100.00% # Type of FU issued |
1937system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1938system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1942system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1943system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
1939system.cpu2.iq.FU_type_0::total 234096 # Type of FU issued 1940system.cpu2.iq.rate 1.319341 # Inst issue rate 1941system.cpu2.iq.fu_busy_cnt 273 # FU busy when requested 1942system.cpu2.iq.fu_busy_rate 0.001166 # FU busy rate (busy events/executed inst) 1943system.cpu2.iq.int_inst_queue_reads 640996 # Number of integer instruction queue reads 1944system.cpu2.iq.int_inst_queue_writes 249665 # Number of integer instruction queue writes 1945system.cpu2.iq.int_inst_queue_wakeup_accesses 232273 # Number of integer instruction queue wakeup accesses | 1944system.cpu2.iq.FU_type_0::total 216336 # Type of FU issued 1945system.cpu2.iq.rate 1.290657 # Inst issue rate 1946system.cpu2.iq.fu_busy_cnt 361 # FU busy when requested 1947system.cpu2.iq.fu_busy_rate 0.001669 # FU busy rate (busy events/executed inst) 1948system.cpu2.iq.int_inst_queue_reads 595623 # Number of integer instruction queue reads 1949system.cpu2.iq.int_inst_queue_writes 234822 # Number of integer instruction queue writes 1950system.cpu2.iq.int_inst_queue_wakeup_accesses 214628 # Number of integer instruction queue wakeup accesses |
1946system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1947system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1948system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 1951system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1952system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1953system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
1949system.cpu2.iq.int_alu_accesses 234369 # Number of integer alu accesses | 1954system.cpu2.iq.int_alu_accesses 216697 # Number of integer alu accesses |
1950system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses | 1955system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses |
1951system.cpu2.iew.lsq.thread0.forwLoads 32149 # Number of loads that had data forwarded from stores | 1956system.cpu2.iew.lsq.thread0.forwLoads 28314 # Number of loads that had data forwarded from stores |
1952system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 1957system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
1953system.cpu2.iew.lsq.thread0.squashedLoads 2502 # Number of loads squashed | 1958system.cpu2.iew.lsq.thread0.squashedLoads 2909 # Number of loads squashed |
1954system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed | 1959system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed |
1955system.cpu2.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations 1956system.cpu2.iew.lsq.thread0.squashedStores 1485 # Number of stores squashed | 1960system.cpu2.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations 1961system.cpu2.iew.lsq.thread0.squashedStores 1648 # Number of stores squashed |
1957system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1958system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1959system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1960system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1961system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 1962system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1963system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1964system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1965system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1966system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
1962system.cpu2.iew.iewSquashCycles 2432 # Number of cycles IEW is squashing 1963system.cpu2.iew.iewBlockCycles 787 # Number of cycles IEW is blocking 1964system.cpu2.iew.iewUnblockCycles 45 # Number of cycles IEW is unblocking 1965system.cpu2.iew.iewDispatchedInsts 277138 # Number of instructions dispatched to IQ 1966system.cpu2.iew.iewDispSquashedInsts 365 # Number of squashed instructions skipped by dispatch 1967system.cpu2.iew.iewDispLoadInsts 79020 # Number of dispatched load instructions 1968system.cpu2.iew.iewDispStoreInsts 37489 # Number of dispatched store instructions 1969system.cpu2.iew.iewDispNonSpecInsts 1072 # Number of dispatched non-speculative instructions 1970system.cpu2.iew.iewIQFullEvents 45 # Number of times the IQ has become full, causing a stall | 1967system.cpu2.iew.iewSquashCycles 1376 # Number of cycles IEW is squashing 1968system.cpu2.iew.iewBlockCycles 7567 # Number of cycles IEW is blocking 1969system.cpu2.iew.iewUnblockCycles 67 # Number of cycles IEW is unblocking 1970system.cpu2.iew.iewDispatchedInsts 256538 # Number of instructions dispatched to IQ 1971system.cpu2.iew.iewDispSquashedInsts 192 # Number of squashed instructions skipped by dispatch 1972system.cpu2.iew.iewDispLoadInsts 71776 # Number of dispatched load instructions 1973system.cpu2.iew.iewDispStoreInsts 33725 # Number of dispatched store instructions 1974system.cpu2.iew.iewDispNonSpecInsts 1099 # Number of dispatched non-speculative instructions 1975system.cpu2.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall |
1971system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall | 1976system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall |
1972system.cpu2.iew.memOrderViolationEvents 46 # Number of memory order violations | 1977system.cpu2.iew.memOrderViolationEvents 44 # Number of memory order violations |
1973system.cpu2.iew.predictedTakenIncorrect 464 # Number of branches that were predicted taken incorrectly | 1978system.cpu2.iew.predictedTakenIncorrect 464 # Number of branches that were predicted taken incorrectly |
1974system.cpu2.iew.predictedNotTakenIncorrect 971 # Number of branches that were predicted not taken incorrectly 1975system.cpu2.iew.branchMispredicts 1435 # Number of branch mispredicts detected at execute 1976system.cpu2.iew.iewExecutedInsts 232944 # Number of executed instructions 1977system.cpu2.iew.iewExecLoadInsts 77967 # Number of load instructions executed 1978system.cpu2.iew.iewExecSquashedInsts 1152 # Number of squashed instructions skipped in execute | 1979system.cpu2.iew.predictedNotTakenIncorrect 1069 # Number of branches that were predicted not taken incorrectly 1980system.cpu2.iew.branchMispredicts 1533 # Number of branch mispredicts detected at execute 1981system.cpu2.iew.iewExecutedInsts 215226 # Number of executed instructions 1982system.cpu2.iew.iewExecLoadInsts 70571 # Number of load instructions executed 1983system.cpu2.iew.iewExecSquashedInsts 1110 # Number of squashed instructions skipped in execute |
1979system.cpu2.iew.exec_swp 0 # number of swp insts executed | 1984system.cpu2.iew.exec_swp 0 # number of swp insts executed |
1980system.cpu2.iew.exec_nop 38626 # number of nop insts executed 1981system.cpu2.iew.exec_refs 114664 # number of memory reference insts executed 1982system.cpu2.iew.exec_branches 47841 # Number of branches executed 1983system.cpu2.iew.exec_stores 36697 # Number of stores executed 1984system.cpu2.iew.exec_rate 1.312849 # Inst execution rate 1985system.cpu2.iew.wb_sent 232563 # cumulative count of insts sent to commit 1986system.cpu2.iew.wb_count 232273 # cumulative count of insts written-back 1987system.cpu2.iew.wb_producers 131430 # num instructions producing a value 1988system.cpu2.iew.wb_consumers 136123 # num instructions consuming a value | 1985system.cpu2.iew.exec_nop 34988 # number of nop insts executed 1986system.cpu2.iew.exec_refs 103485 # number of memory reference insts executed 1987system.cpu2.iew.exec_branches 44292 # Number of branches executed 1988system.cpu2.iew.exec_stores 32914 # Number of stores executed 1989system.cpu2.iew.exec_rate 1.284034 # Inst execution rate 1990system.cpu2.iew.wb_sent 214935 # cumulative count of insts sent to commit 1991system.cpu2.iew.wb_count 214628 # cumulative count of insts written-back 1992system.cpu2.iew.wb_producers 121102 # num instructions producing a value 1993system.cpu2.iew.wb_consumers 127756 # num instructions consuming a value |
1989system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1994system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
1990system.cpu2.iew.wb_rate 1.309067 # insts written-back per cycle 1991system.cpu2.iew.wb_fanout 0.965524 # average fanout of values written-back | 1995system.cpu2.iew.wb_rate 1.280467 # insts written-back per cycle 1996system.cpu2.iew.wb_fanout 0.947916 # average fanout of values written-back |
1992system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 1997system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
1993system.cpu2.commit.commitSquashedInsts 12771 # The number of squashed insts skipped by commit 1994system.cpu2.commit.commitNonSpecStalls 5750 # The number of times commit has been forced to stall to communicate backwards 1995system.cpu2.commit.branchMispredicts 1308 # The number of times a branch was mispredicted 1996system.cpu2.commit.committed_per_cycle::samples 162187 # Number of insts commited each cycle 1997system.cpu2.commit.committed_per_cycle::mean 1.630001 # Number of insts commited each cycle 1998system.cpu2.commit.committed_per_cycle::stdev 2.017893 # Number of insts commited each cycle | 1998system.cpu2.commit.commitSquashedInsts 14883 # The number of squashed insts skipped by commit 1999system.cpu2.commit.commitNonSpecStalls 5947 # The number of times commit has been forced to stall to communicate backwards 2000system.cpu2.commit.branchMispredicts 1298 # The number of times a branch was mispredicted 2001system.cpu2.commit.committed_per_cycle::samples 152800 # Number of insts commited each cycle 2002system.cpu2.commit.committed_per_cycle::mean 1.581165 # Number of insts commited each cycle 2003system.cpu2.commit.committed_per_cycle::stdev 2.037167 # Number of insts commited each cycle |
1999system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 2004system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
2000system.cpu2.commit.committed_per_cycle::0 66847 41.22% 41.22% # Number of insts commited each cycle 2001system.cpu2.commit.committed_per_cycle::1 46010 28.37% 69.58% # Number of insts commited each cycle 2002system.cpu2.commit.committed_per_cycle::2 6109 3.77% 73.35% # Number of insts commited each cycle 2003system.cpu2.commit.committed_per_cycle::3 6666 4.11% 77.46% # Number of insts commited each cycle 2004system.cpu2.commit.committed_per_cycle::4 1557 0.96% 78.42% # Number of insts commited each cycle 2005system.cpu2.commit.committed_per_cycle::5 32708 20.17% 98.59% # Number of insts commited each cycle 2006system.cpu2.commit.committed_per_cycle::6 471 0.29% 98.88% # Number of insts commited each cycle 2007system.cpu2.commit.committed_per_cycle::7 1007 0.62% 99.50% # Number of insts commited each cycle 2008system.cpu2.commit.committed_per_cycle::8 812 0.50% 100.00% # Number of insts commited each cycle | 2005system.cpu2.commit.committed_per_cycle::0 66891 43.78% 43.78% # Number of insts commited each cycle 2006system.cpu2.commit.committed_per_cycle::1 41018 26.84% 70.62% # Number of insts commited each cycle 2007system.cpu2.commit.committed_per_cycle::2 5166 3.38% 74.00% # Number of insts commited each cycle 2008system.cpu2.commit.committed_per_cycle::3 6776 4.43% 78.44% # Number of insts commited each cycle 2009system.cpu2.commit.committed_per_cycle::4 1516 0.99% 79.43% # Number of insts commited each cycle 2010system.cpu2.commit.committed_per_cycle::5 28304 18.52% 97.95% # Number of insts commited each cycle 2011system.cpu2.commit.committed_per_cycle::6 869 0.57% 98.52% # Number of insts commited each cycle 2012system.cpu2.commit.committed_per_cycle::7 954 0.62% 99.15% # Number of insts commited each cycle 2013system.cpu2.commit.committed_per_cycle::8 1306 0.85% 100.00% # Number of insts commited each cycle |
2009system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2010system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2011system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 2014system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2015system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2016system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
2012system.cpu2.commit.committed_per_cycle::total 162187 # Number of insts commited each cycle 2013system.cpu2.commit.committedInsts 264365 # Number of instructions committed 2014system.cpu2.commit.committedOps 264365 # Number of ops (including micro ops) committed | 2017system.cpu2.commit.committed_per_cycle::total 152800 # Number of insts commited each cycle 2018system.cpu2.commit.committedInsts 241602 # Number of instructions committed 2019system.cpu2.commit.committedOps 241602 # Number of ops (including micro ops) committed |
2015system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed | 2020system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed |
2016system.cpu2.commit.refs 112522 # Number of memory references committed 2017system.cpu2.commit.loads 76518 # Number of loads committed 2018system.cpu2.commit.membars 5033 # Number of memory barriers committed 2019system.cpu2.commit.branches 47000 # Number of branches committed | 2021system.cpu2.commit.refs 100944 # Number of memory references committed 2022system.cpu2.commit.loads 68867 # Number of loads committed 2023system.cpu2.commit.membars 5232 # Number of memory barriers committed 2024system.cpu2.commit.branches 43270 # Number of branches committed |
2020system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. | 2025system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. |
2021system.cpu2.commit.int_insts 181641 # Number of committed integer instructions. | 2026system.cpu2.commit.int_insts 166336 # Number of committed integer instructions. |
2022system.cpu2.commit.function_calls 322 # Number of function calls committed. | 2027system.cpu2.commit.function_calls 322 # Number of function calls committed. |
2023system.cpu2.commit.op_class_0::No_OpClass 37787 14.29% 14.29% # Class of committed instruction 2024system.cpu2.commit.op_class_0::IntAlu 109023 41.24% 55.53% # Class of committed instruction 2025system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.53% # Class of committed instruction 2026system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.53% # Class of committed instruction 2027system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.53% # Class of committed instruction 2028system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.53% # Class of committed instruction 2029system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.53% # Class of committed instruction 2030system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.53% # Class of committed instruction 2031system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.53% # Class of committed instruction 2032system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.53% # Class of committed instruction 2033system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.53% # Class of committed instruction 2034system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.53% # Class of committed instruction 2035system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.53% # Class of committed instruction 2036system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.53% # Class of committed instruction 2037system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.53% # Class of committed instruction 2038system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.53% # Class of committed instruction 2039system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.53% # Class of committed instruction 2040system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.53% # Class of committed instruction 2041system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.53% # Class of committed instruction 2042system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.53% # Class of committed instruction 2043system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.53% # Class of committed instruction 2044system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.53% # Class of committed instruction 2045system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.53% # Class of committed instruction 2046system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.53% # Class of committed instruction 2047system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.53% # Class of committed instruction 2048system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.53% # Class of committed instruction 2049system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.53% # Class of committed instruction 2050system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.53% # Class of committed instruction 2051system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.53% # Class of committed instruction 2052system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.53% # Class of committed instruction 2053system.cpu2.commit.op_class_0::MemRead 81551 30.85% 86.38% # Class of committed instruction 2054system.cpu2.commit.op_class_0::MemWrite 36004 13.62% 100.00% # Class of committed instruction | 2028system.cpu2.commit.op_class_0::No_OpClass 34059 14.10% 14.10% # Class of committed instruction 2029system.cpu2.commit.op_class_0::IntAlu 101367 41.96% 56.05% # Class of committed instruction 2030system.cpu2.commit.op_class_0::IntMult 0 0.00% 56.05% # Class of committed instruction 2031system.cpu2.commit.op_class_0::IntDiv 0 0.00% 56.05% # Class of committed instruction 2032system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 56.05% # Class of committed instruction 2033system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 56.05% # Class of committed instruction 2034system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 56.05% # Class of committed instruction 2035system.cpu2.commit.op_class_0::FloatMult 0 0.00% 56.05% # Class of committed instruction 2036system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 56.05% # Class of committed instruction 2037system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 56.05% # Class of committed instruction 2038system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 56.05% # Class of committed instruction 2039system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 56.05% # Class of committed instruction 2040system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 56.05% # Class of committed instruction 2041system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 56.05% # Class of committed instruction 2042system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 56.05% # Class of committed instruction 2043system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 56.05% # Class of committed instruction 2044system.cpu2.commit.op_class_0::SimdMult 0 0.00% 56.05% # Class of committed instruction 2045system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 56.05% # Class of committed instruction 2046system.cpu2.commit.op_class_0::SimdShift 0 0.00% 56.05% # Class of committed instruction 2047system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 56.05% # Class of committed instruction 2048system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 56.05% # Class of committed instruction 2049system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 56.05% # Class of committed instruction 2050system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 56.05% # Class of committed instruction 2051system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 56.05% # Class of committed instruction 2052system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 56.05% # Class of committed instruction 2053system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 56.05% # Class of committed instruction 2054system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 56.05% # Class of committed instruction 2055system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 56.05% # Class of committed instruction 2056system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.05% # Class of committed instruction 2057system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.05% # Class of committed instruction 2058system.cpu2.commit.op_class_0::MemRead 74099 30.67% 86.72% # Class of committed instruction 2059system.cpu2.commit.op_class_0::MemWrite 32077 13.28% 100.00% # Class of committed instruction |
2055system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2056system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 2060system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2061system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
2057system.cpu2.commit.op_class_0::total 264365 # Class of committed instruction 2058system.cpu2.commit.bw_lim_events 812 # number cycles where commit BW limit reached | 2062system.cpu2.commit.op_class_0::total 241602 # Class of committed instruction 2063system.cpu2.commit.bw_lim_events 1306 # number cycles where commit BW limit reached |
2059system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits | 2064system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits |
2060system.cpu2.rob.rob_reads 437924 # The number of ROB reads 2061system.cpu2.rob.rob_writes 556709 # The number of ROB writes 2062system.cpu2.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself 2063system.cpu2.idleCycles 5010 # Total number of cycles that the CPU has spent unscheduled due to idling 2064system.cpu2.quiesceCycles 44506 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2065system.cpu2.committedInsts 221545 # Number of Instructions Simulated 2066system.cpu2.committedOps 221545 # Number of Ops (including micro ops) Simulated 2067system.cpu2.cpi 0.800894 # CPI: Cycles Per Instruction 2068system.cpu2.cpi_total 0.800894 # CPI: Total CPI of All Threads 2069system.cpu2.ipc 1.248605 # IPC: Instructions Per Cycle 2070system.cpu2.ipc_total 1.248605 # IPC: Total IPC of All Threads 2071system.cpu2.int_regfile_reads 402715 # number of integer regfile reads 2072system.cpu2.int_regfile_writes 188101 # number of integer regfile writes | 2065system.cpu2.rob.rob_reads 407392 # The number of ROB reads 2066system.cpu2.rob.rob_writes 515662 # The number of ROB writes 2067system.cpu2.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself 2068system.cpu2.idleCycles 5074 # Total number of cycles that the CPU has spent unscheduled due to idling 2069system.cpu2.quiesceCycles 43660 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2070system.cpu2.committedInsts 202311 # Number of Instructions Simulated 2071system.cpu2.committedOps 202311 # Number of Ops (including micro ops) Simulated 2072system.cpu2.cpi 0.828512 # CPI: Cycles Per Instruction 2073system.cpu2.cpi_total 0.828512 # CPI: Total CPI of All Threads 2074system.cpu2.ipc 1.206984 # IPC: Instructions Per Cycle 2075system.cpu2.ipc_total 1.206984 # IPC: Total IPC of All Threads 2076system.cpu2.int_regfile_reads 370344 # number of integer regfile reads 2077system.cpu2.int_regfile_writes 173891 # number of integer regfile writes |
2073system.cpu2.fp_regfile_writes 64 # number of floating regfile writes | 2078system.cpu2.fp_regfile_writes 64 # number of floating regfile writes |
2074system.cpu2.misc_regfile_reads 116228 # number of misc regfile reads | 2079system.cpu2.misc_regfile_reads 105089 # number of misc regfile reads |
2075system.cpu2.misc_regfile_writes 648 # number of misc regfile writes | 2080system.cpu2.misc_regfile_writes 648 # number of misc regfile writes |
2076system.cpu2.icache.tags.replacements 317 # number of replacements 2077system.cpu2.icache.tags.tagsinuse 81.450670 # Cycle average of tags in use 2078system.cpu2.icache.tags.total_refs 19300 # Total number of references to valid blocks. 2079system.cpu2.icache.tags.sampled_refs 424 # Sample count of references to valid blocks. 2080system.cpu2.icache.tags.avg_refs 45.518868 # Average number of references to valid blocks. | 2081system.cpu2.icache.tags.replacements 378 # number of replacements 2082system.cpu2.icache.tags.tagsinuse 84.908829 # Cycle average of tags in use 2083system.cpu2.icache.tags.total_refs 21796 # Total number of references to valid blocks. 2084system.cpu2.icache.tags.sampled_refs 490 # Sample count of references to valid blocks. 2085system.cpu2.icache.tags.avg_refs 44.481633 # Average number of references to valid blocks. |
2081system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2086system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
2082system.cpu2.icache.tags.occ_blocks::cpu2.inst 81.450670 # Average occupied blocks per requestor 2083system.cpu2.icache.tags.occ_percent::cpu2.inst 0.159083 # Average percentage of cache occupancy 2084system.cpu2.icache.tags.occ_percent::total 0.159083 # Average percentage of cache occupancy 2085system.cpu2.icache.tags.occ_task_id_blocks::1024 107 # Occupied blocks per task id | 2087system.cpu2.icache.tags.occ_blocks::cpu2.inst 84.908829 # Average occupied blocks per requestor 2088system.cpu2.icache.tags.occ_percent::cpu2.inst 0.165838 # Average percentage of cache occupancy 2089system.cpu2.icache.tags.occ_percent::total 0.165838 # Average percentage of cache occupancy 2090system.cpu2.icache.tags.occ_task_id_blocks::1024 112 # Occupied blocks per task id |
2086system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id | 2091system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id |
2087system.cpu2.icache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id 2088system.cpu2.icache.tags.occ_task_id_percent::1024 0.208984 # Percentage of cache occupancy per task id 2089system.cpu2.icache.tags.tag_accesses 20212 # Number of tag accesses 2090system.cpu2.icache.tags.data_accesses 20212 # Number of data accesses 2091system.cpu2.icache.ReadReq_hits::cpu2.inst 19300 # number of ReadReq hits 2092system.cpu2.icache.ReadReq_hits::total 19300 # number of ReadReq hits 2093system.cpu2.icache.demand_hits::cpu2.inst 19300 # number of demand (read+write) hits 2094system.cpu2.icache.demand_hits::total 19300 # number of demand (read+write) hits 2095system.cpu2.icache.overall_hits::cpu2.inst 19300 # number of overall hits 2096system.cpu2.icache.overall_hits::total 19300 # number of overall hits 2097system.cpu2.icache.ReadReq_misses::cpu2.inst 488 # number of ReadReq misses 2098system.cpu2.icache.ReadReq_misses::total 488 # number of ReadReq misses 2099system.cpu2.icache.demand_misses::cpu2.inst 488 # number of demand (read+write) misses 2100system.cpu2.icache.demand_misses::total 488 # number of demand (read+write) misses 2101system.cpu2.icache.overall_misses::cpu2.inst 488 # number of overall misses 2102system.cpu2.icache.overall_misses::total 488 # number of overall misses 2103system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11534741 # number of ReadReq miss cycles 2104system.cpu2.icache.ReadReq_miss_latency::total 11534741 # number of ReadReq miss cycles 2105system.cpu2.icache.demand_miss_latency::cpu2.inst 11534741 # number of demand (read+write) miss cycles 2106system.cpu2.icache.demand_miss_latency::total 11534741 # number of demand (read+write) miss cycles 2107system.cpu2.icache.overall_miss_latency::cpu2.inst 11534741 # number of overall miss cycles 2108system.cpu2.icache.overall_miss_latency::total 11534741 # number of overall miss cycles 2109system.cpu2.icache.ReadReq_accesses::cpu2.inst 19788 # number of ReadReq accesses(hits+misses) 2110system.cpu2.icache.ReadReq_accesses::total 19788 # number of ReadReq accesses(hits+misses) 2111system.cpu2.icache.demand_accesses::cpu2.inst 19788 # number of demand (read+write) accesses 2112system.cpu2.icache.demand_accesses::total 19788 # number of demand (read+write) accesses 2113system.cpu2.icache.overall_accesses::cpu2.inst 19788 # number of overall (read+write) accesses 2114system.cpu2.icache.overall_accesses::total 19788 # number of overall (read+write) accesses 2115system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024661 # miss rate for ReadReq accesses 2116system.cpu2.icache.ReadReq_miss_rate::total 0.024661 # miss rate for ReadReq accesses 2117system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024661 # miss rate for demand accesses 2118system.cpu2.icache.demand_miss_rate::total 0.024661 # miss rate for demand accesses 2119system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024661 # miss rate for overall accesses 2120system.cpu2.icache.overall_miss_rate::total 0.024661 # miss rate for overall accesses 2121system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23636.764344 # average ReadReq miss latency 2122system.cpu2.icache.ReadReq_avg_miss_latency::total 23636.764344 # average ReadReq miss latency 2123system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23636.764344 # average overall miss latency 2124system.cpu2.icache.demand_avg_miss_latency::total 23636.764344 # average overall miss latency 2125system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23636.764344 # average overall miss latency 2126system.cpu2.icache.overall_avg_miss_latency::total 23636.764344 # average overall miss latency 2127system.cpu2.icache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked | 2092system.cpu2.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id 2093system.cpu2.icache.tags.occ_task_id_percent::1024 0.218750 # Percentage of cache occupancy per task id 2094system.cpu2.icache.tags.tag_accesses 22856 # Number of tag accesses 2095system.cpu2.icache.tags.data_accesses 22856 # Number of data accesses 2096system.cpu2.icache.ReadReq_hits::cpu2.inst 21796 # number of ReadReq hits 2097system.cpu2.icache.ReadReq_hits::total 21796 # number of ReadReq hits 2098system.cpu2.icache.demand_hits::cpu2.inst 21796 # number of demand (read+write) hits 2099system.cpu2.icache.demand_hits::total 21796 # number of demand (read+write) hits 2100system.cpu2.icache.overall_hits::cpu2.inst 21796 # number of overall hits 2101system.cpu2.icache.overall_hits::total 21796 # number of overall hits 2102system.cpu2.icache.ReadReq_misses::cpu2.inst 570 # number of ReadReq misses 2103system.cpu2.icache.ReadReq_misses::total 570 # number of ReadReq misses 2104system.cpu2.icache.demand_misses::cpu2.inst 570 # number of demand (read+write) misses 2105system.cpu2.icache.demand_misses::total 570 # number of demand (read+write) misses 2106system.cpu2.icache.overall_misses::cpu2.inst 570 # number of overall misses 2107system.cpu2.icache.overall_misses::total 570 # number of overall misses 2108system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 13348494 # number of ReadReq miss cycles 2109system.cpu2.icache.ReadReq_miss_latency::total 13348494 # number of ReadReq miss cycles 2110system.cpu2.icache.demand_miss_latency::cpu2.inst 13348494 # number of demand (read+write) miss cycles 2111system.cpu2.icache.demand_miss_latency::total 13348494 # number of demand (read+write) miss cycles 2112system.cpu2.icache.overall_miss_latency::cpu2.inst 13348494 # number of overall miss cycles 2113system.cpu2.icache.overall_miss_latency::total 13348494 # number of overall miss cycles 2114system.cpu2.icache.ReadReq_accesses::cpu2.inst 22366 # number of ReadReq accesses(hits+misses) 2115system.cpu2.icache.ReadReq_accesses::total 22366 # number of ReadReq accesses(hits+misses) 2116system.cpu2.icache.demand_accesses::cpu2.inst 22366 # number of demand (read+write) accesses 2117system.cpu2.icache.demand_accesses::total 22366 # number of demand (read+write) accesses 2118system.cpu2.icache.overall_accesses::cpu2.inst 22366 # number of overall (read+write) accesses 2119system.cpu2.icache.overall_accesses::total 22366 # number of overall (read+write) accesses 2120system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.025485 # miss rate for ReadReq accesses 2121system.cpu2.icache.ReadReq_miss_rate::total 0.025485 # miss rate for ReadReq accesses 2122system.cpu2.icache.demand_miss_rate::cpu2.inst 0.025485 # miss rate for demand accesses 2123system.cpu2.icache.demand_miss_rate::total 0.025485 # miss rate for demand accesses 2124system.cpu2.icache.overall_miss_rate::cpu2.inst 0.025485 # miss rate for overall accesses 2125system.cpu2.icache.overall_miss_rate::total 0.025485 # miss rate for overall accesses 2126system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23418.410526 # average ReadReq miss latency 2127system.cpu2.icache.ReadReq_avg_miss_latency::total 23418.410526 # average ReadReq miss latency 2128system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23418.410526 # average overall miss latency 2129system.cpu2.icache.demand_avg_miss_latency::total 23418.410526 # average overall miss latency 2130system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23418.410526 # average overall miss latency 2131system.cpu2.icache.overall_avg_miss_latency::total 23418.410526 # average overall miss latency 2132system.cpu2.icache.blocked_cycles::no_mshrs 128 # number of cycles access was blocked |
2128system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2133system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
2129system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked | 2134system.cpu2.icache.blocked::no_mshrs 3 # number of cycles access was blocked |
2130system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked | 2135system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked |
2131system.cpu2.icache.avg_blocked_cycles::no_mshrs 85 # average number of cycles each access was blocked | 2136system.cpu2.icache.avg_blocked_cycles::no_mshrs 42.666667 # average number of cycles each access was blocked |
2132system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2133system.cpu2.icache.fast_writes 0 # number of fast writes performed 2134system.cpu2.icache.cache_copies 0 # number of cache copies performed | 2137system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2138system.cpu2.icache.fast_writes 0 # number of fast writes performed 2139system.cpu2.icache.cache_copies 0 # number of cache copies performed |
2135system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 64 # number of ReadReq MSHR hits 2136system.cpu2.icache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits 2137system.cpu2.icache.demand_mshr_hits::cpu2.inst 64 # number of demand (read+write) MSHR hits 2138system.cpu2.icache.demand_mshr_hits::total 64 # number of demand (read+write) MSHR hits 2139system.cpu2.icache.overall_mshr_hits::cpu2.inst 64 # number of overall MSHR hits 2140system.cpu2.icache.overall_mshr_hits::total 64 # number of overall MSHR hits 2141system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 424 # number of ReadReq MSHR misses 2142system.cpu2.icache.ReadReq_mshr_misses::total 424 # number of ReadReq MSHR misses 2143system.cpu2.icache.demand_mshr_misses::cpu2.inst 424 # number of demand (read+write) MSHR misses 2144system.cpu2.icache.demand_mshr_misses::total 424 # number of demand (read+write) MSHR misses 2145system.cpu2.icache.overall_mshr_misses::cpu2.inst 424 # number of overall MSHR misses 2146system.cpu2.icache.overall_mshr_misses::total 424 # number of overall MSHR misses 2147system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9234505 # number of ReadReq MSHR miss cycles 2148system.cpu2.icache.ReadReq_mshr_miss_latency::total 9234505 # number of ReadReq MSHR miss cycles 2149system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9234505 # number of demand (read+write) MSHR miss cycles 2150system.cpu2.icache.demand_mshr_miss_latency::total 9234505 # number of demand (read+write) MSHR miss cycles 2151system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9234505 # number of overall MSHR miss cycles 2152system.cpu2.icache.overall_mshr_miss_latency::total 9234505 # number of overall MSHR miss cycles 2153system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021427 # mshr miss rate for ReadReq accesses 2154system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021427 # mshr miss rate for ReadReq accesses 2155system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021427 # mshr miss rate for demand accesses 2156system.cpu2.icache.demand_mshr_miss_rate::total 0.021427 # mshr miss rate for demand accesses 2157system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021427 # mshr miss rate for overall accesses 2158system.cpu2.icache.overall_mshr_miss_rate::total 0.021427 # mshr miss rate for overall accesses 2159system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21779.492925 # average ReadReq mshr miss latency 2160system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21779.492925 # average ReadReq mshr miss latency 2161system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21779.492925 # average overall mshr miss latency 2162system.cpu2.icache.demand_avg_mshr_miss_latency::total 21779.492925 # average overall mshr miss latency 2163system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21779.492925 # average overall mshr miss latency 2164system.cpu2.icache.overall_avg_mshr_miss_latency::total 21779.492925 # average overall mshr miss latency | 2140system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 80 # number of ReadReq MSHR hits 2141system.cpu2.icache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits 2142system.cpu2.icache.demand_mshr_hits::cpu2.inst 80 # number of demand (read+write) MSHR hits 2143system.cpu2.icache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits 2144system.cpu2.icache.overall_mshr_hits::cpu2.inst 80 # number of overall MSHR hits 2145system.cpu2.icache.overall_mshr_hits::total 80 # number of overall MSHR hits 2146system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 490 # number of ReadReq MSHR misses 2147system.cpu2.icache.ReadReq_mshr_misses::total 490 # number of ReadReq MSHR misses 2148system.cpu2.icache.demand_mshr_misses::cpu2.inst 490 # number of demand (read+write) MSHR misses 2149system.cpu2.icache.demand_mshr_misses::total 490 # number of demand (read+write) MSHR misses 2150system.cpu2.icache.overall_mshr_misses::cpu2.inst 490 # number of overall MSHR misses 2151system.cpu2.icache.overall_mshr_misses::total 490 # number of overall MSHR misses 2152system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10380255 # number of ReadReq MSHR miss cycles 2153system.cpu2.icache.ReadReq_mshr_miss_latency::total 10380255 # number of ReadReq MSHR miss cycles 2154system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10380255 # number of demand (read+write) MSHR miss cycles 2155system.cpu2.icache.demand_mshr_miss_latency::total 10380255 # number of demand (read+write) MSHR miss cycles 2156system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10380255 # number of overall MSHR miss cycles 2157system.cpu2.icache.overall_mshr_miss_latency::total 10380255 # number of overall MSHR miss cycles 2158system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021908 # mshr miss rate for ReadReq accesses 2159system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021908 # mshr miss rate for ReadReq accesses 2160system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021908 # mshr miss rate for demand accesses 2161system.cpu2.icache.demand_mshr_miss_rate::total 0.021908 # mshr miss rate for demand accesses 2162system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021908 # mshr miss rate for overall accesses 2163system.cpu2.icache.overall_mshr_miss_rate::total 0.021908 # mshr miss rate for overall accesses 2164system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21184.193878 # average ReadReq mshr miss latency 2165system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21184.193878 # average ReadReq mshr miss latency 2166system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21184.193878 # average overall mshr miss latency 2167system.cpu2.icache.demand_avg_mshr_miss_latency::total 21184.193878 # average overall mshr miss latency 2168system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21184.193878 # average overall mshr miss latency 2169system.cpu2.icache.overall_avg_mshr_miss_latency::total 21184.193878 # average overall mshr miss latency |
2165system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2166system.cpu2.dcache.tags.replacements 0 # number of replacements | 2170system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2171system.cpu2.dcache.tags.replacements 0 # number of replacements |
2167system.cpu2.dcache.tags.tagsinuse 26.136002 # Cycle average of tags in use 2168system.cpu2.dcache.tags.total_refs 42041 # Total number of references to valid blocks. | 2172system.cpu2.dcache.tags.tagsinuse 25.893249 # Cycle average of tags in use 2173system.cpu2.dcache.tags.total_refs 38186 # Total number of references to valid blocks. |
2169system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. | 2174system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. |
2170system.cpu2.dcache.tags.avg_refs 1501.464286 # Average number of references to valid blocks. | 2175system.cpu2.dcache.tags.avg_refs 1363.785714 # Average number of references to valid blocks. |
2171system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2176system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
2172system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.136002 # Average occupied blocks per requestor 2173system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051047 # Average percentage of cache occupancy 2174system.cpu2.dcache.tags.occ_percent::total 0.051047 # Average percentage of cache occupancy | 2177system.cpu2.dcache.tags.occ_blocks::cpu2.data 25.893249 # Average occupied blocks per requestor 2178system.cpu2.dcache.tags.occ_percent::cpu2.data 0.050573 # Average percentage of cache occupancy 2179system.cpu2.dcache.tags.occ_percent::total 0.050573 # Average percentage of cache occupancy |
2175system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id 2176system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 2177system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id | 2180system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id 2181system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 2182system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id |
2178system.cpu2.dcache.tags.tag_accesses 327476 # Number of tag accesses 2179system.cpu2.dcache.tags.data_accesses 327476 # Number of data accesses 2180system.cpu2.dcache.ReadReq_hits::cpu2.data 45457 # number of ReadReq hits 2181system.cpu2.dcache.ReadReq_hits::total 45457 # number of ReadReq hits 2182system.cpu2.dcache.WriteReq_hits::cpu2.data 35794 # number of WriteReq hits 2183system.cpu2.dcache.WriteReq_hits::total 35794 # number of WriteReq hits 2184system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits 2185system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits 2186system.cpu2.dcache.demand_hits::cpu2.data 81251 # number of demand (read+write) hits 2187system.cpu2.dcache.demand_hits::total 81251 # number of demand (read+write) hits 2188system.cpu2.dcache.overall_hits::cpu2.data 81251 # number of overall hits 2189system.cpu2.dcache.overall_hits::total 81251 # number of overall hits 2190system.cpu2.dcache.ReadReq_misses::cpu2.data 345 # number of ReadReq misses 2191system.cpu2.dcache.ReadReq_misses::total 345 # number of ReadReq misses 2192system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses 2193system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses 2194system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses 2195system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses 2196system.cpu2.dcache.demand_misses::cpu2.data 484 # number of demand (read+write) misses 2197system.cpu2.dcache.demand_misses::total 484 # number of demand (read+write) misses 2198system.cpu2.dcache.overall_misses::cpu2.data 484 # number of overall misses 2199system.cpu2.dcache.overall_misses::total 484 # number of overall misses 2200system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5375808 # number of ReadReq miss cycles 2201system.cpu2.dcache.ReadReq_miss_latency::total 5375808 # number of ReadReq miss cycles 2202system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3387510 # number of WriteReq miss cycles 2203system.cpu2.dcache.WriteReq_miss_latency::total 3387510 # number of WriteReq miss cycles 2204system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 561006 # number of SwapReq miss cycles 2205system.cpu2.dcache.SwapReq_miss_latency::total 561006 # number of SwapReq miss cycles 2206system.cpu2.dcache.demand_miss_latency::cpu2.data 8763318 # number of demand (read+write) miss cycles 2207system.cpu2.dcache.demand_miss_latency::total 8763318 # number of demand (read+write) miss cycles 2208system.cpu2.dcache.overall_miss_latency::cpu2.data 8763318 # number of overall miss cycles 2209system.cpu2.dcache.overall_miss_latency::total 8763318 # number of overall miss cycles 2210system.cpu2.dcache.ReadReq_accesses::cpu2.data 45802 # number of ReadReq accesses(hits+misses) 2211system.cpu2.dcache.ReadReq_accesses::total 45802 # number of ReadReq accesses(hits+misses) 2212system.cpu2.dcache.WriteReq_accesses::cpu2.data 35933 # number of WriteReq accesses(hits+misses) 2213system.cpu2.dcache.WriteReq_accesses::total 35933 # number of WriteReq accesses(hits+misses) 2214system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) 2215system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) 2216system.cpu2.dcache.demand_accesses::cpu2.data 81735 # number of demand (read+write) accesses 2217system.cpu2.dcache.demand_accesses::total 81735 # number of demand (read+write) accesses 2218system.cpu2.dcache.overall_accesses::cpu2.data 81735 # number of overall (read+write) accesses 2219system.cpu2.dcache.overall_accesses::total 81735 # number of overall (read+write) accesses 2220system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.007532 # miss rate for ReadReq accesses 2221system.cpu2.dcache.ReadReq_miss_rate::total 0.007532 # miss rate for ReadReq accesses 2222system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003868 # miss rate for WriteReq accesses 2223system.cpu2.dcache.WriteReq_miss_rate::total 0.003868 # miss rate for WriteReq accesses 2224system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.816901 # miss rate for SwapReq accesses 2225system.cpu2.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses 2226system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005922 # miss rate for demand accesses 2227system.cpu2.dcache.demand_miss_rate::total 0.005922 # miss rate for demand accesses 2228system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005922 # miss rate for overall accesses 2229system.cpu2.dcache.overall_miss_rate::total 0.005922 # miss rate for overall accesses 2230system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15582.052174 # average ReadReq miss latency 2231system.cpu2.dcache.ReadReq_avg_miss_latency::total 15582.052174 # average ReadReq miss latency 2232system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24370.575540 # average WriteReq miss latency 2233system.cpu2.dcache.WriteReq_avg_miss_latency::total 24370.575540 # average WriteReq miss latency 2234system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9672.517241 # average SwapReq miss latency 2235system.cpu2.dcache.SwapReq_avg_miss_latency::total 9672.517241 # average SwapReq miss latency 2236system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 18106.028926 # average overall miss latency 2237system.cpu2.dcache.demand_avg_miss_latency::total 18106.028926 # average overall miss latency 2238system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 18106.028926 # average overall miss latency 2239system.cpu2.dcache.overall_avg_miss_latency::total 18106.028926 # average overall miss latency | 2183system.cpu2.dcache.tags.tag_accesses 297518 # Number of tag accesses 2184system.cpu2.dcache.tags.data_accesses 297518 # Number of data accesses 2185system.cpu2.dcache.ReadReq_hits::cpu2.data 41817 # number of ReadReq hits 2186system.cpu2.dcache.ReadReq_hits::total 41817 # number of ReadReq hits 2187system.cpu2.dcache.WriteReq_hits::cpu2.data 31862 # number of WriteReq hits 2188system.cpu2.dcache.WriteReq_hits::total 31862 # number of WriteReq hits 2189system.cpu2.dcache.SwapReq_hits::cpu2.data 14 # number of SwapReq hits 2190system.cpu2.dcache.SwapReq_hits::total 14 # number of SwapReq hits 2191system.cpu2.dcache.demand_hits::cpu2.data 73679 # number of demand (read+write) hits 2192system.cpu2.dcache.demand_hits::total 73679 # number of demand (read+write) hits 2193system.cpu2.dcache.overall_hits::cpu2.data 73679 # number of overall hits 2194system.cpu2.dcache.overall_hits::total 73679 # number of overall hits 2195system.cpu2.dcache.ReadReq_misses::cpu2.data 422 # number of ReadReq misses 2196system.cpu2.dcache.ReadReq_misses::total 422 # number of ReadReq misses 2197system.cpu2.dcache.WriteReq_misses::cpu2.data 146 # number of WriteReq misses 2198system.cpu2.dcache.WriteReq_misses::total 146 # number of WriteReq misses 2199system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses 2200system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses 2201system.cpu2.dcache.demand_misses::cpu2.data 568 # number of demand (read+write) misses 2202system.cpu2.dcache.demand_misses::total 568 # number of demand (read+write) misses 2203system.cpu2.dcache.overall_misses::cpu2.data 568 # number of overall misses 2204system.cpu2.dcache.overall_misses::total 568 # number of overall misses 2205system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7291559 # number of ReadReq miss cycles 2206system.cpu2.dcache.ReadReq_miss_latency::total 7291559 # number of ReadReq miss cycles 2207system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3658011 # number of WriteReq miss cycles 2208system.cpu2.dcache.WriteReq_miss_latency::total 3658011 # number of WriteReq miss cycles 2209system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 499506 # number of SwapReq miss cycles 2210system.cpu2.dcache.SwapReq_miss_latency::total 499506 # number of SwapReq miss cycles 2211system.cpu2.dcache.demand_miss_latency::cpu2.data 10949570 # number of demand (read+write) miss cycles 2212system.cpu2.dcache.demand_miss_latency::total 10949570 # number of demand (read+write) miss cycles 2213system.cpu2.dcache.overall_miss_latency::cpu2.data 10949570 # number of overall miss cycles 2214system.cpu2.dcache.overall_miss_latency::total 10949570 # number of overall miss cycles 2215system.cpu2.dcache.ReadReq_accesses::cpu2.data 42239 # number of ReadReq accesses(hits+misses) 2216system.cpu2.dcache.ReadReq_accesses::total 42239 # number of ReadReq accesses(hits+misses) 2217system.cpu2.dcache.WriteReq_accesses::cpu2.data 32008 # number of WriteReq accesses(hits+misses) 2218system.cpu2.dcache.WriteReq_accesses::total 32008 # number of WriteReq accesses(hits+misses) 2219system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) 2220system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) 2221system.cpu2.dcache.demand_accesses::cpu2.data 74247 # number of demand (read+write) accesses 2222system.cpu2.dcache.demand_accesses::total 74247 # number of demand (read+write) accesses 2223system.cpu2.dcache.overall_accesses::cpu2.data 74247 # number of overall (read+write) accesses 2224system.cpu2.dcache.overall_accesses::total 74247 # number of overall (read+write) accesses 2225system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009991 # miss rate for ReadReq accesses 2226system.cpu2.dcache.ReadReq_miss_rate::total 0.009991 # miss rate for ReadReq accesses 2227system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004561 # miss rate for WriteReq accesses 2228system.cpu2.dcache.WriteReq_miss_rate::total 0.004561 # miss rate for WriteReq accesses 2229system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.797101 # miss rate for SwapReq accesses 2230system.cpu2.dcache.SwapReq_miss_rate::total 0.797101 # miss rate for SwapReq accesses 2231system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007650 # miss rate for demand accesses 2232system.cpu2.dcache.demand_miss_rate::total 0.007650 # miss rate for demand accesses 2233system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007650 # miss rate for overall accesses 2234system.cpu2.dcache.overall_miss_rate::total 0.007650 # miss rate for overall accesses 2235system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17278.575829 # average ReadReq miss latency 2236system.cpu2.dcache.ReadReq_avg_miss_latency::total 17278.575829 # average ReadReq miss latency 2237system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 25054.869863 # average WriteReq miss latency 2238system.cpu2.dcache.WriteReq_avg_miss_latency::total 25054.869863 # average WriteReq miss latency 2239system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9081.927273 # average SwapReq miss latency 2240system.cpu2.dcache.SwapReq_avg_miss_latency::total 9081.927273 # average SwapReq miss latency 2241system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 19277.411972 # average overall miss latency 2242system.cpu2.dcache.demand_avg_miss_latency::total 19277.411972 # average overall miss latency 2243system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 19277.411972 # average overall miss latency 2244system.cpu2.dcache.overall_avg_miss_latency::total 19277.411972 # average overall miss latency |
2240system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2241system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2242system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2243system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 2244system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2245system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2246system.cpu2.dcache.fast_writes 0 # number of fast writes performed 2247system.cpu2.dcache.cache_copies 0 # number of cache copies performed | 2245system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2246system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2247system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2248system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 2249system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2250system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2251system.cpu2.dcache.fast_writes 0 # number of fast writes performed 2252system.cpu2.dcache.cache_copies 0 # number of cache copies performed |
2248system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 184 # number of ReadReq MSHR hits 2249system.cpu2.dcache.ReadReq_mshr_hits::total 184 # number of ReadReq MSHR hits 2250system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 33 # number of WriteReq MSHR hits 2251system.cpu2.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits 2252system.cpu2.dcache.demand_mshr_hits::cpu2.data 217 # number of demand (read+write) MSHR hits 2253system.cpu2.dcache.demand_mshr_hits::total 217 # number of demand (read+write) MSHR hits 2254system.cpu2.dcache.overall_mshr_hits::cpu2.data 217 # number of overall MSHR hits 2255system.cpu2.dcache.overall_mshr_hits::total 217 # number of overall MSHR hits | 2253system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 261 # number of ReadReq MSHR hits 2254system.cpu2.dcache.ReadReq_mshr_hits::total 261 # number of ReadReq MSHR hits 2255system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 40 # number of WriteReq MSHR hits 2256system.cpu2.dcache.WriteReq_mshr_hits::total 40 # number of WriteReq MSHR hits 2257system.cpu2.dcache.demand_mshr_hits::cpu2.data 301 # number of demand (read+write) MSHR hits 2258system.cpu2.dcache.demand_mshr_hits::total 301 # number of demand (read+write) MSHR hits 2259system.cpu2.dcache.overall_mshr_hits::cpu2.data 301 # number of overall MSHR hits 2260system.cpu2.dcache.overall_mshr_hits::total 301 # number of overall MSHR hits |
2256system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses 2257system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses 2258system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses 2259system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses | 2261system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses 2262system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses 2263system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses 2264system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses |
2260system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses 2261system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses | 2265system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 55 # number of SwapReq MSHR misses 2266system.cpu2.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses |
2262system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses 2263system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses 2264system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses 2265system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses | 2267system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses 2268system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses 2269system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses 2270system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses |
2266system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1467781 # number of ReadReq MSHR miss cycles 2267system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1467781 # number of ReadReq MSHR miss cycles 2268system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1796490 # number of WriteReq MSHR miss cycles 2269system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1796490 # number of WriteReq MSHR miss cycles 2270system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 444994 # number of SwapReq MSHR miss cycles 2271system.cpu2.dcache.SwapReq_mshr_miss_latency::total 444994 # number of SwapReq MSHR miss cycles 2272system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3264271 # number of demand (read+write) MSHR miss cycles 2273system.cpu2.dcache.demand_mshr_miss_latency::total 3264271 # number of demand (read+write) MSHR miss cycles 2274system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3264271 # number of overall MSHR miss cycles 2275system.cpu2.dcache.overall_mshr_miss_latency::total 3264271 # number of overall MSHR miss cycles 2276system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003515 # mshr miss rate for ReadReq accesses 2277system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003515 # mshr miss rate for ReadReq accesses 2278system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002950 # mshr miss rate for WriteReq accesses 2279system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002950 # mshr miss rate for WriteReq accesses 2280system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.816901 # mshr miss rate for SwapReq accesses 2281system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses 2282system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003267 # mshr miss rate for demand accesses 2283system.cpu2.dcache.demand_mshr_miss_rate::total 0.003267 # mshr miss rate for demand accesses 2284system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003267 # mshr miss rate for overall accesses 2285system.cpu2.dcache.overall_mshr_miss_rate::total 0.003267 # mshr miss rate for overall accesses 2286system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9116.652174 # average ReadReq mshr miss latency 2287system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9116.652174 # average ReadReq mshr miss latency 2288system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16948.018868 # average WriteReq mshr miss latency 2289system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16948.018868 # average WriteReq mshr miss latency 2290system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7672.310345 # average SwapReq mshr miss latency 2291system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7672.310345 # average SwapReq mshr miss latency 2292system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12225.734082 # average overall mshr miss latency 2293system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12225.734082 # average overall mshr miss latency 2294system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12225.734082 # average overall mshr miss latency 2295system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12225.734082 # average overall mshr miss latency | 2271system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1541774 # number of ReadReq MSHR miss cycles 2272system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1541774 # number of ReadReq MSHR miss cycles 2273system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1509739 # number of WriteReq MSHR miss cycles 2274system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1509739 # number of WriteReq MSHR miss cycles 2275system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 389494 # number of SwapReq MSHR miss cycles 2276system.cpu2.dcache.SwapReq_mshr_miss_latency::total 389494 # number of SwapReq MSHR miss cycles 2277system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3051513 # number of demand (read+write) MSHR miss cycles 2278system.cpu2.dcache.demand_mshr_miss_latency::total 3051513 # number of demand (read+write) MSHR miss cycles 2279system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3051513 # number of overall MSHR miss cycles 2280system.cpu2.dcache.overall_mshr_miss_latency::total 3051513 # number of overall MSHR miss cycles 2281system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003812 # mshr miss rate for ReadReq accesses 2282system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003812 # mshr miss rate for ReadReq accesses 2283system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003312 # mshr miss rate for WriteReq accesses 2284system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003312 # mshr miss rate for WriteReq accesses 2285system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.797101 # mshr miss rate for SwapReq accesses 2286system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.797101 # mshr miss rate for SwapReq accesses 2287system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003596 # mshr miss rate for demand accesses 2288system.cpu2.dcache.demand_mshr_miss_rate::total 0.003596 # mshr miss rate for demand accesses 2289system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003596 # mshr miss rate for overall accesses 2290system.cpu2.dcache.overall_mshr_miss_rate::total 0.003596 # mshr miss rate for overall accesses 2291system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9576.236025 # average ReadReq mshr miss latency 2292system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9576.236025 # average ReadReq mshr miss latency 2293system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14242.820755 # average WriteReq mshr miss latency 2294system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14242.820755 # average WriteReq mshr miss latency 2295system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7081.709091 # average SwapReq mshr miss latency 2296system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7081.709091 # average SwapReq mshr miss latency 2297system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11428.887640 # average overall mshr miss latency 2298system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11428.887640 # average overall mshr miss latency 2299system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11428.887640 # average overall mshr miss latency 2300system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11428.887640 # average overall mshr miss latency |
2296system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 2301system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
2297system.cpu3.branchPred.lookups 47572 # Number of BP lookups 2298system.cpu3.branchPred.condPredicted 44838 # Number of conditional branches predicted 2299system.cpu3.branchPred.condIncorrect 1269 # Number of conditional branches incorrect 2300system.cpu3.branchPred.BTBLookups 41556 # Number of BTB lookups 2301system.cpu3.branchPred.BTBHits 40675 # Number of BTB hits | 2302system.cpu3.branchPred.lookups 48151 # Number of BP lookups 2303system.cpu3.branchPred.condPredicted 44685 # Number of conditional branches predicted 2304system.cpu3.branchPred.condIncorrect 1287 # Number of conditional branches incorrect 2305system.cpu3.branchPred.BTBLookups 41038 # Number of BTB lookups 2306system.cpu3.branchPred.BTBHits 39836 # Number of BTB hits |
2302system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 2307system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
2303system.cpu3.branchPred.BTBHitPct 97.879969 # BTB Hit Percentage 2304system.cpu3.branchPred.usedRAS 650 # Number of times the RAS was used to get a target. 2305system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. 2306system.cpu3.numCycles 177088 # number of cpu cycles simulated | 2308system.cpu3.branchPred.BTBHitPct 97.071007 # BTB Hit Percentage 2309system.cpu3.branchPred.usedRAS 888 # Number of times the RAS was used to get a target. 2310system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. 2311system.cpu3.numCycles 167273 # number of cpu cycles simulated |
2307system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 2308system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed | 2312system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 2313system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed |
2309system.cpu3.fetch.icacheStallCycles 31611 # Number of cycles fetch is stalled on an Icache miss 2310system.cpu3.fetch.Insts 260615 # Number of instructions fetch has processed 2311system.cpu3.fetch.Branches 47572 # Number of branches that fetch encountered 2312system.cpu3.fetch.predictedBranches 41325 # Number of branches that fetch has predicted taken 2313system.cpu3.fetch.Cycles 95272 # Number of cycles fetch has run and was not squashing or blocked 2314system.cpu3.fetch.SquashCycles 3721 # Number of cycles fetch has spent squashing 2315system.cpu3.fetch.BlockedCycles 37783 # Number of cycles fetch has spent blocked 2316system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2317system.cpu3.fetch.NoActiveThreadStallCycles 7803 # Number of stall cycles due to no active thread to fetch from 2318system.cpu3.fetch.PendingTrapStallCycles 790 # Number of stall cycles due to pending traps 2319system.cpu3.fetch.CacheLines 23344 # Number of cache lines fetched 2320system.cpu3.fetch.IcacheSquashes 257 # Number of outstanding Icache misses that were squashed 2321system.cpu3.fetch.rateDist::samples 175638 # Number of instructions fetched each cycle (Total) 2322system.cpu3.fetch.rateDist::mean 1.483819 # Number of instructions fetched each cycle (Total) 2323system.cpu3.fetch.rateDist::stdev 2.061741 # Number of instructions fetched each cycle (Total) | 2314system.cpu3.fetch.icacheStallCycles 33692 # Number of cycles fetch is stalled on an Icache miss 2315system.cpu3.fetch.Insts 260486 # Number of instructions fetch has processed 2316system.cpu3.fetch.Branches 48151 # Number of branches that fetch encountered 2317system.cpu3.fetch.predictedBranches 40724 # Number of branches that fetch has predicted taken 2318system.cpu3.fetch.Cycles 122974 # Number of cycles fetch has run and was not squashing or blocked 2319system.cpu3.fetch.SquashCycles 2726 # Number of cycles fetch has spent squashing 2320system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2321system.cpu3.fetch.NoActiveThreadStallCycles 7060 # Number of stall cycles due to no active thread to fetch from 2322system.cpu3.fetch.PendingTrapStallCycles 1076 # Number of stall cycles due to pending traps 2323system.cpu3.fetch.CacheLines 24907 # Number of cache lines fetched 2324system.cpu3.fetch.IcacheSquashes 418 # Number of outstanding Icache misses that were squashed 2325system.cpu3.fetch.rateDist::samples 166168 # Number of instructions fetched each cycle (Total) 2326system.cpu3.fetch.rateDist::mean 1.567606 # Number of instructions fetched each cycle (Total) 2327system.cpu3.fetch.rateDist::stdev 2.102870 # Number of instructions fetched each cycle (Total) |
2324system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 2328system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
2325system.cpu3.fetch.rateDist::0 80366 45.76% 45.76% # Number of instructions fetched each cycle (Total) 2326system.cpu3.fetch.rateDist::1 49379 28.11% 73.87% # Number of instructions fetched each cycle (Total) 2327system.cpu3.fetch.rateDist::2 7947 4.52% 78.40% # Number of instructions fetched each cycle (Total) 2328system.cpu3.fetch.rateDist::3 3182 1.81% 80.21% # Number of instructions fetched each cycle (Total) 2329system.cpu3.fetch.rateDist::4 669 0.38% 80.59% # Number of instructions fetched each cycle (Total) 2330system.cpu3.fetch.rateDist::5 28809 16.40% 96.99% # Number of instructions fetched each cycle (Total) 2331system.cpu3.fetch.rateDist::6 1228 0.70% 97.69% # Number of instructions fetched each cycle (Total) 2332system.cpu3.fetch.rateDist::7 757 0.43% 98.12% # Number of instructions fetched each cycle (Total) 2333system.cpu3.fetch.rateDist::8 3301 1.88% 100.00% # Number of instructions fetched each cycle (Total) | 2329system.cpu3.fetch.rateDist::0 71279 42.90% 42.90% # Number of instructions fetched each cycle (Total) 2330system.cpu3.fetch.rateDist::1 48852 29.40% 72.29% # Number of instructions fetched each cycle (Total) 2331system.cpu3.fetch.rateDist::2 8282 4.98% 77.28% # Number of instructions fetched each cycle (Total) 2332system.cpu3.fetch.rateDist::3 3511 2.11% 79.39% # Number of instructions fetched each cycle (Total) 2333system.cpu3.fetch.rateDist::4 1059 0.64% 80.03% # Number of instructions fetched each cycle (Total) 2334system.cpu3.fetch.rateDist::5 27347 16.46% 96.49% # Number of instructions fetched each cycle (Total) 2335system.cpu3.fetch.rateDist::6 1190 0.72% 97.20% # Number of instructions fetched each cycle (Total) 2336system.cpu3.fetch.rateDist::7 758 0.46% 97.66% # Number of instructions fetched each cycle (Total) 2337system.cpu3.fetch.rateDist::8 3890 2.34% 100.00% # Number of instructions fetched each cycle (Total) |
2334system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2335system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2336system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 2338system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2339system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2340system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
2337system.cpu3.fetch.rateDist::total 175638 # Number of instructions fetched each cycle (Total) 2338system.cpu3.fetch.branchRate 0.268635 # Number of branch fetches per cycle 2339system.cpu3.fetch.rate 1.471669 # Number of inst fetches per cycle 2340system.cpu3.decode.IdleCycles 38601 # Number of cycles decode is idle 2341system.cpu3.decode.BlockedCycles 32457 # Number of cycles decode is blocked 2342system.cpu3.decode.RunCycles 87595 # Number of cycles decode is running 2343system.cpu3.decode.UnblockCycles 6808 # Number of cycles decode is unblocking 2344system.cpu3.decode.SquashCycles 2374 # Number of cycles decode is squashing 2345system.cpu3.decode.DecodedInsts 256826 # Number of instructions handled by decode 2346system.cpu3.rename.SquashCycles 2374 # Number of cycles rename is squashing 2347system.cpu3.rename.IdleCycles 39299 # Number of cycles rename is idle 2348system.cpu3.rename.BlockCycles 20012 # Number of cycles rename is blocking 2349system.cpu3.rename.serializeStallCycles 11695 # count of cycles rename stalled for serializing inst 2350system.cpu3.rename.RunCycles 81034 # Number of cycles rename is running 2351system.cpu3.rename.UnblockCycles 13421 # Number of cycles rename is unblocking 2352system.cpu3.rename.RenamedInsts 254587 # Number of instructions processed by rename 2353system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full 2354system.cpu3.rename.RenamedOperands 176229 # Number of destination operands rename has renamed 2355system.cpu3.rename.RenameLookups 478476 # Number of register rename lookups that rename has made 2356system.cpu3.rename.int_rename_lookups 373673 # Number of integer rename lookups 2357system.cpu3.rename.CommittedMaps 163264 # Number of HB maps that are committed 2358system.cpu3.rename.UndoneMaps 12965 # Number of HB maps that are undone due to squashing 2359system.cpu3.rename.serializingInsts 1094 # count of serializing insts renamed 2360system.cpu3.rename.tempSerializingInsts 1216 # count of temporary serializing insts renamed 2361system.cpu3.rename.skidInsts 16061 # count of insts added to the skid buffer 2362system.cpu3.memDep0.insertedLoads 69948 # Number of loads inserted to the mem dependence unit. 2363system.cpu3.memDep0.insertedStores 32037 # Number of stores inserted to the mem dependence unit. 2364system.cpu3.memDep0.conflictingLoads 34088 # Number of conflicting loads. 2365system.cpu3.memDep0.conflictingStores 26994 # Number of conflicting stores. 2366system.cpu3.iq.iqInstsAdded 208399 # Number of instructions added to the IQ (excludes non-spec) 2367system.cpu3.iq.iqNonSpecInstsAdded 8161 # Number of non-speculative instructions added to the IQ 2368system.cpu3.iq.iqInstsIssued 212159 # Number of instructions issued 2369system.cpu3.iq.iqSquashedInstsIssued 124 # Number of squashed instructions issued 2370system.cpu3.iq.iqSquashedInstsExamined 10835 # Number of squashed instructions iterated over during squash; mainly for profiling 2371system.cpu3.iq.iqSquashedOperandsExamined 11026 # Number of squashed operands that are examined and possibly removed from graph 2372system.cpu3.iq.iqSquashedNonSpecRemoved 608 # Number of squashed non-spec instructions that were removed 2373system.cpu3.iq.issued_per_cycle::samples 175638 # Number of insts issued each cycle 2374system.cpu3.iq.issued_per_cycle::mean 1.207933 # Number of insts issued each cycle 2375system.cpu3.iq.issued_per_cycle::stdev 1.292111 # Number of insts issued each cycle | 2341system.cpu3.fetch.rateDist::total 166168 # Number of instructions fetched each cycle (Total) 2342system.cpu3.fetch.branchRate 0.287859 # Number of branch fetches per cycle 2343system.cpu3.fetch.rate 1.557251 # Number of inst fetches per cycle 2344system.cpu3.decode.IdleCycles 17558 # Number of cycles decode is idle 2345system.cpu3.decode.BlockedCycles 68128 # Number of cycles decode is blocked 2346system.cpu3.decode.RunCycles 67891 # Number of cycles decode is running 2347system.cpu3.decode.UnblockCycles 4168 # Number of cycles decode is unblocking 2348system.cpu3.decode.SquashCycles 1363 # Number of cycles decode is squashing 2349system.cpu3.decode.DecodedInsts 246104 # Number of instructions handled by decode 2350system.cpu3.rename.SquashCycles 1363 # Number of cycles rename is squashing 2351system.cpu3.rename.IdleCycles 18233 # Number of cycles rename is idle 2352system.cpu3.rename.BlockCycles 33368 # Number of cycles rename is blocking 2353system.cpu3.rename.serializeStallCycles 12463 # count of cycles rename stalled for serializing inst 2354system.cpu3.rename.RunCycles 69060 # Number of cycles rename is running 2355system.cpu3.rename.UnblockCycles 24621 # Number of cycles rename is unblocking 2356system.cpu3.rename.RenamedInsts 242881 # Number of instructions processed by rename 2357system.cpu3.rename.IQFullEvents 21589 # Number of times rename has blocked due to IQ full 2358system.cpu3.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full 2359system.cpu3.rename.FullRegisterEvents 3 # Number of times there has been no free registers 2360system.cpu3.rename.RenamedOperands 169259 # Number of destination operands rename has renamed 2361system.cpu3.rename.RenameLookups 456177 # Number of register rename lookups that rename has made 2362system.cpu3.rename.int_rename_lookups 357242 # Number of integer rename lookups 2363system.cpu3.rename.CommittedMaps 154687 # Number of HB maps that are committed 2364system.cpu3.rename.UndoneMaps 14572 # Number of HB maps that are undone due to squashing 2365system.cpu3.rename.serializingInsts 1184 # count of serializing insts renamed 2366system.cpu3.rename.tempSerializingInsts 1245 # count of temporary serializing insts renamed 2367system.cpu3.rename.skidInsts 29195 # count of insts added to the skid buffer 2368system.cpu3.memDep0.insertedLoads 65863 # Number of loads inserted to the mem dependence unit. 2369system.cpu3.memDep0.insertedStores 30140 # Number of stores inserted to the mem dependence unit. 2370system.cpu3.memDep0.conflictingLoads 31966 # Number of conflicting loads. 2371system.cpu3.memDep0.conflictingStores 25009 # Number of conflicting stores. 2372system.cpu3.iq.iqInstsAdded 199372 # Number of instructions added to the IQ (excludes non-spec) 2373system.cpu3.iq.iqNonSpecInstsAdded 7958 # Number of non-speculative instructions added to the IQ 2374system.cpu3.iq.iqInstsIssued 202308 # Number of instructions issued 2375system.cpu3.iq.iqSquashedInstsIssued 33 # Number of squashed instructions issued 2376system.cpu3.iq.iqSquashedInstsExamined 12859 # Number of squashed instructions iterated over during squash; mainly for profiling 2377system.cpu3.iq.iqSquashedOperandsExamined 11887 # Number of squashed operands that are examined and possibly removed from graph 2378system.cpu3.iq.iqSquashedNonSpecRemoved 683 # Number of squashed non-spec instructions that were removed 2379system.cpu3.iq.issued_per_cycle::samples 166168 # Number of insts issued each cycle 2380system.cpu3.iq.issued_per_cycle::mean 1.217491 # Number of insts issued each cycle 2381system.cpu3.iq.issued_per_cycle::stdev 1.364227 # Number of insts issued each cycle |
2376system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 2382system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
2377system.cpu3.iq.issued_per_cycle::0 77942 44.38% 44.38% # Number of insts issued each cycle 2378system.cpu3.iq.issued_per_cycle::1 27771 15.81% 60.19% # Number of insts issued each cycle 2379system.cpu3.iq.issued_per_cycle::2 32234 18.35% 78.54% # Number of insts issued each cycle 2380system.cpu3.iq.issued_per_cycle::3 32910 18.74% 97.28% # Number of insts issued each cycle 2381system.cpu3.iq.issued_per_cycle::4 3253 1.85% 99.13% # Number of insts issued each cycle 2382system.cpu3.iq.issued_per_cycle::5 1156 0.66% 99.79% # Number of insts issued each cycle 2383system.cpu3.iq.issued_per_cycle::6 263 0.15% 99.94% # Number of insts issued each cycle 2384system.cpu3.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle 2385system.cpu3.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle | 2383system.cpu3.iq.issued_per_cycle::0 75148 45.22% 45.22% # Number of insts issued each cycle 2384system.cpu3.iq.issued_per_cycle::1 26256 15.80% 61.02% # Number of insts issued each cycle 2385system.cpu3.iq.issued_per_cycle::2 29417 17.70% 78.73% # Number of insts issued each cycle 2386system.cpu3.iq.issued_per_cycle::3 29010 17.46% 96.19% # Number of insts issued each cycle 2387system.cpu3.iq.issued_per_cycle::4 3447 2.07% 98.26% # Number of insts issued each cycle 2388system.cpu3.iq.issued_per_cycle::5 1582 0.95% 99.21% # Number of insts issued each cycle 2389system.cpu3.iq.issued_per_cycle::6 873 0.53% 99.74% # Number of insts issued each cycle 2390system.cpu3.iq.issued_per_cycle::7 228 0.14% 99.88% # Number of insts issued each cycle 2391system.cpu3.iq.issued_per_cycle::8 207 0.12% 100.00% # Number of insts issued each cycle |
2386system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2387system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2388system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 2392system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2393system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2394system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
2389system.cpu3.iq.issued_per_cycle::total 175638 # Number of insts issued each cycle | 2395system.cpu3.iq.issued_per_cycle::total 166168 # Number of insts issued each cycle |
2390system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 2396system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
2391system.cpu3.iq.fu_full::IntAlu 12 4.44% 4.44% # attempts to use FU when none available 2392system.cpu3.iq.fu_full::IntMult 0 0.00% 4.44% # attempts to use FU when none available 2393system.cpu3.iq.fu_full::IntDiv 0 0.00% 4.44% # attempts to use FU when none available 2394system.cpu3.iq.fu_full::FloatAdd 0 0.00% 4.44% # attempts to use FU when none available 2395system.cpu3.iq.fu_full::FloatCmp 0 0.00% 4.44% # attempts to use FU when none available 2396system.cpu3.iq.fu_full::FloatCvt 0 0.00% 4.44% # attempts to use FU when none available 2397system.cpu3.iq.fu_full::FloatMult 0 0.00% 4.44% # attempts to use FU when none available 2398system.cpu3.iq.fu_full::FloatDiv 0 0.00% 4.44% # attempts to use FU when none available 2399system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 4.44% # attempts to use FU when none available 2400system.cpu3.iq.fu_full::SimdAdd 0 0.00% 4.44% # attempts to use FU when none available 2401system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 4.44% # attempts to use FU when none available 2402system.cpu3.iq.fu_full::SimdAlu 0 0.00% 4.44% # attempts to use FU when none available 2403system.cpu3.iq.fu_full::SimdCmp 0 0.00% 4.44% # attempts to use FU when none available 2404system.cpu3.iq.fu_full::SimdCvt 0 0.00% 4.44% # attempts to use FU when none available 2405system.cpu3.iq.fu_full::SimdMisc 0 0.00% 4.44% # attempts to use FU when none available 2406system.cpu3.iq.fu_full::SimdMult 0 0.00% 4.44% # attempts to use FU when none available 2407system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 4.44% # attempts to use FU when none available 2408system.cpu3.iq.fu_full::SimdShift 0 0.00% 4.44% # attempts to use FU when none available 2409system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 4.44% # attempts to use FU when none available 2410system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 4.44% # attempts to use FU when none available 2411system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 4.44% # attempts to use FU when none available 2412system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 4.44% # attempts to use FU when none available 2413system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 4.44% # attempts to use FU when none available 2414system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 4.44% # attempts to use FU when none available 2415system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 4.44% # attempts to use FU when none available 2416system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 4.44% # attempts to use FU when none available 2417system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 4.44% # attempts to use FU when none available 2418system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.44% # attempts to use FU when none available 2419system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 4.44% # attempts to use FU when none available 2420system.cpu3.iq.fu_full::MemRead 48 17.78% 22.22% # attempts to use FU when none available 2421system.cpu3.iq.fu_full::MemWrite 210 77.78% 100.00% # attempts to use FU when none available | 2397system.cpu3.iq.fu_full::IntAlu 93 25.83% 25.83% # attempts to use FU when none available 2398system.cpu3.iq.fu_full::IntMult 0 0.00% 25.83% # attempts to use FU when none available 2399system.cpu3.iq.fu_full::IntDiv 0 0.00% 25.83% # attempts to use FU when none available 2400system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.83% # attempts to use FU when none available 2401system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.83% # attempts to use FU when none available 2402system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.83% # attempts to use FU when none available 2403system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.83% # attempts to use FU when none available 2404system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.83% # attempts to use FU when none available 2405system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.83% # attempts to use FU when none available 2406system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.83% # attempts to use FU when none available 2407system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.83% # attempts to use FU when none available 2408system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.83% # attempts to use FU when none available 2409system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.83% # attempts to use FU when none available 2410system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.83% # attempts to use FU when none available 2411system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.83% # attempts to use FU when none available 2412system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.83% # attempts to use FU when none available 2413system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.83% # attempts to use FU when none available 2414system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.83% # attempts to use FU when none available 2415system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.83% # attempts to use FU when none available 2416system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.83% # attempts to use FU when none available 2417system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.83% # attempts to use FU when none available 2418system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.83% # attempts to use FU when none available 2419system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.83% # attempts to use FU when none available 2420system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.83% # attempts to use FU when none available 2421system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.83% # attempts to use FU when none available 2422system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 25.83% # attempts to use FU when none available 2423system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.83% # attempts to use FU when none available 2424system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.83% # attempts to use FU when none available 2425system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.83% # attempts to use FU when none available 2426system.cpu3.iq.fu_full::MemRead 58 16.11% 41.94% # attempts to use FU when none available 2427system.cpu3.iq.fu_full::MemWrite 209 58.06% 100.00% # attempts to use FU when none available |
2422system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2423system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2424system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 2428system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2429system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2430system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
2425system.cpu3.iq.FU_type_0::IntAlu 104799 49.40% 49.40% # Type of FU issued 2426system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.40% # Type of FU issued 2427system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.40% # Type of FU issued 2428system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.40% # Type of FU issued 2429system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.40% # Type of FU issued 2430system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.40% # Type of FU issued 2431system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.40% # Type of FU issued 2432system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.40% # Type of FU issued 2433system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.40% # Type of FU issued 2434system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.40% # Type of FU issued 2435system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.40% # Type of FU issued 2436system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.40% # Type of FU issued 2437system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.40% # Type of FU issued 2438system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.40% # Type of FU issued 2439system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.40% # Type of FU issued 2440system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.40% # Type of FU issued 2441system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.40% # Type of FU issued 2442system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.40% # Type of FU issued 2443system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.40% # Type of FU issued 2444system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.40% # Type of FU issued 2445system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.40% # Type of FU issued 2446system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.40% # Type of FU issued 2447system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.40% # Type of FU issued 2448system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.40% # Type of FU issued 2449system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.40% # Type of FU issued 2450system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.40% # Type of FU issued 2451system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.40% # Type of FU issued 2452system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.40% # Type of FU issued 2453system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.40% # Type of FU issued 2454system.cpu3.iq.FU_type_0::MemRead 76027 35.83% 85.23% # Type of FU issued 2455system.cpu3.iq.FU_type_0::MemWrite 31333 14.77% 100.00% # Type of FU issued | 2431system.cpu3.iq.FU_type_0::IntAlu 101290 50.07% 50.07% # Type of FU issued 2432system.cpu3.iq.FU_type_0::IntMult 0 0.00% 50.07% # Type of FU issued 2433system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 50.07% # Type of FU issued 2434system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 50.07% # Type of FU issued 2435system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 50.07% # Type of FU issued 2436system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 50.07% # Type of FU issued 2437system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 50.07% # Type of FU issued 2438system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 50.07% # Type of FU issued 2439system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 50.07% # Type of FU issued 2440system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 50.07% # Type of FU issued 2441system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 50.07% # Type of FU issued 2442system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 50.07% # Type of FU issued 2443system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 50.07% # Type of FU issued 2444system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 50.07% # Type of FU issued 2445system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 50.07% # Type of FU issued 2446system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 50.07% # Type of FU issued 2447system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 50.07% # Type of FU issued 2448system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 50.07% # Type of FU issued 2449system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.07% # Type of FU issued 2450system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 50.07% # Type of FU issued 2451system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.07% # Type of FU issued 2452system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.07% # Type of FU issued 2453system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.07% # Type of FU issued 2454system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.07% # Type of FU issued 2455system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.07% # Type of FU issued 2456system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.07% # Type of FU issued 2457system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 50.07% # Type of FU issued 2458system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.07% # Type of FU issued 2459system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.07% # Type of FU issued 2460system.cpu3.iq.FU_type_0::MemRead 71575 35.38% 85.45% # Type of FU issued 2461system.cpu3.iq.FU_type_0::MemWrite 29443 14.55% 100.00% # Type of FU issued |
2456system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2457system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 2462system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2463system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
2458system.cpu3.iq.FU_type_0::total 212159 # Type of FU issued 2459system.cpu3.iq.rate 1.198043 # Inst issue rate 2460system.cpu3.iq.fu_busy_cnt 270 # FU busy when requested 2461system.cpu3.iq.fu_busy_rate 0.001273 # FU busy rate (busy events/executed inst) 2462system.cpu3.iq.int_inst_queue_reads 600350 # Number of integer instruction queue reads 2463system.cpu3.iq.int_inst_queue_writes 227441 # Number of integer instruction queue writes 2464system.cpu3.iq.int_inst_queue_wakeup_accesses 210302 # Number of integer instruction queue wakeup accesses | 2464system.cpu3.iq.FU_type_0::total 202308 # Type of FU issued 2465system.cpu3.iq.rate 1.209448 # Inst issue rate 2466system.cpu3.iq.fu_busy_cnt 360 # FU busy when requested 2467system.cpu3.iq.fu_busy_rate 0.001779 # FU busy rate (busy events/executed inst) 2468system.cpu3.iq.int_inst_queue_reads 571177 # Number of integer instruction queue reads 2469system.cpu3.iq.int_inst_queue_writes 220229 # Number of integer instruction queue writes 2470system.cpu3.iq.int_inst_queue_wakeup_accesses 200600 # Number of integer instruction queue wakeup accesses |
2465system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 2466system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 2467system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 2471system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 2472system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 2473system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
2468system.cpu3.iq.int_alu_accesses 212429 # Number of integer alu accesses | 2474system.cpu3.iq.int_alu_accesses 202668 # Number of integer alu accesses |
2469system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses | 2475system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses |
2470system.cpu3.iew.lsq.thread0.forwLoads 26730 # Number of loads that had data forwarded from stores | 2476system.cpu3.iew.lsq.thread0.forwLoads 24749 # Number of loads that had data forwarded from stores |
2471system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 2477system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
2472system.cpu3.iew.lsq.thread0.squashedLoads 2459 # Number of loads squashed | 2478system.cpu3.iew.lsq.thread0.squashedLoads 2800 # Number of loads squashed |
2473system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed | 2479system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed |
2474system.cpu3.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations 2475system.cpu3.iew.lsq.thread0.squashedStores 1447 # Number of stores squashed | 2480system.cpu3.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations 2481system.cpu3.iew.lsq.thread0.squashedStores 1627 # Number of stores squashed |
2476system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2477system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2478system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 2479system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 2480system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 2482system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2483system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2484system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 2485system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 2486system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
2481system.cpu3.iew.iewSquashCycles 2374 # Number of cycles IEW is squashing 2482system.cpu3.iew.iewBlockCycles 705 # Number of cycles IEW is blocking 2483system.cpu3.iew.iewUnblockCycles 44 # Number of cycles IEW is unblocking 2484system.cpu3.iew.iewDispatchedInsts 251552 # Number of instructions dispatched to IQ 2485system.cpu3.iew.iewDispSquashedInsts 401 # Number of squashed instructions skipped by dispatch 2486system.cpu3.iew.iewDispLoadInsts 69948 # Number of dispatched load instructions 2487system.cpu3.iew.iewDispStoreInsts 32037 # Number of dispatched store instructions 2488system.cpu3.iew.iewDispNonSpecInsts 1046 # Number of dispatched non-speculative instructions 2489system.cpu3.iew.iewIQFullEvents 44 # Number of times the IQ has become full, causing a stall | 2487system.cpu3.iew.iewSquashCycles 1363 # Number of cycles IEW is squashing 2488system.cpu3.iew.iewBlockCycles 8604 # Number of cycles IEW is blocking 2489system.cpu3.iew.iewUnblockCycles 61 # Number of cycles IEW is unblocking 2490system.cpu3.iew.iewDispatchedInsts 240098 # Number of instructions dispatched to IQ 2491system.cpu3.iew.iewDispSquashedInsts 201 # Number of squashed instructions skipped by dispatch 2492system.cpu3.iew.iewDispLoadInsts 65863 # Number of dispatched load instructions 2493system.cpu3.iew.iewDispStoreInsts 30140 # Number of dispatched store instructions 2494system.cpu3.iew.iewDispNonSpecInsts 1100 # Number of dispatched non-speculative instructions 2495system.cpu3.iew.iewIQFullEvents 33 # Number of times the IQ has become full, causing a stall |
2490system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall | 2496system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall |
2491system.cpu3.iew.memOrderViolationEvents 46 # Number of memory order violations 2492system.cpu3.iew.predictedTakenIncorrect 464 # Number of branches that were predicted taken incorrectly 2493system.cpu3.iew.predictedNotTakenIncorrect 910 # Number of branches that were predicted not taken incorrectly 2494system.cpu3.iew.branchMispredicts 1374 # Number of branch mispredicts detected at execute 2495system.cpu3.iew.iewExecutedInsts 210966 # Number of executed instructions 2496system.cpu3.iew.iewExecLoadInsts 68906 # Number of load instructions executed 2497system.cpu3.iew.iewExecSquashedInsts 1193 # Number of squashed instructions skipped in execute | 2497system.cpu3.iew.memOrderViolationEvents 40 # Number of memory order violations 2498system.cpu3.iew.predictedTakenIncorrect 473 # Number of branches that were predicted taken incorrectly 2499system.cpu3.iew.predictedNotTakenIncorrect 1038 # Number of branches that were predicted not taken incorrectly 2500system.cpu3.iew.branchMispredicts 1511 # Number of branch mispredicts detected at execute 2501system.cpu3.iew.iewExecutedInsts 201185 # Number of executed instructions 2502system.cpu3.iew.iewExecLoadInsts 64698 # Number of load instructions executed 2503system.cpu3.iew.iewExecSquashedInsts 1123 # Number of squashed instructions skipped in execute |
2498system.cpu3.iew.exec_swp 0 # number of swp insts executed | 2504system.cpu3.iew.exec_swp 0 # number of swp insts executed |
2499system.cpu3.iew.exec_nop 34992 # number of nop insts executed 2500system.cpu3.iew.exec_refs 100151 # number of memory reference insts executed 2501system.cpu3.iew.exec_branches 44184 # Number of branches executed 2502system.cpu3.iew.exec_stores 31245 # Number of stores executed 2503system.cpu3.iew.exec_rate 1.191306 # Inst execution rate 2504system.cpu3.iew.wb_sent 210604 # cumulative count of insts sent to commit 2505system.cpu3.iew.wb_count 210302 # cumulative count of insts written-back 2506system.cpu3.iew.wb_producers 116846 # num instructions producing a value 2507system.cpu3.iew.wb_consumers 121503 # num instructions consuming a value | 2505system.cpu3.iew.exec_nop 32768 # number of nop insts executed 2506system.cpu3.iew.exec_refs 94032 # number of memory reference insts executed 2507system.cpu3.iew.exec_branches 42068 # Number of branches executed 2508system.cpu3.iew.exec_stores 29334 # Number of stores executed 2509system.cpu3.iew.exec_rate 1.202734 # Inst execution rate 2510system.cpu3.iew.wb_sent 200904 # cumulative count of insts sent to commit 2511system.cpu3.iew.wb_count 200600 # cumulative count of insts written-back 2512system.cpu3.iew.wb_producers 111689 # num instructions producing a value 2513system.cpu3.iew.wb_consumers 118263 # num instructions consuming a value |
2508system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 2514system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
2509system.cpu3.iew.wb_rate 1.187556 # insts written-back per cycle 2510system.cpu3.iew.wb_fanout 0.961672 # average fanout of values written-back | 2515system.cpu3.iew.wb_rate 1.199237 # insts written-back per cycle 2516system.cpu3.iew.wb_fanout 0.944412 # average fanout of values written-back |
2511system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 2517system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
2512system.cpu3.commit.commitSquashedInsts 12453 # The number of squashed insts skipped by commit 2513system.cpu3.commit.commitNonSpecStalls 7553 # The number of times commit has been forced to stall to communicate backwards 2514system.cpu3.commit.branchMispredicts 1269 # The number of times a branch was mispredicted 2515system.cpu3.commit.committed_per_cycle::samples 165461 # Number of insts commited each cycle 2516system.cpu3.commit.committed_per_cycle::mean 1.444927 # Number of insts commited each cycle 2517system.cpu3.commit.committed_per_cycle::stdev 1.940782 # Number of insts commited each cycle | 2518system.cpu3.commit.commitSquashedInsts 14520 # The number of squashed insts skipped by commit 2519system.cpu3.commit.commitNonSpecStalls 7275 # The number of times commit has been forced to stall to communicate backwards 2520system.cpu3.commit.branchMispredicts 1287 # The number of times a branch was mispredicted 2521system.cpu3.commit.committed_per_cycle::samples 156480 # Number of insts commited each cycle 2522system.cpu3.commit.committed_per_cycle::mean 1.441238 # Number of insts commited each cycle 2523system.cpu3.commit.committed_per_cycle::stdev 1.976154 # Number of insts commited each cycle |
2518system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 2524system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
2519system.cpu3.commit.committed_per_cycle::0 77418 46.79% 46.79% # Number of insts commited each cycle 2520system.cpu3.commit.committed_per_cycle::1 42307 25.57% 72.36% # Number of insts commited each cycle 2521system.cpu3.commit.committed_per_cycle::2 6087 3.68% 76.04% # Number of insts commited each cycle 2522system.cpu3.commit.committed_per_cycle::3 8486 5.13% 81.17% # Number of insts commited each cycle 2523system.cpu3.commit.committed_per_cycle::4 1577 0.95% 82.12% # Number of insts commited each cycle 2524system.cpu3.commit.committed_per_cycle::5 27301 16.50% 98.62% # Number of insts commited each cycle 2525system.cpu3.commit.committed_per_cycle::6 474 0.29% 98.91% # Number of insts commited each cycle 2526system.cpu3.commit.committed_per_cycle::7 1005 0.61% 99.51% # Number of insts commited each cycle 2527system.cpu3.commit.committed_per_cycle::8 806 0.49% 100.00% # Number of insts commited each cycle | 2525system.cpu3.commit.committed_per_cycle::0 74989 47.92% 47.92% # Number of insts commited each cycle 2526system.cpu3.commit.committed_per_cycle::1 38816 24.81% 72.73% # Number of insts commited each cycle 2527system.cpu3.commit.committed_per_cycle::2 5199 3.32% 76.05% # Number of insts commited each cycle 2528system.cpu3.commit.committed_per_cycle::3 8093 5.17% 81.22% # Number of insts commited each cycle 2529system.cpu3.commit.committed_per_cycle::4 1536 0.98% 82.20% # Number of insts commited each cycle 2530system.cpu3.commit.committed_per_cycle::5 24757 15.82% 98.03% # Number of insts commited each cycle 2531system.cpu3.commit.committed_per_cycle::6 830 0.53% 98.56% # Number of insts commited each cycle 2532system.cpu3.commit.committed_per_cycle::7 957 0.61% 99.17% # Number of insts commited each cycle 2533system.cpu3.commit.committed_per_cycle::8 1303 0.83% 100.00% # Number of insts commited each cycle |
2528system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2529system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2530system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 2534system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2535system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2536system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
2531system.cpu3.commit.committed_per_cycle::total 165461 # Number of insts commited each cycle 2532system.cpu3.commit.committedInsts 239079 # Number of instructions committed 2533system.cpu3.commit.committedOps 239079 # Number of ops (including micro ops) committed | 2537system.cpu3.commit.committed_per_cycle::total 156480 # Number of insts commited each cycle 2538system.cpu3.commit.committedInsts 225525 # Number of instructions committed 2539system.cpu3.commit.committedOps 225525 # Number of ops (including micro ops) committed |
2534system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed | 2540system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed |
2535system.cpu3.commit.refs 98079 # Number of memory references committed 2536system.cpu3.commit.loads 67489 # Number of loads committed 2537system.cpu3.commit.membars 6836 # Number of memory barriers committed 2538system.cpu3.commit.branches 43385 # Number of branches committed | 2541system.cpu3.commit.refs 91576 # Number of memory references committed 2542system.cpu3.commit.loads 63063 # Number of loads committed 2543system.cpu3.commit.membars 6559 # Number of memory barriers committed 2544system.cpu3.commit.branches 41035 # Number of branches committed |
2539system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. | 2545system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. |
2540system.cpu3.commit.int_insts 163585 # Number of committed integer instructions. | 2546system.cpu3.commit.int_insts 154730 # Number of committed integer instructions. |
2541system.cpu3.commit.function_calls 322 # Number of function calls committed. | 2547system.cpu3.commit.function_calls 322 # Number of function calls committed. |
2542system.cpu3.commit.op_class_0::No_OpClass 34172 14.29% 14.29% # Class of committed instruction 2543system.cpu3.commit.op_class_0::IntAlu 99992 41.82% 56.12% # Class of committed instruction 2544system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.12% # Class of committed instruction 2545system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.12% # Class of committed instruction 2546system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.12% # Class of committed instruction 2547system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.12% # Class of committed instruction 2548system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.12% # Class of committed instruction 2549system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.12% # Class of committed instruction 2550system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.12% # Class of committed instruction 2551system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.12% # Class of committed instruction 2552system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.12% # Class of committed instruction 2553system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.12% # Class of committed instruction 2554system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.12% # Class of committed instruction 2555system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.12% # Class of committed instruction 2556system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.12% # Class of committed instruction 2557system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.12% # Class of committed instruction 2558system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.12% # Class of committed instruction 2559system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.12% # Class of committed instruction 2560system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.12% # Class of committed instruction 2561system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.12% # Class of committed instruction 2562system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.12% # Class of committed instruction 2563system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.12% # Class of committed instruction 2564system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.12% # Class of committed instruction 2565system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.12% # Class of committed instruction 2566system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.12% # Class of committed instruction 2567system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.12% # Class of committed instruction 2568system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.12% # Class of committed instruction 2569system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.12% # Class of committed instruction 2570system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.12% # Class of committed instruction 2571system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.12% # Class of committed instruction 2572system.cpu3.commit.op_class_0::MemRead 74325 31.09% 87.21% # Class of committed instruction 2573system.cpu3.commit.op_class_0::MemWrite 30590 12.79% 100.00% # Class of committed instruction | 2548system.cpu3.commit.op_class_0::No_OpClass 31823 14.11% 14.11% # Class of committed instruction 2549system.cpu3.commit.op_class_0::IntAlu 95567 42.38% 56.49% # Class of committed instruction 2550system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.49% # Class of committed instruction 2551system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.49% # Class of committed instruction 2552system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.49% # Class of committed instruction 2553system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.49% # Class of committed instruction 2554system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.49% # Class of committed instruction 2555system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.49% # Class of committed instruction 2556system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.49% # Class of committed instruction 2557system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.49% # Class of committed instruction 2558system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.49% # Class of committed instruction 2559system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.49% # Class of committed instruction 2560system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.49% # Class of committed instruction 2561system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.49% # Class of committed instruction 2562system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.49% # Class of committed instruction 2563system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.49% # Class of committed instruction 2564system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.49% # Class of committed instruction 2565system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.49% # Class of committed instruction 2566system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.49% # Class of committed instruction 2567system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.49% # Class of committed instruction 2568system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.49% # Class of committed instruction 2569system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.49% # Class of committed instruction 2570system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.49% # Class of committed instruction 2571system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.49% # Class of committed instruction 2572system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.49% # Class of committed instruction 2573system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.49% # Class of committed instruction 2574system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.49% # Class of committed instruction 2575system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.49% # Class of committed instruction 2576system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.49% # Class of committed instruction 2577system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.49% # Class of committed instruction 2578system.cpu3.commit.op_class_0::MemRead 69622 30.87% 87.36% # Class of committed instruction 2579system.cpu3.commit.op_class_0::MemWrite 28513 12.64% 100.00% # Class of committed instruction |
2574system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2575system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 2580system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2581system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
2576system.cpu3.commit.op_class_0::total 239079 # Class of committed instruction 2577system.cpu3.commit.bw_lim_events 806 # number cycles where commit BW limit reached | 2582system.cpu3.commit.op_class_0::total 225525 # Class of committed instruction 2583system.cpu3.commit.bw_lim_events 1303 # number cycles where commit BW limit reached |
2578system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits | 2584system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits |
2579system.cpu3.rob.rob_reads 415600 # The number of ROB reads 2580system.cpu3.rob.rob_writes 505444 # The number of ROB writes 2581system.cpu3.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself 2582system.cpu3.idleCycles 1450 # Total number of cycles that the CPU has spent unscheduled due to idling 2583system.cpu3.quiesceCycles 44852 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2584system.cpu3.committedInsts 198071 # Number of Instructions Simulated 2585system.cpu3.committedOps 198071 # Number of Ops (including micro ops) Simulated 2586system.cpu3.cpi 0.894063 # CPI: Cycles Per Instruction 2587system.cpu3.cpi_total 0.894063 # CPI: Total CPI of All Threads 2588system.cpu3.ipc 1.118489 # IPC: Instructions Per Cycle 2589system.cpu3.ipc_total 1.118489 # IPC: Total IPC of All Threads 2590system.cpu3.int_regfile_reads 358875 # number of integer regfile reads 2591system.cpu3.int_regfile_writes 168004 # number of integer regfile writes | 2585system.cpu3.rob.rob_reads 394635 # The number of ROB reads 2586system.cpu3.rob.rob_writes 482728 # The number of ROB writes 2587system.cpu3.timesIdled 203 # Number of times that the entire CPU went into an idle state and unscheduled itself 2588system.cpu3.idleCycles 1105 # Total number of cycles that the CPU has spent unscheduled due to idling 2589system.cpu3.quiesceCycles 44004 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2590system.cpu3.committedInsts 187143 # Number of Instructions Simulated 2591system.cpu3.committedOps 187143 # Number of Ops (including micro ops) Simulated 2592system.cpu3.cpi 0.893825 # CPI: Cycles Per Instruction 2593system.cpu3.cpi_total 0.893825 # CPI: Total CPI of All Threads 2594system.cpu3.ipc 1.118788 # IPC: Instructions Per Cycle 2595system.cpu3.ipc_total 1.118788 # IPC: Total IPC of All Threads 2596system.cpu3.int_regfile_reads 341840 # number of integer regfile reads 2597system.cpu3.int_regfile_writes 160726 # number of integer regfile writes |
2592system.cpu3.fp_regfile_writes 64 # number of floating regfile writes | 2598system.cpu3.fp_regfile_writes 64 # number of floating regfile writes |
2593system.cpu3.misc_regfile_reads 101700 # number of misc regfile reads | 2599system.cpu3.misc_regfile_reads 95629 # number of misc regfile reads |
2594system.cpu3.misc_regfile_writes 648 # number of misc regfile writes | 2600system.cpu3.misc_regfile_writes 648 # number of misc regfile writes |
2595system.cpu3.icache.tags.replacements 319 # number of replacements 2596system.cpu3.icache.tags.tagsinuse 77.082229 # Cycle average of tags in use 2597system.cpu3.icache.tags.total_refs 22869 # Total number of references to valid blocks. 2598system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks. 2599system.cpu3.icache.tags.avg_refs 53.183721 # Average number of references to valid blocks. | 2601system.cpu3.icache.tags.replacements 380 # number of replacements 2602system.cpu3.icache.tags.tagsinuse 77.789470 # Cycle average of tags in use 2603system.cpu3.icache.tags.total_refs 24352 # Total number of references to valid blocks. 2604system.cpu3.icache.tags.sampled_refs 493 # Sample count of references to valid blocks. 2605system.cpu3.icache.tags.avg_refs 49.395538 # Average number of references to valid blocks. |
2600system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2606system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
2601system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.082229 # Average occupied blocks per requestor 2602system.cpu3.icache.tags.occ_percent::cpu3.inst 0.150551 # Average percentage of cache occupancy 2603system.cpu3.icache.tags.occ_percent::total 0.150551 # Average percentage of cache occupancy 2604system.cpu3.icache.tags.occ_task_id_blocks::1024 111 # Occupied blocks per task id | 2607system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.789470 # Average occupied blocks per requestor 2608system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151933 # Average percentage of cache occupancy 2609system.cpu3.icache.tags.occ_percent::total 0.151933 # Average percentage of cache occupancy 2610system.cpu3.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id |
2605system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id | 2611system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id |
2606system.cpu3.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id 2607system.cpu3.icache.tags.occ_task_id_percent::1024 0.216797 # Percentage of cache occupancy per task id 2608system.cpu3.icache.tags.tag_accesses 23774 # Number of tag accesses 2609system.cpu3.icache.tags.data_accesses 23774 # Number of data accesses 2610system.cpu3.icache.ReadReq_hits::cpu3.inst 22869 # number of ReadReq hits 2611system.cpu3.icache.ReadReq_hits::total 22869 # number of ReadReq hits 2612system.cpu3.icache.demand_hits::cpu3.inst 22869 # number of demand (read+write) hits 2613system.cpu3.icache.demand_hits::total 22869 # number of demand (read+write) hits 2614system.cpu3.icache.overall_hits::cpu3.inst 22869 # number of overall hits 2615system.cpu3.icache.overall_hits::total 22869 # number of overall hits 2616system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses 2617system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses 2618system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses 2619system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses 2620system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses 2621system.cpu3.icache.overall_misses::total 475 # number of overall misses 2622system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6365994 # number of ReadReq miss cycles 2623system.cpu3.icache.ReadReq_miss_latency::total 6365994 # number of ReadReq miss cycles 2624system.cpu3.icache.demand_miss_latency::cpu3.inst 6365994 # number of demand (read+write) miss cycles 2625system.cpu3.icache.demand_miss_latency::total 6365994 # number of demand (read+write) miss cycles 2626system.cpu3.icache.overall_miss_latency::cpu3.inst 6365994 # number of overall miss cycles 2627system.cpu3.icache.overall_miss_latency::total 6365994 # number of overall miss cycles 2628system.cpu3.icache.ReadReq_accesses::cpu3.inst 23344 # number of ReadReq accesses(hits+misses) 2629system.cpu3.icache.ReadReq_accesses::total 23344 # number of ReadReq accesses(hits+misses) 2630system.cpu3.icache.demand_accesses::cpu3.inst 23344 # number of demand (read+write) accesses 2631system.cpu3.icache.demand_accesses::total 23344 # number of demand (read+write) accesses 2632system.cpu3.icache.overall_accesses::cpu3.inst 23344 # number of overall (read+write) accesses 2633system.cpu3.icache.overall_accesses::total 23344 # number of overall (read+write) accesses 2634system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020348 # miss rate for ReadReq accesses 2635system.cpu3.icache.ReadReq_miss_rate::total 0.020348 # miss rate for ReadReq accesses 2636system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020348 # miss rate for demand accesses 2637system.cpu3.icache.demand_miss_rate::total 0.020348 # miss rate for demand accesses 2638system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020348 # miss rate for overall accesses 2639system.cpu3.icache.overall_miss_rate::total 0.020348 # miss rate for overall accesses 2640system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13402.092632 # average ReadReq miss latency 2641system.cpu3.icache.ReadReq_avg_miss_latency::total 13402.092632 # average ReadReq miss latency 2642system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13402.092632 # average overall miss latency 2643system.cpu3.icache.demand_avg_miss_latency::total 13402.092632 # average overall miss latency 2644system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13402.092632 # average overall miss latency 2645system.cpu3.icache.overall_avg_miss_latency::total 13402.092632 # average overall miss latency | 2612system.cpu3.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id 2613system.cpu3.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id 2614system.cpu3.icache.tags.tag_accesses 25400 # Number of tag accesses 2615system.cpu3.icache.tags.data_accesses 25400 # Number of data accesses 2616system.cpu3.icache.ReadReq_hits::cpu3.inst 24352 # number of ReadReq hits 2617system.cpu3.icache.ReadReq_hits::total 24352 # number of ReadReq hits 2618system.cpu3.icache.demand_hits::cpu3.inst 24352 # number of demand (read+write) hits 2619system.cpu3.icache.demand_hits::total 24352 # number of demand (read+write) hits 2620system.cpu3.icache.overall_hits::cpu3.inst 24352 # number of overall hits 2621system.cpu3.icache.overall_hits::total 24352 # number of overall hits 2622system.cpu3.icache.ReadReq_misses::cpu3.inst 555 # number of ReadReq misses 2623system.cpu3.icache.ReadReq_misses::total 555 # number of ReadReq misses 2624system.cpu3.icache.demand_misses::cpu3.inst 555 # number of demand (read+write) misses 2625system.cpu3.icache.demand_misses::total 555 # number of demand (read+write) misses 2626system.cpu3.icache.overall_misses::cpu3.inst 555 # number of overall misses 2627system.cpu3.icache.overall_misses::total 555 # number of overall misses 2628system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7324995 # number of ReadReq miss cycles 2629system.cpu3.icache.ReadReq_miss_latency::total 7324995 # number of ReadReq miss cycles 2630system.cpu3.icache.demand_miss_latency::cpu3.inst 7324995 # number of demand (read+write) miss cycles 2631system.cpu3.icache.demand_miss_latency::total 7324995 # number of demand (read+write) miss cycles 2632system.cpu3.icache.overall_miss_latency::cpu3.inst 7324995 # number of overall miss cycles 2633system.cpu3.icache.overall_miss_latency::total 7324995 # number of overall miss cycles 2634system.cpu3.icache.ReadReq_accesses::cpu3.inst 24907 # number of ReadReq accesses(hits+misses) 2635system.cpu3.icache.ReadReq_accesses::total 24907 # number of ReadReq accesses(hits+misses) 2636system.cpu3.icache.demand_accesses::cpu3.inst 24907 # number of demand (read+write) accesses 2637system.cpu3.icache.demand_accesses::total 24907 # number of demand (read+write) accesses 2638system.cpu3.icache.overall_accesses::cpu3.inst 24907 # number of overall (read+write) accesses 2639system.cpu3.icache.overall_accesses::total 24907 # number of overall (read+write) accesses 2640system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.022283 # miss rate for ReadReq accesses 2641system.cpu3.icache.ReadReq_miss_rate::total 0.022283 # miss rate for ReadReq accesses 2642system.cpu3.icache.demand_miss_rate::cpu3.inst 0.022283 # miss rate for demand accesses 2643system.cpu3.icache.demand_miss_rate::total 0.022283 # miss rate for demand accesses 2644system.cpu3.icache.overall_miss_rate::cpu3.inst 0.022283 # miss rate for overall accesses 2645system.cpu3.icache.overall_miss_rate::total 0.022283 # miss rate for overall accesses 2646system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13198.189189 # average ReadReq miss latency 2647system.cpu3.icache.ReadReq_avg_miss_latency::total 13198.189189 # average ReadReq miss latency 2648system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13198.189189 # average overall miss latency 2649system.cpu3.icache.demand_avg_miss_latency::total 13198.189189 # average overall miss latency 2650system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13198.189189 # average overall miss latency 2651system.cpu3.icache.overall_avg_miss_latency::total 13198.189189 # average overall miss latency |
2646system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2647system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2648system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 2649system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 2650system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2651system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2652system.cpu3.icache.fast_writes 0 # number of fast writes performed 2653system.cpu3.icache.cache_copies 0 # number of cache copies performed | 2652system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2653system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2654system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 2655system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 2656system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2657system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2658system.cpu3.icache.fast_writes 0 # number of fast writes performed 2659system.cpu3.icache.cache_copies 0 # number of cache copies performed |
2654system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 45 # number of ReadReq MSHR hits 2655system.cpu3.icache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits 2656system.cpu3.icache.demand_mshr_hits::cpu3.inst 45 # number of demand (read+write) MSHR hits 2657system.cpu3.icache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits 2658system.cpu3.icache.overall_mshr_hits::cpu3.inst 45 # number of overall MSHR hits 2659system.cpu3.icache.overall_mshr_hits::total 45 # number of overall MSHR hits 2660system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 430 # number of ReadReq MSHR misses 2661system.cpu3.icache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses 2662system.cpu3.icache.demand_mshr_misses::cpu3.inst 430 # number of demand (read+write) MSHR misses 2663system.cpu3.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses 2664system.cpu3.icache.overall_mshr_misses::cpu3.inst 430 # number of overall MSHR misses 2665system.cpu3.icache.overall_mshr_misses::total 430 # number of overall MSHR misses 2666system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5107006 # number of ReadReq MSHR miss cycles 2667system.cpu3.icache.ReadReq_mshr_miss_latency::total 5107006 # number of ReadReq MSHR miss cycles 2668system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5107006 # number of demand (read+write) MSHR miss cycles 2669system.cpu3.icache.demand_mshr_miss_latency::total 5107006 # number of demand (read+write) MSHR miss cycles 2670system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5107006 # number of overall MSHR miss cycles 2671system.cpu3.icache.overall_mshr_miss_latency::total 5107006 # number of overall MSHR miss cycles 2672system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.018420 # mshr miss rate for ReadReq accesses 2673system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.018420 # mshr miss rate for ReadReq accesses 2674system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.018420 # mshr miss rate for demand accesses 2675system.cpu3.icache.demand_mshr_miss_rate::total 0.018420 # mshr miss rate for demand accesses 2676system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.018420 # mshr miss rate for overall accesses 2677system.cpu3.icache.overall_mshr_miss_rate::total 0.018420 # mshr miss rate for overall accesses 2678system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11876.758140 # average ReadReq mshr miss latency 2679system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11876.758140 # average ReadReq mshr miss latency 2680system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11876.758140 # average overall mshr miss latency 2681system.cpu3.icache.demand_avg_mshr_miss_latency::total 11876.758140 # average overall mshr miss latency 2682system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11876.758140 # average overall mshr miss latency 2683system.cpu3.icache.overall_avg_mshr_miss_latency::total 11876.758140 # average overall mshr miss latency | 2660system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 62 # number of ReadReq MSHR hits 2661system.cpu3.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits 2662system.cpu3.icache.demand_mshr_hits::cpu3.inst 62 # number of demand (read+write) MSHR hits 2663system.cpu3.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits 2664system.cpu3.icache.overall_mshr_hits::cpu3.inst 62 # number of overall MSHR hits 2665system.cpu3.icache.overall_mshr_hits::total 62 # number of overall MSHR hits 2666system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 493 # number of ReadReq MSHR misses 2667system.cpu3.icache.ReadReq_mshr_misses::total 493 # number of ReadReq MSHR misses 2668system.cpu3.icache.demand_mshr_misses::cpu3.inst 493 # number of demand (read+write) MSHR misses 2669system.cpu3.icache.demand_mshr_misses::total 493 # number of demand (read+write) MSHR misses 2670system.cpu3.icache.overall_mshr_misses::cpu3.inst 493 # number of overall MSHR misses 2671system.cpu3.icache.overall_mshr_misses::total 493 # number of overall MSHR misses 2672system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5824754 # number of ReadReq MSHR miss cycles 2673system.cpu3.icache.ReadReq_mshr_miss_latency::total 5824754 # number of ReadReq MSHR miss cycles 2674system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5824754 # number of demand (read+write) MSHR miss cycles 2675system.cpu3.icache.demand_mshr_miss_latency::total 5824754 # number of demand (read+write) MSHR miss cycles 2676system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5824754 # number of overall MSHR miss cycles 2677system.cpu3.icache.overall_mshr_miss_latency::total 5824754 # number of overall MSHR miss cycles 2678system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.019794 # mshr miss rate for ReadReq accesses 2679system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.019794 # mshr miss rate for ReadReq accesses 2680system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.019794 # mshr miss rate for demand accesses 2681system.cpu3.icache.demand_mshr_miss_rate::total 0.019794 # mshr miss rate for demand accesses 2682system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.019794 # mshr miss rate for overall accesses 2683system.cpu3.icache.overall_mshr_miss_rate::total 0.019794 # mshr miss rate for overall accesses 2684system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11814.916836 # average ReadReq mshr miss latency 2685system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11814.916836 # average ReadReq mshr miss latency 2686system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11814.916836 # average overall mshr miss latency 2687system.cpu3.icache.demand_avg_mshr_miss_latency::total 11814.916836 # average overall mshr miss latency 2688system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11814.916836 # average overall mshr miss latency 2689system.cpu3.icache.overall_avg_mshr_miss_latency::total 11814.916836 # average overall mshr miss latency |
2684system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2685system.cpu3.dcache.tags.replacements 0 # number of replacements | 2690system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2691system.cpu3.dcache.tags.replacements 0 # number of replacements |
2686system.cpu3.dcache.tags.tagsinuse 23.636588 # Cycle average of tags in use 2687system.cpu3.dcache.tags.total_refs 36715 # Total number of references to valid blocks. 2688system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 2689system.cpu3.dcache.tags.avg_refs 1266.034483 # Average number of references to valid blocks. | 2692system.cpu3.dcache.tags.tagsinuse 23.433083 # Cycle average of tags in use 2693system.cpu3.dcache.tags.total_refs 34557 # Total number of references to valid blocks. 2694system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. 2695system.cpu3.dcache.tags.avg_refs 1234.178571 # Average number of references to valid blocks. |
2690system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2696system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
2691system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.636588 # Average occupied blocks per requestor 2692system.cpu3.dcache.tags.occ_percent::cpu3.data 0.046165 # Average percentage of cache occupancy 2693system.cpu3.dcache.tags.occ_percent::total 0.046165 # Average percentage of cache occupancy 2694system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 2695system.cpu3.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id | 2697system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.433083 # Average occupied blocks per requestor 2698system.cpu3.dcache.tags.occ_percent::cpu3.data 0.045768 # Average percentage of cache occupancy 2699system.cpu3.dcache.tags.occ_percent::total 0.045768 # Average percentage of cache occupancy 2700system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id |
2696system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id | 2701system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id |
2697system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 2698system.cpu3.dcache.tags.tag_accesses 291244 # Number of tag accesses 2699system.cpu3.dcache.tags.data_accesses 291244 # Number of data accesses 2700system.cpu3.dcache.ReadReq_hits::cpu3.data 41825 # number of ReadReq hits 2701system.cpu3.dcache.ReadReq_hits::total 41825 # number of ReadReq hits 2702system.cpu3.dcache.WriteReq_hits::cpu3.data 30388 # number of WriteReq hits 2703system.cpu3.dcache.WriteReq_hits::total 30388 # number of WriteReq hits 2704system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits 2705system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits 2706system.cpu3.dcache.demand_hits::cpu3.data 72213 # number of demand (read+write) hits 2707system.cpu3.dcache.demand_hits::total 72213 # number of demand (read+write) hits 2708system.cpu3.dcache.overall_hits::cpu3.data 72213 # number of overall hits 2709system.cpu3.dcache.overall_hits::total 72213 # number of overall hits 2710system.cpu3.dcache.ReadReq_misses::cpu3.data 334 # number of ReadReq misses 2711system.cpu3.dcache.ReadReq_misses::total 334 # number of ReadReq misses 2712system.cpu3.dcache.WriteReq_misses::cpu3.data 131 # number of WriteReq misses 2713system.cpu3.dcache.WriteReq_misses::total 131 # number of WriteReq misses 2714system.cpu3.dcache.SwapReq_misses::cpu3.data 56 # number of SwapReq misses 2715system.cpu3.dcache.SwapReq_misses::total 56 # number of SwapReq misses 2716system.cpu3.dcache.demand_misses::cpu3.data 465 # number of demand (read+write) misses 2717system.cpu3.dcache.demand_misses::total 465 # number of demand (read+write) misses 2718system.cpu3.dcache.overall_misses::cpu3.data 465 # number of overall misses 2719system.cpu3.dcache.overall_misses::total 465 # number of overall misses 2720system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4213650 # number of ReadReq miss cycles 2721system.cpu3.dcache.ReadReq_miss_latency::total 4213650 # number of ReadReq miss cycles 2722system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2829011 # number of WriteReq miss cycles 2723system.cpu3.dcache.WriteReq_miss_latency::total 2829011 # number of WriteReq miss cycles 2724system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 511006 # number of SwapReq miss cycles 2725system.cpu3.dcache.SwapReq_miss_latency::total 511006 # number of SwapReq miss cycles 2726system.cpu3.dcache.demand_miss_latency::cpu3.data 7042661 # number of demand (read+write) miss cycles 2727system.cpu3.dcache.demand_miss_latency::total 7042661 # number of demand (read+write) miss cycles 2728system.cpu3.dcache.overall_miss_latency::cpu3.data 7042661 # number of overall miss cycles 2729system.cpu3.dcache.overall_miss_latency::total 7042661 # number of overall miss cycles 2730system.cpu3.dcache.ReadReq_accesses::cpu3.data 42159 # number of ReadReq accesses(hits+misses) 2731system.cpu3.dcache.ReadReq_accesses::total 42159 # number of ReadReq accesses(hits+misses) 2732system.cpu3.dcache.WriteReq_accesses::cpu3.data 30519 # number of WriteReq accesses(hits+misses) 2733system.cpu3.dcache.WriteReq_accesses::total 30519 # number of WriteReq accesses(hits+misses) 2734system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) 2735system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) 2736system.cpu3.dcache.demand_accesses::cpu3.data 72678 # number of demand (read+write) accesses 2737system.cpu3.dcache.demand_accesses::total 72678 # number of demand (read+write) accesses 2738system.cpu3.dcache.overall_accesses::cpu3.data 72678 # number of overall (read+write) accesses 2739system.cpu3.dcache.overall_accesses::total 72678 # number of overall (read+write) accesses 2740system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.007922 # miss rate for ReadReq accesses 2741system.cpu3.dcache.ReadReq_miss_rate::total 0.007922 # miss rate for ReadReq accesses 2742system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004292 # miss rate for WriteReq accesses 2743system.cpu3.dcache.WriteReq_miss_rate::total 0.004292 # miss rate for WriteReq accesses 2744system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.788732 # miss rate for SwapReq accesses 2745system.cpu3.dcache.SwapReq_miss_rate::total 0.788732 # miss rate for SwapReq accesses 2746system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006398 # miss rate for demand accesses 2747system.cpu3.dcache.demand_miss_rate::total 0.006398 # miss rate for demand accesses 2748system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006398 # miss rate for overall accesses 2749system.cpu3.dcache.overall_miss_rate::total 0.006398 # miss rate for overall accesses 2750system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12615.718563 # average ReadReq miss latency 2751system.cpu3.dcache.ReadReq_avg_miss_latency::total 12615.718563 # average ReadReq miss latency 2752system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 21595.503817 # average WriteReq miss latency 2753system.cpu3.dcache.WriteReq_avg_miss_latency::total 21595.503817 # average WriteReq miss latency 2754system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9125.107143 # average SwapReq miss latency 2755system.cpu3.dcache.SwapReq_avg_miss_latency::total 9125.107143 # average SwapReq miss latency 2756system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 15145.507527 # average overall miss latency 2757system.cpu3.dcache.demand_avg_miss_latency::total 15145.507527 # average overall miss latency 2758system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 15145.507527 # average overall miss latency 2759system.cpu3.dcache.overall_avg_miss_latency::total 15145.507527 # average overall miss latency | 2702system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id 2703system.cpu3.dcache.tags.tag_accesses 274000 # Number of tag accesses 2704system.cpu3.dcache.tags.data_accesses 274000 # Number of data accesses 2705system.cpu3.dcache.ReadReq_hits::cpu3.data 39491 # number of ReadReq hits 2706system.cpu3.dcache.ReadReq_hits::total 39491 # number of ReadReq hits 2707system.cpu3.dcache.WriteReq_hits::cpu3.data 28303 # number of WriteReq hits 2708system.cpu3.dcache.WriteReq_hits::total 28303 # number of WriteReq hits 2709system.cpu3.dcache.SwapReq_hits::cpu3.data 13 # number of SwapReq hits 2710system.cpu3.dcache.SwapReq_hits::total 13 # number of SwapReq hits 2711system.cpu3.dcache.demand_hits::cpu3.data 67794 # number of demand (read+write) hits 2712system.cpu3.dcache.demand_hits::total 67794 # number of demand (read+write) hits 2713system.cpu3.dcache.overall_hits::cpu3.data 67794 # number of overall hits 2714system.cpu3.dcache.overall_hits::total 67794 # number of overall hits 2715system.cpu3.dcache.ReadReq_misses::cpu3.data 432 # number of ReadReq misses 2716system.cpu3.dcache.ReadReq_misses::total 432 # number of ReadReq misses 2717system.cpu3.dcache.WriteReq_misses::cpu3.data 140 # number of WriteReq misses 2718system.cpu3.dcache.WriteReq_misses::total 140 # number of WriteReq misses 2719system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses 2720system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses 2721system.cpu3.dcache.demand_misses::cpu3.data 572 # number of demand (read+write) misses 2722system.cpu3.dcache.demand_misses::total 572 # number of demand (read+write) misses 2723system.cpu3.dcache.overall_misses::cpu3.data 572 # number of overall misses 2724system.cpu3.dcache.overall_misses::total 572 # number of overall misses 2725system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 5736963 # number of ReadReq miss cycles 2726system.cpu3.dcache.ReadReq_miss_latency::total 5736963 # number of ReadReq miss cycles 2727system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2764512 # number of WriteReq miss cycles 2728system.cpu3.dcache.WriteReq_miss_latency::total 2764512 # number of WriteReq miss cycles 2729system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 515508 # number of SwapReq miss cycles 2730system.cpu3.dcache.SwapReq_miss_latency::total 515508 # number of SwapReq miss cycles 2731system.cpu3.dcache.demand_miss_latency::cpu3.data 8501475 # number of demand (read+write) miss cycles 2732system.cpu3.dcache.demand_miss_latency::total 8501475 # number of demand (read+write) miss cycles 2733system.cpu3.dcache.overall_miss_latency::cpu3.data 8501475 # number of overall miss cycles 2734system.cpu3.dcache.overall_miss_latency::total 8501475 # number of overall miss cycles 2735system.cpu3.dcache.ReadReq_accesses::cpu3.data 39923 # number of ReadReq accesses(hits+misses) 2736system.cpu3.dcache.ReadReq_accesses::total 39923 # number of ReadReq accesses(hits+misses) 2737system.cpu3.dcache.WriteReq_accesses::cpu3.data 28443 # number of WriteReq accesses(hits+misses) 2738system.cpu3.dcache.WriteReq_accesses::total 28443 # number of WriteReq accesses(hits+misses) 2739system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses) 2740system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) 2741system.cpu3.dcache.demand_accesses::cpu3.data 68366 # number of demand (read+write) accesses 2742system.cpu3.dcache.demand_accesses::total 68366 # number of demand (read+write) accesses 2743system.cpu3.dcache.overall_accesses::cpu3.data 68366 # number of overall (read+write) accesses 2744system.cpu3.dcache.overall_accesses::total 68366 # number of overall (read+write) accesses 2745system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010821 # miss rate for ReadReq accesses 2746system.cpu3.dcache.ReadReq_miss_rate::total 0.010821 # miss rate for ReadReq accesses 2747system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004922 # miss rate for WriteReq accesses 2748system.cpu3.dcache.WriteReq_miss_rate::total 0.004922 # miss rate for WriteReq accesses 2749system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.814286 # miss rate for SwapReq accesses 2750system.cpu3.dcache.SwapReq_miss_rate::total 0.814286 # miss rate for SwapReq accesses 2751system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008367 # miss rate for demand accesses 2752system.cpu3.dcache.demand_miss_rate::total 0.008367 # miss rate for demand accesses 2753system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008367 # miss rate for overall accesses 2754system.cpu3.dcache.overall_miss_rate::total 0.008367 # miss rate for overall accesses 2755system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 13280.006944 # average ReadReq miss latency 2756system.cpu3.dcache.ReadReq_avg_miss_latency::total 13280.006944 # average ReadReq miss latency 2757system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19746.514286 # average WriteReq miss latency 2758system.cpu3.dcache.WriteReq_avg_miss_latency::total 19746.514286 # average WriteReq miss latency 2759system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9044 # average SwapReq miss latency 2760system.cpu3.dcache.SwapReq_avg_miss_latency::total 9044 # average SwapReq miss latency 2761system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14862.718531 # average overall miss latency 2762system.cpu3.dcache.demand_avg_miss_latency::total 14862.718531 # average overall miss latency 2763system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14862.718531 # average overall miss latency 2764system.cpu3.dcache.overall_avg_miss_latency::total 14862.718531 # average overall miss latency |
2760system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2761system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2762system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2763system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 2764system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2765system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2766system.cpu3.dcache.fast_writes 0 # number of fast writes performed 2767system.cpu3.dcache.cache_copies 0 # number of cache copies performed | 2765system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2766system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2767system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2768system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 2769system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2770system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2771system.cpu3.dcache.fast_writes 0 # number of fast writes performed 2772system.cpu3.dcache.cache_copies 0 # number of cache copies performed |
2768system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 173 # number of ReadReq MSHR hits 2769system.cpu3.dcache.ReadReq_mshr_hits::total 173 # number of ReadReq MSHR hits 2770system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 31 # number of WriteReq MSHR hits 2771system.cpu3.dcache.WriteReq_mshr_hits::total 31 # number of WriteReq MSHR hits 2772system.cpu3.dcache.demand_mshr_hits::cpu3.data 204 # number of demand (read+write) MSHR hits 2773system.cpu3.dcache.demand_mshr_hits::total 204 # number of demand (read+write) MSHR hits 2774system.cpu3.dcache.overall_mshr_hits::cpu3.data 204 # number of overall MSHR hits 2775system.cpu3.dcache.overall_mshr_hits::total 204 # number of overall MSHR hits 2776system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 161 # number of ReadReq MSHR misses 2777system.cpu3.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses 2778system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 100 # number of WriteReq MSHR misses 2779system.cpu3.dcache.WriteReq_mshr_misses::total 100 # number of WriteReq MSHR misses 2780system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 56 # number of SwapReq MSHR misses 2781system.cpu3.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses 2782system.cpu3.dcache.demand_mshr_misses::cpu3.data 261 # number of demand (read+write) MSHR misses 2783system.cpu3.dcache.demand_mshr_misses::total 261 # number of demand (read+write) MSHR misses 2784system.cpu3.dcache.overall_mshr_misses::cpu3.data 261 # number of overall MSHR misses 2785system.cpu3.dcache.overall_mshr_misses::total 261 # number of overall MSHR misses 2786system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1077518 # number of ReadReq MSHR miss cycles 2787system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1077518 # number of ReadReq MSHR miss cycles 2788system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1290489 # number of WriteReq MSHR miss cycles 2789system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1290489 # number of WriteReq MSHR miss cycles 2790system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 398994 # number of SwapReq MSHR miss cycles 2791system.cpu3.dcache.SwapReq_mshr_miss_latency::total 398994 # number of SwapReq MSHR miss cycles 2792system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2368007 # number of demand (read+write) MSHR miss cycles 2793system.cpu3.dcache.demand_mshr_miss_latency::total 2368007 # number of demand (read+write) MSHR miss cycles 2794system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2368007 # number of overall MSHR miss cycles 2795system.cpu3.dcache.overall_mshr_miss_latency::total 2368007 # number of overall MSHR miss cycles 2796system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003819 # mshr miss rate for ReadReq accesses 2797system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003819 # mshr miss rate for ReadReq accesses 2798system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003277 # mshr miss rate for WriteReq accesses 2799system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003277 # mshr miss rate for WriteReq accesses 2800system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.788732 # mshr miss rate for SwapReq accesses 2801system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.788732 # mshr miss rate for SwapReq accesses 2802system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003591 # mshr miss rate for demand accesses 2803system.cpu3.dcache.demand_mshr_miss_rate::total 0.003591 # mshr miss rate for demand accesses 2804system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003591 # mshr miss rate for overall accesses 2805system.cpu3.dcache.overall_mshr_miss_rate::total 0.003591 # mshr miss rate for overall accesses 2806system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6692.658385 # average ReadReq mshr miss latency 2807system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6692.658385 # average ReadReq mshr miss latency 2808system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12904.890000 # average WriteReq mshr miss latency 2809system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12904.890000 # average WriteReq mshr miss latency 2810system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7124.892857 # average SwapReq mshr miss latency 2811system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7124.892857 # average SwapReq mshr miss latency 2812system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9072.823755 # average overall mshr miss latency 2813system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9072.823755 # average overall mshr miss latency 2814system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9072.823755 # average overall mshr miss latency 2815system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9072.823755 # average overall mshr miss latency | 2773system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 269 # number of ReadReq MSHR hits 2774system.cpu3.dcache.ReadReq_mshr_hits::total 269 # number of ReadReq MSHR hits 2775system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits 2776system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits 2777system.cpu3.dcache.demand_mshr_hits::cpu3.data 302 # number of demand (read+write) MSHR hits 2778system.cpu3.dcache.demand_mshr_hits::total 302 # number of demand (read+write) MSHR hits 2779system.cpu3.dcache.overall_mshr_hits::cpu3.data 302 # number of overall MSHR hits 2780system.cpu3.dcache.overall_mshr_hits::total 302 # number of overall MSHR hits 2781system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses 2782system.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses 2783system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses 2784system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses 2785system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses 2786system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses 2787system.cpu3.dcache.demand_mshr_misses::cpu3.data 270 # number of demand (read+write) MSHR misses 2788system.cpu3.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses 2789system.cpu3.dcache.overall_mshr_misses::cpu3.data 270 # number of overall MSHR misses 2790system.cpu3.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses 2791system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1168525 # number of ReadReq MSHR miss cycles 2792system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1168525 # number of ReadReq MSHR miss cycles 2793system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1299988 # number of WriteReq MSHR miss cycles 2794system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1299988 # number of WriteReq MSHR miss cycles 2795system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 401492 # number of SwapReq MSHR miss cycles 2796system.cpu3.dcache.SwapReq_mshr_miss_latency::total 401492 # number of SwapReq MSHR miss cycles 2797system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2468513 # number of demand (read+write) MSHR miss cycles 2798system.cpu3.dcache.demand_mshr_miss_latency::total 2468513 # number of demand (read+write) MSHR miss cycles 2799system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2468513 # number of overall MSHR miss cycles 2800system.cpu3.dcache.overall_mshr_miss_latency::total 2468513 # number of overall MSHR miss cycles 2801system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004083 # mshr miss rate for ReadReq accesses 2802system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004083 # mshr miss rate for ReadReq accesses 2803system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003762 # mshr miss rate for WriteReq accesses 2804system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003762 # mshr miss rate for WriteReq accesses 2805system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.814286 # mshr miss rate for SwapReq accesses 2806system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.814286 # mshr miss rate for SwapReq accesses 2807system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003949 # mshr miss rate for demand accesses 2808system.cpu3.dcache.demand_mshr_miss_rate::total 0.003949 # mshr miss rate for demand accesses 2809system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003949 # mshr miss rate for overall accesses 2810system.cpu3.dcache.overall_mshr_miss_rate::total 0.003949 # mshr miss rate for overall accesses 2811system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 7168.865031 # average ReadReq mshr miss latency 2812system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 7168.865031 # average ReadReq mshr miss latency 2813system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12149.420561 # average WriteReq mshr miss latency 2814system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12149.420561 # average WriteReq mshr miss latency 2815system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7043.719298 # average SwapReq mshr miss latency 2816system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7043.719298 # average SwapReq mshr miss latency 2817system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9142.640741 # average overall mshr miss latency 2818system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9142.640741 # average overall mshr miss latency 2819system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9142.640741 # average overall mshr miss latency 2820system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9142.640741 # average overall mshr miss latency |
2816system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2817 2818---------- End Simulation Statistics ---------- | 2821system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2822 2823---------- End Simulation Statistics ---------- |