| stats.txt (10148:4574d5882066) | stats.txt (10220:9eab5efc02e8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000111 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000111 # Number of seconds simulated |
| 4sim_ticks 110955500 # Number of ticks simulated 5final_tick 110955500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 110872500 # Number of ticks simulated 5final_tick 110872500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 120250 # Simulator instruction rate (inst/s) 8host_op_rate 120250 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 12800201 # Simulator tick rate (ticks/s) 10host_mem_usage 288992 # Number of bytes of host memory used 11host_seconds 8.67 # Real time elapsed on the host 12sim_insts 1042358 # Number of instructions simulated 13sim_ops 1042358 # Number of ops (including micro ops) simulated | 7host_inst_rate 118027 # Simulator instruction rate (inst/s) 8host_op_rate 118027 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 12557410 # Simulator tick rate (ticks/s) 10host_mem_usage 289008 # Number of bytes of host memory used 11host_seconds 8.83 # Real time elapsed on the host 12sim_insts 1042088 # Number of instructions simulated 13sim_ops 1042088 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu2.inst 4608 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory --- 9 unchanged lines hidden (view full) --- 31system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu2.inst 72 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu3.inst 7 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 659 # Number of read requests responded to by this memory | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu2.inst 4608 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory --- 9 unchanged lines hidden (view full) --- 31system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu2.inst 72 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu3.inst 7 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 659 # Number of read requests responded to by this memory |
| 39system.physmem.bw_read::cpu0.inst 205343584 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu0.data 96903714 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu1.inst 5768078 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.data 7498502 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu2.inst 41530163 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu2.data 11536156 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu3.inst 4037655 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu3.data 7498502 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::total 380116353 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu0.inst 205343584 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu1.inst 5768078 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::cpu2.inst 41530163 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu3.inst 4037655 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::total 256679480 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_total::cpu0.inst 205343584 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu0.data 96903714 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu1.inst 5768078 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.data 7498502 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu2.inst 41530163 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.data 11536156 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu3.inst 4037655 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.data 7498502 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::total 380116353 # Total bandwidth to/from this memory (bytes/s) | 39system.physmem.bw_read::cpu0.inst 205497305 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu0.data 96976257 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu1.inst 5772396 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.data 7504115 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu2.inst 41561253 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu2.data 11544792 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu3.inst 4040677 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu3.data 7504115 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::total 380400911 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu0.inst 205497305 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu1.inst 5772396 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::cpu2.inst 41561253 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu3.inst 4040677 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::total 256871632 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_total::cpu0.inst 205497305 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu0.data 96976257 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu1.inst 5772396 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.data 7504115 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu2.inst 41561253 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.data 11544792 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu3.inst 4040677 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.data 7504115 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::total 380400911 # Total bandwidth to/from this memory (bytes/s) |
| 62system.physmem.readReqs 660 # Number of read requests accepted 63system.physmem.writeReqs 0 # Number of write requests accepted 64system.physmem.readBursts 660 # Number of DRAM read bursts, including those serviced by the write queue 65system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 66system.physmem.bytesReadDRAM 42240 # Total number of bytes read from DRAM 67system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 68system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 69system.physmem.bytesReadSys 42240 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 100system.physmem.perBankWrBursts::10 0 # Per bank write bursts 101system.physmem.perBankWrBursts::11 0 # Per bank write bursts 102system.physmem.perBankWrBursts::12 0 # Per bank write bursts 103system.physmem.perBankWrBursts::13 0 # Per bank write bursts 104system.physmem.perBankWrBursts::14 0 # Per bank write bursts 105system.physmem.perBankWrBursts::15 0 # Per bank write bursts 106system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 107system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 62system.physmem.readReqs 660 # Number of read requests accepted 63system.physmem.writeReqs 0 # Number of write requests accepted 64system.physmem.readBursts 660 # Number of DRAM read bursts, including those serviced by the write queue 65system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 66system.physmem.bytesReadDRAM 42240 # Total number of bytes read from DRAM 67system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 68system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 69system.physmem.bytesReadSys 42240 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 100system.physmem.perBankWrBursts::10 0 # Per bank write bursts 101system.physmem.perBankWrBursts::11 0 # Per bank write bursts 102system.physmem.perBankWrBursts::12 0 # Per bank write bursts 103system.physmem.perBankWrBursts::13 0 # Per bank write bursts 104system.physmem.perBankWrBursts::14 0 # Per bank write bursts 105system.physmem.perBankWrBursts::15 0 # Per bank write bursts 106system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 107system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 108system.physmem.totGap 110927500 # Total gap between requests | 108system.physmem.totGap 110844500 # Total gap between requests |
| 109system.physmem.readPktSize::0 0 # Read request sizes (log2) 110system.physmem.readPktSize::1 0 # Read request sizes (log2) 111system.physmem.readPktSize::2 0 # Read request sizes (log2) 112system.physmem.readPktSize::3 0 # Read request sizes (log2) 113system.physmem.readPktSize::4 0 # Read request sizes (log2) 114system.physmem.readPktSize::5 0 # Read request sizes (log2) 115system.physmem.readPktSize::6 660 # Read request sizes (log2) 116system.physmem.writePktSize::0 0 # Write request sizes (log2) 117system.physmem.writePktSize::1 0 # Write request sizes (log2) 118system.physmem.writePktSize::2 0 # Write request sizes (log2) 119system.physmem.writePktSize::3 0 # Write request sizes (log2) 120system.physmem.writePktSize::4 0 # Write request sizes (log2) 121system.physmem.writePktSize::5 0 # Write request sizes (log2) 122system.physmem.writePktSize::6 0 # Write request sizes (log2) | 109system.physmem.readPktSize::0 0 # Read request sizes (log2) 110system.physmem.readPktSize::1 0 # Read request sizes (log2) 111system.physmem.readPktSize::2 0 # Read request sizes (log2) 112system.physmem.readPktSize::3 0 # Read request sizes (log2) 113system.physmem.readPktSize::4 0 # Read request sizes (log2) 114system.physmem.readPktSize::5 0 # Read request sizes (log2) 115system.physmem.readPktSize::6 660 # Read request sizes (log2) 116system.physmem.writePktSize::0 0 # Write request sizes (log2) 117system.physmem.writePktSize::1 0 # Write request sizes (log2) 118system.physmem.writePktSize::2 0 # Write request sizes (log2) 119system.physmem.writePktSize::3 0 # Write request sizes (log2) 120system.physmem.writePktSize::4 0 # Write request sizes (log2) 121system.physmem.writePktSize::5 0 # Write request sizes (log2) 122system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 123system.physmem.rdQLenPdf::0 409 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::1 188 # What read queue length does an incoming req see | 123system.physmem.rdQLenPdf::0 403 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::1 194 # What read queue length does an incoming req see |
| 125system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 78 unchanged lines hidden (view full) --- 211system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 125system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 78 unchanged lines hidden (view full) --- 211system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 219system.physmem.bytesPerActivate::samples 89 # Bytes accessed per row activation 220system.physmem.bytesPerActivate::mean 285.483146 # Bytes accessed per row activation 221system.physmem.bytesPerActivate::gmean 186.878201 # Bytes accessed per row activation 222system.physmem.bytesPerActivate::stdev 280.642368 # Bytes accessed per row activation 223system.physmem.bytesPerActivate::0-127 28 31.46% 31.46% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::128-255 26 29.21% 60.67% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::256-383 13 14.61% 75.28% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::384-511 5 5.62% 80.90% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::512-639 5 5.62% 86.52% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::640-767 3 3.37% 89.89% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::768-895 2 2.25% 92.13% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::896-1023 1 1.12% 93.26% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::1024-1151 6 6.74% 100.00% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::total 89 # Bytes accessed per row activation 233system.physmem.totQLat 3793500 # Total ticks spent queuing 234system.physmem.totMemAccLat 17983500 # Total ticks spent from burst creation until serviced by the DRAM | 219system.physmem.bytesPerActivate::samples 148 # Bytes accessed per row activation 220system.physmem.bytesPerActivate::mean 275.027027 # Bytes accessed per row activation 221system.physmem.bytesPerActivate::gmean 186.656156 # Bytes accessed per row activation 222system.physmem.bytesPerActivate::stdev 254.302887 # Bytes accessed per row activation 223system.physmem.bytesPerActivate::0-127 45 30.41% 30.41% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::128-255 43 29.05% 59.46% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::256-383 21 14.19% 73.65% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::384-511 12 8.11% 81.76% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::512-639 10 6.76% 88.51% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::640-767 5 3.38% 91.89% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::768-895 5 3.38% 95.27% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::896-1023 1 0.68% 95.95% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::1024-1151 6 4.05% 100.00% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::total 148 # Bytes accessed per row activation 233system.physmem.totQLat 5597750 # Total ticks spent queuing 234system.physmem.totMemAccLat 17972750 # Total ticks spent from burst creation until serviced by the DRAM |
| 235system.physmem.totBusLat 3300000 # Total ticks spent in databus transfers | 235system.physmem.totBusLat 3300000 # Total ticks spent in databus transfers |
| 236system.physmem.totBankLat 10890000 # Total ticks spent accessing banks 237system.physmem.avgQLat 5747.73 # Average queueing delay per DRAM burst 238system.physmem.avgBankLat 16500.00 # Average bank access latency per DRAM burst | 236system.physmem.avgQLat 8481.44 # Average queueing delay per DRAM burst |
| 239system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 237system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 240system.physmem.avgMemAccLat 27247.73 # Average memory access latency per DRAM burst 241system.physmem.avgRdBW 380.69 # Average DRAM read bandwidth in MiByte/s | 238system.physmem.avgMemAccLat 27231.44 # Average memory access latency per DRAM burst 239system.physmem.avgRdBW 380.98 # Average DRAM read bandwidth in MiByte/s |
| 242system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 240system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 243system.physmem.avgRdBWSys 380.69 # Average system read bandwidth in MiByte/s | 241system.physmem.avgRdBWSys 380.98 # Average system read bandwidth in MiByte/s |
| 244system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 245system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 242system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 243system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 246system.physmem.busUtil 2.97 # Data bus utilization in percentage 247system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads | 244system.physmem.busUtil 2.98 # Data bus utilization in percentage 245system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads |
| 248system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 249system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing 250system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 251system.physmem.readRowHits 505 # Number of row buffer hits during reads 252system.physmem.writeRowHits 0 # Number of row buffer hits during writes 253system.physmem.readRowHitRate 76.52 # Row buffer hit rate for reads 254system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 246system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 247system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing 248system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 249system.physmem.readRowHits 505 # Number of row buffer hits during reads 250system.physmem.writeRowHits 0 # Number of row buffer hits during writes 251system.physmem.readRowHitRate 76.52 # Row buffer hit rate for reads 252system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 255system.physmem.avgGap 168071.97 # Average gap between requests | 253system.physmem.avgGap 167946.21 # Average gap between requests |
| 256system.physmem.pageHitRate 76.52 # Row buffer hit rate, read and write combined | 254system.physmem.pageHitRate 76.52 # Row buffer hit rate, read and write combined |
| 257system.physmem.prechargeAllPercent 9.12 # Percentage of time for which DRAM has all the banks in precharge state 258system.membus.throughput 380116353 # Throughput (bytes/s) | 255system.physmem.memoryStateTime::IDLE 48028250 # Time in different power states 256system.physmem.memoryStateTime::REF 3640000 # Time in different power states 257system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 258system.physmem.memoryStateTime::ACT 57613000 # Time in different power states 259system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 260system.membus.throughput 380400911 # Throughput (bytes/s) |
| 259system.membus.trans_dist::ReadReq 529 # Transaction distribution 260system.membus.trans_dist::ReadResp 528 # Transaction distribution 261system.membus.trans_dist::UpgradeReq 287 # Transaction distribution 262system.membus.trans_dist::UpgradeResp 77 # Transaction distribution 263system.membus.trans_dist::ReadExReq 163 # Transaction distribution 264system.membus.trans_dist::ReadExResp 131 # Transaction distribution 265system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1715 # Packet count per connected master and slave (bytes) 266system.membus.pkt_count::total 1715 # Packet count per connected master and slave (bytes) 267system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42176 # Cumulative packet size per connected master and slave (bytes) 268system.membus.tot_pkt_size::total 42176 # Cumulative packet size per connected master and slave (bytes) 269system.membus.data_through_bus 42176 # Total data (bytes) 270system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 261system.membus.trans_dist::ReadReq 529 # Transaction distribution 262system.membus.trans_dist::ReadResp 528 # Transaction distribution 263system.membus.trans_dist::UpgradeReq 287 # Transaction distribution 264system.membus.trans_dist::UpgradeResp 77 # Transaction distribution 265system.membus.trans_dist::ReadExReq 163 # Transaction distribution 266system.membus.trans_dist::ReadExResp 131 # Transaction distribution 267system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1715 # Packet count per connected master and slave (bytes) 268system.membus.pkt_count::total 1715 # Packet count per connected master and slave (bytes) 269system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42176 # Cumulative packet size per connected master and slave (bytes) 270system.membus.tot_pkt_size::total 42176 # Cumulative packet size per connected master and slave (bytes) 271system.membus.data_through_bus 42176 # Total data (bytes) 272system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 271system.membus.reqLayer0.occupancy 925000 # Layer occupancy (ticks) | 273system.membus.reqLayer0.occupancy 925500 # Layer occupancy (ticks) |
| 272system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) | 274system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) |
| 273system.membus.respLayer1.occupancy 6291924 # Layer occupancy (ticks) | 275system.membus.respLayer1.occupancy 6302174 # Layer occupancy (ticks) |
| 274system.membus.respLayer1.utilization 5.7 # Layer utilization (%) 275system.cpu_clk_domain.clock 500 # Clock period in ticks 276system.l2c.tags.replacements 0 # number of replacements | 276system.membus.respLayer1.utilization 5.7 # Layer utilization (%) 277system.cpu_clk_domain.clock 500 # Clock period in ticks 278system.l2c.tags.replacements 0 # number of replacements |
| 277system.l2c.tags.tagsinuse 417.123879 # Cycle average of tags in use | 279system.l2c.tags.tagsinuse 417.213115 # Cycle average of tags in use |
| 278system.l2c.tags.total_refs 1443 # Total number of references to valid blocks. 279system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks. 280system.l2c.tags.avg_refs 2.743346 # Average number of references to valid blocks. 281system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 280system.l2c.tags.total_refs 1443 # Total number of references to valid blocks. 281system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks. 282system.l2c.tags.avg_refs 2.743346 # Average number of references to valid blocks. 283system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 282system.l2c.tags.occ_blocks::writebacks 0.799384 # Average occupied blocks per requestor 283system.l2c.tags.occ_blocks::cpu0.inst 285.051208 # Average occupied blocks per requestor 284system.l2c.tags.occ_blocks::cpu0.data 58.412458 # Average occupied blocks per requestor 285system.l2c.tags.occ_blocks::cpu1.inst 7.037952 # Average occupied blocks per requestor 286system.l2c.tags.occ_blocks::cpu1.data 0.694517 # Average occupied blocks per requestor 287system.l2c.tags.occ_blocks::cpu2.inst 55.368542 # Average occupied blocks per requestor 288system.l2c.tags.occ_blocks::cpu2.data 5.407900 # Average occupied blocks per requestor 289system.l2c.tags.occ_blocks::cpu3.inst 3.619836 # Average occupied blocks per requestor 290system.l2c.tags.occ_blocks::cpu3.data 0.732082 # Average occupied blocks per requestor | 284system.l2c.tags.occ_blocks::writebacks 0.799585 # Average occupied blocks per requestor 285system.l2c.tags.occ_blocks::cpu0.inst 285.091922 # Average occupied blocks per requestor 286system.l2c.tags.occ_blocks::cpu0.data 58.421534 # Average occupied blocks per requestor 287system.l2c.tags.occ_blocks::cpu1.inst 7.040102 # Average occupied blocks per requestor 288system.l2c.tags.occ_blocks::cpu1.data 0.695019 # Average occupied blocks per requestor 289system.l2c.tags.occ_blocks::cpu2.inst 55.399606 # Average occupied blocks per requestor 290system.l2c.tags.occ_blocks::cpu2.data 5.410902 # Average occupied blocks per requestor 291system.l2c.tags.occ_blocks::cpu3.inst 3.621924 # Average occupied blocks per requestor 292system.l2c.tags.occ_blocks::cpu3.data 0.732522 # Average occupied blocks per requestor |
| 291system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy 292system.l2c.tags.occ_percent::cpu0.inst 0.004350 # Average percentage of cache occupancy 293system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy 294system.l2c.tags.occ_percent::cpu1.inst 0.000107 # Average percentage of cache occupancy 295system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy 296system.l2c.tags.occ_percent::cpu2.inst 0.000845 # Average percentage of cache occupancy 297system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy 298system.l2c.tags.occ_percent::cpu3.inst 0.000055 # Average percentage of cache occupancy 299system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy | 293system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy 294system.l2c.tags.occ_percent::cpu0.inst 0.004350 # Average percentage of cache occupancy 295system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy 296system.l2c.tags.occ_percent::cpu1.inst 0.000107 # Average percentage of cache occupancy 297system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy 298system.l2c.tags.occ_percent::cpu2.inst 0.000845 # Average percentage of cache occupancy 299system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy 300system.l2c.tags.occ_percent::cpu3.inst 0.000055 # Average percentage of cache occupancy 301system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy |
| 300system.l2c.tags.occ_percent::total 0.006365 # Average percentage of cache occupancy | 302system.l2c.tags.occ_percent::total 0.006366 # Average percentage of cache occupancy |
| 301system.l2c.tags.occ_task_id_blocks::1024 526 # Occupied blocks per task id 302system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id | 303system.l2c.tags.occ_task_id_blocks::1024 526 # Occupied blocks per task id 304system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id |
| 303system.l2c.tags.age_task_id_blocks_1024::1 295 # Occupied blocks per task id 304system.l2c.tags.age_task_id_blocks_1024::2 180 # Occupied blocks per task id | 305system.l2c.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id 306system.l2c.tags.age_task_id_blocks_1024::2 179 # Occupied blocks per task id |
| 305system.l2c.tags.occ_task_id_percent::1024 0.008026 # Percentage of cache occupancy per task id 306system.l2c.tags.tag_accesses 18244 # Number of tag accesses 307system.l2c.tags.data_accesses 18244 # Number of data accesses 308system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits 309system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 310system.l2c.ReadReq_hits::cpu1.inst 413 # number of ReadReq hits 311system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits 312system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits --- 55 unchanged lines hidden (view full) --- 368system.l2c.overall_misses::cpu0.data 168 # number of overall misses 369system.l2c.overall_misses::cpu1.inst 15 # number of overall misses 370system.l2c.overall_misses::cpu1.data 13 # number of overall misses 371system.l2c.overall_misses::cpu2.inst 76 # number of overall misses 372system.l2c.overall_misses::cpu2.data 20 # number of overall misses 373system.l2c.overall_misses::cpu3.inst 10 # number of overall misses 374system.l2c.overall_misses::cpu3.data 13 # number of overall misses 375system.l2c.overall_misses::total 674 # number of overall misses | 307system.l2c.tags.occ_task_id_percent::1024 0.008026 # Percentage of cache occupancy per task id 308system.l2c.tags.tag_accesses 18244 # Number of tag accesses 309system.l2c.tags.data_accesses 18244 # Number of data accesses 310system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits 311system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 312system.l2c.ReadReq_hits::cpu1.inst 413 # number of ReadReq hits 313system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits 314system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits --- 55 unchanged lines hidden (view full) --- 370system.l2c.overall_misses::cpu0.data 168 # number of overall misses 371system.l2c.overall_misses::cpu1.inst 15 # number of overall misses 372system.l2c.overall_misses::cpu1.data 13 # number of overall misses 373system.l2c.overall_misses::cpu2.inst 76 # number of overall misses 374system.l2c.overall_misses::cpu2.data 20 # number of overall misses 375system.l2c.overall_misses::cpu3.inst 10 # number of overall misses 376system.l2c.overall_misses::cpu3.data 13 # number of overall misses 377system.l2c.overall_misses::total 674 # number of overall misses |
| 376system.l2c.ReadReq_miss_latency::cpu0.inst 24538000 # number of ReadReq miss cycles 377system.l2c.ReadReq_miss_latency::cpu0.data 5612000 # number of ReadReq miss cycles 378system.l2c.ReadReq_miss_latency::cpu1.inst 1134000 # number of ReadReq miss cycles | 378system.l2c.ReadReq_miss_latency::cpu0.inst 24533250 # number of ReadReq miss cycles 379system.l2c.ReadReq_miss_latency::cpu0.data 5569000 # number of ReadReq miss cycles 380system.l2c.ReadReq_miss_latency::cpu1.inst 1122250 # number of ReadReq miss cycles |
| 379system.l2c.ReadReq_miss_latency::cpu1.data 74500 # number of ReadReq miss cycles | 381system.l2c.ReadReq_miss_latency::cpu1.data 74500 # number of ReadReq miss cycles |
| 380system.l2c.ReadReq_miss_latency::cpu2.inst 5318500 # number of ReadReq miss cycles | 382system.l2c.ReadReq_miss_latency::cpu2.inst 5286500 # number of ReadReq miss cycles |
| 381system.l2c.ReadReq_miss_latency::cpu2.data 495250 # number of ReadReq miss cycles 382system.l2c.ReadReq_miss_latency::cpu3.inst 658250 # number of ReadReq miss cycles 383system.l2c.ReadReq_miss_latency::cpu3.data 74500 # number of ReadReq miss cycles | 383system.l2c.ReadReq_miss_latency::cpu2.data 495250 # number of ReadReq miss cycles 384system.l2c.ReadReq_miss_latency::cpu3.inst 658250 # number of ReadReq miss cycles 385system.l2c.ReadReq_miss_latency::cpu3.data 74500 # number of ReadReq miss cycles |
| 384system.l2c.ReadReq_miss_latency::total 37905000 # number of ReadReq miss cycles 385system.l2c.ReadExReq_miss_latency::cpu0.data 6786000 # number of ReadExReq miss cycles | 386system.l2c.ReadReq_miss_latency::total 37813500 # number of ReadReq miss cycles 387system.l2c.ReadExReq_miss_latency::cpu0.data 6780000 # number of ReadExReq miss cycles |
| 386system.l2c.ReadExReq_miss_latency::cpu1.data 852250 # number of ReadExReq miss cycles 387system.l2c.ReadExReq_miss_latency::cpu2.data 1087000 # number of ReadExReq miss cycles | 388system.l2c.ReadExReq_miss_latency::cpu1.data 852250 # number of ReadExReq miss cycles 389system.l2c.ReadExReq_miss_latency::cpu2.data 1087000 # number of ReadExReq miss cycles |
| 388system.l2c.ReadExReq_miss_latency::cpu3.data 978750 # number of ReadExReq miss cycles 389system.l2c.ReadExReq_miss_latency::total 9704000 # number of ReadExReq miss cycles 390system.l2c.demand_miss_latency::cpu0.inst 24538000 # number of demand (read+write) miss cycles 391system.l2c.demand_miss_latency::cpu0.data 12398000 # number of demand (read+write) miss cycles 392system.l2c.demand_miss_latency::cpu1.inst 1134000 # number of demand (read+write) miss cycles | 390system.l2c.ReadExReq_miss_latency::cpu3.data 943000 # number of ReadExReq miss cycles 391system.l2c.ReadExReq_miss_latency::total 9662250 # number of ReadExReq miss cycles 392system.l2c.demand_miss_latency::cpu0.inst 24533250 # number of demand (read+write) miss cycles 393system.l2c.demand_miss_latency::cpu0.data 12349000 # number of demand (read+write) miss cycles 394system.l2c.demand_miss_latency::cpu1.inst 1122250 # number of demand (read+write) miss cycles |
| 393system.l2c.demand_miss_latency::cpu1.data 926750 # number of demand (read+write) miss cycles | 395system.l2c.demand_miss_latency::cpu1.data 926750 # number of demand (read+write) miss cycles |
| 394system.l2c.demand_miss_latency::cpu2.inst 5318500 # number of demand (read+write) miss cycles | 396system.l2c.demand_miss_latency::cpu2.inst 5286500 # number of demand (read+write) miss cycles |
| 395system.l2c.demand_miss_latency::cpu2.data 1582250 # number of demand (read+write) miss cycles 396system.l2c.demand_miss_latency::cpu3.inst 658250 # number of demand (read+write) miss cycles | 397system.l2c.demand_miss_latency::cpu2.data 1582250 # number of demand (read+write) miss cycles 398system.l2c.demand_miss_latency::cpu3.inst 658250 # number of demand (read+write) miss cycles |
| 397system.l2c.demand_miss_latency::cpu3.data 1053250 # number of demand (read+write) miss cycles 398system.l2c.demand_miss_latency::total 47609000 # number of demand (read+write) miss cycles 399system.l2c.overall_miss_latency::cpu0.inst 24538000 # number of overall miss cycles 400system.l2c.overall_miss_latency::cpu0.data 12398000 # number of overall miss cycles 401system.l2c.overall_miss_latency::cpu1.inst 1134000 # number of overall miss cycles | 399system.l2c.demand_miss_latency::cpu3.data 1017500 # number of demand (read+write) miss cycles 400system.l2c.demand_miss_latency::total 47475750 # number of demand (read+write) miss cycles 401system.l2c.overall_miss_latency::cpu0.inst 24533250 # number of overall miss cycles 402system.l2c.overall_miss_latency::cpu0.data 12349000 # number of overall miss cycles 403system.l2c.overall_miss_latency::cpu1.inst 1122250 # number of overall miss cycles |
| 402system.l2c.overall_miss_latency::cpu1.data 926750 # number of overall miss cycles | 404system.l2c.overall_miss_latency::cpu1.data 926750 # number of overall miss cycles |
| 403system.l2c.overall_miss_latency::cpu2.inst 5318500 # number of overall miss cycles | 405system.l2c.overall_miss_latency::cpu2.inst 5286500 # number of overall miss cycles |
| 404system.l2c.overall_miss_latency::cpu2.data 1582250 # number of overall miss cycles 405system.l2c.overall_miss_latency::cpu3.inst 658250 # number of overall miss cycles | 406system.l2c.overall_miss_latency::cpu2.data 1582250 # number of overall miss cycles 407system.l2c.overall_miss_latency::cpu3.inst 658250 # number of overall miss cycles |
| 406system.l2c.overall_miss_latency::cpu3.data 1053250 # number of overall miss cycles 407system.l2c.overall_miss_latency::total 47609000 # number of overall miss cycles | 408system.l2c.overall_miss_latency::cpu3.data 1017500 # number of overall miss cycles 409system.l2c.overall_miss_latency::total 47475750 # number of overall miss cycles |
| 408system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses) 409system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) 410system.l2c.ReadReq_accesses::cpu1.inst 428 # number of ReadReq accesses(hits+misses) 411system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) 412system.l2c.ReadReq_accesses::cpu2.inst 425 # number of ReadReq accesses(hits+misses) 413system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) 414system.l2c.ReadReq_accesses::cpu3.inst 430 # number of ReadReq accesses(hits+misses) 415system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) --- 60 unchanged lines hidden (view full) --- 476system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses 477system.l2c.overall_miss_rate::cpu1.inst 0.035047 # miss rate for overall accesses 478system.l2c.overall_miss_rate::cpu1.data 0.541667 # miss rate for overall accesses 479system.l2c.overall_miss_rate::cpu2.inst 0.178824 # miss rate for overall accesses 480system.l2c.overall_miss_rate::cpu2.data 0.800000 # miss rate for overall accesses 481system.l2c.overall_miss_rate::cpu3.inst 0.023256 # miss rate for overall accesses 482system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses 483system.l2c.overall_miss_rate::total 0.318375 # miss rate for overall accesses | 410system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses) 411system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) 412system.l2c.ReadReq_accesses::cpu1.inst 428 # number of ReadReq accesses(hits+misses) 413system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) 414system.l2c.ReadReq_accesses::cpu2.inst 425 # number of ReadReq accesses(hits+misses) 415system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) 416system.l2c.ReadReq_accesses::cpu3.inst 430 # number of ReadReq accesses(hits+misses) 417system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) --- 60 unchanged lines hidden (view full) --- 478system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses 479system.l2c.overall_miss_rate::cpu1.inst 0.035047 # miss rate for overall accesses 480system.l2c.overall_miss_rate::cpu1.data 0.541667 # miss rate for overall accesses 481system.l2c.overall_miss_rate::cpu2.inst 0.178824 # miss rate for overall accesses 482system.l2c.overall_miss_rate::cpu2.data 0.800000 # miss rate for overall accesses 483system.l2c.overall_miss_rate::cpu3.inst 0.023256 # miss rate for overall accesses 484system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses 485system.l2c.overall_miss_rate::total 0.318375 # miss rate for overall accesses |
| 484system.l2c.ReadReq_avg_miss_latency::cpu0.inst 68350.974930 # average ReadReq miss latency 485system.l2c.ReadReq_avg_miss_latency::cpu0.data 75837.837838 # average ReadReq miss latency 486system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75600 # average ReadReq miss latency | 486system.l2c.ReadReq_avg_miss_latency::cpu0.inst 68337.743733 # average ReadReq miss latency 487system.l2c.ReadReq_avg_miss_latency::cpu0.data 75256.756757 # average ReadReq miss latency 488system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74816.666667 # average ReadReq miss latency |
| 487system.l2c.ReadReq_avg_miss_latency::cpu1.data 74500 # average ReadReq miss latency | 489system.l2c.ReadReq_avg_miss_latency::cpu1.data 74500 # average ReadReq miss latency |
| 488system.l2c.ReadReq_avg_miss_latency::cpu2.inst 69980.263158 # average ReadReq miss latency | 490system.l2c.ReadReq_avg_miss_latency::cpu2.inst 69559.210526 # average ReadReq miss latency |
| 489system.l2c.ReadReq_avg_miss_latency::cpu2.data 70750 # average ReadReq miss latency 490system.l2c.ReadReq_avg_miss_latency::cpu3.inst 65825 # average ReadReq miss latency 491system.l2c.ReadReq_avg_miss_latency::cpu3.data 74500 # average ReadReq miss latency | 491system.l2c.ReadReq_avg_miss_latency::cpu2.data 70750 # average ReadReq miss latency 492system.l2c.ReadReq_avg_miss_latency::cpu3.inst 65825 # average ReadReq miss latency 493system.l2c.ReadReq_avg_miss_latency::cpu3.data 74500 # average ReadReq miss latency |
| 492system.l2c.ReadReq_avg_miss_latency::total 69806.629834 # average ReadReq miss latency 493system.l2c.ReadExReq_avg_miss_latency::cpu0.data 72191.489362 # average ReadExReq miss latency | 494system.l2c.ReadReq_avg_miss_latency::total 69638.121547 # average ReadReq miss latency 495system.l2c.ReadExReq_avg_miss_latency::cpu0.data 72127.659574 # average ReadExReq miss latency |
| 494system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71020.833333 # average ReadExReq miss latency 495system.l2c.ReadExReq_avg_miss_latency::cpu2.data 83615.384615 # average ReadExReq miss latency | 496system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71020.833333 # average ReadExReq miss latency 497system.l2c.ReadExReq_avg_miss_latency::cpu2.data 83615.384615 # average ReadExReq miss latency |
| 496system.l2c.ReadExReq_avg_miss_latency::cpu3.data 81562.500000 # average ReadExReq miss latency 497system.l2c.ReadExReq_avg_miss_latency::total 74076.335878 # average ReadExReq miss latency 498system.l2c.demand_avg_miss_latency::cpu0.inst 68350.974930 # average overall miss latency 499system.l2c.demand_avg_miss_latency::cpu0.data 73797.619048 # average overall miss latency 500system.l2c.demand_avg_miss_latency::cpu1.inst 75600 # average overall miss latency | 498system.l2c.ReadExReq_avg_miss_latency::cpu3.data 78583.333333 # average ReadExReq miss latency 499system.l2c.ReadExReq_avg_miss_latency::total 73757.633588 # average ReadExReq miss latency 500system.l2c.demand_avg_miss_latency::cpu0.inst 68337.743733 # average overall miss latency 501system.l2c.demand_avg_miss_latency::cpu0.data 73505.952381 # average overall miss latency 502system.l2c.demand_avg_miss_latency::cpu1.inst 74816.666667 # average overall miss latency |
| 501system.l2c.demand_avg_miss_latency::cpu1.data 71288.461538 # average overall miss latency | 503system.l2c.demand_avg_miss_latency::cpu1.data 71288.461538 # average overall miss latency |
| 502system.l2c.demand_avg_miss_latency::cpu2.inst 69980.263158 # average overall miss latency | 504system.l2c.demand_avg_miss_latency::cpu2.inst 69559.210526 # average overall miss latency |
| 503system.l2c.demand_avg_miss_latency::cpu2.data 79112.500000 # average overall miss latency 504system.l2c.demand_avg_miss_latency::cpu3.inst 65825 # average overall miss latency | 505system.l2c.demand_avg_miss_latency::cpu2.data 79112.500000 # average overall miss latency 506system.l2c.demand_avg_miss_latency::cpu3.inst 65825 # average overall miss latency |
| 505system.l2c.demand_avg_miss_latency::cpu3.data 81019.230769 # average overall miss latency 506system.l2c.demand_avg_miss_latency::total 70636.498516 # average overall miss latency 507system.l2c.overall_avg_miss_latency::cpu0.inst 68350.974930 # average overall miss latency 508system.l2c.overall_avg_miss_latency::cpu0.data 73797.619048 # average overall miss latency 509system.l2c.overall_avg_miss_latency::cpu1.inst 75600 # average overall miss latency | 507system.l2c.demand_avg_miss_latency::cpu3.data 78269.230769 # average overall miss latency 508system.l2c.demand_avg_miss_latency::total 70438.798220 # average overall miss latency 509system.l2c.overall_avg_miss_latency::cpu0.inst 68337.743733 # average overall miss latency 510system.l2c.overall_avg_miss_latency::cpu0.data 73505.952381 # average overall miss latency 511system.l2c.overall_avg_miss_latency::cpu1.inst 74816.666667 # average overall miss latency |
| 510system.l2c.overall_avg_miss_latency::cpu1.data 71288.461538 # average overall miss latency | 512system.l2c.overall_avg_miss_latency::cpu1.data 71288.461538 # average overall miss latency |
| 511system.l2c.overall_avg_miss_latency::cpu2.inst 69980.263158 # average overall miss latency | 513system.l2c.overall_avg_miss_latency::cpu2.inst 69559.210526 # average overall miss latency |
| 512system.l2c.overall_avg_miss_latency::cpu2.data 79112.500000 # average overall miss latency 513system.l2c.overall_avg_miss_latency::cpu3.inst 65825 # average overall miss latency | 514system.l2c.overall_avg_miss_latency::cpu2.data 79112.500000 # average overall miss latency 515system.l2c.overall_avg_miss_latency::cpu3.inst 65825 # average overall miss latency |
| 514system.l2c.overall_avg_miss_latency::cpu3.data 81019.230769 # average overall miss latency 515system.l2c.overall_avg_miss_latency::total 70636.498516 # average overall miss latency | 516system.l2c.overall_avg_miss_latency::cpu3.data 78269.230769 # average overall miss latency 517system.l2c.overall_avg_miss_latency::total 70438.798220 # average overall miss latency |
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| 650system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55954.481793 # average ReadReq mshr miss latency 651system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63533.783784 # average ReadReq mshr miss latency 652system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71100 # average ReadReq mshr miss latency | 652system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55917.366947 # average ReadReq mshr miss latency 653system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62932.432432 # average ReadReq mshr miss latency 654system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69875 # average ReadReq mshr miss latency |
| 653system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62500 # average ReadReq mshr miss latency | 655system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62500 # average ReadReq mshr miss latency |
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| 655system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 58392.857143 # average ReadReq mshr miss latency 656system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 61607.142857 # average ReadReq mshr miss latency 657system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 62500 # average ReadReq mshr miss latency | 657system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 58392.857143 # average ReadReq mshr miss latency 658system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 61607.142857 # average ReadReq mshr miss latency 659system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 62500 # average ReadReq mshr miss latency |
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| 659system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency 660system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10500.947368 # average UpgradeReq mshr miss latency 661system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency 662system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency 663system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10124.363636 # average UpgradeReq mshr miss latency | 661system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency 662system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10500.947368 # average UpgradeReq mshr miss latency 663system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency 664system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency 665system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10124.363636 # average UpgradeReq mshr miss latency |
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| 665system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58479.166667 # average ReadExReq mshr miss latency 666system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71384.615385 # average ReadExReq mshr miss latency | 667system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58479.166667 # average ReadExReq mshr miss latency 668system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71384.615385 # average ReadExReq mshr miss latency |
| 667system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 69062.500000 # average ReadExReq mshr miss latency 668system.l2c.ReadExReq_avg_mshr_miss_latency::total 61641.221374 # average ReadExReq mshr miss latency 669system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55954.481793 # average overall mshr miss latency 670system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61416.666667 # average overall mshr miss latency 671system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71100 # average overall mshr miss latency | 669system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 66041.666667 # average ReadExReq mshr miss latency 670system.l2c.ReadExReq_avg_mshr_miss_latency::total 61288.167939 # average ReadExReq mshr miss latency 671system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55917.366947 # average overall mshr miss latency 672system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61092.261905 # average overall mshr miss latency 673system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69875 # average overall mshr miss latency |
| 672system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency | 674system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency |
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| 676system.l2c.demand_avg_mshr_miss_latency::cpu3.data 68557.692308 # average overall mshr miss latency 677system.l2c.demand_avg_mshr_miss_latency::total 58517.424242 # average overall mshr miss latency 678system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55954.481793 # average overall mshr miss latency 679system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61416.666667 # average overall mshr miss latency 680system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71100 # average overall mshr miss latency | 678system.l2c.demand_avg_mshr_miss_latency::cpu3.data 65769.230769 # average overall mshr miss latency 679system.l2c.demand_avg_mshr_miss_latency::total 58292.045455 # average overall mshr miss latency 680system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55917.366947 # average overall mshr miss latency 681system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61092.261905 # average overall mshr miss latency 682system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69875 # average overall mshr miss latency |
| 681system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency | 683system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency |
| 682system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 58239.583333 # average overall mshr miss latency | 684system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57788.194444 # average overall mshr miss latency |
| 683system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66837.500000 # average overall mshr miss latency 684system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61607.142857 # average overall mshr miss latency | 685system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66837.500000 # average overall mshr miss latency 686system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61607.142857 # average overall mshr miss latency |
| 685system.l2c.overall_avg_mshr_miss_latency::cpu3.data 68557.692308 # average overall mshr miss latency 686system.l2c.overall_avg_mshr_miss_latency::total 58517.424242 # average overall mshr miss latency | 687system.l2c.overall_avg_mshr_miss_latency::cpu3.data 65769.230769 # average overall mshr miss latency 688system.l2c.overall_avg_mshr_miss_latency::total 58292.045455 # average overall mshr miss latency |
| 687system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 689system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| 688system.toL2Bus.throughput 1688893295 # Throughput (bytes/s) | 690system.toL2Bus.throughput 1690157613 # Throughput (bytes/s) |
| 689system.toL2Bus.trans_dist::ReadReq 2536 # Transaction distribution 690system.toL2Bus.trans_dist::ReadResp 2535 # Transaction distribution 691system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution 692system.toL2Bus.trans_dist::UpgradeReq 290 # Transaction distribution 693system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution 694system.toL2Bus.trans_dist::ReadExReq 392 # Transaction distribution 695system.toL2Bus.trans_dist::ReadExResp 392 # Transaction distribution 696system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1175 # Packet count per connected master and slave (bytes) --- 11 unchanged lines hidden (view full) --- 708system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) 709system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 27200 # Cumulative packet size per connected master and slave (bytes) 710system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 711system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 27520 # Cumulative packet size per connected master and slave (bytes) 712system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) 713system.toL2Bus.tot_pkt_size::total 135488 # Cumulative packet size per connected master and slave (bytes) 714system.toL2Bus.data_through_bus 135488 # Total data (bytes) 715system.toL2Bus.snoop_data_through_bus 51904 # Total snoop data (bytes) | 691system.toL2Bus.trans_dist::ReadReq 2536 # Transaction distribution 692system.toL2Bus.trans_dist::ReadResp 2535 # Transaction distribution 693system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution 694system.toL2Bus.trans_dist::UpgradeReq 290 # Transaction distribution 695system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution 696system.toL2Bus.trans_dist::ReadExReq 392 # Transaction distribution 697system.toL2Bus.trans_dist::ReadExResp 392 # Transaction distribution 698system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1175 # Packet count per connected master and slave (bytes) --- 11 unchanged lines hidden (view full) --- 710system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) 711system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 27200 # Cumulative packet size per connected master and slave (bytes) 712system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 713system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 27520 # Cumulative packet size per connected master and slave (bytes) 714system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) 715system.toL2Bus.tot_pkt_size::total 135488 # Cumulative packet size per connected master and slave (bytes) 716system.toL2Bus.data_through_bus 135488 # Total data (bytes) 717system.toL2Bus.snoop_data_through_bus 51904 # Total snoop data (bytes) |
| 716system.toL2Bus.reqLayer0.occupancy 1624976 # Layer occupancy (ticks) | 718system.toL2Bus.reqLayer0.occupancy 1624477 # Layer occupancy (ticks) |
| 717system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) | 719system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) |
| 718system.toL2Bus.respLayer0.occupancy 2704748 # Layer occupancy (ticks) | 720system.toL2Bus.respLayer0.occupancy 2708498 # Layer occupancy (ticks) |
| 719system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) | 721system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) |
| 720system.toL2Bus.respLayer1.occupancy 1464514 # Layer occupancy (ticks) | 722system.toL2Bus.respLayer1.occupancy 1467012 # Layer occupancy (ticks) |
| 721system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) | 723system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) |
| 722system.toL2Bus.respLayer2.occupancy 1928496 # Layer occupancy (ticks) | 724system.toL2Bus.respLayer2.occupancy 1928746 # Layer occupancy (ticks) |
| 723system.toL2Bus.respLayer2.utilization 1.7 # Layer utilization (%) 724system.toL2Bus.respLayer3.occupancy 1148249 # Layer occupancy (ticks) 725system.toL2Bus.respLayer3.utilization 1.0 # Layer utilization (%) 726system.toL2Bus.respLayer4.occupancy 1927493 # Layer occupancy (ticks) 727system.toL2Bus.respLayer4.utilization 1.7 # Layer utilization (%) | 725system.toL2Bus.respLayer2.utilization 1.7 # Layer utilization (%) 726system.toL2Bus.respLayer3.occupancy 1148249 # Layer occupancy (ticks) 727system.toL2Bus.respLayer3.utilization 1.0 # Layer utilization (%) 728system.toL2Bus.respLayer4.occupancy 1927493 # Layer occupancy (ticks) 729system.toL2Bus.respLayer4.utilization 1.7 # Layer utilization (%) |
| 728system.toL2Bus.respLayer5.occupancy 1209236 # Layer occupancy (ticks) | 730system.toL2Bus.respLayer5.occupancy 1209237 # Layer occupancy (ticks) |
| 729system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) 730system.toL2Bus.respLayer6.occupancy 1936745 # Layer occupancy (ticks) 731system.toL2Bus.respLayer6.utilization 1.7 # Layer utilization (%) | 731system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) 732system.toL2Bus.respLayer6.occupancy 1936745 # Layer occupancy (ticks) 733system.toL2Bus.respLayer6.utilization 1.7 # Layer utilization (%) |
| 732system.toL2Bus.respLayer7.occupancy 1133252 # Layer occupancy (ticks) | 734system.toL2Bus.respLayer7.occupancy 1133003 # Layer occupancy (ticks) |
| 733system.toL2Bus.respLayer7.utilization 1.0 # Layer utilization (%) | 735system.toL2Bus.respLayer7.utilization 1.0 # Layer utilization (%) |
| 734system.cpu0.branchPred.lookups 83023 # Number of BP lookups 735system.cpu0.branchPred.condPredicted 80825 # Number of conditional branches predicted | 736system.cpu0.branchPred.lookups 82981 # Number of BP lookups 737system.cpu0.branchPred.condPredicted 80783 # Number of conditional branches predicted |
| 736system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect | 738system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect |
| 737system.cpu0.branchPred.BTBLookups 80352 # Number of BTB lookups 738system.cpu0.branchPred.BTBHits 78307 # Number of BTB hits | 739system.cpu0.branchPred.BTBLookups 80310 # Number of BTB lookups 740system.cpu0.branchPred.BTBHits 78265 # Number of BTB hits |
| 739system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 741system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 740system.cpu0.branchPred.BTBHitPct 97.454948 # BTB Hit Percentage | 742system.cpu0.branchPred.BTBHitPct 97.453617 # BTB Hit Percentage |
| 741system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target. 742system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. 743system.cpu0.workload.num_syscalls 89 # Number of system calls | 743system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target. 744system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. 745system.cpu0.workload.num_syscalls 89 # Number of system calls |
| 744system.cpu0.numCycles 221912 # number of cpu cycles simulated | 746system.cpu0.numCycles 221746 # number of cpu cycles simulated |
| 745system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 746system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 747system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 748system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 747system.cpu0.fetch.icacheStallCycles 17233 # Number of cycles fetch is stalled on an Icache miss 748system.cpu0.fetch.Insts 492726 # Number of instructions fetch has processed 749system.cpu0.fetch.Branches 83023 # Number of branches that fetch encountered 750system.cpu0.fetch.predictedBranches 78819 # Number of branches that fetch has predicted taken 751system.cpu0.fetch.Cycles 161746 # Number of cycles fetch has run and was not squashing or blocked | 749system.cpu0.fetch.icacheStallCycles 17234 # Number of cycles fetch is stalled on an Icache miss 750system.cpu0.fetch.Insts 492474 # Number of instructions fetch has processed 751system.cpu0.fetch.Branches 82981 # Number of branches that fetch encountered 752system.cpu0.fetch.predictedBranches 78777 # Number of branches that fetch has predicted taken 753system.cpu0.fetch.Cycles 161662 # Number of cycles fetch has run and was not squashing or blocked |
| 752system.cpu0.fetch.SquashCycles 3811 # Number of cycles fetch has spent squashing | 754system.cpu0.fetch.SquashCycles 3811 # Number of cycles fetch has spent squashing |
| 753system.cpu0.fetch.BlockedCycles 13929 # Number of cycles fetch has spent blocked | 755system.cpu0.fetch.BlockedCycles 13862 # Number of cycles fetch has spent blocked |
| 754system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 755system.cpu0.fetch.PendingTrapStallCycles 1512 # Number of stall cycles due to pending traps 756system.cpu0.fetch.CacheLines 5835 # Number of cache lines fetched | 756system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 757system.cpu0.fetch.PendingTrapStallCycles 1512 # Number of stall cycles due to pending traps 758system.cpu0.fetch.CacheLines 5835 # Number of cache lines fetched |
| 757system.cpu0.fetch.IcacheSquashes 493 # Number of outstanding Icache misses that were squashed 758system.cpu0.fetch.rateDist::samples 196870 # Number of instructions fetched each cycle (Total) 759system.cpu0.fetch.rateDist::mean 2.502799 # Number of instructions fetched each cycle (Total) 760system.cpu0.fetch.rateDist::stdev 2.215097 # Number of instructions fetched each cycle (Total) | 759system.cpu0.fetch.IcacheSquashes 492 # Number of outstanding Icache misses that were squashed 760system.cpu0.fetch.rateDist::samples 196720 # Number of instructions fetched each cycle (Total) 761system.cpu0.fetch.rateDist::mean 2.503426 # Number of instructions fetched each cycle (Total) 762system.cpu0.fetch.rateDist::stdev 2.215057 # Number of instructions fetched each cycle (Total) |
| 761system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 763system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 762system.cpu0.fetch.rateDist::0 35124 17.84% 17.84% # Number of instructions fetched each cycle (Total) 763system.cpu0.fetch.rateDist::1 80120 40.70% 58.54% # Number of instructions fetched each cycle (Total) 764system.cpu0.fetch.rateDist::2 578 0.29% 58.83% # Number of instructions fetched each cycle (Total) 765system.cpu0.fetch.rateDist::3 973 0.49% 59.33% # Number of instructions fetched each cycle (Total) 766system.cpu0.fetch.rateDist::4 477 0.24% 59.57% # Number of instructions fetched each cycle (Total) 767system.cpu0.fetch.rateDist::5 76224 38.72% 98.29% # Number of instructions fetched each cycle (Total) 768system.cpu0.fetch.rateDist::6 570 0.29% 98.58% # Number of instructions fetched each cycle (Total) | 764system.cpu0.fetch.rateDist::0 35058 17.82% 17.82% # Number of instructions fetched each cycle (Total) 765system.cpu0.fetch.rateDist::1 80078 40.71% 58.53% # Number of instructions fetched each cycle (Total) 766system.cpu0.fetch.rateDist::2 578 0.29% 58.82% # Number of instructions fetched each cycle (Total) 767system.cpu0.fetch.rateDist::3 973 0.49% 59.32% # Number of instructions fetched each cycle (Total) 768system.cpu0.fetch.rateDist::4 477 0.24% 59.56% # Number of instructions fetched each cycle (Total) 769system.cpu0.fetch.rateDist::5 76182 38.73% 98.28% # Number of instructions fetched each cycle (Total) 770system.cpu0.fetch.rateDist::6 570 0.29% 98.57% # Number of instructions fetched each cycle (Total) |
| 769system.cpu0.fetch.rateDist::7 349 0.18% 98.75% # Number of instructions fetched each cycle (Total) 770system.cpu0.fetch.rateDist::8 2455 1.25% 100.00% # Number of instructions fetched each cycle (Total) 771system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 772system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 773system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 771system.cpu0.fetch.rateDist::7 349 0.18% 98.75% # Number of instructions fetched each cycle (Total) 772system.cpu0.fetch.rateDist::8 2455 1.25% 100.00% # Number of instructions fetched each cycle (Total) 773system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 774system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 775system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 774system.cpu0.fetch.rateDist::total 196870 # Number of instructions fetched each cycle (Total) 775system.cpu0.fetch.branchRate 0.374126 # Number of branch fetches per cycle 776system.cpu0.fetch.rate 2.220367 # Number of inst fetches per cycle 777system.cpu0.decode.IdleCycles 17821 # Number of cycles decode is idle 778system.cpu0.decode.BlockedCycles 15547 # Number of cycles decode is blocked 779system.cpu0.decode.RunCycles 160777 # Number of cycles decode is running | 776system.cpu0.fetch.rateDist::total 196720 # Number of instructions fetched each cycle (Total) 777system.cpu0.fetch.branchRate 0.374216 # Number of branch fetches per cycle 778system.cpu0.fetch.rate 2.220892 # Number of inst fetches per cycle 779system.cpu0.decode.IdleCycles 17819 # Number of cycles decode is idle 780system.cpu0.decode.BlockedCycles 15483 # Number of cycles decode is blocked 781system.cpu0.decode.RunCycles 160693 # Number of cycles decode is running |
| 780system.cpu0.decode.UnblockCycles 280 # Number of cycles decode is unblocking 781system.cpu0.decode.SquashCycles 2445 # Number of cycles decode is squashing | 782system.cpu0.decode.UnblockCycles 280 # Number of cycles decode is unblocking 783system.cpu0.decode.SquashCycles 2445 # Number of cycles decode is squashing |
| 782system.cpu0.decode.DecodedInsts 489900 # Number of instructions handled by decode | 784system.cpu0.decode.DecodedInsts 489648 # Number of instructions handled by decode |
| 783system.cpu0.rename.SquashCycles 2445 # Number of cycles rename is squashing | 785system.cpu0.rename.SquashCycles 2445 # Number of cycles rename is squashing |
| 784system.cpu0.rename.IdleCycles 18476 # Number of cycles rename is idle 785system.cpu0.rename.BlockCycles 865 # Number of cycles rename is blocking 786system.cpu0.rename.serializeStallCycles 14063 # count of cycles rename stalled for serializing inst 787system.cpu0.rename.RunCycles 160426 # Number of cycles rename is running 788system.cpu0.rename.UnblockCycles 595 # Number of cycles rename is unblocking 789system.cpu0.rename.RenamedInsts 487057 # Number of instructions processed by rename | 786system.cpu0.rename.IdleCycles 18474 # Number of cycles rename is idle 787system.cpu0.rename.BlockCycles 866 # Number of cycles rename is blocking 788system.cpu0.rename.serializeStallCycles 14003 # count of cycles rename stalled for serializing inst 789system.cpu0.rename.RunCycles 160341 # Number of cycles rename is running 790system.cpu0.rename.UnblockCycles 591 # Number of cycles rename is unblocking 791system.cpu0.rename.RenamedInsts 486805 # Number of instructions processed by rename |
| 790system.cpu0.rename.LSQFullEvents 216 # Number of times rename has blocked due to LSQ full | 792system.cpu0.rename.LSQFullEvents 216 # Number of times rename has blocked due to LSQ full |
| 791system.cpu0.rename.RenamedOperands 333048 # Number of destination operands rename has renamed 792system.cpu0.rename.RenameLookups 971305 # Number of register rename lookups that rename has made 793system.cpu0.rename.int_rename_lookups 733660 # Number of integer rename lookups 794system.cpu0.rename.CommittedMaps 320079 # Number of HB maps that are committed | 793system.cpu0.rename.RenamedOperands 332880 # Number of destination operands rename has renamed 794system.cpu0.rename.RenameLookups 970801 # Number of register rename lookups that rename has made 795system.cpu0.rename.int_rename_lookups 733282 # Number of integer rename lookups 796system.cpu0.rename.CommittedMaps 319911 # Number of HB maps that are committed |
| 795system.cpu0.rename.UndoneMaps 12969 # Number of HB maps that are undone due to squashing 796system.cpu0.rename.serializingInsts 866 # count of serializing insts renamed 797system.cpu0.rename.tempSerializingInsts 886 # count of temporary serializing insts renamed | 797system.cpu0.rename.UndoneMaps 12969 # Number of HB maps that are undone due to squashing 798system.cpu0.rename.serializingInsts 866 # count of serializing insts renamed 799system.cpu0.rename.tempSerializingInsts 886 # count of temporary serializing insts renamed |
| 798system.cpu0.rename.skidInsts 3628 # count of insts added to the skid buffer 799system.cpu0.memDep0.insertedLoads 155827 # Number of loads inserted to the mem dependence unit. 800system.cpu0.memDep0.insertedStores 78749 # Number of stores inserted to the mem dependence unit. 801system.cpu0.memDep0.conflictingLoads 76001 # Number of conflicting loads. 802system.cpu0.memDep0.conflictingStores 75817 # Number of conflicting stores. 803system.cpu0.iq.iqInstsAdded 407304 # Number of instructions added to the IQ (excludes non-spec) | 800system.cpu0.rename.skidInsts 3624 # count of insts added to the skid buffer 801system.cpu0.memDep0.insertedLoads 155743 # Number of loads inserted to the mem dependence unit. 802system.cpu0.memDep0.insertedStores 78707 # Number of stores inserted to the mem dependence unit. 803system.cpu0.memDep0.conflictingLoads 75959 # Number of conflicting loads. 804system.cpu0.memDep0.conflictingStores 75775 # Number of conflicting stores. 805system.cpu0.iq.iqInstsAdded 407094 # Number of instructions added to the IQ (excludes non-spec) |
| 804system.cpu0.iq.iqNonSpecInstsAdded 910 # Number of non-speculative instructions added to the IQ | 806system.cpu0.iq.iqNonSpecInstsAdded 910 # Number of non-speculative instructions added to the IQ |
| 805system.cpu0.iq.iqInstsIssued 404579 # Number of instructions issued 806system.cpu0.iq.iqSquashedInstsIssued 133 # Number of squashed instructions issued | 807system.cpu0.iq.iqInstsIssued 404367 # Number of instructions issued 808system.cpu0.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued |
| 807system.cpu0.iq.iqSquashedInstsExamined 10771 # Number of squashed instructions iterated over during squash; mainly for profiling | 809system.cpu0.iq.iqSquashedInstsExamined 10771 # Number of squashed instructions iterated over during squash; mainly for profiling |
| 808system.cpu0.iq.iqSquashedOperandsExamined 9747 # Number of squashed operands that are examined and possibly removed from graph | 810system.cpu0.iq.iqSquashedOperandsExamined 9755 # Number of squashed operands that are examined and possibly removed from graph |
| 809system.cpu0.iq.iqSquashedNonSpecRemoved 351 # Number of squashed non-spec instructions that were removed | 811system.cpu0.iq.iqSquashedNonSpecRemoved 351 # Number of squashed non-spec instructions that were removed |
| 810system.cpu0.iq.issued_per_cycle::samples 196870 # Number of insts issued each cycle 811system.cpu0.iq.issued_per_cycle::mean 2.055057 # Number of insts issued each cycle 812system.cpu0.iq.issued_per_cycle::stdev 1.097769 # Number of insts issued each cycle | 812system.cpu0.iq.issued_per_cycle::samples 196720 # Number of insts issued each cycle 813system.cpu0.iq.issued_per_cycle::mean 2.055546 # Number of insts issued each cycle 814system.cpu0.iq.issued_per_cycle::stdev 1.097437 # Number of insts issued each cycle |
| 813system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 815system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 814system.cpu0.iq.issued_per_cycle::0 34107 17.32% 17.32% # Number of insts issued each cycle 815system.cpu0.iq.issued_per_cycle::1 4943 2.51% 19.84% # Number of insts issued each cycle 816system.cpu0.iq.issued_per_cycle::2 77928 39.58% 59.42% # Number of insts issued each cycle 817system.cpu0.iq.issued_per_cycle::3 77295 39.26% 98.68% # Number of insts issued each cycle 818system.cpu0.iq.issued_per_cycle::4 1579 0.80% 99.48% # Number of insts issued each cycle 819system.cpu0.iq.issued_per_cycle::5 650 0.33% 99.81% # Number of insts issued each cycle | 816system.cpu0.iq.issued_per_cycle::0 34036 17.30% 17.30% # Number of insts issued each cycle 817system.cpu0.iq.issued_per_cycle::1 4955 2.52% 19.82% # Number of insts issued each cycle 818system.cpu0.iq.issued_per_cycle::2 77877 39.59% 59.41% # Number of insts issued each cycle 819system.cpu0.iq.issued_per_cycle::3 77259 39.27% 98.68% # Number of insts issued each cycle 820system.cpu0.iq.issued_per_cycle::4 1573 0.80% 99.48% # Number of insts issued each cycle 821system.cpu0.iq.issued_per_cycle::5 652 0.33% 99.81% # Number of insts issued each cycle |
| 820system.cpu0.iq.issued_per_cycle::6 264 0.13% 99.95% # Number of insts issued each cycle 821system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle 822system.cpu0.iq.issued_per_cycle::8 17 0.01% 100.00% # Number of insts issued each cycle 823system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 824system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 825system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 822system.cpu0.iq.issued_per_cycle::6 264 0.13% 99.95% # Number of insts issued each cycle 823system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle 824system.cpu0.iq.issued_per_cycle::8 17 0.01% 100.00% # Number of insts issued each cycle 825system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 826system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 827system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 826system.cpu0.iq.issued_per_cycle::total 196870 # Number of insts issued each cycle | 828system.cpu0.iq.issued_per_cycle::total 196720 # Number of insts issued each cycle |
| 827system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 829system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 828system.cpu0.iq.fu_full::IntAlu 57 25.68% 25.68% # attempts to use FU when none available 829system.cpu0.iq.fu_full::IntMult 0 0.00% 25.68% # attempts to use FU when none available 830system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.68% # attempts to use FU when none available 831system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.68% # attempts to use FU when none available 832system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.68% # attempts to use FU when none available 833system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.68% # attempts to use FU when none available 834system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.68% # attempts to use FU when none available 835system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.68% # attempts to use FU when none available 836system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.68% # attempts to use FU when none available 837system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.68% # attempts to use FU when none available 838system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.68% # attempts to use FU when none available 839system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.68% # attempts to use FU when none available 840system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.68% # attempts to use FU when none available 841system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.68% # attempts to use FU when none available 842system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.68% # attempts to use FU when none available 843system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.68% # attempts to use FU when none available 844system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.68% # attempts to use FU when none available 845system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.68% # attempts to use FU when none available 846system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.68% # attempts to use FU when none available 847system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.68% # attempts to use FU when none available 848system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.68% # attempts to use FU when none available 849system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.68% # attempts to use FU when none available 850system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.68% # attempts to use FU when none available 851system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.68% # attempts to use FU when none available 852system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.68% # attempts to use FU when none available 853system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.68% # attempts to use FU when none available 854system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.68% # attempts to use FU when none available 855system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.68% # attempts to use FU when none available 856system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.68% # attempts to use FU when none available 857system.cpu0.iq.fu_full::MemRead 53 23.87% 49.55% # attempts to use FU when none available 858system.cpu0.iq.fu_full::MemWrite 112 50.45% 100.00% # attempts to use FU when none available | 830system.cpu0.iq.fu_full::IntAlu 57 25.79% 25.79% # attempts to use FU when none available 831system.cpu0.iq.fu_full::IntMult 0 0.00% 25.79% # attempts to use FU when none available 832system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.79% # attempts to use FU when none available 833system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.79% # attempts to use FU when none available 834system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.79% # attempts to use FU when none available 835system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.79% # attempts to use FU when none available 836system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.79% # attempts to use FU when none available 837system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.79% # attempts to use FU when none available 838system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.79% # attempts to use FU when none available 839system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.79% # attempts to use FU when none available 840system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.79% # attempts to use FU when none available 841system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.79% # attempts to use FU when none available 842system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.79% # attempts to use FU when none available 843system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.79% # attempts to use FU when none available 844system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.79% # attempts to use FU when none available 845system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.79% # attempts to use FU when none available 846system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.79% # attempts to use FU when none available 847system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.79% # attempts to use FU when none available 848system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.79% # attempts to use FU when none available 849system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.79% # attempts to use FU when none available 850system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.79% # attempts to use FU when none available 851system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.79% # attempts to use FU when none available 852system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.79% # attempts to use FU when none available 853system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.79% # attempts to use FU when none available 854system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.79% # attempts to use FU when none available 855system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.79% # attempts to use FU when none available 856system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.79% # attempts to use FU when none available 857system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.79% # attempts to use FU when none available 858system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.79% # attempts to use FU when none available 859system.cpu0.iq.fu_full::MemRead 52 23.53% 49.32% # attempts to use FU when none available 860system.cpu0.iq.fu_full::MemWrite 112 50.68% 100.00% # attempts to use FU when none available |
| 859system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 860system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 861system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 861system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 862system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 863system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 862system.cpu0.iq.FU_type_0::IntAlu 171055 42.28% 42.28% # Type of FU issued | 864system.cpu0.iq.FU_type_0::IntAlu 170970 42.28% 42.28% # Type of FU issued |
| 863system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.28% # Type of FU issued 864system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.28% # Type of FU issued 865system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.28% # Type of FU issued 866system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.28% # Type of FU issued 867system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.28% # Type of FU issued 868system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.28% # Type of FU issued 869system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.28% # Type of FU issued 870system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.28% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 883system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.28% # Type of FU issued 884system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.28% # Type of FU issued 885system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.28% # Type of FU issued 886system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.28% # Type of FU issued 887system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.28% # Type of FU issued 888system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.28% # Type of FU issued 889system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.28% # Type of FU issued 890system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.28% # Type of FU issued | 865system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.28% # Type of FU issued 866system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.28% # Type of FU issued 867system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.28% # Type of FU issued 868system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.28% # Type of FU issued 869system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.28% # Type of FU issued 870system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.28% # Type of FU issued 871system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.28% # Type of FU issued 872system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.28% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 885system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.28% # Type of FU issued 886system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.28% # Type of FU issued 887system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.28% # Type of FU issued 888system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.28% # Type of FU issued 889system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.28% # Type of FU issued 890system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.28% # Type of FU issued 891system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.28% # Type of FU issued 892system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.28% # Type of FU issued |
| 891system.cpu0.iq.FU_type_0::MemRead 155363 38.40% 80.68% # Type of FU issued 892system.cpu0.iq.FU_type_0::MemWrite 78161 19.32% 100.00% # Type of FU issued | 893system.cpu0.iq.FU_type_0::MemRead 155279 38.40% 80.68% # Type of FU issued 894system.cpu0.iq.FU_type_0::MemWrite 78118 19.32% 100.00% # Type of FU issued |
| 893system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 894system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 895system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 896system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 895system.cpu0.iq.FU_type_0::total 404579 # Type of FU issued 896system.cpu0.iq.rate 1.823151 # Inst issue rate 897system.cpu0.iq.fu_busy_cnt 222 # FU busy when requested 898system.cpu0.iq.fu_busy_rate 0.000549 # FU busy rate (busy events/executed inst) 899system.cpu0.iq.int_inst_queue_reads 1006383 # Number of integer instruction queue reads 900system.cpu0.iq.int_inst_queue_writes 419039 # Number of integer instruction queue writes 901system.cpu0.iq.int_inst_queue_wakeup_accesses 402754 # Number of integer instruction queue wakeup accesses | 897system.cpu0.iq.FU_type_0::total 404367 # Type of FU issued 898system.cpu0.iq.rate 1.823559 # Inst issue rate 899system.cpu0.iq.fu_busy_cnt 221 # FU busy when requested 900system.cpu0.iq.fu_busy_rate 0.000547 # FU busy rate (busy events/executed inst) 901system.cpu0.iq.int_inst_queue_reads 1005807 # Number of integer instruction queue reads 902system.cpu0.iq.int_inst_queue_writes 418829 # Number of integer instruction queue writes 903system.cpu0.iq.int_inst_queue_wakeup_accesses 402541 # Number of integer instruction queue wakeup accesses |
| 902system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 903system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 904system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 904system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 905system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 906system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 905system.cpu0.iq.int_alu_accesses 404801 # Number of integer alu accesses | 907system.cpu0.iq.int_alu_accesses 404588 # Number of integer alu accesses |
| 906system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses | 908system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses |
| 907system.cpu0.iew.lsq.thread0.forwLoads 75529 # Number of loads that had data forwarded from stores | 909system.cpu0.iew.lsq.thread0.forwLoads 75486 # Number of loads that had data forwarded from stores |
| 908system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 909system.cpu0.iew.lsq.thread0.squashedLoads 2198 # Number of loads squashed 910system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed 911system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations 912system.cpu0.iew.lsq.thread0.squashedStores 1428 # Number of stores squashed 913system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 914system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 915system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled | 910system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 911system.cpu0.iew.lsq.thread0.squashedLoads 2198 # Number of loads squashed 912system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed 913system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations 914system.cpu0.iew.lsq.thread0.squashedStores 1428 # Number of stores squashed 915system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 916system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 917system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled |
| 916system.cpu0.iew.lsq.thread0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked | 918system.cpu0.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked |
| 917system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 918system.cpu0.iew.iewSquashCycles 2445 # Number of cycles IEW is squashing | 919system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 920system.cpu0.iew.iewSquashCycles 2445 # Number of cycles IEW is squashing |
| 919system.cpu0.iew.iewBlockCycles 405 # Number of cycles IEW is blocking 920system.cpu0.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking 921system.cpu0.iew.iewDispatchedInsts 484766 # Number of instructions dispatched to IQ 922system.cpu0.iew.iewDispSquashedInsts 308 # Number of squashed instructions skipped by dispatch 923system.cpu0.iew.iewDispLoadInsts 155827 # Number of dispatched load instructions 924system.cpu0.iew.iewDispStoreInsts 78749 # Number of dispatched store instructions | 921system.cpu0.iew.iewBlockCycles 400 # Number of cycles IEW is blocking 922system.cpu0.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking 923system.cpu0.iew.iewDispatchedInsts 484514 # Number of instructions dispatched to IQ 924system.cpu0.iew.iewDispSquashedInsts 312 # Number of squashed instructions skipped by dispatch 925system.cpu0.iew.iewDispLoadInsts 155743 # Number of dispatched load instructions 926system.cpu0.iew.iewDispStoreInsts 78707 # Number of dispatched store instructions |
| 925system.cpu0.iew.iewDispNonSpecInsts 798 # Number of dispatched non-speculative instructions 926system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall 927system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 928system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations 929system.cpu0.iew.predictedTakenIncorrect 343 # Number of branches that were predicted taken incorrectly 930system.cpu0.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly 931system.cpu0.iew.branchMispredicts 1449 # Number of branch mispredicts detected at execute | 927system.cpu0.iew.iewDispNonSpecInsts 798 # Number of dispatched non-speculative instructions 928system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall 929system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 930system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations 931system.cpu0.iew.predictedTakenIncorrect 343 # Number of branches that were predicted taken incorrectly 932system.cpu0.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly 933system.cpu0.iew.branchMispredicts 1449 # Number of branch mispredicts detected at execute |
| 932system.cpu0.iew.iewExecutedInsts 403510 # Number of executed instructions 933system.cpu0.iew.iewExecLoadInsts 155033 # Number of load instructions executed | 934system.cpu0.iew.iewExecutedInsts 403298 # Number of executed instructions 935system.cpu0.iew.iewExecLoadInsts 154949 # Number of load instructions executed |
| 934system.cpu0.iew.iewExecSquashedInsts 1069 # Number of squashed instructions skipped in execute 935system.cpu0.iew.exec_swp 0 # number of swp insts executed | 936system.cpu0.iew.iewExecSquashedInsts 1069 # Number of squashed instructions skipped in execute 937system.cpu0.iew.exec_swp 0 # number of swp insts executed |
| 936system.cpu0.iew.exec_nop 76552 # number of nop insts executed 937system.cpu0.iew.exec_refs 233092 # number of memory reference insts executed 938system.cpu0.iew.exec_branches 80162 # Number of branches executed 939system.cpu0.iew.exec_stores 78059 # Number of stores executed 940system.cpu0.iew.exec_rate 1.818333 # Inst execution rate 941system.cpu0.iew.wb_sent 403084 # cumulative count of insts sent to commit 942system.cpu0.iew.wb_count 402754 # cumulative count of insts written-back 943system.cpu0.iew.wb_producers 238663 # num instructions producing a value 944system.cpu0.iew.wb_consumers 241120 # num instructions consuming a value | 938system.cpu0.iew.exec_nop 76510 # number of nop insts executed 939system.cpu0.iew.exec_refs 232965 # number of memory reference insts executed 940system.cpu0.iew.exec_branches 80120 # Number of branches executed 941system.cpu0.iew.exec_stores 78016 # Number of stores executed 942system.cpu0.iew.exec_rate 1.818739 # Inst execution rate 943system.cpu0.iew.wb_sent 402871 # cumulative count of insts sent to commit 944system.cpu0.iew.wb_count 402541 # cumulative count of insts written-back 945system.cpu0.iew.wb_producers 238524 # num instructions producing a value 946system.cpu0.iew.wb_consumers 240975 # num instructions consuming a value |
| 945system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 947system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 946system.cpu0.iew.wb_rate 1.814927 # insts written-back per cycle 947system.cpu0.iew.wb_fanout 0.989810 # average fanout of values written-back | 948system.cpu0.iew.wb_rate 1.815325 # insts written-back per cycle 949system.cpu0.iew.wb_fanout 0.989829 # average fanout of values written-back |
| 948system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 949system.cpu0.commit.commitSquashedInsts 12269 # The number of squashed insts skipped by commit 950system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards 951system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted | 950system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 951system.cpu0.commit.commitSquashedInsts 12269 # The number of squashed insts skipped by commit 952system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards 953system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted |
| 952system.cpu0.commit.committed_per_cycle::samples 194425 # Number of insts commited each cycle 953system.cpu0.commit.committed_per_cycle::mean 2.430089 # Number of insts commited each cycle 954system.cpu0.commit.committed_per_cycle::stdev 2.136483 # Number of insts commited each cycle | 954system.cpu0.commit.committed_per_cycle::samples 194275 # Number of insts commited each cycle 955system.cpu0.commit.committed_per_cycle::mean 2.430668 # Number of insts commited each cycle 956system.cpu0.commit.committed_per_cycle::stdev 2.136401 # Number of insts commited each cycle |
| 955system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 957system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 956system.cpu0.commit.committed_per_cycle::0 34537 17.76% 17.76% # Number of insts commited each cycle 957system.cpu0.commit.committed_per_cycle::1 79950 41.12% 58.88% # Number of insts commited each cycle 958system.cpu0.commit.committed_per_cycle::2 2378 1.22% 60.11% # Number of insts commited each cycle 959system.cpu0.commit.committed_per_cycle::3 690 0.35% 60.46% # Number of insts commited each cycle 960system.cpu0.commit.committed_per_cycle::4 530 0.27% 60.74% # Number of insts commited each cycle 961system.cpu0.commit.committed_per_cycle::5 75328 38.74% 99.48% # Number of insts commited each cycle 962system.cpu0.commit.committed_per_cycle::6 457 0.24% 99.71% # Number of insts commited each cycle 963system.cpu0.commit.committed_per_cycle::7 248 0.13% 99.84% # Number of insts commited each cycle 964system.cpu0.commit.committed_per_cycle::8 307 0.16% 100.00% # Number of insts commited each cycle | 958system.cpu0.commit.committed_per_cycle::0 34469 17.74% 17.74% # Number of insts commited each cycle 959system.cpu0.commit.committed_per_cycle::1 79913 41.13% 58.88% # Number of insts commited each cycle 960system.cpu0.commit.committed_per_cycle::2 2377 1.22% 60.10% # Number of insts commited each cycle 961system.cpu0.commit.committed_per_cycle::3 686 0.35% 60.45% # Number of insts commited each cycle 962system.cpu0.commit.committed_per_cycle::4 532 0.27% 60.73% # Number of insts commited each cycle 963system.cpu0.commit.committed_per_cycle::5 75283 38.75% 99.48% # Number of insts commited each cycle 964system.cpu0.commit.committed_per_cycle::6 460 0.24% 99.71% # Number of insts commited each cycle 965system.cpu0.commit.committed_per_cycle::7 250 0.13% 99.84% # Number of insts commited each cycle 966system.cpu0.commit.committed_per_cycle::8 305 0.16% 100.00% # Number of insts commited each cycle |
| 965system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 966system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 967system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 967system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 968system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 969system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 968system.cpu0.commit.committed_per_cycle::total 194425 # Number of insts commited each cycle 969system.cpu0.commit.committedInsts 472470 # Number of instructions committed 970system.cpu0.commit.committedOps 472470 # Number of ops (including micro ops) committed | 970system.cpu0.commit.committed_per_cycle::total 194275 # Number of insts commited each cycle 971system.cpu0.commit.committedInsts 472218 # Number of instructions committed 972system.cpu0.commit.committedOps 472218 # Number of ops (including micro ops) committed |
| 971system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed | 973system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed |
| 972system.cpu0.commit.refs 230950 # Number of memory references committed 973system.cpu0.commit.loads 153629 # Number of loads committed | 974system.cpu0.commit.refs 230824 # Number of memory references committed 975system.cpu0.commit.loads 153545 # Number of loads committed |
| 974system.cpu0.commit.membars 84 # Number of memory barriers committed | 976system.cpu0.commit.membars 84 # Number of memory barriers committed |
| 975system.cpu0.commit.branches 79208 # Number of branches committed | 977system.cpu0.commit.branches 79166 # Number of branches committed |
| 976system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. | 978system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. |
| 977system.cpu0.commit.int_insts 318410 # Number of committed integer instructions. | 979system.cpu0.commit.int_insts 318242 # Number of committed integer instructions. |
| 978system.cpu0.commit.function_calls 223 # Number of function calls committed. | 980system.cpu0.commit.function_calls 223 # Number of function calls committed. |
| 979system.cpu0.commit.bw_lim_events 307 # number cycles where commit BW limit reached | 981system.cpu0.commit.op_class_0::No_OpClass 75898 16.07% 16.07% # Class of committed instruction 982system.cpu0.commit.op_class_0::IntAlu 165412 35.03% 51.10% # Class of committed instruction 983system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.10% # Class of committed instruction 984system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.10% # Class of committed instruction 985system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.10% # Class of committed instruction 986system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.10% # Class of committed instruction 987system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.10% # Class of committed instruction 988system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.10% # Class of committed instruction 989system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.10% # Class of committed instruction 990system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.10% # Class of committed instruction 991system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.10% # Class of committed instruction 992system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.10% # Class of committed instruction 993system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.10% # Class of committed instruction 994system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.10% # Class of committed instruction 995system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.10% # Class of committed instruction 996system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.10% # Class of committed instruction 997system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.10% # Class of committed instruction 998system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.10% # Class of committed instruction 999system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.10% # Class of committed instruction 1000system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.10% # Class of committed instruction 1001system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.10% # Class of committed instruction 1002system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.10% # Class of committed instruction 1003system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.10% # Class of committed instruction 1004system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.10% # Class of committed instruction 1005system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.10% # Class of committed instruction 1006system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.10% # Class of committed instruction 1007system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.10% # Class of committed instruction 1008system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.10% # Class of committed instruction 1009system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.10% # Class of committed instruction 1010system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.10% # Class of committed instruction 1011system.cpu0.commit.op_class_0::MemRead 153629 32.53% 83.63% # Class of committed instruction 1012system.cpu0.commit.op_class_0::MemWrite 77279 16.37% 100.00% # Class of committed instruction 1013system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1014system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1015system.cpu0.commit.op_class_0::total 472218 # Class of committed instruction 1016system.cpu0.commit.bw_lim_events 305 # number cycles where commit BW limit reached |
| 980system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits | 1017system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 981system.cpu0.rob.rob_reads 677696 # The number of ROB reads 982system.cpu0.rob.rob_writes 971940 # The number of ROB writes | 1018system.cpu0.rob.rob_reads 677296 # The number of ROB reads 1019system.cpu0.rob.rob_writes 971436 # The number of ROB writes |
| 983system.cpu0.timesIdled 327 # Number of times that the entire CPU went into an idle state and unscheduled itself | 1020system.cpu0.timesIdled 327 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 984system.cpu0.idleCycles 25042 # Total number of cycles that the CPU has spent unscheduled due to idling 985system.cpu0.committedInsts 396446 # Number of Instructions Simulated 986system.cpu0.committedOps 396446 # Number of Ops (including micro ops) Simulated 987system.cpu0.committedInsts_total 396446 # Number of Instructions Simulated 988system.cpu0.cpi 0.559753 # CPI: Cycles Per Instruction 989system.cpu0.cpi_total 0.559753 # CPI: Total CPI of All Threads 990system.cpu0.ipc 1.786501 # IPC: Instructions Per Cycle 991system.cpu0.ipc_total 1.786501 # IPC: Total IPC of All Threads 992system.cpu0.int_regfile_reads 721878 # number of integer regfile reads 993system.cpu0.int_regfile_writes 325337 # number of integer regfile writes | 1021system.cpu0.idleCycles 25026 # Total number of cycles that the CPU has spent unscheduled due to idling 1022system.cpu0.committedInsts 396236 # Number of Instructions Simulated 1023system.cpu0.committedOps 396236 # Number of Ops (including micro ops) Simulated 1024system.cpu0.committedInsts_total 396236 # Number of Instructions Simulated 1025system.cpu0.cpi 0.559631 # CPI: Cycles Per Instruction 1026system.cpu0.cpi_total 0.559631 # CPI: Total CPI of All Threads 1027system.cpu0.ipc 1.786891 # IPC: Instructions Per Cycle 1028system.cpu0.ipc_total 1.786891 # IPC: Total IPC of All Threads 1029system.cpu0.int_regfile_reads 721496 # number of integer regfile reads 1030system.cpu0.int_regfile_writes 325166 # number of integer regfile writes |
| 994system.cpu0.fp_regfile_reads 192 # number of floating regfile reads | 1031system.cpu0.fp_regfile_reads 192 # number of floating regfile reads |
| 995system.cpu0.misc_regfile_reads 234915 # number of misc regfile reads | 1032system.cpu0.misc_regfile_reads 234788 # number of misc regfile reads |
| 996system.cpu0.misc_regfile_writes 564 # number of misc regfile writes 997system.cpu0.icache.tags.replacements 297 # number of replacements | 1033system.cpu0.misc_regfile_writes 564 # number of misc regfile writes 1034system.cpu0.icache.tags.replacements 297 # number of replacements |
| 998system.cpu0.icache.tags.tagsinuse 241.280038 # Cycle average of tags in use | 1035system.cpu0.icache.tags.tagsinuse 241.323737 # Cycle average of tags in use |
| 999system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks. 1000system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks. 1001system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks. 1002system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1036system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks. 1037system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks. 1038system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks. 1039system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1003system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.280038 # Average occupied blocks per requestor 1004system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471250 # Average percentage of cache occupancy 1005system.cpu0.icache.tags.occ_percent::total 0.471250 # Average percentage of cache occupancy | 1040system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.323737 # Average occupied blocks per requestor 1041system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471335 # Average percentage of cache occupancy 1042system.cpu0.icache.tags.occ_percent::total 0.471335 # Average percentage of cache occupancy |
| 1006system.cpu0.icache.tags.occ_task_id_blocks::1024 290 # Occupied blocks per task id 1007system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id 1008system.cpu0.icache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id 1009system.cpu0.icache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id 1010system.cpu0.icache.tags.occ_task_id_percent::1024 0.566406 # Percentage of cache occupancy per task id 1011system.cpu0.icache.tags.tag_accesses 6422 # Number of tag accesses 1012system.cpu0.icache.tags.data_accesses 6422 # Number of data accesses 1013system.cpu0.icache.ReadReq_hits::cpu0.inst 5079 # number of ReadReq hits 1014system.cpu0.icache.ReadReq_hits::total 5079 # number of ReadReq hits 1015system.cpu0.icache.demand_hits::cpu0.inst 5079 # number of demand (read+write) hits 1016system.cpu0.icache.demand_hits::total 5079 # number of demand (read+write) hits 1017system.cpu0.icache.overall_hits::cpu0.inst 5079 # number of overall hits 1018system.cpu0.icache.overall_hits::total 5079 # number of overall hits 1019system.cpu0.icache.ReadReq_misses::cpu0.inst 756 # number of ReadReq misses 1020system.cpu0.icache.ReadReq_misses::total 756 # number of ReadReq misses 1021system.cpu0.icache.demand_misses::cpu0.inst 756 # number of demand (read+write) misses 1022system.cpu0.icache.demand_misses::total 756 # number of demand (read+write) misses 1023system.cpu0.icache.overall_misses::cpu0.inst 756 # number of overall misses 1024system.cpu0.icache.overall_misses::total 756 # number of overall misses | 1043system.cpu0.icache.tags.occ_task_id_blocks::1024 290 # Occupied blocks per task id 1044system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id 1045system.cpu0.icache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id 1046system.cpu0.icache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id 1047system.cpu0.icache.tags.occ_task_id_percent::1024 0.566406 # Percentage of cache occupancy per task id 1048system.cpu0.icache.tags.tag_accesses 6422 # Number of tag accesses 1049system.cpu0.icache.tags.data_accesses 6422 # Number of data accesses 1050system.cpu0.icache.ReadReq_hits::cpu0.inst 5079 # number of ReadReq hits 1051system.cpu0.icache.ReadReq_hits::total 5079 # number of ReadReq hits 1052system.cpu0.icache.demand_hits::cpu0.inst 5079 # number of demand (read+write) hits 1053system.cpu0.icache.demand_hits::total 5079 # number of demand (read+write) hits 1054system.cpu0.icache.overall_hits::cpu0.inst 5079 # number of overall hits 1055system.cpu0.icache.overall_hits::total 5079 # number of overall hits 1056system.cpu0.icache.ReadReq_misses::cpu0.inst 756 # number of ReadReq misses 1057system.cpu0.icache.ReadReq_misses::total 756 # number of ReadReq misses 1058system.cpu0.icache.demand_misses::cpu0.inst 756 # number of demand (read+write) misses 1059system.cpu0.icache.demand_misses::total 756 # number of demand (read+write) misses 1060system.cpu0.icache.overall_misses::cpu0.inst 756 # number of overall misses 1061system.cpu0.icache.overall_misses::total 756 # number of overall misses |
| 1025system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35676245 # number of ReadReq miss cycles 1026system.cpu0.icache.ReadReq_miss_latency::total 35676245 # number of ReadReq miss cycles 1027system.cpu0.icache.demand_miss_latency::cpu0.inst 35676245 # number of demand (read+write) miss cycles 1028system.cpu0.icache.demand_miss_latency::total 35676245 # number of demand (read+write) miss cycles 1029system.cpu0.icache.overall_miss_latency::cpu0.inst 35676245 # number of overall miss cycles 1030system.cpu0.icache.overall_miss_latency::total 35676245 # number of overall miss cycles | 1062system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35655495 # number of ReadReq miss cycles 1063system.cpu0.icache.ReadReq_miss_latency::total 35655495 # number of ReadReq miss cycles 1064system.cpu0.icache.demand_miss_latency::cpu0.inst 35655495 # number of demand (read+write) miss cycles 1065system.cpu0.icache.demand_miss_latency::total 35655495 # number of demand (read+write) miss cycles 1066system.cpu0.icache.overall_miss_latency::cpu0.inst 35655495 # number of overall miss cycles 1067system.cpu0.icache.overall_miss_latency::total 35655495 # number of overall miss cycles |
| 1031system.cpu0.icache.ReadReq_accesses::cpu0.inst 5835 # number of ReadReq accesses(hits+misses) 1032system.cpu0.icache.ReadReq_accesses::total 5835 # number of ReadReq accesses(hits+misses) 1033system.cpu0.icache.demand_accesses::cpu0.inst 5835 # number of demand (read+write) accesses 1034system.cpu0.icache.demand_accesses::total 5835 # number of demand (read+write) accesses 1035system.cpu0.icache.overall_accesses::cpu0.inst 5835 # number of overall (read+write) accesses 1036system.cpu0.icache.overall_accesses::total 5835 # number of overall (read+write) accesses 1037system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.129563 # miss rate for ReadReq accesses 1038system.cpu0.icache.ReadReq_miss_rate::total 0.129563 # miss rate for ReadReq accesses 1039system.cpu0.icache.demand_miss_rate::cpu0.inst 0.129563 # miss rate for demand accesses 1040system.cpu0.icache.demand_miss_rate::total 0.129563 # miss rate for demand accesses 1041system.cpu0.icache.overall_miss_rate::cpu0.inst 0.129563 # miss rate for overall accesses 1042system.cpu0.icache.overall_miss_rate::total 0.129563 # miss rate for overall accesses | 1068system.cpu0.icache.ReadReq_accesses::cpu0.inst 5835 # number of ReadReq accesses(hits+misses) 1069system.cpu0.icache.ReadReq_accesses::total 5835 # number of ReadReq accesses(hits+misses) 1070system.cpu0.icache.demand_accesses::cpu0.inst 5835 # number of demand (read+write) accesses 1071system.cpu0.icache.demand_accesses::total 5835 # number of demand (read+write) accesses 1072system.cpu0.icache.overall_accesses::cpu0.inst 5835 # number of overall (read+write) accesses 1073system.cpu0.icache.overall_accesses::total 5835 # number of overall (read+write) accesses 1074system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.129563 # miss rate for ReadReq accesses 1075system.cpu0.icache.ReadReq_miss_rate::total 0.129563 # miss rate for ReadReq accesses 1076system.cpu0.icache.demand_miss_rate::cpu0.inst 0.129563 # miss rate for demand accesses 1077system.cpu0.icache.demand_miss_rate::total 0.129563 # miss rate for demand accesses 1078system.cpu0.icache.overall_miss_rate::cpu0.inst 0.129563 # miss rate for overall accesses 1079system.cpu0.icache.overall_miss_rate::total 0.129563 # miss rate for overall accesses |
| 1043system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47190.800265 # average ReadReq miss latency 1044system.cpu0.icache.ReadReq_avg_miss_latency::total 47190.800265 # average ReadReq miss latency 1045system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47190.800265 # average overall miss latency 1046system.cpu0.icache.demand_avg_miss_latency::total 47190.800265 # average overall miss latency 1047system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47190.800265 # average overall miss latency 1048system.cpu0.icache.overall_avg_miss_latency::total 47190.800265 # average overall miss latency | 1080system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47163.353175 # average ReadReq miss latency 1081system.cpu0.icache.ReadReq_avg_miss_latency::total 47163.353175 # average ReadReq miss latency 1082system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47163.353175 # average overall miss latency 1083system.cpu0.icache.demand_avg_miss_latency::total 47163.353175 # average overall miss latency 1084system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47163.353175 # average overall miss latency 1085system.cpu0.icache.overall_avg_miss_latency::total 47163.353175 # average overall miss latency |
| 1049system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1050system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1051system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1052system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1053system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1054system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1055system.cpu0.icache.fast_writes 0 # number of fast writes performed 1056system.cpu0.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 1061system.cpu0.icache.overall_mshr_hits::cpu0.inst 168 # number of overall MSHR hits 1062system.cpu0.icache.overall_mshr_hits::total 168 # number of overall MSHR hits 1063system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 588 # number of ReadReq MSHR misses 1064system.cpu0.icache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses 1065system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 # number of demand (read+write) MSHR misses 1066system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses 1067system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses 1068system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses | 1086system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1087system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1088system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1089system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1090system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1091system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1092system.cpu0.icache.fast_writes 0 # number of fast writes performed 1093system.cpu0.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 1098system.cpu0.icache.overall_mshr_hits::cpu0.inst 168 # number of overall MSHR hits 1099system.cpu0.icache.overall_mshr_hits::total 168 # number of overall MSHR hits 1100system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 588 # number of ReadReq MSHR misses 1101system.cpu0.icache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses 1102system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 # number of demand (read+write) MSHR misses 1103system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses 1104system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses 1105system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses |
| 1069system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27430752 # number of ReadReq MSHR miss cycles 1070system.cpu0.icache.ReadReq_mshr_miss_latency::total 27430752 # number of ReadReq MSHR miss cycles 1071system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27430752 # number of demand (read+write) MSHR miss cycles 1072system.cpu0.icache.demand_mshr_miss_latency::total 27430752 # number of demand (read+write) MSHR miss cycles 1073system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27430752 # number of overall MSHR miss cycles 1074system.cpu0.icache.overall_mshr_miss_latency::total 27430752 # number of overall MSHR miss cycles | 1106system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27420002 # number of ReadReq MSHR miss cycles 1107system.cpu0.icache.ReadReq_mshr_miss_latency::total 27420002 # number of ReadReq MSHR miss cycles 1108system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27420002 # number of demand (read+write) MSHR miss cycles 1109system.cpu0.icache.demand_mshr_miss_latency::total 27420002 # number of demand (read+write) MSHR miss cycles 1110system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27420002 # number of overall MSHR miss cycles 1111system.cpu0.icache.overall_mshr_miss_latency::total 27420002 # number of overall MSHR miss cycles |
| 1075system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for ReadReq accesses 1076system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100771 # mshr miss rate for ReadReq accesses 1077system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for demand accesses 1078system.cpu0.icache.demand_mshr_miss_rate::total 0.100771 # mshr miss rate for demand accesses 1079system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for overall accesses 1080system.cpu0.icache.overall_mshr_miss_rate::total 0.100771 # mshr miss rate for overall accesses | 1112system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for ReadReq accesses 1113system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100771 # mshr miss rate for ReadReq accesses 1114system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for demand accesses 1115system.cpu0.icache.demand_mshr_miss_rate::total 0.100771 # mshr miss rate for demand accesses 1116system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for overall accesses 1117system.cpu0.icache.overall_mshr_miss_rate::total 0.100771 # mshr miss rate for overall accesses |
| 1081system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46650.938776 # average ReadReq mshr miss latency 1082system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46650.938776 # average ReadReq mshr miss latency 1083system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46650.938776 # average overall mshr miss latency 1084system.cpu0.icache.demand_avg_mshr_miss_latency::total 46650.938776 # average overall mshr miss latency 1085system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46650.938776 # average overall mshr miss latency 1086system.cpu0.icache.overall_avg_mshr_miss_latency::total 46650.938776 # average overall mshr miss latency | 1118system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46632.656463 # average ReadReq mshr miss latency 1119system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46632.656463 # average ReadReq mshr miss latency 1120system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46632.656463 # average overall mshr miss latency 1121system.cpu0.icache.demand_avg_mshr_miss_latency::total 46632.656463 # average overall mshr miss latency 1122system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46632.656463 # average overall mshr miss latency 1123system.cpu0.icache.overall_avg_mshr_miss_latency::total 46632.656463 # average overall mshr miss latency |
| 1087system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1088system.cpu0.dcache.tags.replacements 2 # number of replacements | 1124system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1125system.cpu0.dcache.tags.replacements 2 # number of replacements |
| 1089system.cpu0.dcache.tags.tagsinuse 142.009454 # Cycle average of tags in use 1090system.cpu0.dcache.tags.total_refs 155675 # Total number of references to valid blocks. | 1126system.cpu0.dcache.tags.tagsinuse 142.026535 # Cycle average of tags in use 1127system.cpu0.dcache.tags.total_refs 155594 # Total number of references to valid blocks. |
| 1091system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. | 1128system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. |
| 1092system.cpu0.dcache.tags.avg_refs 915.735294 # Average number of references to valid blocks. | 1129system.cpu0.dcache.tags.avg_refs 915.258824 # Average number of references to valid blocks. |
| 1093system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1130system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1094system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.009454 # Average occupied blocks per requestor 1095system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277362 # Average percentage of cache occupancy 1096system.cpu0.dcache.tags.occ_percent::total 0.277362 # Average percentage of cache occupancy | 1131system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.026535 # Average occupied blocks per requestor 1132system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277396 # Average percentage of cache occupancy 1133system.cpu0.dcache.tags.occ_percent::total 0.277396 # Average percentage of cache occupancy |
| 1097system.cpu0.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id 1098system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id 1099system.cpu0.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id 1100system.cpu0.dcache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id 1101system.cpu0.dcache.tags.occ_task_id_percent::1024 0.328125 # Percentage of cache occupancy per task id | 1134system.cpu0.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id 1135system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id 1136system.cpu0.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id 1137system.cpu0.dcache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id 1138system.cpu0.dcache.tags.occ_task_id_percent::1024 0.328125 # Percentage of cache occupancy per task id |
| 1102system.cpu0.dcache.tags.tag_accesses 627368 # Number of tag accesses 1103system.cpu0.dcache.tags.data_accesses 627368 # Number of data accesses 1104system.cpu0.dcache.ReadReq_hits::cpu0.data 79025 # number of ReadReq hits 1105system.cpu0.dcache.ReadReq_hits::total 79025 # number of ReadReq hits 1106system.cpu0.dcache.WriteReq_hits::cpu0.data 76734 # number of WriteReq hits 1107system.cpu0.dcache.WriteReq_hits::total 76734 # number of WriteReq hits | 1139system.cpu0.dcache.tags.tag_accesses 627036 # Number of tag accesses 1140system.cpu0.dcache.tags.data_accesses 627036 # Number of data accesses 1141system.cpu0.dcache.ReadReq_hits::cpu0.data 78986 # number of ReadReq hits 1142system.cpu0.dcache.ReadReq_hits::total 78986 # number of ReadReq hits 1143system.cpu0.dcache.WriteReq_hits::cpu0.data 76692 # number of WriteReq hits 1144system.cpu0.dcache.WriteReq_hits::total 76692 # number of WriteReq hits |
| 1108system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits 1109system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits | 1145system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits 1146system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits |
| 1110system.cpu0.dcache.demand_hits::cpu0.data 155759 # number of demand (read+write) hits 1111system.cpu0.dcache.demand_hits::total 155759 # number of demand (read+write) hits 1112system.cpu0.dcache.overall_hits::cpu0.data 155759 # number of overall hits 1113system.cpu0.dcache.overall_hits::total 155759 # number of overall hits 1114system.cpu0.dcache.ReadReq_misses::cpu0.data 418 # number of ReadReq misses 1115system.cpu0.dcache.ReadReq_misses::total 418 # number of ReadReq misses | 1147system.cpu0.dcache.demand_hits::cpu0.data 155678 # number of demand (read+write) hits 1148system.cpu0.dcache.demand_hits::total 155678 # number of demand (read+write) hits 1149system.cpu0.dcache.overall_hits::cpu0.data 155678 # number of overall hits 1150system.cpu0.dcache.overall_hits::total 155678 # number of overall hits 1151system.cpu0.dcache.ReadReq_misses::cpu0.data 416 # number of ReadReq misses 1152system.cpu0.dcache.ReadReq_misses::total 416 # number of ReadReq misses |
| 1116system.cpu0.dcache.WriteReq_misses::cpu0.data 545 # number of WriteReq misses 1117system.cpu0.dcache.WriteReq_misses::total 545 # number of WriteReq misses 1118system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses 1119system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses | 1153system.cpu0.dcache.WriteReq_misses::cpu0.data 545 # number of WriteReq misses 1154system.cpu0.dcache.WriteReq_misses::total 545 # number of WriteReq misses 1155system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses 1156system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses |
| 1120system.cpu0.dcache.demand_misses::cpu0.data 963 # number of demand (read+write) misses 1121system.cpu0.dcache.demand_misses::total 963 # number of demand (read+write) misses 1122system.cpu0.dcache.overall_misses::cpu0.data 963 # number of overall misses 1123system.cpu0.dcache.overall_misses::total 963 # number of overall misses 1124system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13454697 # number of ReadReq miss cycles 1125system.cpu0.dcache.ReadReq_miss_latency::total 13454697 # number of ReadReq miss cycles 1126system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32621759 # number of WriteReq miss cycles 1127system.cpu0.dcache.WriteReq_miss_latency::total 32621759 # number of WriteReq miss cycles | 1157system.cpu0.dcache.demand_misses::cpu0.data 961 # number of demand (read+write) misses 1158system.cpu0.dcache.demand_misses::total 961 # number of demand (read+write) misses 1159system.cpu0.dcache.overall_misses::cpu0.data 961 # number of overall misses 1160system.cpu0.dcache.overall_misses::total 961 # number of overall misses 1161system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13375931 # number of ReadReq miss cycles 1162system.cpu0.dcache.ReadReq_miss_latency::total 13375931 # number of ReadReq miss cycles 1163system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32683256 # number of WriteReq miss cycles 1164system.cpu0.dcache.WriteReq_miss_latency::total 32683256 # number of WriteReq miss cycles |
| 1128system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 404750 # number of SwapReq miss cycles 1129system.cpu0.dcache.SwapReq_miss_latency::total 404750 # number of SwapReq miss cycles | 1165system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 404750 # number of SwapReq miss cycles 1166system.cpu0.dcache.SwapReq_miss_latency::total 404750 # number of SwapReq miss cycles |
| 1130system.cpu0.dcache.demand_miss_latency::cpu0.data 46076456 # number of demand (read+write) miss cycles 1131system.cpu0.dcache.demand_miss_latency::total 46076456 # number of demand (read+write) miss cycles 1132system.cpu0.dcache.overall_miss_latency::cpu0.data 46076456 # number of overall miss cycles 1133system.cpu0.dcache.overall_miss_latency::total 46076456 # number of overall miss cycles 1134system.cpu0.dcache.ReadReq_accesses::cpu0.data 79443 # number of ReadReq accesses(hits+misses) 1135system.cpu0.dcache.ReadReq_accesses::total 79443 # number of ReadReq accesses(hits+misses) 1136system.cpu0.dcache.WriteReq_accesses::cpu0.data 77279 # number of WriteReq accesses(hits+misses) 1137system.cpu0.dcache.WriteReq_accesses::total 77279 # number of WriteReq accesses(hits+misses) | 1167system.cpu0.dcache.demand_miss_latency::cpu0.data 46059187 # number of demand (read+write) miss cycles 1168system.cpu0.dcache.demand_miss_latency::total 46059187 # number of demand (read+write) miss cycles 1169system.cpu0.dcache.overall_miss_latency::cpu0.data 46059187 # number of overall miss cycles 1170system.cpu0.dcache.overall_miss_latency::total 46059187 # number of overall miss cycles 1171system.cpu0.dcache.ReadReq_accesses::cpu0.data 79402 # number of ReadReq accesses(hits+misses) 1172system.cpu0.dcache.ReadReq_accesses::total 79402 # number of ReadReq accesses(hits+misses) 1173system.cpu0.dcache.WriteReq_accesses::cpu0.data 77237 # number of WriteReq accesses(hits+misses) 1174system.cpu0.dcache.WriteReq_accesses::total 77237 # number of WriteReq accesses(hits+misses) |
| 1138system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 1139system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) | 1175system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 1176system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) |
| 1140system.cpu0.dcache.demand_accesses::cpu0.data 156722 # number of demand (read+write) accesses 1141system.cpu0.dcache.demand_accesses::total 156722 # number of demand (read+write) accesses 1142system.cpu0.dcache.overall_accesses::cpu0.data 156722 # number of overall (read+write) accesses 1143system.cpu0.dcache.overall_accesses::total 156722 # number of overall (read+write) accesses 1144system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005262 # miss rate for ReadReq accesses 1145system.cpu0.dcache.ReadReq_miss_rate::total 0.005262 # miss rate for ReadReq accesses 1146system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007052 # miss rate for WriteReq accesses 1147system.cpu0.dcache.WriteReq_miss_rate::total 0.007052 # miss rate for WriteReq accesses | 1177system.cpu0.dcache.demand_accesses::cpu0.data 156639 # number of demand (read+write) accesses 1178system.cpu0.dcache.demand_accesses::total 156639 # number of demand (read+write) accesses 1179system.cpu0.dcache.overall_accesses::cpu0.data 156639 # number of overall (read+write) accesses 1180system.cpu0.dcache.overall_accesses::total 156639 # number of overall (read+write) accesses 1181system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005239 # miss rate for ReadReq accesses 1182system.cpu0.dcache.ReadReq_miss_rate::total 0.005239 # miss rate for ReadReq accesses 1183system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007056 # miss rate for WriteReq accesses 1184system.cpu0.dcache.WriteReq_miss_rate::total 0.007056 # miss rate for WriteReq accesses |
| 1148system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses 1149system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses | 1185system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses 1186system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses |
| 1150system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006145 # miss rate for demand accesses 1151system.cpu0.dcache.demand_miss_rate::total 0.006145 # miss rate for demand accesses 1152system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006145 # miss rate for overall accesses 1153system.cpu0.dcache.overall_miss_rate::total 0.006145 # miss rate for overall accesses 1154system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32188.270335 # average ReadReq miss latency 1155system.cpu0.dcache.ReadReq_avg_miss_latency::total 32188.270335 # average ReadReq miss latency 1156system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 59856.438532 # average WriteReq miss latency 1157system.cpu0.dcache.WriteReq_avg_miss_latency::total 59856.438532 # average WriteReq miss latency | 1187system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006135 # miss rate for demand accesses 1188system.cpu0.dcache.demand_miss_rate::total 0.006135 # miss rate for demand accesses 1189system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006135 # miss rate for overall accesses 1190system.cpu0.dcache.overall_miss_rate::total 0.006135 # miss rate for overall accesses 1191system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32153.680288 # average ReadReq miss latency 1192system.cpu0.dcache.ReadReq_avg_miss_latency::total 32153.680288 # average ReadReq miss latency 1193system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 59969.277064 # average WriteReq miss latency 1194system.cpu0.dcache.WriteReq_avg_miss_latency::total 59969.277064 # average WriteReq miss latency |
| 1158system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19273.809524 # average SwapReq miss latency 1159system.cpu0.dcache.SwapReq_avg_miss_latency::total 19273.809524 # average SwapReq miss latency | 1195system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19273.809524 # average SwapReq miss latency 1196system.cpu0.dcache.SwapReq_avg_miss_latency::total 19273.809524 # average SwapReq miss latency |
| 1160system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47846.787124 # average overall miss latency 1161system.cpu0.dcache.demand_avg_miss_latency::total 47846.787124 # average overall miss latency 1162system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47846.787124 # average overall miss latency 1163system.cpu0.dcache.overall_avg_miss_latency::total 47846.787124 # average overall miss latency 1164system.cpu0.dcache.blocked_cycles::no_mshrs 524 # number of cycles access was blocked | 1197system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47928.394381 # average overall miss latency 1198system.cpu0.dcache.demand_avg_miss_latency::total 47928.394381 # average overall miss latency 1199system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47928.394381 # average overall miss latency 1200system.cpu0.dcache.overall_avg_miss_latency::total 47928.394381 # average overall miss latency 1201system.cpu0.dcache.blocked_cycles::no_mshrs 512 # number of cycles access was blocked |
| 1165system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1202system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1166system.cpu0.dcache.blocked::no_mshrs 20 # number of cycles access was blocked | 1203system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked |
| 1167system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked | 1204system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 1168system.cpu0.dcache.avg_blocked_cycles::no_mshrs 26.200000 # average number of cycles each access was blocked | 1205system.cpu0.dcache.avg_blocked_cycles::no_mshrs 24.380952 # average number of cycles each access was blocked |
| 1169system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1170system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1171system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1172system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 1173system.cpu0.dcache.writebacks::total 1 # number of writebacks | 1206system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1207system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1208system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1209system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 1210system.cpu0.dcache.writebacks::total 1 # number of writebacks |
| 1174system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 230 # number of ReadReq MSHR hits 1175system.cpu0.dcache.ReadReq_mshr_hits::total 230 # number of ReadReq MSHR hits | 1211system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 228 # number of ReadReq MSHR hits 1212system.cpu0.dcache.ReadReq_mshr_hits::total 228 # number of ReadReq MSHR hits |
| 1176system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits 1177system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits | 1213system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits 1214system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits |
| 1178system.cpu0.dcache.demand_mshr_hits::cpu0.data 600 # number of demand (read+write) MSHR hits 1179system.cpu0.dcache.demand_mshr_hits::total 600 # number of demand (read+write) MSHR hits 1180system.cpu0.dcache.overall_mshr_hits::cpu0.data 600 # number of overall MSHR hits 1181system.cpu0.dcache.overall_mshr_hits::total 600 # number of overall MSHR hits | 1215system.cpu0.dcache.demand_mshr_hits::cpu0.data 598 # number of demand (read+write) MSHR hits 1216system.cpu0.dcache.demand_mshr_hits::total 598 # number of demand (read+write) MSHR hits 1217system.cpu0.dcache.overall_mshr_hits::cpu0.data 598 # number of overall MSHR hits 1218system.cpu0.dcache.overall_mshr_hits::total 598 # number of overall MSHR hits |
| 1182system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188 # number of ReadReq MSHR misses 1183system.cpu0.dcache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses 1184system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses 1185system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses 1186system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses 1187system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses 1188system.cpu0.dcache.demand_mshr_misses::cpu0.data 363 # number of demand (read+write) MSHR misses 1189system.cpu0.dcache.demand_mshr_misses::total 363 # number of demand (read+write) MSHR misses 1190system.cpu0.dcache.overall_mshr_misses::cpu0.data 363 # number of overall MSHR misses 1191system.cpu0.dcache.overall_mshr_misses::total 363 # number of overall MSHR misses | 1219system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188 # number of ReadReq MSHR misses 1220system.cpu0.dcache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses 1221system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses 1222system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses 1223system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses 1224system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses 1225system.cpu0.dcache.demand_mshr_misses::cpu0.data 363 # number of demand (read+write) MSHR misses 1226system.cpu0.dcache.demand_mshr_misses::total 363 # number of demand (read+write) MSHR misses 1227system.cpu0.dcache.overall_mshr_misses::cpu0.data 363 # number of overall MSHR misses 1228system.cpu0.dcache.overall_mshr_misses::total 363 # number of overall MSHR misses |
| 1192system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6237508 # number of ReadReq MSHR miss cycles 1193system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6237508 # number of ReadReq MSHR miss cycles 1194system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7264228 # number of WriteReq MSHR miss cycles 1195system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7264228 # number of WriteReq MSHR miss cycles | 1229system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6192510 # number of ReadReq MSHR miss cycles 1230system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6192510 # number of ReadReq MSHR miss cycles 1231system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7258228 # number of WriteReq MSHR miss cycles 1232system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7258228 # number of WriteReq MSHR miss cycles |
| 1196system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 361250 # number of SwapReq MSHR miss cycles 1197system.cpu0.dcache.SwapReq_mshr_miss_latency::total 361250 # number of SwapReq MSHR miss cycles | 1233system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 361250 # number of SwapReq MSHR miss cycles 1234system.cpu0.dcache.SwapReq_mshr_miss_latency::total 361250 # number of SwapReq MSHR miss cycles |
| 1198system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13501736 # number of demand (read+write) MSHR miss cycles 1199system.cpu0.dcache.demand_mshr_miss_latency::total 13501736 # number of demand (read+write) MSHR miss cycles 1200system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13501736 # number of overall MSHR miss cycles 1201system.cpu0.dcache.overall_mshr_miss_latency::total 13501736 # number of overall MSHR miss cycles 1202system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002366 # mshr miss rate for ReadReq accesses 1203system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002366 # mshr miss rate for ReadReq accesses 1204system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002265 # mshr miss rate for WriteReq accesses 1205system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002265 # mshr miss rate for WriteReq accesses | 1235system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13450738 # number of demand (read+write) MSHR miss cycles 1236system.cpu0.dcache.demand_mshr_miss_latency::total 13450738 # number of demand (read+write) MSHR miss cycles 1237system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13450738 # number of overall MSHR miss cycles 1238system.cpu0.dcache.overall_mshr_miss_latency::total 13450738 # number of overall MSHR miss cycles 1239system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002368 # mshr miss rate for ReadReq accesses 1240system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002368 # mshr miss rate for ReadReq accesses 1241system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002266 # mshr miss rate for WriteReq accesses 1242system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002266 # mshr miss rate for WriteReq accesses |
| 1206system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses 1207system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses | 1243system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses 1244system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses |
| 1208system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002316 # mshr miss rate for demand accesses 1209system.cpu0.dcache.demand_mshr_miss_rate::total 0.002316 # mshr miss rate for demand accesses 1210system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002316 # mshr miss rate for overall accesses 1211system.cpu0.dcache.overall_mshr_miss_rate::total 0.002316 # mshr miss rate for overall accesses 1212system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 33178.234043 # average ReadReq mshr miss latency 1213system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 33178.234043 # average ReadReq mshr miss latency 1214system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41509.874286 # average WriteReq mshr miss latency 1215system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41509.874286 # average WriteReq mshr miss latency | 1245system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002317 # mshr miss rate for demand accesses 1246system.cpu0.dcache.demand_mshr_miss_rate::total 0.002317 # mshr miss rate for demand accesses 1247system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002317 # mshr miss rate for overall accesses 1248system.cpu0.dcache.overall_mshr_miss_rate::total 0.002317 # mshr miss rate for overall accesses 1249system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32938.882979 # average ReadReq mshr miss latency 1250system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32938.882979 # average ReadReq mshr miss latency 1251system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41475.588571 # average WriteReq mshr miss latency 1252system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41475.588571 # average WriteReq mshr miss latency |
| 1216system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17202.380952 # average SwapReq mshr miss latency 1217system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17202.380952 # average SwapReq mshr miss latency | 1253system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17202.380952 # average SwapReq mshr miss latency 1254system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17202.380952 # average SwapReq mshr miss latency |
| 1218system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37194.865014 # average overall mshr miss latency 1219system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37194.865014 # average overall mshr miss latency 1220system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37194.865014 # average overall mshr miss latency 1221system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37194.865014 # average overall mshr miss latency | 1255system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37054.374656 # average overall mshr miss latency 1256system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37054.374656 # average overall mshr miss latency 1257system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37054.374656 # average overall mshr miss latency 1258system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37054.374656 # average overall mshr miss latency |
| 1222system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1259system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1223system.cpu1.branchPred.lookups 49230 # Number of BP lookups 1224system.cpu1.branchPred.condPredicted 46482 # Number of conditional branches predicted | 1260system.cpu1.branchPred.lookups 49222 # Number of BP lookups 1261system.cpu1.branchPred.condPredicted 46474 # Number of conditional branches predicted |
| 1225system.cpu1.branchPred.condIncorrect 1275 # Number of conditional branches incorrect | 1262system.cpu1.branchPred.condIncorrect 1275 # Number of conditional branches incorrect |
| 1226system.cpu1.branchPred.BTBLookups 43125 # Number of BTB lookups 1227system.cpu1.branchPred.BTBHits 42318 # Number of BTB hits | 1263system.cpu1.branchPred.BTBLookups 43117 # Number of BTB lookups 1264system.cpu1.branchPred.BTBHits 42310 # Number of BTB hits |
| 1228system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1265system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1229system.cpu1.branchPred.BTBHitPct 98.128696 # BTB Hit Percentage | 1266system.cpu1.branchPred.BTBHitPct 98.128348 # BTB Hit Percentage |
| 1230system.cpu1.branchPred.usedRAS 644 # Number of times the RAS was used to get a target. 1231system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. | 1267system.cpu1.branchPred.usedRAS 644 # Number of times the RAS was used to get a target. 1268system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. |
| 1232system.cpu1.numCycles 177729 # number of cpu cycles simulated | 1269system.cpu1.numCycles 177641 # number of cpu cycles simulated |
| 1233system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1234system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1270system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1271system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1235system.cpu1.fetch.icacheStallCycles 30707 # Number of cycles fetch is stalled on an Icache miss 1236system.cpu1.fetch.Insts 271510 # Number of instructions fetch has processed 1237system.cpu1.fetch.Branches 49230 # Number of branches that fetch encountered 1238system.cpu1.fetch.predictedBranches 42962 # Number of branches that fetch has predicted taken 1239system.cpu1.fetch.Cycles 98061 # Number of cycles fetch has run and was not squashing or blocked | 1272system.cpu1.fetch.icacheStallCycles 30689 # Number of cycles fetch is stalled on an Icache miss 1273system.cpu1.fetch.Insts 271480 # Number of instructions fetch has processed 1274system.cpu1.fetch.Branches 49222 # Number of branches that fetch encountered 1275system.cpu1.fetch.predictedBranches 42954 # Number of branches that fetch has predicted taken 1276system.cpu1.fetch.Cycles 98036 # Number of cycles fetch has run and was not squashing or blocked |
| 1240system.cpu1.fetch.SquashCycles 3712 # Number of cycles fetch has spent squashing | 1277system.cpu1.fetch.SquashCycles 3712 # Number of cycles fetch has spent squashing |
| 1241system.cpu1.fetch.BlockedCycles 35852 # Number of cycles fetch has spent blocked | 1278system.cpu1.fetch.BlockedCycles 35816 # Number of cycles fetch has spent blocked |
| 1242system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 1279system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 1243system.cpu1.fetch.NoActiveThreadStallCycles 7757 # Number of stall cycles due to no active thread to fetch from | 1280system.cpu1.fetch.NoActiveThreadStallCycles 7751 # Number of stall cycles due to no active thread to fetch from |
| 1244system.cpu1.fetch.PendingTrapStallCycles 775 # Number of stall cycles due to pending traps | 1281system.cpu1.fetch.PendingTrapStallCycles 775 # Number of stall cycles due to pending traps |
| 1245system.cpu1.fetch.CacheLines 22354 # Number of cache lines fetched | 1282system.cpu1.fetch.CacheLines 22336 # Number of cache lines fetched |
| 1246system.cpu1.fetch.IcacheSquashes 259 # Number of outstanding Icache misses that were squashed | 1283system.cpu1.fetch.IcacheSquashes 259 # Number of outstanding Icache misses that were squashed |
| 1247system.cpu1.fetch.rateDist::samples 175517 # Number of instructions fetched each cycle (Total) 1248system.cpu1.fetch.rateDist::mean 1.546916 # Number of instructions fetched each cycle (Total) 1249system.cpu1.fetch.rateDist::stdev 2.089154 # Number of instructions fetched each cycle (Total) | 1284system.cpu1.fetch.rateDist::samples 175432 # Number of instructions fetched each cycle (Total) 1285system.cpu1.fetch.rateDist::mean 1.547494 # Number of instructions fetched each cycle (Total) 1286system.cpu1.fetch.rateDist::stdev 2.089471 # Number of instructions fetched each cycle (Total) |
| 1250system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1287system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1251system.cpu1.fetch.rateDist::0 77456 44.13% 44.13% # Number of instructions fetched each cycle (Total) 1252system.cpu1.fetch.rateDist::1 50516 28.78% 72.91% # Number of instructions fetched each cycle (Total) 1253system.cpu1.fetch.rateDist::2 7423 4.23% 77.14% # Number of instructions fetched each cycle (Total) 1254system.cpu1.fetch.rateDist::3 3189 1.82% 78.96% # Number of instructions fetched each cycle (Total) 1255system.cpu1.fetch.rateDist::4 704 0.40% 79.36% # Number of instructions fetched each cycle (Total) 1256system.cpu1.fetch.rateDist::5 30974 17.65% 97.01% # Number of instructions fetched each cycle (Total) 1257system.cpu1.fetch.rateDist::6 1193 0.68% 97.69% # Number of instructions fetched each cycle (Total) | 1288system.cpu1.fetch.rateDist::0 77396 44.12% 44.12% # Number of instructions fetched each cycle (Total) 1289system.cpu1.fetch.rateDist::1 50499 28.79% 72.90% # Number of instructions fetched each cycle (Total) 1290system.cpu1.fetch.rateDist::2 7414 4.23% 77.13% # Number of instructions fetched each cycle (Total) 1291system.cpu1.fetch.rateDist::3 3189 1.82% 78.95% # Number of instructions fetched each cycle (Total) 1292system.cpu1.fetch.rateDist::4 704 0.40% 79.35% # Number of instructions fetched each cycle (Total) 1293system.cpu1.fetch.rateDist::5 30975 17.66% 97.00% # Number of instructions fetched each cycle (Total) 1294system.cpu1.fetch.rateDist::6 1193 0.68% 97.68% # Number of instructions fetched each cycle (Total) |
| 1258system.cpu1.fetch.rateDist::7 759 0.43% 98.12% # Number of instructions fetched each cycle (Total) 1259system.cpu1.fetch.rateDist::8 3303 1.88% 100.00% # Number of instructions fetched each cycle (Total) 1260system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1261system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1262system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 1295system.cpu1.fetch.rateDist::7 759 0.43% 98.12% # Number of instructions fetched each cycle (Total) 1296system.cpu1.fetch.rateDist::8 3303 1.88% 100.00% # Number of instructions fetched each cycle (Total) 1297system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1298system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1299system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 1263system.cpu1.fetch.rateDist::total 175517 # Number of instructions fetched each cycle (Total) 1264system.cpu1.fetch.branchRate 0.276995 # Number of branch fetches per cycle 1265system.cpu1.fetch.rate 1.527663 # Number of inst fetches per cycle 1266system.cpu1.decode.IdleCycles 37188 # Number of cycles decode is idle 1267system.cpu1.decode.BlockedCycles 31008 # Number of cycles decode is blocked 1268system.cpu1.decode.RunCycles 90874 # Number of cycles decode is running 1269system.cpu1.decode.UnblockCycles 6330 # Number of cycles decode is unblocking | 1300system.cpu1.fetch.rateDist::total 175432 # Number of instructions fetched each cycle (Total) 1301system.cpu1.fetch.branchRate 0.277087 # Number of branch fetches per cycle 1302system.cpu1.fetch.rate 1.528251 # Number of inst fetches per cycle 1303system.cpu1.decode.IdleCycles 37161 # Number of cycles decode is idle 1304system.cpu1.decode.BlockedCycles 30981 # Number of cycles decode is blocked 1305system.cpu1.decode.RunCycles 90858 # Number of cycles decode is running 1306system.cpu1.decode.UnblockCycles 6321 # Number of cycles decode is unblocking |
| 1270system.cpu1.decode.SquashCycles 2360 # Number of cycles decode is squashing | 1307system.cpu1.decode.SquashCycles 2360 # Number of cycles decode is squashing |
| 1271system.cpu1.decode.DecodedInsts 267842 # Number of instructions handled by decode | 1308system.cpu1.decode.DecodedInsts 267812 # Number of instructions handled by decode |
| 1272system.cpu1.rename.SquashCycles 2360 # Number of cycles rename is squashing | 1309system.cpu1.rename.SquashCycles 2360 # Number of cycles rename is squashing |
| 1273system.cpu1.rename.IdleCycles 37871 # Number of cycles rename is idle 1274system.cpu1.rename.BlockCycles 18552 # Number of cycles rename is blocking | 1310system.cpu1.rename.IdleCycles 37844 # Number of cycles rename is idle 1311system.cpu1.rename.BlockCycles 18525 # Number of cycles rename is blocking |
| 1275system.cpu1.rename.serializeStallCycles 11702 # count of cycles rename stalled for serializing inst | 1312system.cpu1.rename.serializeStallCycles 11702 # count of cycles rename stalled for serializing inst |
| 1276system.cpu1.rename.RunCycles 84813 # Number of cycles rename is running 1277system.cpu1.rename.UnblockCycles 12462 # Number of cycles rename is unblocking 1278system.cpu1.rename.RenamedInsts 265527 # Number of instructions processed by rename | 1313system.cpu1.rename.RunCycles 84806 # Number of cycles rename is running 1314system.cpu1.rename.UnblockCycles 12444 # Number of cycles rename is unblocking 1315system.cpu1.rename.RenamedInsts 265497 # Number of instructions processed by rename |
| 1279system.cpu1.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full 1280system.cpu1.rename.LSQFullEvents 21 # Number of times rename has blocked due to LSQ full | 1316system.cpu1.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full 1317system.cpu1.rename.LSQFullEvents 21 # Number of times rename has blocked due to LSQ full |
| 1281system.cpu1.rename.RenamedOperands 184379 # Number of destination operands rename has renamed 1282system.cpu1.rename.RenameLookups 502490 # Number of register rename lookups that rename has made 1283system.cpu1.rename.int_rename_lookups 391665 # Number of integer rename lookups 1284system.cpu1.rename.CommittedMaps 171551 # Number of HB maps that are committed | 1318system.cpu1.rename.RenamedOperands 184374 # Number of destination operands rename has renamed 1319system.cpu1.rename.RenameLookups 502466 # Number of register rename lookups that rename has made 1320system.cpu1.rename.int_rename_lookups 391647 # Number of integer rename lookups 1321system.cpu1.rename.CommittedMaps 171546 # Number of HB maps that are committed |
| 1285system.cpu1.rename.UndoneMaps 12828 # Number of HB maps that are undone due to squashing 1286system.cpu1.rename.serializingInsts 1100 # count of serializing insts renamed 1287system.cpu1.rename.tempSerializingInsts 1220 # count of temporary serializing insts renamed | 1322system.cpu1.rename.UndoneMaps 12828 # Number of HB maps that are undone due to squashing 1323system.cpu1.rename.serializingInsts 1100 # count of serializing insts renamed 1324system.cpu1.rename.tempSerializingInsts 1220 # count of temporary serializing insts renamed |
| 1288system.cpu1.rename.skidInsts 15186 # count of insts added to the skid buffer 1289system.cpu1.memDep0.insertedLoads 73774 # Number of loads inserted to the mem dependence unit. 1290system.cpu1.memDep0.insertedStores 34232 # Number of stores inserted to the mem dependence unit. 1291system.cpu1.memDep0.conflictingLoads 35732 # Number of conflicting loads. 1292system.cpu1.memDep0.conflictingStores 29187 # Number of conflicting stores. 1293system.cpu1.iq.iqInstsAdded 218298 # Number of instructions added to the IQ (excludes non-spec) 1294system.cpu1.iq.iqNonSpecInstsAdded 7639 # Number of non-speculative instructions added to the IQ 1295system.cpu1.iq.iqInstsIssued 221677 # Number of instructions issued | 1325system.cpu1.rename.skidInsts 15168 # count of insts added to the skid buffer 1326system.cpu1.memDep0.insertedLoads 73767 # Number of loads inserted to the mem dependence unit. 1327system.cpu1.memDep0.insertedStores 34233 # Number of stores inserted to the mem dependence unit. 1328system.cpu1.memDep0.conflictingLoads 35724 # Number of conflicting loads. 1329system.cpu1.memDep0.conflictingStores 29188 # Number of conflicting stores. 1330system.cpu1.iq.iqInstsAdded 218285 # Number of instructions added to the IQ (excludes non-spec) 1331system.cpu1.iq.iqNonSpecInstsAdded 7630 # Number of non-speculative instructions added to the IQ 1332system.cpu1.iq.iqInstsIssued 221655 # Number of instructions issued |
| 1296system.cpu1.iq.iqSquashedInstsIssued 99 # Number of squashed instructions issued 1297system.cpu1.iq.iqSquashedInstsExamined 10737 # Number of squashed instructions iterated over during squash; mainly for profiling 1298system.cpu1.iq.iqSquashedOperandsExamined 10712 # Number of squashed operands that are examined and possibly removed from graph 1299system.cpu1.iq.iqSquashedNonSpecRemoved 591 # Number of squashed non-spec instructions that were removed | 1333system.cpu1.iq.iqSquashedInstsIssued 99 # Number of squashed instructions issued 1334system.cpu1.iq.iqSquashedInstsExamined 10737 # Number of squashed instructions iterated over during squash; mainly for profiling 1335system.cpu1.iq.iqSquashedOperandsExamined 10712 # Number of squashed operands that are examined and possibly removed from graph 1336system.cpu1.iq.iqSquashedNonSpecRemoved 591 # Number of squashed non-spec instructions that were removed |
| 1300system.cpu1.iq.issued_per_cycle::samples 175517 # Number of insts issued each cycle 1301system.cpu1.iq.issued_per_cycle::mean 1.262994 # Number of insts issued each cycle 1302system.cpu1.iq.issued_per_cycle::stdev 1.299330 # Number of insts issued each cycle | 1337system.cpu1.iq.issued_per_cycle::samples 175432 # Number of insts issued each cycle 1338system.cpu1.iq.issued_per_cycle::mean 1.263481 # Number of insts issued each cycle 1339system.cpu1.iq.issued_per_cycle::stdev 1.299438 # Number of insts issued each cycle |
| 1303system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1340system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1304system.cpu1.iq.issued_per_cycle::0 74868 42.66% 42.66% # Number of insts issued each cycle 1305system.cpu1.iq.issued_per_cycle::1 26303 14.99% 57.64% # Number of insts issued each cycle 1306system.cpu1.iq.issued_per_cycle::2 34475 19.64% 77.28% # Number of insts issued each cycle 1307system.cpu1.iq.issued_per_cycle::3 35103 20.00% 97.28% # Number of insts issued each cycle | 1341system.cpu1.iq.issued_per_cycle::0 74808 42.64% 42.64% # Number of insts issued each cycle 1342system.cpu1.iq.issued_per_cycle::1 26276 14.98% 57.62% # Number of insts issued each cycle 1343system.cpu1.iq.issued_per_cycle::2 34476 19.65% 77.27% # Number of insts issued each cycle 1344system.cpu1.iq.issued_per_cycle::3 35104 20.01% 97.28% # Number of insts issued each cycle |
| 1308system.cpu1.iq.issued_per_cycle::4 3248 1.85% 99.13% # Number of insts issued each cycle 1309system.cpu1.iq.issued_per_cycle::5 1161 0.66% 99.80% # Number of insts issued each cycle 1310system.cpu1.iq.issued_per_cycle::6 252 0.14% 99.94% # Number of insts issued each cycle 1311system.cpu1.iq.issued_per_cycle::7 50 0.03% 99.97% # Number of insts issued each cycle 1312system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle 1313system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1314system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1315system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 1345system.cpu1.iq.issued_per_cycle::4 3248 1.85% 99.13% # Number of insts issued each cycle 1346system.cpu1.iq.issued_per_cycle::5 1161 0.66% 99.80% # Number of insts issued each cycle 1347system.cpu1.iq.issued_per_cycle::6 252 0.14% 99.94% # Number of insts issued each cycle 1348system.cpu1.iq.issued_per_cycle::7 50 0.03% 99.97% # Number of insts issued each cycle 1349system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle 1350system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1351system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1352system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 1316system.cpu1.iq.issued_per_cycle::total 175517 # Number of insts issued each cycle | 1353system.cpu1.iq.issued_per_cycle::total 175432 # Number of insts issued each cycle |
| 1317system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1318system.cpu1.iq.fu_full::IntAlu 12 4.51% 4.51% # attempts to use FU when none available 1319system.cpu1.iq.fu_full::IntMult 0 0.00% 4.51% # attempts to use FU when none available 1320system.cpu1.iq.fu_full::IntDiv 0 0.00% 4.51% # attempts to use FU when none available 1321system.cpu1.iq.fu_full::FloatAdd 0 0.00% 4.51% # attempts to use FU when none available 1322system.cpu1.iq.fu_full::FloatCmp 0 0.00% 4.51% # attempts to use FU when none available 1323system.cpu1.iq.fu_full::FloatCvt 0 0.00% 4.51% # attempts to use FU when none available 1324system.cpu1.iq.fu_full::FloatMult 0 0.00% 4.51% # attempts to use FU when none available --- 19 unchanged lines hidden (view full) --- 1344system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 4.51% # attempts to use FU when none available 1345system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.51% # attempts to use FU when none available 1346system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 4.51% # attempts to use FU when none available 1347system.cpu1.iq.fu_full::MemRead 44 16.54% 21.05% # attempts to use FU when none available 1348system.cpu1.iq.fu_full::MemWrite 210 78.95% 100.00% # attempts to use FU when none available 1349system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1350system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1351system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 1354system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1355system.cpu1.iq.fu_full::IntAlu 12 4.51% 4.51% # attempts to use FU when none available 1356system.cpu1.iq.fu_full::IntMult 0 0.00% 4.51% # attempts to use FU when none available 1357system.cpu1.iq.fu_full::IntDiv 0 0.00% 4.51% # attempts to use FU when none available 1358system.cpu1.iq.fu_full::FloatAdd 0 0.00% 4.51% # attempts to use FU when none available 1359system.cpu1.iq.fu_full::FloatCmp 0 0.00% 4.51% # attempts to use FU when none available 1360system.cpu1.iq.fu_full::FloatCvt 0 0.00% 4.51% # attempts to use FU when none available 1361system.cpu1.iq.fu_full::FloatMult 0 0.00% 4.51% # attempts to use FU when none available --- 19 unchanged lines hidden (view full) --- 1381system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 4.51% # attempts to use FU when none available 1382system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.51% # attempts to use FU when none available 1383system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 4.51% # attempts to use FU when none available 1384system.cpu1.iq.fu_full::MemRead 44 16.54% 21.05% # attempts to use FU when none available 1385system.cpu1.iq.fu_full::MemWrite 210 78.95% 100.00% # attempts to use FU when none available 1386system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1387system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1388system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 1352system.cpu1.iq.FU_type_0::IntAlu 108767 49.07% 49.07% # Type of FU issued | 1389system.cpu1.iq.FU_type_0::IntAlu 108760 49.07% 49.07% # Type of FU issued |
| 1353system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.07% # Type of FU issued 1354system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.07% # Type of FU issued 1355system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.07% # Type of FU issued 1356system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.07% # Type of FU issued 1357system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.07% # Type of FU issued 1358system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.07% # Type of FU issued 1359system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.07% # Type of FU issued 1360system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.07% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 1373system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.07% # Type of FU issued 1374system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.07% # Type of FU issued 1375system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.07% # Type of FU issued 1376system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.07% # Type of FU issued 1377system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.07% # Type of FU issued 1378system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.07% # Type of FU issued 1379system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.07% # Type of FU issued 1380system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.07% # Type of FU issued | 1390system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.07% # Type of FU issued 1391system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.07% # Type of FU issued 1392system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.07% # Type of FU issued 1393system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.07% # Type of FU issued 1394system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.07% # Type of FU issued 1395system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.07% # Type of FU issued 1396system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.07% # Type of FU issued 1397system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.07% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 1410system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.07% # Type of FU issued 1411system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.07% # Type of FU issued 1412system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.07% # Type of FU issued 1413system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.07% # Type of FU issued 1414system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.07% # Type of FU issued 1415system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.07% # Type of FU issued 1416system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.07% # Type of FU issued 1417system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.07% # Type of FU issued |
| 1381system.cpu1.iq.FU_type_0::MemRead 79372 35.81% 84.87% # Type of FU issued 1382system.cpu1.iq.FU_type_0::MemWrite 33538 15.13% 100.00% # Type of FU issued | 1418system.cpu1.iq.FU_type_0::MemRead 79356 35.80% 84.87% # Type of FU issued 1419system.cpu1.iq.FU_type_0::MemWrite 33539 15.13% 100.00% # Type of FU issued |
| 1383system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1384system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1420system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1421system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 1385system.cpu1.iq.FU_type_0::total 221677 # Type of FU issued 1386system.cpu1.iq.rate 1.247275 # Inst issue rate | 1422system.cpu1.iq.FU_type_0::total 221655 # Type of FU issued 1423system.cpu1.iq.rate 1.247769 # Inst issue rate |
| 1387system.cpu1.iq.fu_busy_cnt 266 # FU busy when requested 1388system.cpu1.iq.fu_busy_rate 0.001200 # FU busy rate (busy events/executed inst) | 1424system.cpu1.iq.fu_busy_cnt 266 # FU busy when requested 1425system.cpu1.iq.fu_busy_rate 0.001200 # FU busy rate (busy events/executed inst) |
| 1389system.cpu1.iq.int_inst_queue_reads 619236 # Number of integer instruction queue reads 1390system.cpu1.iq.int_inst_queue_writes 236717 # Number of integer instruction queue writes 1391system.cpu1.iq.int_inst_queue_wakeup_accesses 219849 # Number of integer instruction queue wakeup accesses | 1426system.cpu1.iq.int_inst_queue_reads 619107 # Number of integer instruction queue reads 1427system.cpu1.iq.int_inst_queue_writes 236695 # Number of integer instruction queue writes 1428system.cpu1.iq.int_inst_queue_wakeup_accesses 219827 # Number of integer instruction queue wakeup accesses |
| 1392system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1393system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1394system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 1429system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1430system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1431system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 1395system.cpu1.iq.int_alu_accesses 221943 # Number of integer alu accesses | 1432system.cpu1.iq.int_alu_accesses 221921 # Number of integer alu accesses |
| 1396system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses | 1433system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses |
| 1397system.cpu1.iew.lsq.thread0.forwLoads 28929 # Number of loads that had data forwarded from stores | 1434system.cpu1.iew.lsq.thread0.forwLoads 28930 # Number of loads that had data forwarded from stores |
| 1398system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1399system.cpu1.iew.lsq.thread0.squashedLoads 2394 # Number of loads squashed 1400system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 1401system.cpu1.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations 1402system.cpu1.iew.lsq.thread0.squashedStores 1444 # Number of stores squashed 1403system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1404system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1405system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1406system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1407system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1408system.cpu1.iew.iewSquashCycles 2360 # Number of cycles IEW is squashing 1409system.cpu1.iew.iewBlockCycles 686 # Number of cycles IEW is blocking 1410system.cpu1.iew.iewUnblockCycles 42 # Number of cycles IEW is unblocking | 1435system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1436system.cpu1.iew.lsq.thread0.squashedLoads 2394 # Number of loads squashed 1437system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 1438system.cpu1.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations 1439system.cpu1.iew.lsq.thread0.squashedStores 1444 # Number of stores squashed 1440system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1441system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1442system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1443system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1444system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1445system.cpu1.iew.iewSquashCycles 2360 # Number of cycles IEW is squashing 1446system.cpu1.iew.iewBlockCycles 686 # Number of cycles IEW is blocking 1447system.cpu1.iew.iewUnblockCycles 42 # Number of cycles IEW is unblocking |
| 1411system.cpu1.iew.iewDispatchedInsts 262595 # Number of instructions dispatched to IQ | 1448system.cpu1.iew.iewDispatchedInsts 262565 # Number of instructions dispatched to IQ |
| 1412system.cpu1.iew.iewDispSquashedInsts 349 # Number of squashed instructions skipped by dispatch | 1449system.cpu1.iew.iewDispSquashedInsts 349 # Number of squashed instructions skipped by dispatch |
| 1413system.cpu1.iew.iewDispLoadInsts 73774 # Number of dispatched load instructions 1414system.cpu1.iew.iewDispStoreInsts 34232 # Number of dispatched store instructions | 1450system.cpu1.iew.iewDispLoadInsts 73767 # Number of dispatched load instructions 1451system.cpu1.iew.iewDispStoreInsts 34233 # Number of dispatched store instructions |
| 1415system.cpu1.iew.iewDispNonSpecInsts 1056 # Number of dispatched non-speculative instructions 1416system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall 1417system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1418system.cpu1.iew.memOrderViolationEvents 43 # Number of memory order violations 1419system.cpu1.iew.predictedTakenIncorrect 467 # Number of branches that were predicted taken incorrectly 1420system.cpu1.iew.predictedNotTakenIncorrect 918 # Number of branches that were predicted not taken incorrectly 1421system.cpu1.iew.branchMispredicts 1385 # Number of branch mispredicts detected at execute | 1452system.cpu1.iew.iewDispNonSpecInsts 1056 # Number of dispatched non-speculative instructions 1453system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall 1454system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1455system.cpu1.iew.memOrderViolationEvents 43 # Number of memory order violations 1456system.cpu1.iew.predictedTakenIncorrect 467 # Number of branches that were predicted taken incorrectly 1457system.cpu1.iew.predictedNotTakenIncorrect 918 # Number of branches that were predicted not taken incorrectly 1458system.cpu1.iew.branchMispredicts 1385 # Number of branch mispredicts detected at execute |
| 1422system.cpu1.iew.iewExecutedInsts 220501 # Number of executed instructions 1423system.cpu1.iew.iewExecLoadInsts 72766 # Number of load instructions executed | 1459system.cpu1.iew.iewExecutedInsts 220479 # Number of executed instructions 1460system.cpu1.iew.iewExecLoadInsts 72759 # Number of load instructions executed |
| 1424system.cpu1.iew.iewExecSquashedInsts 1176 # Number of squashed instructions skipped in execute 1425system.cpu1.iew.exec_swp 0 # number of swp insts executed | 1461system.cpu1.iew.iewExecSquashedInsts 1176 # Number of squashed instructions skipped in execute 1462system.cpu1.iew.exec_swp 0 # number of swp insts executed |
| 1426system.cpu1.iew.exec_nop 36658 # number of nop insts executed 1427system.cpu1.iew.exec_refs 106223 # number of memory reference insts executed 1428system.cpu1.iew.exec_branches 45902 # Number of branches executed 1429system.cpu1.iew.exec_stores 33457 # Number of stores executed 1430system.cpu1.iew.exec_rate 1.240659 # Inst execution rate 1431system.cpu1.iew.wb_sent 220134 # cumulative count of insts sent to commit 1432system.cpu1.iew.wb_count 219849 # cumulative count of insts written-back 1433system.cpu1.iew.wb_producers 122957 # num instructions producing a value 1434system.cpu1.iew.wb_consumers 127616 # num instructions consuming a value | 1463system.cpu1.iew.exec_nop 36650 # number of nop insts executed 1464system.cpu1.iew.exec_refs 106217 # number of memory reference insts executed 1465system.cpu1.iew.exec_branches 45894 # Number of branches executed 1466system.cpu1.iew.exec_stores 33458 # Number of stores executed 1467system.cpu1.iew.exec_rate 1.241149 # Inst execution rate 1468system.cpu1.iew.wb_sent 220112 # cumulative count of insts sent to commit 1469system.cpu1.iew.wb_count 219827 # cumulative count of insts written-back 1470system.cpu1.iew.wb_producers 122951 # num instructions producing a value 1471system.cpu1.iew.wb_consumers 127610 # num instructions consuming a value |
| 1435system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1472system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 1436system.cpu1.iew.wb_rate 1.236990 # insts written-back per cycle 1437system.cpu1.iew.wb_fanout 0.963492 # average fanout of values written-back | 1473system.cpu1.iew.wb_rate 1.237479 # insts written-back per cycle 1474system.cpu1.iew.wb_fanout 0.963490 # average fanout of values written-back |
| 1438system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1439system.cpu1.commit.commitSquashedInsts 12326 # The number of squashed insts skipped by commit | 1475system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1476system.cpu1.commit.commitSquashedInsts 12326 # The number of squashed insts skipped by commit |
| 1440system.cpu1.commit.commitNonSpecStalls 7048 # The number of times commit has been forced to stall to communicate backwards | 1477system.cpu1.commit.commitNonSpecStalls 7039 # The number of times commit has been forced to stall to communicate backwards |
| 1441system.cpu1.commit.branchMispredicts 1275 # The number of times a branch was mispredicted | 1478system.cpu1.commit.branchMispredicts 1275 # The number of times a branch was mispredicted |
| 1442system.cpu1.commit.committed_per_cycle::samples 165400 # Number of insts commited each cycle 1443system.cpu1.commit.committed_per_cycle::mean 1.513005 # Number of insts commited each cycle 1444system.cpu1.commit.committed_per_cycle::stdev 1.970213 # Number of insts commited each cycle | 1479system.cpu1.commit.committed_per_cycle::samples 165321 # Number of insts commited each cycle 1480system.cpu1.commit.committed_per_cycle::mean 1.513546 # Number of insts commited each cycle 1481system.cpu1.commit.committed_per_cycle::stdev 1.970448 # Number of insts commited each cycle |
| 1445system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 1482system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 1446system.cpu1.commit.committed_per_cycle::0 73929 44.70% 44.70% # Number of insts commited each cycle 1447system.cpu1.commit.committed_per_cycle::1 44053 26.63% 71.33% # Number of insts commited each cycle 1448system.cpu1.commit.committed_per_cycle::2 6103 3.69% 75.02% # Number of insts commited each cycle 1449system.cpu1.commit.committed_per_cycle::3 7962 4.81% 79.83% # Number of insts commited each cycle 1450system.cpu1.commit.committed_per_cycle::4 1564 0.95% 80.78% # Number of insts commited each cycle 1451system.cpu1.commit.committed_per_cycle::5 29500 17.84% 98.62% # Number of insts commited each cycle | 1483system.cpu1.commit.committed_per_cycle::0 73866 44.68% 44.68% # Number of insts commited each cycle 1484system.cpu1.commit.committed_per_cycle::1 44045 26.64% 71.32% # Number of insts commited each cycle 1485system.cpu1.commit.committed_per_cycle::2 6103 3.69% 75.01% # Number of insts commited each cycle 1486system.cpu1.commit.committed_per_cycle::3 7953 4.81% 79.82% # Number of insts commited each cycle 1487system.cpu1.commit.committed_per_cycle::4 1564 0.95% 80.77% # Number of insts commited each cycle 1488system.cpu1.commit.committed_per_cycle::5 29501 17.84% 98.62% # Number of insts commited each cycle |
| 1452system.cpu1.commit.committed_per_cycle::6 477 0.29% 98.90% # Number of insts commited each cycle 1453system.cpu1.commit.committed_per_cycle::7 1008 0.61% 99.51% # Number of insts commited each cycle 1454system.cpu1.commit.committed_per_cycle::8 804 0.49% 100.00% # Number of insts commited each cycle 1455system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1456system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1457system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 1489system.cpu1.commit.committed_per_cycle::6 477 0.29% 98.90% # Number of insts commited each cycle 1490system.cpu1.commit.committed_per_cycle::7 1008 0.61% 99.51% # Number of insts commited each cycle 1491system.cpu1.commit.committed_per_cycle::8 804 0.49% 100.00% # Number of insts commited each cycle 1492system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1493system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1494system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 1458system.cpu1.commit.committed_per_cycle::total 165400 # Number of insts commited each cycle 1459system.cpu1.commit.committedInsts 250251 # Number of instructions committed 1460system.cpu1.commit.committedOps 250251 # Number of ops (including micro ops) committed | 1495system.cpu1.commit.committed_per_cycle::total 165321 # Number of insts commited each cycle 1496system.cpu1.commit.committedInsts 250221 # Number of instructions committed 1497system.cpu1.commit.committedOps 250221 # Number of ops (including micro ops) committed |
| 1461system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed | 1498system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed |
| 1462system.cpu1.commit.refs 104168 # Number of memory references committed 1463system.cpu1.commit.loads 71380 # Number of loads committed 1464system.cpu1.commit.membars 6331 # Number of memory barriers committed 1465system.cpu1.commit.branches 45080 # Number of branches committed | 1499system.cpu1.commit.refs 104162 # Number of memory references committed 1500system.cpu1.commit.loads 71373 # Number of loads committed 1501system.cpu1.commit.membars 6322 # Number of memory barriers committed 1502system.cpu1.commit.branches 45072 # Number of branches committed |
| 1466system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. | 1503system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. |
| 1467system.cpu1.commit.int_insts 171367 # Number of committed integer instructions. | 1504system.cpu1.commit.int_insts 171353 # Number of committed integer instructions. |
| 1468system.cpu1.commit.function_calls 322 # Number of function calls committed. | 1505system.cpu1.commit.function_calls 322 # Number of function calls committed. |
| 1506system.cpu1.commit.op_class_0::No_OpClass 35859 14.33% 14.33% # Class of committed instruction 1507system.cpu1.commit.op_class_0::IntAlu 103878 41.51% 55.85% # Class of committed instruction 1508system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.85% # Class of committed instruction 1509system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.85% # Class of committed instruction 1510system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.85% # Class of committed instruction 1511system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.85% # Class of committed instruction 1512system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.85% # Class of committed instruction 1513system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.85% # Class of committed instruction 1514system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.85% # Class of committed instruction 1515system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.85% # Class of committed instruction 1516system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.85% # Class of committed instruction 1517system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.85% # Class of committed instruction 1518system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.85% # Class of committed instruction 1519system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.85% # Class of committed instruction 1520system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.85% # Class of committed instruction 1521system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.85% # Class of committed instruction 1522system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.85% # Class of committed instruction 1523system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.85% # Class of committed instruction 1524system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.85% # Class of committed instruction 1525system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.85% # Class of committed instruction 1526system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.85% # Class of committed instruction 1527system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.85% # Class of committed instruction 1528system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.85% # Class of committed instruction 1529system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.85% # Class of committed instruction 1530system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.85% # Class of committed instruction 1531system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.85% # Class of committed instruction 1532system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.85% # Class of committed instruction 1533system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.85% # Class of committed instruction 1534system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.85% # Class of committed instruction 1535system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.85% # Class of committed instruction 1536system.cpu1.commit.op_class_0::MemRead 77695 31.05% 86.90% # Class of committed instruction 1537system.cpu1.commit.op_class_0::MemWrite 32789 13.10% 100.00% # Class of committed instruction 1538system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1539system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1540system.cpu1.commit.op_class_0::total 250221 # Class of committed instruction |
|
| 1469system.cpu1.commit.bw_lim_events 804 # number cycles where commit BW limit reached 1470system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits | 1541system.cpu1.commit.bw_lim_events 804 # number cycles where commit BW limit reached 1542system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 1471system.cpu1.rob.rob_reads 426586 # The number of ROB reads 1472system.cpu1.rob.rob_writes 527520 # The number of ROB writes | 1543system.cpu1.rob.rob_reads 426477 # The number of ROB reads 1544system.cpu1.rob.rob_writes 527460 # The number of ROB writes |
| 1473system.cpu1.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself | 1545system.cpu1.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 1474system.cpu1.idleCycles 2212 # Total number of cycles that the CPU has spent unscheduled due to idling 1475system.cpu1.quiesceCycles 44181 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1476system.cpu1.committedInsts 208053 # Number of Instructions Simulated 1477system.cpu1.committedOps 208053 # Number of Ops (including micro ops) Simulated 1478system.cpu1.committedInsts_total 208053 # Number of Instructions Simulated 1479system.cpu1.cpi 0.854249 # CPI: Cycles Per Instruction 1480system.cpu1.cpi_total 0.854249 # CPI: Total CPI of All Threads 1481system.cpu1.ipc 1.170619 # IPC: Instructions Per Cycle 1482system.cpu1.ipc_total 1.170619 # IPC: Total IPC of All Threads 1483system.cpu1.int_regfile_reads 377223 # number of integer regfile reads 1484system.cpu1.int_regfile_writes 176309 # number of integer regfile writes | 1546system.cpu1.idleCycles 2209 # Total number of cycles that the CPU has spent unscheduled due to idling 1547system.cpu1.quiesceCycles 44103 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1548system.cpu1.committedInsts 208040 # Number of Instructions Simulated 1549system.cpu1.committedOps 208040 # Number of Ops (including micro ops) Simulated 1550system.cpu1.committedInsts_total 208040 # Number of Instructions Simulated 1551system.cpu1.cpi 0.853879 # CPI: Cycles Per Instruction 1552system.cpu1.cpi_total 0.853879 # CPI: Total CPI of All Threads 1553system.cpu1.ipc 1.171126 # IPC: Instructions Per Cycle 1554system.cpu1.ipc_total 1.171126 # IPC: Total IPC of All Threads 1555system.cpu1.int_regfile_reads 377205 # number of integer regfile reads 1556system.cpu1.int_regfile_writes 176304 # number of integer regfile writes |
| 1485system.cpu1.fp_regfile_writes 64 # number of floating regfile writes | 1557system.cpu1.fp_regfile_writes 64 # number of floating regfile writes |
| 1486system.cpu1.misc_regfile_reads 107781 # number of misc regfile reads | 1558system.cpu1.misc_regfile_reads 107775 # number of misc regfile reads |
| 1487system.cpu1.misc_regfile_writes 648 # number of misc regfile writes 1488system.cpu1.icache.tags.replacements 318 # number of replacements | 1559system.cpu1.misc_regfile_writes 648 # number of misc regfile writes 1560system.cpu1.icache.tags.replacements 318 # number of replacements |
| 1489system.cpu1.icache.tags.tagsinuse 76.722565 # Cycle average of tags in use 1490system.cpu1.icache.tags.total_refs 21879 # Total number of references to valid blocks. | 1561system.cpu1.icache.tags.tagsinuse 76.769709 # Cycle average of tags in use 1562system.cpu1.icache.tags.total_refs 21861 # Total number of references to valid blocks. |
| 1491system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks. | 1563system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks. |
| 1492system.cpu1.icache.tags.avg_refs 51.119159 # Average number of references to valid blocks. | 1564system.cpu1.icache.tags.avg_refs 51.077103 # Average number of references to valid blocks. |
| 1493system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1565system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1494system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.722565 # Average occupied blocks per requestor 1495system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149849 # Average percentage of cache occupancy 1496system.cpu1.icache.tags.occ_percent::total 0.149849 # Average percentage of cache occupancy | 1566system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.769709 # Average occupied blocks per requestor 1567system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149941 # Average percentage of cache occupancy 1568system.cpu1.icache.tags.occ_percent::total 0.149941 # Average percentage of cache occupancy |
| 1497system.cpu1.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id 1498system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 1499system.cpu1.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id 1500system.cpu1.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id | 1569system.cpu1.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id 1570system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 1571system.cpu1.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id 1572system.cpu1.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id |
| 1501system.cpu1.icache.tags.tag_accesses 22782 # Number of tag accesses 1502system.cpu1.icache.tags.data_accesses 22782 # Number of data accesses 1503system.cpu1.icache.ReadReq_hits::cpu1.inst 21879 # number of ReadReq hits 1504system.cpu1.icache.ReadReq_hits::total 21879 # number of ReadReq hits 1505system.cpu1.icache.demand_hits::cpu1.inst 21879 # number of demand (read+write) hits 1506system.cpu1.icache.demand_hits::total 21879 # number of demand (read+write) hits 1507system.cpu1.icache.overall_hits::cpu1.inst 21879 # number of overall hits 1508system.cpu1.icache.overall_hits::total 21879 # number of overall hits | 1573system.cpu1.icache.tags.tag_accesses 22764 # Number of tag accesses 1574system.cpu1.icache.tags.data_accesses 22764 # Number of data accesses 1575system.cpu1.icache.ReadReq_hits::cpu1.inst 21861 # number of ReadReq hits 1576system.cpu1.icache.ReadReq_hits::total 21861 # number of ReadReq hits 1577system.cpu1.icache.demand_hits::cpu1.inst 21861 # number of demand (read+write) hits 1578system.cpu1.icache.demand_hits::total 21861 # number of demand (read+write) hits 1579system.cpu1.icache.overall_hits::cpu1.inst 21861 # number of overall hits 1580system.cpu1.icache.overall_hits::total 21861 # number of overall hits |
| 1509system.cpu1.icache.ReadReq_misses::cpu1.inst 475 # number of ReadReq misses 1510system.cpu1.icache.ReadReq_misses::total 475 # number of ReadReq misses 1511system.cpu1.icache.demand_misses::cpu1.inst 475 # number of demand (read+write) misses 1512system.cpu1.icache.demand_misses::total 475 # number of demand (read+write) misses 1513system.cpu1.icache.overall_misses::cpu1.inst 475 # number of overall misses 1514system.cpu1.icache.overall_misses::total 475 # number of overall misses | 1581system.cpu1.icache.ReadReq_misses::cpu1.inst 475 # number of ReadReq misses 1582system.cpu1.icache.ReadReq_misses::total 475 # number of ReadReq misses 1583system.cpu1.icache.demand_misses::cpu1.inst 475 # number of demand (read+write) misses 1584system.cpu1.icache.demand_misses::total 475 # number of demand (read+write) misses 1585system.cpu1.icache.overall_misses::cpu1.inst 475 # number of overall misses 1586system.cpu1.icache.overall_misses::total 475 # number of overall misses |
| 1515system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7157495 # number of ReadReq miss cycles 1516system.cpu1.icache.ReadReq_miss_latency::total 7157495 # number of ReadReq miss cycles 1517system.cpu1.icache.demand_miss_latency::cpu1.inst 7157495 # number of demand (read+write) miss cycles 1518system.cpu1.icache.demand_miss_latency::total 7157495 # number of demand (read+write) miss cycles 1519system.cpu1.icache.overall_miss_latency::cpu1.inst 7157495 # number of overall miss cycles 1520system.cpu1.icache.overall_miss_latency::total 7157495 # number of overall miss cycles 1521system.cpu1.icache.ReadReq_accesses::cpu1.inst 22354 # number of ReadReq accesses(hits+misses) 1522system.cpu1.icache.ReadReq_accesses::total 22354 # number of ReadReq accesses(hits+misses) 1523system.cpu1.icache.demand_accesses::cpu1.inst 22354 # number of demand (read+write) accesses 1524system.cpu1.icache.demand_accesses::total 22354 # number of demand (read+write) accesses 1525system.cpu1.icache.overall_accesses::cpu1.inst 22354 # number of overall (read+write) accesses 1526system.cpu1.icache.overall_accesses::total 22354 # number of overall (read+write) accesses 1527system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.021249 # miss rate for ReadReq accesses 1528system.cpu1.icache.ReadReq_miss_rate::total 0.021249 # miss rate for ReadReq accesses 1529system.cpu1.icache.demand_miss_rate::cpu1.inst 0.021249 # miss rate for demand accesses 1530system.cpu1.icache.demand_miss_rate::total 0.021249 # miss rate for demand accesses 1531system.cpu1.icache.overall_miss_rate::cpu1.inst 0.021249 # miss rate for overall accesses 1532system.cpu1.icache.overall_miss_rate::total 0.021249 # miss rate for overall accesses 1533system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15068.410526 # average ReadReq miss latency 1534system.cpu1.icache.ReadReq_avg_miss_latency::total 15068.410526 # average ReadReq miss latency 1535system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15068.410526 # average overall miss latency 1536system.cpu1.icache.demand_avg_miss_latency::total 15068.410526 # average overall miss latency 1537system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15068.410526 # average overall miss latency 1538system.cpu1.icache.overall_avg_miss_latency::total 15068.410526 # average overall miss latency | 1587system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7146245 # number of ReadReq miss cycles 1588system.cpu1.icache.ReadReq_miss_latency::total 7146245 # number of ReadReq miss cycles 1589system.cpu1.icache.demand_miss_latency::cpu1.inst 7146245 # number of demand (read+write) miss cycles 1590system.cpu1.icache.demand_miss_latency::total 7146245 # number of demand (read+write) miss cycles 1591system.cpu1.icache.overall_miss_latency::cpu1.inst 7146245 # number of overall miss cycles 1592system.cpu1.icache.overall_miss_latency::total 7146245 # number of overall miss cycles 1593system.cpu1.icache.ReadReq_accesses::cpu1.inst 22336 # number of ReadReq accesses(hits+misses) 1594system.cpu1.icache.ReadReq_accesses::total 22336 # number of ReadReq accesses(hits+misses) 1595system.cpu1.icache.demand_accesses::cpu1.inst 22336 # number of demand (read+write) accesses 1596system.cpu1.icache.demand_accesses::total 22336 # number of demand (read+write) accesses 1597system.cpu1.icache.overall_accesses::cpu1.inst 22336 # number of overall (read+write) accesses 1598system.cpu1.icache.overall_accesses::total 22336 # number of overall (read+write) accesses 1599system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.021266 # miss rate for ReadReq accesses 1600system.cpu1.icache.ReadReq_miss_rate::total 0.021266 # miss rate for ReadReq accesses 1601system.cpu1.icache.demand_miss_rate::cpu1.inst 0.021266 # miss rate for demand accesses 1602system.cpu1.icache.demand_miss_rate::total 0.021266 # miss rate for demand accesses 1603system.cpu1.icache.overall_miss_rate::cpu1.inst 0.021266 # miss rate for overall accesses 1604system.cpu1.icache.overall_miss_rate::total 0.021266 # miss rate for overall accesses 1605system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15044.726316 # average ReadReq miss latency 1606system.cpu1.icache.ReadReq_avg_miss_latency::total 15044.726316 # average ReadReq miss latency 1607system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15044.726316 # average overall miss latency 1608system.cpu1.icache.demand_avg_miss_latency::total 15044.726316 # average overall miss latency 1609system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15044.726316 # average overall miss latency 1610system.cpu1.icache.overall_avg_miss_latency::total 15044.726316 # average overall miss latency |
| 1539system.cpu1.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked 1540system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1541system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked 1542system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1543system.cpu1.icache.avg_blocked_cycles::no_mshrs 13 # average number of cycles each access was blocked 1544system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1545system.cpu1.icache.fast_writes 0 # number of fast writes performed 1546system.cpu1.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 1551system.cpu1.icache.overall_mshr_hits::cpu1.inst 47 # number of overall MSHR hits 1552system.cpu1.icache.overall_mshr_hits::total 47 # number of overall MSHR hits 1553system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 428 # number of ReadReq MSHR misses 1554system.cpu1.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses 1555system.cpu1.icache.demand_mshr_misses::cpu1.inst 428 # number of demand (read+write) MSHR misses 1556system.cpu1.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses 1557system.cpu1.icache.overall_mshr_misses::cpu1.inst 428 # number of overall MSHR misses 1558system.cpu1.icache.overall_mshr_misses::total 428 # number of overall MSHR misses | 1611system.cpu1.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked 1612system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1613system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked 1614system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1615system.cpu1.icache.avg_blocked_cycles::no_mshrs 13 # average number of cycles each access was blocked 1616system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1617system.cpu1.icache.fast_writes 0 # number of fast writes performed 1618system.cpu1.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 1623system.cpu1.icache.overall_mshr_hits::cpu1.inst 47 # number of overall MSHR hits 1624system.cpu1.icache.overall_mshr_hits::total 47 # number of overall MSHR hits 1625system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 428 # number of ReadReq MSHR misses 1626system.cpu1.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses 1627system.cpu1.icache.demand_mshr_misses::cpu1.inst 428 # number of demand (read+write) MSHR misses 1628system.cpu1.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses 1629system.cpu1.icache.overall_mshr_misses::cpu1.inst 428 # number of overall MSHR misses 1630system.cpu1.icache.overall_mshr_misses::total 428 # number of overall MSHR misses |
| 1559system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5706004 # number of ReadReq MSHR miss cycles 1560system.cpu1.icache.ReadReq_mshr_miss_latency::total 5706004 # number of ReadReq MSHR miss cycles 1561system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5706004 # number of demand (read+write) MSHR miss cycles 1562system.cpu1.icache.demand_mshr_miss_latency::total 5706004 # number of demand (read+write) MSHR miss cycles 1563system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5706004 # number of overall MSHR miss cycles 1564system.cpu1.icache.overall_mshr_miss_latency::total 5706004 # number of overall MSHR miss cycles 1565system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019146 # mshr miss rate for ReadReq accesses 1566system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019146 # mshr miss rate for ReadReq accesses 1567system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019146 # mshr miss rate for demand accesses 1568system.cpu1.icache.demand_mshr_miss_rate::total 0.019146 # mshr miss rate for demand accesses 1569system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019146 # mshr miss rate for overall accesses 1570system.cpu1.icache.overall_mshr_miss_rate::total 0.019146 # mshr miss rate for overall accesses 1571system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13331.785047 # average ReadReq mshr miss latency 1572system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13331.785047 # average ReadReq mshr miss latency 1573system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13331.785047 # average overall mshr miss latency 1574system.cpu1.icache.demand_avg_mshr_miss_latency::total 13331.785047 # average overall mshr miss latency 1575system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13331.785047 # average overall mshr miss latency 1576system.cpu1.icache.overall_avg_mshr_miss_latency::total 13331.785047 # average overall mshr miss latency | 1631system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5694254 # number of ReadReq MSHR miss cycles 1632system.cpu1.icache.ReadReq_mshr_miss_latency::total 5694254 # number of ReadReq MSHR miss cycles 1633system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5694254 # number of demand (read+write) MSHR miss cycles 1634system.cpu1.icache.demand_mshr_miss_latency::total 5694254 # number of demand (read+write) MSHR miss cycles 1635system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5694254 # number of overall MSHR miss cycles 1636system.cpu1.icache.overall_mshr_miss_latency::total 5694254 # number of overall MSHR miss cycles 1637system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019162 # mshr miss rate for ReadReq accesses 1638system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019162 # mshr miss rate for ReadReq accesses 1639system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019162 # mshr miss rate for demand accesses 1640system.cpu1.icache.demand_mshr_miss_rate::total 0.019162 # mshr miss rate for demand accesses 1641system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019162 # mshr miss rate for overall accesses 1642system.cpu1.icache.overall_mshr_miss_rate::total 0.019162 # mshr miss rate for overall accesses 1643system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13304.331776 # average ReadReq mshr miss latency 1644system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13304.331776 # average ReadReq mshr miss latency 1645system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13304.331776 # average overall mshr miss latency 1646system.cpu1.icache.demand_avg_mshr_miss_latency::total 13304.331776 # average overall mshr miss latency 1647system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13304.331776 # average overall mshr miss latency 1648system.cpu1.icache.overall_avg_mshr_miss_latency::total 13304.331776 # average overall mshr miss latency |
| 1577system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1578system.cpu1.dcache.tags.replacements 0 # number of replacements | 1649system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1650system.cpu1.dcache.tags.replacements 0 # number of replacements |
| 1579system.cpu1.dcache.tags.tagsinuse 23.630187 # Cycle average of tags in use 1580system.cpu1.dcache.tags.total_refs 38790 # Total number of references to valid blocks. | 1651system.cpu1.dcache.tags.tagsinuse 23.645460 # Cycle average of tags in use 1652system.cpu1.dcache.tags.total_refs 38791 # Total number of references to valid blocks. |
| 1581system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. | 1653system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. |
| 1582system.cpu1.dcache.tags.avg_refs 1385.357143 # Average number of references to valid blocks. | 1654system.cpu1.dcache.tags.avg_refs 1385.392857 # Average number of references to valid blocks. |
| 1583system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1655system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1584system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.630187 # Average occupied blocks per requestor 1585system.cpu1.dcache.tags.occ_percent::cpu1.data 0.046153 # Average percentage of cache occupancy 1586system.cpu1.dcache.tags.occ_percent::total 0.046153 # Average percentage of cache occupancy | 1656system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.645460 # Average occupied blocks per requestor 1657system.cpu1.dcache.tags.occ_percent::cpu1.data 0.046183 # Average percentage of cache occupancy 1658system.cpu1.dcache.tags.occ_percent::total 0.046183 # Average percentage of cache occupancy |
| 1587system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id 1588system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 1589system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id | 1659system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id 1660system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 1661system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id |
| 1590system.cpu1.dcache.tags.tag_accesses 306681 # Number of tag accesses 1591system.cpu1.dcache.tags.data_accesses 306681 # Number of data accesses 1592system.cpu1.dcache.ReadReq_hits::cpu1.data 43485 # number of ReadReq hits 1593system.cpu1.dcache.ReadReq_hits::total 43485 # number of ReadReq hits 1594system.cpu1.dcache.WriteReq_hits::cpu1.data 32585 # number of WriteReq hits 1595system.cpu1.dcache.WriteReq_hits::total 32585 # number of WriteReq hits | 1662system.cpu1.dcache.tags.tag_accesses 306653 # Number of tag accesses 1663system.cpu1.dcache.tags.data_accesses 306653 # Number of data accesses 1664system.cpu1.dcache.ReadReq_hits::cpu1.data 43477 # number of ReadReq hits 1665system.cpu1.dcache.ReadReq_hits::total 43477 # number of ReadReq hits 1666system.cpu1.dcache.WriteReq_hits::cpu1.data 32586 # number of WriteReq hits 1667system.cpu1.dcache.WriteReq_hits::total 32586 # number of WriteReq hits |
| 1596system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits 1597system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits | 1668system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits 1669system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits |
| 1598system.cpu1.dcache.demand_hits::cpu1.data 76070 # number of demand (read+write) hits 1599system.cpu1.dcache.demand_hits::total 76070 # number of demand (read+write) hits 1600system.cpu1.dcache.overall_hits::cpu1.data 76070 # number of overall hits 1601system.cpu1.dcache.overall_hits::total 76070 # number of overall hits | 1670system.cpu1.dcache.demand_hits::cpu1.data 76063 # number of demand (read+write) hits 1671system.cpu1.dcache.demand_hits::total 76063 # number of demand (read+write) hits 1672system.cpu1.dcache.overall_hits::cpu1.data 76063 # number of overall hits 1673system.cpu1.dcache.overall_hits::total 76063 # number of overall hits |
| 1602system.cpu1.dcache.ReadReq_misses::cpu1.data 336 # number of ReadReq misses 1603system.cpu1.dcache.ReadReq_misses::total 336 # number of ReadReq misses 1604system.cpu1.dcache.WriteReq_misses::cpu1.data 132 # number of WriteReq misses 1605system.cpu1.dcache.WriteReq_misses::total 132 # number of WriteReq misses 1606system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses 1607system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses 1608system.cpu1.dcache.demand_misses::cpu1.data 468 # number of demand (read+write) misses 1609system.cpu1.dcache.demand_misses::total 468 # number of demand (read+write) misses 1610system.cpu1.dcache.overall_misses::cpu1.data 468 # number of overall misses 1611system.cpu1.dcache.overall_misses::total 468 # number of overall misses | 1674system.cpu1.dcache.ReadReq_misses::cpu1.data 336 # number of ReadReq misses 1675system.cpu1.dcache.ReadReq_misses::total 336 # number of ReadReq misses 1676system.cpu1.dcache.WriteReq_misses::cpu1.data 132 # number of WriteReq misses 1677system.cpu1.dcache.WriteReq_misses::total 132 # number of WriteReq misses 1678system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses 1679system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses 1680system.cpu1.dcache.demand_misses::cpu1.data 468 # number of demand (read+write) misses 1681system.cpu1.dcache.demand_misses::total 468 # number of demand (read+write) misses 1682system.cpu1.dcache.overall_misses::cpu1.data 468 # number of overall misses 1683system.cpu1.dcache.overall_misses::total 468 # number of overall misses |
| 1612system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4179135 # number of ReadReq miss cycles 1613system.cpu1.dcache.ReadReq_miss_latency::total 4179135 # number of ReadReq miss cycles | 1684system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4177635 # number of ReadReq miss cycles 1685system.cpu1.dcache.ReadReq_miss_latency::total 4177635 # number of ReadReq miss cycles |
| 1614system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2763761 # number of WriteReq miss cycles 1615system.cpu1.dcache.WriteReq_miss_latency::total 2763761 # number of WriteReq miss cycles 1616system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 521507 # number of SwapReq miss cycles 1617system.cpu1.dcache.SwapReq_miss_latency::total 521507 # number of SwapReq miss cycles | 1686system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2763761 # number of WriteReq miss cycles 1687system.cpu1.dcache.WriteReq_miss_latency::total 2763761 # number of WriteReq miss cycles 1688system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 521507 # number of SwapReq miss cycles 1689system.cpu1.dcache.SwapReq_miss_latency::total 521507 # number of SwapReq miss cycles |
| 1618system.cpu1.dcache.demand_miss_latency::cpu1.data 6942896 # number of demand (read+write) miss cycles 1619system.cpu1.dcache.demand_miss_latency::total 6942896 # number of demand (read+write) miss cycles 1620system.cpu1.dcache.overall_miss_latency::cpu1.data 6942896 # number of overall miss cycles 1621system.cpu1.dcache.overall_miss_latency::total 6942896 # number of overall miss cycles 1622system.cpu1.dcache.ReadReq_accesses::cpu1.data 43821 # number of ReadReq accesses(hits+misses) 1623system.cpu1.dcache.ReadReq_accesses::total 43821 # number of ReadReq accesses(hits+misses) 1624system.cpu1.dcache.WriteReq_accesses::cpu1.data 32717 # number of WriteReq accesses(hits+misses) 1625system.cpu1.dcache.WriteReq_accesses::total 32717 # number of WriteReq accesses(hits+misses) | 1690system.cpu1.dcache.demand_miss_latency::cpu1.data 6941396 # number of demand (read+write) miss cycles 1691system.cpu1.dcache.demand_miss_latency::total 6941396 # number of demand (read+write) miss cycles 1692system.cpu1.dcache.overall_miss_latency::cpu1.data 6941396 # number of overall miss cycles 1693system.cpu1.dcache.overall_miss_latency::total 6941396 # number of overall miss cycles 1694system.cpu1.dcache.ReadReq_accesses::cpu1.data 43813 # number of ReadReq accesses(hits+misses) 1695system.cpu1.dcache.ReadReq_accesses::total 43813 # number of ReadReq accesses(hits+misses) 1696system.cpu1.dcache.WriteReq_accesses::cpu1.data 32718 # number of WriteReq accesses(hits+misses) 1697system.cpu1.dcache.WriteReq_accesses::total 32718 # number of WriteReq accesses(hits+misses) |
| 1626system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) 1627system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) | 1698system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) 1699system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) |
| 1628system.cpu1.dcache.demand_accesses::cpu1.data 76538 # number of demand (read+write) accesses 1629system.cpu1.dcache.demand_accesses::total 76538 # number of demand (read+write) accesses 1630system.cpu1.dcache.overall_accesses::cpu1.data 76538 # number of overall (read+write) accesses 1631system.cpu1.dcache.overall_accesses::total 76538 # number of overall (read+write) accesses 1632system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.007668 # miss rate for ReadReq accesses 1633system.cpu1.dcache.ReadReq_miss_rate::total 0.007668 # miss rate for ReadReq accesses 1634system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004035 # miss rate for WriteReq accesses 1635system.cpu1.dcache.WriteReq_miss_rate::total 0.004035 # miss rate for WriteReq accesses | 1700system.cpu1.dcache.demand_accesses::cpu1.data 76531 # number of demand (read+write) accesses 1701system.cpu1.dcache.demand_accesses::total 76531 # number of demand (read+write) accesses 1702system.cpu1.dcache.overall_accesses::cpu1.data 76531 # number of overall (read+write) accesses 1703system.cpu1.dcache.overall_accesses::total 76531 # number of overall (read+write) accesses 1704system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.007669 # miss rate for ReadReq accesses 1705system.cpu1.dcache.ReadReq_miss_rate::total 0.007669 # miss rate for ReadReq accesses 1706system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004034 # miss rate for WriteReq accesses 1707system.cpu1.dcache.WriteReq_miss_rate::total 0.004034 # miss rate for WriteReq accesses |
| 1636system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses 1637system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses 1638system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006115 # miss rate for demand accesses 1639system.cpu1.dcache.demand_miss_rate::total 0.006115 # miss rate for demand accesses 1640system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006115 # miss rate for overall accesses 1641system.cpu1.dcache.overall_miss_rate::total 0.006115 # miss rate for overall accesses | 1708system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses 1709system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses 1710system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006115 # miss rate for demand accesses 1711system.cpu1.dcache.demand_miss_rate::total 0.006115 # miss rate for demand accesses 1712system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006115 # miss rate for overall accesses 1713system.cpu1.dcache.overall_miss_rate::total 0.006115 # miss rate for overall accesses |
| 1642system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12437.901786 # average ReadReq miss latency 1643system.cpu1.dcache.ReadReq_avg_miss_latency::total 12437.901786 # average ReadReq miss latency | 1714system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12433.437500 # average ReadReq miss latency 1715system.cpu1.dcache.ReadReq_avg_miss_latency::total 12433.437500 # average ReadReq miss latency |
| 1644system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20937.583333 # average WriteReq miss latency 1645system.cpu1.dcache.WriteReq_avg_miss_latency::total 20937.583333 # average WriteReq miss latency 1646system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9149.245614 # average SwapReq miss latency 1647system.cpu1.dcache.SwapReq_avg_miss_latency::total 9149.245614 # average SwapReq miss latency | 1716system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20937.583333 # average WriteReq miss latency 1717system.cpu1.dcache.WriteReq_avg_miss_latency::total 20937.583333 # average WriteReq miss latency 1718system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9149.245614 # average SwapReq miss latency 1719system.cpu1.dcache.SwapReq_avg_miss_latency::total 9149.245614 # average SwapReq miss latency |
| 1648system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14835.247863 # average overall miss latency 1649system.cpu1.dcache.demand_avg_miss_latency::total 14835.247863 # average overall miss latency 1650system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14835.247863 # average overall miss latency 1651system.cpu1.dcache.overall_avg_miss_latency::total 14835.247863 # average overall miss latency | 1720system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14832.042735 # average overall miss latency 1721system.cpu1.dcache.demand_avg_miss_latency::total 14832.042735 # average overall miss latency 1722system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14832.042735 # average overall miss latency 1723system.cpu1.dcache.overall_avg_miss_latency::total 14832.042735 # average overall miss latency |
| 1652system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1653system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1654system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1655system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1656system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1657system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1658system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1659system.cpu1.dcache.cache_copies 0 # number of cache copies performed --- 10 unchanged lines hidden (view full) --- 1670system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 102 # number of WriteReq MSHR misses 1671system.cpu1.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses 1672system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 57 # number of SwapReq MSHR misses 1673system.cpu1.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses 1674system.cpu1.dcache.demand_mshr_misses::cpu1.data 260 # number of demand (read+write) MSHR misses 1675system.cpu1.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses 1676system.cpu1.dcache.overall_mshr_misses::cpu1.data 260 # number of overall MSHR misses 1677system.cpu1.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses | 1724system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1725system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1726system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1727system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1728system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1729system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1730system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1731system.cpu1.dcache.cache_copies 0 # number of cache copies performed --- 10 unchanged lines hidden (view full) --- 1742system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 102 # number of WriteReq MSHR misses 1743system.cpu1.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses 1744system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 57 # number of SwapReq MSHR misses 1745system.cpu1.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses 1746system.cpu1.dcache.demand_mshr_misses::cpu1.data 260 # number of demand (read+write) MSHR misses 1747system.cpu1.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses 1748system.cpu1.dcache.overall_mshr_misses::cpu1.data 260 # number of overall MSHR misses 1749system.cpu1.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses |
| 1678system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1078019 # number of ReadReq MSHR miss cycles 1679system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1078019 # number of ReadReq MSHR miss cycles | 1750system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1076519 # number of ReadReq MSHR miss cycles 1751system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1076519 # number of ReadReq MSHR miss cycles |
| 1680system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1313739 # number of WriteReq MSHR miss cycles 1681system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1313739 # number of WriteReq MSHR miss cycles 1682system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 407493 # number of SwapReq MSHR miss cycles 1683system.cpu1.dcache.SwapReq_mshr_miss_latency::total 407493 # number of SwapReq MSHR miss cycles | 1752system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1313739 # number of WriteReq MSHR miss cycles 1753system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1313739 # number of WriteReq MSHR miss cycles 1754system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 407493 # number of SwapReq MSHR miss cycles 1755system.cpu1.dcache.SwapReq_mshr_miss_latency::total 407493 # number of SwapReq MSHR miss cycles |
| 1684system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2391758 # number of demand (read+write) MSHR miss cycles 1685system.cpu1.dcache.demand_mshr_miss_latency::total 2391758 # number of demand (read+write) MSHR miss cycles 1686system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2391758 # number of overall MSHR miss cycles 1687system.cpu1.dcache.overall_mshr_miss_latency::total 2391758 # number of overall MSHR miss cycles | 1756system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2390258 # number of demand (read+write) MSHR miss cycles 1757system.cpu1.dcache.demand_mshr_miss_latency::total 2390258 # number of demand (read+write) MSHR miss cycles 1758system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2390258 # number of overall MSHR miss cycles 1759system.cpu1.dcache.overall_mshr_miss_latency::total 2390258 # number of overall MSHR miss cycles |
| 1688system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003606 # mshr miss rate for ReadReq accesses 1689system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003606 # mshr miss rate for ReadReq accesses 1690system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003118 # mshr miss rate for WriteReq accesses 1691system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003118 # mshr miss rate for WriteReq accesses 1692system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.802817 # mshr miss rate for SwapReq accesses 1693system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses 1694system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003397 # mshr miss rate for demand accesses 1695system.cpu1.dcache.demand_mshr_miss_rate::total 0.003397 # mshr miss rate for demand accesses 1696system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003397 # mshr miss rate for overall accesses 1697system.cpu1.dcache.overall_mshr_miss_rate::total 0.003397 # mshr miss rate for overall accesses | 1760system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003606 # mshr miss rate for ReadReq accesses 1761system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003606 # mshr miss rate for ReadReq accesses 1762system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003118 # mshr miss rate for WriteReq accesses 1763system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003118 # mshr miss rate for WriteReq accesses 1764system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.802817 # mshr miss rate for SwapReq accesses 1765system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses 1766system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003397 # mshr miss rate for demand accesses 1767system.cpu1.dcache.demand_mshr_miss_rate::total 0.003397 # mshr miss rate for demand accesses 1768system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003397 # mshr miss rate for overall accesses 1769system.cpu1.dcache.overall_mshr_miss_rate::total 0.003397 # mshr miss rate for overall accesses |
| 1698system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6822.905063 # average ReadReq mshr miss latency 1699system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6822.905063 # average ReadReq mshr miss latency | 1770system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6813.411392 # average ReadReq mshr miss latency 1771system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6813.411392 # average ReadReq mshr miss latency |
| 1700system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12879.794118 # average WriteReq mshr miss latency 1701system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12879.794118 # average WriteReq mshr miss latency 1702system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7149 # average SwapReq mshr miss latency 1703system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7149 # average SwapReq mshr miss latency | 1772system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12879.794118 # average WriteReq mshr miss latency 1773system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12879.794118 # average WriteReq mshr miss latency 1774system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7149 # average SwapReq mshr miss latency 1775system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7149 # average SwapReq mshr miss latency |
| 1704system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9199.069231 # average overall mshr miss latency 1705system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9199.069231 # average overall mshr miss latency 1706system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9199.069231 # average overall mshr miss latency 1707system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9199.069231 # average overall mshr miss latency | 1776system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9193.300000 # average overall mshr miss latency 1777system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9193.300000 # average overall mshr miss latency 1778system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9193.300000 # average overall mshr miss latency 1779system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9193.300000 # average overall mshr miss latency |
| 1708system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1780system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1709system.cpu2.branchPred.lookups 47736 # Number of BP lookups 1710system.cpu2.branchPred.condPredicted 45029 # Number of conditional branches predicted | 1781system.cpu2.branchPred.lookups 47728 # Number of BP lookups 1782system.cpu2.branchPred.condPredicted 45021 # Number of conditional branches predicted |
| 1711system.cpu2.branchPred.condIncorrect 1300 # Number of conditional branches incorrect | 1783system.cpu2.branchPred.condIncorrect 1300 # Number of conditional branches incorrect |
| 1712system.cpu2.branchPred.BTBLookups 41576 # Number of BTB lookups 1713system.cpu2.branchPred.BTBHits 40869 # Number of BTB hits | 1784system.cpu2.branchPred.BTBLookups 41568 # Number of BTB lookups 1785system.cpu2.branchPred.BTBHits 40861 # Number of BTB hits |
| 1714system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1786system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1715system.cpu2.branchPred.BTBHitPct 98.299500 # BTB Hit Percentage | 1787system.cpu2.branchPred.BTBHitPct 98.299172 # BTB Hit Percentage |
| 1716system.cpu2.branchPred.usedRAS 682 # Number of times the RAS was used to get a target. 1717system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. | 1788system.cpu2.branchPred.usedRAS 682 # Number of times the RAS was used to get a target. 1789system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. |
| 1718system.cpu2.numCycles 177364 # number of cpu cycles simulated | 1790system.cpu2.numCycles 177276 # number of cpu cycles simulated |
| 1719system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 1720system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 1721system.cpu2.fetch.icacheStallCycles 30843 # Number of cycles fetch is stalled on an Icache miss | 1791system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 1792system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 1793system.cpu2.fetch.icacheStallCycles 30843 # Number of cycles fetch is stalled on an Icache miss |
| 1722system.cpu2.fetch.Insts 263253 # Number of instructions fetch has processed 1723system.cpu2.fetch.Branches 47736 # Number of branches that fetch encountered 1724system.cpu2.fetch.predictedBranches 41551 # Number of branches that fetch has predicted taken 1725system.cpu2.fetch.Cycles 94921 # Number of cycles fetch has run and was not squashing or blocked | 1794system.cpu2.fetch.Insts 263204 # Number of instructions fetch has processed 1795system.cpu2.fetch.Branches 47728 # Number of branches that fetch encountered 1796system.cpu2.fetch.predictedBranches 41543 # Number of branches that fetch has predicted taken 1797system.cpu2.fetch.Cycles 94904 # Number of cycles fetch has run and was not squashing or blocked |
| 1726system.cpu2.fetch.SquashCycles 3824 # Number of cycles fetch has spent squashing | 1798system.cpu2.fetch.SquashCycles 3824 # Number of cycles fetch has spent squashing |
| 1727system.cpu2.fetch.BlockedCycles 35042 # Number of cycles fetch has spent blocked | 1799system.cpu2.fetch.BlockedCycles 35041 # Number of cycles fetch has spent blocked |
| 1728system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 1800system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 1729system.cpu2.fetch.NoActiveThreadStallCycles 7755 # Number of stall cycles due to no active thread to fetch from | 1801system.cpu2.fetch.NoActiveThreadStallCycles 7749 # Number of stall cycles due to no active thread to fetch from |
| 1730system.cpu2.fetch.PendingTrapStallCycles 807 # Number of stall cycles due to pending traps 1731system.cpu2.fetch.CacheLines 21784 # Number of cache lines fetched 1732system.cpu2.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed | 1802system.cpu2.fetch.PendingTrapStallCycles 807 # Number of stall cycles due to pending traps 1803system.cpu2.fetch.CacheLines 21784 # Number of cache lines fetched 1804system.cpu2.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed |
| 1733system.cpu2.fetch.rateDist::samples 171818 # Number of instructions fetched each cycle (Total) 1734system.cpu2.fetch.rateDist::mean 1.532162 # Number of instructions fetched each cycle (Total) 1735system.cpu2.fetch.rateDist::stdev 2.088026 # Number of instructions fetched each cycle (Total) | 1805system.cpu2.fetch.rateDist::samples 171794 # Number of instructions fetched each cycle (Total) 1806system.cpu2.fetch.rateDist::mean 1.532091 # Number of instructions fetched each cycle (Total) 1807system.cpu2.fetch.rateDist::stdev 2.088011 # Number of instructions fetched each cycle (Total) |
| 1736system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1808system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1737system.cpu2.fetch.rateDist::0 76897 44.75% 44.75% # Number of instructions fetched each cycle (Total) 1738system.cpu2.fetch.rateDist::1 48842 28.43% 73.18% # Number of instructions fetched each cycle (Total) | 1809system.cpu2.fetch.rateDist::0 76890 44.76% 44.76% # Number of instructions fetched each cycle (Total) 1810system.cpu2.fetch.rateDist::1 48833 28.43% 73.18% # Number of instructions fetched each cycle (Total) |
| 1739system.cpu2.fetch.rateDist::2 7151 4.16% 77.34% # Number of instructions fetched each cycle (Total) 1740system.cpu2.fetch.rateDist::3 3183 1.85% 79.20% # Number of instructions fetched each cycle (Total) 1741system.cpu2.fetch.rateDist::4 686 0.40% 79.60% # Number of instructions fetched each cycle (Total) | 1811system.cpu2.fetch.rateDist::2 7151 4.16% 77.34% # Number of instructions fetched each cycle (Total) 1812system.cpu2.fetch.rateDist::3 3183 1.85% 79.20% # Number of instructions fetched each cycle (Total) 1813system.cpu2.fetch.rateDist::4 686 0.40% 79.60% # Number of instructions fetched each cycle (Total) |
| 1742system.cpu2.fetch.rateDist::5 29853 17.37% 96.97% # Number of instructions fetched each cycle (Total) 1743system.cpu2.fetch.rateDist::6 1160 0.68% 97.65% # Number of instructions fetched each cycle (Total) | 1814system.cpu2.fetch.rateDist::5 29845 17.37% 96.97% # Number of instructions fetched each cycle (Total) 1815system.cpu2.fetch.rateDist::6 1160 0.68% 97.64% # Number of instructions fetched each cycle (Total) |
| 1744system.cpu2.fetch.rateDist::7 777 0.45% 98.10% # Number of instructions fetched each cycle (Total) 1745system.cpu2.fetch.rateDist::8 3269 1.90% 100.00% # Number of instructions fetched each cycle (Total) 1746system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1747system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1748system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 1816system.cpu2.fetch.rateDist::7 777 0.45% 98.10% # Number of instructions fetched each cycle (Total) 1817system.cpu2.fetch.rateDist::8 3269 1.90% 100.00% # Number of instructions fetched each cycle (Total) 1818system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1819system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1820system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 1749system.cpu2.fetch.rateDist::total 171818 # Number of instructions fetched each cycle (Total) 1750system.cpu2.fetch.branchRate 0.269141 # Number of branch fetches per cycle 1751system.cpu2.fetch.rate 1.484253 # Number of inst fetches per cycle | 1821system.cpu2.fetch.rateDist::total 171794 # Number of instructions fetched each cycle (Total) 1822system.cpu2.fetch.branchRate 0.269230 # Number of branch fetches per cycle 1823system.cpu2.fetch.rate 1.484713 # Number of inst fetches per cycle |
| 1752system.cpu2.decode.IdleCycles 36742 # Number of cycles decode is idle | 1824system.cpu2.decode.IdleCycles 36742 # Number of cycles decode is idle |
| 1753system.cpu2.decode.BlockedCycles 30807 # Number of cycles decode is blocked 1754system.cpu2.decode.RunCycles 88098 # Number of cycles decode is running | 1825system.cpu2.decode.BlockedCycles 30806 # Number of cycles decode is blocked 1826system.cpu2.decode.RunCycles 88081 # Number of cycles decode is running |
| 1755system.cpu2.decode.UnblockCycles 5970 # Number of cycles decode is unblocking 1756system.cpu2.decode.SquashCycles 2446 # Number of cycles decode is squashing | 1827system.cpu2.decode.UnblockCycles 5970 # Number of cycles decode is unblocking 1828system.cpu2.decode.SquashCycles 2446 # Number of cycles decode is squashing |
| 1757system.cpu2.decode.DecodedInsts 259780 # Number of instructions handled by decode | 1829system.cpu2.decode.DecodedInsts 259729 # Number of instructions handled by decode |
| 1758system.cpu2.rename.SquashCycles 2446 # Number of cycles rename is squashing 1759system.cpu2.rename.IdleCycles 37466 # Number of cycles rename is idle | 1830system.cpu2.rename.SquashCycles 2446 # Number of cycles rename is squashing 1831system.cpu2.rename.IdleCycles 37466 # Number of cycles rename is idle |
| 1760system.cpu2.rename.BlockCycles 17719 # Number of cycles rename is blocking | 1832system.cpu2.rename.BlockCycles 17718 # Number of cycles rename is blocking |
| 1761system.cpu2.rename.serializeStallCycles 12322 # count of cycles rename stalled for serializing inst | 1833system.cpu2.rename.serializeStallCycles 12322 # count of cycles rename stalled for serializing inst |
| 1762system.cpu2.rename.RunCycles 82368 # Number of cycles rename is running | 1834system.cpu2.rename.RunCycles 82351 # Number of cycles rename is running |
| 1763system.cpu2.rename.UnblockCycles 11742 # Number of cycles rename is unblocking | 1835system.cpu2.rename.UnblockCycles 11742 # Number of cycles rename is unblocking |
| 1764system.cpu2.rename.RenamedInsts 257506 # Number of instructions processed by rename | 1836system.cpu2.rename.RenamedInsts 257457 # Number of instructions processed by rename |
| 1765system.cpu2.rename.LSQFullEvents 21 # Number of times rename has blocked due to LSQ full | 1837system.cpu2.rename.LSQFullEvents 21 # Number of times rename has blocked due to LSQ full |
| 1766system.cpu2.rename.RenamedOperands 179566 # Number of destination operands rename has renamed 1767system.cpu2.rename.RenameLookups 487666 # Number of register rename lookups that rename has made 1768system.cpu2.rename.int_rename_lookups 380584 # Number of integer rename lookups 1769system.cpu2.rename.CommittedMaps 166435 # Number of HB maps that are committed | 1838system.cpu2.rename.RenamedOperands 179534 # Number of destination operands rename has renamed 1839system.cpu2.rename.RenameLookups 487570 # Number of register rename lookups that rename has made 1840system.cpu2.rename.int_rename_lookups 380512 # Number of integer rename lookups 1841system.cpu2.rename.CommittedMaps 166403 # Number of HB maps that are committed |
| 1770system.cpu2.rename.UndoneMaps 13131 # Number of HB maps that are undone due to squashing 1771system.cpu2.rename.serializingInsts 1114 # count of serializing insts renamed 1772system.cpu2.rename.tempSerializingInsts 1238 # count of temporary serializing insts renamed 1773system.cpu2.rename.skidInsts 14439 # count of insts added to the skid buffer | 1842system.cpu2.rename.UndoneMaps 13131 # Number of HB maps that are undone due to squashing 1843system.cpu2.rename.serializingInsts 1114 # count of serializing insts renamed 1844system.cpu2.rename.tempSerializingInsts 1238 # count of temporary serializing insts renamed 1845system.cpu2.rename.skidInsts 14439 # count of insts added to the skid buffer |
| 1774system.cpu2.memDep0.insertedLoads 71199 # Number of loads inserted to the mem dependence unit. 1775system.cpu2.memDep0.insertedStores 33061 # Number of stores inserted to the mem dependence unit. 1776system.cpu2.memDep0.conflictingLoads 34327 # Number of conflicting loads. 1777system.cpu2.memDep0.conflictingStores 28016 # Number of conflicting stores. 1778system.cpu2.iq.iqInstsAdded 212074 # Number of instructions added to the IQ (excludes non-spec) | 1846system.cpu2.memDep0.insertedLoads 71183 # Number of loads inserted to the mem dependence unit. 1847system.cpu2.memDep0.insertedStores 33053 # Number of stores inserted to the mem dependence unit. 1848system.cpu2.memDep0.conflictingLoads 34319 # Number of conflicting loads. 1849system.cpu2.memDep0.conflictingStores 28008 # Number of conflicting stores. 1850system.cpu2.iq.iqInstsAdded 212034 # Number of instructions added to the IQ (excludes non-spec) |
| 1779system.cpu2.iq.iqNonSpecInstsAdded 7370 # Number of non-speculative instructions added to the IQ | 1851system.cpu2.iq.iqNonSpecInstsAdded 7370 # Number of non-speculative instructions added to the IQ |
| 1780system.cpu2.iq.iqInstsIssued 214906 # Number of instructions issued | 1852system.cpu2.iq.iqInstsIssued 214866 # Number of instructions issued |
| 1781system.cpu2.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued 1782system.cpu2.iq.iqSquashedInstsExamined 11214 # Number of squashed instructions iterated over during squash; mainly for profiling 1783system.cpu2.iq.iqSquashedOperandsExamined 11199 # Number of squashed operands that are examined and possibly removed from graph 1784system.cpu2.iq.iqSquashedNonSpecRemoved 648 # Number of squashed non-spec instructions that were removed | 1853system.cpu2.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued 1854system.cpu2.iq.iqSquashedInstsExamined 11214 # Number of squashed instructions iterated over during squash; mainly for profiling 1855system.cpu2.iq.iqSquashedOperandsExamined 11199 # Number of squashed operands that are examined and possibly removed from graph 1856system.cpu2.iq.iqSquashedNonSpecRemoved 648 # Number of squashed non-spec instructions that were removed |
| 1785system.cpu2.iq.issued_per_cycle::samples 171818 # Number of insts issued each cycle 1786system.cpu2.iq.issued_per_cycle::mean 1.250777 # Number of insts issued each cycle 1787system.cpu2.iq.issued_per_cycle::stdev 1.303706 # Number of insts issued each cycle | 1857system.cpu2.iq.issued_per_cycle::samples 171794 # Number of insts issued each cycle 1858system.cpu2.iq.issued_per_cycle::mean 1.250719 # Number of insts issued each cycle 1859system.cpu2.iq.issued_per_cycle::stdev 1.303691 # Number of insts issued each cycle |
| 1788system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1860system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1789system.cpu2.iq.issued_per_cycle::0 74494 43.36% 43.36% # Number of insts issued each cycle 1790system.cpu2.iq.issued_per_cycle::1 25338 14.75% 58.10% # Number of insts issued each cycle 1791system.cpu2.iq.issued_per_cycle::2 33284 19.37% 77.48% # Number of insts issued each cycle 1792system.cpu2.iq.issued_per_cycle::3 33913 19.74% 97.21% # Number of insts issued each cycle 1793system.cpu2.iq.issued_per_cycle::4 3241 1.89% 99.10% # Number of insts issued each cycle 1794system.cpu2.iq.issued_per_cycle::5 1161 0.68% 99.77% # Number of insts issued each cycle | 1861system.cpu2.iq.issued_per_cycle::0 74486 43.36% 43.36% # Number of insts issued each cycle 1862system.cpu2.iq.issued_per_cycle::1 25336 14.75% 58.11% # Number of insts issued each cycle 1863system.cpu2.iq.issued_per_cycle::2 33280 19.37% 77.48% # Number of insts issued each cycle 1864system.cpu2.iq.issued_per_cycle::3 33902 19.73% 97.21% # Number of insts issued each cycle 1865system.cpu2.iq.issued_per_cycle::4 3243 1.89% 99.10% # Number of insts issued each cycle 1866system.cpu2.iq.issued_per_cycle::5 1160 0.68% 99.77% # Number of insts issued each cycle |
| 1795system.cpu2.iq.issued_per_cycle::6 274 0.16% 99.93% # Number of insts issued each cycle 1796system.cpu2.iq.issued_per_cycle::7 56 0.03% 99.97% # Number of insts issued each cycle 1797system.cpu2.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle 1798system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1799system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1800system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 1867system.cpu2.iq.issued_per_cycle::6 274 0.16% 99.93% # Number of insts issued each cycle 1868system.cpu2.iq.issued_per_cycle::7 56 0.03% 99.97% # Number of insts issued each cycle 1869system.cpu2.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle 1870system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1871system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1872system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 1801system.cpu2.iq.issued_per_cycle::total 171818 # Number of insts issued each cycle | 1873system.cpu2.iq.issued_per_cycle::total 171794 # Number of insts issued each cycle |
| 1802system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1803system.cpu2.iq.fu_full::IntAlu 17 6.18% 6.18% # attempts to use FU when none available 1804system.cpu2.iq.fu_full::IntMult 0 0.00% 6.18% # attempts to use FU when none available 1805system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.18% # attempts to use FU when none available 1806system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.18% # attempts to use FU when none available 1807system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.18% # attempts to use FU when none available 1808system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.18% # attempts to use FU when none available 1809system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.18% # attempts to use FU when none available --- 19 unchanged lines hidden (view full) --- 1829system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.18% # attempts to use FU when none available 1830system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.18% # attempts to use FU when none available 1831system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.18% # attempts to use FU when none available 1832system.cpu2.iq.fu_full::MemRead 48 17.45% 23.64% # attempts to use FU when none available 1833system.cpu2.iq.fu_full::MemWrite 210 76.36% 100.00% # attempts to use FU when none available 1834system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1835system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1836system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 1874system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1875system.cpu2.iq.fu_full::IntAlu 17 6.18% 6.18% # attempts to use FU when none available 1876system.cpu2.iq.fu_full::IntMult 0 0.00% 6.18% # attempts to use FU when none available 1877system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.18% # attempts to use FU when none available 1878system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.18% # attempts to use FU when none available 1879system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.18% # attempts to use FU when none available 1880system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.18% # attempts to use FU when none available 1881system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.18% # attempts to use FU when none available --- 19 unchanged lines hidden (view full) --- 1901system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.18% # attempts to use FU when none available 1902system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.18% # attempts to use FU when none available 1903system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.18% # attempts to use FU when none available 1904system.cpu2.iq.fu_full::MemRead 48 17.45% 23.64% # attempts to use FU when none available 1905system.cpu2.iq.fu_full::MemWrite 210 76.36% 100.00% # attempts to use FU when none available 1906system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1907system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1908system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 1837system.cpu2.iq.FU_type_0::IntAlu 106166 49.40% 49.40% # Type of FU issued | 1909system.cpu2.iq.FU_type_0::IntAlu 106150 49.40% 49.40% # Type of FU issued |
| 1838system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.40% # Type of FU issued 1839system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.40% # Type of FU issued 1840system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.40% # Type of FU issued 1841system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.40% # Type of FU issued 1842system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.40% # Type of FU issued 1843system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.40% # Type of FU issued 1844system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.40% # Type of FU issued 1845system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.40% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 1858system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.40% # Type of FU issued 1859system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.40% # Type of FU issued 1860system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.40% # Type of FU issued 1861system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.40% # Type of FU issued 1862system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.40% # Type of FU issued 1863system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.40% # Type of FU issued 1864system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.40% # Type of FU issued 1865system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.40% # Type of FU issued | 1910system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.40% # Type of FU issued 1911system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.40% # Type of FU issued 1912system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.40% # Type of FU issued 1913system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.40% # Type of FU issued 1914system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.40% # Type of FU issued 1915system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.40% # Type of FU issued 1916system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.40% # Type of FU issued 1917system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.40% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 1930system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.40% # Type of FU issued 1931system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.40% # Type of FU issued 1932system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.40% # Type of FU issued 1933system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.40% # Type of FU issued 1934system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.40% # Type of FU issued 1935system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.40% # Type of FU issued 1936system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.40% # Type of FU issued 1937system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.40% # Type of FU issued |
| 1866system.cpu2.iq.FU_type_0::MemRead 76377 35.54% 84.94% # Type of FU issued 1867system.cpu2.iq.FU_type_0::MemWrite 32363 15.06% 100.00% # Type of FU issued | 1938system.cpu2.iq.FU_type_0::MemRead 76361 35.54% 84.94% # Type of FU issued 1939system.cpu2.iq.FU_type_0::MemWrite 32355 15.06% 100.00% # Type of FU issued |
| 1868system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1869system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1940system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1941system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 1870system.cpu2.iq.FU_type_0::total 214906 # Type of FU issued 1871system.cpu2.iq.rate 1.211666 # Inst issue rate | 1942system.cpu2.iq.FU_type_0::total 214866 # Type of FU issued 1943system.cpu2.iq.rate 1.212042 # Inst issue rate |
| 1872system.cpu2.iq.fu_busy_cnt 275 # FU busy when requested 1873system.cpu2.iq.fu_busy_rate 0.001280 # FU busy rate (busy events/executed inst) | 1944system.cpu2.iq.fu_busy_cnt 275 # FU busy when requested 1945system.cpu2.iq.fu_busy_rate 0.001280 # FU busy rate (busy events/executed inst) |
| 1874system.cpu2.iq.int_inst_queue_reads 602011 # Number of integer instruction queue reads 1875system.cpu2.iq.int_inst_queue_writes 230706 # Number of integer instruction queue writes 1876system.cpu2.iq.int_inst_queue_wakeup_accesses 213087 # Number of integer instruction queue wakeup accesses | 1946system.cpu2.iq.int_inst_queue_reads 601907 # Number of integer instruction queue reads 1947system.cpu2.iq.int_inst_queue_writes 230666 # Number of integer instruction queue writes 1948system.cpu2.iq.int_inst_queue_wakeup_accesses 213047 # Number of integer instruction queue wakeup accesses |
| 1877system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1878system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1879system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 1949system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1950system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1951system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 1880system.cpu2.iq.int_alu_accesses 215181 # Number of integer alu accesses | 1952system.cpu2.iq.int_alu_accesses 215141 # Number of integer alu accesses |
| 1881system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses | 1953system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses |
| 1882system.cpu2.iew.lsq.thread0.forwLoads 27728 # Number of loads that had data forwarded from stores | 1954system.cpu2.iew.lsq.thread0.forwLoads 27720 # Number of loads that had data forwarded from stores |
| 1883system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1884system.cpu2.iew.lsq.thread0.squashedLoads 2543 # Number of loads squashed 1885system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 1886system.cpu2.iew.lsq.thread0.memOrderViolation 48 # Number of memory ordering violations 1887system.cpu2.iew.lsq.thread0.squashedStores 1469 # Number of stores squashed 1888system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1889system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1890system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1891system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1892system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1893system.cpu2.iew.iewSquashCycles 2446 # Number of cycles IEW is squashing | 1955system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1956system.cpu2.iew.lsq.thread0.squashedLoads 2543 # Number of loads squashed 1957system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 1958system.cpu2.iew.lsq.thread0.memOrderViolation 48 # Number of memory ordering violations 1959system.cpu2.iew.lsq.thread0.squashedStores 1469 # Number of stores squashed 1960system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1961system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1962system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1963system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1964system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1965system.cpu2.iew.iewSquashCycles 2446 # Number of cycles IEW is squashing |
| 1894system.cpu2.iew.iewBlockCycles 917 # Number of cycles IEW is blocking | 1966system.cpu2.iew.iewBlockCycles 916 # Number of cycles IEW is blocking |
| 1895system.cpu2.iew.iewUnblockCycles 52 # Number of cycles IEW is unblocking | 1967system.cpu2.iew.iewUnblockCycles 52 # Number of cycles IEW is unblocking |
| 1896system.cpu2.iew.iewDispatchedInsts 254656 # Number of instructions dispatched to IQ | 1968system.cpu2.iew.iewDispatchedInsts 254607 # Number of instructions dispatched to IQ |
| 1897system.cpu2.iew.iewDispSquashedInsts 365 # Number of squashed instructions skipped by dispatch | 1969system.cpu2.iew.iewDispSquashedInsts 365 # Number of squashed instructions skipped by dispatch |
| 1898system.cpu2.iew.iewDispLoadInsts 71199 # Number of dispatched load instructions 1899system.cpu2.iew.iewDispStoreInsts 33061 # Number of dispatched store instructions | 1970system.cpu2.iew.iewDispLoadInsts 71183 # Number of dispatched load instructions 1971system.cpu2.iew.iewDispStoreInsts 33053 # Number of dispatched store instructions |
| 1900system.cpu2.iew.iewDispNonSpecInsts 1074 # Number of dispatched non-speculative instructions 1901system.cpu2.iew.iewIQFullEvents 52 # Number of times the IQ has become full, causing a stall 1902system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1903system.cpu2.iew.memOrderViolationEvents 48 # Number of memory order violations 1904system.cpu2.iew.predictedTakenIncorrect 458 # Number of branches that were predicted taken incorrectly 1905system.cpu2.iew.predictedNotTakenIncorrect 967 # Number of branches that were predicted not taken incorrectly 1906system.cpu2.iew.branchMispredicts 1425 # Number of branch mispredicts detected at execute | 1972system.cpu2.iew.iewDispNonSpecInsts 1074 # Number of dispatched non-speculative instructions 1973system.cpu2.iew.iewIQFullEvents 52 # Number of times the IQ has become full, causing a stall 1974system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1975system.cpu2.iew.memOrderViolationEvents 48 # Number of memory order violations 1976system.cpu2.iew.predictedTakenIncorrect 458 # Number of branches that were predicted taken incorrectly 1977system.cpu2.iew.predictedNotTakenIncorrect 967 # Number of branches that were predicted not taken incorrectly 1978system.cpu2.iew.branchMispredicts 1425 # Number of branch mispredicts detected at execute |
| 1907system.cpu2.iew.iewExecutedInsts 213756 # Number of executed instructions 1908system.cpu2.iew.iewExecLoadInsts 70098 # Number of load instructions executed | 1979system.cpu2.iew.iewExecutedInsts 213716 # Number of executed instructions 1980system.cpu2.iew.iewExecLoadInsts 70082 # Number of load instructions executed |
| 1909system.cpu2.iew.iewExecSquashedInsts 1150 # Number of squashed instructions skipped in execute 1910system.cpu2.iew.exec_swp 0 # number of swp insts executed | 1981system.cpu2.iew.iewExecSquashedInsts 1150 # Number of squashed instructions skipped in execute 1982system.cpu2.iew.exec_swp 0 # number of swp insts executed |
| 1911system.cpu2.iew.exec_nop 35212 # number of nop insts executed 1912system.cpu2.iew.exec_refs 102378 # number of memory reference insts executed 1913system.cpu2.iew.exec_branches 44395 # Number of branches executed 1914system.cpu2.iew.exec_stores 32280 # Number of stores executed 1915system.cpu2.iew.exec_rate 1.205183 # Inst execution rate 1916system.cpu2.iew.wb_sent 213374 # cumulative count of insts sent to commit 1917system.cpu2.iew.wb_count 213087 # cumulative count of insts written-back 1918system.cpu2.iew.wb_producers 119148 # num instructions producing a value 1919system.cpu2.iew.wb_consumers 123853 # num instructions consuming a value | 1983system.cpu2.iew.exec_nop 35203 # number of nop insts executed 1984system.cpu2.iew.exec_refs 102354 # number of memory reference insts executed 1985system.cpu2.iew.exec_branches 44387 # Number of branches executed 1986system.cpu2.iew.exec_stores 32272 # Number of stores executed 1987system.cpu2.iew.exec_rate 1.205555 # Inst execution rate 1988system.cpu2.iew.wb_sent 213334 # cumulative count of insts sent to commit 1989system.cpu2.iew.wb_count 213047 # cumulative count of insts written-back 1990system.cpu2.iew.wb_producers 119124 # num instructions producing a value 1991system.cpu2.iew.wb_consumers 123829 # num instructions consuming a value |
| 1920system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1992system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 1921system.cpu2.iew.wb_rate 1.201411 # insts written-back per cycle 1922system.cpu2.iew.wb_fanout 0.962011 # average fanout of values written-back | 1993system.cpu2.iew.wb_rate 1.201781 # insts written-back per cycle 1994system.cpu2.iew.wb_fanout 0.962004 # average fanout of values written-back |
| 1923system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 1995system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 1924system.cpu2.commit.commitSquashedInsts 12898 # The number of squashed insts skipped by commit | 1996system.cpu2.commit.commitSquashedInsts 12897 # The number of squashed insts skipped by commit |
| 1925system.cpu2.commit.commitNonSpecStalls 6722 # The number of times commit has been forced to stall to communicate backwards 1926system.cpu2.commit.branchMispredicts 1300 # The number of times a branch was mispredicted | 1997system.cpu2.commit.commitNonSpecStalls 6722 # The number of times commit has been forced to stall to communicate backwards 1998system.cpu2.commit.branchMispredicts 1300 # The number of times a branch was mispredicted |
| 1927system.cpu2.commit.committed_per_cycle::samples 161617 # Number of insts commited each cycle 1928system.cpu2.commit.committed_per_cycle::mean 1.495857 # Number of insts commited each cycle 1929system.cpu2.commit.committed_per_cycle::stdev 1.966536 # Number of insts commited each cycle | 1999system.cpu2.commit.committed_per_cycle::samples 161599 # Number of insts commited each cycle 2000system.cpu2.commit.committed_per_cycle::mean 1.495727 # Number of insts commited each cycle 2001system.cpu2.commit.committed_per_cycle::stdev 1.966465 # Number of insts commited each cycle |
| 1930system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 2002system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 1931system.cpu2.commit.committed_per_cycle::0 73208 45.30% 45.30% # Number of insts commited each cycle 1932system.cpu2.commit.committed_per_cycle::1 42532 26.32% 71.61% # Number of insts commited each cycle | 2003system.cpu2.commit.committed_per_cycle::0 73205 45.30% 45.30% # Number of insts commited each cycle 2004system.cpu2.commit.committed_per_cycle::1 42525 26.32% 71.62% # Number of insts commited each cycle |
| 1933system.cpu2.commit.committed_per_cycle::2 6095 3.77% 75.39% # Number of insts commited each cycle | 2005system.cpu2.commit.committed_per_cycle::2 6095 3.77% 75.39% # Number of insts commited each cycle |
| 1934system.cpu2.commit.committed_per_cycle::3 7628 4.72% 80.10% # Number of insts commited each cycle | 2006system.cpu2.commit.committed_per_cycle::3 7628 4.72% 80.11% # Number of insts commited each cycle |
| 1935system.cpu2.commit.committed_per_cycle::4 1558 0.96% 81.07% # Number of insts commited each cycle | 2007system.cpu2.commit.committed_per_cycle::4 1558 0.96% 81.07% # Number of insts commited each cycle |
| 1936system.cpu2.commit.committed_per_cycle::5 28303 17.51% 98.58% # Number of insts commited each cycle 1937system.cpu2.commit.committed_per_cycle::6 470 0.29% 98.87% # Number of insts commited each cycle | 2008system.cpu2.commit.committed_per_cycle::5 28296 17.51% 98.58% # Number of insts commited each cycle 2009system.cpu2.commit.committed_per_cycle::6 469 0.29% 98.87% # Number of insts commited each cycle |
| 1938system.cpu2.commit.committed_per_cycle::7 1001 0.62% 99.49% # Number of insts commited each cycle 1939system.cpu2.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle 1940system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1941system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1942system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 2010system.cpu2.commit.committed_per_cycle::7 1001 0.62% 99.49% # Number of insts commited each cycle 2011system.cpu2.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle 2012system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2013system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2014system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 1943system.cpu2.commit.committed_per_cycle::total 161617 # Number of insts commited each cycle 1944system.cpu2.commit.committedInsts 241756 # Number of instructions committed 1945system.cpu2.commit.committedOps 241756 # Number of ops (including micro ops) committed | 2015system.cpu2.commit.committed_per_cycle::total 161599 # Number of insts commited each cycle 2016system.cpu2.commit.committedInsts 241708 # Number of instructions committed 2017system.cpu2.commit.committedOps 241708 # Number of ops (including micro ops) committed |
| 1946system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed | 2018system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed |
| 1947system.cpu2.commit.refs 100248 # Number of memory references committed 1948system.cpu2.commit.loads 68656 # Number of loads committed | 2019system.cpu2.commit.refs 100224 # Number of memory references committed 2020system.cpu2.commit.loads 68640 # Number of loads committed |
| 1949system.cpu2.commit.membars 6003 # Number of memory barriers committed | 2021system.cpu2.commit.membars 6003 # Number of memory barriers committed |
| 1950system.cpu2.commit.branches 43556 # Number of branches committed | 2022system.cpu2.commit.branches 43548 # Number of branches committed |
| 1951system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. | 2023system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. |
| 1952system.cpu2.commit.int_insts 165922 # Number of committed integer instructions. | 2024system.cpu2.commit.int_insts 165890 # Number of committed integer instructions. |
| 1953system.cpu2.commit.function_calls 322 # Number of function calls committed. | 2025system.cpu2.commit.function_calls 322 # Number of function calls committed. |
| 2026system.cpu2.commit.op_class_0::No_OpClass 34333 14.20% 14.20% # Class of committed instruction 2027system.cpu2.commit.op_class_0::IntAlu 101148 41.85% 56.05% # Class of committed instruction 2028system.cpu2.commit.op_class_0::IntMult 0 0.00% 56.05% # Class of committed instruction 2029system.cpu2.commit.op_class_0::IntDiv 0 0.00% 56.05% # Class of committed instruction 2030system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 56.05% # Class of committed instruction 2031system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 56.05% # Class of committed instruction 2032system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 56.05% # Class of committed instruction 2033system.cpu2.commit.op_class_0::FloatMult 0 0.00% 56.05% # Class of committed instruction 2034system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 56.05% # Class of committed instruction 2035system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 56.05% # Class of committed instruction 2036system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 56.05% # Class of committed instruction 2037system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 56.05% # Class of committed instruction 2038system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 56.05% # Class of committed instruction 2039system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 56.05% # Class of committed instruction 2040system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 56.05% # Class of committed instruction 2041system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 56.05% # Class of committed instruction 2042system.cpu2.commit.op_class_0::SimdMult 0 0.00% 56.05% # Class of committed instruction 2043system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 56.05% # Class of committed instruction 2044system.cpu2.commit.op_class_0::SimdShift 0 0.00% 56.05% # Class of committed instruction 2045system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 56.05% # Class of committed instruction 2046system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 56.05% # Class of committed instruction 2047system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 56.05% # Class of committed instruction 2048system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 56.05% # Class of committed instruction 2049system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 56.05% # Class of committed instruction 2050system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 56.05% # Class of committed instruction 2051system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 56.05% # Class of committed instruction 2052system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 56.05% # Class of committed instruction 2053system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 56.05% # Class of committed instruction 2054system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.05% # Class of committed instruction 2055system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.05% # Class of committed instruction 2056system.cpu2.commit.op_class_0::MemRead 74643 30.88% 86.93% # Class of committed instruction 2057system.cpu2.commit.op_class_0::MemWrite 31584 13.07% 100.00% # Class of committed instruction 2058system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2059system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2060system.cpu2.commit.op_class_0::total 241708 # Class of committed instruction |
|
| 1954system.cpu2.commit.bw_lim_events 822 # number cycles where commit BW limit reached 1955system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits | 2061system.cpu2.commit.bw_lim_events 822 # number cycles where commit BW limit reached 2062system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 1956system.cpu2.rob.rob_reads 414862 # The number of ROB reads 1957system.cpu2.rob.rob_writes 511759 # The number of ROB writes | 2063system.cpu2.rob.rob_reads 414795 # The number of ROB reads 2064system.cpu2.rob.rob_writes 511661 # The number of ROB writes |
| 1958system.cpu2.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself | 2065system.cpu2.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 1959system.cpu2.idleCycles 5546 # Total number of cycles that the CPU has spent unscheduled due to idling 1960system.cpu2.quiesceCycles 44546 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1961system.cpu2.committedInsts 201412 # Number of Instructions Simulated 1962system.cpu2.committedOps 201412 # Number of Ops (including micro ops) Simulated 1963system.cpu2.committedInsts_total 201412 # Number of Instructions Simulated 1964system.cpu2.cpi 0.880603 # CPI: Cycles Per Instruction 1965system.cpu2.cpi_total 0.880603 # CPI: Total CPI of All Threads 1966system.cpu2.ipc 1.135586 # IPC: Instructions Per Cycle 1967system.cpu2.ipc_total 1.135586 # IPC: Total IPC of All Threads 1968system.cpu2.int_regfile_reads 365854 # number of integer regfile reads 1969system.cpu2.int_regfile_writes 171387 # number of integer regfile writes | 2066system.cpu2.idleCycles 5482 # Total number of cycles that the CPU has spent unscheduled due to idling 2067system.cpu2.quiesceCycles 44468 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2068system.cpu2.committedInsts 201372 # Number of Instructions Simulated 2069system.cpu2.committedOps 201372 # Number of Ops (including micro ops) Simulated 2070system.cpu2.committedInsts_total 201372 # Number of Instructions Simulated 2071system.cpu2.cpi 0.880341 # CPI: Cycles Per Instruction 2072system.cpu2.cpi_total 0.880341 # CPI: Total CPI of All Threads 2073system.cpu2.ipc 1.135924 # IPC: Instructions Per Cycle 2074system.cpu2.ipc_total 1.135924 # IPC: Total IPC of All Threads 2075system.cpu2.int_regfile_reads 365782 # number of integer regfile reads 2076system.cpu2.int_regfile_writes 171355 # number of integer regfile writes |
| 1970system.cpu2.fp_regfile_writes 64 # number of floating regfile writes | 2077system.cpu2.fp_regfile_writes 64 # number of floating regfile writes |
| 1971system.cpu2.misc_regfile_reads 103940 # number of misc regfile reads | 2078system.cpu2.misc_regfile_reads 103916 # number of misc regfile reads |
| 1972system.cpu2.misc_regfile_writes 648 # number of misc regfile writes 1973system.cpu2.icache.tags.replacements 317 # number of replacements | 2079system.cpu2.misc_regfile_writes 648 # number of misc regfile writes 2080system.cpu2.icache.tags.replacements 317 # number of replacements |
| 1974system.cpu2.icache.tags.tagsinuse 82.194037 # Cycle average of tags in use | 2081system.cpu2.icache.tags.tagsinuse 82.236907 # Cycle average of tags in use |
| 1975system.cpu2.icache.tags.total_refs 21297 # Total number of references to valid blocks. 1976system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks. 1977system.cpu2.icache.tags.avg_refs 50.110588 # Average number of references to valid blocks. 1978system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2082system.cpu2.icache.tags.total_refs 21297 # Total number of references to valid blocks. 2083system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks. 2084system.cpu2.icache.tags.avg_refs 50.110588 # Average number of references to valid blocks. 2085system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1979system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.194037 # Average occupied blocks per requestor 1980system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160535 # Average percentage of cache occupancy 1981system.cpu2.icache.tags.occ_percent::total 0.160535 # Average percentage of cache occupancy | 2086system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.236907 # Average occupied blocks per requestor 2087system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160619 # Average percentage of cache occupancy 2088system.cpu2.icache.tags.occ_percent::total 0.160619 # Average percentage of cache occupancy |
| 1982system.cpu2.icache.tags.occ_task_id_blocks::1024 108 # Occupied blocks per task id 1983system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 1984system.cpu2.icache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id 1985system.cpu2.icache.tags.occ_task_id_percent::1024 0.210938 # Percentage of cache occupancy per task id 1986system.cpu2.icache.tags.tag_accesses 22209 # Number of tag accesses 1987system.cpu2.icache.tags.data_accesses 22209 # Number of data accesses 1988system.cpu2.icache.ReadReq_hits::cpu2.inst 21297 # number of ReadReq hits 1989system.cpu2.icache.ReadReq_hits::total 21297 # number of ReadReq hits 1990system.cpu2.icache.demand_hits::cpu2.inst 21297 # number of demand (read+write) hits 1991system.cpu2.icache.demand_hits::total 21297 # number of demand (read+write) hits 1992system.cpu2.icache.overall_hits::cpu2.inst 21297 # number of overall hits 1993system.cpu2.icache.overall_hits::total 21297 # number of overall hits 1994system.cpu2.icache.ReadReq_misses::cpu2.inst 487 # number of ReadReq misses 1995system.cpu2.icache.ReadReq_misses::total 487 # number of ReadReq misses 1996system.cpu2.icache.demand_misses::cpu2.inst 487 # number of demand (read+write) misses 1997system.cpu2.icache.demand_misses::total 487 # number of demand (read+write) misses 1998system.cpu2.icache.overall_misses::cpu2.inst 487 # number of overall misses 1999system.cpu2.icache.overall_misses::total 487 # number of overall misses | 2089system.cpu2.icache.tags.occ_task_id_blocks::1024 108 # Occupied blocks per task id 2090system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 2091system.cpu2.icache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id 2092system.cpu2.icache.tags.occ_task_id_percent::1024 0.210938 # Percentage of cache occupancy per task id 2093system.cpu2.icache.tags.tag_accesses 22209 # Number of tag accesses 2094system.cpu2.icache.tags.data_accesses 22209 # Number of data accesses 2095system.cpu2.icache.ReadReq_hits::cpu2.inst 21297 # number of ReadReq hits 2096system.cpu2.icache.ReadReq_hits::total 21297 # number of ReadReq hits 2097system.cpu2.icache.demand_hits::cpu2.inst 21297 # number of demand (read+write) hits 2098system.cpu2.icache.demand_hits::total 21297 # number of demand (read+write) hits 2099system.cpu2.icache.overall_hits::cpu2.inst 21297 # number of overall hits 2100system.cpu2.icache.overall_hits::total 21297 # number of overall hits 2101system.cpu2.icache.ReadReq_misses::cpu2.inst 487 # number of ReadReq misses 2102system.cpu2.icache.ReadReq_misses::total 487 # number of ReadReq misses 2103system.cpu2.icache.demand_misses::cpu2.inst 487 # number of demand (read+write) misses 2104system.cpu2.icache.demand_misses::total 487 # number of demand (read+write) misses 2105system.cpu2.icache.overall_misses::cpu2.inst 487 # number of overall misses 2106system.cpu2.icache.overall_misses::total 487 # number of overall misses |
| 2000system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11553239 # number of ReadReq miss cycles 2001system.cpu2.icache.ReadReq_miss_latency::total 11553239 # number of ReadReq miss cycles 2002system.cpu2.icache.demand_miss_latency::cpu2.inst 11553239 # number of demand (read+write) miss cycles 2003system.cpu2.icache.demand_miss_latency::total 11553239 # number of demand (read+write) miss cycles 2004system.cpu2.icache.overall_miss_latency::cpu2.inst 11553239 # number of overall miss cycles 2005system.cpu2.icache.overall_miss_latency::total 11553239 # number of overall miss cycles | 2107system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11521239 # number of ReadReq miss cycles 2108system.cpu2.icache.ReadReq_miss_latency::total 11521239 # number of ReadReq miss cycles 2109system.cpu2.icache.demand_miss_latency::cpu2.inst 11521239 # number of demand (read+write) miss cycles 2110system.cpu2.icache.demand_miss_latency::total 11521239 # number of demand (read+write) miss cycles 2111system.cpu2.icache.overall_miss_latency::cpu2.inst 11521239 # number of overall miss cycles 2112system.cpu2.icache.overall_miss_latency::total 11521239 # number of overall miss cycles |
| 2006system.cpu2.icache.ReadReq_accesses::cpu2.inst 21784 # number of ReadReq accesses(hits+misses) 2007system.cpu2.icache.ReadReq_accesses::total 21784 # number of ReadReq accesses(hits+misses) 2008system.cpu2.icache.demand_accesses::cpu2.inst 21784 # number of demand (read+write) accesses 2009system.cpu2.icache.demand_accesses::total 21784 # number of demand (read+write) accesses 2010system.cpu2.icache.overall_accesses::cpu2.inst 21784 # number of overall (read+write) accesses 2011system.cpu2.icache.overall_accesses::total 21784 # number of overall (read+write) accesses 2012system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.022356 # miss rate for ReadReq accesses 2013system.cpu2.icache.ReadReq_miss_rate::total 0.022356 # miss rate for ReadReq accesses 2014system.cpu2.icache.demand_miss_rate::cpu2.inst 0.022356 # miss rate for demand accesses 2015system.cpu2.icache.demand_miss_rate::total 0.022356 # miss rate for demand accesses 2016system.cpu2.icache.overall_miss_rate::cpu2.inst 0.022356 # miss rate for overall accesses 2017system.cpu2.icache.overall_miss_rate::total 0.022356 # miss rate for overall accesses | 2113system.cpu2.icache.ReadReq_accesses::cpu2.inst 21784 # number of ReadReq accesses(hits+misses) 2114system.cpu2.icache.ReadReq_accesses::total 21784 # number of ReadReq accesses(hits+misses) 2115system.cpu2.icache.demand_accesses::cpu2.inst 21784 # number of demand (read+write) accesses 2116system.cpu2.icache.demand_accesses::total 21784 # number of demand (read+write) accesses 2117system.cpu2.icache.overall_accesses::cpu2.inst 21784 # number of overall (read+write) accesses 2118system.cpu2.icache.overall_accesses::total 21784 # number of overall (read+write) accesses 2119system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.022356 # miss rate for ReadReq accesses 2120system.cpu2.icache.ReadReq_miss_rate::total 0.022356 # miss rate for ReadReq accesses 2121system.cpu2.icache.demand_miss_rate::cpu2.inst 0.022356 # miss rate for demand accesses 2122system.cpu2.icache.demand_miss_rate::total 0.022356 # miss rate for demand accesses 2123system.cpu2.icache.overall_miss_rate::cpu2.inst 0.022356 # miss rate for overall accesses 2124system.cpu2.icache.overall_miss_rate::total 0.022356 # miss rate for overall accesses |
| 2018system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23723.283368 # average ReadReq miss latency 2019system.cpu2.icache.ReadReq_avg_miss_latency::total 23723.283368 # average ReadReq miss latency 2020system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23723.283368 # average overall miss latency 2021system.cpu2.icache.demand_avg_miss_latency::total 23723.283368 # average overall miss latency 2022system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23723.283368 # average overall miss latency 2023system.cpu2.icache.overall_avg_miss_latency::total 23723.283368 # average overall miss latency | 2125system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23657.574949 # average ReadReq miss latency 2126system.cpu2.icache.ReadReq_avg_miss_latency::total 23657.574949 # average ReadReq miss latency 2127system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23657.574949 # average overall miss latency 2128system.cpu2.icache.demand_avg_miss_latency::total 23657.574949 # average overall miss latency 2129system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23657.574949 # average overall miss latency 2130system.cpu2.icache.overall_avg_miss_latency::total 23657.574949 # average overall miss latency |
| 2024system.cpu2.icache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked 2025system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2026system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked 2027system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 2028system.cpu2.icache.avg_blocked_cycles::no_mshrs 85 # average number of cycles each access was blocked 2029system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2030system.cpu2.icache.fast_writes 0 # number of fast writes performed 2031system.cpu2.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 2036system.cpu2.icache.overall_mshr_hits::cpu2.inst 62 # number of overall MSHR hits 2037system.cpu2.icache.overall_mshr_hits::total 62 # number of overall MSHR hits 2038system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 425 # number of ReadReq MSHR misses 2039system.cpu2.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses 2040system.cpu2.icache.demand_mshr_misses::cpu2.inst 425 # number of demand (read+write) MSHR misses 2041system.cpu2.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses 2042system.cpu2.icache.overall_mshr_misses::cpu2.inst 425 # number of overall MSHR misses 2043system.cpu2.icache.overall_mshr_misses::total 425 # number of overall MSHR misses | 2131system.cpu2.icache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked 2132system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2133system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked 2134system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 2135system.cpu2.icache.avg_blocked_cycles::no_mshrs 85 # average number of cycles each access was blocked 2136system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2137system.cpu2.icache.fast_writes 0 # number of fast writes performed 2138system.cpu2.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 2143system.cpu2.icache.overall_mshr_hits::cpu2.inst 62 # number of overall MSHR hits 2144system.cpu2.icache.overall_mshr_hits::total 62 # number of overall MSHR hits 2145system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 425 # number of ReadReq MSHR misses 2146system.cpu2.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses 2147system.cpu2.icache.demand_mshr_misses::cpu2.inst 425 # number of demand (read+write) MSHR misses 2148system.cpu2.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses 2149system.cpu2.icache.overall_mshr_misses::cpu2.inst 425 # number of overall MSHR misses 2150system.cpu2.icache.overall_mshr_misses::total 425 # number of overall MSHR misses |
| 2044system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9258007 # number of ReadReq MSHR miss cycles 2045system.cpu2.icache.ReadReq_mshr_miss_latency::total 9258007 # number of ReadReq MSHR miss cycles 2046system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9258007 # number of demand (read+write) MSHR miss cycles 2047system.cpu2.icache.demand_mshr_miss_latency::total 9258007 # number of demand (read+write) MSHR miss cycles 2048system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9258007 # number of overall MSHR miss cycles 2049system.cpu2.icache.overall_mshr_miss_latency::total 9258007 # number of overall MSHR miss cycles | 2151system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9226007 # number of ReadReq MSHR miss cycles 2152system.cpu2.icache.ReadReq_mshr_miss_latency::total 9226007 # number of ReadReq MSHR miss cycles 2153system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9226007 # number of demand (read+write) MSHR miss cycles 2154system.cpu2.icache.demand_mshr_miss_latency::total 9226007 # number of demand (read+write) MSHR miss cycles 2155system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9226007 # number of overall MSHR miss cycles 2156system.cpu2.icache.overall_mshr_miss_latency::total 9226007 # number of overall MSHR miss cycles |
| 2050system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.019510 # mshr miss rate for ReadReq accesses 2051system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.019510 # mshr miss rate for ReadReq accesses 2052system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.019510 # mshr miss rate for demand accesses 2053system.cpu2.icache.demand_mshr_miss_rate::total 0.019510 # mshr miss rate for demand accesses 2054system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.019510 # mshr miss rate for overall accesses 2055system.cpu2.icache.overall_mshr_miss_rate::total 0.019510 # mshr miss rate for overall accesses | 2157system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.019510 # mshr miss rate for ReadReq accesses 2158system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.019510 # mshr miss rate for ReadReq accesses 2159system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.019510 # mshr miss rate for demand accesses 2160system.cpu2.icache.demand_mshr_miss_rate::total 0.019510 # mshr miss rate for demand accesses 2161system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.019510 # mshr miss rate for overall accesses 2162system.cpu2.icache.overall_mshr_miss_rate::total 0.019510 # mshr miss rate for overall accesses |
| 2056system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21783.545882 # average ReadReq mshr miss latency 2057system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21783.545882 # average ReadReq mshr miss latency 2058system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21783.545882 # average overall mshr miss latency 2059system.cpu2.icache.demand_avg_mshr_miss_latency::total 21783.545882 # average overall mshr miss latency 2060system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21783.545882 # average overall mshr miss latency 2061system.cpu2.icache.overall_avg_mshr_miss_latency::total 21783.545882 # average overall mshr miss latency | 2163system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21708.251765 # average ReadReq mshr miss latency 2164system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21708.251765 # average ReadReq mshr miss latency 2165system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21708.251765 # average overall mshr miss latency 2166system.cpu2.icache.demand_avg_mshr_miss_latency::total 21708.251765 # average overall mshr miss latency 2167system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21708.251765 # average overall mshr miss latency 2168system.cpu2.icache.overall_avg_mshr_miss_latency::total 21708.251765 # average overall mshr miss latency |
| 2062system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2063system.cpu2.dcache.tags.replacements 0 # number of replacements | 2169system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2170system.cpu2.dcache.tags.replacements 0 # number of replacements |
| 2064system.cpu2.dcache.tags.tagsinuse 26.156826 # Cycle average of tags in use 2065system.cpu2.dcache.tags.total_refs 37738 # Total number of references to valid blocks. | 2171system.cpu2.dcache.tags.tagsinuse 26.169210 # Cycle average of tags in use 2172system.cpu2.dcache.tags.total_refs 37730 # Total number of references to valid blocks. |
| 2066system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. | 2173system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. |
| 2067system.cpu2.dcache.tags.avg_refs 1301.310345 # Average number of references to valid blocks. | 2174system.cpu2.dcache.tags.avg_refs 1301.034483 # Average number of references to valid blocks. |
| 2068system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2175system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 2069system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.156826 # Average occupied blocks per requestor 2070system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051088 # Average percentage of cache occupancy 2071system.cpu2.dcache.tags.occ_percent::total 0.051088 # Average percentage of cache occupancy | 2176system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.169210 # Average occupied blocks per requestor 2177system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051112 # Average percentage of cache occupancy 2178system.cpu2.dcache.tags.occ_percent::total 0.051112 # Average percentage of cache occupancy |
| 2072system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 2073system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 2074system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 2075system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id | 2179system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 2180system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 2181system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 2182system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id |
| 2076system.cpu2.dcache.tags.tag_accesses 296038 # Number of tag accesses 2077system.cpu2.dcache.tags.data_accesses 296038 # Number of data accesses 2078system.cpu2.dcache.ReadReq_hits::cpu2.data 42011 # number of ReadReq hits 2079system.cpu2.dcache.ReadReq_hits::total 42011 # number of ReadReq hits 2080system.cpu2.dcache.WriteReq_hits::cpu2.data 31379 # number of WriteReq hits 2081system.cpu2.dcache.WriteReq_hits::total 31379 # number of WriteReq hits | 2183system.cpu2.dcache.tags.tag_accesses 295974 # Number of tag accesses 2184system.cpu2.dcache.tags.data_accesses 295974 # Number of data accesses 2185system.cpu2.dcache.ReadReq_hits::cpu2.data 42003 # number of ReadReq hits 2186system.cpu2.dcache.ReadReq_hits::total 42003 # number of ReadReq hits 2187system.cpu2.dcache.WriteReq_hits::cpu2.data 31371 # number of WriteReq hits 2188system.cpu2.dcache.WriteReq_hits::total 31371 # number of WriteReq hits |
| 2082system.cpu2.dcache.SwapReq_hits::cpu2.data 14 # number of SwapReq hits 2083system.cpu2.dcache.SwapReq_hits::total 14 # number of SwapReq hits | 2189system.cpu2.dcache.SwapReq_hits::cpu2.data 14 # number of SwapReq hits 2190system.cpu2.dcache.SwapReq_hits::total 14 # number of SwapReq hits |
| 2084system.cpu2.dcache.demand_hits::cpu2.data 73390 # number of demand (read+write) hits 2085system.cpu2.dcache.demand_hits::total 73390 # number of demand (read+write) hits 2086system.cpu2.dcache.overall_hits::cpu2.data 73390 # number of overall hits 2087system.cpu2.dcache.overall_hits::total 73390 # number of overall hits | 2191system.cpu2.dcache.demand_hits::cpu2.data 73374 # number of demand (read+write) hits 2192system.cpu2.dcache.demand_hits::total 73374 # number of demand (read+write) hits 2193system.cpu2.dcache.overall_hits::cpu2.data 73374 # number of overall hits 2194system.cpu2.dcache.overall_hits::total 73374 # number of overall hits |
| 2088system.cpu2.dcache.ReadReq_misses::cpu2.data 342 # number of ReadReq misses 2089system.cpu2.dcache.ReadReq_misses::total 342 # number of ReadReq misses 2090system.cpu2.dcache.WriteReq_misses::cpu2.data 140 # number of WriteReq misses 2091system.cpu2.dcache.WriteReq_misses::total 140 # number of WriteReq misses 2092system.cpu2.dcache.SwapReq_misses::cpu2.data 59 # number of SwapReq misses 2093system.cpu2.dcache.SwapReq_misses::total 59 # number of SwapReq misses 2094system.cpu2.dcache.demand_misses::cpu2.data 482 # number of demand (read+write) misses 2095system.cpu2.dcache.demand_misses::total 482 # number of demand (read+write) misses 2096system.cpu2.dcache.overall_misses::cpu2.data 482 # number of overall misses 2097system.cpu2.dcache.overall_misses::total 482 # number of overall misses | 2195system.cpu2.dcache.ReadReq_misses::cpu2.data 342 # number of ReadReq misses 2196system.cpu2.dcache.ReadReq_misses::total 342 # number of ReadReq misses 2197system.cpu2.dcache.WriteReq_misses::cpu2.data 140 # number of WriteReq misses 2198system.cpu2.dcache.WriteReq_misses::total 140 # number of WriteReq misses 2199system.cpu2.dcache.SwapReq_misses::cpu2.data 59 # number of SwapReq misses 2200system.cpu2.dcache.SwapReq_misses::total 59 # number of SwapReq misses 2201system.cpu2.dcache.demand_misses::cpu2.data 482 # number of demand (read+write) misses 2202system.cpu2.dcache.demand_misses::total 482 # number of demand (read+write) misses 2203system.cpu2.dcache.overall_misses::cpu2.data 482 # number of overall misses 2204system.cpu2.dcache.overall_misses::total 482 # number of overall misses |
| 2098system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5441573 # number of ReadReq miss cycles 2099system.cpu2.dcache.ReadReq_miss_latency::total 5441573 # number of ReadReq miss cycles | 2205system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5435581 # number of ReadReq miss cycles 2206system.cpu2.dcache.ReadReq_miss_latency::total 5435581 # number of ReadReq miss cycles |
| 2100system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3139010 # number of WriteReq miss cycles 2101system.cpu2.dcache.WriteReq_miss_latency::total 3139010 # number of WriteReq miss cycles 2102system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 574505 # number of SwapReq miss cycles 2103system.cpu2.dcache.SwapReq_miss_latency::total 574505 # number of SwapReq miss cycles | 2207system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3139010 # number of WriteReq miss cycles 2208system.cpu2.dcache.WriteReq_miss_latency::total 3139010 # number of WriteReq miss cycles 2209system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 574505 # number of SwapReq miss cycles 2210system.cpu2.dcache.SwapReq_miss_latency::total 574505 # number of SwapReq miss cycles |
| 2104system.cpu2.dcache.demand_miss_latency::cpu2.data 8580583 # number of demand (read+write) miss cycles 2105system.cpu2.dcache.demand_miss_latency::total 8580583 # number of demand (read+write) miss cycles 2106system.cpu2.dcache.overall_miss_latency::cpu2.data 8580583 # number of overall miss cycles 2107system.cpu2.dcache.overall_miss_latency::total 8580583 # number of overall miss cycles 2108system.cpu2.dcache.ReadReq_accesses::cpu2.data 42353 # number of ReadReq accesses(hits+misses) 2109system.cpu2.dcache.ReadReq_accesses::total 42353 # number of ReadReq accesses(hits+misses) 2110system.cpu2.dcache.WriteReq_accesses::cpu2.data 31519 # number of WriteReq accesses(hits+misses) 2111system.cpu2.dcache.WriteReq_accesses::total 31519 # number of WriteReq accesses(hits+misses) | 2211system.cpu2.dcache.demand_miss_latency::cpu2.data 8574591 # number of demand (read+write) miss cycles 2212system.cpu2.dcache.demand_miss_latency::total 8574591 # number of demand (read+write) miss cycles 2213system.cpu2.dcache.overall_miss_latency::cpu2.data 8574591 # number of overall miss cycles 2214system.cpu2.dcache.overall_miss_latency::total 8574591 # number of overall miss cycles 2215system.cpu2.dcache.ReadReq_accesses::cpu2.data 42345 # number of ReadReq accesses(hits+misses) 2216system.cpu2.dcache.ReadReq_accesses::total 42345 # number of ReadReq accesses(hits+misses) 2217system.cpu2.dcache.WriteReq_accesses::cpu2.data 31511 # number of WriteReq accesses(hits+misses) 2218system.cpu2.dcache.WriteReq_accesses::total 31511 # number of WriteReq accesses(hits+misses) |
| 2112system.cpu2.dcache.SwapReq_accesses::cpu2.data 73 # number of SwapReq accesses(hits+misses) 2113system.cpu2.dcache.SwapReq_accesses::total 73 # number of SwapReq accesses(hits+misses) | 2219system.cpu2.dcache.SwapReq_accesses::cpu2.data 73 # number of SwapReq accesses(hits+misses) 2220system.cpu2.dcache.SwapReq_accesses::total 73 # number of SwapReq accesses(hits+misses) |
| 2114system.cpu2.dcache.demand_accesses::cpu2.data 73872 # number of demand (read+write) accesses 2115system.cpu2.dcache.demand_accesses::total 73872 # number of demand (read+write) accesses 2116system.cpu2.dcache.overall_accesses::cpu2.data 73872 # number of overall (read+write) accesses 2117system.cpu2.dcache.overall_accesses::total 73872 # number of overall (read+write) accesses 2118system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.008075 # miss rate for ReadReq accesses 2119system.cpu2.dcache.ReadReq_miss_rate::total 0.008075 # miss rate for ReadReq accesses 2120system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004442 # miss rate for WriteReq accesses 2121system.cpu2.dcache.WriteReq_miss_rate::total 0.004442 # miss rate for WriteReq accesses | 2221system.cpu2.dcache.demand_accesses::cpu2.data 73856 # number of demand (read+write) accesses 2222system.cpu2.dcache.demand_accesses::total 73856 # number of demand (read+write) accesses 2223system.cpu2.dcache.overall_accesses::cpu2.data 73856 # number of overall (read+write) accesses 2224system.cpu2.dcache.overall_accesses::total 73856 # number of overall (read+write) accesses 2225system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.008077 # miss rate for ReadReq accesses 2226system.cpu2.dcache.ReadReq_miss_rate::total 0.008077 # miss rate for ReadReq accesses 2227system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004443 # miss rate for WriteReq accesses 2228system.cpu2.dcache.WriteReq_miss_rate::total 0.004443 # miss rate for WriteReq accesses |
| 2122system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.808219 # miss rate for SwapReq accesses 2123system.cpu2.dcache.SwapReq_miss_rate::total 0.808219 # miss rate for SwapReq accesses | 2229system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.808219 # miss rate for SwapReq accesses 2230system.cpu2.dcache.SwapReq_miss_rate::total 0.808219 # miss rate for SwapReq accesses |
| 2124system.cpu2.dcache.demand_miss_rate::cpu2.data 0.006525 # miss rate for demand accesses 2125system.cpu2.dcache.demand_miss_rate::total 0.006525 # miss rate for demand accesses 2126system.cpu2.dcache.overall_miss_rate::cpu2.data 0.006525 # miss rate for overall accesses 2127system.cpu2.dcache.overall_miss_rate::total 0.006525 # miss rate for overall accesses 2128system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15911.032164 # average ReadReq miss latency 2129system.cpu2.dcache.ReadReq_avg_miss_latency::total 15911.032164 # average ReadReq miss latency | 2231system.cpu2.dcache.demand_miss_rate::cpu2.data 0.006526 # miss rate for demand accesses 2232system.cpu2.dcache.demand_miss_rate::total 0.006526 # miss rate for demand accesses 2233system.cpu2.dcache.overall_miss_rate::cpu2.data 0.006526 # miss rate for overall accesses 2234system.cpu2.dcache.overall_miss_rate::total 0.006526 # miss rate for overall accesses 2235system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15893.511696 # average ReadReq miss latency 2236system.cpu2.dcache.ReadReq_avg_miss_latency::total 15893.511696 # average ReadReq miss latency |
| 2130system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22421.500000 # average WriteReq miss latency 2131system.cpu2.dcache.WriteReq_avg_miss_latency::total 22421.500000 # average WriteReq miss latency 2132system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9737.372881 # average SwapReq miss latency 2133system.cpu2.dcache.SwapReq_avg_miss_latency::total 9737.372881 # average SwapReq miss latency | 2237system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22421.500000 # average WriteReq miss latency 2238system.cpu2.dcache.WriteReq_avg_miss_latency::total 22421.500000 # average WriteReq miss latency 2239system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9737.372881 # average SwapReq miss latency 2240system.cpu2.dcache.SwapReq_avg_miss_latency::total 9737.372881 # average SwapReq miss latency |
| 2134system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17802.039419 # average overall miss latency 2135system.cpu2.dcache.demand_avg_miss_latency::total 17802.039419 # average overall miss latency 2136system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17802.039419 # average overall miss latency 2137system.cpu2.dcache.overall_avg_miss_latency::total 17802.039419 # average overall miss latency | 2241system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17789.607884 # average overall miss latency 2242system.cpu2.dcache.demand_avg_miss_latency::total 17789.607884 # average overall miss latency 2243system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17789.607884 # average overall miss latency 2244system.cpu2.dcache.overall_avg_miss_latency::total 17789.607884 # average overall miss latency |
| 2138system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2139system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2140system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2141system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 2142system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2143system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2144system.cpu2.dcache.fast_writes 0 # number of fast writes performed 2145system.cpu2.dcache.cache_copies 0 # number of cache copies performed --- 10 unchanged lines hidden (view full) --- 2156system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses 2157system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses 2158system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 59 # number of SwapReq MSHR misses 2159system.cpu2.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses 2160system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses 2161system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses 2162system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses 2163system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses | 2245system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2246system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2247system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2248system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 2249system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2250system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2251system.cpu2.dcache.fast_writes 0 # number of fast writes performed 2252system.cpu2.dcache.cache_copies 0 # number of cache copies performed --- 10 unchanged lines hidden (view full) --- 2263system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses 2264system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses 2265system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 59 # number of SwapReq MSHR misses 2266system.cpu2.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses 2267system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses 2268system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses 2269system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses 2270system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses |
| 2164system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1516779 # number of ReadReq MSHR miss cycles 2165system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1516779 # number of ReadReq MSHR miss cycles | 2271system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1515278 # number of ReadReq MSHR miss cycles 2272system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1515278 # number of ReadReq MSHR miss cycles |
| 2166system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1527990 # number of WriteReq MSHR miss cycles 2167system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1527990 # number of WriteReq MSHR miss cycles 2168system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 456495 # number of SwapReq MSHR miss cycles 2169system.cpu2.dcache.SwapReq_mshr_miss_latency::total 456495 # number of SwapReq MSHR miss cycles | 2273system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1527990 # number of WriteReq MSHR miss cycles 2274system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1527990 # number of WriteReq MSHR miss cycles 2275system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 456495 # number of SwapReq MSHR miss cycles 2276system.cpu2.dcache.SwapReq_mshr_miss_latency::total 456495 # number of SwapReq MSHR miss cycles |
| 2170system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3044769 # number of demand (read+write) MSHR miss cycles 2171system.cpu2.dcache.demand_mshr_miss_latency::total 3044769 # number of demand (read+write) MSHR miss cycles 2172system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3044769 # number of overall MSHR miss cycles 2173system.cpu2.dcache.overall_mshr_miss_latency::total 3044769 # number of overall MSHR miss cycles 2174system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003896 # mshr miss rate for ReadReq accesses 2175system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003896 # mshr miss rate for ReadReq accesses 2176system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003363 # mshr miss rate for WriteReq accesses 2177system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003363 # mshr miss rate for WriteReq accesses | 2277system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3043268 # number of demand (read+write) MSHR miss cycles 2278system.cpu2.dcache.demand_mshr_miss_latency::total 3043268 # number of demand (read+write) MSHR miss cycles 2279system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3043268 # number of overall MSHR miss cycles 2280system.cpu2.dcache.overall_mshr_miss_latency::total 3043268 # number of overall MSHR miss cycles 2281system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003897 # mshr miss rate for ReadReq accesses 2282system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003897 # mshr miss rate for ReadReq accesses 2283system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003364 # mshr miss rate for WriteReq accesses 2284system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003364 # mshr miss rate for WriteReq accesses |
| 2178system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.808219 # mshr miss rate for SwapReq accesses 2179system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.808219 # mshr miss rate for SwapReq accesses 2180system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003669 # mshr miss rate for demand accesses 2181system.cpu2.dcache.demand_mshr_miss_rate::total 0.003669 # mshr miss rate for demand accesses 2182system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003669 # mshr miss rate for overall accesses 2183system.cpu2.dcache.overall_mshr_miss_rate::total 0.003669 # mshr miss rate for overall accesses | 2285system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.808219 # mshr miss rate for SwapReq accesses 2286system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.808219 # mshr miss rate for SwapReq accesses 2287system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003669 # mshr miss rate for demand accesses 2288system.cpu2.dcache.demand_mshr_miss_rate::total 0.003669 # mshr miss rate for demand accesses 2289system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003669 # mshr miss rate for overall accesses 2290system.cpu2.dcache.overall_mshr_miss_rate::total 0.003669 # mshr miss rate for overall accesses |
| 2184system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9192.600000 # average ReadReq mshr miss latency 2185system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9192.600000 # average ReadReq mshr miss latency | 2291system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9183.503030 # average ReadReq mshr miss latency 2292system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9183.503030 # average ReadReq mshr miss latency |
| 2186system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14415 # average WriteReq mshr miss latency 2187system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14415 # average WriteReq mshr miss latency 2188system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7737.203390 # average SwapReq mshr miss latency 2189system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7737.203390 # average SwapReq mshr miss latency | 2293system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14415 # average WriteReq mshr miss latency 2294system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14415 # average WriteReq mshr miss latency 2295system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7737.203390 # average SwapReq mshr miss latency 2296system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7737.203390 # average SwapReq mshr miss latency |
| 2190system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11235.309963 # average overall mshr miss latency 2191system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11235.309963 # average overall mshr miss latency 2192system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11235.309963 # average overall mshr miss latency 2193system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11235.309963 # average overall mshr miss latency | 2297system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11229.771218 # average overall mshr miss latency 2298system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11229.771218 # average overall mshr miss latency 2299system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11229.771218 # average overall mshr miss latency 2300system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11229.771218 # average overall mshr miss latency |
| 2194system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 2301system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2195system.cpu3.branchPred.lookups 53969 # Number of BP lookups 2196system.cpu3.branchPred.condPredicted 51237 # Number of conditional branches predicted | 2302system.cpu3.branchPred.lookups 53964 # Number of BP lookups 2303system.cpu3.branchPred.condPredicted 51232 # Number of conditional branches predicted |
| 2197system.cpu3.branchPred.condIncorrect 1265 # Number of conditional branches incorrect | 2304system.cpu3.branchPred.condIncorrect 1265 # Number of conditional branches incorrect |
| 2198system.cpu3.branchPred.BTBLookups 47879 # Number of BTB lookups 2199system.cpu3.branchPred.BTBHits 47122 # Number of BTB hits | 2305system.cpu3.branchPred.BTBLookups 47874 # Number of BTB lookups 2306system.cpu3.branchPred.BTBHits 47117 # Number of BTB hits |
| 2200system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 2307system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 2201system.cpu3.branchPred.BTBHitPct 98.418931 # BTB Hit Percentage | 2308system.cpu3.branchPred.BTBHitPct 98.418766 # BTB Hit Percentage |
| 2202system.cpu3.branchPred.usedRAS 645 # Number of times the RAS was used to get a target. 2203system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. | 2309system.cpu3.branchPred.usedRAS 645 # Number of times the RAS was used to get a target. 2310system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. |
| 2204system.cpu3.numCycles 177018 # number of cpu cycles simulated | 2311system.cpu3.numCycles 176930 # number of cpu cycles simulated |
| 2205system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 2206system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed | 2312system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 2313system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 2207system.cpu3.fetch.icacheStallCycles 27849 # Number of cycles fetch is stalled on an Icache miss 2208system.cpu3.fetch.Insts 302683 # Number of instructions fetch has processed 2209system.cpu3.fetch.Branches 53969 # Number of branches that fetch encountered 2210system.cpu3.fetch.predictedBranches 47767 # Number of branches that fetch has predicted taken 2211system.cpu3.fetch.Cycles 106238 # Number of cycles fetch has run and was not squashing or blocked | 2314system.cpu3.fetch.icacheStallCycles 27837 # Number of cycles fetch is stalled on an Icache miss 2315system.cpu3.fetch.Insts 302665 # Number of instructions fetch has processed 2316system.cpu3.fetch.Branches 53964 # Number of branches that fetch encountered 2317system.cpu3.fetch.predictedBranches 47762 # Number of branches that fetch has predicted taken 2318system.cpu3.fetch.Cycles 106222 # Number of cycles fetch has run and was not squashing or blocked |
| 2212system.cpu3.fetch.SquashCycles 3643 # Number of cycles fetch has spent squashing | 2319system.cpu3.fetch.SquashCycles 3643 # Number of cycles fetch has spent squashing |
| 2213system.cpu3.fetch.BlockedCycles 30687 # Number of cycles fetch has spent blocked | 2320system.cpu3.fetch.BlockedCycles 30631 # Number of cycles fetch has spent blocked |
| 2214system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 2321system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 2215system.cpu3.fetch.NoActiveThreadStallCycles 7755 # Number of stall cycles due to no active thread to fetch from | 2322system.cpu3.fetch.NoActiveThreadStallCycles 7749 # Number of stall cycles due to no active thread to fetch from |
| 2216system.cpu3.fetch.PendingTrapStallCycles 799 # Number of stall cycles due to pending traps | 2323system.cpu3.fetch.PendingTrapStallCycles 799 # Number of stall cycles due to pending traps |
| 2217system.cpu3.fetch.CacheLines 19589 # Number of cache lines fetched | 2324system.cpu3.fetch.CacheLines 19577 # Number of cache lines fetched |
| 2218system.cpu3.fetch.IcacheSquashes 266 # Number of outstanding Icache misses that were squashed | 2325system.cpu3.fetch.IcacheSquashes 266 # Number of outstanding Icache misses that were squashed |
| 2219system.cpu3.fetch.rateDist::samples 175633 # Number of instructions fetched each cycle (Total) 2220system.cpu3.fetch.rateDist::mean 1.723383 # Number of instructions fetched each cycle (Total) 2221system.cpu3.fetch.rateDist::stdev 2.153093 # Number of instructions fetched each cycle (Total) | 2326system.cpu3.fetch.rateDist::samples 175543 # Number of instructions fetched each cycle (Total) 2327system.cpu3.fetch.rateDist::mean 1.724164 # Number of instructions fetched each cycle (Total) 2328system.cpu3.fetch.rateDist::stdev 2.153360 # Number of instructions fetched each cycle (Total) |
| 2222system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 2329system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 2223system.cpu3.fetch.rateDist::0 69395 39.51% 39.51% # Number of instructions fetched each cycle (Total) 2224system.cpu3.fetch.rateDist::1 53961 30.72% 70.24% # Number of instructions fetched each cycle (Total) 2225system.cpu3.fetch.rateDist::2 6037 3.44% 73.67% # Number of instructions fetched each cycle (Total) 2226system.cpu3.fetch.rateDist::3 3206 1.83% 75.50% # Number of instructions fetched each cycle (Total) 2227system.cpu3.fetch.rateDist::4 696 0.40% 75.89% # Number of instructions fetched each cycle (Total) 2228system.cpu3.fetch.rateDist::5 37090 21.12% 97.01% # Number of instructions fetched each cycle (Total) | 2330system.cpu3.fetch.rateDist::0 69321 39.49% 39.49% # Number of instructions fetched each cycle (Total) 2331system.cpu3.fetch.rateDist::1 53950 30.73% 70.22% # Number of instructions fetched each cycle (Total) 2332system.cpu3.fetch.rateDist::2 6031 3.44% 73.66% # Number of instructions fetched each cycle (Total) 2333system.cpu3.fetch.rateDist::3 3206 1.83% 75.48% # Number of instructions fetched each cycle (Total) 2334system.cpu3.fetch.rateDist::4 696 0.40% 75.88% # Number of instructions fetched each cycle (Total) 2335system.cpu3.fetch.rateDist::5 37091 21.13% 97.01% # Number of instructions fetched each cycle (Total) |
| 2229system.cpu3.fetch.rateDist::6 1217 0.69% 97.70% # Number of instructions fetched each cycle (Total) 2230system.cpu3.fetch.rateDist::7 754 0.43% 98.13% # Number of instructions fetched each cycle (Total) 2231system.cpu3.fetch.rateDist::8 3277 1.87% 100.00% # Number of instructions fetched each cycle (Total) 2232system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2233system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2234system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 2336system.cpu3.fetch.rateDist::6 1217 0.69% 97.70% # Number of instructions fetched each cycle (Total) 2337system.cpu3.fetch.rateDist::7 754 0.43% 98.13% # Number of instructions fetched each cycle (Total) 2338system.cpu3.fetch.rateDist::8 3277 1.87% 100.00% # Number of instructions fetched each cycle (Total) 2339system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2340system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2341system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 2235system.cpu3.fetch.rateDist::total 175633 # Number of instructions fetched each cycle (Total) 2236system.cpu3.fetch.branchRate 0.304879 # Number of branch fetches per cycle 2237system.cpu3.fetch.rate 1.709900 # Number of inst fetches per cycle 2238system.cpu3.decode.IdleCycles 32991 # Number of cycles decode is idle 2239system.cpu3.decode.BlockedCycles 27180 # Number of cycles decode is blocked 2240system.cpu3.decode.RunCycles 100358 # Number of cycles decode is running 2241system.cpu3.decode.UnblockCycles 5049 # Number of cycles decode is unblocking | 2342system.cpu3.fetch.rateDist::total 175543 # Number of instructions fetched each cycle (Total) 2343system.cpu3.fetch.branchRate 0.305002 # Number of branch fetches per cycle 2344system.cpu3.fetch.rate 1.710648 # Number of inst fetches per cycle 2345system.cpu3.decode.IdleCycles 32973 # Number of cycles decode is idle 2346system.cpu3.decode.BlockedCycles 27130 # Number of cycles decode is blocked 2347system.cpu3.decode.RunCycles 100348 # Number of cycles decode is running 2348system.cpu3.decode.UnblockCycles 5043 # Number of cycles decode is unblocking |
| 2242system.cpu3.decode.SquashCycles 2300 # Number of cycles decode is squashing | 2349system.cpu3.decode.SquashCycles 2300 # Number of cycles decode is squashing |
| 2243system.cpu3.decode.DecodedInsts 299127 # Number of instructions handled by decode | 2350system.cpu3.decode.DecodedInsts 299109 # Number of instructions handled by decode |
| 2244system.cpu3.rename.SquashCycles 2300 # Number of cycles rename is squashing | 2351system.cpu3.rename.SquashCycles 2300 # Number of cycles rename is squashing |
| 2245system.cpu3.rename.IdleCycles 33666 # Number of cycles rename is idle 2246system.cpu3.rename.BlockCycles 14636 # Number of cycles rename is blocking 2247system.cpu3.rename.serializeStallCycles 11796 # count of cycles rename stalled for serializing inst 2248system.cpu3.rename.RunCycles 95593 # Number of cycles rename is running 2249system.cpu3.rename.UnblockCycles 9887 # Number of cycles rename is unblocking 2250system.cpu3.rename.RenamedInsts 297010 # Number of instructions processed by rename | 2352system.cpu3.rename.IdleCycles 33648 # Number of cycles rename is idle 2353system.cpu3.rename.BlockCycles 14616 # Number of cycles rename is blocking 2354system.cpu3.rename.serializeStallCycles 11766 # count of cycles rename stalled for serializing inst 2355system.cpu3.rename.RunCycles 95589 # Number of cycles rename is running 2356system.cpu3.rename.UnblockCycles 9875 # Number of cycles rename is unblocking 2357system.cpu3.rename.RenamedInsts 296992 # Number of instructions processed by rename |
| 2251system.cpu3.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full 2252system.cpu3.rename.LSQFullEvents 23 # Number of times rename has blocked due to LSQ full | 2358system.cpu3.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full 2359system.cpu3.rename.LSQFullEvents 23 # Number of times rename has blocked due to LSQ full |
| 2253system.cpu3.rename.RenamedOperands 207704 # Number of destination operands rename has renamed 2254system.cpu3.rename.RenameLookups 570857 # Number of register rename lookups that rename has made 2255system.cpu3.rename.int_rename_lookups 442944 # Number of integer rename lookups 2256system.cpu3.rename.CommittedMaps 195081 # Number of HB maps that are committed | 2360system.cpu3.rename.RenamedOperands 207702 # Number of destination operands rename has renamed 2361system.cpu3.rename.RenameLookups 570845 # Number of register rename lookups that rename has made 2362system.cpu3.rename.int_rename_lookups 442935 # Number of integer rename lookups 2363system.cpu3.rename.CommittedMaps 195079 # Number of HB maps that are committed |
| 2257system.cpu3.rename.UndoneMaps 12623 # Number of HB maps that are undone due to squashing 2258system.cpu3.rename.serializingInsts 1101 # count of serializing insts renamed 2259system.cpu3.rename.tempSerializingInsts 1224 # count of temporary serializing insts renamed | 2364system.cpu3.rename.UndoneMaps 12623 # Number of HB maps that are undone due to squashing 2365system.cpu3.rename.serializingInsts 1101 # count of serializing insts renamed 2366system.cpu3.rename.tempSerializingInsts 1224 # count of temporary serializing insts renamed |
| 2260system.cpu3.rename.skidInsts 12502 # count of insts added to the skid buffer 2261system.cpu3.memDep0.insertedLoads 84726 # Number of loads inserted to the mem dependence unit. 2262system.cpu3.memDep0.insertedStores 40382 # Number of stores inserted to the mem dependence unit. 2263system.cpu3.memDep0.conflictingLoads 40460 # Number of conflicting loads. 2264system.cpu3.memDep0.conflictingStores 35337 # Number of conflicting stores. 2265system.cpu3.iq.iqInstsAdded 246420 # Number of instructions added to the IQ (excludes non-spec) 2266system.cpu3.iq.iqNonSpecInstsAdded 6261 # Number of non-speculative instructions added to the IQ 2267system.cpu3.iq.iqInstsIssued 248749 # Number of instructions issued 2268system.cpu3.iq.iqSquashedInstsIssued 57 # Number of squashed instructions issued | 2367system.cpu3.rename.skidInsts 12490 # count of insts added to the skid buffer 2368system.cpu3.memDep0.insertedLoads 84722 # Number of loads inserted to the mem dependence unit. 2369system.cpu3.memDep0.insertedStores 40383 # Number of stores inserted to the mem dependence unit. 2370system.cpu3.memDep0.conflictingLoads 40455 # Number of conflicting loads. 2371system.cpu3.memDep0.conflictingStores 35338 # Number of conflicting stores. 2372system.cpu3.iq.iqInstsAdded 246413 # Number of instructions added to the IQ (excludes non-spec) 2373system.cpu3.iq.iqNonSpecInstsAdded 6255 # Number of non-speculative instructions added to the IQ 2374system.cpu3.iq.iqInstsIssued 248738 # Number of instructions issued 2375system.cpu3.iq.iqSquashedInstsIssued 58 # Number of squashed instructions issued |
| 2269system.cpu3.iq.iqSquashedInstsExamined 10413 # Number of squashed instructions iterated over during squash; mainly for profiling | 2376system.cpu3.iq.iqSquashedInstsExamined 10413 # Number of squashed instructions iterated over during squash; mainly for profiling |
| 2270system.cpu3.iq.iqSquashedOperandsExamined 9956 # Number of squashed operands that are examined and possibly removed from graph | 2377system.cpu3.iq.iqSquashedOperandsExamined 9948 # Number of squashed operands that are examined and possibly removed from graph |
| 2271system.cpu3.iq.iqSquashedNonSpecRemoved 566 # Number of squashed non-spec instructions that were removed | 2378system.cpu3.iq.iqSquashedNonSpecRemoved 566 # Number of squashed non-spec instructions that were removed |
| 2272system.cpu3.iq.issued_per_cycle::samples 175633 # Number of insts issued each cycle 2273system.cpu3.iq.issued_per_cycle::mean 1.416300 # Number of insts issued each cycle 2274system.cpu3.iq.issued_per_cycle::stdev 1.309117 # Number of insts issued each cycle | 2379system.cpu3.iq.issued_per_cycle::samples 175543 # Number of insts issued each cycle 2380system.cpu3.iq.issued_per_cycle::mean 1.416963 # Number of insts issued each cycle 2381system.cpu3.iq.issued_per_cycle::stdev 1.309147 # Number of insts issued each cycle |
| 2275system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 2382system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 2276system.cpu3.iq.issued_per_cycle::0 66575 37.91% 37.91% # Number of insts issued each cycle 2277system.cpu3.iq.issued_per_cycle::1 22292 12.69% 50.60% # Number of insts issued each cycle 2278system.cpu3.iq.issued_per_cycle::2 40685 23.16% 73.76% # Number of insts issued each cycle 2279system.cpu3.iq.issued_per_cycle::3 41298 23.51% 97.28% # Number of insts issued each cycle 2280system.cpu3.iq.issued_per_cycle::4 3252 1.85% 99.13% # Number of insts issued each cycle | 2383system.cpu3.iq.issued_per_cycle::0 66501 37.88% 37.88% # Number of insts issued each cycle 2384system.cpu3.iq.issued_per_cycle::1 22275 12.69% 50.57% # Number of insts issued each cycle 2385system.cpu3.iq.issued_per_cycle::2 40683 23.18% 73.75% # Number of insts issued each cycle 2386system.cpu3.iq.issued_per_cycle::3 41300 23.53% 97.27% # Number of insts issued each cycle 2387system.cpu3.iq.issued_per_cycle::4 3253 1.85% 99.13% # Number of insts issued each cycle |
| 2281system.cpu3.iq.issued_per_cycle::5 1166 0.66% 99.79% # Number of insts issued each cycle 2282system.cpu3.iq.issued_per_cycle::6 259 0.15% 99.94% # Number of insts issued each cycle 2283system.cpu3.iq.issued_per_cycle::7 47 0.03% 99.97% # Number of insts issued each cycle 2284system.cpu3.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle 2285system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2286system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2287system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 2388system.cpu3.iq.issued_per_cycle::5 1166 0.66% 99.79% # Number of insts issued each cycle 2389system.cpu3.iq.issued_per_cycle::6 259 0.15% 99.94% # Number of insts issued each cycle 2390system.cpu3.iq.issued_per_cycle::7 47 0.03% 99.97% # Number of insts issued each cycle 2391system.cpu3.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle 2392system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2393system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2394system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 2288system.cpu3.iq.issued_per_cycle::total 175633 # Number of insts issued each cycle | 2395system.cpu3.iq.issued_per_cycle::total 175543 # Number of insts issued each cycle |
| 2289system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 2396system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 2290system.cpu3.iq.fu_full::IntAlu 17 6.46% 6.46% # attempts to use FU when none available 2291system.cpu3.iq.fu_full::IntMult 0 0.00% 6.46% # attempts to use FU when none available 2292system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.46% # attempts to use FU when none available 2293system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.46% # attempts to use FU when none available 2294system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.46% # attempts to use FU when none available 2295system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.46% # attempts to use FU when none available 2296system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.46% # attempts to use FU when none available 2297system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.46% # attempts to use FU when none available 2298system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.46% # attempts to use FU when none available 2299system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.46% # attempts to use FU when none available 2300system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.46% # attempts to use FU when none available 2301system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.46% # attempts to use FU when none available 2302system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.46% # attempts to use FU when none available 2303system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.46% # attempts to use FU when none available 2304system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.46% # attempts to use FU when none available 2305system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.46% # attempts to use FU when none available 2306system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.46% # attempts to use FU when none available 2307system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.46% # attempts to use FU when none available 2308system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.46% # attempts to use FU when none available 2309system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.46% # attempts to use FU when none available 2310system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.46% # attempts to use FU when none available 2311system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.46% # attempts to use FU when none available 2312system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.46% # attempts to use FU when none available 2313system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.46% # attempts to use FU when none available 2314system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.46% # attempts to use FU when none available 2315system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.46% # attempts to use FU when none available 2316system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.46% # attempts to use FU when none available 2317system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.46% # attempts to use FU when none available 2318system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.46% # attempts to use FU when none available 2319system.cpu3.iq.fu_full::MemRead 36 13.69% 20.15% # attempts to use FU when none available 2320system.cpu3.iq.fu_full::MemWrite 210 79.85% 100.00% # attempts to use FU when none available | 2397system.cpu3.iq.fu_full::IntAlu 17 6.44% 6.44% # attempts to use FU when none available 2398system.cpu3.iq.fu_full::IntMult 0 0.00% 6.44% # attempts to use FU when none available 2399system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.44% # attempts to use FU when none available 2400system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.44% # attempts to use FU when none available 2401system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.44% # attempts to use FU when none available 2402system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.44% # attempts to use FU when none available 2403system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.44% # attempts to use FU when none available 2404system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.44% # attempts to use FU when none available 2405system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.44% # attempts to use FU when none available 2406system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.44% # attempts to use FU when none available 2407system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.44% # attempts to use FU when none available 2408system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.44% # attempts to use FU when none available 2409system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.44% # attempts to use FU when none available 2410system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.44% # attempts to use FU when none available 2411system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.44% # attempts to use FU when none available 2412system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.44% # attempts to use FU when none available 2413system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.44% # attempts to use FU when none available 2414system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.44% # attempts to use FU when none available 2415system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.44% # attempts to use FU when none available 2416system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.44% # attempts to use FU when none available 2417system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.44% # attempts to use FU when none available 2418system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.44% # attempts to use FU when none available 2419system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.44% # attempts to use FU when none available 2420system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.44% # attempts to use FU when none available 2421system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.44% # attempts to use FU when none available 2422system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.44% # attempts to use FU when none available 2423system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.44% # attempts to use FU when none available 2424system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.44% # attempts to use FU when none available 2425system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.44% # attempts to use FU when none available 2426system.cpu3.iq.fu_full::MemRead 37 14.02% 20.45% # attempts to use FU when none available 2427system.cpu3.iq.fu_full::MemWrite 210 79.55% 100.00% # attempts to use FU when none available |
| 2321system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2322system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2323system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 2428system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2429system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2430system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 2324system.cpu3.iq.FU_type_0::IntAlu 119915 48.21% 48.21% # Type of FU issued | 2431system.cpu3.iq.FU_type_0::IntAlu 119912 48.21% 48.21% # Type of FU issued |
| 2325system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.21% # Type of FU issued 2326system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.21% # Type of FU issued 2327system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.21% # Type of FU issued 2328system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.21% # Type of FU issued 2329system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.21% # Type of FU issued 2330system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.21% # Type of FU issued 2331system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.21% # Type of FU issued 2332system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.21% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 2345system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.21% # Type of FU issued 2346system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.21% # Type of FU issued 2347system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.21% # Type of FU issued 2348system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.21% # Type of FU issued 2349system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.21% # Type of FU issued 2350system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.21% # Type of FU issued 2351system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.21% # Type of FU issued 2352system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.21% # Type of FU issued | 2432system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.21% # Type of FU issued 2433system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.21% # Type of FU issued 2434system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.21% # Type of FU issued 2435system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.21% # Type of FU issued 2436system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.21% # Type of FU issued 2437system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.21% # Type of FU issued 2438system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.21% # Type of FU issued 2439system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.21% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 2452system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.21% # Type of FU issued 2453system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.21% # Type of FU issued 2454system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.21% # Type of FU issued 2455system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.21% # Type of FU issued 2456system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.21% # Type of FU issued 2457system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.21% # Type of FU issued 2458system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.21% # Type of FU issued 2459system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.21% # Type of FU issued |
| 2353system.cpu3.iq.FU_type_0::MemRead 89111 35.82% 84.03% # Type of FU issued 2354system.cpu3.iq.FU_type_0::MemWrite 39723 15.97% 100.00% # Type of FU issued | 2460system.cpu3.iq.FU_type_0::MemRead 89101 35.82% 84.03% # Type of FU issued 2461system.cpu3.iq.FU_type_0::MemWrite 39725 15.97% 100.00% # Type of FU issued |
| 2355system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2356system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 2462system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2463system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 2357system.cpu3.iq.FU_type_0::total 248749 # Type of FU issued 2358system.cpu3.iq.rate 1.405219 # Inst issue rate 2359system.cpu3.iq.fu_busy_cnt 263 # FU busy when requested 2360system.cpu3.iq.fu_busy_rate 0.001057 # FU busy rate (busy events/executed inst) 2361system.cpu3.iq.int_inst_queue_reads 673451 # Number of integer instruction queue reads 2362system.cpu3.iq.int_inst_queue_writes 263132 # Number of integer instruction queue writes 2363system.cpu3.iq.int_inst_queue_wakeup_accesses 246950 # Number of integer instruction queue wakeup accesses | 2464system.cpu3.iq.FU_type_0::total 248738 # Type of FU issued 2465system.cpu3.iq.rate 1.405855 # Inst issue rate 2466system.cpu3.iq.fu_busy_cnt 264 # FU busy when requested 2467system.cpu3.iq.fu_busy_rate 0.001061 # FU busy rate (busy events/executed inst) 2468system.cpu3.iq.int_inst_queue_reads 673341 # Number of integer instruction queue reads 2469system.cpu3.iq.int_inst_queue_writes 263119 # Number of integer instruction queue writes 2470system.cpu3.iq.int_inst_queue_wakeup_accesses 246940 # Number of integer instruction queue wakeup accesses |
| 2364system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 2365system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 2366system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 2471system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 2472system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 2473system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 2367system.cpu3.iq.int_alu_accesses 249012 # Number of integer alu accesses | 2474system.cpu3.iq.int_alu_accesses 249002 # Number of integer alu accesses |
| 2368system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses | 2475system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses |
| 2369system.cpu3.iew.lsq.thread0.forwLoads 35153 # Number of loads that had data forwarded from stores | 2476system.cpu3.iew.lsq.thread0.forwLoads 35155 # Number of loads that had data forwarded from stores |
| 2370system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2371system.cpu3.iew.lsq.thread0.squashedLoads 2247 # Number of loads squashed 2372system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 2373system.cpu3.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations 2374system.cpu3.iew.lsq.thread0.squashedStores 1385 # Number of stores squashed 2375system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2376system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2377system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 2378system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 2379system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2380system.cpu3.iew.iewSquashCycles 2300 # Number of cycles IEW is squashing | 2477system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2478system.cpu3.iew.lsq.thread0.squashedLoads 2247 # Number of loads squashed 2479system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 2480system.cpu3.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations 2481system.cpu3.iew.lsq.thread0.squashedStores 1385 # Number of stores squashed 2482system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2483system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2484system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 2485system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 2486system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2487system.cpu3.iew.iewSquashCycles 2300 # Number of cycles IEW is squashing |
| 2381system.cpu3.iew.iewBlockCycles 645 # Number of cycles IEW is blocking | 2488system.cpu3.iew.iewBlockCycles 643 # Number of cycles IEW is blocking |
| 2382system.cpu3.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking | 2489system.cpu3.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking |
| 2383system.cpu3.iew.iewDispatchedInsts 294144 # Number of instructions dispatched to IQ | 2490system.cpu3.iew.iewDispatchedInsts 294126 # Number of instructions dispatched to IQ |
| 2384system.cpu3.iew.iewDispSquashedInsts 354 # Number of squashed instructions skipped by dispatch | 2491system.cpu3.iew.iewDispSquashedInsts 354 # Number of squashed instructions skipped by dispatch |
| 2385system.cpu3.iew.iewDispLoadInsts 84726 # Number of dispatched load instructions 2386system.cpu3.iew.iewDispStoreInsts 40382 # Number of dispatched store instructions | 2492system.cpu3.iew.iewDispLoadInsts 84722 # Number of dispatched load instructions 2493system.cpu3.iew.iewDispStoreInsts 40383 # Number of dispatched store instructions |
| 2387system.cpu3.iew.iewDispNonSpecInsts 1060 # Number of dispatched non-speculative instructions 2388system.cpu3.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall 2389system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 2390system.cpu3.iew.memOrderViolationEvents 38 # Number of memory order violations 2391system.cpu3.iew.predictedTakenIncorrect 459 # Number of branches that were predicted taken incorrectly 2392system.cpu3.iew.predictedNotTakenIncorrect 919 # Number of branches that were predicted not taken incorrectly 2393system.cpu3.iew.branchMispredicts 1378 # Number of branch mispredicts detected at execute | 2494system.cpu3.iew.iewDispNonSpecInsts 1060 # Number of dispatched non-speculative instructions 2495system.cpu3.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall 2496system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 2497system.cpu3.iew.memOrderViolationEvents 38 # Number of memory order violations 2498system.cpu3.iew.predictedTakenIncorrect 459 # Number of branches that were predicted taken incorrectly 2499system.cpu3.iew.predictedNotTakenIncorrect 919 # Number of branches that were predicted not taken incorrectly 2500system.cpu3.iew.branchMispredicts 1378 # Number of branch mispredicts detected at execute |
| 2394system.cpu3.iew.iewExecutedInsts 247595 # Number of executed instructions 2395system.cpu3.iew.iewExecLoadInsts 83855 # Number of load instructions executed | 2501system.cpu3.iew.iewExecutedInsts 247584 # Number of executed instructions 2502system.cpu3.iew.iewExecLoadInsts 83851 # Number of load instructions executed |
| 2396system.cpu3.iew.iewExecSquashedInsts 1154 # Number of squashed instructions skipped in execute 2397system.cpu3.iew.exec_swp 0 # number of swp insts executed | 2503system.cpu3.iew.iewExecSquashedInsts 1154 # Number of squashed instructions skipped in execute 2504system.cpu3.iew.exec_swp 0 # number of swp insts executed |
| 2398system.cpu3.iew.exec_nop 41463 # number of nop insts executed 2399system.cpu3.iew.exec_refs 123509 # number of memory reference insts executed 2400system.cpu3.iew.exec_branches 50804 # Number of branches executed 2401system.cpu3.iew.exec_stores 39654 # Number of stores executed 2402system.cpu3.iew.exec_rate 1.398700 # Inst execution rate 2403system.cpu3.iew.wb_sent 247239 # cumulative count of insts sent to commit 2404system.cpu3.iew.wb_count 246950 # cumulative count of insts written-back 2405system.cpu3.iew.wb_producers 140249 # num instructions producing a value 2406system.cpu3.iew.wb_consumers 144916 # num instructions consuming a value | 2505system.cpu3.iew.exec_nop 41458 # number of nop insts executed 2506system.cpu3.iew.exec_refs 123507 # number of memory reference insts executed 2507system.cpu3.iew.exec_branches 50799 # Number of branches executed 2508system.cpu3.iew.exec_stores 39656 # Number of stores executed 2509system.cpu3.iew.exec_rate 1.399333 # Inst execution rate 2510system.cpu3.iew.wb_sent 247229 # cumulative count of insts sent to commit 2511system.cpu3.iew.wb_count 246940 # cumulative count of insts written-back 2512system.cpu3.iew.wb_producers 140247 # num instructions producing a value 2513system.cpu3.iew.wb_consumers 144914 # num instructions consuming a value |
| 2407system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 2514system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 2408system.cpu3.iew.wb_rate 1.395056 # insts written-back per cycle | 2515system.cpu3.iew.wb_rate 1.395693 # insts written-back per cycle |
| 2409system.cpu3.iew.wb_fanout 0.967795 # average fanout of values written-back 2410system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 2411system.cpu3.commit.commitSquashedInsts 11951 # The number of squashed insts skipped by commit | 2516system.cpu3.iew.wb_fanout 0.967795 # average fanout of values written-back 2517system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 2518system.cpu3.commit.commitSquashedInsts 11951 # The number of squashed insts skipped by commit |
| 2412system.cpu3.commit.commitNonSpecStalls 5695 # The number of times commit has been forced to stall to communicate backwards | 2519system.cpu3.commit.commitNonSpecStalls 5689 # The number of times commit has been forced to stall to communicate backwards |
| 2413system.cpu3.commit.branchMispredicts 1265 # The number of times a branch was mispredicted | 2520system.cpu3.commit.branchMispredicts 1265 # The number of times a branch was mispredicted |
| 2414system.cpu3.commit.committed_per_cycle::samples 165578 # Number of insts commited each cycle 2415system.cpu3.commit.committed_per_cycle::mean 1.704170 # Number of insts commited each cycle 2416system.cpu3.commit.committed_per_cycle::stdev 2.038930 # Number of insts commited each cycle | 2521system.cpu3.commit.committed_per_cycle::samples 165494 # Number of insts commited each cycle 2522system.cpu3.commit.committed_per_cycle::mean 1.704926 # Number of insts commited each cycle 2523system.cpu3.commit.committed_per_cycle::stdev 2.039126 # Number of insts commited each cycle |
| 2417system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 2524system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 2418system.cpu3.commit.committed_per_cycle::0 64386 38.89% 38.89% # Number of insts commited each cycle 2419system.cpu3.commit.committed_per_cycle::1 48906 29.54% 68.42% # Number of insts commited each cycle 2420system.cpu3.commit.committed_per_cycle::2 6087 3.68% 72.10% # Number of insts commited each cycle 2421system.cpu3.commit.committed_per_cycle::3 6642 4.01% 76.11% # Number of insts commited each cycle 2422system.cpu3.commit.committed_per_cycle::4 1574 0.95% 77.06% # Number of insts commited each cycle 2423system.cpu3.commit.committed_per_cycle::5 35662 21.54% 98.60% # Number of insts commited each cycle | 2525system.cpu3.commit.committed_per_cycle::0 64312 38.86% 38.86% # Number of insts commited each cycle 2526system.cpu3.commit.committed_per_cycle::1 48901 29.55% 68.41% # Number of insts commited each cycle 2527system.cpu3.commit.committed_per_cycle::2 6087 3.68% 72.09% # Number of insts commited each cycle 2528system.cpu3.commit.committed_per_cycle::3 6636 4.01% 76.10% # Number of insts commited each cycle 2529system.cpu3.commit.committed_per_cycle::4 1574 0.95% 77.05% # Number of insts commited each cycle 2530system.cpu3.commit.committed_per_cycle::5 35663 21.55% 98.60% # Number of insts commited each cycle |
| 2424system.cpu3.commit.committed_per_cycle::6 504 0.30% 98.90% # Number of insts commited each cycle 2425system.cpu3.commit.committed_per_cycle::7 999 0.60% 99.51% # Number of insts commited each cycle 2426system.cpu3.commit.committed_per_cycle::8 818 0.49% 100.00% # Number of insts commited each cycle 2427system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2428system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2429system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 2531system.cpu3.commit.committed_per_cycle::6 504 0.30% 98.90% # Number of insts commited each cycle 2532system.cpu3.commit.committed_per_cycle::7 999 0.60% 99.51% # Number of insts commited each cycle 2533system.cpu3.commit.committed_per_cycle::8 818 0.49% 100.00% # Number of insts commited each cycle 2534system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2535system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2536system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 2430system.cpu3.commit.committed_per_cycle::total 165578 # Number of insts commited each cycle 2431system.cpu3.commit.committedInsts 282173 # Number of instructions committed 2432system.cpu3.commit.committedOps 282173 # Number of ops (including micro ops) committed | 2537system.cpu3.commit.committed_per_cycle::total 165494 # Number of insts commited each cycle 2538system.cpu3.commit.committedInsts 282155 # Number of instructions committed 2539system.cpu3.commit.committedOps 282155 # Number of ops (including micro ops) committed |
| 2433system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed | 2540system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed |
| 2434system.cpu3.commit.refs 121476 # Number of memory references committed 2435system.cpu3.commit.loads 82479 # Number of loads committed 2436system.cpu3.commit.membars 4985 # Number of memory barriers committed 2437system.cpu3.commit.branches 49947 # Number of branches committed | 2541system.cpu3.commit.refs 121473 # Number of memory references committed 2542system.cpu3.commit.loads 82475 # Number of loads committed 2543system.cpu3.commit.membars 4979 # Number of memory barriers committed 2544system.cpu3.commit.branches 49942 # Number of branches committed |
| 2438system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. | 2545system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. |
| 2439system.cpu3.commit.int_insts 193548 # Number of committed integer instructions. | 2546system.cpu3.commit.int_insts 193540 # Number of committed integer instructions. |
| 2440system.cpu3.commit.function_calls 322 # Number of function calls committed. | 2547system.cpu3.commit.function_calls 322 # Number of function calls committed. |
| 2548system.cpu3.commit.op_class_0::No_OpClass 40736 14.44% 14.44% # Class of committed instruction 2549system.cpu3.commit.op_class_0::IntAlu 114967 40.75% 55.18% # Class of committed instruction 2550system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.18% # Class of committed instruction 2551system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.18% # Class of committed instruction 2552system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.18% # Class of committed instruction 2553system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.18% # Class of committed instruction 2554system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.18% # Class of committed instruction 2555system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.18% # Class of committed instruction 2556system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.18% # Class of committed instruction 2557system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.18% # Class of committed instruction 2558system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.18% # Class of committed instruction 2559system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.18% # Class of committed instruction 2560system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.18% # Class of committed instruction 2561system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.18% # Class of committed instruction 2562system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.18% # Class of committed instruction 2563system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.18% # Class of committed instruction 2564system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.18% # Class of committed instruction 2565system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.18% # Class of committed instruction 2566system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.18% # Class of committed instruction 2567system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.18% # Class of committed instruction 2568system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.18% # Class of committed instruction 2569system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.18% # Class of committed instruction 2570system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.18% # Class of committed instruction 2571system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.18% # Class of committed instruction 2572system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.18% # Class of committed instruction 2573system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.18% # Class of committed instruction 2574system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.18% # Class of committed instruction 2575system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.18% # Class of committed instruction 2576system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.18% # Class of committed instruction 2577system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.18% # Class of committed instruction 2578system.cpu3.commit.op_class_0::MemRead 87454 31.00% 86.18% # Class of committed instruction 2579system.cpu3.commit.op_class_0::MemWrite 38998 13.82% 100.00% # Class of committed instruction 2580system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2581system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2582system.cpu3.commit.op_class_0::total 282155 # Class of committed instruction |
|
| 2441system.cpu3.commit.bw_lim_events 818 # number cycles where commit BW limit reached 2442system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits | 2583system.cpu3.commit.bw_lim_events 818 # number cycles where commit BW limit reached 2584system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 2443system.cpu3.rob.rob_reads 458297 # The number of ROB reads 2444system.cpu3.rob.rob_writes 590554 # The number of ROB writes | 2585system.cpu3.rob.rob_reads 458195 # The number of ROB reads 2586system.cpu3.rob.rob_writes 590518 # The number of ROB writes |
| 2445system.cpu3.timesIdled 210 # Number of times that the entire CPU went into an idle state and unscheduled itself | 2587system.cpu3.timesIdled 210 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 2446system.cpu3.idleCycles 1385 # Total number of cycles that the CPU has spent unscheduled due to idling 2447system.cpu3.quiesceCycles 44892 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2448system.cpu3.committedInsts 236447 # Number of Instructions Simulated 2449system.cpu3.committedOps 236447 # Number of Ops (including micro ops) Simulated 2450system.cpu3.committedInsts_total 236447 # Number of Instructions Simulated 2451system.cpu3.cpi 0.748658 # CPI: Cycles Per Instruction 2452system.cpu3.cpi_total 0.748658 # CPI: Total CPI of All Threads 2453system.cpu3.ipc 1.335723 # IPC: Instructions Per Cycle 2454system.cpu3.ipc_total 1.335723 # IPC: Total IPC of All Threads 2455system.cpu3.int_regfile_reads 429146 # number of integer regfile reads 2456system.cpu3.int_regfile_writes 199911 # number of integer regfile writes | 2588system.cpu3.idleCycles 1387 # Total number of cycles that the CPU has spent unscheduled due to idling 2589system.cpu3.quiesceCycles 44814 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2590system.cpu3.committedInsts 236440 # Number of Instructions Simulated 2591system.cpu3.committedOps 236440 # Number of Ops (including micro ops) Simulated 2592system.cpu3.committedInsts_total 236440 # Number of Instructions Simulated 2593system.cpu3.cpi 0.748308 # CPI: Cycles Per Instruction 2594system.cpu3.cpi_total 0.748308 # CPI: Total CPI of All Threads 2595system.cpu3.ipc 1.336348 # IPC: Instructions Per Cycle 2596system.cpu3.ipc_total 1.336348 # IPC: Total IPC of All Threads 2597system.cpu3.int_regfile_reads 429141 # number of integer regfile reads 2598system.cpu3.int_regfile_writes 199912 # number of integer regfile writes |
| 2457system.cpu3.fp_regfile_writes 64 # number of floating regfile writes | 2599system.cpu3.fp_regfile_writes 64 # number of floating regfile writes |
| 2458system.cpu3.misc_regfile_reads 125103 # number of misc regfile reads | 2600system.cpu3.misc_regfile_reads 125101 # number of misc regfile reads |
| 2459system.cpu3.misc_regfile_writes 648 # number of misc regfile writes 2460system.cpu3.icache.tags.replacements 319 # number of replacements | 2601system.cpu3.misc_regfile_writes 648 # number of misc regfile writes 2602system.cpu3.icache.tags.replacements 319 # number of replacements |
| 2461system.cpu3.icache.tags.tagsinuse 80.480006 # Cycle average of tags in use 2462system.cpu3.icache.tags.total_refs 19114 # Total number of references to valid blocks. | 2603system.cpu3.icache.tags.tagsinuse 80.524551 # Cycle average of tags in use 2604system.cpu3.icache.tags.total_refs 19102 # Total number of references to valid blocks. |
| 2463system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks. | 2605system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks. |
| 2464system.cpu3.icache.tags.avg_refs 44.451163 # Average number of references to valid blocks. | 2606system.cpu3.icache.tags.avg_refs 44.423256 # Average number of references to valid blocks. |
| 2465system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2607system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 2466system.cpu3.icache.tags.occ_blocks::cpu3.inst 80.480006 # Average occupied blocks per requestor 2467system.cpu3.icache.tags.occ_percent::cpu3.inst 0.157188 # Average percentage of cache occupancy 2468system.cpu3.icache.tags.occ_percent::total 0.157188 # Average percentage of cache occupancy | 2608system.cpu3.icache.tags.occ_blocks::cpu3.inst 80.524551 # Average occupied blocks per requestor 2609system.cpu3.icache.tags.occ_percent::cpu3.inst 0.157275 # Average percentage of cache occupancy 2610system.cpu3.icache.tags.occ_percent::total 0.157275 # Average percentage of cache occupancy |
| 2469system.cpu3.icache.tags.occ_task_id_blocks::1024 111 # Occupied blocks per task id 2470system.cpu3.icache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id 2471system.cpu3.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id 2472system.cpu3.icache.tags.occ_task_id_percent::1024 0.216797 # Percentage of cache occupancy per task id | 2611system.cpu3.icache.tags.occ_task_id_blocks::1024 111 # Occupied blocks per task id 2612system.cpu3.icache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id 2613system.cpu3.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id 2614system.cpu3.icache.tags.occ_task_id_percent::1024 0.216797 # Percentage of cache occupancy per task id |
| 2473system.cpu3.icache.tags.tag_accesses 20019 # Number of tag accesses 2474system.cpu3.icache.tags.data_accesses 20019 # Number of data accesses 2475system.cpu3.icache.ReadReq_hits::cpu3.inst 19114 # number of ReadReq hits 2476system.cpu3.icache.ReadReq_hits::total 19114 # number of ReadReq hits 2477system.cpu3.icache.demand_hits::cpu3.inst 19114 # number of demand (read+write) hits 2478system.cpu3.icache.demand_hits::total 19114 # number of demand (read+write) hits 2479system.cpu3.icache.overall_hits::cpu3.inst 19114 # number of overall hits 2480system.cpu3.icache.overall_hits::total 19114 # number of overall hits | 2615system.cpu3.icache.tags.tag_accesses 20007 # Number of tag accesses 2616system.cpu3.icache.tags.data_accesses 20007 # Number of data accesses 2617system.cpu3.icache.ReadReq_hits::cpu3.inst 19102 # number of ReadReq hits 2618system.cpu3.icache.ReadReq_hits::total 19102 # number of ReadReq hits 2619system.cpu3.icache.demand_hits::cpu3.inst 19102 # number of demand (read+write) hits 2620system.cpu3.icache.demand_hits::total 19102 # number of demand (read+write) hits 2621system.cpu3.icache.overall_hits::cpu3.inst 19102 # number of overall hits 2622system.cpu3.icache.overall_hits::total 19102 # number of overall hits |
| 2481system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses 2482system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses 2483system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses 2484system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses 2485system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses 2486system.cpu3.icache.overall_misses::total 475 # number of overall misses 2487system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6525745 # number of ReadReq miss cycles 2488system.cpu3.icache.ReadReq_miss_latency::total 6525745 # number of ReadReq miss cycles 2489system.cpu3.icache.demand_miss_latency::cpu3.inst 6525745 # number of demand (read+write) miss cycles 2490system.cpu3.icache.demand_miss_latency::total 6525745 # number of demand (read+write) miss cycles 2491system.cpu3.icache.overall_miss_latency::cpu3.inst 6525745 # number of overall miss cycles 2492system.cpu3.icache.overall_miss_latency::total 6525745 # number of overall miss cycles | 2623system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses 2624system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses 2625system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses 2626system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses 2627system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses 2628system.cpu3.icache.overall_misses::total 475 # number of overall misses 2629system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6525745 # number of ReadReq miss cycles 2630system.cpu3.icache.ReadReq_miss_latency::total 6525745 # number of ReadReq miss cycles 2631system.cpu3.icache.demand_miss_latency::cpu3.inst 6525745 # number of demand (read+write) miss cycles 2632system.cpu3.icache.demand_miss_latency::total 6525745 # number of demand (read+write) miss cycles 2633system.cpu3.icache.overall_miss_latency::cpu3.inst 6525745 # number of overall miss cycles 2634system.cpu3.icache.overall_miss_latency::total 6525745 # number of overall miss cycles |
| 2493system.cpu3.icache.ReadReq_accesses::cpu3.inst 19589 # number of ReadReq accesses(hits+misses) 2494system.cpu3.icache.ReadReq_accesses::total 19589 # number of ReadReq accesses(hits+misses) 2495system.cpu3.icache.demand_accesses::cpu3.inst 19589 # number of demand (read+write) accesses 2496system.cpu3.icache.demand_accesses::total 19589 # number of demand (read+write) accesses 2497system.cpu3.icache.overall_accesses::cpu3.inst 19589 # number of overall (read+write) accesses 2498system.cpu3.icache.overall_accesses::total 19589 # number of overall (read+write) accesses 2499system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.024248 # miss rate for ReadReq accesses 2500system.cpu3.icache.ReadReq_miss_rate::total 0.024248 # miss rate for ReadReq accesses 2501system.cpu3.icache.demand_miss_rate::cpu3.inst 0.024248 # miss rate for demand accesses 2502system.cpu3.icache.demand_miss_rate::total 0.024248 # miss rate for demand accesses 2503system.cpu3.icache.overall_miss_rate::cpu3.inst 0.024248 # miss rate for overall accesses 2504system.cpu3.icache.overall_miss_rate::total 0.024248 # miss rate for overall accesses | 2635system.cpu3.icache.ReadReq_accesses::cpu3.inst 19577 # number of ReadReq accesses(hits+misses) 2636system.cpu3.icache.ReadReq_accesses::total 19577 # number of ReadReq accesses(hits+misses) 2637system.cpu3.icache.demand_accesses::cpu3.inst 19577 # number of demand (read+write) accesses 2638system.cpu3.icache.demand_accesses::total 19577 # number of demand (read+write) accesses 2639system.cpu3.icache.overall_accesses::cpu3.inst 19577 # number of overall (read+write) accesses 2640system.cpu3.icache.overall_accesses::total 19577 # number of overall (read+write) accesses 2641system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.024263 # miss rate for ReadReq accesses 2642system.cpu3.icache.ReadReq_miss_rate::total 0.024263 # miss rate for ReadReq accesses 2643system.cpu3.icache.demand_miss_rate::cpu3.inst 0.024263 # miss rate for demand accesses 2644system.cpu3.icache.demand_miss_rate::total 0.024263 # miss rate for demand accesses 2645system.cpu3.icache.overall_miss_rate::cpu3.inst 0.024263 # miss rate for overall accesses 2646system.cpu3.icache.overall_miss_rate::total 0.024263 # miss rate for overall accesses |
| 2505system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13738.410526 # average ReadReq miss latency 2506system.cpu3.icache.ReadReq_avg_miss_latency::total 13738.410526 # average ReadReq miss latency 2507system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13738.410526 # average overall miss latency 2508system.cpu3.icache.demand_avg_miss_latency::total 13738.410526 # average overall miss latency 2509system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13738.410526 # average overall miss latency 2510system.cpu3.icache.overall_avg_miss_latency::total 13738.410526 # average overall miss latency 2511system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2512system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked --- 16 unchanged lines hidden (view full) --- 2529system.cpu3.icache.overall_mshr_misses::cpu3.inst 430 # number of overall MSHR misses 2530system.cpu3.icache.overall_mshr_misses::total 430 # number of overall MSHR misses 2531system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5298255 # number of ReadReq MSHR miss cycles 2532system.cpu3.icache.ReadReq_mshr_miss_latency::total 5298255 # number of ReadReq MSHR miss cycles 2533system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5298255 # number of demand (read+write) MSHR miss cycles 2534system.cpu3.icache.demand_mshr_miss_latency::total 5298255 # number of demand (read+write) MSHR miss cycles 2535system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5298255 # number of overall MSHR miss cycles 2536system.cpu3.icache.overall_mshr_miss_latency::total 5298255 # number of overall MSHR miss cycles | 2647system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13738.410526 # average ReadReq miss latency 2648system.cpu3.icache.ReadReq_avg_miss_latency::total 13738.410526 # average ReadReq miss latency 2649system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13738.410526 # average overall miss latency 2650system.cpu3.icache.demand_avg_miss_latency::total 13738.410526 # average overall miss latency 2651system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13738.410526 # average overall miss latency 2652system.cpu3.icache.overall_avg_miss_latency::total 13738.410526 # average overall miss latency 2653system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2654system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked --- 16 unchanged lines hidden (view full) --- 2671system.cpu3.icache.overall_mshr_misses::cpu3.inst 430 # number of overall MSHR misses 2672system.cpu3.icache.overall_mshr_misses::total 430 # number of overall MSHR misses 2673system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5298255 # number of ReadReq MSHR miss cycles 2674system.cpu3.icache.ReadReq_mshr_miss_latency::total 5298255 # number of ReadReq MSHR miss cycles 2675system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5298255 # number of demand (read+write) MSHR miss cycles 2676system.cpu3.icache.demand_mshr_miss_latency::total 5298255 # number of demand (read+write) MSHR miss cycles 2677system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5298255 # number of overall MSHR miss cycles 2678system.cpu3.icache.overall_mshr_miss_latency::total 5298255 # number of overall MSHR miss cycles |
| 2537system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.021951 # mshr miss rate for ReadReq accesses 2538system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.021951 # mshr miss rate for ReadReq accesses 2539system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.021951 # mshr miss rate for demand accesses 2540system.cpu3.icache.demand_mshr_miss_rate::total 0.021951 # mshr miss rate for demand accesses 2541system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.021951 # mshr miss rate for overall accesses 2542system.cpu3.icache.overall_mshr_miss_rate::total 0.021951 # mshr miss rate for overall accesses | 2679system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.021965 # mshr miss rate for ReadReq accesses 2680system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.021965 # mshr miss rate for ReadReq accesses 2681system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.021965 # mshr miss rate for demand accesses 2682system.cpu3.icache.demand_mshr_miss_rate::total 0.021965 # mshr miss rate for demand accesses 2683system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.021965 # mshr miss rate for overall accesses 2684system.cpu3.icache.overall_mshr_miss_rate::total 0.021965 # mshr miss rate for overall accesses |
| 2543system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12321.523256 # average ReadReq mshr miss latency 2544system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12321.523256 # average ReadReq mshr miss latency 2545system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12321.523256 # average overall mshr miss latency 2546system.cpu3.icache.demand_avg_mshr_miss_latency::total 12321.523256 # average overall mshr miss latency 2547system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12321.523256 # average overall mshr miss latency 2548system.cpu3.icache.overall_avg_mshr_miss_latency::total 12321.523256 # average overall mshr miss latency 2549system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2550system.cpu3.dcache.tags.replacements 0 # number of replacements | 2685system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12321.523256 # average ReadReq mshr miss latency 2686system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12321.523256 # average ReadReq mshr miss latency 2687system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12321.523256 # average overall mshr miss latency 2688system.cpu3.icache.demand_avg_mshr_miss_latency::total 12321.523256 # average overall mshr miss latency 2689system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12321.523256 # average overall mshr miss latency 2690system.cpu3.icache.overall_avg_mshr_miss_latency::total 12321.523256 # average overall mshr miss latency 2691system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2692system.cpu3.dcache.tags.replacements 0 # number of replacements |
| 2551system.cpu3.dcache.tags.tagsinuse 24.751493 # Cycle average of tags in use 2552system.cpu3.dcache.tags.total_refs 44991 # Total number of references to valid blocks. | 2693system.cpu3.dcache.tags.tagsinuse 24.706550 # Cycle average of tags in use 2694system.cpu3.dcache.tags.total_refs 44992 # Total number of references to valid blocks. |
| 2553system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. | 2695system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. |
| 2554system.cpu3.dcache.tags.avg_refs 1606.821429 # Average number of references to valid blocks. | 2696system.cpu3.dcache.tags.avg_refs 1606.857143 # Average number of references to valid blocks. |
| 2555system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2697system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 2556system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.751493 # Average occupied blocks per requestor 2557system.cpu3.dcache.tags.occ_percent::cpu3.data 0.048343 # Average percentage of cache occupancy 2558system.cpu3.dcache.tags.occ_percent::total 0.048343 # Average percentage of cache occupancy | 2698system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.706550 # Average occupied blocks per requestor 2699system.cpu3.dcache.tags.occ_percent::cpu3.data 0.048255 # Average percentage of cache occupancy 2700system.cpu3.dcache.tags.occ_percent::total 0.048255 # Average percentage of cache occupancy |
| 2559system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id 2560system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 2561system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id | 2701system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id 2702system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 2703system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id |
| 2562system.cpu3.dcache.tags.tag_accesses 350966 # Number of tag accesses 2563system.cpu3.dcache.tags.data_accesses 350966 # Number of data accesses 2564system.cpu3.dcache.ReadReq_hits::cpu3.data 48333 # number of ReadReq hits 2565system.cpu3.dcache.ReadReq_hits::total 48333 # number of ReadReq hits 2566system.cpu3.dcache.WriteReq_hits::cpu3.data 38794 # number of WriteReq hits 2567system.cpu3.dcache.WriteReq_hits::total 38794 # number of WriteReq hits | 2704system.cpu3.dcache.tags.tag_accesses 350946 # Number of tag accesses 2705system.cpu3.dcache.tags.data_accesses 350946 # Number of data accesses 2706system.cpu3.dcache.ReadReq_hits::cpu3.data 48327 # number of ReadReq hits 2707system.cpu3.dcache.ReadReq_hits::total 48327 # number of ReadReq hits 2708system.cpu3.dcache.WriteReq_hits::cpu3.data 38795 # number of WriteReq hits 2709system.cpu3.dcache.WriteReq_hits::total 38795 # number of WriteReq hits |
| 2568system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits 2569system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits | 2710system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits 2711system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits |
| 2570system.cpu3.dcache.demand_hits::cpu3.data 87127 # number of demand (read+write) hits 2571system.cpu3.dcache.demand_hits::total 87127 # number of demand (read+write) hits 2572system.cpu3.dcache.overall_hits::cpu3.data 87127 # number of overall hits 2573system.cpu3.dcache.overall_hits::total 87127 # number of overall hits | 2712system.cpu3.dcache.demand_hits::cpu3.data 87122 # number of demand (read+write) hits 2713system.cpu3.dcache.demand_hits::total 87122 # number of demand (read+write) hits 2714system.cpu3.dcache.overall_hits::cpu3.data 87122 # number of overall hits 2715system.cpu3.dcache.overall_hits::total 87122 # number of overall hits |
| 2574system.cpu3.dcache.ReadReq_misses::cpu3.data 351 # number of ReadReq misses 2575system.cpu3.dcache.ReadReq_misses::total 351 # number of ReadReq misses 2576system.cpu3.dcache.WriteReq_misses::cpu3.data 139 # number of WriteReq misses 2577system.cpu3.dcache.WriteReq_misses::total 139 # number of WriteReq misses 2578system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses 2579system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses 2580system.cpu3.dcache.demand_misses::cpu3.data 490 # number of demand (read+write) misses 2581system.cpu3.dcache.demand_misses::total 490 # number of demand (read+write) misses 2582system.cpu3.dcache.overall_misses::cpu3.data 490 # number of overall misses 2583system.cpu3.dcache.overall_misses::total 490 # number of overall misses | 2716system.cpu3.dcache.ReadReq_misses::cpu3.data 351 # number of ReadReq misses 2717system.cpu3.dcache.ReadReq_misses::total 351 # number of ReadReq misses 2718system.cpu3.dcache.WriteReq_misses::cpu3.data 139 # number of WriteReq misses 2719system.cpu3.dcache.WriteReq_misses::total 139 # number of WriteReq misses 2720system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses 2721system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses 2722system.cpu3.dcache.demand_misses::cpu3.data 490 # number of demand (read+write) misses 2723system.cpu3.dcache.demand_misses::total 490 # number of demand (read+write) misses 2724system.cpu3.dcache.overall_misses::cpu3.data 490 # number of overall misses 2725system.cpu3.dcache.overall_misses::total 490 # number of overall misses |
| 2584system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4639136 # number of ReadReq miss cycles 2585system.cpu3.dcache.ReadReq_miss_latency::total 4639136 # number of ReadReq miss cycles 2586system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3479012 # number of WriteReq miss cycles 2587system.cpu3.dcache.WriteReq_miss_latency::total 3479012 # number of WriteReq miss cycles 2588system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 512008 # number of SwapReq miss cycles 2589system.cpu3.dcache.SwapReq_miss_latency::total 512008 # number of SwapReq miss cycles 2590system.cpu3.dcache.demand_miss_latency::cpu3.data 8118148 # number of demand (read+write) miss cycles 2591system.cpu3.dcache.demand_miss_latency::total 8118148 # number of demand (read+write) miss cycles 2592system.cpu3.dcache.overall_miss_latency::cpu3.data 8118148 # number of overall miss cycles 2593system.cpu3.dcache.overall_miss_latency::total 8118148 # number of overall miss cycles 2594system.cpu3.dcache.ReadReq_accesses::cpu3.data 48684 # number of ReadReq accesses(hits+misses) 2595system.cpu3.dcache.ReadReq_accesses::total 48684 # number of ReadReq accesses(hits+misses) 2596system.cpu3.dcache.WriteReq_accesses::cpu3.data 38933 # number of WriteReq accesses(hits+misses) 2597system.cpu3.dcache.WriteReq_accesses::total 38933 # number of WriteReq accesses(hits+misses) | 2726system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4621144 # number of ReadReq miss cycles 2727system.cpu3.dcache.ReadReq_miss_latency::total 4621144 # number of ReadReq miss cycles 2728system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3311512 # number of WriteReq miss cycles 2729system.cpu3.dcache.WriteReq_miss_latency::total 3311512 # number of WriteReq miss cycles 2730system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 513008 # number of SwapReq miss cycles 2731system.cpu3.dcache.SwapReq_miss_latency::total 513008 # number of SwapReq miss cycles 2732system.cpu3.dcache.demand_miss_latency::cpu3.data 7932656 # number of demand (read+write) miss cycles 2733system.cpu3.dcache.demand_miss_latency::total 7932656 # number of demand (read+write) miss cycles 2734system.cpu3.dcache.overall_miss_latency::cpu3.data 7932656 # number of overall miss cycles 2735system.cpu3.dcache.overall_miss_latency::total 7932656 # number of overall miss cycles 2736system.cpu3.dcache.ReadReq_accesses::cpu3.data 48678 # number of ReadReq accesses(hits+misses) 2737system.cpu3.dcache.ReadReq_accesses::total 48678 # number of ReadReq accesses(hits+misses) 2738system.cpu3.dcache.WriteReq_accesses::cpu3.data 38934 # number of WriteReq accesses(hits+misses) 2739system.cpu3.dcache.WriteReq_accesses::total 38934 # number of WriteReq accesses(hits+misses) |
| 2598system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses) 2599system.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses) | 2740system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses) 2741system.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses) |
| 2600system.cpu3.dcache.demand_accesses::cpu3.data 87617 # number of demand (read+write) accesses 2601system.cpu3.dcache.demand_accesses::total 87617 # number of demand (read+write) accesses 2602system.cpu3.dcache.overall_accesses::cpu3.data 87617 # number of overall (read+write) accesses 2603system.cpu3.dcache.overall_accesses::total 87617 # number of overall (read+write) accesses 2604system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.007210 # miss rate for ReadReq accesses 2605system.cpu3.dcache.ReadReq_miss_rate::total 0.007210 # miss rate for ReadReq accesses | 2742system.cpu3.dcache.demand_accesses::cpu3.data 87612 # number of demand (read+write) accesses 2743system.cpu3.dcache.demand_accesses::total 87612 # number of demand (read+write) accesses 2744system.cpu3.dcache.overall_accesses::cpu3.data 87612 # number of overall (read+write) accesses 2745system.cpu3.dcache.overall_accesses::total 87612 # number of overall (read+write) accesses 2746system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.007211 # miss rate for ReadReq accesses 2747system.cpu3.dcache.ReadReq_miss_rate::total 0.007211 # miss rate for ReadReq accesses |
| 2606system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003570 # miss rate for WriteReq accesses 2607system.cpu3.dcache.WriteReq_miss_rate::total 0.003570 # miss rate for WriteReq accesses 2608system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.812500 # miss rate for SwapReq accesses 2609system.cpu3.dcache.SwapReq_miss_rate::total 0.812500 # miss rate for SwapReq accesses 2610system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005593 # miss rate for demand accesses 2611system.cpu3.dcache.demand_miss_rate::total 0.005593 # miss rate for demand accesses 2612system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005593 # miss rate for overall accesses 2613system.cpu3.dcache.overall_miss_rate::total 0.005593 # miss rate for overall accesses | 2748system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003570 # miss rate for WriteReq accesses 2749system.cpu3.dcache.WriteReq_miss_rate::total 0.003570 # miss rate for WriteReq accesses 2750system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.812500 # miss rate for SwapReq accesses 2751system.cpu3.dcache.SwapReq_miss_rate::total 0.812500 # miss rate for SwapReq accesses 2752system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005593 # miss rate for demand accesses 2753system.cpu3.dcache.demand_miss_rate::total 0.005593 # miss rate for demand accesses 2754system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005593 # miss rate for overall accesses 2755system.cpu3.dcache.overall_miss_rate::total 0.005593 # miss rate for overall accesses |
| 2614system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 13216.911681 # average ReadReq miss latency 2615system.cpu3.dcache.ReadReq_avg_miss_latency::total 13216.911681 # average ReadReq miss latency 2616system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25028.863309 # average WriteReq miss latency 2617system.cpu3.dcache.WriteReq_avg_miss_latency::total 25028.863309 # average WriteReq miss latency 2618system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9846.307692 # average SwapReq miss latency 2619system.cpu3.dcache.SwapReq_avg_miss_latency::total 9846.307692 # average SwapReq miss latency 2620system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16567.648980 # average overall miss latency 2621system.cpu3.dcache.demand_avg_miss_latency::total 16567.648980 # average overall miss latency 2622system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16567.648980 # average overall miss latency 2623system.cpu3.dcache.overall_avg_miss_latency::total 16567.648980 # average overall miss latency | 2756system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 13165.652422 # average ReadReq miss latency 2757system.cpu3.dcache.ReadReq_avg_miss_latency::total 13165.652422 # average ReadReq miss latency 2758system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 23823.827338 # average WriteReq miss latency 2759system.cpu3.dcache.WriteReq_avg_miss_latency::total 23823.827338 # average WriteReq miss latency 2760system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9865.538462 # average SwapReq miss latency 2761system.cpu3.dcache.SwapReq_avg_miss_latency::total 9865.538462 # average SwapReq miss latency 2762system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16189.093878 # average overall miss latency 2763system.cpu3.dcache.demand_avg_miss_latency::total 16189.093878 # average overall miss latency 2764system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16189.093878 # average overall miss latency 2765system.cpu3.dcache.overall_avg_miss_latency::total 16189.093878 # average overall miss latency |
| 2624system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2625system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2626system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2627system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 2628system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2629system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2630system.cpu3.dcache.fast_writes 0 # number of fast writes performed 2631system.cpu3.dcache.cache_copies 0 # number of cache copies performed --- 10 unchanged lines hidden (view full) --- 2642system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106 # number of WriteReq MSHR misses 2643system.cpu3.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses 2644system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 52 # number of SwapReq MSHR misses 2645system.cpu3.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses 2646system.cpu3.dcache.demand_mshr_misses::cpu3.data 260 # number of demand (read+write) MSHR misses 2647system.cpu3.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses 2648system.cpu3.dcache.overall_mshr_misses::cpu3.data 260 # number of overall MSHR misses 2649system.cpu3.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses | 2766system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2767system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2768system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2769system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 2770system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2771system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2772system.cpu3.dcache.fast_writes 0 # number of fast writes performed 2773system.cpu3.dcache.cache_copies 0 # number of cache copies performed --- 10 unchanged lines hidden (view full) --- 2784system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106 # number of WriteReq MSHR misses 2785system.cpu3.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses 2786system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 52 # number of SwapReq MSHR misses 2787system.cpu3.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses 2788system.cpu3.dcache.demand_mshr_misses::cpu3.data 260 # number of demand (read+write) MSHR misses 2789system.cpu3.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses 2790system.cpu3.dcache.overall_mshr_misses::cpu3.data 260 # number of overall MSHR misses 2791system.cpu3.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses |
| 2650system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1051018 # number of ReadReq MSHR miss cycles 2651system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1051018 # number of ReadReq MSHR miss cycles 2652system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1439238 # number of WriteReq MSHR miss cycles 2653system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1439238 # number of WriteReq MSHR miss cycles 2654system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 407992 # number of SwapReq MSHR miss cycles 2655system.cpu3.dcache.SwapReq_mshr_miss_latency::total 407992 # number of SwapReq MSHR miss cycles 2656system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2490256 # number of demand (read+write) MSHR miss cycles 2657system.cpu3.dcache.demand_mshr_miss_latency::total 2490256 # number of demand (read+write) MSHR miss cycles 2658system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2490256 # number of overall MSHR miss cycles 2659system.cpu3.dcache.overall_mshr_miss_latency::total 2490256 # number of overall MSHR miss cycles 2660system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003163 # mshr miss rate for ReadReq accesses 2661system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003163 # mshr miss rate for ReadReq accesses | 2792system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1052517 # number of ReadReq MSHR miss cycles 2793system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1052517 # number of ReadReq MSHR miss cycles 2794system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1403488 # number of WriteReq MSHR miss cycles 2795system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1403488 # number of WriteReq MSHR miss cycles 2796system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 408992 # number of SwapReq MSHR miss cycles 2797system.cpu3.dcache.SwapReq_mshr_miss_latency::total 408992 # number of SwapReq MSHR miss cycles 2798system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2456005 # number of demand (read+write) MSHR miss cycles 2799system.cpu3.dcache.demand_mshr_miss_latency::total 2456005 # number of demand (read+write) MSHR miss cycles 2800system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2456005 # number of overall MSHR miss cycles 2801system.cpu3.dcache.overall_mshr_miss_latency::total 2456005 # number of overall MSHR miss cycles 2802system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003164 # mshr miss rate for ReadReq accesses 2803system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003164 # mshr miss rate for ReadReq accesses |
| 2662system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002723 # mshr miss rate for WriteReq accesses 2663system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002723 # mshr miss rate for WriteReq accesses 2664system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.812500 # mshr miss rate for SwapReq accesses 2665system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.812500 # mshr miss rate for SwapReq accesses | 2804system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002723 # mshr miss rate for WriteReq accesses 2805system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002723 # mshr miss rate for WriteReq accesses 2806system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.812500 # mshr miss rate for SwapReq accesses 2807system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.812500 # mshr miss rate for SwapReq accesses |
| 2666system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002967 # mshr miss rate for demand accesses 2667system.cpu3.dcache.demand_mshr_miss_rate::total 0.002967 # mshr miss rate for demand accesses 2668system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002967 # mshr miss rate for overall accesses 2669system.cpu3.dcache.overall_mshr_miss_rate::total 0.002967 # mshr miss rate for overall accesses 2670system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6824.792208 # average ReadReq mshr miss latency 2671system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6824.792208 # average ReadReq mshr miss latency 2672system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13577.716981 # average WriteReq mshr miss latency 2673system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13577.716981 # average WriteReq mshr miss latency 2674system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7846 # average SwapReq mshr miss latency 2675system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7846 # average SwapReq mshr miss latency 2676system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9577.907692 # average overall mshr miss latency 2677system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9577.907692 # average overall mshr miss latency 2678system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9577.907692 # average overall mshr miss latency 2679system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9577.907692 # average overall mshr miss latency | 2808system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002968 # mshr miss rate for demand accesses 2809system.cpu3.dcache.demand_mshr_miss_rate::total 0.002968 # mshr miss rate for demand accesses 2810system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002968 # mshr miss rate for overall accesses 2811system.cpu3.dcache.overall_mshr_miss_rate::total 0.002968 # mshr miss rate for overall accesses 2812system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6834.525974 # average ReadReq mshr miss latency 2813system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6834.525974 # average ReadReq mshr miss latency 2814system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13240.452830 # average WriteReq mshr miss latency 2815system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13240.452830 # average WriteReq mshr miss latency 2816system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7865.230769 # average SwapReq mshr miss latency 2817system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7865.230769 # average SwapReq mshr miss latency 2818system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9446.173077 # average overall mshr miss latency 2819system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9446.173077 # average overall mshr miss latency 2820system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9446.173077 # average overall mshr miss latency 2821system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9446.173077 # average overall mshr miss latency |
| 2680system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2681 2682---------- End Simulation Statistics ---------- | 2822system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2823 2824---------- End Simulation Statistics ---------- |