7,11c7,11
< host_inst_rate 119782 # Simulator instruction rate (inst/s)
< host_op_rate 119782 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 12747983 # Simulator tick rate (ticks/s)
< host_mem_usage 275656 # Number of bytes of host memory used
< host_seconds 8.71 # Real time elapsed on the host
---
> host_inst_rate 77886 # Simulator instruction rate (inst/s)
> host_op_rate 77886 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 8289137 # Simulator tick rate (ticks/s)
> host_mem_usage 295244 # Number of bytes of host memory used
> host_seconds 13.39 # Real time elapsed on the host
207,208c207,208
< system.physmem.totQLat 4010250 # Total ticks spent queuing
< system.physmem.totMemAccLat 18159000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 4008250 # Total ticks spent queuing
> system.physmem.totMemAccLat 18157000 # Total ticks spent from burst creation until serviced by the DRAM
211c211
< system.physmem.avgQLat 6076.14 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 6073.11 # Average queueing delay per DRAM burst
214c214
< system.physmem.avgMemAccLat 27513.64 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 27510.61 # Average memory access latency per DRAM burst
245c245
< system.membus.reqLayer0.occupancy 931500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 932000 # Layer occupancy (ticks)
247c247
< system.membus.respLayer1.occupancy 6289925 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 6290425 # Layer occupancy (ticks)
250c250
< system.l2c.tags.tagsinuse 417.165472 # Cycle average of tags in use
---
> system.l2c.tags.tagsinuse 417.163639 # Cycle average of tags in use
256,257c256,257
< system.l2c.tags.occ_blocks::cpu0.inst 285.088059 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 58.417692 # Average occupied blocks per requestor
---
> system.l2c.tags.occ_blocks::cpu0.inst 285.086488 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 58.417431 # Average occupied blocks per requestor
342c342
< system.l2c.ReadReq_miss_latency::cpu0.inst 24801500 # number of ReadReq miss cycles
---
> system.l2c.ReadReq_miss_latency::cpu0.inst 24802000 # number of ReadReq miss cycles
348c348
< system.l2c.ReadReq_miss_latency::cpu3.inst 584250 # number of ReadReq miss cycles
---
> system.l2c.ReadReq_miss_latency::cpu3.inst 583750 # number of ReadReq miss cycles
354,356c354,356
< system.l2c.ReadExReq_miss_latency::cpu3.data 958250 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 9622500 # number of ReadExReq miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 24801500 # number of demand (read+write) miss cycles
---
> system.l2c.ReadExReq_miss_latency::cpu3.data 957750 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 9622000 # number of ReadExReq miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 24802000 # number of demand (read+write) miss cycles
362,365c362,365
< system.l2c.demand_miss_latency::cpu3.inst 584250 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu3.data 1032750 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 47788500 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 24801500 # number of overall miss cycles
---
> system.l2c.demand_miss_latency::cpu3.inst 583750 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu3.data 1032250 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 47788000 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 24802000 # number of overall miss cycles
371,373c371,373
< system.l2c.overall_miss_latency::cpu3.inst 584250 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu3.data 1032750 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 47788500 # number of overall miss cycles
---
> system.l2c.overall_miss_latency::cpu3.inst 583750 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu3.data 1032250 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 47788000 # number of overall miss cycles
450c450
< system.l2c.ReadReq_avg_miss_latency::cpu0.inst 69084.958217 # average ReadReq miss latency
---
> system.l2c.ReadReq_avg_miss_latency::cpu0.inst 69086.350975 # average ReadReq miss latency
456c456
< system.l2c.ReadReq_avg_miss_latency::cpu3.inst 64916.666667 # average ReadReq miss latency
---
> system.l2c.ReadReq_avg_miss_latency::cpu3.inst 64861.111111 # average ReadReq miss latency
462,464c462,464
< system.l2c.ReadExReq_avg_miss_latency::cpu3.data 79854.166667 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 73454.198473 # average ReadExReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 69084.958217 # average overall miss latency
---
> system.l2c.ReadExReq_avg_miss_latency::cpu3.data 79812.500000 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 73450.381679 # average ReadExReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 69086.350975 # average overall miss latency
470,473c470,473
< system.l2c.demand_avg_miss_latency::cpu3.inst 64916.666667 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu3.data 79442.307692 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 70902.818991 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 69084.958217 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu3.inst 64861.111111 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu3.data 79403.846154 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 70902.077151 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 69086.350975 # average overall miss latency
479,481c479,481
< system.l2c.overall_avg_miss_latency::cpu3.inst 64916.666667 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu3.data 79442.307692 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 70902.818991 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::cpu3.inst 64861.111111 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu3.data 79403.846154 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 70902.077151 # average overall miss latency
548c548
< system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 369750 # number of ReadReq MSHR miss cycles
---
> system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 369250 # number of ReadReq MSHR miss cycles
550c550
< system.l2c.ReadReq_mshr_miss_latency::total 30807000 # number of ReadReq MSHR miss cycles
---
> system.l2c.ReadReq_mshr_miss_latency::total 30806500 # number of ReadReq MSHR miss cycles
559,560c559,560
< system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 807750 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 7989500 # number of ReadExReq MSHR miss cycles
---
> system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 807250 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 7989000 # number of ReadExReq MSHR miss cycles
567,569c567,569
< system.l2c.demand_mshr_miss_latency::cpu3.inst 369750 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu3.data 870250 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 38796500 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu3.inst 369250 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu3.data 869750 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 38795500 # number of demand (read+write) MSHR miss cycles
576,578c576,578
< system.l2c.overall_mshr_miss_latency::cpu3.inst 369750 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu3.data 870250 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 38796500 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::cpu3.inst 369250 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu3.data 869750 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 38795500 # number of overall MSHR miss cycles
622c622
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 61625 # average ReadReq mshr miss latency
---
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 61541.666667 # average ReadReq mshr miss latency
624c624
< system.l2c.ReadReq_avg_mshr_miss_latency::total 58236.294896 # average ReadReq mshr miss latency
---
> system.l2c.ReadReq_avg_mshr_miss_latency::total 58235.349716 # average ReadReq mshr miss latency
633,634c633,634
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 67312.500000 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 60988.549618 # average ReadExReq mshr miss latency
---
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 67270.833333 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 60984.732824 # average ReadExReq mshr miss latency
641,643c641,643
< system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 61625 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu3.data 66942.307692 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 58782.575758 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 61541.666667 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu3.data 66903.846154 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 58781.060606 # average overall mshr miss latency
650,652c650,652
< system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61625 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu3.data 66942.307692 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 58782.575758 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61541.666667 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu3.data 66903.846154 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 58781.060606 # average overall mshr miss latency
713c713
< system.cpu0.fetch.icacheStallCycles 17258 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu0.fetch.icacheStallCycles 17259 # Number of cycles fetch is stalled on an Icache miss
723,726c723,726
< system.cpu0.fetch.IcacheSquashes 489 # Number of outstanding Icache misses that were squashed
< system.cpu0.fetch.rateDist::samples 197037 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::mean 2.503043 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::stdev 2.216869 # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.IcacheSquashes 488 # Number of outstanding Icache misses that were squashed
> system.cpu0.fetch.rateDist::samples 197038 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::mean 2.503030 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::stdev 2.216871 # Number of instructions fetched each cycle (Total)
728c728
< system.cpu0.fetch.rateDist::0 35208 17.87% 17.87% # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.rateDist::0 35209 17.87% 17.87% # Number of instructions fetched each cycle (Total)
740c740
< system.cpu0.fetch.rateDist::total 197037 # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.rateDist::total 197038 # Number of instructions fetched each cycle (Total)
743c743
< system.cpu0.decode.IdleCycles 17850 # Number of cycles decode is idle
---
> system.cpu0.decode.IdleCycles 17851 # Number of cycles decode is idle
750c750
< system.cpu0.rename.IdleCycles 18506 # Number of cycles rename is idle
---
> system.cpu0.rename.IdleCycles 18507 # Number of cycles rename is idle
772,773c772,773
< system.cpu0.iq.iqInstsIssued 405049 # Number of instructions issued
< system.cpu0.iq.iqSquashedInstsIssued 128 # Number of squashed instructions issued
---
> system.cpu0.iq.iqInstsIssued 405044 # Number of instructions issued
> system.cpu0.iq.iqSquashedInstsIssued 133 # Number of squashed instructions issued
775c775
< system.cpu0.iq.iqSquashedOperandsExamined 9381 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu0.iq.iqSquashedOperandsExamined 9396 # Number of squashed operands that are examined and possibly removed from graph
777,779c777,779
< system.cpu0.iq.issued_per_cycle::samples 197037 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::mean 2.055700 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::stdev 1.097210 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::samples 197038 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::mean 2.055664 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::stdev 1.097184 # Number of insts issued each cycle
781c781
< system.cpu0.iq.issued_per_cycle::0 34075 17.29% 17.29% # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::0 34076 17.29% 17.29% # Number of insts issued each cycle
784,785c784,785
< system.cpu0.iq.issued_per_cycle::3 77366 39.26% 98.69% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::4 1557 0.79% 99.48% # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::3 77371 39.27% 98.69% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::4 1552 0.79% 99.48% # Number of insts issued each cycle
793c793
< system.cpu0.iq.issued_per_cycle::total 197037 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::total 197038 # Number of insts issued each cycle
858c858
< system.cpu0.iq.FU_type_0::MemRead 155510 38.39% 80.69% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::MemRead 155505 38.39% 80.69% # Type of FU issued
862,863c862,863
< system.cpu0.iq.FU_type_0::total 405049 # Type of FU issued
< system.cpu0.iq.rate 1.824118 # Inst issue rate
---
> system.cpu0.iq.FU_type_0::total 405044 # Type of FU issued
> system.cpu0.iq.rate 1.824095 # Inst issue rate
866c866
< system.cpu0.iq.int_inst_queue_reads 1007474 # Number of integer instruction queue reads
---
> system.cpu0.iq.int_inst_queue_reads 1007470 # Number of integer instruction queue reads
868c868
< system.cpu0.iq.int_inst_queue_wakeup_accesses 403236 # Number of integer instruction queue wakeup accesses
---
> system.cpu0.iq.int_inst_queue_wakeup_accesses 403231 # Number of integer instruction queue wakeup accesses
872c872
< system.cpu0.iq.int_alu_accesses 405260 # Number of integer alu accesses
---
> system.cpu0.iq.int_alu_accesses 405255 # Number of integer alu accesses
901c901
< system.cpu0.iew.iewExecSquashedInsts 1071 # Number of squashed instructions skipped in execute
---
> system.cpu0.iew.iewExecSquashedInsts 1066 # Number of squashed instructions skipped in execute
908,911c908,911
< system.cpu0.iew.wb_sent 403577 # cumulative count of insts sent to commit
< system.cpu0.iew.wb_count 403236 # cumulative count of insts written-back
< system.cpu0.iew.wb_producers 238895 # num instructions producing a value
< system.cpu0.iew.wb_consumers 241362 # num instructions consuming a value
---
> system.cpu0.iew.wb_sent 403557 # cumulative count of insts sent to commit
> system.cpu0.iew.wb_count 403231 # cumulative count of insts written-back
> system.cpu0.iew.wb_producers 238890 # num instructions producing a value
> system.cpu0.iew.wb_consumers 241357 # num instructions consuming a value
913c913
< system.cpu0.iew.wb_rate 1.815953 # insts written-back per cycle
---
> system.cpu0.iew.wb_rate 1.815931 # insts written-back per cycle
919,921c919,921
< system.cpu0.commit.committed_per_cycle::samples 194597 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::mean 2.430500 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::stdev 2.136019 # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::samples 194598 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::mean 2.430487 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::stdev 2.136021 # Number of insts commited each cycle
923c923
< system.cpu0.commit.committed_per_cycle::0 34534 17.75% 17.75% # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::0 34535 17.75% 17.75% # Number of insts commited each cycle
935c935
< system.cpu0.commit.committed_per_cycle::total 194597 # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::total 194598 # Number of insts commited each cycle
948c948
< system.cpu0.rob.rob_reads 678234 # The number of ROB reads
---
> system.cpu0.rob.rob_reads 678235 # The number of ROB reads
951c951
< system.cpu0.idleCycles 25015 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu0.idleCycles 25014 # Total number of cycles that the CPU has spent unscheduled due to idling
960c960
< system.cpu0.int_regfile_writes 325773 # number of integer regfile writes
---
> system.cpu0.int_regfile_writes 325753 # number of integer regfile writes
965c965
< system.cpu0.icache.tags.tagsinuse 241.313735 # Cycle average of tags in use
---
> system.cpu0.icache.tags.tagsinuse 241.312438 # Cycle average of tags in use
970,972c970,972
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.313735 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471316 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.471316 # Average percentage of cache occupancy
---
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.312438 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471313 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.471313 # Average percentage of cache occupancy
985,990c985,990
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35940245 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 35940245 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 35940245 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 35940245 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 35940245 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 35940245 # number of overall miss cycles
---
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35939745 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 35939745 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 35939745 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 35939745 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 35939745 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 35939745 # number of overall miss cycles
1003,1008c1003,1008
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47540.006614 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 47540.006614 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47540.006614 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 47540.006614 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47540.006614 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 47540.006614 # average overall miss latency
---
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47539.345238 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 47539.345238 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47539.345238 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 47539.345238 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47539.345238 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 47539.345238 # average overall miss latency
1029,1034c1029,1034
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27686252 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 27686252 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27686252 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 27686252 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27686252 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 27686252 # number of overall MSHR miss cycles
---
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27686752 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 27686752 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27686752 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 27686752 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27686752 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 27686752 # number of overall MSHR miss cycles
1041,1046c1041,1046
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47085.462585 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47085.462585 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47085.462585 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 47085.462585 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47085.462585 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 47085.462585 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47086.312925 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47086.312925 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47086.312925 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 47086.312925 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47086.312925 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 47086.312925 # average overall mshr miss latency
1049c1049
< system.cpu0.dcache.tags.tagsinuse 142.026994 # Cycle average of tags in use
---
> system.cpu0.dcache.tags.tagsinuse 142.026071 # Cycle average of tags in use
1054,1056c1054,1056
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.026994 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277396 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.277396 # Average percentage of cache occupancy
---
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.026071 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277395 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.277395 # Average percentage of cache occupancy
1248,1249c1248,1249
< system.cpu1.iq.iqInstsIssued 211924 # Number of instructions issued
< system.cpu1.iq.iqSquashedInstsIssued 72 # Number of squashed instructions issued
---
> system.cpu1.iq.iqInstsIssued 211912 # Number of instructions issued
> system.cpu1.iq.iqSquashedInstsIssued 84 # Number of squashed instructions issued
1251c1251
< system.cpu1.iq.iqSquashedOperandsExamined 10911 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu1.iq.iqSquashedOperandsExamined 10947 # Number of squashed operands that are examined and possibly removed from graph
1254,1255c1254,1255
< system.cpu1.iq.issued_per_cycle::mean 1.206019 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::stdev 1.291588 # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::mean 1.205950 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::stdev 1.291467 # Number of insts issued each cycle
1260,1261c1260,1261
< system.cpu1.iq.issued_per_cycle::3 32801 18.67% 97.26% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::4 3291 1.87% 99.13% # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::3 32813 18.67% 97.26% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::4 3279 1.87% 99.13% # Number of insts issued each cycle
1334c1334
< system.cpu1.iq.FU_type_0::MemRead 75900 35.81% 85.24% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::MemRead 75888 35.81% 85.24% # Type of FU issued
1338,1339c1338,1339
< system.cpu1.iq.FU_type_0::total 211924 # Type of FU issued
< system.cpu1.iq.rate 1.191033 # Inst issue rate
---
> system.cpu1.iq.FU_type_0::total 211912 # Type of FU issued
> system.cpu1.iq.rate 1.190965 # Inst issue rate
1342c1342
< system.cpu1.iq.int_inst_queue_reads 599908 # Number of integer instruction queue reads
---
> system.cpu1.iq.int_inst_queue_reads 599896 # Number of integer instruction queue reads
1344c1344
< system.cpu1.iq.int_inst_queue_wakeup_accesses 210080 # Number of integer instruction queue wakeup accesses
---
> system.cpu1.iq.int_inst_queue_wakeup_accesses 210068 # Number of integer instruction queue wakeup accesses
1348c1348
< system.cpu1.iq.int_alu_accesses 212190 # Number of integer alu accesses
---
> system.cpu1.iq.int_alu_accesses 212178 # Number of integer alu accesses
1377c1377
< system.cpu1.iew.iewExecSquashedInsts 1195 # Number of squashed instructions skipped in execute
---
> system.cpu1.iew.iewExecSquashedInsts 1183 # Number of squashed instructions skipped in execute
1384,1387c1384,1387
< system.cpu1.iew.wb_sent 210404 # cumulative count of insts sent to commit
< system.cpu1.iew.wb_count 210080 # cumulative count of insts written-back
< system.cpu1.iew.wb_producers 116723 # num instructions producing a value
< system.cpu1.iew.wb_consumers 121388 # num instructions consuming a value
---
> system.cpu1.iew.wb_sent 210356 # cumulative count of insts sent to commit
> system.cpu1.iew.wb_count 210068 # cumulative count of insts written-back
> system.cpu1.iew.wb_producers 116711 # num instructions producing a value
> system.cpu1.iew.wb_consumers 121376 # num instructions consuming a value
1389,1390c1389,1390
< system.cpu1.iew.wb_rate 1.180669 # insts written-back per cycle
< system.cpu1.iew.wb_fanout 0.961570 # average fanout of values written-back
---
> system.cpu1.iew.wb_rate 1.180602 # insts written-back per cycle
> system.cpu1.iew.wb_fanout 0.961566 # average fanout of values written-back
1437c1437
< system.cpu1.int_regfile_writes 167816 # number of integer regfile writes
---
> system.cpu1.int_regfile_writes 167768 # number of integer regfile writes
1442c1442
< system.cpu1.icache.tags.tagsinuse 76.730522 # Cycle average of tags in use
---
> system.cpu1.icache.tags.tagsinuse 76.730517 # Cycle average of tags in use
1447c1447
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.730522 # Average occupied blocks per requestor
---
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.730517 # Average occupied blocks per requestor
1462,1467c1462,1467
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7185993 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 7185993 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 7185993 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 7185993 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 7185993 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 7185993 # number of overall miss cycles
---
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7186493 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 7186493 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 7186493 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 7186493 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 7186493 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 7186493 # number of overall miss cycles
1480,1485c1480,1485
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15096.623950 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 15096.623950 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15096.623950 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 15096.623950 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15096.623950 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 15096.623950 # average overall miss latency
---
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15097.674370 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 15097.674370 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15097.674370 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 15097.674370 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15097.674370 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 15097.674370 # average overall miss latency
1506,1511c1506,1511
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5726006 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 5726006 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5726006 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 5726006 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5726006 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 5726006 # number of overall MSHR miss cycles
---
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5726506 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 5726506 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5726506 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 5726506 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5726506 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 5726506 # number of overall MSHR miss cycles
1518,1523c1518,1523
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13378.518692 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13378.518692 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13378.518692 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 13378.518692 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13378.518692 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 13378.518692 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13379.686916 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13379.686916 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13379.686916 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 13379.686916 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13379.686916 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 13379.686916 # average overall mshr miss latency
1651c1651
< system.cpu2.branchPred.lookups 51290 # Number of BP lookups
---
> system.cpu2.branchPred.lookups 51289 # Number of BP lookups
1654c1654
< system.cpu2.branchPred.BTBLookups 45092 # Number of BTB lookups
---
> system.cpu2.branchPred.BTBLookups 45091 # Number of BTB lookups
1657c1657
< system.cpu2.branchPred.BTBHitPct 98.465360 # BTB Hit Percentage
---
> system.cpu2.branchPred.BTBHitPct 98.467543 # BTB Hit Percentage
1663,1665c1663,1665
< system.cpu2.fetch.icacheStallCycles 28807 # Number of cycles fetch is stalled on an Icache miss
< system.cpu2.fetch.Insts 286591 # Number of instructions fetch has processed
< system.cpu2.fetch.Branches 51290 # Number of branches that fetch encountered
---
> system.cpu2.fetch.icacheStallCycles 28811 # Number of cycles fetch is stalled on an Icache miss
> system.cpu2.fetch.Insts 286582 # Number of instructions fetch has processed
> system.cpu2.fetch.Branches 51289 # Number of branches that fetch encountered
1667c1667
< system.cpu2.fetch.Cycles 100996 # Number of cycles fetch has run and was not squashing or blocked
---
> system.cpu2.fetch.Cycles 100994 # Number of cycles fetch has run and was not squashing or blocked
1669c1669
< system.cpu2.fetch.BlockedCycles 31176 # Number of cycles fetch has spent blocked
---
> system.cpu2.fetch.BlockedCycles 31174 # Number of cycles fetch has spent blocked
1673,1674c1673,1674
< system.cpu2.fetch.CacheLines 19752 # Number of cache lines fetched
< system.cpu2.fetch.IcacheSquashes 272 # Number of outstanding Icache misses that were squashed
---
> system.cpu2.fetch.CacheLines 19751 # Number of cache lines fetched
> system.cpu2.fetch.IcacheSquashes 271 # Number of outstanding Icache misses that were squashed
1676,1677c1676,1677
< system.cpu2.fetch.rateDist::mean 1.666178 # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::stdev 2.140016 # Number of instructions fetched each cycle (Total)
---
> system.cpu2.fetch.rateDist::mean 1.666126 # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::stdev 2.139968 # Number of instructions fetched each cycle (Total)
1679,1680c1679,1680
< system.cpu2.fetch.rateDist::0 71009 41.28% 41.28% # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::1 51379 29.87% 71.15% # Number of instructions fetched each cycle (Total)
---
> system.cpu2.fetch.rateDist::0 71011 41.28% 41.28% # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::1 51378 29.87% 71.15% # Number of instructions fetched each cycle (Total)
1687c1687
< system.cpu2.fetch.rateDist::8 3272 1.90% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu2.fetch.rateDist::8 3271 1.90% 100.00% # Number of instructions fetched each cycle (Total)
1692,1693c1692,1693
< system.cpu2.fetch.branchRate 0.288847 # Number of branch fetches per cycle
< system.cpu2.fetch.rate 1.613979 # Number of inst fetches per cycle
---
> system.cpu2.fetch.branchRate 0.288841 # Number of branch fetches per cycle
> system.cpu2.fetch.rate 1.613928 # Number of inst fetches per cycle
1695,1696c1695,1696
< system.cpu2.decode.BlockedCycles 27885 # Number of cycles decode is blocked
< system.cpu2.decode.RunCycles 95101 # Number of cycles decode is running
---
> system.cpu2.decode.BlockedCycles 27886 # Number of cycles decode is blocked
> system.cpu2.decode.RunCycles 95100 # Number of cycles decode is running
1699c1699
< system.cpu2.decode.DecodedInsts 283083 # Number of instructions handled by decode
---
> system.cpu2.decode.DecodedInsts 283075 # Number of instructions handled by decode
1703,1704c1703,1704
< system.cpu2.rename.serializeStallCycles 12251 # count of cycles rename stalled for serializing inst
< system.cpu2.rename.RunCycles 90316 # Number of cycles rename is running
---
> system.cpu2.rename.serializeStallCycles 12252 # count of cycles rename stalled for serializing inst
> system.cpu2.rename.RunCycles 90315 # Number of cycles rename is running
1706c1706
< system.cpu2.rename.RenamedInsts 280840 # Number of instructions processed by rename
---
> system.cpu2.rename.RenamedInsts 280839 # Number of instructions processed by rename
1709,1710c1709,1710
< system.cpu2.rename.RenameLookups 538434 # Number of register rename lookups that rename has made
< system.cpu2.rename.int_rename_lookups 418653 # Number of integer rename lookups
---
> system.cpu2.rename.RenameLookups 538430 # Number of register rename lookups that rename has made
> system.cpu2.rename.int_rename_lookups 418650 # Number of integer rename lookups
1722,1723c1722,1723
< system.cpu2.iq.iqInstsIssued 234909 # Number of instructions issued
< system.cpu2.iq.iqSquashedInstsIssued 92 # Number of squashed instructions issued
---
> system.cpu2.iq.iqInstsIssued 234900 # Number of instructions issued
> system.cpu2.iq.iqSquashedInstsIssued 101 # Number of squashed instructions issued
1725c1725
< system.cpu2.iq.iqSquashedOperandsExamined 10823 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu2.iq.iqSquashedOperandsExamined 10850 # Number of squashed operands that are examined and possibly removed from graph
1728,1729c1728,1729
< system.cpu2.iq.issued_per_cycle::mean 1.365710 # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::stdev 1.313889 # Number of insts issued each cycle
---
> system.cpu2.iq.issued_per_cycle::mean 1.365658 # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::stdev 1.313804 # Number of insts issued each cycle
1734,1735c1734,1735
< system.cpu2.iq.issued_per_cycle::3 38461 22.36% 97.20% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::4 3256 1.89% 99.09% # Number of insts issued each cycle
---
> system.cpu2.iq.issued_per_cycle::3 38470 22.37% 97.21% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::4 3247 1.89% 99.09% # Number of insts issued each cycle
1808c1808
< system.cpu2.iq.FU_type_0::MemRead 83601 35.59% 84.27% # Type of FU issued
---
> system.cpu2.iq.FU_type_0::MemRead 83592 35.59% 84.27% # Type of FU issued
1812,1813c1812,1813
< system.cpu2.iq.FU_type_0::total 234909 # Type of FU issued
< system.cpu2.iq.rate 1.322924 # Inst issue rate
---
> system.cpu2.iq.FU_type_0::total 234900 # Type of FU issued
> system.cpu2.iq.rate 1.322873 # Inst issue rate
1816c1816
< system.cpu2.iq.int_inst_queue_reads 642198 # Number of integer instruction queue reads
---
> system.cpu2.iq.int_inst_queue_reads 642189 # Number of integer instruction queue reads
1818c1818
< system.cpu2.iq.int_inst_queue_wakeup_accesses 233108 # Number of integer instruction queue wakeup accesses
---
> system.cpu2.iq.int_inst_queue_wakeup_accesses 233099 # Number of integer instruction queue wakeup accesses
1822c1822
< system.cpu2.iq.int_alu_accesses 235192 # Number of integer alu accesses
---
> system.cpu2.iq.int_alu_accesses 235183 # Number of integer alu accesses
1851c1851
< system.cpu2.iew.iewExecSquashedInsts 1144 # Number of squashed instructions skipped in execute
---
> system.cpu2.iew.iewExecSquashedInsts 1135 # Number of squashed instructions skipped in execute
1858,1861c1858,1861
< system.cpu2.iew.wb_sent 233421 # cumulative count of insts sent to commit
< system.cpu2.iew.wb_count 233108 # cumulative count of insts written-back
< system.cpu2.iew.wb_producers 131942 # num instructions producing a value
< system.cpu2.iew.wb_consumers 136650 # num instructions consuming a value
---
> system.cpu2.iew.wb_sent 233385 # cumulative count of insts sent to commit
> system.cpu2.iew.wb_count 233099 # cumulative count of insts written-back
> system.cpu2.iew.wb_producers 131933 # num instructions producing a value
> system.cpu2.iew.wb_consumers 136641 # num instructions consuming a value
1863,1864c1863,1864
< system.cpu2.iew.wb_rate 1.312782 # insts written-back per cycle
< system.cpu2.iew.wb_fanout 0.965547 # average fanout of values written-back
---
> system.cpu2.iew.wb_rate 1.312731 # insts written-back per cycle
> system.cpu2.iew.wb_fanout 0.965545 # average fanout of values written-back
1911c1911
< system.cpu2.int_regfile_writes 188808 # number of integer regfile writes
---
> system.cpu2.int_regfile_writes 188772 # number of integer regfile writes
1916,1917c1916,1917
< system.cpu2.icache.tags.tagsinuse 82.236622 # Cycle average of tags in use
< system.cpu2.icache.tags.total_refs 19259 # Total number of references to valid blocks.
---
> system.cpu2.icache.tags.tagsinuse 82.236554 # Cycle average of tags in use
> system.cpu2.icache.tags.total_refs 19258 # Total number of references to valid blocks.
1919c1919
< system.cpu2.icache.tags.avg_refs 45.315294 # Average number of references to valid blocks.
---
> system.cpu2.icache.tags.avg_refs 45.312941 # Average number of references to valid blocks.
1921c1921
< system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.236622 # Average occupied blocks per requestor
---
> system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.236554 # Average occupied blocks per requestor
1924,1929c1924,1929
< system.cpu2.icache.ReadReq_hits::cpu2.inst 19259 # number of ReadReq hits
< system.cpu2.icache.ReadReq_hits::total 19259 # number of ReadReq hits
< system.cpu2.icache.demand_hits::cpu2.inst 19259 # number of demand (read+write) hits
< system.cpu2.icache.demand_hits::total 19259 # number of demand (read+write) hits
< system.cpu2.icache.overall_hits::cpu2.inst 19259 # number of overall hits
< system.cpu2.icache.overall_hits::total 19259 # number of overall hits
---
> system.cpu2.icache.ReadReq_hits::cpu2.inst 19258 # number of ReadReq hits
> system.cpu2.icache.ReadReq_hits::total 19258 # number of ReadReq hits
> system.cpu2.icache.demand_hits::cpu2.inst 19258 # number of demand (read+write) hits
> system.cpu2.icache.demand_hits::total 19258 # number of demand (read+write) hits
> system.cpu2.icache.overall_hits::cpu2.inst 19258 # number of overall hits
> system.cpu2.icache.overall_hits::total 19258 # number of overall hits
1936,1959c1936,1959
< system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11620241 # number of ReadReq miss cycles
< system.cpu2.icache.ReadReq_miss_latency::total 11620241 # number of ReadReq miss cycles
< system.cpu2.icache.demand_miss_latency::cpu2.inst 11620241 # number of demand (read+write) miss cycles
< system.cpu2.icache.demand_miss_latency::total 11620241 # number of demand (read+write) miss cycles
< system.cpu2.icache.overall_miss_latency::cpu2.inst 11620241 # number of overall miss cycles
< system.cpu2.icache.overall_miss_latency::total 11620241 # number of overall miss cycles
< system.cpu2.icache.ReadReq_accesses::cpu2.inst 19752 # number of ReadReq accesses(hits+misses)
< system.cpu2.icache.ReadReq_accesses::total 19752 # number of ReadReq accesses(hits+misses)
< system.cpu2.icache.demand_accesses::cpu2.inst 19752 # number of demand (read+write) accesses
< system.cpu2.icache.demand_accesses::total 19752 # number of demand (read+write) accesses
< system.cpu2.icache.overall_accesses::cpu2.inst 19752 # number of overall (read+write) accesses
< system.cpu2.icache.overall_accesses::total 19752 # number of overall (read+write) accesses
< system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024959 # miss rate for ReadReq accesses
< system.cpu2.icache.ReadReq_miss_rate::total 0.024959 # miss rate for ReadReq accesses
< system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024959 # miss rate for demand accesses
< system.cpu2.icache.demand_miss_rate::total 0.024959 # miss rate for demand accesses
< system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024959 # miss rate for overall accesses
< system.cpu2.icache.overall_miss_rate::total 0.024959 # miss rate for overall accesses
< system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23570.468560 # average ReadReq miss latency
< system.cpu2.icache.ReadReq_avg_miss_latency::total 23570.468560 # average ReadReq miss latency
< system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23570.468560 # average overall miss latency
< system.cpu2.icache.demand_avg_miss_latency::total 23570.468560 # average overall miss latency
< system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23570.468560 # average overall miss latency
< system.cpu2.icache.overall_avg_miss_latency::total 23570.468560 # average overall miss latency
---
> system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11621241 # number of ReadReq miss cycles
> system.cpu2.icache.ReadReq_miss_latency::total 11621241 # number of ReadReq miss cycles
> system.cpu2.icache.demand_miss_latency::cpu2.inst 11621241 # number of demand (read+write) miss cycles
> system.cpu2.icache.demand_miss_latency::total 11621241 # number of demand (read+write) miss cycles
> system.cpu2.icache.overall_miss_latency::cpu2.inst 11621241 # number of overall miss cycles
> system.cpu2.icache.overall_miss_latency::total 11621241 # number of overall miss cycles
> system.cpu2.icache.ReadReq_accesses::cpu2.inst 19751 # number of ReadReq accesses(hits+misses)
> system.cpu2.icache.ReadReq_accesses::total 19751 # number of ReadReq accesses(hits+misses)
> system.cpu2.icache.demand_accesses::cpu2.inst 19751 # number of demand (read+write) accesses
> system.cpu2.icache.demand_accesses::total 19751 # number of demand (read+write) accesses
> system.cpu2.icache.overall_accesses::cpu2.inst 19751 # number of overall (read+write) accesses
> system.cpu2.icache.overall_accesses::total 19751 # number of overall (read+write) accesses
> system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024961 # miss rate for ReadReq accesses
> system.cpu2.icache.ReadReq_miss_rate::total 0.024961 # miss rate for ReadReq accesses
> system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024961 # miss rate for demand accesses
> system.cpu2.icache.demand_miss_rate::total 0.024961 # miss rate for demand accesses
> system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024961 # miss rate for overall accesses
> system.cpu2.icache.overall_miss_rate::total 0.024961 # miss rate for overall accesses
> system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23572.496957 # average ReadReq miss latency
> system.cpu2.icache.ReadReq_avg_miss_latency::total 23572.496957 # average ReadReq miss latency
> system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23572.496957 # average overall miss latency
> system.cpu2.icache.demand_avg_miss_latency::total 23572.496957 # average overall miss latency
> system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23572.496957 # average overall miss latency
> system.cpu2.icache.overall_avg_miss_latency::total 23572.496957 # average overall miss latency
1980,1997c1980,1997
< system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9299505 # number of ReadReq MSHR miss cycles
< system.cpu2.icache.ReadReq_mshr_miss_latency::total 9299505 # number of ReadReq MSHR miss cycles
< system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9299505 # number of demand (read+write) MSHR miss cycles
< system.cpu2.icache.demand_mshr_miss_latency::total 9299505 # number of demand (read+write) MSHR miss cycles
< system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9299505 # number of overall MSHR miss cycles
< system.cpu2.icache.overall_mshr_miss_latency::total 9299505 # number of overall MSHR miss cycles
< system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021517 # mshr miss rate for ReadReq accesses
< system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021517 # mshr miss rate for ReadReq accesses
< system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021517 # mshr miss rate for demand accesses
< system.cpu2.icache.demand_mshr_miss_rate::total 0.021517 # mshr miss rate for demand accesses
< system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021517 # mshr miss rate for overall accesses
< system.cpu2.icache.overall_mshr_miss_rate::total 0.021517 # mshr miss rate for overall accesses
< system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21881.188235 # average ReadReq mshr miss latency
< system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21881.188235 # average ReadReq mshr miss latency
< system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21881.188235 # average overall mshr miss latency
< system.cpu2.icache.demand_avg_mshr_miss_latency::total 21881.188235 # average overall mshr miss latency
< system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21881.188235 # average overall mshr miss latency
< system.cpu2.icache.overall_avg_mshr_miss_latency::total 21881.188235 # average overall mshr miss latency
---
> system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9301005 # number of ReadReq MSHR miss cycles
> system.cpu2.icache.ReadReq_mshr_miss_latency::total 9301005 # number of ReadReq MSHR miss cycles
> system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9301005 # number of demand (read+write) MSHR miss cycles
> system.cpu2.icache.demand_mshr_miss_latency::total 9301005 # number of demand (read+write) MSHR miss cycles
> system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9301005 # number of overall MSHR miss cycles
> system.cpu2.icache.overall_mshr_miss_latency::total 9301005 # number of overall MSHR miss cycles
> system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021518 # mshr miss rate for ReadReq accesses
> system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021518 # mshr miss rate for ReadReq accesses
> system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021518 # mshr miss rate for demand accesses
> system.cpu2.icache.demand_mshr_miss_rate::total 0.021518 # mshr miss rate for demand accesses
> system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021518 # mshr miss rate for overall accesses
> system.cpu2.icache.overall_mshr_miss_rate::total 0.021518 # mshr miss rate for overall accesses
> system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21884.717647 # average ReadReq mshr miss latency
> system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21884.717647 # average ReadReq mshr miss latency
> system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21884.717647 # average overall mshr miss latency
> system.cpu2.icache.demand_avg_mshr_miss_latency::total 21884.717647 # average overall mshr miss latency
> system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21884.717647 # average overall mshr miss latency
> system.cpu2.icache.overall_avg_mshr_miss_latency::total 21884.717647 # average overall mshr miss latency
2000c2000
< system.cpu2.dcache.tags.tagsinuse 26.142582 # Cycle average of tags in use
---
> system.cpu2.dcache.tags.tagsinuse 26.142591 # Cycle average of tags in use
2005c2005
< system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.142582 # Average occupied blocks per requestor
---
> system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.142591 # Average occupied blocks per requestor
2028,2029c2028,2029
< system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5531640 # number of ReadReq miss cycles
< system.cpu2.dcache.ReadReq_miss_latency::total 5531640 # number of ReadReq miss cycles
---
> system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5532140 # number of ReadReq miss cycles
> system.cpu2.dcache.ReadReq_miss_latency::total 5532140 # number of ReadReq miss cycles
2034,2037c2034,2037
< system.cpu2.dcache.demand_miss_latency::cpu2.data 8662651 # number of demand (read+write) miss cycles
< system.cpu2.dcache.demand_miss_latency::total 8662651 # number of demand (read+write) miss cycles
< system.cpu2.dcache.overall_miss_latency::cpu2.data 8662651 # number of overall miss cycles
< system.cpu2.dcache.overall_miss_latency::total 8662651 # number of overall miss cycles
---
> system.cpu2.dcache.demand_miss_latency::cpu2.data 8663151 # number of demand (read+write) miss cycles
> system.cpu2.dcache.demand_miss_latency::total 8663151 # number of demand (read+write) miss cycles
> system.cpu2.dcache.overall_miss_latency::cpu2.data 8663151 # number of overall miss cycles
> system.cpu2.dcache.overall_miss_latency::total 8663151 # number of overall miss cycles
2058,2059c2058,2059
< system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15987.398844 # average ReadReq miss latency
< system.cpu2.dcache.ReadReq_avg_miss_latency::total 15987.398844 # average ReadReq miss latency
---
> system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15988.843931 # average ReadReq miss latency
> system.cpu2.dcache.ReadReq_avg_miss_latency::total 15988.843931 # average ReadReq miss latency
2064,2067c2064,2067
< system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17861.136082 # average overall miss latency
< system.cpu2.dcache.demand_avg_miss_latency::total 17861.136082 # average overall miss latency
< system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17861.136082 # average overall miss latency
< system.cpu2.dcache.overall_avg_miss_latency::total 17861.136082 # average overall miss latency
---
> system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17862.167010 # average overall miss latency
> system.cpu2.dcache.demand_avg_miss_latency::total 17862.167010 # average overall miss latency
> system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17862.167010 # average overall miss latency
> system.cpu2.dcache.overall_avg_miss_latency::total 17862.167010 # average overall miss latency
2137c2137
< system.cpu3.fetch.icacheStallCycles 28850 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu3.fetch.icacheStallCycles 28851 # Number of cycles fetch is stalled on an Icache miss
2143c2143
< system.cpu3.fetch.BlockedCycles 32602 # Number of cycles fetch has spent blocked
---
> system.cpu3.fetch.BlockedCycles 32601 # Number of cycles fetch has spent blocked
2168,2169c2168,2169
< system.cpu3.decode.IdleCycles 34476 # Number of cycles decode is idle
< system.cpu3.decode.BlockedCycles 28632 # Number of cycles decode is blocked
---
> system.cpu3.decode.IdleCycles 34477 # Number of cycles decode is idle
> system.cpu3.decode.BlockedCycles 28631 # Number of cycles decode is blocked
2175c2175
< system.cpu3.rename.IdleCycles 35171 # Number of cycles rename is idle
---
> system.cpu3.rename.IdleCycles 35172 # Number of cycles rename is idle
2177c2177
< system.cpu3.rename.serializeStallCycles 11805 # count of cycles rename stalled for serializing inst
---
> system.cpu3.rename.serializeStallCycles 11804 # count of cycles rename stalled for serializing inst
2197,2198c2197,2198
< system.cpu3.iq.iqInstsIssued 239002 # Number of instructions issued
< system.cpu3.iq.iqSquashedInstsIssued 90 # Number of squashed instructions issued
---
> system.cpu3.iq.iqInstsIssued 238990 # Number of instructions issued
> system.cpu3.iq.iqSquashedInstsIssued 102 # Number of squashed instructions issued
2200c2200
< system.cpu3.iq.iqSquashedOperandsExamined 10694 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu3.iq.iqSquashedOperandsExamined 10730 # Number of squashed operands that are examined and possibly removed from graph
2203,2204c2203,2204
< system.cpu3.iq.issued_per_cycle::mean 1.359356 # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::stdev 1.308484 # Number of insts issued each cycle
---
> system.cpu3.iq.issued_per_cycle::mean 1.359288 # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::stdev 1.308373 # Number of insts issued each cycle
2209,2210c2209,2210
< system.cpu3.iq.issued_per_cycle::3 39034 22.20% 97.27% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::4 3259 1.85% 99.12% # Number of insts issued each cycle
---
> system.cpu3.iq.issued_per_cycle::3 39046 22.21% 97.27% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::4 3247 1.85% 99.12% # Number of insts issued each cycle
2283c2283
< system.cpu3.iq.FU_type_0::MemRead 85680 35.85% 84.31% # Type of FU issued
---
> system.cpu3.iq.FU_type_0::MemRead 85668 35.85% 84.31% # Type of FU issued
2287,2288c2287,2288
< system.cpu3.iq.FU_type_0::total 239002 # Type of FU issued
< system.cpu3.iq.rate 1.348602 # Inst issue rate
---
> system.cpu3.iq.FU_type_0::total 238990 # Type of FU issued
> system.cpu3.iq.rate 1.348535 # Inst issue rate
2291c2291
< system.cpu3.iq.int_inst_queue_reads 654188 # Number of integer instruction queue reads
---
> system.cpu3.iq.int_inst_queue_reads 654176 # Number of integer instruction queue reads
2293c2293
< system.cpu3.iq.int_inst_queue_wakeup_accesses 237209 # Number of integer instruction queue wakeup accesses
---
> system.cpu3.iq.int_inst_queue_wakeup_accesses 237197 # Number of integer instruction queue wakeup accesses
2297c2297
< system.cpu3.iq.int_alu_accesses 239276 # Number of integer alu accesses
---
> system.cpu3.iq.int_alu_accesses 239264 # Number of integer alu accesses
2326c2326
< system.cpu3.iew.iewExecSquashedInsts 1154 # Number of squashed instructions skipped in execute
---
> system.cpu3.iew.iewExecSquashedInsts 1142 # Number of squashed instructions skipped in execute
2333,2336c2333,2336
< system.cpu3.iew.wb_sent 237529 # cumulative count of insts sent to commit
< system.cpu3.iew.wb_count 237209 # cumulative count of insts written-back
< system.cpu3.iew.wb_producers 134044 # num instructions producing a value
< system.cpu3.iew.wb_consumers 138720 # num instructions consuming a value
---
> system.cpu3.iew.wb_sent 237481 # cumulative count of insts sent to commit
> system.cpu3.iew.wb_count 237197 # cumulative count of insts written-back
> system.cpu3.iew.wb_producers 134032 # num instructions producing a value
> system.cpu3.iew.wb_consumers 138708 # num instructions consuming a value
2338,2339c2338,2339
< system.cpu3.iew.wb_rate 1.338485 # insts written-back per cycle
< system.cpu3.iew.wb_fanout 0.966292 # average fanout of values written-back
---
> system.cpu3.iew.wb_rate 1.338417 # insts written-back per cycle
> system.cpu3.iew.wb_fanout 0.966289 # average fanout of values written-back
2386c2386
< system.cpu3.int_regfile_writes 191401 # number of integer regfile writes
---
> system.cpu3.int_regfile_writes 191353 # number of integer regfile writes
2391c2391
< system.cpu3.icache.tags.tagsinuse 79.942849 # Cycle average of tags in use
---
> system.cpu3.icache.tags.tagsinuse 79.942822 # Cycle average of tags in use
2396c2396
< system.cpu3.icache.tags.occ_blocks::cpu3.inst 79.942849 # Average occupied blocks per requestor
---
> system.cpu3.icache.tags.occ_blocks::cpu3.inst 79.942822 # Average occupied blocks per requestor
2411,2416c2411,2416
< system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6449245 # number of ReadReq miss cycles
< system.cpu3.icache.ReadReq_miss_latency::total 6449245 # number of ReadReq miss cycles
< system.cpu3.icache.demand_miss_latency::cpu3.inst 6449245 # number of demand (read+write) miss cycles
< system.cpu3.icache.demand_miss_latency::total 6449245 # number of demand (read+write) miss cycles
< system.cpu3.icache.overall_miss_latency::cpu3.inst 6449245 # number of overall miss cycles
< system.cpu3.icache.overall_miss_latency::total 6449245 # number of overall miss cycles
---
> system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6449745 # number of ReadReq miss cycles
> system.cpu3.icache.ReadReq_miss_latency::total 6449745 # number of ReadReq miss cycles
> system.cpu3.icache.demand_miss_latency::cpu3.inst 6449745 # number of demand (read+write) miss cycles
> system.cpu3.icache.demand_miss_latency::total 6449745 # number of demand (read+write) miss cycles
> system.cpu3.icache.overall_miss_latency::cpu3.inst 6449745 # number of overall miss cycles
> system.cpu3.icache.overall_miss_latency::total 6449745 # number of overall miss cycles
2429,2434c2429,2434
< system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13577.357895 # average ReadReq miss latency
< system.cpu3.icache.ReadReq_avg_miss_latency::total 13577.357895 # average ReadReq miss latency
< system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13577.357895 # average overall miss latency
< system.cpu3.icache.demand_avg_miss_latency::total 13577.357895 # average overall miss latency
< system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13577.357895 # average overall miss latency
< system.cpu3.icache.overall_avg_miss_latency::total 13577.357895 # average overall miss latency
---
> system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13578.410526 # average ReadReq miss latency
> system.cpu3.icache.ReadReq_avg_miss_latency::total 13578.410526 # average ReadReq miss latency
> system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13578.410526 # average overall miss latency
> system.cpu3.icache.demand_avg_miss_latency::total 13578.410526 # average overall miss latency
> system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13578.410526 # average overall miss latency
> system.cpu3.icache.overall_avg_miss_latency::total 13578.410526 # average overall miss latency
2455,2460c2455,2460
< system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5223255 # number of ReadReq MSHR miss cycles
< system.cpu3.icache.ReadReq_mshr_miss_latency::total 5223255 # number of ReadReq MSHR miss cycles
< system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5223255 # number of demand (read+write) MSHR miss cycles
< system.cpu3.icache.demand_mshr_miss_latency::total 5223255 # number of demand (read+write) MSHR miss cycles
< system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5223255 # number of overall MSHR miss cycles
< system.cpu3.icache.overall_mshr_miss_latency::total 5223255 # number of overall MSHR miss cycles
---
> system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5223755 # number of ReadReq MSHR miss cycles
> system.cpu3.icache.ReadReq_mshr_miss_latency::total 5223755 # number of ReadReq MSHR miss cycles
> system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5223755 # number of demand (read+write) MSHR miss cycles
> system.cpu3.icache.demand_mshr_miss_latency::total 5223755 # number of demand (read+write) MSHR miss cycles
> system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5223755 # number of overall MSHR miss cycles
> system.cpu3.icache.overall_mshr_miss_latency::total 5223755 # number of overall MSHR miss cycles
2467,2472c2467,2472
< system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12175.419580 # average ReadReq mshr miss latency
< system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12175.419580 # average ReadReq mshr miss latency
< system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12175.419580 # average overall mshr miss latency
< system.cpu3.icache.demand_avg_mshr_miss_latency::total 12175.419580 # average overall mshr miss latency
< system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12175.419580 # average overall mshr miss latency
< system.cpu3.icache.overall_avg_mshr_miss_latency::total 12175.419580 # average overall mshr miss latency
---
> system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12176.585082 # average ReadReq mshr miss latency
> system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12176.585082 # average ReadReq mshr miss latency
> system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12176.585082 # average overall mshr miss latency
> system.cpu3.icache.demand_avg_mshr_miss_latency::total 12176.585082 # average overall mshr miss latency
> system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12176.585082 # average overall mshr miss latency
> system.cpu3.icache.overall_avg_mshr_miss_latency::total 12176.585082 # average overall mshr miss latency
2475c2475
< system.cpu3.dcache.tags.tagsinuse 24.692253 # Cycle average of tags in use
---
> system.cpu3.dcache.tags.tagsinuse 24.692248 # Cycle average of tags in use
2480c2480
< system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.692253 # Average occupied blocks per requestor
---
> system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.692248 # Average occupied blocks per requestor
2503,2506c2503,2506
< system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4249100 # number of ReadReq miss cycles
< system.cpu3.dcache.ReadReq_miss_latency::total 4249100 # number of ReadReq miss cycles
< system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3352512 # number of WriteReq miss cycles
< system.cpu3.dcache.WriteReq_miss_latency::total 3352512 # number of WriteReq miss cycles
---
> system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4248100 # number of ReadReq miss cycles
> system.cpu3.dcache.ReadReq_miss_latency::total 4248100 # number of ReadReq miss cycles
> system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3351512 # number of WriteReq miss cycles
> system.cpu3.dcache.WriteReq_miss_latency::total 3351512 # number of WriteReq miss cycles
2509,2512c2509,2512
< system.cpu3.dcache.demand_miss_latency::cpu3.data 7601612 # number of demand (read+write) miss cycles
< system.cpu3.dcache.demand_miss_latency::total 7601612 # number of demand (read+write) miss cycles
< system.cpu3.dcache.overall_miss_latency::cpu3.data 7601612 # number of overall miss cycles
< system.cpu3.dcache.overall_miss_latency::total 7601612 # number of overall miss cycles
---
> system.cpu3.dcache.demand_miss_latency::cpu3.data 7599612 # number of demand (read+write) miss cycles
> system.cpu3.dcache.demand_miss_latency::total 7599612 # number of demand (read+write) miss cycles
> system.cpu3.dcache.overall_miss_latency::cpu3.data 7599612 # number of overall miss cycles
> system.cpu3.dcache.overall_miss_latency::total 7599612 # number of overall miss cycles
2533,2536c2533,2536
< system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12760.060060 # average ReadReq miss latency
< system.cpu3.dcache.ReadReq_avg_miss_latency::total 12760.060060 # average ReadReq miss latency
< system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25591.694656 # average WriteReq miss latency
< system.cpu3.dcache.WriteReq_avg_miss_latency::total 25591.694656 # average WriteReq miss latency
---
> system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12757.057057 # average ReadReq miss latency
> system.cpu3.dcache.ReadReq_avg_miss_latency::total 12757.057057 # average ReadReq miss latency
> system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25584.061069 # average WriteReq miss latency
> system.cpu3.dcache.WriteReq_avg_miss_latency::total 25584.061069 # average WriteReq miss latency
2539,2542c2539,2542
< system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16382.784483 # average overall miss latency
< system.cpu3.dcache.demand_avg_miss_latency::total 16382.784483 # average overall miss latency
< system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16382.784483 # average overall miss latency
< system.cpu3.dcache.overall_avg_miss_latency::total 16382.784483 # average overall miss latency
---
> system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16378.474138 # average overall miss latency
> system.cpu3.dcache.demand_avg_miss_latency::total 16378.474138 # average overall miss latency
> system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16378.474138 # average overall miss latency
> system.cpu3.dcache.overall_avg_miss_latency::total 16378.474138 # average overall miss latency
2571,2572c2571,2572
< system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1408738 # number of WriteReq MSHR miss cycles
< system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1408738 # number of WriteReq MSHR miss cycles
---
> system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1408238 # number of WriteReq MSHR miss cycles
> system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1408238 # number of WriteReq MSHR miss cycles
2575,2578c2575,2578
< system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2411262 # number of demand (read+write) MSHR miss cycles
< system.cpu3.dcache.demand_mshr_miss_latency::total 2411262 # number of demand (read+write) MSHR miss cycles
< system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2411262 # number of overall MSHR miss cycles
< system.cpu3.dcache.overall_mshr_miss_latency::total 2411262 # number of overall MSHR miss cycles
---
> system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2410762 # number of demand (read+write) MSHR miss cycles
> system.cpu3.dcache.demand_mshr_miss_latency::total 2410762 # number of demand (read+write) MSHR miss cycles
> system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2410762 # number of overall MSHR miss cycles
> system.cpu3.dcache.overall_mshr_miss_latency::total 2410762 # number of overall MSHR miss cycles
2591,2592c2591,2592
< system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14087.380000 # average WriteReq mshr miss latency
< system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14087.380000 # average WriteReq mshr miss latency
---
> system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14082.380000 # average WriteReq mshr miss latency
> system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14082.380000 # average WriteReq mshr miss latency
2595,2598c2595,2598
< system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9568.500000 # average overall mshr miss latency
< system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9568.500000 # average overall mshr miss latency
< system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9568.500000 # average overall mshr miss latency
< system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9568.500000 # average overall mshr miss latency
---
> system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9566.515873 # average overall mshr miss latency
> system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9566.515873 # average overall mshr miss latency
> system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9566.515873 # average overall mshr miss latency
> system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9566.515873 # average overall mshr miss latency