Cross Reference: /gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

Deleted Added

sdiff udiff text old ( 11312:3d7a85d71bd1 ) new ( 11336:b318499f676c )

full compact

4,5c4,5
< sim_ticks 107836000 # Number of ticks simulated
< final_tick 107836000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 107700000 # Number of ticks simulated
> final_tick 107700000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 68965 # Simulator instruction rate (inst/s)
< host_op_rate 68965 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 7480497 # Simulator tick rate (ticks/s)
< host_mem_usage 247424 # Number of bytes of host memory used
< host_seconds 14.42 # Real time elapsed on the host
< sim_insts 994171 # Number of instructions simulated
< sim_ops 994171 # Number of ops (including micro ops) simulated
---
> host_inst_rate 155633 # Simulator instruction rate (inst/s)
> host_op_rate 155632 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 16853882 # Simulator tick rate (ticks/s)
> host_mem_usage 312924 # Number of bytes of host memory used
> host_seconds 6.39 # Real time elapsed on the host
> sim_insts 994522 # Number of instructions simulated
> sim_ops 994522 # Number of ops (including micro ops) simulated
18c18
< system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu1.inst 5248 # Number of bytes read from this memory
20c20
< system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu2.inst 384 # Number of bytes read from this memory
22c22
< system.physmem.bytes_read::cpu3.inst 448 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory
26,28c26,28
< system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu3.inst 448 # Number of instructions bytes read from this memory
---
> system.physmem.bytes_inst_read::cpu1.inst 5248 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu2.inst 384 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory
32c32
< system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu1.inst 82 # Number of read requests responded to by this memory
34c34
< system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu2.inst 6 # Number of read requests responded to by this memory
36c36
< system.physmem.num_reads::cpu3.inst 7 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory
39,61c39,61
< system.physmem.bw_read::cpu0.inst 213657777 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 100300456 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 47479506 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 11869876 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu2.inst 1780481 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu2.data 7715420 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu3.inst 4154457 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu3.data 7715420 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 394673393 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 213657777 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 47479506 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu2.inst 1780481 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu3.inst 4154457 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 267072221 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 213657777 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 100300456 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 47479506 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 11869876 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu2.inst 1780481 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu2.data 7715420 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu3.inst 4154457 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu3.data 7715420 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 394673393 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu0.inst 213927577 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 100427112 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 48727948 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 11884865 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu2.inst 3565460 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu2.data 7725162 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu3.inst 1188487 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu3.data 7725162 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 395171773 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 213927577 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 48727948 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu2.inst 3565460 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu3.inst 1188487 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 267409471 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 213927577 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 100427112 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 48727948 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 11884865 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu2.inst 3565460 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu2.data 7725162 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu3.inst 1188487 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu3.data 7725162 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 395171773 # Total bandwidth to/from this memory (bytes/s)
73c73
< system.physmem.neitherReadNorWriteReqs 89 # Number of requests that are neither read nor write
---
> system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
108c108
< system.physmem.totGap 107808000 # Total gap between requests
---
> system.physmem.totGap 107672000 # Total gap between requests
233,234c233,234
< system.physmem.totQLat 6565250 # Total ticks spent queuing
< system.physmem.totMemAccLat 19052750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 6586250 # Total ticks spent queuing
> system.physmem.totMemAccLat 19073750 # Total ticks spent from burst creation until serviced by the DRAM
236c236
< system.physmem.avgQLat 9857.73 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 9889.26 # Average queueing delay per DRAM burst
238,239c238,239
< system.physmem.avgMemAccLat 28607.73 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 395.27 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 28639.26 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 395.77 # Average DRAM read bandwidth in MiByte/s
241c241
< system.physmem.avgRdBWSys 395.27 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 395.77 # Average system read bandwidth in MiByte/s
253c253
< system.physmem.avgGap 161873.87 # Average gap between requests
---
> system.physmem.avgGap 161669.67 # Average gap between requests
260,264c260,264
< system.physmem_0.actBackEnergy 38088540 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 27477750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 76044960 # Total energy per rank (pJ)
< system.physmem_0.averagePower 749.349855 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 47969250 # Time in different power states
---
> system.physmem_0.actBackEnergy 38199690 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 27380250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 76058610 # Total energy per rank (pJ)
> system.physmem_0.averagePower 749.484363 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 47670750 # Time in different power states
267c267
< system.physmem_0.memoryStateTime::ACT 52649750 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 52812250 # Time in different power states
274,278c274,278
< system.physmem_1.actBackEnergy 32065065 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 32761500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 74015040 # Total energy per rank (pJ)
< system.physmem_1.averagePower 729.346948 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 57811250 # Time in different power states
---
> system.physmem_1.actBackEnergy 32151420 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 32685750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 74025645 # Total energy per rank (pJ)
> system.physmem_1.averagePower 729.451450 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 57549250 # Time in different power states
281c281
< system.physmem_1.memoryStateTime::ACT 43803750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 43929750 # Time in different power states
283,284c283,284
< system.cpu0.branchPred.lookups 81652 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 79008 # Number of conditional branches predicted
---
> system.cpu0.branchPred.lookups 81595 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 78953 # Number of conditional branches predicted
286,287c286,287
< system.cpu0.branchPred.BTBLookups 78985 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 76270 # Number of BTB hits
---
> system.cpu0.branchPred.BTBLookups 78929 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 76214 # Number of BTB hits
289c289
< system.cpu0.branchPred.BTBHitPct 96.562638 # BTB Hit Percentage
---
> system.cpu0.branchPred.BTBHitPct 96.560200 # BTB Hit Percentage
294c294
< system.cpu0.numCycles 215673 # number of cpu cycles simulated
---
> system.cpu0.numCycles 215401 # number of cpu cycles simulated
297,301c297,301
< system.cpu0.fetch.icacheStallCycles 19729 # Number of cycles fetch is stalled on an Icache miss
< system.cpu0.fetch.Insts 482689 # Number of instructions fetch has processed
< system.cpu0.fetch.Branches 81652 # Number of branches that fetch encountered
< system.cpu0.fetch.predictedBranches 76915 # Number of branches that fetch has predicted taken
< system.cpu0.fetch.Cycles 165939 # Number of cycles fetch has run and was not squashing or blocked
---
> system.cpu0.fetch.icacheStallCycles 19727 # Number of cycles fetch is stalled on an Icache miss
> system.cpu0.fetch.Insts 482343 # Number of instructions fetch has processed
> system.cpu0.fetch.Branches 81595 # Number of branches that fetch encountered
> system.cpu0.fetch.predictedBranches 76859 # Number of branches that fetch has predicted taken
> system.cpu0.fetch.Cycles 165670 # Number of cycles fetch has run and was not squashing or blocked
305,306c305,306
< system.cpu0.fetch.PendingTrapStallCycles 1994 # Number of stall cycles due to pending traps
< system.cpu0.fetch.CacheLines 6734 # Number of cache lines fetched
---
> system.cpu0.fetch.PendingTrapStallCycles 1993 # Number of stall cycles due to pending traps
> system.cpu0.fetch.CacheLines 6732 # Number of cache lines fetched
309,311c309,311
< system.cpu0.fetch.rateDist::samples 189011 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::mean 2.553761 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::stdev 2.213837 # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.rateDist::samples 188739 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::mean 2.555609 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::stdev 2.213598 # Number of instructions fetched each cycle (Total)
313,321c313,321
< system.cpu0.fetch.rateDist::0 30617 16.20% 16.20% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::1 78326 41.44% 57.64% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::2 798 0.42% 58.06% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::3 1203 0.64% 58.70% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::4 614 0.32% 59.02% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::5 73725 39.01% 98.03% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::6 672 0.36% 98.38% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::7 403 0.21% 98.60% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::8 2653 1.40% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.rateDist::0 30459 16.14% 16.14% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::1 78270 41.47% 57.61% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::2 797 0.42% 58.03% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::3 1203 0.64% 58.67% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::4 613 0.32% 58.99% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::5 73671 39.03% 98.03% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::6 671 0.36% 98.38% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::7 403 0.21% 98.59% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::8 2652 1.41% 100.00% # Number of instructions fetched each cycle (Total)
325,331c325,331
< system.cpu0.fetch.rateDist::total 189011 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.branchRate 0.378592 # Number of branch fetches per cycle
< system.cpu0.fetch.rate 2.238059 # Number of inst fetches per cycle
< system.cpu0.decode.IdleCycles 15475 # Number of cycles decode is idle
< system.cpu0.decode.BlockedCycles 18570 # Number of cycles decode is blocked
< system.cpu0.decode.RunCycles 153063 # Number of cycles decode is running
< system.cpu0.decode.UnblockCycles 653 # Number of cycles decode is unblocking
---
> system.cpu0.fetch.rateDist::total 188739 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.branchRate 0.378805 # Number of branch fetches per cycle
> system.cpu0.fetch.rate 2.239279 # Number of inst fetches per cycle
> system.cpu0.decode.IdleCycles 15463 # Number of cycles decode is idle
> system.cpu0.decode.BlockedCycles 18382 # Number of cycles decode is blocked
> system.cpu0.decode.RunCycles 152999 # Number of cycles decode is running
> system.cpu0.decode.UnblockCycles 645 # Number of cycles decode is unblocking
333c333
< system.cpu0.decode.DecodedInsts 472193 # Number of instructions handled by decode
---
> system.cpu0.decode.DecodedInsts 471851 # Number of instructions handled by decode
335,340c335,340
< system.cpu0.rename.IdleCycles 16079 # Number of cycles rename is idle
< system.cpu0.rename.BlockCycles 2117 # Number of cycles rename is blocking
< system.cpu0.rename.serializeStallCycles 15116 # count of cycles rename stalled for serializing inst
< system.cpu0.rename.RunCycles 153063 # Number of cycles rename is running
< system.cpu0.rename.UnblockCycles 1386 # Number of cycles rename is unblocking
< system.cpu0.rename.RenamedInsts 469016 # Number of instructions processed by rename
---
> system.cpu0.rename.IdleCycles 16060 # Number of cycles rename is idle
> system.cpu0.rename.BlockCycles 2005 # Number of cycles rename is blocking
> system.cpu0.rename.serializeStallCycles 15072 # count of cycles rename stalled for serializing inst
> system.cpu0.rename.RunCycles 152998 # Number of cycles rename is running
> system.cpu0.rename.UnblockCycles 1354 # Number of cycles rename is unblocking
> system.cpu0.rename.RenamedInsts 468673 # Number of instructions processed by rename
343,356c343,356
< system.cpu0.rename.SQFullEvents 883 # Number of times rename has blocked due to SQ full
< system.cpu0.rename.RenamedOperands 320676 # Number of destination operands rename has renamed
< system.cpu0.rename.RenameLookups 935403 # Number of register rename lookups that rename has made
< system.cpu0.rename.int_rename_lookups 706479 # Number of integer rename lookups
< system.cpu0.rename.CommittedMaps 307583 # Number of HB maps that are committed
< system.cpu0.rename.UndoneMaps 13093 # Number of HB maps that are undone due to squashing
< system.cpu0.rename.serializingInsts 822 # count of serializing insts renamed
< system.cpu0.rename.tempSerializingInsts 832 # count of temporary serializing insts renamed
< system.cpu0.rename.skidInsts 4383 # count of insts added to the skid buffer
< system.cpu0.memDep0.insertedLoads 150037 # Number of loads inserted to the mem dependence unit.
< system.cpu0.memDep0.insertedStores 75873 # Number of stores inserted to the mem dependence unit.
< system.cpu0.memDep0.conflictingLoads 73364 # Number of conflicting loads.
< system.cpu0.memDep0.conflictingStores 72959 # Number of conflicting stores.
< system.cpu0.iq.iqInstsAdded 392343 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu0.rename.SQFullEvents 851 # Number of times rename has blocked due to SQ full
> system.cpu0.rename.RenamedOperands 320440 # Number of destination operands rename has renamed
> system.cpu0.rename.RenameLookups 934717 # Number of register rename lookups that rename has made
> system.cpu0.rename.int_rename_lookups 705961 # Number of integer rename lookups
> system.cpu0.rename.CommittedMaps 307367 # Number of HB maps that are committed
> system.cpu0.rename.UndoneMaps 13073 # Number of HB maps that are undone due to squashing
> system.cpu0.rename.serializingInsts 821 # count of serializing insts renamed
> system.cpu0.rename.tempSerializingInsts 831 # count of temporary serializing insts renamed
> system.cpu0.rename.skidInsts 4337 # count of insts added to the skid buffer
> system.cpu0.memDep0.insertedLoads 149926 # Number of loads inserted to the mem dependence unit.
> system.cpu0.memDep0.insertedStores 75817 # Number of stores inserted to the mem dependence unit.
> system.cpu0.memDep0.conflictingLoads 73307 # Number of conflicting loads.
> system.cpu0.memDep0.conflictingStores 72919 # Number of conflicting stores.
> system.cpu0.iq.iqInstsAdded 392051 # Number of instructions added to the IQ (excludes non-spec)
358c358
< system.cpu0.iq.iqInstsIssued 388906 # Number of instructions issued
---
> system.cpu0.iq.iqInstsIssued 388622 # Number of instructions issued
360,361c360,361
< system.cpu0.iq.iqSquashedInstsExamined 12322 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu0.iq.iqSquashedOperandsExamined 11733 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu0.iq.iqSquashedInstsExamined 12300 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu0.iq.iqSquashedOperandsExamined 11714 # Number of squashed operands that are examined and possibly removed from graph
363,365c363,365
< system.cpu0.iq.issued_per_cycle::samples 189011 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::mean 2.057584 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::stdev 1.125737 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::samples 188739 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::mean 2.059045 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::stdev 1.124370 # Number of insts issued each cycle
367,373c367,373
< system.cpu0.iq.issued_per_cycle::0 33687 17.82% 17.82% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::1 4243 2.24% 20.07% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::2 74165 39.24% 59.31% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::3 73776 39.03% 98.34% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::4 1622 0.86% 99.20% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::5 890 0.47% 99.67% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::6 405 0.21% 99.88% # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::0 33524 17.76% 17.76% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::1 4207 2.23% 19.99% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::2 74141 39.28% 59.27% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::3 73776 39.09% 98.36% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::4 1579 0.84% 99.20% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::5 884 0.47% 99.67% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::6 404 0.21% 99.88% # Number of insts issued each cycle
375c375
< system.cpu0.iq.issued_per_cycle::8 76 0.04% 100.00% # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::8 77 0.04% 100.00% # Number of insts issued each cycle
379c379
< system.cpu0.iq.issued_per_cycle::total 189011 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::total 188739 # Number of insts issued each cycle
381,411c381,411
< system.cpu0.iq.fu_full::IntAlu 62 21.45% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntMult 0 0.00% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.45% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemRead 124 42.91% 64.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemWrite 103 35.64% 100.00% # attempts to use FU when none available
---
> system.cpu0.iq.fu_full::IntAlu 61 21.18% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntMult 0 0.00% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.18% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemRead 124 43.06% 64.24% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemWrite 103 35.76% 100.00% # attempts to use FU when none available
415c415
< system.cpu0.iq.FU_type_0::IntAlu 164396 42.27% 42.27% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::IntAlu 164274 42.27% 42.27% # Type of FU issued
444,445c444,445
< system.cpu0.iq.FU_type_0::MemRead 149390 38.41% 80.68% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemWrite 75120 19.32% 100.00% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::MemRead 149282 38.41% 80.68% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemWrite 75066 19.32% 100.00% # Type of FU issued
448,454c448,454
< system.cpu0.iq.FU_type_0::total 388906 # Type of FU issued
< system.cpu0.iq.rate 1.803221 # Inst issue rate
< system.cpu0.iq.fu_busy_cnt 289 # FU busy when requested
< system.cpu0.iq.fu_busy_rate 0.000743 # FU busy rate (busy events/executed inst)
< system.cpu0.iq.int_inst_queue_reads 967143 # Number of integer instruction queue reads
< system.cpu0.iq.int_inst_queue_writes 405616 # Number of integer instruction queue writes
< system.cpu0.iq.int_inst_queue_wakeup_accesses 387054 # Number of integer instruction queue wakeup accesses
---
> system.cpu0.iq.FU_type_0::total 388622 # Type of FU issued
> system.cpu0.iq.rate 1.804179 # Inst issue rate
> system.cpu0.iq.fu_busy_cnt 288 # FU busy when requested
> system.cpu0.iq.fu_busy_rate 0.000741 # FU busy rate (busy events/executed inst)
> system.cpu0.iq.int_inst_queue_reads 966302 # Number of integer instruction queue reads
> system.cpu0.iq.int_inst_queue_writes 405302 # Number of integer instruction queue writes
> system.cpu0.iq.int_inst_queue_wakeup_accesses 386770 # Number of integer instruction queue wakeup accesses
458c458
< system.cpu0.iq.int_alu_accesses 389195 # Number of integer alu accesses
---
> system.cpu0.iq.int_alu_accesses 388910 # Number of integer alu accesses
460c460
< system.cpu0.iew.lsq.thread0.forwLoads 72474 # Number of loads that had data forwarded from stores
---
> system.cpu0.iew.lsq.thread0.forwLoads 72419 # Number of loads that had data forwarded from stores
462c462
< system.cpu0.iew.lsq.thread0.squashedLoads 2656 # Number of loads squashed
---
> system.cpu0.iew.lsq.thread0.squashedLoads 2653 # Number of loads squashed
465c465
< system.cpu0.iew.lsq.thread0.squashedStores 1676 # Number of stores squashed
---
> system.cpu0.iew.lsq.thread0.squashedStores 1674 # Number of stores squashed
472c472
< system.cpu0.iew.iewBlockCycles 2081 # Number of cycles IEW is blocking
---
> system.cpu0.iew.iewBlockCycles 1969 # Number of cycles IEW is blocking
474c474
< system.cpu0.iew.iewDispatchedInsts 466895 # Number of instructions dispatched to IQ
---
> system.cpu0.iew.iewDispatchedInsts 466549 # Number of instructions dispatched to IQ
476,477c476,477
< system.cpu0.iew.iewDispLoadInsts 150037 # Number of dispatched load instructions
< system.cpu0.iew.iewDispStoreInsts 75873 # Number of dispatched store instructions
---
> system.cpu0.iew.iewDispLoadInsts 149926 # Number of dispatched load instructions
> system.cpu0.iew.iewDispStoreInsts 75817 # Number of dispatched store instructions
485,486c485,486
< system.cpu0.iew.iewExecutedInsts 387894 # Number of executed instructions
< system.cpu0.iew.iewExecLoadInsts 149051 # Number of load instructions executed
---
> system.cpu0.iew.iewExecutedInsts 387610 # Number of executed instructions
> system.cpu0.iew.iewExecLoadInsts 148943 # Number of load instructions executed
489,500c489,500
< system.cpu0.iew.exec_nop 73663 # number of nop insts executed
< system.cpu0.iew.exec_refs 224021 # number of memory reference insts executed
< system.cpu0.iew.exec_branches 76988 # Number of branches executed
< system.cpu0.iew.exec_stores 74970 # Number of stores executed
< system.cpu0.iew.exec_rate 1.798528 # Inst execution rate
< system.cpu0.iew.wb_sent 387462 # cumulative count of insts sent to commit
< system.cpu0.iew.wb_count 387054 # cumulative count of insts written-back
< system.cpu0.iew.wb_producers 229603 # num instructions producing a value
< system.cpu0.iew.wb_consumers 232649 # num instructions consuming a value
< system.cpu0.iew.wb_rate 1.794634 # insts written-back per cycle
< system.cpu0.iew.wb_fanout 0.986907 # average fanout of values written-back
< system.cpu0.commit.commitSquashedInsts 13111 # The number of squashed insts skipped by commit
---
> system.cpu0.iew.exec_nop 73609 # number of nop insts executed
> system.cpu0.iew.exec_refs 223859 # number of memory reference insts executed
> system.cpu0.iew.exec_branches 76931 # Number of branches executed
> system.cpu0.iew.exec_stores 74916 # Number of stores executed
> system.cpu0.iew.exec_rate 1.799481 # Inst execution rate
> system.cpu0.iew.wb_sent 387178 # cumulative count of insts sent to commit
> system.cpu0.iew.wb_count 386770 # cumulative count of insts written-back
> system.cpu0.iew.wb_producers 229443 # num instructions producing a value
> system.cpu0.iew.wb_consumers 232488 # num instructions consuming a value
> system.cpu0.iew.wb_rate 1.795581 # insts written-back per cycle
> system.cpu0.iew.wb_fanout 0.986903 # average fanout of values written-back
> system.cpu0.commit.commitSquashedInsts 13089 # The number of squashed insts skipped by commit
503,505c503,505
< system.cpu0.commit.committed_per_cycle::samples 186547 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::mean 2.432234 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::stdev 2.149146 # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::samples 186278 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::mean 2.434007 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::stdev 2.148610 # Number of insts commited each cycle
507,514c507,514
< system.cpu0.commit.committed_per_cycle::0 33930 18.19% 18.19% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::1 76047 40.77% 58.95% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::2 1940 1.04% 59.99% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::3 670 0.36% 60.35% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::4 524 0.28% 60.63% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::5 72154 38.68% 99.31% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::6 534 0.29% 99.60% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::7 265 0.14% 99.74% # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::0 33753 18.12% 18.12% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::1 76007 40.80% 58.92% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::2 1940 1.04% 59.96% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::3 664 0.36% 60.32% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::4 518 0.28% 60.60% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::5 72154 38.73% 99.33% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::6 496 0.27% 99.60% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::7 263 0.14% 99.74% # Number of insts commited each cycle
519,521c519,521
< system.cpu0.commit.committed_per_cycle::total 186547 # Number of insts commited each cycle
< system.cpu0.commit.committedInsts 453726 # Number of instructions committed
< system.cpu0.commit.committedOps 453726 # Number of ops (including micro ops) committed
---
> system.cpu0.commit.committed_per_cycle::total 186278 # Number of insts commited each cycle
> system.cpu0.commit.committedInsts 453402 # Number of instructions committed
> system.cpu0.commit.committedOps 453402 # Number of ops (including micro ops) committed
523,524c523,524
< system.cpu0.commit.refs 221578 # Number of memory references committed
< system.cpu0.commit.loads 147381 # Number of loads committed
---
> system.cpu0.commit.refs 221416 # Number of memory references committed
> system.cpu0.commit.loads 147273 # Number of loads committed
526c526
< system.cpu0.commit.branches 76084 # Number of branches committed
---
> system.cpu0.commit.branches 76030 # Number of branches committed
528c528
< system.cpu0.commit.int_insts 305914 # Number of committed integer instructions.
---
> system.cpu0.commit.int_insts 305698 # Number of committed integer instructions.
530,531c530,531
< system.cpu0.commit.op_class_0::No_OpClass 72816 16.05% 16.05% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntAlu 159248 35.10% 51.15% # Class of committed instruction
---
> system.cpu0.commit.op_class_0::No_OpClass 72762 16.05% 16.05% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntAlu 159140 35.10% 51.15% # Class of committed instruction
560,561c560,561
< system.cpu0.commit.op_class_0::MemRead 147465 32.50% 83.65% # Class of committed instruction
< system.cpu0.commit.op_class_0::MemWrite 74197 16.35% 100.00% # Class of committed instruction
---
> system.cpu0.commit.op_class_0::MemRead 147357 32.50% 83.65% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemWrite 74143 16.35% 100.00% # Class of committed instruction
564c564
< system.cpu0.commit.op_class_0::total 453726 # Class of committed instruction
---
> system.cpu0.commit.op_class_0::total 453402 # Class of committed instruction
566,567c566,567
< system.cpu0.rob.rob_reads 651740 # The number of ROB reads
< system.cpu0.rob.rob_writes 936154 # The number of ROB writes
---
> system.cpu0.rob.rob_reads 651125 # The number of ROB reads
> system.cpu0.rob.rob_writes 935459 # The number of ROB writes
570,577c570,577
< system.cpu0.committedInsts 380826 # Number of Instructions Simulated
< system.cpu0.committedOps 380826 # Number of Ops (including micro ops) Simulated
< system.cpu0.cpi 0.566330 # CPI: Cycles Per Instruction
< system.cpu0.cpi_total 0.566330 # CPI: Total CPI of All Threads
< system.cpu0.ipc 1.765756 # IPC: Instructions Per Cycle
< system.cpu0.ipc_total 1.765756 # IPC: Total IPC of All Threads
< system.cpu0.int_regfile_reads 693989 # number of integer regfile reads
< system.cpu0.int_regfile_writes 312909 # number of integer regfile writes
---
> system.cpu0.committedInsts 380556 # Number of Instructions Simulated
> system.cpu0.committedOps 380556 # Number of Ops (including micro ops) Simulated
> system.cpu0.cpi 0.566017 # CPI: Cycles Per Instruction
> system.cpu0.cpi_total 0.566017 # CPI: Total CPI of All Threads
> system.cpu0.ipc 1.766733 # IPC: Instructions Per Cycle
> system.cpu0.ipc_total 1.766733 # IPC: Total IPC of All Threads
> system.cpu0.int_regfile_reads 693485 # number of integer regfile reads
> system.cpu0.int_regfile_writes 312678 # number of integer regfile writes
579c579
< system.cpu0.misc_regfile_reads 225890 # number of misc regfile reads
---
> system.cpu0.misc_regfile_reads 225727 # number of misc regfile reads
582,583c582,583
< system.cpu0.dcache.tags.tagsinuse 141.137199 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 149509 # Total number of references to valid blocks.
---
> system.cpu0.dcache.tags.tagsinuse 141.118700 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 149407 # Total number of references to valid blocks.
585c585
< system.cpu0.dcache.tags.avg_refs 874.321637 # Average number of references to valid blocks.
---
> system.cpu0.dcache.tags.avg_refs 873.725146 # Average number of references to valid blocks.
587,589c587,589
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.137199 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275659 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.275659 # Average percentage of cache occupancy
---
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.118700 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275622 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.275622 # Average percentage of cache occupancy
595,600c595,600
< system.cpu0.dcache.tags.tag_accesses 603167 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 603167 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 75961 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 75961 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 73598 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 73598 # number of WriteReq hits
---
> system.cpu0.dcache.tags.tag_accesses 602739 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 602739 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 75912 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 75912 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 73546 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 73546 # number of WriteReq hits
603,610c603,610
< system.cpu0.dcache.demand_hits::cpu0.data 149559 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 149559 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 149559 # number of overall hits
< system.cpu0.dcache.overall_hits::total 149559 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 557 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 557 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 557 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 557 # number of WriteReq misses
---
> system.cpu0.dcache.demand_hits::cpu0.data 149458 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 149458 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 149458 # number of overall hits
> system.cpu0.dcache.overall_hits::total 149458 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 553 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 553 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 555 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 555 # number of WriteReq misses
613,620c613,620
< system.cpu0.dcache.demand_misses::cpu0.data 1114 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 1114 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 1114 # number of overall misses
< system.cpu0.dcache.overall_misses::total 1114 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17293500 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 17293500 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34774980 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 34774980 # number of WriteReq miss cycles
---
> system.cpu0.dcache.demand_misses::cpu0.data 1108 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 1108 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 1108 # number of overall misses
> system.cpu0.dcache.overall_misses::total 1108 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16789000 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 16789000 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34744480 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 34744480 # number of WriteReq miss cycles
623,630c623,630
< system.cpu0.dcache.demand_miss_latency::cpu0.data 52068480 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 52068480 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 52068480 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 52068480 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 76518 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 76518 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 74155 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 74155 # number of WriteReq accesses(hits+misses)
---
> system.cpu0.dcache.demand_miss_latency::cpu0.data 51533480 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 51533480 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 51533480 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 51533480 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 76465 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 76465 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 74101 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 74101 # number of WriteReq accesses(hits+misses)
633,640c633,640
< system.cpu0.dcache.demand_accesses::cpu0.data 150673 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 150673 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 150673 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 150673 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007279 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.007279 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007511 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.007511 # miss rate for WriteReq accesses
---
> system.cpu0.dcache.demand_accesses::cpu0.data 150566 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 150566 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 150566 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 150566 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007232 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.007232 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007490 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.007490 # miss rate for WriteReq accesses
643,650c643,650
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007393 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.007393 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007393 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.007393 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31047.576302 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 31047.576302 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62432.639138 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 62432.639138 # average WriteReq miss latency
---
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007359 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.007359 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007359 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.007359 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30359.855335 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 30359.855335 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62602.666667 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 62602.666667 # average WriteReq miss latency
653,656c653,656
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46740.107720 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 46740.107720 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46740.107720 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 46740.107720 # average overall miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46510.361011 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 46510.361011 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46510.361011 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 46510.361011 # average overall miss latency
667,678c667,678
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 375 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 375 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 379 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 379 # number of WriteReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 754 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 754 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 754 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 754 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 178 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 178 # number of WriteReq MSHR misses
---
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 370 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 370 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 378 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 378 # number of WriteReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 748 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 748 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 748 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 748 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 183 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 177 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 177 # number of WriteReq MSHR misses
685,688c685,688
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6892000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6892000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8487000 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8487000 # number of WriteReq MSHR miss cycles
---
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6853000 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6853000 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8423500 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8423500 # number of WriteReq MSHR miss cycles
691,698c691,698
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15379000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 15379000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15379000 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 15379000 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002379 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002379 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002400 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002400 # mshr miss rate for WriteReq accesses
---
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15276500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 15276500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15276500 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 15276500 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002393 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002393 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002389 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002389 # mshr miss rate for WriteReq accesses
701,708c701,708
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002389 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.002389 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002389 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.002389 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37868.131868 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37868.131868 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47679.775281 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47679.775281 # average WriteReq mshr miss latency
---
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002391 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.002391 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002391 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.002391 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37448.087432 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37448.087432 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47590.395480 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47590.395480 # average WriteReq mshr miss latency
711,714c711,714
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42719.444444 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42719.444444 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42719.444444 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42719.444444 # average overall mshr miss latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42434.722222 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42434.722222 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42434.722222 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42434.722222 # average overall mshr miss latency
717,718c717,718
< system.cpu0.icache.tags.tagsinuse 241.200073 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 5951 # Total number of references to valid blocks.
---
> system.cpu0.icache.tags.tagsinuse 241.159002 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 5949 # Total number of references to valid blocks.
720c720
< system.cpu0.icache.tags.avg_refs 9.803954 # Average number of references to valid blocks.
---
> system.cpu0.icache.tags.avg_refs 9.800659 # Average number of references to valid blocks.
722,724c722,724
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.200073 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471094 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.471094 # Average percentage of cache occupancy
---
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.159002 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471014 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.471014 # Average percentage of cache occupancy
727,728c727,728
< system.cpu0.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id
730,737c730,737
< system.cpu0.icache.tags.tag_accesses 7341 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 7341 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 5951 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 5951 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 5951 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 5951 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 5951 # number of overall hits
< system.cpu0.icache.overall_hits::total 5951 # number of overall hits
---
> system.cpu0.icache.tags.tag_accesses 7339 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 7339 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 5949 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 5949 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 5949 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 5949 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 5949 # number of overall hits
> system.cpu0.icache.overall_hits::total 5949 # number of overall hits
744,767c744,767
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40367500 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 40367500 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 40367500 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 40367500 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 40367500 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 40367500 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 6734 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 6734 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 6734 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 6734 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 6734 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 6734 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116276 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.116276 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116276 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.116276 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116276 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.116276 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51554.916986 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 51554.916986 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51554.916986 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 51554.916986 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51554.916986 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 51554.916986 # average overall miss latency
---
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40394500 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 40394500 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 40394500 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 40394500 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 40394500 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 40394500 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 6732 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 6732 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 6732 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 6732 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 6732 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 6732 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116310 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.116310 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116310 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.116310 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116310 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.116310 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51589.399745 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 51589.399745 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51589.399745 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 51589.399745 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51589.399745 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 51589.399745 # average overall miss latency
790,807c790,807
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31309500 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 31309500 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31309500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 31309500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31309500 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 31309500 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090288 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090288 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090288 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.090288 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090288 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.090288 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51495.888158 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51495.888158 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51495.888158 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 51495.888158 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51495.888158 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 51495.888158 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31312500 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 31312500 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31312500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 31312500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31312500 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 31312500 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090315 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090315 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090315 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.090315 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090315 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.090315 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51500.822368 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51500.822368 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51500.822368 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 51500.822368 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51500.822368 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 51500.822368 # average overall mshr miss latency
809,813c809,813
< system.cpu1.branchPred.lookups 53782 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 50347 # Number of conditional branches predicted
< system.cpu1.branchPred.condIncorrect 1277 # Number of conditional branches incorrect
< system.cpu1.branchPred.BTBLookups 46315 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 45397 # Number of BTB hits
---
> system.cpu1.branchPred.lookups 52270 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 48857 # Number of conditional branches predicted
> system.cpu1.branchPred.condIncorrect 1261 # Number of conditional branches incorrect
> system.cpu1.branchPred.BTBLookups 45038 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 43957 # Number of BTB hits
815,816c815,816
< system.cpu1.branchPred.BTBHitPct 98.017921 # BTB Hit Percentage
< system.cpu1.branchPred.usedRAS 899 # Number of times the RAS was used to get a target.
---
> system.cpu1.branchPred.BTBHitPct 97.599805 # BTB Hit Percentage
> system.cpu1.branchPred.usedRAS 912 # Number of times the RAS was used to get a target.
818c818
< system.cpu1.numCycles 162898 # number of cpu cycles simulated
---
> system.cpu1.numCycles 162626 # number of cpu cycles simulated
821,826c821,826
< system.cpu1.fetch.icacheStallCycles 29679 # Number of cycles fetch is stalled on an Icache miss
< system.cpu1.fetch.Insts 299544 # Number of instructions fetch has processed
< system.cpu1.fetch.Branches 53782 # Number of branches that fetch encountered
< system.cpu1.fetch.predictedBranches 46296 # Number of branches that fetch has predicted taken
< system.cpu1.fetch.Cycles 124703 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu1.fetch.SquashCycles 2711 # Number of cycles fetch has spent squashing
---
> system.cpu1.fetch.icacheStallCycles 30636 # Number of cycles fetch is stalled on an Icache miss
> system.cpu1.fetch.Insts 289541 # Number of instructions fetch has processed
> system.cpu1.fetch.Branches 52270 # Number of branches that fetch encountered
> system.cpu1.fetch.predictedBranches 44869 # Number of branches that fetch has predicted taken
> system.cpu1.fetch.Cycles 123502 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu1.fetch.SquashCycles 2677 # Number of cycles fetch has spent squashing
831,835c831,835
< system.cpu1.fetch.CacheLines 20165 # Number of cache lines fetched
< system.cpu1.fetch.IcacheSquashes 457 # Number of outstanding Icache misses that were squashed
< system.cpu1.fetch.rateDist::samples 156846 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::mean 1.909797 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::stdev 2.217375 # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.CacheLines 21117 # Number of cache lines fetched
> system.cpu1.fetch.IcacheSquashes 458 # Number of outstanding Icache misses that were squashed
> system.cpu1.fetch.rateDist::samples 156585 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::mean 1.849098 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::stdev 2.199028 # Number of instructions fetched each cycle (Total)
837,845c837,845
< system.cpu1.fetch.rateDist::0 53057 33.83% 33.83% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::1 52143 33.24% 67.07% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::2 5878 3.75% 70.82% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::3 3526 2.25% 73.07% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::4 939 0.60% 73.67% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::5 35272 22.49% 96.15% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::6 1247 0.80% 96.95% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::7 803 0.51% 97.46% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::8 3981 2.54% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::0 55186 35.24% 35.24% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::1 51235 32.72% 67.96% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::2 6397 4.09% 72.05% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::3 3507 2.24% 74.29% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::4 942 0.60% 74.89% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::5 33361 21.31% 96.20% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::6 1213 0.77% 96.97% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::7 812 0.52% 97.49% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::8 3932 2.51% 100.00% # Number of instructions fetched each cycle (Total)
849,866c849,866
< system.cpu1.fetch.rateDist::total 156846 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.branchRate 0.330158 # Number of branch fetches per cycle
< system.cpu1.fetch.rate 1.838844 # Number of inst fetches per cycle
< system.cpu1.decode.IdleCycles 17882 # Number of cycles decode is idle
< system.cpu1.decode.BlockedCycles 51023 # Number of cycles decode is blocked
< system.cpu1.decode.RunCycles 83554 # Number of cycles decode is running
< system.cpu1.decode.UnblockCycles 3022 # Number of cycles decode is unblocking
< system.cpu1.decode.SquashCycles 1355 # Number of cycles decode is squashing
< system.cpu1.decode.DecodedInsts 284108 # Number of instructions handled by decode
< system.cpu1.rename.SquashCycles 1355 # Number of cycles rename is squashing
< system.cpu1.rename.IdleCycles 18601 # Number of cycles rename is idle
< system.cpu1.rename.BlockCycles 22664 # Number of cycles rename is blocking
< system.cpu1.rename.serializeStallCycles 13899 # count of cycles rename stalled for serializing inst
< system.cpu1.rename.RunCycles 84840 # Number of cycles rename is running
< system.cpu1.rename.UnblockCycles 15477 # Number of cycles rename is unblocking
< system.cpu1.rename.RenamedInsts 280728 # Number of instructions processed by rename
< system.cpu1.rename.IQFullEvents 13732 # Number of times rename has blocked due to IQ full
< system.cpu1.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full
---
> system.cpu1.fetch.rateDist::total 156585 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.branchRate 0.321412 # Number of branch fetches per cycle
> system.cpu1.fetch.rate 1.780410 # Number of inst fetches per cycle
> system.cpu1.decode.IdleCycles 17913 # Number of cycles decode is idle
> system.cpu1.decode.BlockedCycles 54188 # Number of cycles decode is blocked
> system.cpu1.decode.RunCycles 79912 # Number of cycles decode is running
> system.cpu1.decode.UnblockCycles 3224 # Number of cycles decode is unblocking
> system.cpu1.decode.SquashCycles 1338 # Number of cycles decode is squashing
> system.cpu1.decode.DecodedInsts 274398 # Number of instructions handled by decode
> system.cpu1.rename.SquashCycles 1338 # Number of cycles rename is squashing
> system.cpu1.rename.IdleCycles 18610 # Number of cycles rename is idle
> system.cpu1.rename.BlockCycles 24678 # Number of cycles rename is blocking
> system.cpu1.rename.serializeStallCycles 13550 # count of cycles rename stalled for serializing inst
> system.cpu1.rename.RunCycles 81416 # Number of cycles rename is running
> system.cpu1.rename.UnblockCycles 16983 # Number of cycles rename is unblocking
> system.cpu1.rename.RenamedInsts 271226 # Number of instructions processed by rename
> system.cpu1.rename.IQFullEvents 15241 # Number of times rename has blocked due to IQ full
> system.cpu1.rename.LQFullEvents 15 # Number of times rename has blocked due to LQ full
868,889c868,889
< system.cpu1.rename.RenamedOperands 198394 # Number of destination operands rename has renamed
< system.cpu1.rename.RenameLookups 541219 # Number of register rename lookups that rename has made
< system.cpu1.rename.int_rename_lookups 420944 # Number of integer rename lookups
< system.cpu1.rename.CommittedMaps 184552 # Number of HB maps that are committed
< system.cpu1.rename.UndoneMaps 13842 # Number of HB maps that are undone due to squashing
< system.cpu1.rename.serializingInsts 1192 # count of serializing insts renamed
< system.cpu1.rename.tempSerializingInsts 1257 # count of temporary serializing insts renamed
< system.cpu1.rename.skidInsts 20109 # count of insts added to the skid buffer
< system.cpu1.memDep0.insertedLoads 79403 # Number of loads inserted to the mem dependence unit.
< system.cpu1.memDep0.insertedStores 38032 # Number of stores inserted to the mem dependence unit.
< system.cpu1.memDep0.conflictingLoads 37516 # Number of conflicting loads.
< system.cpu1.memDep0.conflictingStores 32939 # Number of conflicting stores.
< system.cpu1.iq.iqInstsAdded 234221 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu1.iq.iqNonSpecInstsAdded 5649 # Number of non-speculative instructions added to the IQ
< system.cpu1.iq.iqInstsIssued 235400 # Number of instructions issued
< system.cpu1.iq.iqSquashedInstsIssued 7 # Number of squashed instructions issued
< system.cpu1.iq.iqSquashedInstsExamined 12841 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu1.iq.iqSquashedOperandsExamined 10393 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu1.iq.iqSquashedNonSpecRemoved 661 # Number of squashed non-spec instructions that were removed
< system.cpu1.iq.issued_per_cycle::samples 156846 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::mean 1.500835 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::stdev 1.378978 # Number of insts issued each cycle
---
> system.cpu1.rename.RenamedOperands 191192 # Number of destination operands rename has renamed
> system.cpu1.rename.RenameLookups 520363 # Number of register rename lookups that rename has made
> system.cpu1.rename.int_rename_lookups 405271 # Number of integer rename lookups
> system.cpu1.rename.CommittedMaps 177667 # Number of HB maps that are committed
> system.cpu1.rename.UndoneMaps 13525 # Number of HB maps that are undone due to squashing
> system.cpu1.rename.serializingInsts 1180 # count of serializing insts renamed
> system.cpu1.rename.tempSerializingInsts 1251 # count of temporary serializing insts renamed
> system.cpu1.rename.skidInsts 21370 # count of insts added to the skid buffer
> system.cpu1.memDep0.insertedLoads 76128 # Number of loads inserted to the mem dependence unit.
> system.cpu1.memDep0.insertedStores 36144 # Number of stores inserted to the mem dependence unit.
> system.cpu1.memDep0.conflictingLoads 36135 # Number of conflicting loads.
> system.cpu1.memDep0.conflictingStores 31079 # Number of conflicting stores.
> system.cpu1.iq.iqInstsAdded 225686 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu1.iq.iqNonSpecInstsAdded 6135 # Number of non-speculative instructions added to the IQ
> system.cpu1.iq.iqInstsIssued 227404 # Number of instructions issued
> system.cpu1.iq.iqSquashedInstsIssued 8 # Number of squashed instructions issued
> system.cpu1.iq.iqSquashedInstsExamined 12625 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu1.iq.iqSquashedOperandsExamined 10115 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu1.iq.iqSquashedNonSpecRemoved 706 # Number of squashed non-spec instructions that were removed
> system.cpu1.iq.issued_per_cycle::samples 156585 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::mean 1.452272 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::stdev 1.380275 # Number of insts issued each cycle
891,899c891,899
< system.cpu1.iq.issued_per_cycle::0 56627 36.10% 36.10% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::1 19405 12.37% 48.48% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::2 37510 23.92% 72.39% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::3 37026 23.61% 96.00% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::4 3380 2.15% 98.15% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::5 1607 1.02% 99.18% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::6 891 0.57% 99.74% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::7 204 0.13% 99.88% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::8 196 0.12% 100.00% # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::0 58755 37.52% 37.52% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::1 20747 13.25% 50.77% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::2 35642 22.76% 73.53% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::3 35172 22.46% 96.00% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::4 3374 2.15% 98.15% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::5 1612 1.03% 99.18% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::6 878 0.56% 99.74% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::7 207 0.13% 99.87% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::8 198 0.13% 100.00% # Number of insts issued each cycle
903c903
< system.cpu1.iq.issued_per_cycle::total 156846 # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::total 156585 # Number of insts issued each cycle
905,935c905,935
< system.cpu1.iq.fu_full::IntAlu 79 24.38% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntMult 0 0.00% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntDiv 0 0.00% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatAdd 0 0.00% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCmp 0 0.00% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCvt 0 0.00% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMult 0 0.00% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatDiv 0 0.00% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAdd 0 0.00% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAlu 0 0.00% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCmp 0 0.00% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCvt 0 0.00% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMisc 0 0.00% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMult 0 0.00% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShift 0 0.00% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 24.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemRead 36 11.11% 35.49% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemWrite 209 64.51% 100.00% # attempts to use FU when none available
---
> system.cpu1.iq.fu_full::IntAlu 79 24.01% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntMult 0 0.00% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntDiv 0 0.00% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatAdd 0 0.00% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCmp 0 0.00% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCvt 0 0.00% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMult 0 0.00% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatDiv 0 0.00% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAdd 0 0.00% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAlu 0 0.00% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCmp 0 0.00% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCvt 0 0.00% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMisc 0 0.00% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMult 0 0.00% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShift 0 0.00% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 24.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemRead 41 12.46% 36.47% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemWrite 209 63.53% 100.00% # attempts to use FU when none available
939,969c939,969
< system.cpu1.iq.FU_type_0::IntAlu 114995 48.85% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemRead 82971 35.25% 84.10% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemWrite 37434 15.90% 100.00% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::IntAlu 111654 49.10% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemRead 80158 35.25% 84.35% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemWrite 35592 15.65% 100.00% # Type of FU issued
972,978c972,978
< system.cpu1.iq.FU_type_0::total 235400 # Type of FU issued
< system.cpu1.iq.rate 1.445076 # Inst issue rate
< system.cpu1.iq.fu_busy_cnt 324 # FU busy when requested
< system.cpu1.iq.fu_busy_rate 0.001376 # FU busy rate (busy events/executed inst)
< system.cpu1.iq.int_inst_queue_reads 627977 # Number of integer instruction queue reads
< system.cpu1.iq.int_inst_queue_writes 252747 # Number of integer instruction queue writes
< system.cpu1.iq.int_inst_queue_wakeup_accesses 233879 # Number of integer instruction queue wakeup accesses
---
> system.cpu1.iq.FU_type_0::total 227404 # Type of FU issued
> system.cpu1.iq.rate 1.398325 # Inst issue rate
> system.cpu1.iq.fu_busy_cnt 329 # FU busy when requested
> system.cpu1.iq.fu_busy_rate 0.001447 # FU busy rate (busy events/executed inst)
> system.cpu1.iq.int_inst_queue_reads 611730 # Number of integer instruction queue reads
> system.cpu1.iq.int_inst_queue_writes 244482 # Number of integer instruction queue writes
> system.cpu1.iq.int_inst_queue_wakeup_accesses 225916 # Number of integer instruction queue wakeup accesses
982c982
< system.cpu1.iq.int_alu_accesses 235724 # Number of integer alu accesses
---
> system.cpu1.iq.int_alu_accesses 227733 # Number of integer alu accesses
984c984
< system.cpu1.iew.lsq.thread0.forwLoads 32768 # Number of loads that had data forwarded from stores
---
> system.cpu1.iew.lsq.thread0.forwLoads 30932 # Number of loads that had data forwarded from stores
986c986
< system.cpu1.iew.lsq.thread0.squashedLoads 2551 # Number of loads squashed
---
> system.cpu1.iew.lsq.thread0.squashedLoads 2495 # Number of loads squashed
989c989
< system.cpu1.iew.lsq.thread0.squashedStores 1483 # Number of stores squashed
---
> system.cpu1.iew.lsq.thread0.squashedStores 1427 # Number of stores squashed
995,1003c995,1003
< system.cpu1.iew.iewSquashCycles 1355 # Number of cycles IEW is squashing
< system.cpu1.iew.iewBlockCycles 6889 # Number of cycles IEW is blocking
< system.cpu1.iew.iewUnblockCycles 69 # Number of cycles IEW is unblocking
< system.cpu1.iew.iewDispatchedInsts 278263 # Number of instructions dispatched to IQ
< system.cpu1.iew.iewDispSquashedInsts 133 # Number of squashed instructions skipped by dispatch
< system.cpu1.iew.iewDispLoadInsts 79403 # Number of dispatched load instructions
< system.cpu1.iew.iewDispStoreInsts 38032 # Number of dispatched store instructions
< system.cpu1.iew.iewDispNonSpecInsts 1130 # Number of dispatched non-speculative instructions
< system.cpu1.iew.iewIQFullEvents 43 # Number of times the IQ has become full, causing a stall
---
> system.cpu1.iew.iewSquashCycles 1338 # Number of cycles IEW is squashing
> system.cpu1.iew.iewBlockCycles 7175 # Number of cycles IEW is blocking
> system.cpu1.iew.iewUnblockCycles 65 # Number of cycles IEW is unblocking
> system.cpu1.iew.iewDispatchedInsts 268817 # Number of instructions dispatched to IQ
> system.cpu1.iew.iewDispSquashedInsts 146 # Number of squashed instructions skipped by dispatch
> system.cpu1.iew.iewDispLoadInsts 76128 # Number of dispatched load instructions
> system.cpu1.iew.iewDispStoreInsts 36144 # Number of dispatched store instructions
> system.cpu1.iew.iewDispNonSpecInsts 1126 # Number of dispatched non-speculative instructions
> system.cpu1.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall
1006,1011c1006,1011
< system.cpu1.iew.predictedTakenIncorrect 442 # Number of branches that were predicted taken incorrectly
< system.cpu1.iew.predictedNotTakenIncorrect 1069 # Number of branches that were predicted not taken incorrectly
< system.cpu1.iew.branchMispredicts 1511 # Number of branch mispredicts detected at execute
< system.cpu1.iew.iewExecutedInsts 234388 # Number of executed instructions
< system.cpu1.iew.iewExecLoadInsts 78381 # Number of load instructions executed
< system.cpu1.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute
---
> system.cpu1.iew.predictedTakenIncorrect 440 # Number of branches that were predicted taken incorrectly
> system.cpu1.iew.predictedNotTakenIncorrect 1052 # Number of branches that were predicted not taken incorrectly
> system.cpu1.iew.branchMispredicts 1492 # Number of branch mispredicts detected at execute
> system.cpu1.iew.iewExecutedInsts 226425 # Number of executed instructions
> system.cpu1.iew.iewExecLoadInsts 75137 # Number of load instructions executed
> system.cpu1.iew.iewExecSquashedInsts 979 # Number of squashed instructions skipped in execute
1013,1029c1013,1029
< system.cpu1.iew.exec_nop 38393 # number of nop insts executed
< system.cpu1.iew.exec_refs 115730 # number of memory reference insts executed
< system.cpu1.iew.exec_branches 47858 # Number of branches executed
< system.cpu1.iew.exec_stores 37349 # Number of stores executed
< system.cpu1.iew.exec_rate 1.438864 # Inst execution rate
< system.cpu1.iew.wb_sent 234148 # cumulative count of insts sent to commit
< system.cpu1.iew.wb_count 233879 # cumulative count of insts written-back
< system.cpu1.iew.wb_producers 133368 # num instructions producing a value
< system.cpu1.iew.wb_consumers 139978 # num instructions consuming a value
< system.cpu1.iew.wb_rate 1.435739 # insts written-back per cycle
< system.cpu1.iew.wb_fanout 0.952778 # average fanout of values written-back
< system.cpu1.commit.commitSquashedInsts 13605 # The number of squashed insts skipped by commit
< system.cpu1.commit.commitNonSpecStalls 4988 # The number of times commit has been forced to stall to communicate backwards
< system.cpu1.commit.branchMispredicts 1277 # The number of times a branch was mispredicted
< system.cpu1.commit.committed_per_cycle::samples 154309 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::mean 1.714761 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::stdev 2.081585 # Number of insts commited each cycle
---
> system.cpu1.iew.exec_nop 36996 # number of nop insts executed
> system.cpu1.iew.exec_refs 110644 # number of memory reference insts executed
> system.cpu1.iew.exec_branches 46426 # Number of branches executed
> system.cpu1.iew.exec_stores 35507 # Number of stores executed
> system.cpu1.iew.exec_rate 1.392305 # Inst execution rate
> system.cpu1.iew.wb_sent 226182 # cumulative count of insts sent to commit
> system.cpu1.iew.wb_count 225916 # cumulative count of insts written-back
> system.cpu1.iew.wb_producers 128242 # num instructions producing a value
> system.cpu1.iew.wb_consumers 134834 # num instructions consuming a value
> system.cpu1.iew.wb_rate 1.389175 # insts written-back per cycle
> system.cpu1.iew.wb_fanout 0.951110 # average fanout of values written-back
> system.cpu1.commit.commitSquashedInsts 13383 # The number of squashed insts skipped by commit
> system.cpu1.commit.commitNonSpecStalls 5429 # The number of times commit has been forced to stall to communicate backwards
> system.cpu1.commit.branchMispredicts 1261 # The number of times a branch was mispredicted
> system.cpu1.commit.committed_per_cycle::samples 154086 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::mean 1.657380 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::stdev 2.063453 # Number of insts commited each cycle
1031,1039c1031,1039
< system.cpu1.commit.committed_per_cycle::0 61394 39.79% 39.79% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::1 44430 28.79% 68.58% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::2 5247 3.40% 71.98% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::3 5803 3.76% 75.74% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::4 1533 0.99% 76.73% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::5 32828 21.27% 98.01% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::6 824 0.53% 98.54% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::7 946 0.61% 99.15% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::8 1304 0.85% 100.00% # Number of insts commited each cycle
---
> system.cpu1.commit.committed_per_cycle::0 63982 41.52% 41.52% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::1 43006 27.91% 69.43% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::2 5237 3.40% 72.83% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::3 6258 4.06% 76.89% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::4 1532 0.99% 77.89% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::5 30979 20.11% 97.99% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::6 844 0.55% 98.54% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::7 946 0.61% 99.16% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::8 1302 0.84% 100.00% # Number of insts commited each cycle
1043,1045c1043,1045
< system.cpu1.commit.committed_per_cycle::total 154309 # Number of insts commited each cycle
< system.cpu1.commit.committedInsts 264603 # Number of instructions committed
< system.cpu1.commit.committedOps 264603 # Number of ops (including micro ops) committed
---
> system.cpu1.commit.committed_per_cycle::total 154086 # Number of insts commited each cycle
> system.cpu1.commit.committedInsts 255379 # Number of instructions committed
> system.cpu1.commit.committedOps 255379 # Number of ops (including micro ops) committed
1047,1050c1047,1050
< system.cpu1.commit.refs 113401 # Number of memory references committed
< system.cpu1.commit.loads 76852 # Number of loads committed
< system.cpu1.commit.membars 4272 # Number of memory barriers committed
< system.cpu1.commit.branches 46786 # Number of branches committed
---
> system.cpu1.commit.refs 108350 # Number of memory references committed
> system.cpu1.commit.loads 73633 # Number of loads committed
> system.cpu1.commit.membars 4715 # Number of memory barriers committed
> system.cpu1.commit.branches 45393 # Number of branches committed
1052c1052
< system.cpu1.commit.int_insts 182306 # Number of committed integer instructions.
---
> system.cpu1.commit.int_insts 175866 # Number of committed integer instructions.
1054,1085c1054,1085
< system.cpu1.commit.op_class_0::No_OpClass 37574 14.20% 14.20% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntAlu 109356 41.33% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.53% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemRead 81124 30.66% 86.19% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemWrite 36549 13.81% 100.00% # Class of committed instruction
---
> system.cpu1.commit.op_class_0::No_OpClass 36183 14.17% 14.17% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntAlu 106131 41.56% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemRead 78348 30.68% 86.41% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemWrite 34717 13.59% 100.00% # Class of committed instruction
1088,1093c1088,1093
< system.cpu1.commit.op_class_0::total 264603 # Class of committed instruction
< system.cpu1.commit.bw_lim_events 1304 # number cycles where commit BW limit reached
< system.cpu1.rob.rob_reads 430627 # The number of ROB reads
< system.cpu1.rob.rob_writes 558953 # The number of ROB writes
< system.cpu1.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu1.idleCycles 6052 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu1.commit.op_class_0::total 255379 # Class of committed instruction
> system.cpu1.commit.bw_lim_events 1302 # number cycles where commit BW limit reached
> system.cpu1.rob.rob_reads 420960 # The number of ROB reads
> system.cpu1.rob.rob_writes 540023 # The number of ROB writes
> system.cpu1.timesIdled 227 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu1.idleCycles 6041 # Total number of cycles that the CPU has spent unscheduled due to idling
1095,1102c1095,1102
< system.cpu1.committedInsts 222757 # Number of Instructions Simulated
< system.cpu1.committedOps 222757 # Number of Ops (including micro ops) Simulated
< system.cpu1.cpi 0.731281 # CPI: Cycles Per Instruction
< system.cpu1.cpi_total 0.731281 # CPI: Total CPI of All Threads
< system.cpu1.ipc 1.367463 # IPC: Instructions Per Cycle
< system.cpu1.ipc_total 1.367463 # IPC: Total IPC of All Threads
< system.cpu1.int_regfile_reads 407061 # number of integer regfile reads
< system.cpu1.int_regfile_writes 190501 # number of integer regfile writes
---
> system.cpu1.committedInsts 214481 # Number of Instructions Simulated
> system.cpu1.committedOps 214481 # Number of Ops (including micro ops) Simulated
> system.cpu1.cpi 0.758230 # CPI: Cycles Per Instruction
> system.cpu1.cpi_total 0.758230 # CPI: Total CPI of All Threads
> system.cpu1.ipc 1.318860 # IPC: Instructions Per Cycle
> system.cpu1.ipc_total 1.318860 # IPC: Total IPC of All Threads
> system.cpu1.int_regfile_reads 391734 # number of integer regfile reads
> system.cpu1.int_regfile_writes 183502 # number of integer regfile writes
1104c1104
< system.cpu1.misc_regfile_reads 117378 # number of misc regfile reads
---
> system.cpu1.misc_regfile_reads 112279 # number of misc regfile reads
1107,1110c1107,1110
< system.cpu1.dcache.tags.tagsinuse 25.769381 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 42560 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 1520 # Average number of references to valid blocks.
---
> system.cpu1.dcache.tags.tagsinuse 25.736588 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 40830 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 1407.931034 # Average number of references to valid blocks.
1112,1115c1112,1116
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.769381 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050331 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.050331 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id
---
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.736588 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050267 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.050267 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
1117,1179c1118,1180
< system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id
< system.cpu1.dcache.tags.tag_accesses 328816 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 328816 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 45076 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 45076 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 36319 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 36319 # number of WriteReq hits
< system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits
< system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 81395 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 81395 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 81395 # number of overall hits
< system.cpu1.dcache.overall_hits::total 81395 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 515 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 515 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 160 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 160 # number of WriteReq misses
< system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses
< system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 675 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 675 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 675 # number of overall misses
< system.cpu1.dcache.overall_misses::total 675 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 10357000 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 10357000 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3384000 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 3384000 # number of WriteReq miss cycles
< system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 705000 # number of SwapReq miss cycles
< system.cpu1.dcache.SwapReq_miss_latency::total 705000 # number of SwapReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 13741000 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 13741000 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 13741000 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 13741000 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 45591 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 45591 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 36479 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 36479 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses)
< system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 82070 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 82070 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 82070 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 82070 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011296 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.011296 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004386 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.004386 # miss rate for WriteReq accesses
< system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.800000 # miss rate for SwapReq accesses
< system.cpu1.dcache.SwapReq_miss_rate::total 0.800000 # miss rate for SwapReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.008225 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.008225 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.008225 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.008225 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20110.679612 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 20110.679612 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21150 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 21150 # average WriteReq miss latency
< system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 12589.285714 # average SwapReq miss latency
< system.cpu1.dcache.SwapReq_avg_miss_latency::total 12589.285714 # average SwapReq miss latency
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20357.037037 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 20357.037037 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20357.037037 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 20357.037037 # average overall miss latency
---
> system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
> system.cpu1.dcache.tags.tag_accesses 315852 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 315852 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 43688 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 43688 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 34492 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 34492 # number of WriteReq hits
> system.cpu1.dcache.SwapReq_hits::cpu1.data 17 # number of SwapReq hits
> system.cpu1.dcache.SwapReq_hits::total 17 # number of SwapReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 78180 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 78180 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 78180 # number of overall hits
> system.cpu1.dcache.overall_hits::total 78180 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 495 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 495 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 157 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 157 # number of WriteReq misses
> system.cpu1.dcache.SwapReq_misses::cpu1.data 51 # number of SwapReq misses
> system.cpu1.dcache.SwapReq_misses::total 51 # number of SwapReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 652 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 652 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 652 # number of overall misses
> system.cpu1.dcache.overall_misses::total 652 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8967000 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 8967000 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3364000 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 3364000 # number of WriteReq miss cycles
> system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 599000 # number of SwapReq miss cycles
> system.cpu1.dcache.SwapReq_miss_latency::total 599000 # number of SwapReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 12331000 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 12331000 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 12331000 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 12331000 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 44183 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 44183 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 34649 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 34649 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SwapReq_accesses::cpu1.data 68 # number of SwapReq accesses(hits+misses)
> system.cpu1.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 78832 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 78832 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 78832 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 78832 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011203 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.011203 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004531 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.004531 # miss rate for WriteReq accesses
> system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.750000 # miss rate for SwapReq accesses
> system.cpu1.dcache.SwapReq_miss_rate::total 0.750000 # miss rate for SwapReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.008271 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.008271 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.008271 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.008271 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18115.151515 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 18115.151515 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21426.751592 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 21426.751592 # average WriteReq miss latency
> system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 11745.098039 # average SwapReq miss latency
> system.cpu1.dcache.SwapReq_avg_miss_latency::total 11745.098039 # average SwapReq miss latency
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18912.576687 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 18912.576687 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18912.576687 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 18912.576687 # average overall miss latency
1188,1235c1189,1236
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 349 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 349 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 53 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 53 # number of WriteReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 402 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 402 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 402 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 402 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses
< system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses
< system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 273 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 273 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 273 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 273 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2153500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2153500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1760500 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1760500 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 649000 # number of SwapReq MSHR miss cycles
< system.cpu1.dcache.SwapReq_mshr_miss_latency::total 649000 # number of SwapReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3914000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 3914000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3914000 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 3914000 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003641 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003641 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002933 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002933 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SwapReq accesses
< system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.800000 # mshr miss rate for SwapReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003326 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.003326 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003326 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.003326 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12972.891566 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12972.891566 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16453.271028 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16453.271028 # average WriteReq mshr miss latency
< system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 11589.285714 # average SwapReq mshr miss latency
< system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 11589.285714 # average SwapReq mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14336.996337 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14336.996337 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14336.996337 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14336.996337 # average overall mshr miss latency
---
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 331 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 331 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 51 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 51 # number of WriteReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 382 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 382 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 382 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 382 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 164 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses
> system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 51 # number of SwapReq MSHR misses
> system.cpu1.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1988000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1988000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1748500 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1748500 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 548000 # number of SwapReq MSHR miss cycles
> system.cpu1.dcache.SwapReq_mshr_miss_latency::total 548000 # number of SwapReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3736500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 3736500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3736500 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 3736500 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003712 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003712 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003059 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003059 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.750000 # mshr miss rate for SwapReq accesses
> system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.750000 # mshr miss rate for SwapReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003425 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.003425 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003425 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.003425 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12121.951220 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12121.951220 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16495.283019 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16495.283019 # average WriteReq mshr miss latency
> system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10745.098039 # average SwapReq mshr miss latency
> system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10745.098039 # average SwapReq mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13838.888889 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13838.888889 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13838.888889 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13838.888889 # average overall mshr miss latency
1238,1239c1239,1240
< system.cpu1.icache.tags.tagsinuse 84.449474 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 19585 # Total number of references to valid blocks.
---
> system.cpu1.icache.tags.tagsinuse 84.417280 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 20534 # Total number of references to valid blocks.
1241c1242
< system.cpu1.icache.tags.avg_refs 39.485887 # Average number of references to valid blocks.
---
> system.cpu1.icache.tags.avg_refs 41.399194 # Average number of references to valid blocks.
1243,1245c1244,1246
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 84.449474 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.164940 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.164940 # Average percentage of cache occupancy
---
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 84.417280 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.164877 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.164877 # Average percentage of cache occupancy
1250,1287c1251,1288
< system.cpu1.icache.tags.tag_accesses 20661 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 20661 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 19585 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 19585 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 19585 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 19585 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 19585 # number of overall hits
< system.cpu1.icache.overall_hits::total 19585 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 580 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 580 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 580 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 580 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 580 # number of overall misses
< system.cpu1.icache.overall_misses::total 580 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14033000 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 14033000 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 14033000 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 14033000 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 14033000 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 14033000 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 20165 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 20165 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 20165 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 20165 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 20165 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 20165 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028763 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.028763 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028763 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.028763 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028763 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.028763 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24194.827586 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 24194.827586 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24194.827586 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 24194.827586 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24194.827586 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 24194.827586 # average overall miss latency
---
> system.cpu1.icache.tags.tag_accesses 21613 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 21613 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 20534 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 20534 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 20534 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 20534 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 20534 # number of overall hits
> system.cpu1.icache.overall_hits::total 20534 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 583 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 583 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 583 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 583 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 583 # number of overall misses
> system.cpu1.icache.overall_misses::total 583 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14299500 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 14299500 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 14299500 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 14299500 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 14299500 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 14299500 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 21117 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 21117 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 21117 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 21117 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 21117 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 21117 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.027608 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.027608 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.027608 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.027608 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.027608 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.027608 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24527.444254 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 24527.444254 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24527.444254 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 24527.444254 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24527.444254 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 24527.444254 # average overall miss latency
1298,1303c1299,1304
< system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 84 # number of ReadReq MSHR hits
< system.cpu1.icache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits
< system.cpu1.icache.demand_mshr_hits::cpu1.inst 84 # number of demand (read+write) MSHR hits
< system.cpu1.icache.demand_mshr_hits::total 84 # number of demand (read+write) MSHR hits
< system.cpu1.icache.overall_mshr_hits::cpu1.inst 84 # number of overall MSHR hits
< system.cpu1.icache.overall_mshr_hits::total 84 # number of overall MSHR hits
---
> system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 87 # number of ReadReq MSHR hits
> system.cpu1.icache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits
> system.cpu1.icache.demand_mshr_hits::cpu1.inst 87 # number of demand (read+write) MSHR hits
> system.cpu1.icache.demand_mshr_hits::total 87 # number of demand (read+write) MSHR hits
> system.cpu1.icache.overall_mshr_hits::cpu1.inst 87 # number of overall MSHR hits
> system.cpu1.icache.overall_mshr_hits::total 87 # number of overall MSHR hits
1310,1327c1311,1328
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11668000 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 11668000 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11668000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 11668000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11668000 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 11668000 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024597 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024597 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024597 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.024597 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024597 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.024597 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23524.193548 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23524.193548 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23524.193548 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 23524.193548 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23524.193548 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 23524.193548 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11785500 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 11785500 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11785500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 11785500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11785500 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 11785500 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023488 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023488 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023488 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.023488 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023488 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.023488 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23761.088710 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23761.088710 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23761.088710 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 23761.088710 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23761.088710 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 23761.088710 # average overall mshr miss latency
1329,1333c1330,1334
< system.cpu2.branchPred.lookups 46151 # Number of BP lookups
< system.cpu2.branchPred.condPredicted 42669 # Number of conditional branches predicted
< system.cpu2.branchPred.condIncorrect 1261 # Number of conditional branches incorrect
< system.cpu2.branchPred.BTBLookups 38744 # Number of BTB lookups
< system.cpu2.branchPred.BTBHits 37721 # Number of BTB hits
---
> system.cpu2.branchPred.lookups 51016 # Number of BP lookups
> system.cpu2.branchPred.condPredicted 47608 # Number of conditional branches predicted
> system.cpu2.branchPred.condIncorrect 1273 # Number of conditional branches incorrect
> system.cpu2.branchPred.BTBLookups 43707 # Number of BTB lookups
> system.cpu2.branchPred.BTBHits 42688 # Number of BTB hits
1335c1336
< system.cpu2.branchPred.BTBHitPct 97.359591 # BTB Hit Percentage
---
> system.cpu2.branchPred.BTBHitPct 97.668566 # BTB Hit Percentage
1338c1339
< system.cpu2.numCycles 162526 # number of cpu cycles simulated
---
> system.cpu2.numCycles 162253 # number of cpu cycles simulated
1341,1346c1342,1347
< system.cpu2.fetch.icacheStallCycles 35053 # Number of cycles fetch is stalled on an Icache miss
< system.cpu2.fetch.Insts 247865 # Number of instructions fetch has processed
< system.cpu2.fetch.Branches 46151 # Number of branches that fetch encountered
< system.cpu2.fetch.predictedBranches 38624 # Number of branches that fetch has predicted taken
< system.cpu2.fetch.Cycles 123337 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu2.fetch.SquashCycles 2679 # Number of cycles fetch has spent squashing
---
> system.cpu2.fetch.icacheStallCycles 31836 # Number of cycles fetch is stalled on an Icache miss
> system.cpu2.fetch.Insts 280333 # Number of instructions fetch has processed
> system.cpu2.fetch.Branches 51016 # Number of branches that fetch encountered
> system.cpu2.fetch.predictedBranches 43591 # Number of branches that fetch has predicted taken
> system.cpu2.fetch.Cycles 126252 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu2.fetch.SquashCycles 2703 # Number of cycles fetch has spent squashing
1349,1354c1350,1355
< system.cpu2.fetch.PendingTrapStallCycles 1154 # Number of stall cycles due to pending traps
< system.cpu2.fetch.CacheLines 26088 # Number of cache lines fetched
< system.cpu2.fetch.IcacheSquashes 455 # Number of outstanding Icache misses that were squashed
< system.cpu2.fetch.rateDist::samples 160896 # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::mean 1.540529 # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::stdev 2.092892 # Number of instructions fetched each cycle (Total)
---
> system.cpu2.fetch.PendingTrapStallCycles 1153 # Number of stall cycles due to pending traps
> system.cpu2.fetch.CacheLines 22874 # Number of cache lines fetched
> system.cpu2.fetch.IcacheSquashes 441 # Number of outstanding Icache misses that were squashed
> system.cpu2.fetch.rateDist::samples 160605 # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::mean 1.745481 # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::stdev 2.165535 # Number of instructions fetched each cycle (Total)
1356,1364c1357,1365
< system.cpu2.fetch.rateDist::0 69454 43.17% 43.17% # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::1 47444 29.49% 72.65% # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::2 8853 5.50% 78.16% # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::3 3439 2.14% 80.29% # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::4 969 0.60% 80.90% # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::5 24720 15.36% 96.26% # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::6 1203 0.75% 97.01% # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::7 808 0.50% 97.51% # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::8 4006 2.49% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu2.fetch.rateDist::0 60810 37.86% 37.86% # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::1 50841 31.66% 69.52% # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::2 7311 4.55% 74.07% # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::3 3498 2.18% 76.25% # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::4 961 0.60% 76.85% # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::5 31234 19.45% 96.30% # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::6 1226 0.76% 97.06% # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::7 786 0.49% 97.55% # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::8 3938 2.45% 100.00% # Number of instructions fetched each cycle (Total)
1368,1385c1369,1386
< system.cpu2.fetch.rateDist::total 160896 # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.branchRate 0.283961 # Number of branch fetches per cycle
< system.cpu2.fetch.rate 1.525079 # Number of inst fetches per cycle
< system.cpu2.decode.IdleCycles 17877 # Number of cycles decode is idle
< system.cpu2.decode.BlockedCycles 74268 # Number of cycles decode is blocked
< system.cpu2.decode.RunCycles 63015 # Number of cycles decode is running
< system.cpu2.decode.UnblockCycles 4387 # Number of cycles decode is unblocking
< system.cpu2.decode.SquashCycles 1339 # Number of cycles decode is squashing
< system.cpu2.decode.DecodedInsts 232406 # Number of instructions handled by decode
< system.cpu2.rename.SquashCycles 1339 # Number of cycles rename is squashing
< system.cpu2.rename.IdleCycles 18566 # Number of cycles rename is idle
< system.cpu2.rename.BlockCycles 36272 # Number of cycles rename is blocking
< system.cpu2.rename.serializeStallCycles 13923 # count of cycles rename stalled for serializing inst
< system.cpu2.rename.RunCycles 64728 # Number of cycles rename is running
< system.cpu2.rename.UnblockCycles 26058 # Number of cycles rename is unblocking
< system.cpu2.rename.RenamedInsts 229231 # Number of instructions processed by rename
< system.cpu2.rename.IQFullEvents 23352 # Number of times rename has blocked due to IQ full
< system.cpu2.rename.LQFullEvents 13 # Number of times rename has blocked due to LQ full
---
> system.cpu2.fetch.rateDist::total 160605 # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.branchRate 0.314423 # Number of branch fetches per cycle
> system.cpu2.fetch.rate 1.727752 # Number of inst fetches per cycle
> system.cpu2.decode.IdleCycles 17488 # Number of cycles decode is idle
> system.cpu2.decode.BlockedCycles 62772 # Number of cycles decode is blocked
> system.cpu2.decode.RunCycles 75260 # Number of cycles decode is running
> system.cpu2.decode.UnblockCycles 3724 # Number of cycles decode is unblocking
> system.cpu2.decode.SquashCycles 1351 # Number of cycles decode is squashing
> system.cpu2.decode.DecodedInsts 265175 # Number of instructions handled by decode
> system.cpu2.rename.SquashCycles 1351 # Number of cycles rename is squashing
> system.cpu2.rename.IdleCycles 18185 # Number of cycles rename is idle
> system.cpu2.rename.BlockCycles 29493 # Number of cycles rename is blocking
> system.cpu2.rename.serializeStallCycles 13900 # count of cycles rename stalled for serializing inst
> system.cpu2.rename.RunCycles 76790 # Number of cycles rename is running
> system.cpu2.rename.UnblockCycles 20876 # Number of cycles rename is unblocking
> system.cpu2.rename.RenamedInsts 262017 # Number of instructions processed by rename
> system.cpu2.rename.IQFullEvents 18650 # Number of times rename has blocked due to IQ full
> system.cpu2.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full
1387,1408c1388,1409
< system.cpu2.rename.RenamedOperands 159189 # Number of destination operands rename has renamed
< system.cpu2.rename.RenameLookups 426806 # Number of register rename lookups that rename has made
< system.cpu2.rename.int_rename_lookups 335096 # Number of integer rename lookups
< system.cpu2.rename.CommittedMaps 145681 # Number of HB maps that are committed
< system.cpu2.rename.UndoneMaps 13508 # Number of HB maps that are undone due to squashing
< system.cpu2.rename.serializingInsts 1198 # count of serializing insts renamed
< system.cpu2.rename.tempSerializingInsts 1266 # count of temporary serializing insts renamed
< system.cpu2.rename.skidInsts 30557 # count of insts added to the skid buffer
< system.cpu2.memDep0.insertedLoads 61312 # Number of loads inserted to the mem dependence unit.
< system.cpu2.memDep0.insertedStores 27565 # Number of stores inserted to the mem dependence unit.
< system.cpu2.memDep0.conflictingLoads 29913 # Number of conflicting loads.
< system.cpu2.memDep0.conflictingStores 22477 # Number of conflicting stores.
< system.cpu2.iq.iqInstsAdded 187400 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu2.iq.iqNonSpecInstsAdded 8554 # Number of non-speculative instructions added to the IQ
< system.cpu2.iq.iqInstsIssued 191519 # Number of instructions issued
< system.cpu2.iq.iqSquashedInstsIssued 13 # Number of squashed instructions issued
< system.cpu2.iq.iqSquashedInstsExamined 12551 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu2.iq.iqSquashedOperandsExamined 10065 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu2.iq.iqSquashedNonSpecRemoved 731 # Number of squashed non-spec instructions that were removed
< system.cpu2.iq.issued_per_cycle::samples 160896 # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::mean 1.190328 # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::stdev 1.355636 # Number of insts issued each cycle
---
> system.cpu2.rename.RenamedOperands 183428 # Number of destination operands rename has renamed
> system.cpu2.rename.RenameLookups 498093 # Number of register rename lookups that rename has made
> system.cpu2.rename.int_rename_lookups 388599 # Number of integer rename lookups
> system.cpu2.rename.CommittedMaps 169446 # Number of HB maps that are committed
> system.cpu2.rename.UndoneMaps 13982 # Number of HB maps that are undone due to squashing
> system.cpu2.rename.serializingInsts 1189 # count of serializing insts renamed
> system.cpu2.rename.tempSerializingInsts 1258 # count of temporary serializing insts renamed
> system.cpu2.rename.skidInsts 25354 # count of insts added to the skid buffer
> system.cpu2.memDep0.insertedLoads 72684 # Number of loads inserted to the mem dependence unit.
> system.cpu2.memDep0.insertedStores 33991 # Number of stores inserted to the mem dependence unit.
> system.cpu2.memDep0.conflictingLoads 34917 # Number of conflicting loads.
> system.cpu2.memDep0.conflictingStores 28890 # Number of conflicting stores.
> system.cpu2.iq.iqInstsAdded 216663 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu2.iq.iqNonSpecInstsAdded 7106 # Number of non-speculative instructions added to the IQ
> system.cpu2.iq.iqInstsIssued 219007 # Number of instructions issued
> system.cpu2.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued
> system.cpu2.iq.iqSquashedInstsExamined 13119 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu2.iq.iqSquashedOperandsExamined 11098 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu2.iq.iqSquashedNonSpecRemoved 687 # Number of squashed non-spec instructions that were removed
> system.cpu2.iq.issued_per_cycle::samples 160605 # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::mean 1.363637 # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::stdev 1.376138 # Number of insts issued each cycle
1410,1418c1411,1419
< system.cpu2.iq.issued_per_cycle::0 73129 45.45% 45.45% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::1 27885 17.33% 62.78% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::2 27023 16.80% 79.58% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::3 26608 16.54% 96.11% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::4 3367 2.09% 98.21% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::5 1611 1.00% 99.21% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::6 866 0.54% 99.75% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::7 211 0.13% 99.88% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::8 196 0.12% 100.00% # Number of insts issued each cycle
---
> system.cpu2.iq.issued_per_cycle::0 64456 40.13% 40.13% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::1 23625 14.71% 54.84% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::2 33318 20.75% 75.59% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::3 32915 20.49% 96.08% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::4 3374 2.10% 98.18% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::5 1611 1.00% 99.19% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::6 893 0.56% 99.74% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::7 212 0.13% 99.87% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::8 201 0.13% 100.00% # Number of insts issued each cycle
1422c1423
< system.cpu2.iq.issued_per_cycle::total 160896 # Number of insts issued each cycle
---
> system.cpu2.iq.issued_per_cycle::total 160605 # Number of insts issued each cycle
1424,1454c1425,1455
< system.cpu2.iq.fu_full::IntAlu 80 24.02% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::IntMult 0 0.00% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::IntDiv 0 0.00% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::FloatAdd 0 0.00% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::FloatCmp 0 0.00% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::FloatCvt 0 0.00% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::FloatMult 0 0.00% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::FloatDiv 0 0.00% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdAdd 0 0.00% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdAlu 0 0.00% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdCmp 0 0.00% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdCvt 0 0.00% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdMisc 0 0.00% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdMult 0 0.00% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdShift 0 0.00% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 24.02% # attempts to use FU when none available
< system.cpu2.iq.fu_full::MemRead 44 13.21% 37.24% # attempts to use FU when none available
< system.cpu2.iq.fu_full::MemWrite 209 62.76% 100.00% # attempts to use FU when none available
---
> system.cpu2.iq.fu_full::IntAlu 80 23.32% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::IntMult 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::MemRead 54 15.74% 39.07% # attempts to use FU when none available
> system.cpu2.iq.fu_full::MemWrite 209 60.93% 100.00% # attempts to use FU when none available
1458,1488c1459,1489
< system.cpu2.iq.FU_type_0::IntAlu 96792 50.54% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::IntMult 0 0.00% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.54% # Type of FU issued
< system.cpu2.iq.FU_type_0::MemRead 67722 35.36% 85.90% # Type of FU issued
< system.cpu2.iq.FU_type_0::MemWrite 27005 14.10% 100.00% # Type of FU issued
---
> system.cpu2.iq.FU_type_0::IntAlu 108075 49.35% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.35% # Type of FU issued
> system.cpu2.iq.FU_type_0::MemRead 77606 35.44% 84.78% # Type of FU issued
> system.cpu2.iq.FU_type_0::MemWrite 33326 15.22% 100.00% # Type of FU issued
1491,1497c1492,1498
< system.cpu2.iq.FU_type_0::total 191519 # Type of FU issued
< system.cpu2.iq.rate 1.178390 # Inst issue rate
< system.cpu2.iq.fu_busy_cnt 333 # FU busy when requested
< system.cpu2.iq.fu_busy_rate 0.001739 # FU busy rate (busy events/executed inst)
< system.cpu2.iq.int_inst_queue_reads 544280 # Number of integer instruction queue reads
< system.cpu2.iq.int_inst_queue_writes 208542 # Number of integer instruction queue writes
< system.cpu2.iq.int_inst_queue_wakeup_accesses 190032 # Number of integer instruction queue wakeup accesses
---
> system.cpu2.iq.FU_type_0::total 219007 # Type of FU issued
> system.cpu2.iq.rate 1.349787 # Inst issue rate
> system.cpu2.iq.fu_busy_cnt 343 # FU busy when requested
> system.cpu2.iq.fu_busy_rate 0.001566 # FU busy rate (busy events/executed inst)
> system.cpu2.iq.int_inst_queue_reads 598981 # Number of integer instruction queue reads
> system.cpu2.iq.int_inst_queue_writes 236927 # Number of integer instruction queue writes
> system.cpu2.iq.int_inst_queue_wakeup_accesses 217448 # Number of integer instruction queue wakeup accesses
1501c1502
< system.cpu2.iq.int_alu_accesses 191852 # Number of integer alu accesses
---
> system.cpu2.iq.int_alu_accesses 219350 # Number of integer alu accesses
1503c1504
< system.cpu2.iew.lsq.thread0.forwLoads 22329 # Number of loads that had data forwarded from stores
---
> system.cpu2.iew.lsq.thread0.forwLoads 28643 # Number of loads that had data forwarded from stores
1505c1506
< system.cpu2.iew.lsq.thread0.squashedLoads 2475 # Number of loads squashed
---
> system.cpu2.iew.lsq.thread0.squashedLoads 2671 # Number of loads squashed
1507,1508c1508,1509
< system.cpu2.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations
< system.cpu2.iew.lsq.thread0.squashedStores 1441 # Number of stores squashed
---
> system.cpu2.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations
> system.cpu2.iew.lsq.thread0.squashedStores 1575 # Number of stores squashed
1514,1515c1515,1516
< system.cpu2.iew.iewSquashCycles 1339 # Number of cycles IEW is squashing
< system.cpu2.iew.iewBlockCycles 9482 # Number of cycles IEW is blocking
---
> system.cpu2.iew.iewSquashCycles 1351 # Number of cycles IEW is squashing
> system.cpu2.iew.iewBlockCycles 8096 # Number of cycles IEW is blocking
1517,1522c1518,1523
< system.cpu2.iew.iewDispatchedInsts 226726 # Number of instructions dispatched to IQ
< system.cpu2.iew.iewDispSquashedInsts 191 # Number of squashed instructions skipped by dispatch
< system.cpu2.iew.iewDispLoadInsts 61312 # Number of dispatched load instructions
< system.cpu2.iew.iewDispStoreInsts 27565 # Number of dispatched store instructions
< system.cpu2.iew.iewDispNonSpecInsts 1142 # Number of dispatched non-speculative instructions
< system.cpu2.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall
---
> system.cpu2.iew.iewDispatchedInsts 259522 # Number of instructions dispatched to IQ
> system.cpu2.iew.iewDispSquashedInsts 168 # Number of squashed instructions skipped by dispatch
> system.cpu2.iew.iewDispLoadInsts 72684 # Number of dispatched load instructions
> system.cpu2.iew.iewDispStoreInsts 33991 # Number of dispatched store instructions
> system.cpu2.iew.iewDispNonSpecInsts 1139 # Number of dispatched non-speculative instructions
> system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall
1524,1530c1525,1531
< system.cpu2.iew.memOrderViolationEvents 37 # Number of memory order violations
< system.cpu2.iew.predictedTakenIncorrect 430 # Number of branches that were predicted taken incorrectly
< system.cpu2.iew.predictedNotTakenIncorrect 1052 # Number of branches that were predicted not taken incorrectly
< system.cpu2.iew.branchMispredicts 1482 # Number of branch mispredicts detected at execute
< system.cpu2.iew.iewExecutedInsts 190532 # Number of executed instructions
< system.cpu2.iew.iewExecLoadInsts 60316 # Number of load instructions executed
< system.cpu2.iew.iewExecSquashedInsts 987 # Number of squashed instructions skipped in execute
---
> system.cpu2.iew.memOrderViolationEvents 39 # Number of memory order violations
> system.cpu2.iew.predictedTakenIncorrect 443 # Number of branches that were predicted taken incorrectly
> system.cpu2.iew.predictedNotTakenIncorrect 1062 # Number of branches that were predicted not taken incorrectly
> system.cpu2.iew.branchMispredicts 1505 # Number of branch mispredicts detected at execute
> system.cpu2.iew.iewExecutedInsts 217972 # Number of executed instructions
> system.cpu2.iew.iewExecLoadInsts 71586 # Number of load instructions executed
> system.cpu2.iew.iewExecSquashedInsts 1035 # Number of squashed instructions skipped in execute
1532,1548c1533,1549
< system.cpu2.iew.exec_nop 30772 # number of nop insts executed
< system.cpu2.iew.exec_refs 87235 # number of memory reference insts executed
< system.cpu2.iew.exec_branches 40210 # Number of branches executed
< system.cpu2.iew.exec_stores 26919 # Number of stores executed
< system.cpu2.iew.exec_rate 1.172317 # Inst execution rate
< system.cpu2.iew.wb_sent 190296 # cumulative count of insts sent to commit
< system.cpu2.iew.wb_count 190032 # cumulative count of insts written-back
< system.cpu2.iew.wb_producers 104798 # num instructions producing a value
< system.cpu2.iew.wb_consumers 111375 # num instructions consuming a value
< system.cpu2.iew.wb_rate 1.169241 # insts written-back per cycle
< system.cpu2.iew.wb_fanout 0.940947 # average fanout of values written-back
< system.cpu2.commit.commitSquashedInsts 13298 # The number of squashed insts skipped by commit
< system.cpu2.commit.commitNonSpecStalls 7823 # The number of times commit has been forced to stall to communicate backwards
< system.cpu2.commit.branchMispredicts 1261 # The number of times a branch was mispredicted
< system.cpu2.commit.committed_per_cycle::samples 158397 # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::mean 1.347140 # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::stdev 1.933730 # Number of insts commited each cycle
---
> system.cpu2.iew.exec_nop 35753 # number of nop insts executed
> system.cpu2.iew.exec_refs 104818 # number of memory reference insts executed
> system.cpu2.iew.exec_branches 45124 # Number of branches executed
> system.cpu2.iew.exec_stores 33232 # Number of stores executed
> system.cpu2.iew.exec_rate 1.343408 # Inst execution rate
> system.cpu2.iew.wb_sent 217734 # cumulative count of insts sent to commit
> system.cpu2.iew.wb_count 217448 # cumulative count of insts written-back
> system.cpu2.iew.wb_producers 122408 # num instructions producing a value
> system.cpu2.iew.wb_consumers 129014 # num instructions consuming a value
> system.cpu2.iew.wb_rate 1.340179 # insts written-back per cycle
> system.cpu2.iew.wb_fanout 0.948796 # average fanout of values written-back
> system.cpu2.commit.commitSquashedInsts 13957 # The number of squashed insts skipped by commit
> system.cpu2.commit.commitNonSpecStalls 6419 # The number of times commit has been forced to stall to communicate backwards
> system.cpu2.commit.branchMispredicts 1273 # The number of times a branch was mispredicted
> system.cpu2.commit.committed_per_cycle::samples 158015 # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::mean 1.553777 # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::stdev 2.025126 # Number of insts commited each cycle
1550,1558c1551,1559
< system.cpu2.commit.committed_per_cycle::0 80708 50.95% 50.95% # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::1 36780 23.22% 74.17% # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::2 5258 3.32% 77.49% # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::3 8633 5.45% 82.94% # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::4 1531 0.97% 83.91% # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::5 22393 14.14% 98.05% # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::6 849 0.54% 98.58% # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::7 955 0.60% 99.19% # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::8 1290 0.81% 100.00% # Number of insts commited each cycle
---
> system.cpu2.commit.committed_per_cycle::0 70555 44.65% 44.65% # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::1 41677 26.38% 71.03% # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::2 5250 3.32% 74.35% # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::3 7214 4.57% 78.91% # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::4 1535 0.97% 79.89% # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::5 28695 18.16% 98.05% # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::6 838 0.53% 98.58% # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::7 950 0.60% 99.18% # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::8 1301 0.82% 100.00% # Number of insts commited each cycle
1562,1564c1563,1565
< system.cpu2.commit.committed_per_cycle::total 158397 # Number of insts commited each cycle
< system.cpu2.commit.committedInsts 213383 # Number of instructions committed
< system.cpu2.commit.committedOps 213383 # Number of ops (including micro ops) committed
---
> system.cpu2.commit.committed_per_cycle::total 158015 # Number of insts commited each cycle
> system.cpu2.commit.committedInsts 245520 # Number of instructions committed
> system.cpu2.commit.committedOps 245520 # Number of ops (including micro ops) committed
1566,1569c1567,1570
< system.cpu2.commit.refs 84961 # Number of memory references committed
< system.cpu2.commit.loads 58837 # Number of loads committed
< system.cpu2.commit.membars 7109 # Number of memory barriers committed
< system.cpu2.commit.branches 39190 # Number of branches committed
---
> system.cpu2.commit.refs 102429 # Number of memory references committed
> system.cpu2.commit.loads 70013 # Number of loads committed
> system.cpu2.commit.membars 5702 # Number of memory barriers committed
> system.cpu2.commit.branches 44083 # Number of branches committed
1571c1572
< system.cpu2.commit.int_insts 146276 # Number of committed integer instructions.
---
> system.cpu2.commit.int_insts 168630 # Number of committed integer instructions.
1573,1604c1574,1605
< system.cpu2.commit.op_class_0::No_OpClass 29980 14.05% 14.05% # Class of committed instruction
< system.cpu2.commit.op_class_0::IntAlu 91333 42.80% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::IntMult 0 0.00% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::IntDiv 0 0.00% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::FloatMult 0 0.00% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdMult 0 0.00% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdShift 0 0.00% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.85% # Class of committed instruction
< system.cpu2.commit.op_class_0::MemRead 65946 30.90% 87.76% # Class of committed instruction
< system.cpu2.commit.op_class_0::MemWrite 26124 12.24% 100.00% # Class of committed instruction
---
> system.cpu2.commit.op_class_0::No_OpClass 34870 14.20% 14.20% # Class of committed instruction
> system.cpu2.commit.op_class_0::IntAlu 102519 41.76% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.96% # Class of committed instruction
> system.cpu2.commit.op_class_0::MemRead 75715 30.84% 86.80% # Class of committed instruction
> system.cpu2.commit.op_class_0::MemWrite 32416 13.20% 100.00% # Class of committed instruction
1607,1612c1608,1613
< system.cpu2.commit.op_class_0::total 213383 # Class of committed instruction
< system.cpu2.commit.bw_lim_events 1290 # number cycles where commit BW limit reached
< system.cpu2.rob.rob_reads 383202 # The number of ROB reads
< system.cpu2.rob.rob_writes 455861 # The number of ROB writes
< system.cpu2.timesIdled 213 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu2.idleCycles 1630 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu2.commit.op_class_0::total 245520 # Class of committed instruction
> system.cpu2.commit.bw_lim_events 1301 # number cycles where commit BW limit reached
> system.cpu2.rob.rob_reads 415605 # The number of ROB reads
> system.cpu2.rob.rob_writes 521544 # The number of ROB writes
> system.cpu2.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu2.idleCycles 1648 # Total number of cycles that the CPU has spent unscheduled due to idling
1614,1621c1615,1622
< system.cpu2.committedInsts 176294 # Number of Instructions Simulated
< system.cpu2.committedOps 176294 # Number of Ops (including micro ops) Simulated
< system.cpu2.cpi 0.921903 # CPI: Cycles Per Instruction
< system.cpu2.cpi_total 0.921903 # CPI: Total CPI of All Threads
< system.cpu2.ipc 1.084713 # IPC: Instructions Per Cycle
< system.cpu2.ipc_total 1.084713 # IPC: Total IPC of All Threads
< system.cpu2.int_regfile_reads 321409 # number of integer regfile reads
< system.cpu2.int_regfile_writes 151400 # number of integer regfile writes
---
> system.cpu2.committedInsts 204948 # Number of Instructions Simulated
> system.cpu2.committedOps 204948 # Number of Ops (including micro ops) Simulated
> system.cpu2.cpi 0.791679 # CPI: Cycles Per Instruction
> system.cpu2.cpi_total 0.791679 # CPI: Total CPI of All Threads
> system.cpu2.ipc 1.263138 # IPC: Instructions Per Cycle
> system.cpu2.ipc_total 1.263138 # IPC: Total IPC of All Threads
> system.cpu2.int_regfile_reads 374158 # number of integer regfile reads
> system.cpu2.int_regfile_writes 175347 # number of integer regfile writes
1623c1624
< system.cpu2.misc_regfile_reads 88848 # number of misc regfile reads
---
> system.cpu2.misc_regfile_reads 106430 # number of misc regfile reads
1626,1629c1627,1630
< system.cpu2.dcache.tags.tagsinuse 23.120660 # Cycle average of tags in use
< system.cpu2.dcache.tags.total_refs 32242 # Total number of references to valid blocks.
< system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
< system.cpu2.dcache.tags.avg_refs 1111.793103 # Average number of references to valid blocks.
---
> system.cpu2.dcache.tags.tagsinuse 23.147052 # Cycle average of tags in use
> system.cpu2.dcache.tags.total_refs 38440 # Total number of references to valid blocks.
> system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
> system.cpu2.dcache.tags.avg_refs 1372.857143 # Average number of references to valid blocks.
1631,1635c1632,1635
< system.cpu2.dcache.tags.occ_blocks::cpu2.data 23.120660 # Average occupied blocks per requestor
< system.cpu2.dcache.tags.occ_percent::cpu2.data 0.045158 # Average percentage of cache occupancy
< system.cpu2.dcache.tags.occ_percent::total 0.045158 # Average percentage of cache occupancy
< system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
< system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
---
> system.cpu2.dcache.tags.occ_blocks::cpu2.data 23.147052 # Average occupied blocks per requestor
> system.cpu2.dcache.tags.occ_percent::cpu2.data 0.045209 # Average percentage of cache occupancy
> system.cpu2.dcache.tags.occ_percent::total 0.045209 # Average percentage of cache occupancy
> system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id
1637,1699c1637,1699
< system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
< system.cpu2.dcache.tags.tag_accesses 256599 # Number of tag accesses
< system.cpu2.dcache.tags.data_accesses 256599 # Number of data accesses
< system.cpu2.dcache.ReadReq_hits::cpu2.data 37491 # number of ReadReq hits
< system.cpu2.dcache.ReadReq_hits::total 37491 # number of ReadReq hits
< system.cpu2.dcache.WriteReq_hits::cpu2.data 25903 # number of WriteReq hits
< system.cpu2.dcache.WriteReq_hits::total 25903 # number of WriteReq hits
< system.cpu2.dcache.SwapReq_hits::cpu2.data 19 # number of SwapReq hits
< system.cpu2.dcache.SwapReq_hits::total 19 # number of SwapReq hits
< system.cpu2.dcache.demand_hits::cpu2.data 63394 # number of demand (read+write) hits
< system.cpu2.dcache.demand_hits::total 63394 # number of demand (read+write) hits
< system.cpu2.dcache.overall_hits::cpu2.data 63394 # number of overall hits
< system.cpu2.dcache.overall_hits::total 63394 # number of overall hits
< system.cpu2.dcache.ReadReq_misses::cpu2.data 473 # number of ReadReq misses
< system.cpu2.dcache.ReadReq_misses::total 473 # number of ReadReq misses
< system.cpu2.dcache.WriteReq_misses::cpu2.data 153 # number of WriteReq misses
< system.cpu2.dcache.WriteReq_misses::total 153 # number of WriteReq misses
< system.cpu2.dcache.SwapReq_misses::cpu2.data 49 # number of SwapReq misses
< system.cpu2.dcache.SwapReq_misses::total 49 # number of SwapReq misses
< system.cpu2.dcache.demand_misses::cpu2.data 626 # number of demand (read+write) misses
< system.cpu2.dcache.demand_misses::total 626 # number of demand (read+write) misses
< system.cpu2.dcache.overall_misses::cpu2.data 626 # number of overall misses
< system.cpu2.dcache.overall_misses::total 626 # number of overall misses
< system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7957500 # number of ReadReq miss cycles
< system.cpu2.dcache.ReadReq_miss_latency::total 7957500 # number of ReadReq miss cycles
< system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3701500 # number of WriteReq miss cycles
< system.cpu2.dcache.WriteReq_miss_latency::total 3701500 # number of WriteReq miss cycles
< system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 605000 # number of SwapReq miss cycles
< system.cpu2.dcache.SwapReq_miss_latency::total 605000 # number of SwapReq miss cycles
< system.cpu2.dcache.demand_miss_latency::cpu2.data 11659000 # number of demand (read+write) miss cycles
< system.cpu2.dcache.demand_miss_latency::total 11659000 # number of demand (read+write) miss cycles
< system.cpu2.dcache.overall_miss_latency::cpu2.data 11659000 # number of overall miss cycles
< system.cpu2.dcache.overall_miss_latency::total 11659000 # number of overall miss cycles
< system.cpu2.dcache.ReadReq_accesses::cpu2.data 37964 # number of ReadReq accesses(hits+misses)
< system.cpu2.dcache.ReadReq_accesses::total 37964 # number of ReadReq accesses(hits+misses)
< system.cpu2.dcache.WriteReq_accesses::cpu2.data 26056 # number of WriteReq accesses(hits+misses)
< system.cpu2.dcache.WriteReq_accesses::total 26056 # number of WriteReq accesses(hits+misses)
< system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses)
< system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses)
< system.cpu2.dcache.demand_accesses::cpu2.data 64020 # number of demand (read+write) accesses
< system.cpu2.dcache.demand_accesses::total 64020 # number of demand (read+write) accesses
< system.cpu2.dcache.overall_accesses::cpu2.data 64020 # number of overall (read+write) accesses
< system.cpu2.dcache.overall_accesses::total 64020 # number of overall (read+write) accesses
< system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.012459 # miss rate for ReadReq accesses
< system.cpu2.dcache.ReadReq_miss_rate::total 0.012459 # miss rate for ReadReq accesses
< system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.005872 # miss rate for WriteReq accesses
< system.cpu2.dcache.WriteReq_miss_rate::total 0.005872 # miss rate for WriteReq accesses
< system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.720588 # miss rate for SwapReq accesses
< system.cpu2.dcache.SwapReq_miss_rate::total 0.720588 # miss rate for SwapReq accesses
< system.cpu2.dcache.demand_miss_rate::cpu2.data 0.009778 # miss rate for demand accesses
< system.cpu2.dcache.demand_miss_rate::total 0.009778 # miss rate for demand accesses
< system.cpu2.dcache.overall_miss_rate::cpu2.data 0.009778 # miss rate for overall accesses
< system.cpu2.dcache.overall_miss_rate::total 0.009778 # miss rate for overall accesses
< system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16823.467230 # average ReadReq miss latency
< system.cpu2.dcache.ReadReq_avg_miss_latency::total 16823.467230 # average ReadReq miss latency
< system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24192.810458 # average WriteReq miss latency
< system.cpu2.dcache.WriteReq_avg_miss_latency::total 24192.810458 # average WriteReq miss latency
< system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 12346.938776 # average SwapReq miss latency
< system.cpu2.dcache.SwapReq_avg_miss_latency::total 12346.938776 # average SwapReq miss latency
< system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 18624.600639 # average overall miss latency
< system.cpu2.dcache.demand_avg_miss_latency::total 18624.600639 # average overall miss latency
< system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 18624.600639 # average overall miss latency
< system.cpu2.dcache.overall_avg_miss_latency::total 18624.600639 # average overall miss latency
---
> system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id
> system.cpu2.dcache.tags.tag_accesses 301603 # Number of tag accesses
> system.cpu2.dcache.tags.data_accesses 301603 # Number of data accesses
> system.cpu2.dcache.ReadReq_hits::cpu2.data 42391 # number of ReadReq hits
> system.cpu2.dcache.ReadReq_hits::total 42391 # number of ReadReq hits
> system.cpu2.dcache.WriteReq_hits::cpu2.data 32186 # number of WriteReq hits
> system.cpu2.dcache.WriteReq_hits::total 32186 # number of WriteReq hits
> system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits
> system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits
> system.cpu2.dcache.demand_hits::cpu2.data 74577 # number of demand (read+write) hits
> system.cpu2.dcache.demand_hits::total 74577 # number of demand (read+write) hits
> system.cpu2.dcache.overall_hits::cpu2.data 74577 # number of overall hits
> system.cpu2.dcache.overall_hits::total 74577 # number of overall hits
> system.cpu2.dcache.ReadReq_misses::cpu2.data 529 # number of ReadReq misses
> system.cpu2.dcache.ReadReq_misses::total 529 # number of ReadReq misses
> system.cpu2.dcache.WriteReq_misses::cpu2.data 159 # number of WriteReq misses
> system.cpu2.dcache.WriteReq_misses::total 159 # number of WriteReq misses
> system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses
> system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses
> system.cpu2.dcache.demand_misses::cpu2.data 688 # number of demand (read+write) misses
> system.cpu2.dcache.demand_misses::total 688 # number of demand (read+write) misses
> system.cpu2.dcache.overall_misses::cpu2.data 688 # number of overall misses
> system.cpu2.dcache.overall_misses::total 688 # number of overall misses
> system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 8601000 # number of ReadReq miss cycles
> system.cpu2.dcache.ReadReq_miss_latency::total 8601000 # number of ReadReq miss cycles
> system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3593000 # number of WriteReq miss cycles
> system.cpu2.dcache.WriteReq_miss_latency::total 3593000 # number of WriteReq miss cycles
> system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 655000 # number of SwapReq miss cycles
> system.cpu2.dcache.SwapReq_miss_latency::total 655000 # number of SwapReq miss cycles
> system.cpu2.dcache.demand_miss_latency::cpu2.data 12194000 # number of demand (read+write) miss cycles
> system.cpu2.dcache.demand_miss_latency::total 12194000 # number of demand (read+write) miss cycles
> system.cpu2.dcache.overall_miss_latency::cpu2.data 12194000 # number of overall miss cycles
> system.cpu2.dcache.overall_miss_latency::total 12194000 # number of overall miss cycles
> system.cpu2.dcache.ReadReq_accesses::cpu2.data 42920 # number of ReadReq accesses(hits+misses)
> system.cpu2.dcache.ReadReq_accesses::total 42920 # number of ReadReq accesses(hits+misses)
> system.cpu2.dcache.WriteReq_accesses::cpu2.data 32345 # number of WriteReq accesses(hits+misses)
> system.cpu2.dcache.WriteReq_accesses::total 32345 # number of WriteReq accesses(hits+misses)
> system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses)
> system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
> system.cpu2.dcache.demand_accesses::cpu2.data 75265 # number of demand (read+write) accesses
> system.cpu2.dcache.demand_accesses::total 75265 # number of demand (read+write) accesses
> system.cpu2.dcache.overall_accesses::cpu2.data 75265 # number of overall (read+write) accesses
> system.cpu2.dcache.overall_accesses::total 75265 # number of overall (read+write) accesses
> system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.012325 # miss rate for ReadReq accesses
> system.cpu2.dcache.ReadReq_miss_rate::total 0.012325 # miss rate for ReadReq accesses
> system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004916 # miss rate for WriteReq accesses
> system.cpu2.dcache.WriteReq_miss_rate::total 0.004916 # miss rate for WriteReq accesses
> system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.816901 # miss rate for SwapReq accesses
> system.cpu2.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses
> system.cpu2.dcache.demand_miss_rate::cpu2.data 0.009141 # miss rate for demand accesses
> system.cpu2.dcache.demand_miss_rate::total 0.009141 # miss rate for demand accesses
> system.cpu2.dcache.overall_miss_rate::cpu2.data 0.009141 # miss rate for overall accesses
> system.cpu2.dcache.overall_miss_rate::total 0.009141 # miss rate for overall accesses
> system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16258.979206 # average ReadReq miss latency
> system.cpu2.dcache.ReadReq_avg_miss_latency::total 16258.979206 # average ReadReq miss latency
> system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22597.484277 # average WriteReq miss latency
> system.cpu2.dcache.WriteReq_avg_miss_latency::total 22597.484277 # average WriteReq miss latency
> system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 11293.103448 # average SwapReq miss latency
> system.cpu2.dcache.SwapReq_avg_miss_latency::total 11293.103448 # average SwapReq miss latency
> system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17723.837209 # average overall miss latency
> system.cpu2.dcache.demand_avg_miss_latency::total 17723.837209 # average overall miss latency
> system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17723.837209 # average overall miss latency
> system.cpu2.dcache.overall_avg_miss_latency::total 17723.837209 # average overall miss latency
1708,1755c1708,1755
< system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 311 # number of ReadReq MSHR hits
< system.cpu2.dcache.ReadReq_mshr_hits::total 311 # number of ReadReq MSHR hits
< system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 50 # number of WriteReq MSHR hits
< system.cpu2.dcache.WriteReq_mshr_hits::total 50 # number of WriteReq MSHR hits
< system.cpu2.dcache.demand_mshr_hits::cpu2.data 361 # number of demand (read+write) MSHR hits
< system.cpu2.dcache.demand_mshr_hits::total 361 # number of demand (read+write) MSHR hits
< system.cpu2.dcache.overall_mshr_hits::cpu2.data 361 # number of overall MSHR hits
< system.cpu2.dcache.overall_mshr_hits::total 361 # number of overall MSHR hits
< system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses
< system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses
< system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 103 # number of WriteReq MSHR misses
< system.cpu2.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses
< system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 49 # number of SwapReq MSHR misses
< system.cpu2.dcache.SwapReq_mshr_misses::total 49 # number of SwapReq MSHR misses
< system.cpu2.dcache.demand_mshr_misses::cpu2.data 265 # number of demand (read+write) MSHR misses
< system.cpu2.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses
< system.cpu2.dcache.overall_mshr_misses::cpu2.data 265 # number of overall MSHR misses
< system.cpu2.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses
< system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1647500 # number of ReadReq MSHR miss cycles
< system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1647500 # number of ReadReq MSHR miss cycles
< system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1967500 # number of WriteReq MSHR miss cycles
< system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1967500 # number of WriteReq MSHR miss cycles
< system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 556000 # number of SwapReq MSHR miss cycles
< system.cpu2.dcache.SwapReq_mshr_miss_latency::total 556000 # number of SwapReq MSHR miss cycles
< system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3615000 # number of demand (read+write) MSHR miss cycles
< system.cpu2.dcache.demand_mshr_miss_latency::total 3615000 # number of demand (read+write) MSHR miss cycles
< system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3615000 # number of overall MSHR miss cycles
< system.cpu2.dcache.overall_mshr_miss_latency::total 3615000 # number of overall MSHR miss cycles
< system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004267 # mshr miss rate for ReadReq accesses
< system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004267 # mshr miss rate for ReadReq accesses
< system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003953 # mshr miss rate for WriteReq accesses
< system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003953 # mshr miss rate for WriteReq accesses
< system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.720588 # mshr miss rate for SwapReq accesses
< system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.720588 # mshr miss rate for SwapReq accesses
< system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004139 # mshr miss rate for demand accesses
< system.cpu2.dcache.demand_mshr_miss_rate::total 0.004139 # mshr miss rate for demand accesses
< system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004139 # mshr miss rate for overall accesses
< system.cpu2.dcache.overall_mshr_miss_rate::total 0.004139 # mshr miss rate for overall accesses
< system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10169.753086 # average ReadReq mshr miss latency
< system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10169.753086 # average ReadReq mshr miss latency
< system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19101.941748 # average WriteReq mshr miss latency
< system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19101.941748 # average WriteReq mshr miss latency
< system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 11346.938776 # average SwapReq mshr miss latency
< system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 11346.938776 # average SwapReq mshr miss latency
< system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13641.509434 # average overall mshr miss latency
< system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13641.509434 # average overall mshr miss latency
< system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13641.509434 # average overall mshr miss latency
< system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13641.509434 # average overall mshr miss latency
---
> system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 359 # number of ReadReq MSHR hits
> system.cpu2.dcache.ReadReq_mshr_hits::total 359 # number of ReadReq MSHR hits
> system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 53 # number of WriteReq MSHR hits
> system.cpu2.dcache.WriteReq_mshr_hits::total 53 # number of WriteReq MSHR hits
> system.cpu2.dcache.demand_mshr_hits::cpu2.data 412 # number of demand (read+write) MSHR hits
> system.cpu2.dcache.demand_mshr_hits::total 412 # number of demand (read+write) MSHR hits
> system.cpu2.dcache.overall_mshr_hits::cpu2.data 412 # number of overall MSHR hits
> system.cpu2.dcache.overall_mshr_hits::total 412 # number of overall MSHR hits
> system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 170 # number of ReadReq MSHR misses
> system.cpu2.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses
> system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses
> system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses
> system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses
> system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses
> system.cpu2.dcache.demand_mshr_misses::cpu2.data 276 # number of demand (read+write) MSHR misses
> system.cpu2.dcache.demand_mshr_misses::total 276 # number of demand (read+write) MSHR misses
> system.cpu2.dcache.overall_mshr_misses::cpu2.data 276 # number of overall MSHR misses
> system.cpu2.dcache.overall_mshr_misses::total 276 # number of overall MSHR misses
> system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1653000 # number of ReadReq MSHR miss cycles
> system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1653000 # number of ReadReq MSHR miss cycles
> system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1845000 # number of WriteReq MSHR miss cycles
> system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1845000 # number of WriteReq MSHR miss cycles
> system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 597000 # number of SwapReq MSHR miss cycles
> system.cpu2.dcache.SwapReq_mshr_miss_latency::total 597000 # number of SwapReq MSHR miss cycles
> system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3498000 # number of demand (read+write) MSHR miss cycles
> system.cpu2.dcache.demand_mshr_miss_latency::total 3498000 # number of demand (read+write) MSHR miss cycles
> system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3498000 # number of overall MSHR miss cycles
> system.cpu2.dcache.overall_mshr_miss_latency::total 3498000 # number of overall MSHR miss cycles
> system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003961 # mshr miss rate for ReadReq accesses
> system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003961 # mshr miss rate for ReadReq accesses
> system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003277 # mshr miss rate for WriteReq accesses
> system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003277 # mshr miss rate for WriteReq accesses
> system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.816901 # mshr miss rate for SwapReq accesses
> system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses
> system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003667 # mshr miss rate for demand accesses
> system.cpu2.dcache.demand_mshr_miss_rate::total 0.003667 # mshr miss rate for demand accesses
> system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003667 # mshr miss rate for overall accesses
> system.cpu2.dcache.overall_mshr_miss_rate::total 0.003667 # mshr miss rate for overall accesses
> system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9723.529412 # average ReadReq mshr miss latency
> system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9723.529412 # average ReadReq mshr miss latency
> system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 17405.660377 # average WriteReq mshr miss latency
> system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 17405.660377 # average WriteReq mshr miss latency
> system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 10293.103448 # average SwapReq mshr miss latency
> system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 10293.103448 # average SwapReq mshr miss latency
> system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12673.913043 # average overall mshr miss latency
> system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12673.913043 # average overall mshr miss latency
> system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12673.913043 # average overall mshr miss latency
> system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12673.913043 # average overall mshr miss latency
1758,1759c1758,1759
< system.cpu2.icache.tags.tagsinuse 77.580266 # Cycle average of tags in use
< system.cpu2.icache.tags.total_refs 25515 # Total number of references to valid blocks.
---
> system.cpu2.icache.tags.tagsinuse 77.661611 # Cycle average of tags in use
> system.cpu2.icache.tags.total_refs 22304 # Total number of references to valid blocks.
1761c1761
< system.cpu2.icache.tags.avg_refs 51.030000 # Average number of references to valid blocks.
---
> system.cpu2.icache.tags.avg_refs 44.608000 # Average number of references to valid blocks.
1763,1765c1763,1765
< system.cpu2.icache.tags.occ_blocks::cpu2.inst 77.580266 # Average occupied blocks per requestor
< system.cpu2.icache.tags.occ_percent::cpu2.inst 0.151524 # Average percentage of cache occupancy
< system.cpu2.icache.tags.occ_percent::total 0.151524 # Average percentage of cache occupancy
---
> system.cpu2.icache.tags.occ_blocks::cpu2.inst 77.661611 # Average occupied blocks per requestor
> system.cpu2.icache.tags.occ_percent::cpu2.inst 0.151683 # Average percentage of cache occupancy
> system.cpu2.icache.tags.occ_percent::total 0.151683 # Average percentage of cache occupancy
1770,1807c1770,1807
< system.cpu2.icache.tags.tag_accesses 26588 # Number of tag accesses
< system.cpu2.icache.tags.data_accesses 26588 # Number of data accesses
< system.cpu2.icache.ReadReq_hits::cpu2.inst 25515 # number of ReadReq hits
< system.cpu2.icache.ReadReq_hits::total 25515 # number of ReadReq hits
< system.cpu2.icache.demand_hits::cpu2.inst 25515 # number of demand (read+write) hits
< system.cpu2.icache.demand_hits::total 25515 # number of demand (read+write) hits
< system.cpu2.icache.overall_hits::cpu2.inst 25515 # number of overall hits
< system.cpu2.icache.overall_hits::total 25515 # number of overall hits
< system.cpu2.icache.ReadReq_misses::cpu2.inst 573 # number of ReadReq misses
< system.cpu2.icache.ReadReq_misses::total 573 # number of ReadReq misses
< system.cpu2.icache.demand_misses::cpu2.inst 573 # number of demand (read+write) misses
< system.cpu2.icache.demand_misses::total 573 # number of demand (read+write) misses
< system.cpu2.icache.overall_misses::cpu2.inst 573 # number of overall misses
< system.cpu2.icache.overall_misses::total 573 # number of overall misses
< system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7955500 # number of ReadReq miss cycles
< system.cpu2.icache.ReadReq_miss_latency::total 7955500 # number of ReadReq miss cycles
< system.cpu2.icache.demand_miss_latency::cpu2.inst 7955500 # number of demand (read+write) miss cycles
< system.cpu2.icache.demand_miss_latency::total 7955500 # number of demand (read+write) miss cycles
< system.cpu2.icache.overall_miss_latency::cpu2.inst 7955500 # number of overall miss cycles
< system.cpu2.icache.overall_miss_latency::total 7955500 # number of overall miss cycles
< system.cpu2.icache.ReadReq_accesses::cpu2.inst 26088 # number of ReadReq accesses(hits+misses)
< system.cpu2.icache.ReadReq_accesses::total 26088 # number of ReadReq accesses(hits+misses)
< system.cpu2.icache.demand_accesses::cpu2.inst 26088 # number of demand (read+write) accesses
< system.cpu2.icache.demand_accesses::total 26088 # number of demand (read+write) accesses
< system.cpu2.icache.overall_accesses::cpu2.inst 26088 # number of overall (read+write) accesses
< system.cpu2.icache.overall_accesses::total 26088 # number of overall (read+write) accesses
< system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.021964 # miss rate for ReadReq accesses
< system.cpu2.icache.ReadReq_miss_rate::total 0.021964 # miss rate for ReadReq accesses
< system.cpu2.icache.demand_miss_rate::cpu2.inst 0.021964 # miss rate for demand accesses
< system.cpu2.icache.demand_miss_rate::total 0.021964 # miss rate for demand accesses
< system.cpu2.icache.overall_miss_rate::cpu2.inst 0.021964 # miss rate for overall accesses
< system.cpu2.icache.overall_miss_rate::total 0.021964 # miss rate for overall accesses
< system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13883.944154 # average ReadReq miss latency
< system.cpu2.icache.ReadReq_avg_miss_latency::total 13883.944154 # average ReadReq miss latency
< system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13883.944154 # average overall miss latency
< system.cpu2.icache.demand_avg_miss_latency::total 13883.944154 # average overall miss latency
< system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13883.944154 # average overall miss latency
< system.cpu2.icache.overall_avg_miss_latency::total 13883.944154 # average overall miss latency
---
> system.cpu2.icache.tags.tag_accesses 23374 # Number of tag accesses
> system.cpu2.icache.tags.data_accesses 23374 # Number of data accesses
> system.cpu2.icache.ReadReq_hits::cpu2.inst 22304 # number of ReadReq hits
> system.cpu2.icache.ReadReq_hits::total 22304 # number of ReadReq hits
> system.cpu2.icache.demand_hits::cpu2.inst 22304 # number of demand (read+write) hits
> system.cpu2.icache.demand_hits::total 22304 # number of demand (read+write) hits
> system.cpu2.icache.overall_hits::cpu2.inst 22304 # number of overall hits
> system.cpu2.icache.overall_hits::total 22304 # number of overall hits
> system.cpu2.icache.ReadReq_misses::cpu2.inst 570 # number of ReadReq misses
> system.cpu2.icache.ReadReq_misses::total 570 # number of ReadReq misses
> system.cpu2.icache.demand_misses::cpu2.inst 570 # number of demand (read+write) misses
> system.cpu2.icache.demand_misses::total 570 # number of demand (read+write) misses
> system.cpu2.icache.overall_misses::cpu2.inst 570 # number of overall misses
> system.cpu2.icache.overall_misses::total 570 # number of overall misses
> system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8095000 # number of ReadReq miss cycles
> system.cpu2.icache.ReadReq_miss_latency::total 8095000 # number of ReadReq miss cycles
> system.cpu2.icache.demand_miss_latency::cpu2.inst 8095000 # number of demand (read+write) miss cycles
> system.cpu2.icache.demand_miss_latency::total 8095000 # number of demand (read+write) miss cycles
> system.cpu2.icache.overall_miss_latency::cpu2.inst 8095000 # number of overall miss cycles
> system.cpu2.icache.overall_miss_latency::total 8095000 # number of overall miss cycles
> system.cpu2.icache.ReadReq_accesses::cpu2.inst 22874 # number of ReadReq accesses(hits+misses)
> system.cpu2.icache.ReadReq_accesses::total 22874 # number of ReadReq accesses(hits+misses)
> system.cpu2.icache.demand_accesses::cpu2.inst 22874 # number of demand (read+write) accesses
> system.cpu2.icache.demand_accesses::total 22874 # number of demand (read+write) accesses
> system.cpu2.icache.overall_accesses::cpu2.inst 22874 # number of overall (read+write) accesses
> system.cpu2.icache.overall_accesses::total 22874 # number of overall (read+write) accesses
> system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024919 # miss rate for ReadReq accesses
> system.cpu2.icache.ReadReq_miss_rate::total 0.024919 # miss rate for ReadReq accesses
> system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024919 # miss rate for demand accesses
> system.cpu2.icache.demand_miss_rate::total 0.024919 # miss rate for demand accesses
> system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024919 # miss rate for overall accesses
> system.cpu2.icache.overall_miss_rate::total 0.024919 # miss rate for overall accesses
> system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14201.754386 # average ReadReq miss latency
> system.cpu2.icache.ReadReq_avg_miss_latency::total 14201.754386 # average ReadReq miss latency
> system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14201.754386 # average overall miss latency
> system.cpu2.icache.demand_avg_miss_latency::total 14201.754386 # average overall miss latency
> system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14201.754386 # average overall miss latency
> system.cpu2.icache.overall_avg_miss_latency::total 14201.754386 # average overall miss latency
1818,1823c1818,1823
< system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 73 # number of ReadReq MSHR hits
< system.cpu2.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
< system.cpu2.icache.demand_mshr_hits::cpu2.inst 73 # number of demand (read+write) MSHR hits
< system.cpu2.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
< system.cpu2.icache.overall_mshr_hits::cpu2.inst 73 # number of overall MSHR hits
< system.cpu2.icache.overall_mshr_hits::total 73 # number of overall MSHR hits
---
> system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 70 # number of ReadReq MSHR hits
> system.cpu2.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits
> system.cpu2.icache.demand_mshr_hits::cpu2.inst 70 # number of demand (read+write) MSHR hits
> system.cpu2.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits
> system.cpu2.icache.overall_mshr_hits::cpu2.inst 70 # number of overall MSHR hits
> system.cpu2.icache.overall_mshr_hits::total 70 # number of overall MSHR hits
1830,1847c1830,1847
< system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6895000 # number of ReadReq MSHR miss cycles
< system.cpu2.icache.ReadReq_mshr_miss_latency::total 6895000 # number of ReadReq MSHR miss cycles
< system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6895000 # number of demand (read+write) MSHR miss cycles
< system.cpu2.icache.demand_mshr_miss_latency::total 6895000 # number of demand (read+write) MSHR miss cycles
< system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6895000 # number of overall MSHR miss cycles
< system.cpu2.icache.overall_mshr_miss_latency::total 6895000 # number of overall MSHR miss cycles
< system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.019166 # mshr miss rate for ReadReq accesses
< system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.019166 # mshr miss rate for ReadReq accesses
< system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.019166 # mshr miss rate for demand accesses
< system.cpu2.icache.demand_mshr_miss_rate::total 0.019166 # mshr miss rate for demand accesses
< system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.019166 # mshr miss rate for overall accesses
< system.cpu2.icache.overall_mshr_miss_rate::total 0.019166 # mshr miss rate for overall accesses
< system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13790 # average ReadReq mshr miss latency
< system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13790 # average ReadReq mshr miss latency
< system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13790 # average overall mshr miss latency
< system.cpu2.icache.demand_avg_mshr_miss_latency::total 13790 # average overall mshr miss latency
< system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13790 # average overall mshr miss latency
< system.cpu2.icache.overall_avg_mshr_miss_latency::total 13790 # average overall mshr miss latency
---
> system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7049500 # number of ReadReq MSHR miss cycles
> system.cpu2.icache.ReadReq_mshr_miss_latency::total 7049500 # number of ReadReq MSHR miss cycles
> system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7049500 # number of demand (read+write) MSHR miss cycles
> system.cpu2.icache.demand_mshr_miss_latency::total 7049500 # number of demand (read+write) MSHR miss cycles
> system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7049500 # number of overall MSHR miss cycles
> system.cpu2.icache.overall_mshr_miss_latency::total 7049500 # number of overall MSHR miss cycles
> system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021859 # mshr miss rate for ReadReq accesses
> system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021859 # mshr miss rate for ReadReq accesses
> system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021859 # mshr miss rate for demand accesses
> system.cpu2.icache.demand_mshr_miss_rate::total 0.021859 # mshr miss rate for demand accesses
> system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021859 # mshr miss rate for overall accesses
> system.cpu2.icache.overall_mshr_miss_rate::total 0.021859 # mshr miss rate for overall accesses
> system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 14099 # average ReadReq mshr miss latency
> system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 14099 # average ReadReq mshr miss latency
> system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 14099 # average overall mshr miss latency
> system.cpu2.icache.demand_avg_mshr_miss_latency::total 14099 # average overall mshr miss latency
> system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 14099 # average overall mshr miss latency
> system.cpu2.icache.overall_avg_mshr_miss_latency::total 14099 # average overall mshr miss latency
1849,1853c1849,1853
< system.cpu3.branchPred.lookups 52678 # Number of BP lookups
< system.cpu3.branchPred.condPredicted 49211 # Number of conditional branches predicted
< system.cpu3.branchPred.condIncorrect 1284 # Number of conditional branches incorrect
< system.cpu3.branchPred.BTBLookups 45275 # Number of BTB lookups
< system.cpu3.branchPred.BTBHits 44303 # Number of BTB hits
---
> system.cpu3.branchPred.lookups 49230 # Number of BP lookups
> system.cpu3.branchPred.condPredicted 45728 # Number of conditional branches predicted
> system.cpu3.branchPred.condIncorrect 1271 # Number of conditional branches incorrect
> system.cpu3.branchPred.BTBLookups 41796 # Number of BTB lookups
> system.cpu3.branchPred.BTBHits 40803 # Number of BTB hits
1855c1855
< system.cpu3.branchPred.BTBHitPct 97.853120 # BTB Hit Percentage
---
> system.cpu3.branchPred.BTBHitPct 97.624175 # BTB Hit Percentage
1858c1858
< system.cpu3.numCycles 162161 # number of cpu cycles simulated
---
> system.cpu3.numCycles 161890 # number of cpu cycles simulated
1861,1866c1861,1866
< system.cpu3.fetch.icacheStallCycles 30846 # Number of cycles fetch is stalled on an Icache miss
< system.cpu3.fetch.Insts 291154 # Number of instructions fetch has processed
< system.cpu3.fetch.Branches 52678 # Number of branches that fetch encountered
< system.cpu3.fetch.predictedBranches 45209 # Number of branches that fetch has predicted taken
< system.cpu3.fetch.Cycles 126827 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu3.fetch.SquashCycles 2723 # Number of cycles fetch has spent squashing
---
> system.cpu3.fetch.icacheStallCycles 32992 # Number of cycles fetch is stalled on an Icache miss
> system.cpu3.fetch.Insts 268412 # Number of instructions fetch has processed
> system.cpu3.fetch.Branches 49230 # Number of branches that fetch encountered
> system.cpu3.fetch.predictedBranches 41709 # Number of branches that fetch has predicted taken
> system.cpu3.fetch.Cycles 124419 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu3.fetch.SquashCycles 2697 # Number of cycles fetch has spent squashing
1869,1870c1869,1870
< system.cpu3.fetch.PendingTrapStallCycles 1166 # Number of stall cycles due to pending traps
< system.cpu3.fetch.CacheLines 21882 # Number of cache lines fetched
---
> system.cpu3.fetch.PendingTrapStallCycles 1165 # Number of stall cycles due to pending traps
> system.cpu3.fetch.CacheLines 24017 # Number of cache lines fetched
1872,1874c1872,1874
< system.cpu3.fetch.rateDist::samples 160213 # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::mean 1.817293 # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::stdev 2.188011 # Number of instructions fetched each cycle (Total)
---
> system.cpu3.fetch.rateDist::samples 159937 # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::mean 1.678236 # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::stdev 2.146445 # Number of instructions fetched each cycle (Total)
1876,1884c1876,1884
< system.cpu3.fetch.rateDist::0 57700 36.01% 36.01% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::1 51927 32.41% 68.43% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::2 6814 4.25% 72.68% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::3 3535 2.21% 74.89% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::4 932 0.58% 75.47% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::5 33301 20.79% 96.25% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::6 1242 0.78% 97.03% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::7 787 0.49% 97.52% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::8 3975 2.48% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu3.fetch.rateDist::0 63357 39.61% 39.61% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::1 49486 30.94% 70.55% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::2 7847 4.91% 75.46% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::3 3455 2.16% 77.62% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::4 942 0.59% 78.21% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::5 28830 18.03% 96.24% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::6 1207 0.75% 96.99% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::7 797 0.50% 97.49% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::8 4016 2.51% 100.00% # Number of instructions fetched each cycle (Total)
1888,1905c1888,1905
< system.cpu3.fetch.rateDist::total 160213 # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.branchRate 0.324850 # Number of branch fetches per cycle
< system.cpu3.fetch.rate 1.795463 # Number of inst fetches per cycle
< system.cpu3.decode.IdleCycles 17433 # Number of cycles decode is idle
< system.cpu3.decode.BlockedCycles 58368 # Number of cycles decode is blocked
< system.cpu3.decode.RunCycles 79576 # Number of cycles decode is running
< system.cpu3.decode.UnblockCycles 3465 # Number of cycles decode is unblocking
< system.cpu3.decode.SquashCycles 1361 # Number of cycles decode is squashing
< system.cpu3.decode.DecodedInsts 275763 # Number of instructions handled by decode
< system.cpu3.rename.SquashCycles 1361 # Number of cycles rename is squashing
< system.cpu3.rename.IdleCycles 18155 # Number of cycles rename is idle
< system.cpu3.rename.BlockCycles 26788 # Number of cycles rename is blocking
< system.cpu3.rename.serializeStallCycles 14101 # count of cycles rename stalled for serializing inst
< system.cpu3.rename.RunCycles 81078 # Number of cycles rename is running
< system.cpu3.rename.UnblockCycles 18720 # Number of cycles rename is unblocking
< system.cpu3.rename.RenamedInsts 272367 # Number of instructions processed by rename
< system.cpu3.rename.IQFullEvents 16743 # Number of times rename has blocked due to IQ full
< system.cpu3.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full
---
> system.cpu3.fetch.rateDist::total 159937 # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.branchRate 0.304095 # Number of branch fetches per cycle
> system.cpu3.fetch.rate 1.657990 # Number of inst fetches per cycle
> system.cpu3.decode.IdleCycles 17620 # Number of cycles decode is idle
> system.cpu3.decode.BlockedCycles 66098 # Number of cycles decode is blocked
> system.cpu3.decode.RunCycles 70935 # Number of cycles decode is running
> system.cpu3.decode.UnblockCycles 3926 # Number of cycles decode is unblocking
> system.cpu3.decode.SquashCycles 1348 # Number of cycles decode is squashing
> system.cpu3.decode.DecodedInsts 252986 # Number of instructions handled by decode
> system.cpu3.rename.SquashCycles 1348 # Number of cycles rename is squashing
> system.cpu3.rename.IdleCycles 18323 # Number of cycles rename is idle
> system.cpu3.rename.BlockCycles 31370 # Number of cycles rename is blocking
> system.cpu3.rename.serializeStallCycles 13970 # count of cycles rename stalled for serializing inst
> system.cpu3.rename.RunCycles 72885 # Number of cycles rename is running
> system.cpu3.rename.UnblockCycles 22031 # Number of cycles rename is unblocking
> system.cpu3.rename.RenamedInsts 249675 # Number of instructions processed by rename
> system.cpu3.rename.IQFullEvents 20026 # Number of times rename has blocked due to IQ full
> system.cpu3.rename.LQFullEvents 15 # Number of times rename has blocked due to LQ full
1907,1928c1907,1928
< system.cpu3.rename.RenamedOperands 191251 # Number of destination operands rename has renamed
< system.cpu3.rename.RenameLookups 520897 # Number of register rename lookups that rename has made
< system.cpu3.rename.int_rename_lookups 405695 # Number of integer rename lookups
< system.cpu3.rename.CommittedMaps 177247 # Number of HB maps that are committed
< system.cpu3.rename.UndoneMaps 14004 # Number of HB maps that are undone due to squashing
< system.cpu3.rename.serializingInsts 1196 # count of serializing insts renamed
< system.cpu3.rename.tempSerializingInsts 1267 # count of temporary serializing insts renamed
< system.cpu3.rename.skidInsts 23402 # count of insts added to the skid buffer
< system.cpu3.memDep0.insertedLoads 76309 # Number of loads inserted to the mem dependence unit.
< system.cpu3.memDep0.insertedStores 36069 # Number of stores inserted to the mem dependence unit.
< system.cpu3.memDep0.conflictingLoads 36463 # Number of conflicting loads.
< system.cpu3.memDep0.conflictingStores 30962 # Number of conflicting stores.
< system.cpu3.iq.iqInstsAdded 226032 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu3.iq.iqNonSpecInstsAdded 6585 # Number of non-speculative instructions added to the IQ
< system.cpu3.iq.iqInstsIssued 227862 # Number of instructions issued
< system.cpu3.iq.iqSquashedInstsIssued 13 # Number of squashed instructions issued
< system.cpu3.iq.iqSquashedInstsExamined 13164 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu3.iq.iqSquashedOperandsExamined 10986 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu3.iq.iqSquashedNonSpecRemoved 709 # Number of squashed non-spec instructions that were removed
< system.cpu3.iq.issued_per_cycle::samples 160213 # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::mean 1.422244 # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::stdev 1.377526 # Number of insts issued each cycle
---
> system.cpu3.rename.RenamedOperands 174506 # Number of destination operands rename has renamed
> system.cpu3.rename.RenameLookups 471658 # Number of register rename lookups that rename has made
> system.cpu3.rename.int_rename_lookups 368736 # Number of integer rename lookups
> system.cpu3.rename.CommittedMaps 160859 # Number of HB maps that are committed
> system.cpu3.rename.UndoneMaps 13647 # Number of HB maps that are undone due to squashing
> system.cpu3.rename.serializingInsts 1202 # count of serializing insts renamed
> system.cpu3.rename.tempSerializingInsts 1275 # count of temporary serializing insts renamed
> system.cpu3.rename.skidInsts 26657 # count of insts added to the skid buffer
> system.cpu3.memDep0.insertedLoads 68456 # Number of loads inserted to the mem dependence unit.
> system.cpu3.memDep0.insertedStores 31644 # Number of stores inserted to the mem dependence unit.
> system.cpu3.memDep0.conflictingLoads 33001 # Number of conflicting loads.
> system.cpu3.memDep0.conflictingStores 26549 # Number of conflicting stores.
> system.cpu3.iq.iqInstsAdded 205848 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu3.iq.iqNonSpecInstsAdded 7559 # Number of non-speculative instructions added to the IQ
> system.cpu3.iq.iqInstsIssued 208921 # Number of instructions issued
> system.cpu3.iq.iqSquashedInstsIssued 4 # Number of squashed instructions issued
> system.cpu3.iq.iqSquashedInstsExamined 12739 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu3.iq.iqSquashedOperandsExamined 10220 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu3.iq.iqSquashedNonSpecRemoved 712 # Number of squashed non-spec instructions that were removed
> system.cpu3.iq.issued_per_cycle::samples 159937 # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::mean 1.306271 # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::stdev 1.372225 # Number of insts issued each cycle
1930,1938c1930,1938
< system.cpu3.iq.issued_per_cycle::0 61467 38.37% 38.37% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::1 22016 13.74% 52.11% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::2 35438 22.12% 74.23% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::3 35000 21.85% 96.07% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::4 3395 2.12% 98.19% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::5 1603 1.00% 99.19% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::6 883 0.55% 99.74% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::7 211 0.13% 99.88% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::8 200 0.12% 100.00% # Number of insts issued each cycle
---
> system.cpu3.iq.issued_per_cycle::0 67005 41.89% 41.89% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::1 24940 15.59% 57.49% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::2 31075 19.43% 76.92% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::3 30637 19.16% 96.07% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::4 3376 2.11% 98.18% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::5 1620 1.01% 99.20% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::6 871 0.54% 99.74% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::7 214 0.13% 99.88% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::8 199 0.12% 100.00% # Number of insts issued each cycle
1942c1942
< system.cpu3.iq.issued_per_cycle::total 160213 # Number of insts issued each cycle
---
> system.cpu3.iq.issued_per_cycle::total 159937 # Number of insts issued each cycle
1944,1974c1944,1974
< system.cpu3.iq.fu_full::IntAlu 82 24.12% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::IntMult 0 0.00% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::IntDiv 0 0.00% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::FloatAdd 0 0.00% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::FloatCmp 0 0.00% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::FloatCvt 0 0.00% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::FloatMult 0 0.00% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::FloatDiv 0 0.00% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdAdd 0 0.00% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdAlu 0 0.00% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdCmp 0 0.00% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdCvt 0 0.00% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdMisc 0 0.00% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdMult 0 0.00% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdShift 0 0.00% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 24.12% # attempts to use FU when none available
< system.cpu3.iq.fu_full::MemRead 49 14.41% 38.53% # attempts to use FU when none available
< system.cpu3.iq.fu_full::MemWrite 209 61.47% 100.00% # attempts to use FU when none available
---
> system.cpu3.iq.fu_full::IntAlu 82 24.70% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::IntMult 0 0.00% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::IntDiv 0 0.00% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::FloatAdd 0 0.00% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::FloatCmp 0 0.00% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::FloatCvt 0 0.00% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::FloatMult 0 0.00% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::FloatDiv 0 0.00% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdAdd 0 0.00% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdAlu 0 0.00% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdCmp 0 0.00% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdCvt 0 0.00% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdMisc 0 0.00% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdMult 0 0.00% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdShift 0 0.00% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 24.70% # attempts to use FU when none available
> system.cpu3.iq.fu_full::MemRead 41 12.35% 37.05% # attempts to use FU when none available
> system.cpu3.iq.fu_full::MemWrite 209 62.95% 100.00% # attempts to use FU when none available
1978,2008c1978,2008
< system.cpu3.iq.FU_type_0::IntAlu 111773 49.05% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.05% # Type of FU issued
< system.cpu3.iq.FU_type_0::MemRead 80677 35.41% 84.46% # Type of FU issued
< system.cpu3.iq.FU_type_0::MemWrite 35412 15.54% 100.00% # Type of FU issued
---
> system.cpu3.iq.FU_type_0::IntAlu 103999 49.78% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.78% # Type of FU issued
> system.cpu3.iq.FU_type_0::MemRead 73864 35.35% 85.13% # Type of FU issued
> system.cpu3.iq.FU_type_0::MemWrite 31058 14.87% 100.00% # Type of FU issued
2011,2017c2011,2017
< system.cpu3.iq.FU_type_0::total 227862 # Type of FU issued
< system.cpu3.iq.rate 1.405159 # Inst issue rate
< system.cpu3.iq.fu_busy_cnt 340 # FU busy when requested
< system.cpu3.iq.fu_busy_rate 0.001492 # FU busy rate (busy events/executed inst)
< system.cpu3.iq.int_inst_queue_reads 616290 # Number of integer instruction queue reads
< system.cpu3.iq.int_inst_queue_writes 245818 # Number of integer instruction queue writes
< system.cpu3.iq.int_inst_queue_wakeup_accesses 226322 # Number of integer instruction queue wakeup accesses
---
> system.cpu3.iq.FU_type_0::total 208921 # Type of FU issued
> system.cpu3.iq.rate 1.290512 # Inst issue rate
> system.cpu3.iq.fu_busy_cnt 332 # FU busy when requested
> system.cpu3.iq.fu_busy_rate 0.001589 # FU busy rate (busy events/executed inst)
> system.cpu3.iq.int_inst_queue_reads 578115 # Number of integer instruction queue reads
> system.cpu3.iq.int_inst_queue_writes 226182 # Number of integer instruction queue writes
> system.cpu3.iq.int_inst_queue_wakeup_accesses 207437 # Number of integer instruction queue wakeup accesses
2021c2021
< system.cpu3.iq.int_alu_accesses 228202 # Number of integer alu accesses
---
> system.cpu3.iq.int_alu_accesses 209253 # Number of integer alu accesses
2023c2023
< system.cpu3.iew.lsq.thread0.forwLoads 30727 # Number of loads that had data forwarded from stores
---
> system.cpu3.iew.lsq.thread0.forwLoads 26373 # Number of loads that had data forwarded from stores
2025c2025
< system.cpu3.iew.lsq.thread0.squashedLoads 2667 # Number of loads squashed
---
> system.cpu3.iew.lsq.thread0.squashedLoads 2521 # Number of loads squashed
2027,2028c2027,2028
< system.cpu3.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations
< system.cpu3.iew.lsq.thread0.squashedStores 1566 # Number of stores squashed
---
> system.cpu3.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations
> system.cpu3.iew.lsq.thread0.squashedStores 1480 # Number of stores squashed
2034,2040c2034,2040
< system.cpu3.iew.iewSquashCycles 1361 # Number of cycles IEW is squashing
< system.cpu3.iew.iewBlockCycles 7576 # Number of cycles IEW is blocking
< system.cpu3.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking
< system.cpu3.iew.iewDispatchedInsts 269910 # Number of instructions dispatched to IQ
< system.cpu3.iew.iewDispSquashedInsts 166 # Number of squashed instructions skipped by dispatch
< system.cpu3.iew.iewDispLoadInsts 76309 # Number of dispatched load instructions
< system.cpu3.iew.iewDispStoreInsts 36069 # Number of dispatched store instructions
---
> system.cpu3.iew.iewSquashCycles 1348 # Number of cycles IEW is squashing
> system.cpu3.iew.iewBlockCycles 8395 # Number of cycles IEW is blocking
> system.cpu3.iew.iewUnblockCycles 63 # Number of cycles IEW is unblocking
> system.cpu3.iew.iewDispatchedInsts 247262 # Number of instructions dispatched to IQ
> system.cpu3.iew.iewDispSquashedInsts 160 # Number of squashed instructions skipped by dispatch
> system.cpu3.iew.iewDispLoadInsts 68456 # Number of dispatched load instructions
> system.cpu3.iew.iewDispStoreInsts 31644 # Number of dispatched store instructions
2042c2042
< system.cpu3.iew.iewIQFullEvents 41 # Number of times the IQ has become full, causing a stall
---
> system.cpu3.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall
2044,2050c2044,2050
< system.cpu3.iew.memOrderViolationEvents 37 # Number of memory order violations
< system.cpu3.iew.predictedTakenIncorrect 452 # Number of branches that were predicted taken incorrectly
< system.cpu3.iew.predictedNotTakenIncorrect 1067 # Number of branches that were predicted not taken incorrectly
< system.cpu3.iew.branchMispredicts 1519 # Number of branch mispredicts detected at execute
< system.cpu3.iew.iewExecutedInsts 226838 # Number of executed instructions
< system.cpu3.iew.iewExecLoadInsts 75201 # Number of load instructions executed
< system.cpu3.iew.iewExecSquashedInsts 1024 # Number of squashed instructions skipped in execute
---
> system.cpu3.iew.memOrderViolationEvents 36 # Number of memory order violations
> system.cpu3.iew.predictedTakenIncorrect 438 # Number of branches that were predicted taken incorrectly
> system.cpu3.iew.predictedNotTakenIncorrect 1065 # Number of branches that were predicted not taken incorrectly
> system.cpu3.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute
> system.cpu3.iew.iewExecutedInsts 207928 # Number of executed instructions
> system.cpu3.iew.iewExecLoadInsts 67431 # Number of load instructions executed
> system.cpu3.iew.iewExecSquashedInsts 993 # Number of squashed instructions skipped in execute
2052,2068c2052,2068
< system.cpu3.iew.exec_nop 37293 # number of nop insts executed
< system.cpu3.iew.exec_refs 110524 # number of memory reference insts executed
< system.cpu3.iew.exec_branches 46686 # Number of branches executed
< system.cpu3.iew.exec_stores 35323 # Number of stores executed
< system.cpu3.iew.exec_rate 1.398844 # Inst execution rate
< system.cpu3.iew.wb_sent 226605 # cumulative count of insts sent to commit
< system.cpu3.iew.wb_count 226322 # cumulative count of insts written-back
< system.cpu3.iew.wb_producers 128132 # num instructions producing a value
< system.cpu3.iew.wb_consumers 134738 # num instructions consuming a value
< system.cpu3.iew.wb_rate 1.395662 # insts written-back per cycle
< system.cpu3.iew.wb_fanout 0.950972 # average fanout of values written-back
< system.cpu3.commit.commitSquashedInsts 13998 # The number of squashed insts skipped by commit
< system.cpu3.commit.commitNonSpecStalls 5876 # The number of times commit has been forced to stall to communicate backwards
< system.cpu3.commit.branchMispredicts 1284 # The number of times a branch was mispredicted
< system.cpu3.commit.committed_per_cycle::samples 157615 # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::mean 1.623367 # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::stdev 2.050526 # Number of insts commited each cycle
---
> system.cpu3.iew.exec_nop 33855 # number of nop insts executed
> system.cpu3.iew.exec_refs 98404 # number of memory reference insts executed
> system.cpu3.iew.exec_branches 43312 # Number of branches executed
> system.cpu3.iew.exec_stores 30973 # Number of stores executed
> system.cpu3.iew.exec_rate 1.284378 # Inst execution rate
> system.cpu3.iew.wb_sent 207701 # cumulative count of insts sent to commit
> system.cpu3.iew.wb_count 207437 # cumulative count of insts written-back
> system.cpu3.iew.wb_producers 116002 # num instructions producing a value
> system.cpu3.iew.wb_consumers 122598 # num instructions consuming a value
> system.cpu3.iew.wb_rate 1.281345 # insts written-back per cycle
> system.cpu3.iew.wb_fanout 0.946198 # average fanout of values written-back
> system.cpu3.commit.commitSquashedInsts 13505 # The number of squashed insts skipped by commit
> system.cpu3.commit.commitNonSpecStalls 6847 # The number of times commit has been forced to stall to communicate backwards
> system.cpu3.commit.branchMispredicts 1271 # The number of times a branch was mispredicted
> system.cpu3.commit.committed_per_cycle::samples 157409 # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::mean 1.484744 # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::stdev 1.997930 # Number of insts commited each cycle
2070,2078c2070,2078
< system.cpu3.commit.committed_per_cycle::0 67043 42.54% 42.54% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::1 43238 27.43% 69.97% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::2 5262 3.34% 73.31% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::3 6673 4.23% 77.54% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::4 1534 0.97% 78.51% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::5 30788 19.53% 98.05% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::6 827 0.52% 98.57% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::7 952 0.60% 99.18% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::8 1298 0.82% 100.00% # Number of insts commited each cycle
---
> system.cpu3.commit.committed_per_cycle::0 73609 46.76% 46.76% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::1 39844 25.31% 72.08% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::2 5242 3.33% 75.41% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::3 7652 4.86% 80.27% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::4 1542 0.98% 81.25% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::5 26417 16.78% 98.03% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::6 849 0.54% 98.57% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::7 951 0.60% 99.17% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::8 1303 0.83% 100.00% # Number of insts commited each cycle
2082,2084c2082,2084
< system.cpu3.commit.committed_per_cycle::total 157615 # Number of insts commited each cycle
< system.cpu3.commit.committedInsts 255867 # Number of instructions committed
< system.cpu3.commit.committedOps 255867 # Number of ops (including micro ops) committed
---
> system.cpu3.commit.committed_per_cycle::total 157409 # Number of insts commited each cycle
> system.cpu3.commit.committedInsts 233712 # Number of instructions committed
> system.cpu3.commit.committedOps 233712 # Number of ops (including micro ops) committed
2086,2089c2086,2089
< system.cpu3.commit.refs 108145 # Number of memory references committed
< system.cpu3.commit.loads 73642 # Number of loads committed
< system.cpu3.commit.membars 5159 # Number of memory barriers committed
< system.cpu3.commit.branches 45627 # Number of branches committed
---
> system.cpu3.commit.refs 96099 # Number of memory references committed
> system.cpu3.commit.loads 65935 # Number of loads committed
> system.cpu3.commit.membars 6131 # Number of memory barriers committed
> system.cpu3.commit.branches 42256 # Number of branches committed
2091c2091
< system.cpu3.commit.int_insts 175889 # Number of committed integer instructions.
---
> system.cpu3.commit.int_insts 160475 # Number of committed integer instructions.
2093,2124c2093,2124
< system.cpu3.commit.op_class_0::No_OpClass 36414 14.23% 14.23% # Class of committed instruction
< system.cpu3.commit.op_class_0::IntAlu 106149 41.49% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.72% # Class of committed instruction
< system.cpu3.commit.op_class_0::MemRead 78801 30.80% 86.52% # Class of committed instruction
< system.cpu3.commit.op_class_0::MemWrite 34503 13.48% 100.00% # Class of committed instruction
---
> system.cpu3.commit.op_class_0::No_OpClass 33044 14.14% 14.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::IntAlu 98438 42.12% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.26% # Class of committed instruction
> system.cpu3.commit.op_class_0::MemRead 72066 30.84% 87.09% # Class of committed instruction
> system.cpu3.commit.op_class_0::MemWrite 30164 12.91% 100.00% # Class of committed instruction
2127,2132c2127,2132
< system.cpu3.commit.op_class_0::total 255867 # Class of committed instruction
< system.cpu3.commit.bw_lim_events 1298 # number cycles where commit BW limit reached
< system.cpu3.rob.rob_reads 425596 # The number of ROB reads
< system.cpu3.rob.rob_writes 542328 # The number of ROB writes
< system.cpu3.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu3.idleCycles 1948 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu3.commit.op_class_0::total 233712 # Class of committed instruction
> system.cpu3.commit.bw_lim_events 1303 # number cycles where commit BW limit reached
> system.cpu3.rob.rob_reads 402737 # The number of ROB reads
> system.cpu3.rob.rob_writes 496962 # The number of ROB writes
> system.cpu3.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu3.idleCycles 1953 # Total number of cycles that the CPU has spent unscheduled due to idling
2134,2141c2134,2141
< system.cpu3.committedInsts 214294 # Number of Instructions Simulated
< system.cpu3.committedOps 214294 # Number of Ops (including micro ops) Simulated
< system.cpu3.cpi 0.756722 # CPI: Cycles Per Instruction
< system.cpu3.cpi_total 0.756722 # CPI: Total CPI of All Threads
< system.cpu3.ipc 1.321489 # IPC: Instructions Per Cycle
< system.cpu3.ipc_total 1.321489 # IPC: Total IPC of All Threads
< system.cpu3.int_regfile_reads 391365 # number of integer regfile reads
< system.cpu3.int_regfile_writes 183208 # number of integer regfile writes
---
> system.cpu3.committedInsts 194537 # Number of Instructions Simulated
> system.cpu3.committedOps 194537 # Number of Ops (including micro ops) Simulated
> system.cpu3.cpi 0.832181 # CPI: Cycles Per Instruction
> system.cpu3.cpi_total 0.832181 # CPI: Total CPI of All Threads
> system.cpu3.ipc 1.201662 # IPC: Instructions Per Cycle
> system.cpu3.ipc_total 1.201662 # IPC: Total IPC of All Threads
> system.cpu3.int_regfile_reads 355006 # number of integer regfile reads
> system.cpu3.int_regfile_writes 166699 # number of integer regfile writes
2143c2143
< system.cpu3.misc_regfile_reads 112150 # number of misc regfile reads
---
> system.cpu3.misc_regfile_reads 100037 # number of misc regfile reads
2146,2147c2146,2147
< system.cpu3.dcache.tags.tagsinuse 24.277315 # Cycle average of tags in use
< system.cpu3.dcache.tags.total_refs 40522 # Total number of references to valid blocks.
---
> system.cpu3.dcache.tags.tagsinuse 24.251319 # Cycle average of tags in use
> system.cpu3.dcache.tags.total_refs 36167 # Total number of references to valid blocks.
2149c2149
< system.cpu3.dcache.tags.avg_refs 1447.214286 # Average number of references to valid blocks.
---
> system.cpu3.dcache.tags.avg_refs 1291.678571 # Average number of references to valid blocks.
2151,2153c2151,2153
< system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.277315 # Average occupied blocks per requestor
< system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047417 # Average percentage of cache occupancy
< system.cpu3.dcache.tags.occ_percent::total 0.047417 # Average percentage of cache occupancy
---
> system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.251319 # Average occupied blocks per requestor
> system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047366 # Average percentage of cache occupancy
> system.cpu3.dcache.tags.occ_percent::total 0.047366 # Average percentage of cache occupancy
2157,2218c2157,2218
< system.cpu3.dcache.tags.tag_accesses 316074 # Number of tag accesses
< system.cpu3.dcache.tags.data_accesses 316074 # Number of data accesses
< system.cpu3.dcache.ReadReq_hits::cpu3.data 43937 # number of ReadReq hits
< system.cpu3.dcache.ReadReq_hits::total 43937 # number of ReadReq hits
< system.cpu3.dcache.WriteReq_hits::cpu3.data 34273 # number of WriteReq hits
< system.cpu3.dcache.WriteReq_hits::total 34273 # number of WriteReq hits
< system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits
< system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits
< system.cpu3.dcache.demand_hits::cpu3.data 78210 # number of demand (read+write) hits
< system.cpu3.dcache.demand_hits::total 78210 # number of demand (read+write) hits
< system.cpu3.dcache.overall_hits::cpu3.data 78210 # number of overall hits
< system.cpu3.dcache.overall_hits::total 78210 # number of overall hits
< system.cpu3.dcache.ReadReq_misses::cpu3.data 514 # number of ReadReq misses
< system.cpu3.dcache.ReadReq_misses::total 514 # number of ReadReq misses
< system.cpu3.dcache.WriteReq_misses::cpu3.data 159 # number of WriteReq misses
< system.cpu3.dcache.WriteReq_misses::total 159 # number of WriteReq misses
< system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses
< system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses
< system.cpu3.dcache.demand_misses::cpu3.data 673 # number of demand (read+write) misses
< system.cpu3.dcache.demand_misses::total 673 # number of demand (read+write) misses
< system.cpu3.dcache.overall_misses::cpu3.data 673 # number of overall misses
< system.cpu3.dcache.overall_misses::total 673 # number of overall misses
< system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 9349000 # number of ReadReq miss cycles
< system.cpu3.dcache.ReadReq_miss_latency::total 9349000 # number of ReadReq miss cycles
< system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3790500 # number of WriteReq miss cycles
< system.cpu3.dcache.WriteReq_miss_latency::total 3790500 # number of WriteReq miss cycles
< system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 680500 # number of SwapReq miss cycles
< system.cpu3.dcache.SwapReq_miss_latency::total 680500 # number of SwapReq miss cycles
< system.cpu3.dcache.demand_miss_latency::cpu3.data 13139500 # number of demand (read+write) miss cycles
< system.cpu3.dcache.demand_miss_latency::total 13139500 # number of demand (read+write) miss cycles
< system.cpu3.dcache.overall_miss_latency::cpu3.data 13139500 # number of overall miss cycles
< system.cpu3.dcache.overall_miss_latency::total 13139500 # number of overall miss cycles
< system.cpu3.dcache.ReadReq_accesses::cpu3.data 44451 # number of ReadReq accesses(hits+misses)
< system.cpu3.dcache.ReadReq_accesses::total 44451 # number of ReadReq accesses(hits+misses)
< system.cpu3.dcache.WriteReq_accesses::cpu3.data 34432 # number of WriteReq accesses(hits+misses)
< system.cpu3.dcache.WriteReq_accesses::total 34432 # number of WriteReq accesses(hits+misses)
< system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses)
< system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
< system.cpu3.dcache.demand_accesses::cpu3.data 78883 # number of demand (read+write) accesses
< system.cpu3.dcache.demand_accesses::total 78883 # number of demand (read+write) accesses
< system.cpu3.dcache.overall_accesses::cpu3.data 78883 # number of overall (read+write) accesses
< system.cpu3.dcache.overall_accesses::total 78883 # number of overall (read+write) accesses
< system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.011563 # miss rate for ReadReq accesses
< system.cpu3.dcache.ReadReq_miss_rate::total 0.011563 # miss rate for ReadReq accesses
< system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004618 # miss rate for WriteReq accesses
< system.cpu3.dcache.WriteReq_miss_rate::total 0.004618 # miss rate for WriteReq accesses
< system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses
< system.cpu3.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses
< system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008532 # miss rate for demand accesses
< system.cpu3.dcache.demand_miss_rate::total 0.008532 # miss rate for demand accesses
< system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008532 # miss rate for overall accesses
< system.cpu3.dcache.overall_miss_rate::total 0.008532 # miss rate for overall accesses
< system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 18188.715953 # average ReadReq miss latency
< system.cpu3.dcache.ReadReq_avg_miss_latency::total 18188.715953 # average ReadReq miss latency
< system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 23839.622642 # average WriteReq miss latency
< system.cpu3.dcache.WriteReq_avg_miss_latency::total 23839.622642 # average WriteReq miss latency
< system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 11938.596491 # average SwapReq miss latency
< system.cpu3.dcache.SwapReq_avg_miss_latency::total 11938.596491 # average SwapReq miss latency
< system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 19523.774146 # average overall miss latency
< system.cpu3.dcache.demand_avg_miss_latency::total 19523.774146 # average overall miss latency
< system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 19523.774146 # average overall miss latency
< system.cpu3.dcache.overall_avg_miss_latency::total 19523.774146 # average overall miss latency
---
> system.cpu3.dcache.tags.tag_accesses 285043 # Number of tag accesses
> system.cpu3.dcache.tags.data_accesses 285043 # Number of data accesses
> system.cpu3.dcache.ReadReq_hits::cpu3.data 40546 # number of ReadReq hits
> system.cpu3.dcache.ReadReq_hits::total 40546 # number of ReadReq hits
> system.cpu3.dcache.WriteReq_hits::cpu3.data 29945 # number of WriteReq hits
> system.cpu3.dcache.WriteReq_hits::total 29945 # number of WriteReq hits
> system.cpu3.dcache.SwapReq_hits::cpu3.data 17 # number of SwapReq hits
> system.cpu3.dcache.SwapReq_hits::total 17 # number of SwapReq hits
> system.cpu3.dcache.demand_hits::cpu3.data 70491 # number of demand (read+write) hits
> system.cpu3.dcache.demand_hits::total 70491 # number of demand (read+write) hits
> system.cpu3.dcache.overall_hits::cpu3.data 70491 # number of overall hits
> system.cpu3.dcache.overall_hits::total 70491 # number of overall hits
> system.cpu3.dcache.ReadReq_misses::cpu3.data 489 # number of ReadReq misses
> system.cpu3.dcache.ReadReq_misses::total 489 # number of ReadReq misses
> system.cpu3.dcache.WriteReq_misses::cpu3.data 149 # number of WriteReq misses
> system.cpu3.dcache.WriteReq_misses::total 149 # number of WriteReq misses
> system.cpu3.dcache.SwapReq_misses::cpu3.data 53 # number of SwapReq misses
> system.cpu3.dcache.SwapReq_misses::total 53 # number of SwapReq misses
> system.cpu3.dcache.demand_misses::cpu3.data 638 # number of demand (read+write) misses
> system.cpu3.dcache.demand_misses::total 638 # number of demand (read+write) misses
> system.cpu3.dcache.overall_misses::cpu3.data 638 # number of overall misses
> system.cpu3.dcache.overall_misses::total 638 # number of overall misses
> system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 8138500 # number of ReadReq miss cycles
> system.cpu3.dcache.ReadReq_miss_latency::total 8138500 # number of ReadReq miss cycles
> system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3781500 # number of WriteReq miss cycles
> system.cpu3.dcache.WriteReq_miss_latency::total 3781500 # number of WriteReq miss cycles
> system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 606500 # number of SwapReq miss cycles
> system.cpu3.dcache.SwapReq_miss_latency::total 606500 # number of SwapReq miss cycles
> system.cpu3.dcache.demand_miss_latency::cpu3.data 11920000 # number of demand (read+write) miss cycles
> system.cpu3.dcache.demand_miss_latency::total 11920000 # number of demand (read+write) miss cycles
> system.cpu3.dcache.overall_miss_latency::cpu3.data 11920000 # number of overall miss cycles
> system.cpu3.dcache.overall_miss_latency::total 11920000 # number of overall miss cycles
> system.cpu3.dcache.ReadReq_accesses::cpu3.data 41035 # number of ReadReq accesses(hits+misses)
> system.cpu3.dcache.ReadReq_accesses::total 41035 # number of ReadReq accesses(hits+misses)
> system.cpu3.dcache.WriteReq_accesses::cpu3.data 30094 # number of WriteReq accesses(hits+misses)
> system.cpu3.dcache.WriteReq_accesses::total 30094 # number of WriteReq accesses(hits+misses)
> system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses)
> system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses)
> system.cpu3.dcache.demand_accesses::cpu3.data 71129 # number of demand (read+write) accesses
> system.cpu3.dcache.demand_accesses::total 71129 # number of demand (read+write) accesses
> system.cpu3.dcache.overall_accesses::cpu3.data 71129 # number of overall (read+write) accesses
> system.cpu3.dcache.overall_accesses::total 71129 # number of overall (read+write) accesses
> system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.011917 # miss rate for ReadReq accesses
> system.cpu3.dcache.ReadReq_miss_rate::total 0.011917 # miss rate for ReadReq accesses
> system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004951 # miss rate for WriteReq accesses
> system.cpu3.dcache.WriteReq_miss_rate::total 0.004951 # miss rate for WriteReq accesses
> system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.757143 # miss rate for SwapReq accesses
> system.cpu3.dcache.SwapReq_miss_rate::total 0.757143 # miss rate for SwapReq accesses
> system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008970 # miss rate for demand accesses
> system.cpu3.dcache.demand_miss_rate::total 0.008970 # miss rate for demand accesses
> system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008970 # miss rate for overall accesses
> system.cpu3.dcache.overall_miss_rate::total 0.008970 # miss rate for overall accesses
> system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16643.149284 # average ReadReq miss latency
> system.cpu3.dcache.ReadReq_avg_miss_latency::total 16643.149284 # average ReadReq miss latency
> system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25379.194631 # average WriteReq miss latency
> system.cpu3.dcache.WriteReq_avg_miss_latency::total 25379.194631 # average WriteReq miss latency
> system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 11443.396226 # average SwapReq miss latency
> system.cpu3.dcache.SwapReq_avg_miss_latency::total 11443.396226 # average SwapReq miss latency
> system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18683.385580 # average overall miss latency
> system.cpu3.dcache.demand_avg_miss_latency::total 18683.385580 # average overall miss latency
> system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18683.385580 # average overall miss latency
> system.cpu3.dcache.overall_avg_miss_latency::total 18683.385580 # average overall miss latency
2227,2274c2227,2274
< system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 347 # number of ReadReq MSHR hits
< system.cpu3.dcache.ReadReq_mshr_hits::total 347 # number of ReadReq MSHR hits
< system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 52 # number of WriteReq MSHR hits
< system.cpu3.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits
< system.cpu3.dcache.demand_mshr_hits::cpu3.data 399 # number of demand (read+write) MSHR hits
< system.cpu3.dcache.demand_mshr_hits::total 399 # number of demand (read+write) MSHR hits
< system.cpu3.dcache.overall_mshr_hits::cpu3.data 399 # number of overall MSHR hits
< system.cpu3.dcache.overall_mshr_hits::total 399 # number of overall MSHR hits
< system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 167 # number of ReadReq MSHR misses
< system.cpu3.dcache.ReadReq_mshr_misses::total 167 # number of ReadReq MSHR misses
< system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses
< system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses
< system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses
< system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses
< system.cpu3.dcache.demand_mshr_misses::cpu3.data 274 # number of demand (read+write) MSHR misses
< system.cpu3.dcache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses
< system.cpu3.dcache.overall_mshr_misses::cpu3.data 274 # number of overall MSHR misses
< system.cpu3.dcache.overall_mshr_misses::total 274 # number of overall MSHR misses
< system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1719000 # number of ReadReq MSHR miss cycles
< system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1719000 # number of ReadReq MSHR miss cycles
< system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 2129500 # number of WriteReq MSHR miss cycles
< system.cpu3.dcache.WriteReq_mshr_miss_latency::total 2129500 # number of WriteReq MSHR miss cycles
< system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 623500 # number of SwapReq MSHR miss cycles
< system.cpu3.dcache.SwapReq_mshr_miss_latency::total 623500 # number of SwapReq MSHR miss cycles
< system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3848500 # number of demand (read+write) MSHR miss cycles
< system.cpu3.dcache.demand_mshr_miss_latency::total 3848500 # number of demand (read+write) MSHR miss cycles
< system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3848500 # number of overall MSHR miss cycles
< system.cpu3.dcache.overall_mshr_miss_latency::total 3848500 # number of overall MSHR miss cycles
< system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003757 # mshr miss rate for ReadReq accesses
< system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003757 # mshr miss rate for ReadReq accesses
< system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003108 # mshr miss rate for WriteReq accesses
< system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003108 # mshr miss rate for WriteReq accesses
< system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses
< system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses
< system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003473 # mshr miss rate for demand accesses
< system.cpu3.dcache.demand_mshr_miss_rate::total 0.003473 # mshr miss rate for demand accesses
< system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003473 # mshr miss rate for overall accesses
< system.cpu3.dcache.overall_mshr_miss_rate::total 0.003473 # mshr miss rate for overall accesses
< system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 10293.413174 # average ReadReq mshr miss latency
< system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 10293.413174 # average ReadReq mshr miss latency
< system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 19901.869159 # average WriteReq mshr miss latency
< system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 19901.869159 # average WriteReq mshr miss latency
< system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 10938.596491 # average SwapReq mshr miss latency
< system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 10938.596491 # average SwapReq mshr miss latency
< system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14045.620438 # average overall mshr miss latency
< system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14045.620438 # average overall mshr miss latency
< system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14045.620438 # average overall mshr miss latency
< system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14045.620438 # average overall mshr miss latency
---
> system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 328 # number of ReadReq MSHR hits
> system.cpu3.dcache.ReadReq_mshr_hits::total 328 # number of ReadReq MSHR hits
> system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 46 # number of WriteReq MSHR hits
> system.cpu3.dcache.WriteReq_mshr_hits::total 46 # number of WriteReq MSHR hits
> system.cpu3.dcache.demand_mshr_hits::cpu3.data 374 # number of demand (read+write) MSHR hits
> system.cpu3.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits
> system.cpu3.dcache.overall_mshr_hits::cpu3.data 374 # number of overall MSHR hits
> system.cpu3.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits
> system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 161 # number of ReadReq MSHR misses
> system.cpu3.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses
> system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 103 # number of WriteReq MSHR misses
> system.cpu3.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses
> system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 53 # number of SwapReq MSHR misses
> system.cpu3.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses
> system.cpu3.dcache.demand_mshr_misses::cpu3.data 264 # number of demand (read+write) MSHR misses
> system.cpu3.dcache.demand_mshr_misses::total 264 # number of demand (read+write) MSHR misses
> system.cpu3.dcache.overall_mshr_misses::cpu3.data 264 # number of overall MSHR misses
> system.cpu3.dcache.overall_mshr_misses::total 264 # number of overall MSHR misses
> system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1609000 # number of ReadReq MSHR miss cycles
> system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1609000 # number of ReadReq MSHR miss cycles
> system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 2139500 # number of WriteReq MSHR miss cycles
> system.cpu3.dcache.WriteReq_mshr_miss_latency::total 2139500 # number of WriteReq MSHR miss cycles
> system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 553500 # number of SwapReq MSHR miss cycles
> system.cpu3.dcache.SwapReq_mshr_miss_latency::total 553500 # number of SwapReq MSHR miss cycles
> system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3748500 # number of demand (read+write) MSHR miss cycles
> system.cpu3.dcache.demand_mshr_miss_latency::total 3748500 # number of demand (read+write) MSHR miss cycles
> system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3748500 # number of overall MSHR miss cycles
> system.cpu3.dcache.overall_mshr_miss_latency::total 3748500 # number of overall MSHR miss cycles
> system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003923 # mshr miss rate for ReadReq accesses
> system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003923 # mshr miss rate for ReadReq accesses
> system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003423 # mshr miss rate for WriteReq accesses
> system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003423 # mshr miss rate for WriteReq accesses
> system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.757143 # mshr miss rate for SwapReq accesses
> system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.757143 # mshr miss rate for SwapReq accesses
> system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003712 # mshr miss rate for demand accesses
> system.cpu3.dcache.demand_mshr_miss_rate::total 0.003712 # mshr miss rate for demand accesses
> system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003712 # mshr miss rate for overall accesses
> system.cpu3.dcache.overall_mshr_miss_rate::total 0.003712 # mshr miss rate for overall accesses
> system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9993.788820 # average ReadReq mshr miss latency
> system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9993.788820 # average ReadReq mshr miss latency
> system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 20771.844660 # average WriteReq mshr miss latency
> system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 20771.844660 # average WriteReq mshr miss latency
> system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 10443.396226 # average SwapReq mshr miss latency
> system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 10443.396226 # average SwapReq mshr miss latency
> system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14198.863636 # average overall mshr miss latency
> system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14198.863636 # average overall mshr miss latency
> system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14198.863636 # average overall mshr miss latency
> system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14198.863636 # average overall mshr miss latency
2277,2278c2277,2278
< system.cpu3.icache.tags.tagsinuse 81.046367 # Cycle average of tags in use
< system.cpu3.icache.tags.total_refs 21310 # Total number of references to valid blocks.
---
> system.cpu3.icache.tags.tagsinuse 80.879647 # Cycle average of tags in use
> system.cpu3.icache.tags.total_refs 23443 # Total number of references to valid blocks.
2280c2280
< system.cpu3.icache.tags.avg_refs 42.791165 # Average number of references to valid blocks.
---
> system.cpu3.icache.tags.avg_refs 47.074297 # Average number of references to valid blocks.
2282,2284c2282,2284
< system.cpu3.icache.tags.occ_blocks::cpu3.inst 81.046367 # Average occupied blocks per requestor
< system.cpu3.icache.tags.occ_percent::cpu3.inst 0.158294 # Average percentage of cache occupancy
< system.cpu3.icache.tags.occ_percent::total 0.158294 # Average percentage of cache occupancy
---
> system.cpu3.icache.tags.occ_blocks::cpu3.inst 80.879647 # Average occupied blocks per requestor
> system.cpu3.icache.tags.occ_percent::cpu3.inst 0.157968 # Average percentage of cache occupancy
> system.cpu3.icache.tags.occ_percent::total 0.157968 # Average percentage of cache occupancy
2289,2326c2289,2326
< system.cpu3.icache.tags.tag_accesses 22380 # Number of tag accesses
< system.cpu3.icache.tags.data_accesses 22380 # Number of data accesses
< system.cpu3.icache.ReadReq_hits::cpu3.inst 21310 # number of ReadReq hits
< system.cpu3.icache.ReadReq_hits::total 21310 # number of ReadReq hits
< system.cpu3.icache.demand_hits::cpu3.inst 21310 # number of demand (read+write) hits
< system.cpu3.icache.demand_hits::total 21310 # number of demand (read+write) hits
< system.cpu3.icache.overall_hits::cpu3.inst 21310 # number of overall hits
< system.cpu3.icache.overall_hits::total 21310 # number of overall hits
< system.cpu3.icache.ReadReq_misses::cpu3.inst 572 # number of ReadReq misses
< system.cpu3.icache.ReadReq_misses::total 572 # number of ReadReq misses
< system.cpu3.icache.demand_misses::cpu3.inst 572 # number of demand (read+write) misses
< system.cpu3.icache.demand_misses::total 572 # number of demand (read+write) misses
< system.cpu3.icache.overall_misses::cpu3.inst 572 # number of overall misses
< system.cpu3.icache.overall_misses::total 572 # number of overall misses
< system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 8104500 # number of ReadReq miss cycles
< system.cpu3.icache.ReadReq_miss_latency::total 8104500 # number of ReadReq miss cycles
< system.cpu3.icache.demand_miss_latency::cpu3.inst 8104500 # number of demand (read+write) miss cycles
< system.cpu3.icache.demand_miss_latency::total 8104500 # number of demand (read+write) miss cycles
< system.cpu3.icache.overall_miss_latency::cpu3.inst 8104500 # number of overall miss cycles
< system.cpu3.icache.overall_miss_latency::total 8104500 # number of overall miss cycles
< system.cpu3.icache.ReadReq_accesses::cpu3.inst 21882 # number of ReadReq accesses(hits+misses)
< system.cpu3.icache.ReadReq_accesses::total 21882 # number of ReadReq accesses(hits+misses)
< system.cpu3.icache.demand_accesses::cpu3.inst 21882 # number of demand (read+write) accesses
< system.cpu3.icache.demand_accesses::total 21882 # number of demand (read+write) accesses
< system.cpu3.icache.overall_accesses::cpu3.inst 21882 # number of overall (read+write) accesses
< system.cpu3.icache.overall_accesses::total 21882 # number of overall (read+write) accesses
< system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.026140 # miss rate for ReadReq accesses
< system.cpu3.icache.ReadReq_miss_rate::total 0.026140 # miss rate for ReadReq accesses
< system.cpu3.icache.demand_miss_rate::cpu3.inst 0.026140 # miss rate for demand accesses
< system.cpu3.icache.demand_miss_rate::total 0.026140 # miss rate for demand accesses
< system.cpu3.icache.overall_miss_rate::cpu3.inst 0.026140 # miss rate for overall accesses
< system.cpu3.icache.overall_miss_rate::total 0.026140 # miss rate for overall accesses
< system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14168.706294 # average ReadReq miss latency
< system.cpu3.icache.ReadReq_avg_miss_latency::total 14168.706294 # average ReadReq miss latency
< system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14168.706294 # average overall miss latency
< system.cpu3.icache.demand_avg_miss_latency::total 14168.706294 # average overall miss latency
< system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14168.706294 # average overall miss latency
< system.cpu3.icache.overall_avg_miss_latency::total 14168.706294 # average overall miss latency
---
> system.cpu3.icache.tags.tag_accesses 24515 # Number of tag accesses
> system.cpu3.icache.tags.data_accesses 24515 # Number of data accesses
> system.cpu3.icache.ReadReq_hits::cpu3.inst 23443 # number of ReadReq hits
> system.cpu3.icache.ReadReq_hits::total 23443 # number of ReadReq hits
> system.cpu3.icache.demand_hits::cpu3.inst 23443 # number of demand (read+write) hits
> system.cpu3.icache.demand_hits::total 23443 # number of demand (read+write) hits
> system.cpu3.icache.overall_hits::cpu3.inst 23443 # number of overall hits
> system.cpu3.icache.overall_hits::total 23443 # number of overall hits
> system.cpu3.icache.ReadReq_misses::cpu3.inst 574 # number of ReadReq misses
> system.cpu3.icache.ReadReq_misses::total 574 # number of ReadReq misses
> system.cpu3.icache.demand_misses::cpu3.inst 574 # number of demand (read+write) misses
> system.cpu3.icache.demand_misses::total 574 # number of demand (read+write) misses
> system.cpu3.icache.overall_misses::cpu3.inst 574 # number of overall misses
> system.cpu3.icache.overall_misses::total 574 # number of overall misses
> system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7717500 # number of ReadReq miss cycles
> system.cpu3.icache.ReadReq_miss_latency::total 7717500 # number of ReadReq miss cycles
> system.cpu3.icache.demand_miss_latency::cpu3.inst 7717500 # number of demand (read+write) miss cycles
> system.cpu3.icache.demand_miss_latency::total 7717500 # number of demand (read+write) miss cycles
> system.cpu3.icache.overall_miss_latency::cpu3.inst 7717500 # number of overall miss cycles
> system.cpu3.icache.overall_miss_latency::total 7717500 # number of overall miss cycles
> system.cpu3.icache.ReadReq_accesses::cpu3.inst 24017 # number of ReadReq accesses(hits+misses)
> system.cpu3.icache.ReadReq_accesses::total 24017 # number of ReadReq accesses(hits+misses)
> system.cpu3.icache.demand_accesses::cpu3.inst 24017 # number of demand (read+write) accesses
> system.cpu3.icache.demand_accesses::total 24017 # number of demand (read+write) accesses
> system.cpu3.icache.overall_accesses::cpu3.inst 24017 # number of overall (read+write) accesses
> system.cpu3.icache.overall_accesses::total 24017 # number of overall (read+write) accesses
> system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023900 # miss rate for ReadReq accesses
> system.cpu3.icache.ReadReq_miss_rate::total 0.023900 # miss rate for ReadReq accesses
> system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023900 # miss rate for demand accesses
> system.cpu3.icache.demand_miss_rate::total 0.023900 # miss rate for demand accesses
> system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023900 # miss rate for overall accesses
> system.cpu3.icache.overall_miss_rate::total 0.023900 # miss rate for overall accesses
> system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13445.121951 # average ReadReq miss latency
> system.cpu3.icache.ReadReq_avg_miss_latency::total 13445.121951 # average ReadReq miss latency
> system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13445.121951 # average overall miss latency
> system.cpu3.icache.demand_avg_miss_latency::total 13445.121951 # average overall miss latency
> system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13445.121951 # average overall miss latency
> system.cpu3.icache.overall_avg_miss_latency::total 13445.121951 # average overall miss latency
2337,2342c2337,2342
< system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 74 # number of ReadReq MSHR hits
< system.cpu3.icache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits
< system.cpu3.icache.demand_mshr_hits::cpu3.inst 74 # number of demand (read+write) MSHR hits
< system.cpu3.icache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits
< system.cpu3.icache.overall_mshr_hits::cpu3.inst 74 # number of overall MSHR hits
< system.cpu3.icache.overall_mshr_hits::total 74 # number of overall MSHR hits
---
> system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 76 # number of ReadReq MSHR hits
> system.cpu3.icache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits
> system.cpu3.icache.demand_mshr_hits::cpu3.inst 76 # number of demand (read+write) MSHR hits
> system.cpu3.icache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits
> system.cpu3.icache.overall_mshr_hits::cpu3.inst 76 # number of overall MSHR hits
> system.cpu3.icache.overall_mshr_hits::total 76 # number of overall MSHR hits
2349,2366c2349,2366
< system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6912000 # number of ReadReq MSHR miss cycles
< system.cpu3.icache.ReadReq_mshr_miss_latency::total 6912000 # number of ReadReq MSHR miss cycles
< system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6912000 # number of demand (read+write) MSHR miss cycles
< system.cpu3.icache.demand_mshr_miss_latency::total 6912000 # number of demand (read+write) MSHR miss cycles
< system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6912000 # number of overall MSHR miss cycles
< system.cpu3.icache.overall_mshr_miss_latency::total 6912000 # number of overall MSHR miss cycles
< system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.022758 # mshr miss rate for ReadReq accesses
< system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.022758 # mshr miss rate for ReadReq accesses
< system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.022758 # mshr miss rate for demand accesses
< system.cpu3.icache.demand_mshr_miss_rate::total 0.022758 # mshr miss rate for demand accesses
< system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.022758 # mshr miss rate for overall accesses
< system.cpu3.icache.overall_mshr_miss_rate::total 0.022758 # mshr miss rate for overall accesses
< system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13879.518072 # average ReadReq mshr miss latency
< system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13879.518072 # average ReadReq mshr miss latency
< system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13879.518072 # average overall mshr miss latency
< system.cpu3.icache.demand_avg_mshr_miss_latency::total 13879.518072 # average overall mshr miss latency
< system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13879.518072 # average overall mshr miss latency
< system.cpu3.icache.overall_avg_mshr_miss_latency::total 13879.518072 # average overall mshr miss latency
---
> system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6640500 # number of ReadReq MSHR miss cycles
> system.cpu3.icache.ReadReq_mshr_miss_latency::total 6640500 # number of ReadReq MSHR miss cycles
> system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6640500 # number of demand (read+write) MSHR miss cycles
> system.cpu3.icache.demand_mshr_miss_latency::total 6640500 # number of demand (read+write) MSHR miss cycles
> system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6640500 # number of overall MSHR miss cycles
> system.cpu3.icache.overall_mshr_miss_latency::total 6640500 # number of overall MSHR miss cycles
> system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020735 # mshr miss rate for ReadReq accesses
> system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020735 # mshr miss rate for ReadReq accesses
> system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020735 # mshr miss rate for demand accesses
> system.cpu3.icache.demand_mshr_miss_rate::total 0.020735 # mshr miss rate for demand accesses
> system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020735 # mshr miss rate for overall accesses
> system.cpu3.icache.overall_mshr_miss_rate::total 0.020735 # mshr miss rate for overall accesses
> system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13334.337349 # average ReadReq mshr miss latency
> system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13334.337349 # average ReadReq mshr miss latency
> system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13334.337349 # average overall mshr miss latency
> system.cpu3.icache.demand_avg_mshr_miss_latency::total 13334.337349 # average overall mshr miss latency
> system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13334.337349 # average overall mshr miss latency
> system.cpu3.icache.overall_avg_mshr_miss_latency::total 13334.337349 # average overall mshr miss latency
2369c2369
< system.l2c.tags.tagsinuse 419.218954 # Cycle average of tags in use
---
> system.l2c.tags.tagsinuse 419.138543 # Cycle average of tags in use
2374,2382c2374,2382
< system.l2c.tags.occ_blocks::writebacks 0.788461 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 288.048945 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 58.083381 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 60.484959 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 5.324168 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu2.inst 2.350458 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu2.data 0.677584 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu3.inst 2.742702 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu3.data 0.718294 # Average occupied blocks per requestor
---
> system.l2c.tags.occ_blocks::writebacks 0.788194 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 288.006073 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 58.075910 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 61.760427 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 5.322052 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu2.inst 2.559109 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu2.data 0.677187 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu3.inst 1.231634 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu3.data 0.717957 # Average occupied blocks per requestor
2386c2386
< system.l2c.tags.occ_percent::cpu1.inst 0.000923 # Average percentage of cache occupancy
---
> system.l2c.tags.occ_percent::cpu1.inst 0.000942 # Average percentage of cache occupancy
2388c2388
< system.l2c.tags.occ_percent::cpu2.inst 0.000036 # Average percentage of cache occupancy
---
> system.l2c.tags.occ_percent::cpu2.inst 0.000039 # Average percentage of cache occupancy
2390c2390
< system.l2c.tags.occ_percent::cpu3.inst 0.000042 # Average percentage of cache occupancy
---
> system.l2c.tags.occ_percent::cpu3.inst 0.000019 # Average percentage of cache occupancy
2392c2392
< system.l2c.tags.occ_percent::total 0.006397 # Average percentage of cache occupancy
---
> system.l2c.tags.occ_percent::total 0.006396 # Average percentage of cache occupancy
2395,2396c2395,2396
< system.l2c.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 141 # Occupied blocks per task id
---
> system.l2c.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 138 # Occupied blocks per task id
2407,2409c2407,2409
< system.l2c.ReadCleanReq_hits::cpu1.inst 412 # number of ReadCleanReq hits
< system.l2c.ReadCleanReq_hits::cpu2.inst 491 # number of ReadCleanReq hits
< system.l2c.ReadCleanReq_hits::cpu3.inst 489 # number of ReadCleanReq hits
---
> system.l2c.ReadCleanReq_hits::cpu1.inst 410 # number of ReadCleanReq hits
> system.l2c.ReadCleanReq_hits::cpu2.inst 489 # number of ReadCleanReq hits
> system.l2c.ReadCleanReq_hits::cpu3.inst 493 # number of ReadCleanReq hits
2418c2418
< system.l2c.demand_hits::cpu1.inst 412 # number of demand (read+write) hits
---
> system.l2c.demand_hits::cpu1.inst 410 # number of demand (read+write) hits
2420c2420
< system.l2c.demand_hits::cpu2.inst 491 # number of demand (read+write) hits
---
> system.l2c.demand_hits::cpu2.inst 489 # number of demand (read+write) hits
2422c2422
< system.l2c.demand_hits::cpu3.inst 489 # number of demand (read+write) hits
---
> system.l2c.demand_hits::cpu3.inst 493 # number of demand (read+write) hits
2427c2427
< system.l2c.overall_hits::cpu1.inst 412 # number of overall hits
---
> system.l2c.overall_hits::cpu1.inst 410 # number of overall hits
2429c2429
< system.l2c.overall_hits::cpu2.inst 491 # number of overall hits
---
> system.l2c.overall_hits::cpu2.inst 489 # number of overall hits
2431c2431
< system.l2c.overall_hits::cpu3.inst 489 # number of overall hits
---
> system.l2c.overall_hits::cpu3.inst 493 # number of overall hits
2435c2435
< system.l2c.UpgradeReq_misses::cpu1.data 20 # number of UpgradeReq misses
---
> system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses
2437c2437
< system.l2c.UpgradeReq_misses::cpu3.data 21 # number of UpgradeReq misses
---
> system.l2c.UpgradeReq_misses::cpu3.data 22 # number of UpgradeReq misses
2445,2447c2445,2447
< system.l2c.ReadCleanReq_misses::cpu1.inst 84 # number of ReadCleanReq misses
< system.l2c.ReadCleanReq_misses::cpu2.inst 9 # number of ReadCleanReq misses
< system.l2c.ReadCleanReq_misses::cpu3.inst 9 # number of ReadCleanReq misses
---
> system.l2c.ReadCleanReq_misses::cpu1.inst 86 # number of ReadCleanReq misses
> system.l2c.ReadCleanReq_misses::cpu2.inst 11 # number of ReadCleanReq misses
> system.l2c.ReadCleanReq_misses::cpu3.inst 5 # number of ReadCleanReq misses
2456c2456
< system.l2c.demand_misses::cpu1.inst 84 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu1.inst 86 # number of demand (read+write) misses
2458c2458
< system.l2c.demand_misses::cpu2.inst 9 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu2.inst 11 # number of demand (read+write) misses
2460c2460
< system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu3.inst 5 # number of demand (read+write) misses
2465c2465
< system.l2c.overall_misses::cpu1.inst 84 # number of overall misses
---
> system.l2c.overall_misses::cpu1.inst 86 # number of overall misses
2467c2467
< system.l2c.overall_misses::cpu2.inst 9 # number of overall misses
---
> system.l2c.overall_misses::cpu2.inst 11 # number of overall misses
2469c2469
< system.l2c.overall_misses::cpu3.inst 9 # number of overall misses
---
> system.l2c.overall_misses::cpu3.inst 5 # number of overall misses
2472c2472
< system.l2c.ReadExReq_miss_latency::cpu0.data 7611000 # number of ReadExReq miss cycles
---
> system.l2c.ReadExReq_miss_latency::cpu0.data 7622500 # number of ReadExReq miss cycles
2474,2481c2474,2481
< system.l2c.ReadExReq_miss_latency::cpu2.data 1210500 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu3.data 1399000 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 11279500 # number of ReadExReq miss cycles
< system.l2c.ReadCleanReq_miss_latency::cpu0.inst 27676500 # number of ReadCleanReq miss cycles
< system.l2c.ReadCleanReq_miss_latency::cpu1.inst 6293000 # number of ReadCleanReq miss cycles
< system.l2c.ReadCleanReq_miss_latency::cpu2.inst 614000 # number of ReadCleanReq miss cycles
< system.l2c.ReadCleanReq_miss_latency::cpu3.inst 660000 # number of ReadCleanReq miss cycles
< system.l2c.ReadCleanReq_miss_latency::total 35243500 # number of ReadCleanReq miss cycles
---
> system.l2c.ReadExReq_miss_latency::cpu2.data 1210000 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu3.data 1404500 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 11296000 # number of ReadExReq miss cycles
> system.l2c.ReadCleanReq_miss_latency::cpu0.inst 27679500 # number of ReadCleanReq miss cycles
> system.l2c.ReadCleanReq_miss_latency::cpu1.inst 6438500 # number of ReadCleanReq miss cycles
> system.l2c.ReadCleanReq_miss_latency::cpu2.inst 788500 # number of ReadCleanReq miss cycles
> system.l2c.ReadCleanReq_miss_latency::cpu3.inst 341500 # number of ReadCleanReq miss cycles
> system.l2c.ReadCleanReq_miss_latency::total 35248000 # number of ReadCleanReq miss cycles
2487,2489c2487,2489
< system.l2c.demand_miss_latency::cpu0.inst 27676500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 13592500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 6293000 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::cpu0.inst 27679500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 13604000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 6438500 # number of demand (read+write) miss cycles
2491,2498c2491,2498
< system.l2c.demand_miss_latency::cpu2.inst 614000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu2.data 1293000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu3.inst 660000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu3.data 1495500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 53223500 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 27676500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 13592500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 6293000 # number of overall miss cycles
---
> system.l2c.demand_miss_latency::cpu2.inst 788500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu2.data 1292500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu3.inst 341500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu3.data 1501000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 53244500 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 27679500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 13604000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 6438500 # number of overall miss cycles
2500,2504c2500,2504
< system.l2c.overall_miss_latency::cpu2.inst 614000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu2.data 1293000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu3.inst 660000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu3.data 1495500 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 53223500 # number of overall miss cycles
---
> system.l2c.overall_miss_latency::cpu2.inst 788500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu2.data 1292500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu3.inst 341500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu3.data 1501000 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 53244500 # number of overall miss cycles
2510c2510
< system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses)
---
> system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses)
2512c2512
< system.l2c.UpgradeReq_accesses::cpu3.data 21 # number of UpgradeReq accesses(hits+misses)
---
> system.l2c.UpgradeReq_accesses::cpu3.data 22 # number of UpgradeReq accesses(hits+misses)
2558,2560c2558,2560
< system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.169355 # miss rate for ReadCleanReq accesses
< system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.018000 # miss rate for ReadCleanReq accesses
< system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.018072 # miss rate for ReadCleanReq accesses
---
> system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.173387 # miss rate for ReadCleanReq accesses
> system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.022000 # miss rate for ReadCleanReq accesses
> system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.010040 # miss rate for ReadCleanReq accesses
2569c2569
< system.l2c.demand_miss_rate::cpu1.inst 0.169355 # miss rate for demand accesses
---
> system.l2c.demand_miss_rate::cpu1.inst 0.173387 # miss rate for demand accesses
2571c2571
< system.l2c.demand_miss_rate::cpu2.inst 0.018000 # miss rate for demand accesses
---
> system.l2c.demand_miss_rate::cpu2.inst 0.022000 # miss rate for demand accesses
2573c2573
< system.l2c.demand_miss_rate::cpu3.inst 0.018072 # miss rate for demand accesses
---
> system.l2c.demand_miss_rate::cpu3.inst 0.010040 # miss rate for demand accesses
2578c2578
< system.l2c.overall_miss_rate::cpu1.inst 0.169355 # miss rate for overall accesses
---
> system.l2c.overall_miss_rate::cpu1.inst 0.173387 # miss rate for overall accesses
2580c2580
< system.l2c.overall_miss_rate::cpu2.inst 0.018000 # miss rate for overall accesses
---
> system.l2c.overall_miss_rate::cpu2.inst 0.022000 # miss rate for overall accesses
2582c2582
< system.l2c.overall_miss_rate::cpu3.inst 0.018072 # miss rate for overall accesses
---
> system.l2c.overall_miss_rate::cpu3.inst 0.010040 # miss rate for overall accesses
2585c2585
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 80968.085106 # average ReadExReq miss latency
---
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81090.425532 # average ReadExReq miss latency
2587,2594c2587,2594
< system.l2c.ReadExReq_avg_miss_latency::cpu2.data 100875 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu3.data 116583.333333 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 86103.053435 # average ReadExReq miss latency
< system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 76454.419890 # average ReadCleanReq miss latency
< system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 74916.666667 # average ReadCleanReq miss latency
< system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 68222.222222 # average ReadCleanReq miss latency
< system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 73333.333333 # average ReadCleanReq miss latency
< system.l2c.ReadCleanReq_avg_miss_latency::total 75955.818966 # average ReadCleanReq miss latency
---
> system.l2c.ReadExReq_avg_miss_latency::cpu2.data 100833.333333 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu3.data 117041.666667 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 86229.007634 # average ReadExReq miss latency
> system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 76462.707182 # average ReadCleanReq miss latency
> system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 74866.279070 # average ReadCleanReq miss latency
> system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 71681.818182 # average ReadCleanReq miss latency
> system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 68300 # average ReadCleanReq miss latency
> system.l2c.ReadCleanReq_avg_miss_latency::total 75965.517241 # average ReadCleanReq miss latency
2600,2602c2600,2602
< system.l2c.demand_avg_miss_latency::cpu0.inst 76454.419890 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 80428.994083 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 74916.666667 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu0.inst 76462.707182 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 80497.041420 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 74866.279070 # average overall miss latency
2604,2611c2604,2611
< system.l2c.demand_avg_miss_latency::cpu2.inst 68222.222222 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu2.data 99461.538462 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu3.inst 73333.333333 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu3.data 115038.461538 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 78385.125184 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 76454.419890 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 80428.994083 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 74916.666667 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu2.inst 71681.818182 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu2.data 99423.076923 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu3.inst 68300 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu3.data 115461.538462 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 78416.053019 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 76462.707182 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 80497.041420 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 74866.279070 # average overall miss latency
2613,2617c2613,2617
< system.l2c.overall_avg_miss_latency::cpu2.inst 68222.222222 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu2.data 99461.538462 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu3.inst 73333.333333 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu3.data 115038.461538 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 78385.125184 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::cpu2.inst 71681.818182 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu2.data 99423.076923 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu3.inst 68300 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu3.data 115461.538462 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 78416.053019 # average overall miss latency
2628,2629c2628,2629
< system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 6 # number of ReadCleanReq MSHR hits
< system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 2 # number of ReadCleanReq MSHR hits
---
> system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 5 # number of ReadCleanReq MSHR hits
> system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 3 # number of ReadCleanReq MSHR hits
2633,2634c2633,2634
< system.l2c.demand_mshr_hits::cpu2.inst 6 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu3.inst 2 # number of demand (read+write) MSHR hits
---
> system.l2c.demand_mshr_hits::cpu2.inst 5 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu3.inst 3 # number of demand (read+write) MSHR hits
2638,2639c2638,2639
< system.l2c.overall_mshr_hits::cpu2.inst 6 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu3.inst 2 # number of overall MSHR hits
---
> system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu3.inst 3 # number of overall MSHR hits
2642c2642
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 20 # number of UpgradeReq MSHR misses
---
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 19 # number of UpgradeReq MSHR misses
2644c2644
< system.l2c.UpgradeReq_mshr_misses::cpu3.data 21 # number of UpgradeReq MSHR misses
---
> system.l2c.UpgradeReq_mshr_misses::cpu3.data 22 # number of UpgradeReq MSHR misses
2652,2654c2652,2654
< system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 80 # number of ReadCleanReq MSHR misses
< system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 3 # number of ReadCleanReq MSHR misses
< system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 7 # number of ReadCleanReq MSHR misses
---
> system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 82 # number of ReadCleanReq MSHR misses
> system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 6 # number of ReadCleanReq MSHR misses
> system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 2 # number of ReadCleanReq MSHR misses
2663c2663
< system.l2c.demand_mshr_misses::cpu1.inst 80 # number of demand (read+write) MSHR misses
---
> system.l2c.demand_mshr_misses::cpu1.inst 82 # number of demand (read+write) MSHR misses
2665c2665
< system.l2c.demand_mshr_misses::cpu2.inst 3 # number of demand (read+write) MSHR misses
---
> system.l2c.demand_mshr_misses::cpu2.inst 6 # number of demand (read+write) MSHR misses
2667c2667
< system.l2c.demand_mshr_misses::cpu3.inst 7 # number of demand (read+write) MSHR misses
---
> system.l2c.demand_mshr_misses::cpu3.inst 2 # number of demand (read+write) MSHR misses
2672c2672
< system.l2c.overall_mshr_misses::cpu1.inst 80 # number of overall MSHR misses
---
> system.l2c.overall_mshr_misses::cpu1.inst 82 # number of overall MSHR misses
2674c2674
< system.l2c.overall_mshr_misses::cpu2.inst 3 # number of overall MSHR misses
---
> system.l2c.overall_mshr_misses::cpu2.inst 6 # number of overall MSHR misses
2676c2676
< system.l2c.overall_mshr_misses::cpu3.inst 7 # number of overall MSHR misses
---
> system.l2c.overall_mshr_misses::cpu3.inst 2 # number of overall MSHR misses
2679,2684c2679,2684
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 587000 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 437000 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 459996 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 457500 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 1941496 # number of UpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6671000 # number of ReadExReq MSHR miss cycles
---
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 512500 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 359500 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 401500 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 416000 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 1689500 # number of UpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6682500 # number of ReadExReq MSHR miss cycles
2686,2688c2686,2688
< system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1090500 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 1279000 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 9969500 # number of ReadExReq MSHR miss cycles
---
> system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1090000 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 1284500 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 9986000 # number of ReadExReq MSHR miss cycles
2690,2693c2690,2693
< system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 5285500 # number of ReadCleanReq MSHR miss cycles
< system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 219000 # number of ReadCleanReq MSHR miss cycles
< system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 495500 # number of ReadCleanReq MSHR miss cycles
< system.l2c.ReadCleanReq_mshr_miss_latency::total 29889000 # number of ReadCleanReq MSHR miss cycles
---
> system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 5419500 # number of ReadCleanReq MSHR miss cycles
> system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 436500 # number of ReadCleanReq MSHR miss cycles
> system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 145500 # number of ReadCleanReq MSHR miss cycles
> system.l2c.ReadCleanReq_mshr_miss_latency::total 29890500 # number of ReadCleanReq MSHR miss cycles
2700,2701c2700,2701
< system.l2c.demand_mshr_miss_latency::cpu0.data 11902500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 5285500 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu0.data 11914000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 5419500 # number of demand (read+write) MSHR miss cycles
2703,2707c2703,2707
< system.l2c.demand_mshr_miss_latency::cpu2.inst 219000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu2.data 1163000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu3.inst 495500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu3.data 1365500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 45719000 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu2.inst 436500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu2.data 1162500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu3.inst 145500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu3.data 1371000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 45737000 # number of demand (read+write) MSHR miss cycles
2709,2710c2709,2710
< system.l2c.overall_mshr_miss_latency::cpu0.data 11902500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 5285500 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::cpu0.data 11914000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 5419500 # number of overall MSHR miss cycles
2712,2716c2712,2716
< system.l2c.overall_mshr_miss_latency::cpu2.inst 219000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu2.data 1163000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu3.inst 495500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu3.data 1365500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 45719000 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::cpu2.inst 436500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu2.data 1162500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu3.inst 145500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu3.data 1371000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 45737000 # number of overall MSHR miss cycles
2728,2730c2728,2730
< system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.161290 # mshr miss rate for ReadCleanReq accesses
< system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for ReadCleanReq accesses
< system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.014056 # mshr miss rate for ReadCleanReq accesses
---
> system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for ReadCleanReq accesses
> system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.012000 # mshr miss rate for ReadCleanReq accesses
> system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for ReadCleanReq accesses
2739c2739
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161290 # mshr miss rate for demand accesses
---
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for demand accesses
2741c2741
< system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for demand accesses
---
> system.l2c.demand_mshr_miss_rate::cpu2.inst 0.012000 # mshr miss rate for demand accesses
2743c2743
< system.l2c.demand_mshr_miss_rate::cpu3.inst 0.014056 # mshr miss rate for demand accesses
---
> system.l2c.demand_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for demand accesses
2748c2748
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161290 # mshr miss rate for overall accesses
---
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for overall accesses
2750c2750
< system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for overall accesses
---
> system.l2c.overall_mshr_miss_rate::cpu2.inst 0.012000 # mshr miss rate for overall accesses
2752c2752
< system.l2c.overall_mshr_miss_rate::cpu3.inst 0.014056 # mshr miss rate for overall accesses
---
> system.l2c.overall_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for overall accesses
2755,2760c2755,2760
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21740.740741 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21850 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 21904.571429 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 21785.714286 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21814.561798 # average UpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70968.085106 # average ReadExReq mshr miss latency
---
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18981.481481 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18921.052632 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 19119.047619 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 18909.090909 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18983.146067 # average UpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 71090.425532 # average ReadExReq mshr miss latency
2762,2764c2762,2764
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 90875 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 106583.333333 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 76103.053435 # average ReadExReq mshr miss latency
---
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 90833.333333 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 107041.666667 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 76229.007634 # average ReadExReq mshr miss latency
2766,2769c2766,2769
< system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66068.750000 # average ReadCleanReq mshr miss latency
< system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73000 # average ReadCleanReq mshr miss latency
< system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 70785.714286 # average ReadCleanReq mshr miss latency
< system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 66272.727273 # average ReadCleanReq mshr miss latency
---
> system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66091.463415 # average ReadCleanReq mshr miss latency
> system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72750 # average ReadCleanReq mshr miss latency
> system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 72750 # average ReadCleanReq mshr miss latency
> system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 66276.053215 # average ReadCleanReq mshr miss latency
2776,2777c2776,2777
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 70428.994083 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66068.750000 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 70497.041420 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66091.463415 # average overall mshr miss latency
2779,2783c2779,2783
< system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73000 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu2.data 89461.538462 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 70785.714286 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu3.data 105038.461538 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 68647.147147 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72750 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu2.data 89423.076923 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 72750 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu3.data 105461.538462 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 68674.174174 # average overall mshr miss latency
2785,2786c2785,2786
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 70428.994083 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66068.750000 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 70497.041420 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66091.463415 # average overall mshr miss latency
2788,2792c2788,2792
< system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73000 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu2.data 89461.538462 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 70785.714286 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu3.data 105038.461538 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 68647.147147 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72750 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu2.data 89423.076923 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 72750 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu3.data 105461.538462 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 68674.174174 # average overall mshr miss latency
2795,2797c2795,2796
< system.membus.trans_dist::UpgradeReq 290 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 89 # Transaction distribution
< system.membus.trans_dist::ReadExReq 162 # Transaction distribution
---
> system.membus.trans_dist::UpgradeReq 291 # Transaction distribution
> system.membus.trans_dist::ReadExReq 159 # Transaction distribution
2800,2801c2799,2800
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1741 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 1741 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1650 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1650 # Packet count per connected master and slave (bytes)
2804,2805c2803,2804
< system.membus.snoops 232 # Total snoops (count)
< system.membus.snoop_fanout::samples 987 # Request fanout histogram
---
> system.membus.snoops 230 # Total snoops (count)
> system.membus.snoop_fanout::samples 985 # Request fanout histogram
2809c2808
< system.membus.snoop_fanout::0 987 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 985 100.00% 100.00% # Request fanout histogram
2814,2815c2813,2814
< system.membus.snoop_fanout::total 987 # Request fanout histogram
< system.membus.reqLayer0.occupancy 936504 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 985 # Request fanout histogram
> system.membus.reqLayer0.occupancy 928501 # Layer occupancy (ticks)
2817,2821c2816,2820
< system.membus.respLayer1.occupancy 3712661 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 3.4 # Layer utilization (%)
< system.toL2Bus.snoop_filter.tot_requests 4933 # Total number of requests made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_requests 1339 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_requests 2364 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
---
> system.membus.respLayer1.occupancy 3534750 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 3.3 # Layer utilization (%)
> system.toL2Bus.snoop_filter.tot_requests 4931 # Total number of requests made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_requests 1335 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_requests 2366 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2825c2824
< system.toL2Bus.trans_dist::ReadResp 2778 # Transaction distribution
---
> system.toL2Bus.trans_dist::ReadResp 2779 # Transaction distribution
2827c2826
< system.toL2Bus.trans_dist::WritebackClean 676 # Transaction distribution
---
> system.toL2Bus.trans_dist::WritebackClean 1468 # Transaction distribution
2829,2832c2828,2831
< system.toL2Bus.trans_dist::UpgradeReq 293 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 293 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 391 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 391 # Transaction distribution
---
> system.toL2Bus.trans_dist::UpgradeReq 294 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 294 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 387 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 387 # Transaction distribution
2834,2844c2833,2843
< system.toL2Bus.trans_dist::ReadSharedReq 677 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1448 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 592 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1140 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 374 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1151 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 360 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1140 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 376 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 6581 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 53760 # Cumulative packet size per connected master and slave (bytes)
---
> system.toL2Bus.trans_dist::ReadSharedReq 678 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1530 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 593 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1375 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1386 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 379 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1380 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 363 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 7371 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 59008 # Cumulative packet size per connected master and slave (bytes)
2846c2845
< system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41216 # Cumulative packet size per connected master and slave (bytes)
---
> system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 56256 # Cumulative packet size per connected master and slave (bytes)
2848c2847
< system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 41664 # Cumulative packet size per connected master and slave (bytes)
---
> system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 56704 # Cumulative packet size per connected master and slave (bytes)
2850c2849
< system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 41088 # Cumulative packet size per connected master and slave (bytes)
---
> system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes)
2852,2856c2851,2855
< system.toL2Bus.pkt_size::total 193600 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 1022 # Total snoops (count)
< system.toL2Bus.snoop_fanout::samples 3463 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 1.289633 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 1.182691 # Request fanout histogram
---
> system.toL2Bus.pkt_size::total 244288 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 1020 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 3461 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 1.293268 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 1.185819 # Request fanout histogram
2858,2861c2857,2860
< system.toL2Bus.snoop_fanout::0 1230 35.52% 35.52% # Request fanout histogram
< system.toL2Bus.snoop_fanout::1 835 24.11% 59.63% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 563 16.26% 75.89% # Request fanout histogram
< system.toL2Bus.snoop_fanout::3 835 24.11% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::0 1230 35.54% 35.54% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 830 23.98% 59.52% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 557 16.09% 75.61% # Request fanout histogram
> system.toL2Bus.snoop_fanout::3 844 24.39% 100.00% # Request fanout histogram
2870,2871c2869,2870
< system.toL2Bus.snoop_fanout::total 3463 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 3953462 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::total 3461 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 3950967 # Layer occupancy (ticks)
2877c2876
< system.toL2Bus.respLayer2.occupancy 746495 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer2.occupancy 746494 # Layer occupancy (ticks)
2879c2878
< system.toL2Bus.respLayer3.occupancy 439455 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer3.occupancy 429965 # Layer occupancy (ticks)
2881c2880
< system.toL2Bus.respLayer4.occupancy 752991 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer4.occupancy 752493 # Layer occupancy (ticks)
2883c2882
< system.toL2Bus.respLayer5.occupancy 419474 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer5.occupancy 440466 # Layer occupancy (ticks)
2885c2884
< system.toL2Bus.respLayer6.occupancy 747998 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer6.occupancy 748497 # Layer occupancy (ticks)
2887c2886
< system.toL2Bus.respLayer7.occupancy 434475 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer7.occupancy 422962 # Layer occupancy (ticks)