Cross Reference: /gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

Deleted Added

sdiff udiff text old ( 11103:38f6188421e0 ) new ( 11138:a611a23c8cc2 )

full compact

3,5c3,5
< sim_seconds 0.000107 # Number of seconds simulated
< sim_ticks 107049000 # Number of ticks simulated
< final_tick 107049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000108 # Number of seconds simulated
> sim_ticks 107711000 # Number of ticks simulated
> final_tick 107711000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 93620 # Simulator instruction rate (inst/s)
< host_op_rate 93620 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 10161795 # Simulator tick rate (ticks/s)
< host_mem_usage 304708 # Number of bytes of host memory used
< host_seconds 10.53 # Real time elapsed on the host
< sim_insts 986230 # Number of instructions simulated
< sim_ops 986230 # Number of ops (including micro ops) simulated
---
> host_inst_rate 152784 # Simulator instruction rate (inst/s)
> host_op_rate 152784 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 16568657 # Simulator tick rate (ticks/s)
> host_mem_usage 311444 # Number of bytes of host memory used
> host_seconds 6.50 # Real time elapsed on the host
> sim_insts 993230 # Number of instructions simulated
> sim_ops 993230 # Number of ops (including micro ops) simulated
18c18
< system.physmem.bytes_read::cpu1.inst 5248 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu1.inst 5312 # Number of bytes read from this memory
20c20
< system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu2.inst 320 # Number of bytes read from this memory
22c22
< system.physmem.bytes_read::cpu3.inst 320 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory
26,28c26,28
< system.physmem.bytes_inst_read::cpu1.inst 5248 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu3.inst 320 # Number of instructions bytes read from this memory
---
> system.physmem.bytes_inst_read::cpu1.inst 5312 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu2.inst 320 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory
32c32
< system.physmem.num_reads::cpu1.inst 82 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu1.inst 83 # Number of read requests responded to by this memory
34c34
< system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu2.inst 5 # Number of read requests responded to by this memory
36c36
< system.physmem.num_reads::cpu3.inst 5 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory
39,61c39,61
< system.physmem.bw_read::cpu0.inst 215228540 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 101037842 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 49024279 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 11957141 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu2.inst 1793571 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu2.data 7772142 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu3.inst 2989285 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu3.data 7772142 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 397574942 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 215228540 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 49024279 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu2.inst 1793571 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu3.inst 2989285 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 269035675 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 215228540 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 101037842 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 49024279 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 11957141 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu2.inst 1793571 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu2.data 7772142 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu3.inst 2989285 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu3.data 7772142 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 397574942 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu0.inst 213905729 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 100416856 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 49317154 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 11883652 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu2.inst 2970913 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu2.data 7724374 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu3.inst 1188365 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu3.data 7724374 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 395131416 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 213905729 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 49317154 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu2.inst 2970913 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu3.inst 1188365 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 267382162 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 213905729 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 100416856 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 49317154 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 11883652 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu2.inst 2970913 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu2.data 7724374 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu3.inst 1188365 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu3.data 7724374 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 395131416 # Total bandwidth to/from this memory (bytes/s)
73c73
< system.physmem.neitherReadNorWriteReqs 89 # Number of requests that are neither read nor write
---
> system.physmem.neitherReadNorWriteReqs 87 # Number of requests that are neither read nor write
108c108
< system.physmem.totGap 107021000 # Total gap between requests
---
> system.physmem.totGap 107683000 # Total gap between requests
123,125c123,125
< system.physmem.rdQLenPdf::0 399 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 198 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 396 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 199 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see
219,234c219,234
< system.physmem.bytesPerActivate::samples 144 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 276.444444 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 188.969078 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 251.786617 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 43 29.86% 29.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 36 25.00% 54.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 28 19.44% 74.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 12 8.33% 82.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 7 4.86% 87.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 8 5.56% 93.06% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 2 1.39% 94.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 3 2.08% 96.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 5 3.47% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 144 # Bytes accessed per row activation
< system.physmem.totQLat 6009250 # Total ticks spent queuing
< system.physmem.totMemAccLat 18496750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 145 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 274.537931 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 187.244268 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 251.506931 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 44 30.34% 30.34% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 37 25.52% 55.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 28 19.31% 75.17% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 11 7.59% 82.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 7 4.83% 87.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 8 5.52% 93.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 2 1.38% 94.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 3 2.07% 96.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 5 3.45% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 145 # Bytes accessed per row activation
> system.physmem.totQLat 6590000 # Total ticks spent queuing
> system.physmem.totMemAccLat 19077500 # Total ticks spent from burst creation until serviced by the DRAM
236c236
< system.physmem.avgQLat 9022.90 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 9894.89 # Average queueing delay per DRAM burst
238,239c238,239
< system.physmem.avgMemAccLat 27772.90 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 398.17 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 28644.89 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 395.73 # Average DRAM read bandwidth in MiByte/s
241c241
< system.physmem.avgRdBWSys 398.17 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 395.73 # Average system read bandwidth in MiByte/s
244,245c244,245
< system.physmem.busUtil 3.11 # Data bus utilization in percentage
< system.physmem.busUtilRead 3.11 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 3.09 # Data bus utilization in percentage
> system.physmem.busUtilRead 3.09 # Data bus utilization in percentage for reads
247c247
< system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.29 # Average read queue length when enqueuing
249c249
< system.physmem.readRowHits 511 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 510 # Number of row buffer hits during reads
251c251
< system.physmem.readRowHitRate 76.73 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 76.58 # Row buffer hit rate for reads
253,256c253,256
< system.physmem.avgGap 160692.19 # Average gap between requests
< system.physmem.pageHitRate 76.73 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 703080 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 383625 # Energy for precharge commands per rank (pJ)
---
> system.physmem.avgGap 161686.19 # Average gap between requests
> system.physmem.pageHitRate 76.58 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 710640 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 387750 # Energy for precharge commands per rank (pJ)
260,264c260,264
< system.physmem_0.actBackEnergy 37638810 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 27872250 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 75978045 # Total energy per rank (pJ)
< system.physmem_0.averagePower 748.690472 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 47858250 # Time in different power states
---
> system.physmem_0.actBackEnergy 38163780 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 27411750 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 76054200 # Total energy per rank (pJ)
> system.physmem_0.averagePower 749.440907 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 47737250 # Time in different power states
267c267
< system.physmem_0.memoryStateTime::ACT 51979250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 52758750 # Time in different power states
274,278c274,278
< system.physmem_1.actBackEnergy 32994450 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 31946250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 74129175 # Total energy per rank (pJ)
< system.physmem_1.averagePower 730.471639 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 55670750 # Time in different power states
---
> system.physmem_1.actBackEnergy 32134320 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 32700750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 74023545 # Total energy per rank (pJ)
> system.physmem_1.averagePower 729.430757 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 57587750 # Time in different power states
281c281
< system.physmem_1.memoryStateTime::ACT 45162250 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 43903750 # Time in different power states
283,284c283,284
< system.cpu0.branchPred.lookups 81022 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 78376 # Number of conditional branches predicted
---
> system.cpu0.branchPred.lookups 81565 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 78921 # Number of conditional branches predicted
286,287c286,287
< system.cpu0.branchPred.BTBLookups 78355 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 75640 # Number of BTB hits
---
> system.cpu0.branchPred.BTBLookups 78897 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 76181 # Number of BTB hits
289c289
< system.cpu0.branchPred.BTBHitPct 96.535001 # BTB Hit Percentage
---
> system.cpu0.branchPred.BTBHitPct 96.557537 # BTB Hit Percentage
294c294
< system.cpu0.numCycles 214099 # number of cpu cycles simulated
---
> system.cpu0.numCycles 215423 # number of cpu cycles simulated
297,301c297,301
< system.cpu0.fetch.icacheStallCycles 19687 # Number of cycles fetch is stalled on an Icache miss
< system.cpu0.fetch.Insts 478911 # Number of instructions fetch has processed
< system.cpu0.fetch.Branches 81022 # Number of branches that fetch encountered
< system.cpu0.fetch.predictedBranches 76285 # Number of branches that fetch has predicted taken
< system.cpu0.fetch.Cycles 164512 # Number of cycles fetch has run and was not squashing or blocked
---
> system.cpu0.fetch.icacheStallCycles 19725 # Number of cycles fetch is stalled on an Icache miss
> system.cpu0.fetch.Insts 482162 # Number of instructions fetch has processed
> system.cpu0.fetch.Branches 81565 # Number of branches that fetch encountered
> system.cpu0.fetch.predictedBranches 76826 # Number of branches that fetch has predicted taken
> system.cpu0.fetch.Cycles 165719 # Number of cycles fetch has run and was not squashing or blocked
305c305
< system.cpu0.fetch.PendingTrapStallCycles 1992 # Number of stall cycles due to pending traps
---
> system.cpu0.fetch.PendingTrapStallCycles 1994 # Number of stall cycles due to pending traps
307c307
< system.cpu0.fetch.IcacheSquashes 617 # Number of outstanding Icache misses that were squashed
---
> system.cpu0.fetch.IcacheSquashes 620 # Number of outstanding Icache misses that were squashed
309,311c309,311
< system.cpu0.fetch.rateDist::samples 187540 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::mean 2.553647 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::stdev 2.214546 # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.rateDist::samples 188787 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::mean 2.554000 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::stdev 2.213947 # Number of instructions fetched each cycle (Total)
313,321c313,321
< system.cpu0.fetch.rateDist::0 30407 16.21% 16.21% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::1 77695 41.43% 57.64% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::2 798 0.43% 58.07% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::3 1205 0.64% 58.71% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::4 612 0.33% 59.04% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::5 73095 38.98% 98.01% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::6 670 0.36% 98.37% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::7 402 0.21% 98.58% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::8 2656 1.42% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.rateDist::0 30573 16.19% 16.19% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::1 78235 41.44% 57.64% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::2 796 0.42% 58.06% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::3 1203 0.64% 58.69% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::4 613 0.32% 59.02% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::5 73639 39.01% 98.03% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::6 671 0.36% 98.38% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::7 403 0.21% 98.59% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::8 2654 1.41% 100.00% # Number of instructions fetched each cycle (Total)
325,331c325,331
< system.cpu0.fetch.rateDist::total 187540 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.branchRate 0.378432 # Number of branch fetches per cycle
< system.cpu0.fetch.rate 2.236867 # Number of inst fetches per cycle
< system.cpu0.decode.IdleCycles 15435 # Number of cycles decode is idle
< system.cpu0.decode.BlockedCycles 18383 # Number of cycles decode is blocked
< system.cpu0.decode.RunCycles 151822 # Number of cycles decode is running
< system.cpu0.decode.UnblockCycles 650 # Number of cycles decode is unblocking
---
> system.cpu0.fetch.rateDist::total 188787 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.branchRate 0.378627 # Number of branch fetches per cycle
> system.cpu0.fetch.rate 2.238210 # Number of inst fetches per cycle
> system.cpu0.decode.IdleCycles 15472 # Number of cycles decode is idle
> system.cpu0.decode.BlockedCycles 18515 # Number of cycles decode is blocked
> system.cpu0.decode.RunCycles 152899 # Number of cycles decode is running
> system.cpu0.decode.UnblockCycles 651 # Number of cycles decode is unblocking
333c333
< system.cpu0.decode.DecodedInsts 468409 # Number of instructions handled by decode
---
> system.cpu0.decode.DecodedInsts 471677 # Number of instructions handled by decode
335,356c335,356
< system.cpu0.rename.IdleCycles 16041 # Number of cycles rename is idle
< system.cpu0.rename.BlockCycles 2079 # Number of cycles rename is blocking
< system.cpu0.rename.serializeStallCycles 14982 # count of cycles rename stalled for serializing inst
< system.cpu0.rename.RunCycles 151818 # Number of cycles rename is running
< system.cpu0.rename.UnblockCycles 1370 # Number of cycles rename is unblocking
< system.cpu0.rename.RenamedInsts 465227 # Number of instructions processed by rename
< system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full
< system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full
< system.cpu0.rename.SQFullEvents 867 # Number of times rename has blocked due to SQ full
< system.cpu0.rename.RenamedOperands 318145 # Number of destination operands rename has renamed
< system.cpu0.rename.RenameLookups 927822 # Number of register rename lookups that rename has made
< system.cpu0.rename.int_rename_lookups 700792 # Number of integer rename lookups
< system.cpu0.rename.CommittedMaps 305063 # Number of HB maps that are committed
< system.cpu0.rename.UndoneMaps 13082 # Number of HB maps that are undone due to squashing
< system.cpu0.rename.serializingInsts 821 # count of serializing insts renamed
< system.cpu0.rename.tempSerializingInsts 831 # count of temporary serializing insts renamed
< system.cpu0.rename.skidInsts 4377 # count of insts added to the skid buffer
< system.cpu0.memDep0.insertedLoads 148776 # Number of loads inserted to the mem dependence unit.
< system.cpu0.memDep0.insertedStores 75241 # Number of stores inserted to the mem dependence unit.
< system.cpu0.memDep0.conflictingLoads 72733 # Number of conflicting loads.
< system.cpu0.memDep0.conflictingStores 72329 # Number of conflicting stores.
< system.cpu0.iq.iqInstsAdded 389183 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu0.rename.IdleCycles 16075 # Number of cycles rename is idle
> system.cpu0.rename.BlockCycles 2062 # Number of cycles rename is blocking
> system.cpu0.rename.serializeStallCycles 15118 # count of cycles rename stalled for serializing inst
> system.cpu0.rename.RunCycles 152899 # Number of cycles rename is running
> system.cpu0.rename.UnblockCycles 1383 # Number of cycles rename is unblocking
> system.cpu0.rename.RenamedInsts 468509 # Number of instructions processed by rename
> system.cpu0.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full
> system.cpu0.rename.LQFullEvents 10 # Number of times rename has blocked due to LQ full
> system.cpu0.rename.SQFullEvents 883 # Number of times rename has blocked due to SQ full
> system.cpu0.rename.RenamedOperands 320339 # Number of destination operands rename has renamed
> system.cpu0.rename.RenameLookups 934389 # Number of register rename lookups that rename has made
> system.cpu0.rename.int_rename_lookups 705719 # Number of integer rename lookups
> system.cpu0.rename.CommittedMaps 307267 # Number of HB maps that are committed
> system.cpu0.rename.UndoneMaps 13072 # Number of HB maps that are undone due to squashing
> system.cpu0.rename.serializingInsts 822 # count of serializing insts renamed
> system.cpu0.rename.tempSerializingInsts 832 # count of temporary serializing insts renamed
> system.cpu0.rename.skidInsts 4372 # count of insts added to the skid buffer
> system.cpu0.memDep0.insertedLoads 149868 # Number of loads inserted to the mem dependence unit.
> system.cpu0.memDep0.insertedStores 75788 # Number of stores inserted to the mem dependence unit.
> system.cpu0.memDep0.conflictingLoads 73280 # Number of conflicting loads.
> system.cpu0.memDep0.conflictingStores 72874 # Number of conflicting stores.
> system.cpu0.iq.iqInstsAdded 391921 # Number of instructions added to the IQ (excludes non-spec)
358c358
< system.cpu0.iq.iqInstsIssued 385745 # Number of instructions issued
---
> system.cpu0.iq.iqInstsIssued 388505 # Number of instructions issued
360,361c360,361
< system.cpu0.iq.iqSquashedInstsExamined 12312 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu0.iq.iqSquashedOperandsExamined 11729 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu0.iq.iqSquashedInstsExamined 12295 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu0.iq.iqSquashedOperandsExamined 11684 # Number of squashed operands that are examined and possibly removed from graph
363,365c363,365
< system.cpu0.iq.issued_per_cycle::samples 187540 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::mean 2.056868 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::stdev 1.126403 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::samples 188787 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::mean 2.057901 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::stdev 1.125475 # Number of insts issued each cycle
367,373c367,373
< system.cpu0.iq.issued_per_cycle::0 33477 17.85% 17.85% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::1 4232 2.26% 20.11% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::2 73531 39.21% 59.32% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::3 73185 39.02% 98.34% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::4 1601 0.85% 99.19% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::5 889 0.47% 99.67% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::6 403 0.21% 99.88% # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::0 33627 17.81% 17.81% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::1 4227 2.24% 20.05% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::2 74093 39.25% 59.30% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::3 73707 39.04% 98.34% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::4 1618 0.86% 99.20% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::5 890 0.47% 99.67% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::6 402 0.21% 99.88% # Number of insts issued each cycle
375c375
< system.cpu0.iq.issued_per_cycle::8 75 0.04% 100.00% # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::8 76 0.04% 100.00% # Number of insts issued each cycle
379c379
< system.cpu0.iq.issued_per_cycle::total 187540 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::total 188787 # Number of insts issued each cycle
381,410c381,410
< system.cpu0.iq.fu_full::IntAlu 61 21.11% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntMult 0 0.00% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.11% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemRead 125 43.25% 64.36% # attempts to use FU when none available
---
> system.cpu0.iq.fu_full::IntAlu 62 21.45% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntMult 0 0.00% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemRead 124 42.91% 64.36% # attempts to use FU when none available
415,445c415,445
< system.cpu0.iq.FU_type_0::IntAlu 163127 42.29% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemRead 148129 38.40% 80.69% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemWrite 74489 19.31% 100.00% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::IntAlu 164238 42.27% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemRead 149226 38.41% 80.68% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemWrite 75041 19.32% 100.00% # Type of FU issued
448,449c448,449
< system.cpu0.iq.FU_type_0::total 385745 # Type of FU issued
< system.cpu0.iq.rate 1.801713 # Inst issue rate
---
> system.cpu0.iq.FU_type_0::total 388505 # Type of FU issued
> system.cpu0.iq.rate 1.803452 # Inst issue rate
451,454c451,454
< system.cpu0.iq.fu_busy_rate 0.000749 # FU busy rate (busy events/executed inst)
< system.cpu0.iq.int_inst_queue_reads 959350 # Number of integer instruction queue reads
< system.cpu0.iq.int_inst_queue_writes 402446 # Number of integer instruction queue writes
< system.cpu0.iq.int_inst_queue_wakeup_accesses 383893 # Number of integer instruction queue wakeup accesses
---
> system.cpu0.iq.fu_busy_rate 0.000744 # FU busy rate (busy events/executed inst)
> system.cpu0.iq.int_inst_queue_reads 966117 # Number of integer instruction queue reads
> system.cpu0.iq.int_inst_queue_writes 405167 # Number of integer instruction queue writes
> system.cpu0.iq.int_inst_queue_wakeup_accesses 386653 # Number of integer instruction queue wakeup accesses
458c458
< system.cpu0.iq.int_alu_accesses 386034 # Number of integer alu accesses
---
> system.cpu0.iq.int_alu_accesses 388794 # Number of integer alu accesses
460c460
< system.cpu0.iew.lsq.thread0.forwLoads 71845 # Number of loads that had data forwarded from stores
---
> system.cpu0.iew.lsq.thread0.forwLoads 72393 # Number of loads that had data forwarded from stores
462c462
< system.cpu0.iew.lsq.thread0.squashedLoads 2655 # Number of loads squashed
---
> system.cpu0.iew.lsq.thread0.squashedLoads 2645 # Number of loads squashed
465c465
< system.cpu0.iew.lsq.thread0.squashedStores 1674 # Number of stores squashed
---
> system.cpu0.iew.lsq.thread0.squashedStores 1670 # Number of stores squashed
472,474c472,474
< system.cpu0.iew.iewBlockCycles 2043 # Number of cycles IEW is blocking
< system.cpu0.iew.iewUnblockCycles 38 # Number of cycles IEW is unblocking
< system.cpu0.iew.iewDispatchedInsts 463105 # Number of instructions dispatched to IQ
---
> system.cpu0.iew.iewBlockCycles 2029 # Number of cycles IEW is blocking
> system.cpu0.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking
> system.cpu0.iew.iewDispatchedInsts 466388 # Number of instructions dispatched to IQ
476,477c476,477
< system.cpu0.iew.iewDispLoadInsts 148776 # Number of dispatched load instructions
< system.cpu0.iew.iewDispStoreInsts 75241 # Number of dispatched store instructions
---
> system.cpu0.iew.iewDispLoadInsts 149868 # Number of dispatched load instructions
> system.cpu0.iew.iewDispStoreInsts 75788 # Number of dispatched store instructions
479c479
< system.cpu0.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall
---
> system.cpu0.iew.iewIQFullEvents 44 # Number of times the IQ has become full, causing a stall
483,486c483,486
< system.cpu0.iew.predictedNotTakenIncorrect 990 # Number of branches that were predicted not taken incorrectly
< system.cpu0.iew.branchMispredicts 1308 # Number of branch mispredicts detected at execute
< system.cpu0.iew.iewExecutedInsts 384734 # Number of executed instructions
< system.cpu0.iew.iewExecLoadInsts 147791 # Number of load instructions executed
---
> system.cpu0.iew.predictedNotTakenIncorrect 991 # Number of branches that were predicted not taken incorrectly
> system.cpu0.iew.branchMispredicts 1309 # Number of branch mispredicts detected at execute
> system.cpu0.iew.iewExecutedInsts 387494 # Number of executed instructions
> system.cpu0.iew.iewExecLoadInsts 148888 # Number of load instructions executed
489,497c489,497
< system.cpu0.iew.exec_nop 73033 # number of nop insts executed
< system.cpu0.iew.exec_refs 222131 # number of memory reference insts executed
< system.cpu0.iew.exec_branches 76355 # Number of branches executed
< system.cpu0.iew.exec_stores 74340 # Number of stores executed
< system.cpu0.iew.exec_rate 1.796991 # Inst execution rate
< system.cpu0.iew.wb_sent 384301 # cumulative count of insts sent to commit
< system.cpu0.iew.wb_count 383893 # cumulative count of insts written-back
< system.cpu0.iew.wb_producers 227714 # num instructions producing a value
< system.cpu0.iew.wb_consumers 230757 # num instructions consuming a value
---
> system.cpu0.iew.exec_nop 73578 # number of nop insts executed
> system.cpu0.iew.exec_refs 223779 # number of memory reference insts executed
> system.cpu0.iew.exec_branches 76909 # Number of branches executed
> system.cpu0.iew.exec_stores 74891 # Number of stores executed
> system.cpu0.iew.exec_rate 1.798759 # Inst execution rate
> system.cpu0.iew.wb_sent 387061 # cumulative count of insts sent to commit
> system.cpu0.iew.wb_count 386653 # cumulative count of insts written-back
> system.cpu0.iew.wb_producers 229361 # num instructions producing a value
> system.cpu0.iew.wb_consumers 232407 # num instructions consuming a value
499,500c499,500
< system.cpu0.iew.wb_rate 1.793063 # insts written-back per cycle
< system.cpu0.iew.wb_fanout 0.986813 # average fanout of values written-back
---
> system.cpu0.iew.wb_rate 1.794855 # insts written-back per cycle
> system.cpu0.iew.wb_fanout 0.986894 # average fanout of values written-back
502c502
< system.cpu0.commit.commitSquashedInsts 13101 # The number of squashed insts skipped by commit
---
> system.cpu0.commit.commitSquashedInsts 13078 # The number of squashed insts skipped by commit
505,507c505,507
< system.cpu0.commit.committed_per_cycle::samples 185078 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::mean 2.431116 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::stdev 2.149204 # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::samples 186327 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::mean 2.432562 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::stdev 2.148979 # Number of insts commited each cycle
509,516c509,516
< system.cpu0.commit.committed_per_cycle::0 33718 18.22% 18.22% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::1 75423 40.75% 58.97% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::2 1935 1.05% 60.02% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::3 662 0.36% 60.37% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::4 535 0.29% 60.66% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::5 71534 38.65% 99.31% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::6 523 0.28% 99.60% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::7 265 0.14% 99.74% # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::0 33862 18.17% 18.17% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::1 75972 40.77% 58.95% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::2 1939 1.04% 59.99% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::3 672 0.36% 60.35% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::4 526 0.28% 60.63% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::5 72083 38.69% 99.32% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::6 527 0.28% 99.60% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::7 263 0.14% 99.74% # Number of insts commited each cycle
521,523c521,523
< system.cpu0.commit.committed_per_cycle::total 185078 # Number of insts commited each cycle
< system.cpu0.commit.committedInsts 449946 # Number of instructions committed
< system.cpu0.commit.committedOps 449946 # Number of ops (including micro ops) committed
---
> system.cpu0.commit.committed_per_cycle::total 186327 # Number of insts commited each cycle
> system.cpu0.commit.committedInsts 453252 # Number of instructions committed
> system.cpu0.commit.committedOps 453252 # Number of ops (including micro ops) committed
525,526c525,526
< system.cpu0.commit.refs 219688 # Number of memory references committed
< system.cpu0.commit.loads 146121 # Number of loads committed
---
> system.cpu0.commit.refs 221341 # Number of memory references committed
> system.cpu0.commit.loads 147223 # Number of loads committed
528c528
< system.cpu0.commit.branches 75454 # Number of branches committed
---
> system.cpu0.commit.branches 76005 # Number of branches committed
530c530
< system.cpu0.commit.int_insts 303394 # Number of committed integer instructions.
---
> system.cpu0.commit.int_insts 305598 # Number of committed integer instructions.
532,563c532,563
< system.cpu0.commit.op_class_0::No_OpClass 72186 16.04% 16.04% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntAlu 157988 35.11% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::MemRead 146205 32.49% 83.65% # Class of committed instruction
< system.cpu0.commit.op_class_0::MemWrite 73567 16.35% 100.00% # Class of committed instruction
---
> system.cpu0.commit.op_class_0::No_OpClass 72737 16.05% 16.05% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntAlu 159090 35.10% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemRead 147307 32.50% 83.65% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemWrite 74118 16.35% 100.00% # Class of committed instruction
566c566
< system.cpu0.commit.op_class_0::total 449946 # Class of committed instruction
---
> system.cpu0.commit.op_class_0::total 453252 # Class of committed instruction
568,569c568,569
< system.cpu0.rob.rob_reads 646481 # The number of ROB reads
< system.cpu0.rob.rob_writes 928572 # The number of ROB writes
---
> system.cpu0.rob.rob_reads 651013 # The number of ROB reads
> system.cpu0.rob.rob_writes 935136 # The number of ROB writes
571,579c571,579
< system.cpu0.idleCycles 26559 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu0.committedInsts 377676 # Number of Instructions Simulated
< system.cpu0.committedOps 377676 # Number of Ops (including micro ops) Simulated
< system.cpu0.cpi 0.566885 # CPI: Cycles Per Instruction
< system.cpu0.cpi_total 0.566885 # CPI: Total CPI of All Threads
< system.cpu0.ipc 1.764025 # IPC: Instructions Per Cycle
< system.cpu0.ipc_total 1.764025 # IPC: Total IPC of All Threads
< system.cpu0.int_regfile_reads 688304 # number of integer regfile reads
< system.cpu0.int_regfile_writes 310378 # number of integer regfile writes
---
> system.cpu0.idleCycles 26636 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu0.committedInsts 380431 # Number of Instructions Simulated
> system.cpu0.committedOps 380431 # Number of Ops (including micro ops) Simulated
> system.cpu0.cpi 0.566260 # CPI: Cycles Per Instruction
> system.cpu0.cpi_total 0.566260 # CPI: Total CPI of All Threads
> system.cpu0.ipc 1.765972 # IPC: Instructions Per Cycle
> system.cpu0.ipc_total 1.765972 # IPC: Total IPC of All Threads
> system.cpu0.int_regfile_reads 693268 # number of integer regfile reads
> system.cpu0.int_regfile_writes 312587 # number of integer regfile writes
581c581
< system.cpu0.misc_regfile_reads 223999 # number of misc regfile reads
---
> system.cpu0.misc_regfile_reads 225648 # number of misc regfile reads
584,585c584,585
< system.cpu0.dcache.tags.tagsinuse 141.054653 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 148243 # Total number of references to valid blocks.
---
> system.cpu0.dcache.tags.tagsinuse 141.123038 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 149358 # Total number of references to valid blocks.
587c587
< system.cpu0.dcache.tags.avg_refs 866.918129 # Average number of references to valid blocks.
---
> system.cpu0.dcache.tags.avg_refs 873.438596 # Average number of references to valid blocks.
589,591c589,591
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.054653 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275497 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.275497 # Average percentage of cache occupancy
---
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.123038 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275631 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.275631 # Average percentage of cache occupancy
594,595c594,595
< system.cpu0.dcache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
---
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id
597,602c597,602
< system.cpu0.dcache.tags.tag_accesses 598124 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 598124 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 75326 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 75326 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 72968 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 72968 # number of WriteReq hits
---
> system.cpu0.dcache.tags.tag_accesses 602523 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 602523 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 75889 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 75889 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 73521 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 73521 # number of WriteReq hits
605,612c605,612
< system.cpu0.dcache.demand_hits::cpu0.data 148294 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 148294 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 148294 # number of overall hits
< system.cpu0.dcache.overall_hits::total 148294 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 561 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 561 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 557 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 557 # number of WriteReq misses
---
> system.cpu0.dcache.demand_hits::cpu0.data 149410 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 149410 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 149410 # number of overall hits
> system.cpu0.dcache.overall_hits::total 149410 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 547 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 547 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 555 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 555 # number of WriteReq misses
615,622c615,622
< system.cpu0.dcache.demand_misses::cpu0.data 1118 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 1118 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 1118 # number of overall misses
< system.cpu0.dcache.overall_misses::total 1118 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17156000 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 17156000 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 33757980 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 33757980 # number of WriteReq miss cycles
---
> system.cpu0.dcache.demand_misses::cpu0.data 1102 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 1102 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 1102 # number of overall misses
> system.cpu0.dcache.overall_misses::total 1102 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16913500 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 16913500 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34798980 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 34798980 # number of WriteReq miss cycles
625,632c625,632
< system.cpu0.dcache.demand_miss_latency::cpu0.data 50913980 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 50913980 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 50913980 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 50913980 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 75887 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 75887 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 73525 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 73525 # number of WriteReq accesses(hits+misses)
---
> system.cpu0.dcache.demand_miss_latency::cpu0.data 51712480 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 51712480 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 51712480 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 51712480 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 76436 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 76436 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 74076 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 74076 # number of WriteReq accesses(hits+misses)
635,642c635,642
< system.cpu0.dcache.demand_accesses::cpu0.data 149412 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 149412 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 149412 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 149412 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007393 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.007393 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007576 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.007576 # miss rate for WriteReq accesses
---
> system.cpu0.dcache.demand_accesses::cpu0.data 150512 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 150512 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 150512 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 150512 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007156 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.007156 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007492 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.007492 # miss rate for WriteReq accesses
645,652c645,652
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007483 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.007483 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007483 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.007483 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30581.105169 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 30581.105169 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 60606.786355 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 60606.786355 # average WriteReq miss latency
---
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007322 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.007322 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007322 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.007322 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30920.475320 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 30920.475320 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62700.864865 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 62700.864865 # average WriteReq miss latency
655,658c655,658
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45540.232558 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 45540.232558 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45540.232558 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 45540.232558 # average overall miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46926.025408 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 46926.025408 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46926.025408 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 46926.025408 # average overall miss latency
669,680c669,680
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 378 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 378 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 380 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 380 # number of WriteReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 758 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 758 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 758 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 758 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 183 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 177 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 177 # number of WriteReq MSHR misses
---
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 365 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 365 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 377 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 377 # number of WriteReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 742 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 742 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 742 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 742 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 178 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 178 # number of WriteReq MSHR misses
687,690c687,690
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6883000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6883000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8240500 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8240500 # number of WriteReq MSHR miss cycles
---
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6860000 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6860000 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8493000 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8493000 # number of WriteReq MSHR miss cycles
693,700c693,700
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15123500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 15123500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15123500 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 15123500 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002411 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002411 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002407 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002407 # mshr miss rate for WriteReq accesses
---
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15353000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 15353000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15353000 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 15353000 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002381 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002381 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002403 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002403 # mshr miss rate for WriteReq accesses
703,710c703,710
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002409 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.002409 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002409 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.002409 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37612.021858 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37612.021858 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46556.497175 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46556.497175 # average WriteReq mshr miss latency
---
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.002392 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.002392 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37692.307692 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37692.307692 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47713.483146 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47713.483146 # average WriteReq mshr miss latency
713,716c713,716
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42009.722222 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42009.722222 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42009.722222 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42009.722222 # average overall mshr miss latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42647.222222 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42647.222222 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42647.222222 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42647.222222 # average overall mshr miss latency
719c719
< system.cpu0.icache.tags.tagsinuse 241.042514 # Cycle average of tags in use
---
> system.cpu0.icache.tags.tagsinuse 241.163907 # Cycle average of tags in use
724,726c724,726
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.042514 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.470786 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.470786 # Average percentage of cache occupancy
---
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.163907 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471023 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.471023 # Average percentage of cache occupancy
729,730c729,730
< system.cpu0.icache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id
746,751c746,751
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40365000 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 40365000 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 40365000 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 40365000 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 40365000 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 40365000 # number of overall miss cycles
---
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40406000 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 40406000 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 40406000 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 40406000 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 40406000 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 40406000 # number of overall miss cycles
764,769c764,769
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51485.969388 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 51485.969388 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51485.969388 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 51485.969388 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51485.969388 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 51485.969388 # average overall miss latency
---
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51538.265306 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 51538.265306 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51538.265306 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 51538.265306 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51538.265306 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 51538.265306 # average overall miss latency
790,795c790,795
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31177000 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 31177000 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31177000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 31177000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31177000 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 31177000 # number of overall MSHR miss cycles
---
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31294000 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 31294000 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31294000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 31294000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31294000 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 31294000 # number of overall MSHR miss cycles
802,807c802,807
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51277.960526 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51277.960526 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51277.960526 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 51277.960526 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51277.960526 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 51277.960526 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51470.394737 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51470.394737 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51470.394737 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 51470.394737 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51470.394737 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 51470.394737 # average overall mshr miss latency
809,813c809,813
< system.cpu1.branchPred.lookups 50039 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 46665 # Number of conditional branches predicted
< system.cpu1.branchPred.condIncorrect 1271 # Number of conditional branches incorrect
< system.cpu1.branchPred.BTBLookups 42823 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 41749 # Number of BTB hits
---
> system.cpu1.branchPred.lookups 53924 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 50532 # Number of conditional branches predicted
> system.cpu1.branchPred.condIncorrect 1274 # Number of conditional branches incorrect
> system.cpu1.branchPred.BTBLookups 46687 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 45618 # Number of BTB hits
815,816c815,816
< system.cpu1.branchPred.BTBHitPct 97.492002 # BTB Hit Percentage
< system.cpu1.branchPred.usedRAS 914 # Number of times the RAS was used to get a target.
---
> system.cpu1.branchPred.BTBHitPct 97.710283 # BTB Hit Percentage
> system.cpu1.branchPred.usedRAS 909 # Number of times the RAS was used to get a target.
818c818
< system.cpu1.numCycles 161348 # number of cpu cycles simulated
---
> system.cpu1.numCycles 162664 # number of cpu cycles simulated
821,826c821,826
< system.cpu1.fetch.icacheStallCycles 31303 # Number of cycles fetch is stalled on an Icache miss
< system.cpu1.fetch.Insts 275372 # Number of instructions fetch has processed
< system.cpu1.fetch.Branches 50039 # Number of branches that fetch encountered
< system.cpu1.fetch.predictedBranches 42663 # Number of branches that fetch has predicted taken
< system.cpu1.fetch.Cycles 121719 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu1.fetch.SquashCycles 2699 # Number of cycles fetch has spent squashing
---
> system.cpu1.fetch.icacheStallCycles 29507 # Number of cycles fetch is stalled on an Icache miss
> system.cpu1.fetch.Insts 300555 # Number of instructions fetch has processed
> system.cpu1.fetch.Branches 53924 # Number of branches that fetch encountered
> system.cpu1.fetch.predictedBranches 46527 # Number of branches that fetch has predicted taken
> system.cpu1.fetch.Cycles 124688 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu1.fetch.SquashCycles 2705 # Number of cycles fetch has spent squashing
831,835c831,835
< system.cpu1.fetch.CacheLines 21928 # Number of cache lines fetched
< system.cpu1.fetch.IcacheSquashes 442 # Number of outstanding Icache misses that were squashed
< system.cpu1.fetch.rateDist::samples 155480 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::mean 1.771109 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::stdev 2.178899 # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.CacheLines 20020 # Number of cache lines fetched
> system.cpu1.fetch.IcacheSquashes 452 # Number of outstanding Icache misses that were squashed
> system.cpu1.fetch.rateDist::samples 156656 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::mean 1.918567 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::stdev 2.216659 # Number of instructions fetched each cycle (Total)
837,845c837,845
< system.cpu1.fetch.rateDist::0 58088 37.36% 37.36% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::1 49421 31.79% 69.15% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::2 6835 4.40% 73.54% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::3 3518 2.26% 75.81% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::4 944 0.61% 76.41% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::5 30727 19.76% 96.18% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::6 1228 0.79% 96.96% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::7 804 0.52% 97.48% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::8 3915 2.52% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::0 52489 33.51% 33.51% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::1 52328 33.40% 66.91% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::2 5864 3.74% 70.65% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::3 3542 2.26% 72.91% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::4 937 0.60% 73.51% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::5 35524 22.68% 96.19% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::6 1237 0.79% 96.98% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::7 797 0.51% 97.49% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::8 3938 2.51% 100.00% # Number of instructions fetched each cycle (Total)
849,866c849,866
< system.cpu1.fetch.rateDist::total 155480 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.branchRate 0.310131 # Number of branch fetches per cycle
< system.cpu1.fetch.rate 1.706696 # Number of inst fetches per cycle
< system.cpu1.decode.IdleCycles 17833 # Number of cycles decode is idle
< system.cpu1.decode.BlockedCycles 58352 # Number of cycles decode is blocked
< system.cpu1.decode.RunCycles 74506 # Number of cycles decode is running
< system.cpu1.decode.UnblockCycles 3430 # Number of cycles decode is unblocking
< system.cpu1.decode.SquashCycles 1349 # Number of cycles decode is squashing
< system.cpu1.decode.DecodedInsts 260078 # Number of instructions handled by decode
< system.cpu1.rename.SquashCycles 1349 # Number of cycles rename is squashing
< system.cpu1.rename.IdleCycles 18539 # Number of cycles rename is idle
< system.cpu1.rename.BlockCycles 27109 # Number of cycles rename is blocking
< system.cpu1.rename.serializeStallCycles 13862 # count of cycles rename stalled for serializing inst
< system.cpu1.rename.RunCycles 76429 # Number of cycles rename is running
< system.cpu1.rename.UnblockCycles 18182 # Number of cycles rename is unblocking
< system.cpu1.rename.RenamedInsts 256857 # Number of instructions processed by rename
< system.cpu1.rename.IQFullEvents 16651 # Number of times rename has blocked due to IQ full
< system.cpu1.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full
---
> system.cpu1.fetch.rateDist::total 156656 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.branchRate 0.331505 # Number of branch fetches per cycle
> system.cpu1.fetch.rate 1.847704 # Number of inst fetches per cycle
> system.cpu1.decode.IdleCycles 17844 # Number of cycles decode is idle
> system.cpu1.decode.BlockedCycles 50371 # Number of cycles decode is blocked
> system.cpu1.decode.RunCycles 84089 # Number of cycles decode is running
> system.cpu1.decode.UnblockCycles 2990 # Number of cycles decode is unblocking
> system.cpu1.decode.SquashCycles 1352 # Number of cycles decode is squashing
> system.cpu1.decode.DecodedInsts 285365 # Number of instructions handled by decode
> system.cpu1.rename.SquashCycles 1352 # Number of cycles rename is squashing
> system.cpu1.rename.IdleCycles 18555 # Number of cycles rename is idle
> system.cpu1.rename.BlockCycles 22336 # Number of cycles rename is blocking
> system.cpu1.rename.serializeStallCycles 13775 # count of cycles rename stalled for serializing inst
> system.cpu1.rename.RunCycles 85993 # Number of cycles rename is running
> system.cpu1.rename.UnblockCycles 14635 # Number of cycles rename is unblocking
> system.cpu1.rename.RenamedInsts 282118 # Number of instructions processed by rename
> system.cpu1.rename.IQFullEvents 13530 # Number of times rename has blocked due to IQ full
> system.cpu1.rename.LQFullEvents 15 # Number of times rename has blocked due to LQ full
868,889c868,889
< system.cpu1.rename.RenamedOperands 180872 # Number of destination operands rename has renamed
< system.cpu1.rename.RenameLookups 489824 # Number of register rename lookups that rename has made
< system.cpu1.rename.int_rename_lookups 382391 # Number of integer rename lookups
< system.cpu1.rename.CommittedMaps 167019 # Number of HB maps that are committed
< system.cpu1.rename.UndoneMaps 13853 # Number of HB maps that are undone due to squashing
< system.cpu1.rename.serializingInsts 1180 # count of serializing insts renamed
< system.cpu1.rename.tempSerializingInsts 1251 # count of temporary serializing insts renamed
< system.cpu1.rename.skidInsts 22657 # count of insts added to the skid buffer
< system.cpu1.memDep0.insertedLoads 71171 # Number of loads inserted to the mem dependence unit.
< system.cpu1.memDep0.insertedStores 33454 # Number of stores inserted to the mem dependence unit.
< system.cpu1.memDep0.conflictingLoads 33920 # Number of conflicting loads.
< system.cpu1.memDep0.conflictingStores 28372 # Number of conflicting stores.
< system.cpu1.iq.iqInstsAdded 213121 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu1.iq.iqNonSpecInstsAdded 6586 # Number of non-speculative instructions added to the IQ
< system.cpu1.iq.iqInstsIssued 214969 # Number of instructions issued
< system.cpu1.iq.iqSquashedInstsIssued 17 # Number of squashed instructions issued
< system.cpu1.iq.iqSquashedInstsExamined 13076 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu1.iq.iqSquashedOperandsExamined 10906 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu1.iq.iqSquashedNonSpecRemoved 730 # Number of squashed non-spec instructions that were removed
< system.cpu1.iq.issued_per_cycle::samples 155480 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::mean 1.382615 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::stdev 1.383057 # Number of insts issued each cycle
---
> system.cpu1.rename.RenamedOperands 199297 # Number of destination operands rename has renamed
> system.cpu1.rename.RenameLookups 544091 # Number of register rename lookups that rename has made
> system.cpu1.rename.int_rename_lookups 423098 # Number of integer rename lookups
> system.cpu1.rename.CommittedMaps 185456 # Number of HB maps that are committed
> system.cpu1.rename.UndoneMaps 13841 # Number of HB maps that are undone due to squashing
> system.cpu1.rename.serializingInsts 1187 # count of serializing insts renamed
> system.cpu1.rename.tempSerializingInsts 1257 # count of temporary serializing insts renamed
> system.cpu1.rename.skidInsts 19159 # count of insts added to the skid buffer
> system.cpu1.memDep0.insertedLoads 79883 # Number of loads inserted to the mem dependence unit.
> system.cpu1.memDep0.insertedStores 38287 # Number of stores inserted to the mem dependence unit.
> system.cpu1.memDep0.conflictingLoads 37783 # Number of conflicting loads.
> system.cpu1.memDep0.conflictingStores 33197 # Number of conflicting stores.
> system.cpu1.iq.iqInstsAdded 235383 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu1.iq.iqNonSpecInstsAdded 5651 # Number of non-speculative instructions added to the IQ
> system.cpu1.iq.iqInstsIssued 236419 # Number of instructions issued
> system.cpu1.iq.iqSquashedInstsIssued 14 # Number of squashed instructions issued
> system.cpu1.iq.iqSquashedInstsExamined 12945 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu1.iq.iqSquashedOperandsExamined 10680 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu1.iq.iqSquashedNonSpecRemoved 703 # Number of squashed non-spec instructions that were removed
> system.cpu1.iq.issued_per_cycle::samples 156656 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::mean 1.509160 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::stdev 1.379040 # Number of insts issued each cycle
891,899c891,899
< system.cpu1.iq.issued_per_cycle::0 61906 39.82% 39.82% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::1 21977 14.13% 53.95% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::2 32894 21.16% 75.11% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::3 32429 20.86% 95.96% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::4 3365 2.16% 98.13% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::5 1605 1.03% 99.16% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::6 896 0.58% 99.74% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::7 208 0.13% 99.87% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::8 200 0.13% 100.00% # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::0 56139 35.84% 35.84% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::1 19247 12.29% 48.12% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::2 37725 24.08% 72.20% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::3 37266 23.79% 95.99% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::4 3381 2.16% 98.15% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::5 1595 1.02% 99.17% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::6 897 0.57% 99.74% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::7 205 0.13% 99.87% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::8 201 0.13% 100.00% # Number of insts issued each cycle
903c903
< system.cpu1.iq.issued_per_cycle::total 155480 # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::total 156656 # Number of insts issued each cycle
905,935c905,935
< system.cpu1.iq.fu_full::IntAlu 79 23.72% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntMult 0 0.00% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntDiv 0 0.00% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatAdd 0 0.00% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCmp 0 0.00% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCvt 0 0.00% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMult 0 0.00% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatDiv 0 0.00% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAdd 0 0.00% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAlu 0 0.00% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCmp 0 0.00% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCvt 0 0.00% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMisc 0 0.00% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMult 0 0.00% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShift 0 0.00% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 23.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemRead 45 13.51% 37.24% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemWrite 209 62.76% 100.00% # attempts to use FU when none available
---
> system.cpu1.iq.fu_full::IntAlu 79 23.65% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntMult 0 0.00% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntDiv 0 0.00% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatAdd 0 0.00% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCmp 0 0.00% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCvt 0 0.00% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMult 0 0.00% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatDiv 0 0.00% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAdd 0 0.00% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAlu 0 0.00% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCmp 0 0.00% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCvt 0 0.00% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMisc 0 0.00% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMult 0 0.00% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShift 0 0.00% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 23.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemRead 46 13.77% 37.43% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemWrite 209 62.57% 100.00% # attempts to use FU when none available
939,969c939,969
< system.cpu1.iq.FU_type_0::IntAlu 106597 49.59% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.59% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemRead 75532 35.14% 84.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemWrite 32840 15.28% 100.00% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::IntAlu 115374 48.80% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.80% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemRead 83373 35.26% 84.07% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemWrite 37672 15.93% 100.00% # Type of FU issued
972,978c972,978
< system.cpu1.iq.FU_type_0::total 214969 # Type of FU issued
< system.cpu1.iq.rate 1.332331 # Inst issue rate
< system.cpu1.iq.fu_busy_cnt 333 # FU busy when requested
< system.cpu1.iq.fu_busy_rate 0.001549 # FU busy rate (busy events/executed inst)
< system.cpu1.iq.int_inst_queue_reads 585768 # Number of integer instruction queue reads
< system.cpu1.iq.int_inst_queue_writes 232822 # Number of integer instruction queue writes
< system.cpu1.iq.int_inst_queue_wakeup_accesses 213429 # Number of integer instruction queue wakeup accesses
---
> system.cpu1.iq.FU_type_0::total 236419 # Type of FU issued
> system.cpu1.iq.rate 1.453419 # Inst issue rate
> system.cpu1.iq.fu_busy_cnt 334 # FU busy when requested
> system.cpu1.iq.fu_busy_rate 0.001413 # FU busy rate (busy events/executed inst)
> system.cpu1.iq.int_inst_queue_reads 629842 # Number of integer instruction queue reads
> system.cpu1.iq.int_inst_queue_writes 254017 # Number of integer instruction queue writes
> system.cpu1.iq.int_inst_queue_wakeup_accesses 234890 # Number of integer instruction queue wakeup accesses
982c982
< system.cpu1.iq.int_alu_accesses 215302 # Number of integer alu accesses
---
> system.cpu1.iq.int_alu_accesses 236753 # Number of integer alu accesses
984c984
< system.cpu1.iew.lsq.thread0.forwLoads 28182 # Number of loads that had data forwarded from stores
---
> system.cpu1.iew.lsq.thread0.forwLoads 33006 # Number of loads that had data forwarded from stores
986c986
< system.cpu1.iew.lsq.thread0.squashedLoads 2653 # Number of loads squashed
---
> system.cpu1.iew.lsq.thread0.squashedLoads 2599 # Number of loads squashed
988,989c988,989
< system.cpu1.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations
< system.cpu1.iew.lsq.thread0.squashedStores 1503 # Number of stores squashed
---
> system.cpu1.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations
> system.cpu1.iew.lsq.thread0.squashedStores 1501 # Number of stores squashed
995,1003c995,1003
< system.cpu1.iew.iewSquashCycles 1349 # Number of cycles IEW is squashing
< system.cpu1.iew.iewBlockCycles 7989 # Number of cycles IEW is blocking
< system.cpu1.iew.iewUnblockCycles 73 # Number of cycles IEW is unblocking
< system.cpu1.iew.iewDispatchedInsts 254448 # Number of instructions dispatched to IQ
< system.cpu1.iew.iewDispSquashedInsts 142 # Number of squashed instructions skipped by dispatch
< system.cpu1.iew.iewDispLoadInsts 71171 # Number of dispatched load instructions
< system.cpu1.iew.iewDispStoreInsts 33454 # Number of dispatched store instructions
< system.cpu1.iew.iewDispNonSpecInsts 1130 # Number of dispatched non-speculative instructions
< system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall
---
> system.cpu1.iew.iewSquashCycles 1352 # Number of cycles IEW is squashing
> system.cpu1.iew.iewBlockCycles 6792 # Number of cycles IEW is blocking
> system.cpu1.iew.iewUnblockCycles 64 # Number of cycles IEW is unblocking
> system.cpu1.iew.iewDispatchedInsts 279653 # Number of instructions dispatched to IQ
> system.cpu1.iew.iewDispSquashedInsts 149 # Number of squashed instructions skipped by dispatch
> system.cpu1.iew.iewDispLoadInsts 79883 # Number of dispatched load instructions
> system.cpu1.iew.iewDispStoreInsts 38287 # Number of dispatched store instructions
> system.cpu1.iew.iewDispNonSpecInsts 1135 # Number of dispatched non-speculative instructions
> system.cpu1.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall
1005,1011c1005,1011
< system.cpu1.iew.memOrderViolationEvents 39 # Number of memory order violations
< system.cpu1.iew.predictedTakenIncorrect 452 # Number of branches that were predicted taken incorrectly
< system.cpu1.iew.predictedNotTakenIncorrect 1051 # Number of branches that were predicted not taken incorrectly
< system.cpu1.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute
< system.cpu1.iew.iewExecutedInsts 213962 # Number of executed instructions
< system.cpu1.iew.iewExecLoadInsts 70077 # Number of load instructions executed
< system.cpu1.iew.iewExecSquashedInsts 1007 # Number of squashed instructions skipped in execute
---
> system.cpu1.iew.memOrderViolationEvents 38 # Number of memory order violations
> system.cpu1.iew.predictedTakenIncorrect 444 # Number of branches that were predicted taken incorrectly
> system.cpu1.iew.predictedNotTakenIncorrect 1061 # Number of branches that were predicted not taken incorrectly
> system.cpu1.iew.branchMispredicts 1505 # Number of branch mispredicts detected at execute
> system.cpu1.iew.iewExecutedInsts 235416 # Number of executed instructions
> system.cpu1.iew.iewExecLoadInsts 78826 # Number of load instructions executed
> system.cpu1.iew.iewExecSquashedInsts 1003 # Number of squashed instructions skipped in execute
1013,1021c1013,1021
< system.cpu1.iew.exec_nop 34741 # number of nop insts executed
< system.cpu1.iew.exec_refs 102825 # number of memory reference insts executed
< system.cpu1.iew.exec_branches 44094 # Number of branches executed
< system.cpu1.iew.exec_stores 32748 # Number of stores executed
< system.cpu1.iew.exec_rate 1.326090 # Inst execution rate
< system.cpu1.iew.wb_sent 213711 # cumulative count of insts sent to commit
< system.cpu1.iew.wb_count 213429 # cumulative count of insts written-back
< system.cpu1.iew.wb_producers 120431 # num instructions producing a value
< system.cpu1.iew.wb_consumers 127039 # num instructions consuming a value
---
> system.cpu1.iew.exec_nop 38619 # number of nop insts executed
> system.cpu1.iew.exec_refs 116410 # number of memory reference insts executed
> system.cpu1.iew.exec_branches 48027 # Number of branches executed
> system.cpu1.iew.exec_stores 37584 # Number of stores executed
> system.cpu1.iew.exec_rate 1.447253 # Inst execution rate
> system.cpu1.iew.wb_sent 235168 # cumulative count of insts sent to commit
> system.cpu1.iew.wb_count 234890 # cumulative count of insts written-back
> system.cpu1.iew.wb_producers 134020 # num instructions producing a value
> system.cpu1.iew.wb_consumers 140635 # num instructions consuming a value
1023,1024c1023,1024
< system.cpu1.iew.wb_rate 1.322787 # insts written-back per cycle
< system.cpu1.iew.wb_fanout 0.947984 # average fanout of values written-back
---
> system.cpu1.iew.wb_rate 1.444020 # insts written-back per cycle
> system.cpu1.iew.wb_fanout 0.952963 # average fanout of values written-back
1026,1031c1026,1031
< system.cpu1.commit.commitSquashedInsts 13922 # The number of squashed insts skipped by commit
< system.cpu1.commit.commitNonSpecStalls 5856 # The number of times commit has been forced to stall to communicate backwards
< system.cpu1.commit.branchMispredicts 1271 # The number of times a branch was mispredicted
< system.cpu1.commit.committed_per_cycle::samples 152910 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::mean 1.572631 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::stdev 2.035068 # Number of insts commited each cycle
---
> system.cpu1.commit.commitSquashedInsts 13740 # The number of squashed insts skipped by commit
> system.cpu1.commit.commitNonSpecStalls 4948 # The number of times commit has been forced to stall to communicate backwards
> system.cpu1.commit.branchMispredicts 1274 # The number of times a branch was mispredicted
> system.cpu1.commit.committed_per_cycle::samples 154106 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::mean 1.725163 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::stdev 2.084593 # Number of insts commited each cycle
1033,1041c1033,1041
< system.cpu1.commit.committed_per_cycle::0 67472 44.13% 44.13% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::1 40678 26.60% 70.73% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::2 5251 3.43% 74.16% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::3 6680 4.37% 78.53% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::4 1520 0.99% 79.52% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::5 28236 18.47% 97.99% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::6 823 0.54% 98.53% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::7 947 0.62% 99.15% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::8 1303 0.85% 100.00% # Number of insts commited each cycle
---
> system.cpu1.commit.committed_per_cycle::0 60830 39.47% 39.47% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::1 44602 28.94% 68.42% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::2 5225 3.39% 71.81% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::3 5769 3.74% 75.55% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::4 1531 0.99% 76.54% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::5 33080 21.47% 98.01% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::6 818 0.53% 98.54% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::7 941 0.61% 99.15% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::8 1310 0.85% 100.00% # Number of insts commited each cycle
1045,1047c1045,1047
< system.cpu1.commit.committed_per_cycle::total 152910 # Number of insts commited each cycle
< system.cpu1.commit.committedInsts 240471 # Number of instructions committed
< system.cpu1.commit.committedOps 240471 # Number of ops (including micro ops) committed
---
> system.cpu1.commit.committed_per_cycle::total 154106 # Number of insts commited each cycle
> system.cpu1.commit.committedInsts 265858 # Number of instructions committed
> system.cpu1.commit.committedOps 265858 # Number of ops (including micro ops) committed
1049,1052c1049,1052
< system.cpu1.commit.refs 100469 # Number of memory references committed
< system.cpu1.commit.loads 68518 # Number of loads committed
< system.cpu1.commit.membars 5139 # Number of memory barriers committed
< system.cpu1.commit.branches 43053 # Number of branches committed
---
> system.cpu1.commit.refs 114070 # Number of memory references committed
> system.cpu1.commit.loads 77284 # Number of loads committed
> system.cpu1.commit.membars 4232 # Number of memory barriers committed
> system.cpu1.commit.branches 46981 # Number of branches committed
1054c1054
< system.cpu1.commit.int_insts 165641 # Number of committed integer instructions.
---
> system.cpu1.commit.int_insts 183171 # Number of committed integer instructions.
1056,1087c1056,1087
< system.cpu1.commit.op_class_0::No_OpClass 33840 14.07% 14.07% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntAlu 101023 42.01% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntMult 0 0.00% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntDiv 0 0.00% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatMult 0 0.00% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMult 0 0.00% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdShift 0 0.00% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.08% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemRead 73657 30.63% 86.71% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemWrite 31951 13.29% 100.00% # Class of committed instruction
---
> system.cpu1.commit.op_class_0::No_OpClass 37769 14.21% 14.21% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntAlu 109787 41.30% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemRead 81516 30.66% 86.16% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemWrite 36786 13.84% 100.00% # Class of committed instruction
1090,1095c1090,1095
< system.cpu1.commit.op_class_0::total 240471 # Class of committed instruction
< system.cpu1.commit.bw_lim_events 1303 # number cycles where commit BW limit reached
< system.cpu1.rob.rob_reads 405414 # The number of ROB reads
< system.cpu1.rob.rob_writes 511356 # The number of ROB writes
< system.cpu1.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu1.idleCycles 5868 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu1.commit.op_class_0::total 265858 # Class of committed instruction
> system.cpu1.commit.bw_lim_events 1310 # number cycles where commit BW limit reached
> system.cpu1.rob.rob_reads 431808 # The number of ROB reads
> system.cpu1.rob.rob_writes 561746 # The number of ROB writes
> system.cpu1.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu1.idleCycles 6008 # Total number of cycles that the CPU has spent unscheduled due to idling
1097,1104c1097,1104
< system.cpu1.committedInsts 201492 # Number of Instructions Simulated
< system.cpu1.committedOps 201492 # Number of Ops (including micro ops) Simulated
< system.cpu1.cpi 0.800766 # CPI: Cycles Per Instruction
< system.cpu1.cpi_total 0.800766 # CPI: Total CPI of All Threads
< system.cpu1.ipc 1.248804 # IPC: Instructions Per Cycle
< system.cpu1.ipc_total 1.248804 # IPC: Total IPC of All Threads
< system.cpu1.int_regfile_reads 368266 # number of integer regfile reads
< system.cpu1.int_regfile_writes 172947 # number of integer regfile writes
---
> system.cpu1.committedInsts 223857 # Number of Instructions Simulated
> system.cpu1.committedOps 223857 # Number of Ops (including micro ops) Simulated
> system.cpu1.cpi 0.726642 # CPI: Cycles Per Instruction
> system.cpu1.cpi_total 0.726642 # CPI: Total CPI of All Threads
> system.cpu1.ipc 1.376193 # IPC: Instructions Per Cycle
> system.cpu1.ipc_total 1.376193 # IPC: Total IPC of All Threads
> system.cpu1.int_regfile_reads 409049 # number of integer regfile reads
> system.cpu1.int_regfile_writes 191377 # number of integer regfile writes
1106c1106
< system.cpu1.misc_regfile_reads 104453 # number of misc regfile reads
---
> system.cpu1.misc_regfile_reads 118040 # number of misc regfile reads
1109,1110c1109,1110
< system.cpu1.dcache.tags.tagsinuse 25.714463 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 38066 # Total number of references to valid blocks.
---
> system.cpu1.dcache.tags.tagsinuse 25.752806 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 42910 # Total number of references to valid blocks.
1112c1112
< system.cpu1.dcache.tags.avg_refs 1312.620690 # Average number of references to valid blocks.
---
> system.cpu1.dcache.tags.avg_refs 1479.655172 # Average number of references to valid blocks.
1114,1116c1114,1116
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.714463 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050224 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.050224 # Average percentage of cache occupancy
---
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.752806 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050298 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.050298 # Average percentage of cache occupancy
1121,1126c1121,1126
< system.cpu1.dcache.tags.tag_accesses 295559 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 295559 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 41369 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 41369 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 31720 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 31720 # number of WriteReq hits
---
> system.cpu1.dcache.tags.tag_accesses 330593 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 330593 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 45309 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 45309 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 36557 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 36557 # number of WriteReq hits
1129,1182c1129,1182
< system.cpu1.dcache.demand_hits::cpu1.data 73089 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 73089 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 73089 # number of overall hits
< system.cpu1.dcache.overall_hits::total 73089 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 504 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 504 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 160 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 160 # number of WriteReq misses
< system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses
< system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 664 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 664 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 664 # number of overall misses
< system.cpu1.dcache.overall_misses::total 664 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9769000 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 9769000 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3369500 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 3369500 # number of WriteReq miss cycles
< system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 693500 # number of SwapReq miss cycles
< system.cpu1.dcache.SwapReq_miss_latency::total 693500 # number of SwapReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 13138500 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 13138500 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 13138500 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 13138500 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 41873 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 41873 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 31880 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 31880 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses)
< system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 73753 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 73753 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 73753 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 73753 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.012036 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.012036 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.005019 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.005019 # miss rate for WriteReq accesses
< system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.788732 # miss rate for SwapReq accesses
< system.cpu1.dcache.SwapReq_miss_rate::total 0.788732 # miss rate for SwapReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.009003 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.009003 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.009003 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.009003 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19382.936508 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 19382.936508 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21059.375000 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 21059.375000 # average WriteReq miss latency
< system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 12383.928571 # average SwapReq miss latency
< system.cpu1.dcache.SwapReq_avg_miss_latency::total 12383.928571 # average SwapReq miss latency
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19786.897590 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 19786.897590 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19786.897590 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 19786.897590 # average overall miss latency
---
> system.cpu1.dcache.demand_hits::cpu1.data 81866 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 81866 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 81866 # number of overall hits
> system.cpu1.dcache.overall_hits::total 81866 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 489 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 489 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 159 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 159 # number of WriteReq misses
> system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses
> system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 648 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 648 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 648 # number of overall misses
> system.cpu1.dcache.overall_misses::total 648 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9556000 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 9556000 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3376000 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 3376000 # number of WriteReq miss cycles
> system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 667000 # number of SwapReq miss cycles
> system.cpu1.dcache.SwapReq_miss_latency::total 667000 # number of SwapReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 12932000 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 12932000 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 12932000 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 12932000 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 45798 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 45798 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 36716 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 36716 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses)
> system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 82514 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 82514 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 82514 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 82514 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010677 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.010677 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004331 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.004331 # miss rate for WriteReq accesses
> system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.785714 # miss rate for SwapReq accesses
> system.cpu1.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007853 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.007853 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007853 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.007853 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19541.922290 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 19541.922290 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21232.704403 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 21232.704403 # average WriteReq miss latency
> system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 12127.272727 # average SwapReq miss latency
> system.cpu1.dcache.SwapReq_avg_miss_latency::total 12127.272727 # average SwapReq miss latency
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19956.790123 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 19956.790123 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19956.790123 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 19956.790123 # average overall miss latency
1191,1192c1191,1192
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 332 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 332 # number of ReadReq MSHR hits
---
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 325 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 325 # number of ReadReq MSHR hits
1195,1238c1195,1238
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 385 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 385 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 385 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 385 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses
< system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses
< system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 279 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 279 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 279 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2195000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2195000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1746000 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1746000 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 637500 # number of SwapReq MSHR miss cycles
< system.cpu1.dcache.SwapReq_mshr_miss_latency::total 637500 # number of SwapReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3941000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 3941000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3941000 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 3941000 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004108 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004108 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003356 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003356 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.788732 # mshr miss rate for SwapReq accesses
< system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.788732 # mshr miss rate for SwapReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003783 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.003783 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003783 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.003783 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12761.627907 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12761.627907 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16317.757009 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16317.757009 # average WriteReq mshr miss latency
< system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 11383.928571 # average SwapReq mshr miss latency
< system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 11383.928571 # average SwapReq mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14125.448029 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14125.448029 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14125.448029 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14125.448029 # average overall mshr miss latency
---
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 378 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 378 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 378 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 378 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 164 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses
> system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses
> system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2051500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2051500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1754500 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1754500 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 612000 # number of SwapReq MSHR miss cycles
> system.cpu1.dcache.SwapReq_mshr_miss_latency::total 612000 # number of SwapReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3806000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 3806000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3806000 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 3806000 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003581 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003581 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002887 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002887 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for SwapReq accesses
> system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.785714 # mshr miss rate for SwapReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003272 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.003272 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003272 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.003272 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12509.146341 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12509.146341 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16551.886792 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16551.886792 # average WriteReq mshr miss latency
> system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 11127.272727 # average SwapReq mshr miss latency
> system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 11127.272727 # average SwapReq mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14096.296296 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14096.296296 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14096.296296 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14096.296296 # average overall mshr miss latency
1241,1242c1241,1242
< system.cpu1.icache.tags.tagsinuse 84.275379 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 21349 # Total number of references to valid blocks.
---
> system.cpu1.icache.tags.tagsinuse 84.461587 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 19439 # Total number of references to valid blocks.
1244c1244
< system.cpu1.icache.tags.avg_refs 43.042339 # Average number of references to valid blocks.
---
> system.cpu1.icache.tags.avg_refs 39.191532 # Average number of references to valid blocks.
1246,1248c1246,1248
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 84.275379 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.164600 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.164600 # Average percentage of cache occupancy
---
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 84.461587 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.164964 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.164964 # Average percentage of cache occupancy
1253,1290c1253,1290
< system.cpu1.icache.tags.tag_accesses 22424 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 22424 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 21349 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 21349 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 21349 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 21349 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 21349 # number of overall hits
< system.cpu1.icache.overall_hits::total 21349 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 579 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 579 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 579 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 579 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 579 # number of overall misses
< system.cpu1.icache.overall_misses::total 579 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 13955500 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 13955500 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 13955500 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 13955500 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 13955500 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 13955500 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 21928 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 21928 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 21928 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 21928 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 21928 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 21928 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.026405 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.026405 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.026405 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.026405 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.026405 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.026405 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24102.763385 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 24102.763385 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24102.763385 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 24102.763385 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24102.763385 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 24102.763385 # average overall miss latency
---
> system.cpu1.icache.tags.tag_accesses 20516 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 20516 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 19439 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 19439 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 19439 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 19439 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 19439 # number of overall hits
> system.cpu1.icache.overall_hits::total 19439 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 581 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 581 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 581 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 581 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 581 # number of overall misses
> system.cpu1.icache.overall_misses::total 581 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14331000 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 14331000 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 14331000 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 14331000 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 14331000 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 14331000 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 20020 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 20020 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 20020 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 20020 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 20020 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 20020 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029021 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.029021 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029021 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.029021 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029021 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.029021 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24666.092943 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 24666.092943 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24666.092943 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 24666.092943 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24666.092943 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 24666.092943 # average overall miss latency
1299,1304c1299,1304
< system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 83 # number of ReadReq MSHR hits
< system.cpu1.icache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits
< system.cpu1.icache.demand_mshr_hits::cpu1.inst 83 # number of demand (read+write) MSHR hits
< system.cpu1.icache.demand_mshr_hits::total 83 # number of demand (read+write) MSHR hits
< system.cpu1.icache.overall_mshr_hits::cpu1.inst 83 # number of overall MSHR hits
< system.cpu1.icache.overall_mshr_hits::total 83 # number of overall MSHR hits
---
> system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 85 # number of ReadReq MSHR hits
> system.cpu1.icache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits
> system.cpu1.icache.demand_mshr_hits::cpu1.inst 85 # number of demand (read+write) MSHR hits
> system.cpu1.icache.demand_mshr_hits::total 85 # number of demand (read+write) MSHR hits
> system.cpu1.icache.overall_mshr_hits::cpu1.inst 85 # number of overall MSHR hits
> system.cpu1.icache.overall_mshr_hits::total 85 # number of overall MSHR hits
1311,1328c1311,1328
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11502500 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 11502500 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11502500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 11502500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11502500 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 11502500 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022619 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022619 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022619 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.022619 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022619 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.022619 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23190.524194 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23190.524194 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23190.524194 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 23190.524194 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23190.524194 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 23190.524194 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11831000 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 11831000 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11831000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 11831000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11831000 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 11831000 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024775 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024775 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024775 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.024775 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024775 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.024775 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23852.822581 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23852.822581 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23852.822581 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 23852.822581 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23852.822581 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 23852.822581 # average overall mshr miss latency
1330,1334c1330,1334
< system.cpu2.branchPred.lookups 42880 # Number of BP lookups
< system.cpu2.branchPred.condPredicted 39445 # Number of conditional branches predicted
< system.cpu2.branchPred.condIncorrect 1259 # Number of conditional branches incorrect
< system.cpu2.branchPred.BTBLookups 35521 # Number of BTB lookups
< system.cpu2.branchPred.BTBHits 34492 # Number of BTB hits
---
> system.cpu2.branchPred.lookups 55489 # Number of BP lookups
> system.cpu2.branchPred.condPredicted 52130 # Number of conditional branches predicted
> system.cpu2.branchPred.condIncorrect 1272 # Number of conditional branches incorrect
> system.cpu2.branchPred.BTBLookups 48168 # Number of BTB lookups
> system.cpu2.branchPred.BTBHits 47221 # Number of BTB hits
1336,1337c1336,1337
< system.cpu2.branchPred.BTBHitPct 97.103122 # BTB Hit Percentage
< system.cpu2.branchPred.usedRAS 904 # Number of times the RAS was used to get a target.
---
> system.cpu2.branchPred.BTBHitPct 98.033964 # BTB Hit Percentage
> system.cpu2.branchPred.usedRAS 905 # Number of times the RAS was used to get a target.
1339c1339
< system.cpu2.numCycles 160976 # number of cpu cycles simulated
---
> system.cpu2.numCycles 162291 # number of cpu cycles simulated
1342,1347c1342,1347
< system.cpu2.fetch.icacheStallCycles 36449 # Number of cycles fetch is stalled on an Icache miss
< system.cpu2.fetch.Insts 226588 # Number of instructions fetch has processed
< system.cpu2.fetch.Branches 42880 # Number of branches that fetch encountered
< system.cpu2.fetch.predictedBranches 35396 # Number of branches that fetch has predicted taken
< system.cpu2.fetch.Cycles 120624 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu2.fetch.SquashCycles 2677 # Number of cycles fetch has spent squashing
---
> system.cpu2.fetch.icacheStallCycles 28975 # Number of cycles fetch is stalled on an Icache miss
> system.cpu2.fetch.Insts 310103 # Number of instructions fetch has processed
> system.cpu2.fetch.Branches 55489 # Number of branches that fetch encountered
> system.cpu2.fetch.predictedBranches 48126 # Number of branches that fetch has predicted taken
> system.cpu2.fetch.Cycles 128617 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu2.fetch.SquashCycles 2701 # Number of cycles fetch has spent squashing
1350,1355c1350,1355
< system.cpu2.fetch.PendingTrapStallCycles 1157 # Number of stall cycles due to pending traps
< system.cpu2.fetch.CacheLines 27680 # Number of cache lines fetched
< system.cpu2.fetch.IcacheSquashes 445 # Number of outstanding Icache misses that were squashed
< system.cpu2.fetch.rateDist::samples 159581 # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::mean 1.419893 # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::stdev 2.036694 # Number of instructions fetched each cycle (Total)
---
> system.cpu2.fetch.PendingTrapStallCycles 1166 # Number of stall cycles due to pending traps
> system.cpu2.fetch.CacheLines 20027 # Number of cache lines fetched
> system.cpu2.fetch.IcacheSquashes 452 # Number of outstanding Icache misses that were squashed
> system.cpu2.fetch.rateDist::samples 160121 # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::mean 1.936679 # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::stdev 2.215928 # Number of instructions fetched each cycle (Total)
1357,1365c1357,1365
< system.cpu2.fetch.rateDist::0 73772 46.23% 46.23% # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::1 45044 28.23% 74.45% # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::2 9695 6.08% 80.53% # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::3 3476 2.18% 82.71% # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::4 968 0.61% 83.32% # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::5 20661 12.95% 96.26% # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::6 1186 0.74% 97.01% # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::7 799 0.50% 97.51% # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::8 3980 2.49% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu2.fetch.rateDist::0 52703 32.91% 32.91% # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::1 53972 33.71% 66.62% # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::2 5883 3.67% 70.30% # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::3 3530 2.20% 72.50% # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::4 955 0.60% 73.10% # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::5 37143 23.20% 96.29% # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::6 1222 0.76% 97.06% # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::7 796 0.50% 97.55% # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::8 3917 2.45% 100.00% # Number of instructions fetched each cycle (Total)
1369,1409c1369,1409
< system.cpu2.fetch.rateDist::total 159581 # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.branchRate 0.266375 # Number of branch fetches per cycle
< system.cpu2.fetch.rate 1.407589 # Number of inst fetches per cycle
< system.cpu2.decode.IdleCycles 17760 # Number of cycles decode is idle
< system.cpu2.decode.BlockedCycles 80804 # Number of cycles decode is blocked
< system.cpu2.decode.RunCycles 54882 # Number of cycles decode is running
< system.cpu2.decode.UnblockCycles 4787 # Number of cycles decode is unblocking
< system.cpu2.decode.SquashCycles 1338 # Number of cycles decode is squashing
< system.cpu2.decode.DecodedInsts 211151 # Number of instructions handled by decode
< system.cpu2.rename.SquashCycles 1338 # Number of cycles rename is squashing
< system.cpu2.rename.IdleCycles 18439 # Number of cycles rename is idle
< system.cpu2.rename.BlockCycles 40468 # Number of cycles rename is blocking
< system.cpu2.rename.serializeStallCycles 13548 # count of cycles rename stalled for serializing inst
< system.cpu2.rename.RunCycles 56825 # Number of cycles rename is running
< system.cpu2.rename.UnblockCycles 28953 # Number of cycles rename is unblocking
< system.cpu2.rename.RenamedInsts 208031 # Number of instructions processed by rename
< system.cpu2.rename.IQFullEvents 26065 # Number of times rename has blocked due to IQ full
< system.cpu2.rename.LQFullEvents 14 # Number of times rename has blocked due to LQ full
< system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers
< system.cpu2.rename.RenamedOperands 143630 # Number of destination operands rename has renamed
< system.cpu2.rename.RenameLookups 381000 # Number of register rename lookups that rename has made
< system.cpu2.rename.int_rename_lookups 300757 # Number of integer rename lookups
< system.cpu2.rename.CommittedMaps 129882 # Number of HB maps that are committed
< system.cpu2.rename.UndoneMaps 13748 # Number of HB maps that are undone due to squashing
< system.cpu2.rename.serializingInsts 1193 # count of serializing insts renamed
< system.cpu2.rename.tempSerializingInsts 1262 # count of temporary serializing insts renamed
< system.cpu2.rename.skidInsts 33404 # count of insts added to the skid buffer
< system.cpu2.memDep0.insertedLoads 53977 # Number of loads inserted to the mem dependence unit.
< system.cpu2.memDep0.insertedStores 23458 # Number of stores inserted to the mem dependence unit.
< system.cpu2.memDep0.conflictingLoads 26723 # Number of conflicting loads.
< system.cpu2.memDep0.conflictingStores 18373 # Number of conflicting stores.
< system.cpu2.iq.iqInstsAdded 168634 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu2.iq.iqNonSpecInstsAdded 9408 # Number of non-speculative instructions added to the IQ
< system.cpu2.iq.iqInstsIssued 173236 # Number of instructions issued
< system.cpu2.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued
< system.cpu2.iq.iqSquashedInstsExamined 12983 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu2.iq.iqSquashedOperandsExamined 10808 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu2.iq.iqSquashedNonSpecRemoved 781 # Number of squashed non-spec instructions that were removed
< system.cpu2.iq.issued_per_cycle::samples 159581 # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::mean 1.085568 # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::stdev 1.335871 # Number of insts issued each cycle
---
> system.cpu2.fetch.rateDist::total 160121 # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.branchRate 0.341911 # Number of branch fetches per cycle
> system.cpu2.fetch.rate 1.910784 # Number of inst fetches per cycle
> system.cpu2.decode.IdleCycles 17197 # Number of cycles decode is idle
> system.cpu2.decode.BlockedCycles 51483 # Number of cycles decode is blocked
> system.cpu2.decode.RunCycles 87022 # Number of cycles decode is running
> system.cpu2.decode.UnblockCycles 3059 # Number of cycles decode is unblocking
> system.cpu2.decode.SquashCycles 1350 # Number of cycles decode is squashing
> system.cpu2.decode.DecodedInsts 295507 # Number of instructions handled by decode
> system.cpu2.rename.SquashCycles 1350 # Number of cycles rename is squashing
> system.cpu2.rename.IdleCycles 17911 # Number of cycles rename is idle
> system.cpu2.rename.BlockCycles 22825 # Number of cycles rename is blocking
> system.cpu2.rename.serializeStallCycles 13935 # count of cycles rename stalled for serializing inst
> system.cpu2.rename.RunCycles 88104 # Number of cycles rename is running
> system.cpu2.rename.UnblockCycles 15986 # Number of cycles rename is unblocking
> system.cpu2.rename.RenamedInsts 292291 # Number of instructions processed by rename
> system.cpu2.rename.IQFullEvents 14001 # Number of times rename has blocked due to IQ full
> system.cpu2.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full
> system.cpu2.rename.FullRegisterEvents 3 # Number of times there has been no free registers
> system.cpu2.rename.RenamedOperands 205997 # Number of destination operands rename has renamed
> system.cpu2.rename.RenameLookups 564188 # Number of register rename lookups that rename has made
> system.cpu2.rename.int_rename_lookups 438175 # Number of integer rename lookups
> system.cpu2.rename.CommittedMaps 191932 # Number of HB maps that are committed
> system.cpu2.rename.UndoneMaps 14065 # Number of HB maps that are undone due to squashing
> system.cpu2.rename.serializingInsts 1173 # count of serializing insts renamed
> system.cpu2.rename.tempSerializingInsts 1240 # count of temporary serializing insts renamed
> system.cpu2.rename.skidInsts 20395 # count of insts added to the skid buffer
> system.cpu2.memDep0.insertedLoads 83226 # Number of loads inserted to the mem dependence unit.
> system.cpu2.memDep0.insertedStores 39943 # Number of stores inserted to the mem dependence unit.
> system.cpu2.memDep0.conflictingLoads 39492 # Number of conflicting loads.
> system.cpu2.memDep0.conflictingStores 34851 # Number of conflicting stores.
> system.cpu2.iq.iqInstsAdded 243755 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu2.iq.iqNonSpecInstsAdded 5682 # Number of non-speculative instructions added to the IQ
> system.cpu2.iq.iqInstsIssued 244785 # Number of instructions issued
> system.cpu2.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued
> system.cpu2.iq.iqSquashedInstsExamined 13094 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu2.iq.iqSquashedOperandsExamined 10962 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu2.iq.iqSquashedNonSpecRemoved 644 # Number of squashed non-spec instructions that were removed
> system.cpu2.iq.issued_per_cycle::samples 160121 # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::mean 1.528750 # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::stdev 1.374157 # Number of insts issued each cycle
1411,1419c1411,1419
< system.cpu2.iq.issued_per_cycle::0 77748 48.72% 48.72% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::1 30232 18.94% 67.66% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::2 22868 14.33% 81.99% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::3 22470 14.08% 96.08% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::4 3364 2.11% 98.18% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::5 1606 1.01% 99.19% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::6 879 0.55% 99.74% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::7 214 0.13% 99.87% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::8 200 0.13% 100.00% # Number of insts issued each cycle
---
> system.cpu2.iq.issued_per_cycle::0 56124 35.05% 35.05% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::1 19550 12.21% 47.26% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::2 39272 24.53% 71.79% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::3 38854 24.27% 96.05% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::4 3402 2.12% 98.18% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::5 1615 1.01% 99.19% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::6 887 0.55% 99.74% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::7 212 0.13% 99.87% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::8 205 0.13% 100.00% # Number of insts issued each cycle
1423c1423
< system.cpu2.iq.issued_per_cycle::total 159581 # Number of insts issued each cycle
---
> system.cpu2.iq.issued_per_cycle::total 160121 # Number of insts issued each cycle
1425,1455c1425,1455
< system.cpu2.iq.fu_full::IntAlu 79 23.94% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::IntMult 0 0.00% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.94% # attempts to use FU when none available
< system.cpu2.iq.fu_full::MemRead 42 12.73% 36.67% # attempts to use FU when none available
< system.cpu2.iq.fu_full::MemWrite 209 63.33% 100.00% # attempts to use FU when none available
---
> system.cpu2.iq.fu_full::IntAlu 80 23.32% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::IntMult 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.32% # attempts to use FU when none available
> system.cpu2.iq.fu_full::MemRead 54 15.74% 39.07% # attempts to use FU when none available
> system.cpu2.iq.fu_full::MemWrite 209 60.93% 100.00% # attempts to use FU when none available
1459,1489c1459,1489
< system.cpu2.iq.FU_type_0::IntAlu 89318 51.56% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::IntMult 0 0.00% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.56% # Type of FU issued
< system.cpu2.iq.FU_type_0::MemRead 61054 35.24% 86.80% # Type of FU issued
< system.cpu2.iq.FU_type_0::MemWrite 22864 13.20% 100.00% # Type of FU issued
---
> system.cpu2.iq.FU_type_0::IntAlu 118682 48.48% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.48% # Type of FU issued
> system.cpu2.iq.FU_type_0::MemRead 86809 35.46% 83.95% # Type of FU issued
> system.cpu2.iq.FU_type_0::MemWrite 39294 16.05% 100.00% # Type of FU issued
1492,1498c1492,1498
< system.cpu2.iq.FU_type_0::total 173236 # Type of FU issued
< system.cpu2.iq.rate 1.076160 # Inst issue rate
< system.cpu2.iq.fu_busy_cnt 330 # FU busy when requested
< system.cpu2.iq.fu_busy_rate 0.001905 # FU busy rate (busy events/executed inst)
< system.cpu2.iq.int_inst_queue_reads 506398 # Number of integer instruction queue reads
< system.cpu2.iq.int_inst_queue_writes 191064 # Number of integer instruction queue writes
< system.cpu2.iq.int_inst_queue_wakeup_accesses 171727 # Number of integer instruction queue wakeup accesses
---
> system.cpu2.iq.FU_type_0::total 244785 # Type of FU issued
> system.cpu2.iq.rate 1.508309 # Inst issue rate
> system.cpu2.iq.fu_busy_cnt 343 # FU busy when requested
> system.cpu2.iq.fu_busy_rate 0.001401 # FU busy rate (busy events/executed inst)
> system.cpu2.iq.int_inst_queue_reads 650053 # Number of integer instruction queue reads
> system.cpu2.iq.int_inst_queue_writes 262570 # Number of integer instruction queue writes
> system.cpu2.iq.int_inst_queue_wakeup_accesses 243225 # Number of integer instruction queue wakeup accesses
1502c1502
< system.cpu2.iq.int_alu_accesses 173566 # Number of integer alu accesses
---
> system.cpu2.iq.int_alu_accesses 245128 # Number of integer alu accesses
1504c1504
< system.cpu2.iew.lsq.thread0.forwLoads 18193 # Number of loads that had data forwarded from stores
---
> system.cpu2.iew.lsq.thread0.forwLoads 34614 # Number of loads that had data forwarded from stores
1506c1506
< system.cpu2.iew.lsq.thread0.squashedLoads 2642 # Number of loads squashed
---
> system.cpu2.iew.lsq.thread0.squashedLoads 2656 # Number of loads squashed
1509c1509
< system.cpu2.iew.lsq.thread0.squashedStores 1482 # Number of stores squashed
---
> system.cpu2.iew.lsq.thread0.squashedStores 1565 # Number of stores squashed
1515,1523c1515,1523
< system.cpu2.iew.iewSquashCycles 1338 # Number of cycles IEW is squashing
< system.cpu2.iew.iewBlockCycles 10563 # Number of cycles IEW is blocking
< system.cpu2.iew.iewUnblockCycles 81 # Number of cycles IEW is unblocking
< system.cpu2.iew.iewDispatchedInsts 205567 # Number of instructions dispatched to IQ
< system.cpu2.iew.iewDispSquashedInsts 184 # Number of squashed instructions skipped by dispatch
< system.cpu2.iew.iewDispLoadInsts 53977 # Number of dispatched load instructions
< system.cpu2.iew.iewDispStoreInsts 23458 # Number of dispatched store instructions
< system.cpu2.iew.iewDispNonSpecInsts 1137 # Number of dispatched non-speculative instructions
< system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall
---
> system.cpu2.iew.iewSquashCycles 1350 # Number of cycles IEW is squashing
> system.cpu2.iew.iewBlockCycles 6752 # Number of cycles IEW is blocking
> system.cpu2.iew.iewUnblockCycles 63 # Number of cycles IEW is unblocking
> system.cpu2.iew.iewDispatchedInsts 289758 # Number of instructions dispatched to IQ
> system.cpu2.iew.iewDispSquashedInsts 176 # Number of squashed instructions skipped by dispatch
> system.cpu2.iew.iewDispLoadInsts 83226 # Number of dispatched load instructions
> system.cpu2.iew.iewDispStoreInsts 39943 # Number of dispatched store instructions
> system.cpu2.iew.iewDispNonSpecInsts 1125 # Number of dispatched non-speculative instructions
> system.cpu2.iew.iewIQFullEvents 41 # Number of times the IQ has become full, causing a stall
1526,1531c1526,1531
< system.cpu2.iew.predictedTakenIncorrect 430 # Number of branches that were predicted taken incorrectly
< system.cpu2.iew.predictedNotTakenIncorrect 1053 # Number of branches that were predicted not taken incorrectly
< system.cpu2.iew.branchMispredicts 1483 # Number of branch mispredicts detected at execute
< system.cpu2.iew.iewExecutedInsts 172231 # Number of executed instructions
< system.cpu2.iew.iewExecLoadInsts 52840 # Number of load instructions executed
< system.cpu2.iew.iewExecSquashedInsts 1005 # Number of squashed instructions skipped in execute
---
> system.cpu2.iew.predictedTakenIncorrect 446 # Number of branches that were predicted taken incorrectly
> system.cpu2.iew.predictedNotTakenIncorrect 1057 # Number of branches that were predicted not taken incorrectly
> system.cpu2.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute
> system.cpu2.iew.iewExecutedInsts 243760 # Number of executed instructions
> system.cpu2.iew.iewExecLoadInsts 82166 # Number of load instructions executed
> system.cpu2.iew.iewExecSquashedInsts 1025 # Number of squashed instructions skipped in execute
1533,1541c1533,1541
< system.cpu2.iew.exec_nop 27525 # number of nop insts executed
< system.cpu2.iew.exec_refs 75615 # number of memory reference insts executed
< system.cpu2.iew.exec_branches 36863 # Number of branches executed
< system.cpu2.iew.exec_stores 22775 # Number of stores executed
< system.cpu2.iew.exec_rate 1.069917 # Inst execution rate
< system.cpu2.iew.wb_sent 171997 # cumulative count of insts sent to commit
< system.cpu2.iew.wb_count 171727 # cumulative count of insts written-back
< system.cpu2.iew.wb_producers 93200 # num instructions producing a value
< system.cpu2.iew.wb_consumers 99800 # num instructions consuming a value
---
> system.cpu2.iew.exec_nop 40321 # number of nop insts executed
> system.cpu2.iew.exec_refs 121366 # number of memory reference insts executed
> system.cpu2.iew.exec_branches 49723 # Number of branches executed
> system.cpu2.iew.exec_stores 39200 # Number of stores executed
> system.cpu2.iew.exec_rate 1.501993 # Inst execution rate
> system.cpu2.iew.wb_sent 243514 # cumulative count of insts sent to commit
> system.cpu2.iew.wb_count 243225 # cumulative count of insts written-back
> system.cpu2.iew.wb_producers 138958 # num instructions producing a value
> system.cpu2.iew.wb_consumers 145563 # num instructions consuming a value
1543,1544c1543,1544
< system.cpu2.iew.wb_rate 1.066786 # insts written-back per cycle
< system.cpu2.iew.wb_fanout 0.933868 # average fanout of values written-back
---
> system.cpu2.iew.wb_rate 1.498697 # insts written-back per cycle
> system.cpu2.iew.wb_fanout 0.954624 # average fanout of values written-back
1546,1551c1546,1551
< system.cpu2.commit.commitSquashedInsts 13823 # The number of squashed insts skipped by commit
< system.cpu2.commit.commitNonSpecStalls 8627 # The number of times commit has been forced to stall to communicate backwards
< system.cpu2.commit.branchMispredicts 1259 # The number of times a branch was mispredicted
< system.cpu2.commit.committed_per_cycle::samples 157016 # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::mean 1.220837 # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::stdev 1.865055 # Number of insts commited each cycle
---
> system.cpu2.commit.commitSquashedInsts 13911 # The number of squashed insts skipped by commit
> system.cpu2.commit.commitNonSpecStalls 5038 # The number of times commit has been forced to stall to communicate backwards
> system.cpu2.commit.branchMispredicts 1272 # The number of times a branch was mispredicted
> system.cpu2.commit.committed_per_cycle::samples 157537 # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::mean 1.750713 # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::stdev 2.089801 # Number of insts commited each cycle
1553,1561c1553,1561
< system.cpu2.commit.committed_per_cycle::0 86039 54.80% 54.80% # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::1 33434 21.29% 76.09% # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::2 5238 3.34% 79.43% # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::3 9429 6.01% 85.43% # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::4 1533 0.98% 86.41% # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::5 18255 11.63% 98.03% # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::6 831 0.53% 98.56% # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::7 955 0.61% 99.17% # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::8 1302 0.83% 100.00% # Number of insts commited each cycle
---
> system.cpu2.commit.committed_per_cycle::0 60893 38.65% 38.65% # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::1 46269 29.37% 68.02% # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::2 5250 3.33% 71.36% # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::3 5861 3.72% 75.08% # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::4 1535 0.97% 76.05% # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::5 34623 21.98% 98.03% # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::6 855 0.54% 98.57% # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::7 943 0.60% 99.17% # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::8 1308 0.83% 100.00% # Number of insts commited each cycle
1565,1567c1565,1567
< system.cpu2.commit.committed_per_cycle::total 157016 # Number of insts commited each cycle
< system.cpu2.commit.committedInsts 191691 # Number of instructions committed
< system.cpu2.commit.committedOps 191691 # Number of ops (including micro ops) committed
---
> system.cpu2.commit.committed_per_cycle::total 157537 # Number of insts commited each cycle
> system.cpu2.commit.committedInsts 275802 # Number of instructions committed
> system.cpu2.commit.committedOps 275802 # Number of ops (including micro ops) committed
1569,1572c1569,1572
< system.cpu2.commit.refs 73311 # Number of memory references committed
< system.cpu2.commit.loads 51335 # Number of loads committed
< system.cpu2.commit.membars 7910 # Number of memory barriers committed
< system.cpu2.commit.branches 35845 # Number of branches committed
---
> system.cpu2.commit.refs 118948 # Number of memory references committed
> system.cpu2.commit.loads 80570 # Number of loads committed
> system.cpu2.commit.membars 4324 # Number of memory barriers committed
> system.cpu2.commit.branches 48669 # Number of branches committed
1574c1574
< system.cpu2.commit.int_insts 131277 # Number of committed integer instructions.
---
> system.cpu2.commit.int_insts 189737 # Number of committed integer instructions.
1576,1607c1576,1607
< system.cpu2.commit.op_class_0::No_OpClass 26632 13.89% 13.89% # Class of committed instruction
< system.cpu2.commit.op_class_0::IntAlu 83838 43.74% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::IntMult 0 0.00% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::IntDiv 0 0.00% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::FloatMult 0 0.00% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdMult 0 0.00% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdShift 0 0.00% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 57.63% # Class of committed instruction
< system.cpu2.commit.op_class_0::MemRead 59245 30.91% 88.54% # Class of committed instruction
< system.cpu2.commit.op_class_0::MemWrite 21976 11.46% 100.00% # Class of committed instruction
---
> system.cpu2.commit.op_class_0::No_OpClass 39459 14.31% 14.31% # Class of committed instruction
> system.cpu2.commit.op_class_0::IntAlu 113071 41.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.30% # Class of committed instruction
> system.cpu2.commit.op_class_0::MemRead 84894 30.78% 86.08% # Class of committed instruction
> system.cpu2.commit.op_class_0::MemWrite 38378 13.92% 100.00% # Class of committed instruction
1610,1615c1610,1615
< system.cpu2.commit.op_class_0::total 191691 # Class of committed instruction
< system.cpu2.commit.bw_lim_events 1302 # number cycles where commit BW limit reached
< system.cpu2.rob.rob_reads 360642 # The number of ROB reads
< system.cpu2.rob.rob_writes 413593 # The number of ROB writes
< system.cpu2.timesIdled 204 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu2.idleCycles 1395 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu2.commit.op_class_0::total 275802 # Class of committed instruction
> system.cpu2.commit.bw_lim_events 1308 # number cycles where commit BW limit reached
> system.cpu2.rob.rob_reads 445356 # The number of ROB reads
> system.cpu2.rob.rob_writes 582010 # The number of ROB writes
> system.cpu2.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu2.idleCycles 2170 # Total number of cycles that the CPU has spent unscheduled due to idling
1617,1624c1617,1624
< system.cpu2.committedInsts 157149 # Number of Instructions Simulated
< system.cpu2.committedOps 157149 # Number of Ops (including micro ops) Simulated
< system.cpu2.cpi 1.024353 # CPI: Cycles Per Instruction
< system.cpu2.cpi_total 1.024353 # CPI: Total CPI of All Threads
< system.cpu2.ipc 0.976226 # IPC: Instructions Per Cycle
< system.cpu2.ipc_total 0.976226 # IPC: Total IPC of All Threads
< system.cpu2.int_regfile_reads 286558 # number of integer regfile reads
< system.cpu2.int_regfile_writes 135654 # number of integer regfile writes
---
> system.cpu2.committedInsts 232019 # Number of Instructions Simulated
> system.cpu2.committedOps 232019 # Number of Ops (including micro ops) Simulated
> system.cpu2.cpi 0.699473 # CPI: Cycles Per Instruction
> system.cpu2.cpi_total 0.699473 # CPI: Total CPI of All Threads
> system.cpu2.ipc 1.429648 # IPC: Instructions Per Cycle
> system.cpu2.ipc_total 1.429648 # IPC: Total IPC of All Threads
> system.cpu2.int_regfile_reads 423842 # number of integer regfile reads
> system.cpu2.int_regfile_writes 197927 # number of integer regfile writes
1626c1626
< system.cpu2.misc_regfile_reads 77226 # number of misc regfile reads
---
> system.cpu2.misc_regfile_reads 122993 # number of misc regfile reads
1629,1630c1629,1630
< system.cpu2.dcache.tags.tagsinuse 23.071332 # Cycle average of tags in use
< system.cpu2.dcache.tags.total_refs 27978 # Total number of references to valid blocks.
---
> system.cpu2.dcache.tags.tagsinuse 24.276146 # Cycle average of tags in use
> system.cpu2.dcache.tags.total_refs 44407 # Total number of references to valid blocks.
1632c1632
< system.cpu2.dcache.tags.avg_refs 999.214286 # Average number of references to valid blocks.
---
> system.cpu2.dcache.tags.avg_refs 1585.964286 # Average number of references to valid blocks.
1634,1636c1634,1636
< system.cpu2.dcache.tags.occ_blocks::cpu2.data 23.071332 # Average occupied blocks per requestor
< system.cpu2.dcache.tags.occ_percent::cpu2.data 0.045061 # Average percentage of cache occupancy
< system.cpu2.dcache.tags.occ_percent::total 0.045061 # Average percentage of cache occupancy
---
> system.cpu2.dcache.tags.occ_blocks::cpu2.data 24.276146 # Average occupied blocks per requestor
> system.cpu2.dcache.tags.occ_percent::cpu2.data 0.047414 # Average percentage of cache occupancy
> system.cpu2.dcache.tags.occ_percent::total 0.047414 # Average percentage of cache occupancy
1640,1701c1640,1701
< system.cpu2.dcache.tags.tag_accesses 226658 # Number of tag accesses
< system.cpu2.dcache.tags.data_accesses 226658 # Number of data accesses
< system.cpu2.dcache.ReadReq_hits::cpu2.data 34141 # number of ReadReq hits
< system.cpu2.dcache.ReadReq_hits::total 34141 # number of ReadReq hits
< system.cpu2.dcache.WriteReq_hits::cpu2.data 21749 # number of WriteReq hits
< system.cpu2.dcache.WriteReq_hits::total 21749 # number of WriteReq hits
< system.cpu2.dcache.SwapReq_hits::cpu2.data 19 # number of SwapReq hits
< system.cpu2.dcache.SwapReq_hits::total 19 # number of SwapReq hits
< system.cpu2.dcache.demand_hits::cpu2.data 55890 # number of demand (read+write) hits
< system.cpu2.dcache.demand_hits::total 55890 # number of demand (read+write) hits
< system.cpu2.dcache.overall_hits::cpu2.data 55890 # number of overall hits
< system.cpu2.dcache.overall_hits::total 55890 # number of overall hits
< system.cpu2.dcache.ReadReq_misses::cpu2.data 483 # number of ReadReq misses
< system.cpu2.dcache.ReadReq_misses::total 483 # number of ReadReq misses
< system.cpu2.dcache.WriteReq_misses::cpu2.data 156 # number of WriteReq misses
< system.cpu2.dcache.WriteReq_misses::total 156 # number of WriteReq misses
< system.cpu2.dcache.SwapReq_misses::cpu2.data 52 # number of SwapReq misses
< system.cpu2.dcache.SwapReq_misses::total 52 # number of SwapReq misses
< system.cpu2.dcache.demand_misses::cpu2.data 639 # number of demand (read+write) misses
< system.cpu2.dcache.demand_misses::total 639 # number of demand (read+write) misses
< system.cpu2.dcache.overall_misses::cpu2.data 639 # number of overall misses
< system.cpu2.dcache.overall_misses::total 639 # number of overall misses
< system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7783500 # number of ReadReq miss cycles
< system.cpu2.dcache.ReadReq_miss_latency::total 7783500 # number of ReadReq miss cycles
< system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3187000 # number of WriteReq miss cycles
< system.cpu2.dcache.WriteReq_miss_latency::total 3187000 # number of WriteReq miss cycles
< system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 671500 # number of SwapReq miss cycles
< system.cpu2.dcache.SwapReq_miss_latency::total 671500 # number of SwapReq miss cycles
< system.cpu2.dcache.demand_miss_latency::cpu2.data 10970500 # number of demand (read+write) miss cycles
< system.cpu2.dcache.demand_miss_latency::total 10970500 # number of demand (read+write) miss cycles
< system.cpu2.dcache.overall_miss_latency::cpu2.data 10970500 # number of overall miss cycles
< system.cpu2.dcache.overall_miss_latency::total 10970500 # number of overall miss cycles
< system.cpu2.dcache.ReadReq_accesses::cpu2.data 34624 # number of ReadReq accesses(hits+misses)
< system.cpu2.dcache.ReadReq_accesses::total 34624 # number of ReadReq accesses(hits+misses)
< system.cpu2.dcache.WriteReq_accesses::cpu2.data 21905 # number of WriteReq accesses(hits+misses)
< system.cpu2.dcache.WriteReq_accesses::total 21905 # number of WriteReq accesses(hits+misses)
< system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses)
< system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
< system.cpu2.dcache.demand_accesses::cpu2.data 56529 # number of demand (read+write) accesses
< system.cpu2.dcache.demand_accesses::total 56529 # number of demand (read+write) accesses
< system.cpu2.dcache.overall_accesses::cpu2.data 56529 # number of overall (read+write) accesses
< system.cpu2.dcache.overall_accesses::total 56529 # number of overall (read+write) accesses
< system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.013950 # miss rate for ReadReq accesses
< system.cpu2.dcache.ReadReq_miss_rate::total 0.013950 # miss rate for ReadReq accesses
< system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007122 # miss rate for WriteReq accesses
< system.cpu2.dcache.WriteReq_miss_rate::total 0.007122 # miss rate for WriteReq accesses
< system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.732394 # miss rate for SwapReq accesses
< system.cpu2.dcache.SwapReq_miss_rate::total 0.732394 # miss rate for SwapReq accesses
< system.cpu2.dcache.demand_miss_rate::cpu2.data 0.011304 # miss rate for demand accesses
< system.cpu2.dcache.demand_miss_rate::total 0.011304 # miss rate for demand accesses
< system.cpu2.dcache.overall_miss_rate::cpu2.data 0.011304 # miss rate for overall accesses
< system.cpu2.dcache.overall_miss_rate::total 0.011304 # miss rate for overall accesses
< system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16114.906832 # average ReadReq miss latency
< system.cpu2.dcache.ReadReq_avg_miss_latency::total 16114.906832 # average ReadReq miss latency
< system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20429.487179 # average WriteReq miss latency
< system.cpu2.dcache.WriteReq_avg_miss_latency::total 20429.487179 # average WriteReq miss latency
< system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 12913.461538 # average SwapReq miss latency
< system.cpu2.dcache.SwapReq_avg_miss_latency::total 12913.461538 # average SwapReq miss latency
< system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17168.231612 # average overall miss latency
< system.cpu2.dcache.demand_avg_miss_latency::total 17168.231612 # average overall miss latency
< system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17168.231612 # average overall miss latency
< system.cpu2.dcache.overall_avg_miss_latency::total 17168.231612 # average overall miss latency
---
> system.cpu2.dcache.tags.tag_accesses 343879 # Number of tag accesses
> system.cpu2.dcache.tags.data_accesses 343879 # Number of data accesses
> system.cpu2.dcache.ReadReq_hits::cpu2.data 47002 # number of ReadReq hits
> system.cpu2.dcache.ReadReq_hits::total 47002 # number of ReadReq hits
> system.cpu2.dcache.WriteReq_hits::cpu2.data 38151 # number of WriteReq hits
> system.cpu2.dcache.WriteReq_hits::total 38151 # number of WriteReq hits
> system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits
> system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits
> system.cpu2.dcache.demand_hits::cpu2.data 85153 # number of demand (read+write) hits
> system.cpu2.dcache.demand_hits::total 85153 # number of demand (read+write) hits
> system.cpu2.dcache.overall_hits::cpu2.data 85153 # number of overall hits
> system.cpu2.dcache.overall_hits::total 85153 # number of overall hits
> system.cpu2.dcache.ReadReq_misses::cpu2.data 527 # number of ReadReq misses
> system.cpu2.dcache.ReadReq_misses::total 527 # number of ReadReq misses
> system.cpu2.dcache.WriteReq_misses::cpu2.data 159 # number of WriteReq misses
> system.cpu2.dcache.WriteReq_misses::total 159 # number of WriteReq misses
> system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses
> system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses
> system.cpu2.dcache.demand_misses::cpu2.data 686 # number of demand (read+write) misses
> system.cpu2.dcache.demand_misses::total 686 # number of demand (read+write) misses
> system.cpu2.dcache.overall_misses::cpu2.data 686 # number of overall misses
> system.cpu2.dcache.overall_misses::total 686 # number of overall misses
> system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 9963000 # number of ReadReq miss cycles
> system.cpu2.dcache.ReadReq_miss_latency::total 9963000 # number of ReadReq miss cycles
> system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 4178000 # number of WriteReq miss cycles
> system.cpu2.dcache.WriteReq_miss_latency::total 4178000 # number of WriteReq miss cycles
> system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 670500 # number of SwapReq miss cycles
> system.cpu2.dcache.SwapReq_miss_latency::total 670500 # number of SwapReq miss cycles
> system.cpu2.dcache.demand_miss_latency::cpu2.data 14141000 # number of demand (read+write) miss cycles
> system.cpu2.dcache.demand_miss_latency::total 14141000 # number of demand (read+write) miss cycles
> system.cpu2.dcache.overall_miss_latency::cpu2.data 14141000 # number of overall miss cycles
> system.cpu2.dcache.overall_miss_latency::total 14141000 # number of overall miss cycles
> system.cpu2.dcache.ReadReq_accesses::cpu2.data 47529 # number of ReadReq accesses(hits+misses)
> system.cpu2.dcache.ReadReq_accesses::total 47529 # number of ReadReq accesses(hits+misses)
> system.cpu2.dcache.WriteReq_accesses::cpu2.data 38310 # number of WriteReq accesses(hits+misses)
> system.cpu2.dcache.WriteReq_accesses::total 38310 # number of WriteReq accesses(hits+misses)
> system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses)
> system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses)
> system.cpu2.dcache.demand_accesses::cpu2.data 85839 # number of demand (read+write) accesses
> system.cpu2.dcache.demand_accesses::total 85839 # number of demand (read+write) accesses
> system.cpu2.dcache.overall_accesses::cpu2.data 85839 # number of overall (read+write) accesses
> system.cpu2.dcache.overall_accesses::total 85839 # number of overall (read+write) accesses
> system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.011088 # miss rate for ReadReq accesses
> system.cpu2.dcache.ReadReq_miss_rate::total 0.011088 # miss rate for ReadReq accesses
> system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004150 # miss rate for WriteReq accesses
> system.cpu2.dcache.WriteReq_miss_rate::total 0.004150 # miss rate for WriteReq accesses
> system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.823529 # miss rate for SwapReq accesses
> system.cpu2.dcache.SwapReq_miss_rate::total 0.823529 # miss rate for SwapReq accesses
> system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007992 # miss rate for demand accesses
> system.cpu2.dcache.demand_miss_rate::total 0.007992 # miss rate for demand accesses
> system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007992 # miss rate for overall accesses
> system.cpu2.dcache.overall_miss_rate::total 0.007992 # miss rate for overall accesses
> system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 18905.123340 # average ReadReq miss latency
> system.cpu2.dcache.ReadReq_avg_miss_latency::total 18905.123340 # average ReadReq miss latency
> system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 26276.729560 # average WriteReq miss latency
> system.cpu2.dcache.WriteReq_avg_miss_latency::total 26276.729560 # average WriteReq miss latency
> system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 11973.214286 # average SwapReq miss latency
> system.cpu2.dcache.SwapReq_avg_miss_latency::total 11973.214286 # average SwapReq miss latency
> system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 20613.702624 # average overall miss latency
> system.cpu2.dcache.demand_avg_miss_latency::total 20613.702624 # average overall miss latency
> system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 20613.702624 # average overall miss latency
> system.cpu2.dcache.overall_avg_miss_latency::total 20613.702624 # average overall miss latency
1710,1757c1710,1757
< system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 311 # number of ReadReq MSHR hits
< system.cpu2.dcache.ReadReq_mshr_hits::total 311 # number of ReadReq MSHR hits
< system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 53 # number of WriteReq MSHR hits
< system.cpu2.dcache.WriteReq_mshr_hits::total 53 # number of WriteReq MSHR hits
< system.cpu2.dcache.demand_mshr_hits::cpu2.data 364 # number of demand (read+write) MSHR hits
< system.cpu2.dcache.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits
< system.cpu2.dcache.overall_mshr_hits::cpu2.data 364 # number of overall MSHR hits
< system.cpu2.dcache.overall_mshr_hits::total 364 # number of overall MSHR hits
< system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 172 # number of ReadReq MSHR misses
< system.cpu2.dcache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses
< system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 103 # number of WriteReq MSHR misses
< system.cpu2.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses
< system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 52 # number of SwapReq MSHR misses
< system.cpu2.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses
< system.cpu2.dcache.demand_mshr_misses::cpu2.data 275 # number of demand (read+write) MSHR misses
< system.cpu2.dcache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses
< system.cpu2.dcache.overall_mshr_misses::cpu2.data 275 # number of overall MSHR misses
< system.cpu2.dcache.overall_mshr_misses::total 275 # number of overall MSHR misses
< system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1811500 # number of ReadReq MSHR miss cycles
< system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1811500 # number of ReadReq MSHR miss cycles
< system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1702500 # number of WriteReq MSHR miss cycles
< system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1702500 # number of WriteReq MSHR miss cycles
< system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 619500 # number of SwapReq MSHR miss cycles
< system.cpu2.dcache.SwapReq_mshr_miss_latency::total 619500 # number of SwapReq MSHR miss cycles
< system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3514000 # number of demand (read+write) MSHR miss cycles
< system.cpu2.dcache.demand_mshr_miss_latency::total 3514000 # number of demand (read+write) MSHR miss cycles
< system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3514000 # number of overall MSHR miss cycles
< system.cpu2.dcache.overall_mshr_miss_latency::total 3514000 # number of overall MSHR miss cycles
< system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004968 # mshr miss rate for ReadReq accesses
< system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004968 # mshr miss rate for ReadReq accesses
< system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.004702 # mshr miss rate for WriteReq accesses
< system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.004702 # mshr miss rate for WriteReq accesses
< system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.732394 # mshr miss rate for SwapReq accesses
< system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.732394 # mshr miss rate for SwapReq accesses
< system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004865 # mshr miss rate for demand accesses
< system.cpu2.dcache.demand_mshr_miss_rate::total 0.004865 # mshr miss rate for demand accesses
< system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004865 # mshr miss rate for overall accesses
< system.cpu2.dcache.overall_mshr_miss_rate::total 0.004865 # mshr miss rate for overall accesses
< system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10531.976744 # average ReadReq mshr miss latency
< system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10531.976744 # average ReadReq mshr miss latency
< system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16529.126214 # average WriteReq mshr miss latency
< system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16529.126214 # average WriteReq mshr miss latency
< system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 11913.461538 # average SwapReq mshr miss latency
< system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 11913.461538 # average SwapReq mshr miss latency
< system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12778.181818 # average overall mshr miss latency
< system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12778.181818 # average overall mshr miss latency
< system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12778.181818 # average overall mshr miss latency
< system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12778.181818 # average overall mshr miss latency
---
> system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 367 # number of ReadReq MSHR hits
> system.cpu2.dcache.ReadReq_mshr_hits::total 367 # number of ReadReq MSHR hits
> system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 51 # number of WriteReq MSHR hits
> system.cpu2.dcache.WriteReq_mshr_hits::total 51 # number of WriteReq MSHR hits
> system.cpu2.dcache.demand_mshr_hits::cpu2.data 418 # number of demand (read+write) MSHR hits
> system.cpu2.dcache.demand_mshr_hits::total 418 # number of demand (read+write) MSHR hits
> system.cpu2.dcache.overall_mshr_hits::cpu2.data 418 # number of overall MSHR hits
> system.cpu2.dcache.overall_mshr_hits::total 418 # number of overall MSHR hits
> system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 160 # number of ReadReq MSHR misses
> system.cpu2.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses
> system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses
> system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses
> system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses
> system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses
> system.cpu2.dcache.demand_mshr_misses::cpu2.data 268 # number of demand (read+write) MSHR misses
> system.cpu2.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses
> system.cpu2.dcache.overall_mshr_misses::cpu2.data 268 # number of overall MSHR misses
> system.cpu2.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses
> system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1620500 # number of ReadReq MSHR miss cycles
> system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1620500 # number of ReadReq MSHR miss cycles
> system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2159500 # number of WriteReq MSHR miss cycles
> system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2159500 # number of WriteReq MSHR miss cycles
> system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 614500 # number of SwapReq MSHR miss cycles
> system.cpu2.dcache.SwapReq_mshr_miss_latency::total 614500 # number of SwapReq MSHR miss cycles
> system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3780000 # number of demand (read+write) MSHR miss cycles
> system.cpu2.dcache.demand_mshr_miss_latency::total 3780000 # number of demand (read+write) MSHR miss cycles
> system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3780000 # number of overall MSHR miss cycles
> system.cpu2.dcache.overall_mshr_miss_latency::total 3780000 # number of overall MSHR miss cycles
> system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003366 # mshr miss rate for ReadReq accesses
> system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003366 # mshr miss rate for ReadReq accesses
> system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002819 # mshr miss rate for WriteReq accesses
> system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002819 # mshr miss rate for WriteReq accesses
> system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.823529 # mshr miss rate for SwapReq accesses
> system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.823529 # mshr miss rate for SwapReq accesses
> system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003122 # mshr miss rate for demand accesses
> system.cpu2.dcache.demand_mshr_miss_rate::total 0.003122 # mshr miss rate for demand accesses
> system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003122 # mshr miss rate for overall accesses
> system.cpu2.dcache.overall_mshr_miss_rate::total 0.003122 # mshr miss rate for overall accesses
> system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10128.125000 # average ReadReq mshr miss latency
> system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10128.125000 # average ReadReq mshr miss latency
> system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19995.370370 # average WriteReq mshr miss latency
> system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19995.370370 # average WriteReq mshr miss latency
> system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 10973.214286 # average SwapReq mshr miss latency
> system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 10973.214286 # average SwapReq mshr miss latency
> system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14104.477612 # average overall mshr miss latency
> system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14104.477612 # average overall mshr miss latency
> system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14104.477612 # average overall mshr miss latency
> system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14104.477612 # average overall mshr miss latency
1760,1761c1760,1761
< system.cpu2.icache.tags.tagsinuse 77.667456 # Cycle average of tags in use
< system.cpu2.icache.tags.total_refs 27109 # Total number of references to valid blocks.
---
> system.cpu2.icache.tags.tagsinuse 80.953803 # Cycle average of tags in use
> system.cpu2.icache.tags.total_refs 19454 # Total number of references to valid blocks.
1763c1763
< system.cpu2.icache.tags.avg_refs 54.218000 # Average number of references to valid blocks.
---
> system.cpu2.icache.tags.avg_refs 38.908000 # Average number of references to valid blocks.
1765,1767c1765,1767
< system.cpu2.icache.tags.occ_blocks::cpu2.inst 77.667456 # Average occupied blocks per requestor
< system.cpu2.icache.tags.occ_percent::cpu2.inst 0.151694 # Average percentage of cache occupancy
< system.cpu2.icache.tags.occ_percent::total 0.151694 # Average percentage of cache occupancy
---
> system.cpu2.icache.tags.occ_blocks::cpu2.inst 80.953803 # Average occupied blocks per requestor
> system.cpu2.icache.tags.occ_percent::cpu2.inst 0.158113 # Average percentage of cache occupancy
> system.cpu2.icache.tags.occ_percent::total 0.158113 # Average percentage of cache occupancy
1772,1810c1772,1810
< system.cpu2.icache.tags.tag_accesses 28180 # Number of tag accesses
< system.cpu2.icache.tags.data_accesses 28180 # Number of data accesses
< system.cpu2.icache.ReadReq_hits::cpu2.inst 27109 # number of ReadReq hits
< system.cpu2.icache.ReadReq_hits::total 27109 # number of ReadReq hits
< system.cpu2.icache.demand_hits::cpu2.inst 27109 # number of demand (read+write) hits
< system.cpu2.icache.demand_hits::total 27109 # number of demand (read+write) hits
< system.cpu2.icache.overall_hits::cpu2.inst 27109 # number of overall hits
< system.cpu2.icache.overall_hits::total 27109 # number of overall hits
< system.cpu2.icache.ReadReq_misses::cpu2.inst 571 # number of ReadReq misses
< system.cpu2.icache.ReadReq_misses::total 571 # number of ReadReq misses
< system.cpu2.icache.demand_misses::cpu2.inst 571 # number of demand (read+write) misses
< system.cpu2.icache.demand_misses::total 571 # number of demand (read+write) misses
< system.cpu2.icache.overall_misses::cpu2.inst 571 # number of overall misses
< system.cpu2.icache.overall_misses::total 571 # number of overall misses
< system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7541500 # number of ReadReq miss cycles
< system.cpu2.icache.ReadReq_miss_latency::total 7541500 # number of ReadReq miss cycles
< system.cpu2.icache.demand_miss_latency::cpu2.inst 7541500 # number of demand (read+write) miss cycles
< system.cpu2.icache.demand_miss_latency::total 7541500 # number of demand (read+write) miss cycles
< system.cpu2.icache.overall_miss_latency::cpu2.inst 7541500 # number of overall miss cycles
< system.cpu2.icache.overall_miss_latency::total 7541500 # number of overall miss cycles
< system.cpu2.icache.ReadReq_accesses::cpu2.inst 27680 # number of ReadReq accesses(hits+misses)
< system.cpu2.icache.ReadReq_accesses::total 27680 # number of ReadReq accesses(hits+misses)
< system.cpu2.icache.demand_accesses::cpu2.inst 27680 # number of demand (read+write) accesses
< system.cpu2.icache.demand_accesses::total 27680 # number of demand (read+write) accesses
< system.cpu2.icache.overall_accesses::cpu2.inst 27680 # number of overall (read+write) accesses
< system.cpu2.icache.overall_accesses::total 27680 # number of overall (read+write) accesses
< system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.020629 # miss rate for ReadReq accesses
< system.cpu2.icache.ReadReq_miss_rate::total 0.020629 # miss rate for ReadReq accesses
< system.cpu2.icache.demand_miss_rate::cpu2.inst 0.020629 # miss rate for demand accesses
< system.cpu2.icache.demand_miss_rate::total 0.020629 # miss rate for demand accesses
< system.cpu2.icache.overall_miss_rate::cpu2.inst 0.020629 # miss rate for overall accesses
< system.cpu2.icache.overall_miss_rate::total 0.020629 # miss rate for overall accesses
< system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13207.530648 # average ReadReq miss latency
< system.cpu2.icache.ReadReq_avg_miss_latency::total 13207.530648 # average ReadReq miss latency
< system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13207.530648 # average overall miss latency
< system.cpu2.icache.demand_avg_miss_latency::total 13207.530648 # average overall miss latency
< system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13207.530648 # average overall miss latency
< system.cpu2.icache.overall_avg_miss_latency::total 13207.530648 # average overall miss latency
< system.cpu2.icache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked
---
> system.cpu2.icache.tags.tag_accesses 20527 # Number of tag accesses
> system.cpu2.icache.tags.data_accesses 20527 # Number of data accesses
> system.cpu2.icache.ReadReq_hits::cpu2.inst 19454 # number of ReadReq hits
> system.cpu2.icache.ReadReq_hits::total 19454 # number of ReadReq hits
> system.cpu2.icache.demand_hits::cpu2.inst 19454 # number of demand (read+write) hits
> system.cpu2.icache.demand_hits::total 19454 # number of demand (read+write) hits
> system.cpu2.icache.overall_hits::cpu2.inst 19454 # number of overall hits
> system.cpu2.icache.overall_hits::total 19454 # number of overall hits
> system.cpu2.icache.ReadReq_misses::cpu2.inst 573 # number of ReadReq misses
> system.cpu2.icache.ReadReq_misses::total 573 # number of ReadReq misses
> system.cpu2.icache.demand_misses::cpu2.inst 573 # number of demand (read+write) misses
> system.cpu2.icache.demand_misses::total 573 # number of demand (read+write) misses
> system.cpu2.icache.overall_misses::cpu2.inst 573 # number of overall misses
> system.cpu2.icache.overall_misses::total 573 # number of overall misses
> system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8014500 # number of ReadReq miss cycles
> system.cpu2.icache.ReadReq_miss_latency::total 8014500 # number of ReadReq miss cycles
> system.cpu2.icache.demand_miss_latency::cpu2.inst 8014500 # number of demand (read+write) miss cycles
> system.cpu2.icache.demand_miss_latency::total 8014500 # number of demand (read+write) miss cycles
> system.cpu2.icache.overall_miss_latency::cpu2.inst 8014500 # number of overall miss cycles
> system.cpu2.icache.overall_miss_latency::total 8014500 # number of overall miss cycles
> system.cpu2.icache.ReadReq_accesses::cpu2.inst 20027 # number of ReadReq accesses(hits+misses)
> system.cpu2.icache.ReadReq_accesses::total 20027 # number of ReadReq accesses(hits+misses)
> system.cpu2.icache.demand_accesses::cpu2.inst 20027 # number of demand (read+write) accesses
> system.cpu2.icache.demand_accesses::total 20027 # number of demand (read+write) accesses
> system.cpu2.icache.overall_accesses::cpu2.inst 20027 # number of overall (read+write) accesses
> system.cpu2.icache.overall_accesses::total 20027 # number of overall (read+write) accesses
> system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.028611 # miss rate for ReadReq accesses
> system.cpu2.icache.ReadReq_miss_rate::total 0.028611 # miss rate for ReadReq accesses
> system.cpu2.icache.demand_miss_rate::cpu2.inst 0.028611 # miss rate for demand accesses
> system.cpu2.icache.demand_miss_rate::total 0.028611 # miss rate for demand accesses
> system.cpu2.icache.overall_miss_rate::cpu2.inst 0.028611 # miss rate for overall accesses
> system.cpu2.icache.overall_miss_rate::total 0.028611 # miss rate for overall accesses
> system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13986.910995 # average ReadReq miss latency
> system.cpu2.icache.ReadReq_avg_miss_latency::total 13986.910995 # average ReadReq miss latency
> system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13986.910995 # average overall miss latency
> system.cpu2.icache.demand_avg_miss_latency::total 13986.910995 # average overall miss latency
> system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13986.910995 # average overall miss latency
> system.cpu2.icache.overall_avg_miss_latency::total 13986.910995 # average overall miss latency
> system.cpu2.icache.blocked_cycles::no_mshrs 5 # number of cycles access was blocked
1814c1814
< system.cpu2.icache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked
---
> system.cpu2.icache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked
1818,1823c1818,1823
< system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 71 # number of ReadReq MSHR hits
< system.cpu2.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits
< system.cpu2.icache.demand_mshr_hits::cpu2.inst 71 # number of demand (read+write) MSHR hits
< system.cpu2.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits
< system.cpu2.icache.overall_mshr_hits::cpu2.inst 71 # number of overall MSHR hits
< system.cpu2.icache.overall_mshr_hits::total 71 # number of overall MSHR hits
---
> system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 73 # number of ReadReq MSHR hits
> system.cpu2.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
> system.cpu2.icache.demand_mshr_hits::cpu2.inst 73 # number of demand (read+write) MSHR hits
> system.cpu2.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
> system.cpu2.icache.overall_mshr_hits::cpu2.inst 73 # number of overall MSHR hits
> system.cpu2.icache.overall_mshr_hits::total 73 # number of overall MSHR hits
1830,1847c1830,1847
< system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6543500 # number of ReadReq MSHR miss cycles
< system.cpu2.icache.ReadReq_mshr_miss_latency::total 6543500 # number of ReadReq MSHR miss cycles
< system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6543500 # number of demand (read+write) MSHR miss cycles
< system.cpu2.icache.demand_mshr_miss_latency::total 6543500 # number of demand (read+write) MSHR miss cycles
< system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6543500 # number of overall MSHR miss cycles
< system.cpu2.icache.overall_mshr_miss_latency::total 6543500 # number of overall MSHR miss cycles
< system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.018064 # mshr miss rate for ReadReq accesses
< system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.018064 # mshr miss rate for ReadReq accesses
< system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.018064 # mshr miss rate for demand accesses
< system.cpu2.icache.demand_mshr_miss_rate::total 0.018064 # mshr miss rate for demand accesses
< system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.018064 # mshr miss rate for overall accesses
< system.cpu2.icache.overall_mshr_miss_rate::total 0.018064 # mshr miss rate for overall accesses
< system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13087 # average ReadReq mshr miss latency
< system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13087 # average ReadReq mshr miss latency
< system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13087 # average overall mshr miss latency
< system.cpu2.icache.demand_avg_mshr_miss_latency::total 13087 # average overall mshr miss latency
< system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13087 # average overall mshr miss latency
< system.cpu2.icache.overall_avg_mshr_miss_latency::total 13087 # average overall mshr miss latency
---
> system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6952000 # number of ReadReq MSHR miss cycles
> system.cpu2.icache.ReadReq_mshr_miss_latency::total 6952000 # number of ReadReq MSHR miss cycles
> system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6952000 # number of demand (read+write) MSHR miss cycles
> system.cpu2.icache.demand_mshr_miss_latency::total 6952000 # number of demand (read+write) MSHR miss cycles
> system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6952000 # number of overall MSHR miss cycles
> system.cpu2.icache.overall_mshr_miss_latency::total 6952000 # number of overall MSHR miss cycles
> system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.024966 # mshr miss rate for ReadReq accesses
> system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.024966 # mshr miss rate for ReadReq accesses
> system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.024966 # mshr miss rate for demand accesses
> system.cpu2.icache.demand_mshr_miss_rate::total 0.024966 # mshr miss rate for demand accesses
> system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.024966 # mshr miss rate for overall accesses
> system.cpu2.icache.overall_mshr_miss_rate::total 0.024966 # mshr miss rate for overall accesses
> system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13904 # average ReadReq mshr miss latency
> system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13904 # average ReadReq mshr miss latency
> system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13904 # average overall mshr miss latency
> system.cpu2.icache.demand_avg_mshr_miss_latency::total 13904 # average overall mshr miss latency
> system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13904 # average overall mshr miss latency
> system.cpu2.icache.overall_avg_mshr_miss_latency::total 13904 # average overall mshr miss latency
1849,1853c1849,1853
< system.cpu3.branchPred.lookups 58611 # Number of BP lookups
< system.cpu3.branchPred.condPredicted 55067 # Number of conditional branches predicted
< system.cpu3.branchPred.condIncorrect 1279 # Number of conditional branches incorrect
< system.cpu3.branchPred.BTBLookups 51125 # Number of BTB lookups
< system.cpu3.branchPred.BTBHits 50131 # Number of BTB hits
---
> system.cpu3.branchPred.lookups 42820 # Number of BP lookups
> system.cpu3.branchPred.condPredicted 39316 # Number of conditional branches predicted
> system.cpu3.branchPred.condIncorrect 1255 # Number of conditional branches incorrect
> system.cpu3.branchPred.BTBLookups 35479 # Number of BTB lookups
> system.cpu3.branchPred.BTBHits 34386 # Number of BTB hits
1855,1856c1855,1856
< system.cpu3.branchPred.BTBHitPct 98.055746 # BTB Hit Percentage
< system.cpu3.branchPred.usedRAS 906 # Number of times the RAS was used to get a target.
---
> system.cpu3.branchPred.BTBHitPct 96.919304 # BTB Hit Percentage
> system.cpu3.branchPred.usedRAS 900 # Number of times the RAS was used to get a target.
1858c1858
< system.cpu3.numCycles 160611 # number of cpu cycles simulated
---
> system.cpu3.numCycles 161928 # number of cpu cycles simulated
1861,1866c1861,1866
< system.cpu3.fetch.icacheStallCycles 27021 # Number of cycles fetch is stalled on an Icache miss
< system.cpu3.fetch.Insts 330369 # Number of instructions fetch has processed
< system.cpu3.fetch.Branches 58611 # Number of branches that fetch encountered
< system.cpu3.fetch.predictedBranches 51037 # Number of branches that fetch has predicted taken
< system.cpu3.fetch.Cycles 129883 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu3.fetch.SquashCycles 2715 # Number of cycles fetch has spent squashing
---
> system.cpu3.fetch.icacheStallCycles 36909 # Number of cycles fetch is stalled on an Icache miss
> system.cpu3.fetch.Insts 226016 # Number of instructions fetch has processed
> system.cpu3.fetch.Branches 42820 # Number of branches that fetch encountered
> system.cpu3.fetch.predictedBranches 35286 # Number of branches that fetch has predicted taken
> system.cpu3.fetch.Cycles 121156 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu3.fetch.SquashCycles 2665 # Number of cycles fetch has spent squashing
1869,1874c1869,1874
< system.cpu3.fetch.PendingTrapStallCycles 1165 # Number of stall cycles due to pending traps
< system.cpu3.fetch.CacheLines 18269 # Number of cache lines fetched
< system.cpu3.fetch.IcacheSquashes 450 # Number of outstanding Icache misses that were squashed
< system.cpu3.fetch.rateDist::samples 159439 # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::mean 2.072071 # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::stdev 2.246890 # Number of instructions fetched each cycle (Total)
---
> system.cpu3.fetch.PendingTrapStallCycles 1154 # Number of stall cycles due to pending traps
> system.cpu3.fetch.CacheLines 27941 # Number of cache lines fetched
> system.cpu3.fetch.IcacheSquashes 455 # Number of outstanding Icache misses that were squashed
> system.cpu3.fetch.rateDist::samples 160564 # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::mean 1.407638 # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::stdev 2.031731 # Number of instructions fetched each cycle (Total)
1876,1884c1876,1884
< system.cpu3.fetch.rateDist::0 47077 29.53% 29.53% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::1 55913 35.07% 64.60% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::2 4932 3.09% 67.69% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::3 3522 2.21% 69.90% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::4 934 0.59% 70.48% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::5 40952 25.69% 96.17% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::6 1272 0.80% 96.97% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::7 798 0.50% 97.47% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::8 4039 2.53% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu3.fetch.rateDist::0 74840 46.61% 46.61% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::1 45030 28.04% 74.66% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::2 9823 6.12% 80.77% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::3 3413 2.13% 82.90% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::4 964 0.60% 83.50% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::5 20524 12.78% 96.28% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::6 1162 0.72% 97.01% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::7 811 0.51% 97.51% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::8 3997 2.49% 100.00% # Number of instructions fetched each cycle (Total)
1888,1928c1888,1928
< system.cpu3.fetch.rateDist::total 159439 # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.branchRate 0.364925 # Number of branch fetches per cycle
< system.cpu3.fetch.rate 2.056951 # Number of inst fetches per cycle
< system.cpu3.decode.IdleCycles 16993 # Number of cycles decode is idle
< system.cpu3.decode.BlockedCycles 43740 # Number of cycles decode is blocked
< system.cpu3.decode.RunCycles 94729 # Number of cycles decode is running
< system.cpu3.decode.UnblockCycles 2610 # Number of cycles decode is unblocking
< system.cpu3.decode.SquashCycles 1357 # Number of cycles decode is squashing
< system.cpu3.decode.DecodedInsts 315004 # Number of instructions handled by decode
< system.cpu3.rename.SquashCycles 1357 # Number of cycles rename is squashing
< system.cpu3.rename.IdleCycles 17735 # Number of cycles rename is idle
< system.cpu3.rename.BlockCycles 17944 # Number of cycles rename is blocking
< system.cpu3.rename.serializeStallCycles 14128 # count of cycles rename stalled for serializing inst
< system.cpu3.rename.RunCycles 95562 # Number of cycles rename is running
< system.cpu3.rename.UnblockCycles 12703 # Number of cycles rename is unblocking
< system.cpu3.rename.RenamedInsts 311495 # Number of instructions processed by rename
< system.cpu3.rename.IQFullEvents 10931 # Number of times rename has blocked due to IQ full
< system.cpu3.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full
< system.cpu3.rename.FullRegisterEvents 2 # Number of times there has been no free registers
< system.cpu3.rename.RenamedOperands 220426 # Number of destination operands rename has renamed
< system.cpu3.rename.RenameLookups 606441 # Number of register rename lookups that rename has made
< system.cpu3.rename.int_rename_lookups 469854 # Number of integer rename lookups
< system.cpu3.rename.CommittedMaps 206787 # Number of HB maps that are committed
< system.cpu3.rename.UndoneMaps 13639 # Number of HB maps that are undone due to squashing
< system.cpu3.rename.serializingInsts 1207 # count of serializing insts renamed
< system.cpu3.rename.tempSerializingInsts 1278 # count of temporary serializing insts renamed
< system.cpu3.rename.skidInsts 17457 # count of insts added to the skid buffer
< system.cpu3.memDep0.insertedLoads 89942 # Number of loads inserted to the mem dependence unit.
< system.cpu3.memDep0.insertedStores 43802 # Number of stores inserted to the mem dependence unit.
< system.cpu3.memDep0.conflictingLoads 42282 # Number of conflicting loads.
< system.cpu3.memDep0.conflictingStores 38692 # Number of conflicting stores.
< system.cpu3.iq.iqInstsAdded 261084 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu3.iq.iqNonSpecInstsAdded 4750 # Number of non-speculative instructions added to the IQ
< system.cpu3.iq.iqInstsIssued 261694 # Number of instructions issued
< system.cpu3.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued
< system.cpu3.iq.iqSquashedInstsExamined 12498 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu3.iq.iqSquashedOperandsExamined 9712 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu3.iq.iqSquashedNonSpecRemoved 614 # Number of squashed non-spec instructions that were removed
< system.cpu3.iq.issued_per_cycle::samples 159439 # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::mean 1.641342 # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::stdev 1.359128 # Number of insts issued each cycle
---
> system.cpu3.fetch.rateDist::total 160564 # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.branchRate 0.264439 # Number of branch fetches per cycle
> system.cpu3.fetch.rate 1.395781 # Number of inst fetches per cycle
> system.cpu3.decode.IdleCycles 17966 # Number of cycles decode is idle
> system.cpu3.decode.BlockedCycles 81801 # Number of cycles decode is blocked
> system.cpu3.decode.RunCycles 54656 # Number of cycles decode is running
> system.cpu3.decode.UnblockCycles 4799 # Number of cycles decode is unblocking
> system.cpu3.decode.SquashCycles 1332 # Number of cycles decode is squashing
> system.cpu3.decode.DecodedInsts 210555 # Number of instructions handled by decode
> system.cpu3.rename.SquashCycles 1332 # Number of cycles rename is squashing
> system.cpu3.rename.IdleCycles 18639 # Number of cycles rename is idle
> system.cpu3.rename.BlockCycles 40771 # Number of cycles rename is blocking
> system.cpu3.rename.serializeStallCycles 13962 # count of cycles rename stalled for serializing inst
> system.cpu3.rename.RunCycles 56374 # Number of cycles rename is running
> system.cpu3.rename.UnblockCycles 29476 # Number of cycles rename is unblocking
> system.cpu3.rename.RenamedInsts 207391 # Number of instructions processed by rename
> system.cpu3.rename.IQFullEvents 26344 # Number of times rename has blocked due to IQ full
> system.cpu3.rename.LQFullEvents 13 # Number of times rename has blocked due to LQ full
> system.cpu3.rename.FullRegisterEvents 3 # Number of times there has been no free registers
> system.cpu3.rename.RenamedOperands 143048 # Number of destination operands rename has renamed
> system.cpu3.rename.RenameLookups 379530 # Number of register rename lookups that rename has made
> system.cpu3.rename.int_rename_lookups 299622 # Number of integer rename lookups
> system.cpu3.rename.CommittedMaps 129648 # Number of HB maps that are committed
> system.cpu3.rename.UndoneMaps 13400 # Number of HB maps that are undone due to squashing
> system.cpu3.rename.serializingInsts 1181 # count of serializing insts renamed
> system.cpu3.rename.tempSerializingInsts 1248 # count of temporary serializing insts renamed
> system.cpu3.rename.skidInsts 33973 # count of insts added to the skid buffer
> system.cpu3.memDep0.insertedLoads 53782 # Number of loads inserted to the mem dependence unit.
> system.cpu3.memDep0.insertedStores 23352 # Number of stores inserted to the mem dependence unit.
> system.cpu3.memDep0.conflictingLoads 26620 # Number of conflicting loads.
> system.cpu3.memDep0.conflictingStores 18276 # Number of conflicting stores.
> system.cpu3.iq.iqInstsAdded 168080 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu3.iq.iqNonSpecInstsAdded 9470 # Number of non-speculative instructions added to the IQ
> system.cpu3.iq.iqInstsIssued 172966 # Number of instructions issued
> system.cpu3.iq.iqSquashedInstsIssued 9 # Number of squashed instructions issued
> system.cpu3.iq.iqSquashedInstsExamined 12631 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu3.iq.iqSquashedOperandsExamined 10295 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu3.iq.iqSquashedNonSpecRemoved 757 # Number of squashed non-spec instructions that were removed
> system.cpu3.iq.issued_per_cycle::samples 160564 # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::mean 1.077240 # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::stdev 1.332251 # Number of insts issued each cycle
1930,1938c1930,1938
< system.cpu3.iq.issued_per_cycle::0 50249 31.52% 31.52% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::1 16842 10.56% 42.08% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::2 43259 27.13% 69.21% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::3 42799 26.84% 96.05% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::4 3393 2.13% 98.18% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::5 1616 1.01% 99.20% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::6 876 0.55% 99.75% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::7 211 0.13% 99.88% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::8 194 0.12% 100.00% # Number of insts issued each cycle
---
> system.cpu3.iq.issued_per_cycle::0 78662 48.99% 48.99% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::1 30467 18.97% 67.97% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::2 22821 14.21% 82.18% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::3 22372 13.93% 96.11% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::4 3353 2.09% 98.20% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::5 1614 1.01% 99.21% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::6 863 0.54% 99.74% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::7 215 0.13% 99.88% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::8 197 0.12% 100.00% # Number of insts issued each cycle
1942c1942
< system.cpu3.iq.issued_per_cycle::total 159439 # Number of insts issued each cycle
---
> system.cpu3.iq.issued_per_cycle::total 160564 # Number of insts issued each cycle
1944,1974c1944,1974
< system.cpu3.iq.fu_full::IntAlu 81 26.21% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::IntMult 0 0.00% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::IntDiv 0 0.00% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.21% # attempts to use FU when none available
< system.cpu3.iq.fu_full::MemRead 19 6.15% 32.36% # attempts to use FU when none available
< system.cpu3.iq.fu_full::MemWrite 209 67.64% 100.00% # attempts to use FU when none available
---
> system.cpu3.iq.fu_full::IntAlu 82 24.55% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::IntMult 0 0.00% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::IntDiv 0 0.00% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::FloatAdd 0 0.00% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::FloatCmp 0 0.00% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::FloatCvt 0 0.00% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::FloatMult 0 0.00% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::FloatDiv 0 0.00% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdAdd 0 0.00% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdAlu 0 0.00% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdCmp 0 0.00% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdCvt 0 0.00% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdMisc 0 0.00% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdMult 0 0.00% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdShift 0 0.00% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 24.55% # attempts to use FU when none available
> system.cpu3.iq.fu_full::MemRead 43 12.87% 37.43% # attempts to use FU when none available
> system.cpu3.iq.fu_full::MemWrite 209 62.57% 100.00% # attempts to use FU when none available
1978,2008c1978,2008
< system.cpu3.iq.FU_type_0::IntAlu 125700 48.03% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::MemRead 92778 35.45% 83.49% # Type of FU issued
< system.cpu3.iq.FU_type_0::MemWrite 43216 16.51% 100.00% # Type of FU issued
---
> system.cpu3.iq.FU_type_0::IntAlu 89169 51.55% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::IntMult 0 0.00% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.55% # Type of FU issued
> system.cpu3.iq.FU_type_0::MemRead 61014 35.28% 86.83% # Type of FU issued
> system.cpu3.iq.FU_type_0::MemWrite 22783 13.17% 100.00% # Type of FU issued
2011,2017c2011,2017
< system.cpu3.iq.FU_type_0::total 261694 # Type of FU issued
< system.cpu3.iq.rate 1.629365 # Inst issue rate
< system.cpu3.iq.fu_busy_cnt 309 # FU busy when requested
< system.cpu3.iq.fu_busy_rate 0.001181 # FU busy rate (busy events/executed inst)
< system.cpu3.iq.int_inst_queue_reads 683137 # Number of integer instruction queue reads
< system.cpu3.iq.int_inst_queue_writes 278366 # Number of integer instruction queue writes
< system.cpu3.iq.int_inst_queue_wakeup_accesses 260191 # Number of integer instruction queue wakeup accesses
---
> system.cpu3.iq.FU_type_0::total 172966 # Type of FU issued
> system.cpu3.iq.rate 1.068166 # Inst issue rate
> system.cpu3.iq.fu_busy_cnt 334 # FU busy when requested
> system.cpu3.iq.fu_busy_rate 0.001931 # FU busy rate (busy events/executed inst)
> system.cpu3.iq.int_inst_queue_reads 506839 # Number of integer instruction queue reads
> system.cpu3.iq.int_inst_queue_writes 190218 # Number of integer instruction queue writes
> system.cpu3.iq.int_inst_queue_wakeup_accesses 171502 # Number of integer instruction queue wakeup accesses
2021c2021
< system.cpu3.iq.int_alu_accesses 262003 # Number of integer alu accesses
---
> system.cpu3.iq.int_alu_accesses 173300 # Number of integer alu accesses
2023c2023
< system.cpu3.iew.lsq.thread0.forwLoads 38539 # Number of loads that had data forwarded from stores
---
> system.cpu3.iew.lsq.thread0.forwLoads 18096 # Number of loads that had data forwarded from stores
2025c2025
< system.cpu3.iew.lsq.thread0.squashedLoads 2394 # Number of loads squashed
---
> system.cpu3.iew.lsq.thread0.squashedLoads 2521 # Number of loads squashed
2027,2028c2027,2028
< system.cpu3.iew.lsq.thread0.memOrderViolation 34 # Number of memory ordering violations
< system.cpu3.iew.lsq.thread0.squashedStores 1484 # Number of stores squashed
---
> system.cpu3.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations
> system.cpu3.iew.lsq.thread0.squashedStores 1454 # Number of stores squashed
2034,2042c2034,2042
< system.cpu3.iew.iewSquashCycles 1357 # Number of cycles IEW is squashing
< system.cpu3.iew.iewBlockCycles 5389 # Number of cycles IEW is blocking
< system.cpu3.iew.iewUnblockCycles 51 # Number of cycles IEW is unblocking
< system.cpu3.iew.iewDispatchedInsts 309030 # Number of instructions dispatched to IQ
< system.cpu3.iew.iewDispSquashedInsts 159 # Number of squashed instructions skipped by dispatch
< system.cpu3.iew.iewDispLoadInsts 89942 # Number of dispatched load instructions
< system.cpu3.iew.iewDispStoreInsts 43802 # Number of dispatched store instructions
< system.cpu3.iew.iewDispNonSpecInsts 1148 # Number of dispatched non-speculative instructions
< system.cpu3.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall
---
> system.cpu3.iew.iewSquashCycles 1332 # Number of cycles IEW is squashing
> system.cpu3.iew.iewBlockCycles 10558 # Number of cycles IEW is blocking
> system.cpu3.iew.iewUnblockCycles 75 # Number of cycles IEW is unblocking
> system.cpu3.iew.iewDispatchedInsts 205014 # Number of instructions dispatched to IQ
> system.cpu3.iew.iewDispSquashedInsts 178 # Number of squashed instructions skipped by dispatch
> system.cpu3.iew.iewDispLoadInsts 53782 # Number of dispatched load instructions
> system.cpu3.iew.iewDispStoreInsts 23352 # Number of dispatched store instructions
> system.cpu3.iew.iewDispNonSpecInsts 1140 # Number of dispatched non-speculative instructions
> system.cpu3.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall
2044,2050c2044,2050
< system.cpu3.iew.memOrderViolationEvents 34 # Number of memory order violations
< system.cpu3.iew.predictedTakenIncorrect 441 # Number of branches that were predicted taken incorrectly
< system.cpu3.iew.predictedNotTakenIncorrect 1075 # Number of branches that were predicted not taken incorrectly
< system.cpu3.iew.branchMispredicts 1516 # Number of branch mispredicts detected at execute
< system.cpu3.iew.iewExecutedInsts 260676 # Number of executed instructions
< system.cpu3.iew.iewExecLoadInsts 89042 # Number of load instructions executed
< system.cpu3.iew.iewExecSquashedInsts 1018 # Number of squashed instructions skipped in execute
---
> system.cpu3.iew.memOrderViolationEvents 37 # Number of memory order violations
> system.cpu3.iew.predictedTakenIncorrect 429 # Number of branches that were predicted taken incorrectly
> system.cpu3.iew.predictedNotTakenIncorrect 1047 # Number of branches that were predicted not taken incorrectly
> system.cpu3.iew.branchMispredicts 1476 # Number of branch mispredicts detected at execute
> system.cpu3.iew.iewExecutedInsts 171988 # Number of executed instructions
> system.cpu3.iew.iewExecLoadInsts 52726 # Number of load instructions executed
> system.cpu3.iew.iewExecSquashedInsts 978 # Number of squashed instructions skipped in execute
2052,2060c2052,2060
< system.cpu3.iew.exec_nop 43196 # number of nop insts executed
< system.cpu3.iew.exec_refs 132177 # number of memory reference insts executed
< system.cpu3.iew.exec_branches 52784 # Number of branches executed
< system.cpu3.iew.exec_stores 43135 # Number of stores executed
< system.cpu3.iew.exec_rate 1.623027 # Inst execution rate
< system.cpu3.iew.wb_sent 260451 # cumulative count of insts sent to commit
< system.cpu3.iew.wb_count 260191 # cumulative count of insts written-back
< system.cpu3.iew.wb_producers 149829 # num instructions producing a value
< system.cpu3.iew.wb_consumers 156442 # num instructions consuming a value
---
> system.cpu3.iew.exec_nop 27464 # number of nop insts executed
> system.cpu3.iew.exec_refs 75422 # number of memory reference insts executed
> system.cpu3.iew.exec_branches 36861 # Number of branches executed
> system.cpu3.iew.exec_stores 22696 # Number of stores executed
> system.cpu3.iew.exec_rate 1.062126 # Inst execution rate
> system.cpu3.iew.wb_sent 171762 # cumulative count of insts sent to commit
> system.cpu3.iew.wb_count 171502 # cumulative count of insts written-back
> system.cpu3.iew.wb_producers 92998 # num instructions producing a value
> system.cpu3.iew.wb_consumers 99577 # num instructions consuming a value
2062,2063c2062,2063
< system.cpu3.iew.wb_rate 1.620007 # insts written-back per cycle
< system.cpu3.iew.wb_fanout 0.957729 # average fanout of values written-back
---
> system.cpu3.iew.wb_rate 1.059125 # insts written-back per cycle
> system.cpu3.iew.wb_fanout 0.933931 # average fanout of values written-back
2065,2070c2065,2070
< system.cpu3.commit.commitSquashedInsts 13144 # The number of squashed insts skipped by commit
< system.cpu3.commit.commitNonSpecStalls 4136 # The number of times commit has been forced to stall to communicate backwards
< system.cpu3.commit.branchMispredicts 1279 # The number of times a branch was mispredicted
< system.cpu3.commit.committed_per_cycle::samples 156952 # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::mean 1.884863 # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::stdev 2.121598 # Number of insts commited each cycle
---
> system.cpu3.commit.commitSquashedInsts 13412 # The number of squashed insts skipped by commit
> system.cpu3.commit.commitNonSpecStalls 8713 # The number of times commit has been forced to stall to communicate backwards
> system.cpu3.commit.branchMispredicts 1255 # The number of times a branch was mispredicted
> system.cpu3.commit.committed_per_cycle::samples 158053 # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::mean 1.211980 # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::stdev 1.860135 # Number of insts commited each cycle
2072,2080c2072,2080
< system.cpu3.commit.committed_per_cycle::0 54210 34.54% 34.54% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::1 49323 31.43% 65.96% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::2 5280 3.36% 69.33% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::3 4930 3.14% 72.47% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::4 1531 0.98% 73.45% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::5 38585 24.58% 98.03% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::6 839 0.53% 98.56% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::7 955 0.61% 99.17% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::8 1299 0.83% 100.00% # Number of insts commited each cycle
---
> system.cpu3.commit.committed_per_cycle::0 87086 55.10% 55.10% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::1 33413 21.14% 76.24% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::2 5238 3.31% 79.55% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::3 9506 6.01% 85.57% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::4 1538 0.97% 86.54% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::5 18185 11.51% 98.05% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::6 832 0.53% 98.57% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::7 959 0.61% 99.18% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::8 1296 0.82% 100.00% # Number of insts commited each cycle
2084,2086c2084,2086
< system.cpu3.commit.committed_per_cycle::total 156952 # Number of insts commited each cycle
< system.cpu3.commit.committedInsts 295833 # Number of instructions committed
< system.cpu3.commit.committedOps 295833 # Number of ops (including micro ops) committed
---
> system.cpu3.commit.committed_per_cycle::total 158053 # Number of insts commited each cycle
> system.cpu3.commit.committedInsts 191557 # Number of instructions committed
> system.cpu3.commit.committedOps 191557 # Number of ops (including micro ops) committed
2088,2091c2088,2091
< system.cpu3.commit.refs 129866 # Number of memory references committed
< system.cpu3.commit.loads 87548 # Number of loads committed
< system.cpu3.commit.membars 3423 # Number of memory barriers committed
< system.cpu3.commit.branches 51706 # Number of branches committed
---
> system.cpu3.commit.refs 73159 # Number of memory references committed
> system.cpu3.commit.loads 51261 # Number of loads committed
> system.cpu3.commit.membars 7996 # Number of memory barriers committed
> system.cpu3.commit.branches 35851 # Number of branches committed
2093c2093
< system.cpu3.commit.int_insts 203693 # Number of committed integer instructions.
---
> system.cpu3.commit.int_insts 131131 # Number of committed integer instructions.
2095,2126c2095,2126
< system.cpu3.commit.op_class_0::No_OpClass 42497 14.37% 14.37% # Class of committed instruction
< system.cpu3.commit.op_class_0::IntAlu 120047 40.58% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::IntMult 0 0.00% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::IntDiv 0 0.00% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::FloatMult 0 0.00% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdMult 0 0.00% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdShift 0 0.00% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.94% # Class of committed instruction
< system.cpu3.commit.op_class_0::MemRead 90971 30.75% 85.70% # Class of committed instruction
< system.cpu3.commit.op_class_0::MemWrite 42318 14.30% 100.00% # Class of committed instruction
---
> system.cpu3.commit.op_class_0::No_OpClass 26638 13.91% 13.91% # Class of committed instruction
> system.cpu3.commit.op_class_0::IntAlu 83764 43.73% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::IntMult 0 0.00% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::IntDiv 0 0.00% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::FloatMult 0 0.00% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdMult 0 0.00% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdShift 0 0.00% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 57.63% # Class of committed instruction
> system.cpu3.commit.op_class_0::MemRead 59257 30.93% 88.57% # Class of committed instruction
> system.cpu3.commit.op_class_0::MemWrite 21898 11.43% 100.00% # Class of committed instruction
2129,2134c2129,2134
< system.cpu3.commit.op_class_0::total 295833 # Class of committed instruction
< system.cpu3.commit.bw_lim_events 1299 # number cycles where commit BW limit reached
< system.cpu3.rob.rob_reads 464044 # The number of ROB reads
< system.cpu3.rob.rob_writes 620441 # The number of ROB writes
< system.cpu3.timesIdled 203 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu3.idleCycles 1172 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu3.commit.op_class_0::total 191557 # Class of committed instruction
> system.cpu3.commit.bw_lim_events 1296 # number cycles where commit BW limit reached
> system.cpu3.rob.rob_reads 361140 # The number of ROB reads
> system.cpu3.rob.rob_writes 412450 # The number of ROB writes
> system.cpu3.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu3.idleCycles 1364 # Total number of cycles that the CPU has spent unscheduled due to idling
2136,2143c2136,2143
< system.cpu3.committedInsts 249913 # Number of Instructions Simulated
< system.cpu3.committedOps 249913 # Number of Ops (including micro ops) Simulated
< system.cpu3.cpi 0.642668 # CPI: Cycles Per Instruction
< system.cpu3.cpi_total 0.642668 # CPI: Total CPI of All Threads
< system.cpu3.ipc 1.556014 # IPC: Instructions Per Cycle
< system.cpu3.ipc_total 1.556014 # IPC: Total IPC of All Threads
< system.cpu3.int_regfile_reads 456401 # number of integer regfile reads
< system.cpu3.int_regfile_writes 212686 # number of integer regfile writes
---
> system.cpu3.committedInsts 156923 # Number of Instructions Simulated
> system.cpu3.committedOps 156923 # Number of Ops (including micro ops) Simulated
> system.cpu3.cpi 1.031895 # CPI: Cycles Per Instruction
> system.cpu3.cpi_total 1.031895 # CPI: Total CPI of All Threads
> system.cpu3.ipc 0.969091 # IPC: Instructions Per Cycle
> system.cpu3.ipc_total 0.969091 # IPC: Total IPC of All Threads
> system.cpu3.int_regfile_reads 285937 # number of integer regfile reads
> system.cpu3.int_regfile_writes 135307 # number of integer regfile writes
2145c2145
< system.cpu3.misc_regfile_reads 133817 # number of misc regfile reads
---
> system.cpu3.misc_regfile_reads 77019 # number of misc regfile reads
2148,2149c2148,2149
< system.cpu3.dcache.tags.tagsinuse 24.217896 # Cycle average of tags in use
< system.cpu3.dcache.tags.total_refs 48316 # Total number of references to valid blocks.
---
> system.cpu3.dcache.tags.tagsinuse 23.138417 # Cycle average of tags in use
> system.cpu3.dcache.tags.total_refs 27896 # Total number of references to valid blocks.
2151c2151
< system.cpu3.dcache.tags.avg_refs 1725.571429 # Average number of references to valid blocks.
---
> system.cpu3.dcache.tags.avg_refs 996.285714 # Average number of references to valid blocks.
2153,2155c2153,2155
< system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.217896 # Average occupied blocks per requestor
< system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047301 # Average percentage of cache occupancy
< system.cpu3.dcache.tags.occ_percent::total 0.047301 # Average percentage of cache occupancy
---
> system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.138417 # Average occupied blocks per requestor
> system.cpu3.dcache.tags.occ_percent::cpu3.data 0.045192 # Average percentage of cache occupancy
> system.cpu3.dcache.tags.occ_percent::total 0.045192 # Average percentage of cache occupancy
2159,2220c2159,2220
< system.cpu3.dcache.tags.tag_accesses 371433 # Number of tag accesses
< system.cpu3.dcache.tags.data_accesses 371433 # Number of data accesses
< system.cpu3.dcache.ReadReq_hits::cpu3.data 49959 # number of ReadReq hits
< system.cpu3.dcache.ReadReq_hits::total 49959 # number of ReadReq hits
< system.cpu3.dcache.WriteReq_hits::cpu3.data 42098 # number of WriteReq hits
< system.cpu3.dcache.WriteReq_hits::total 42098 # number of WriteReq hits
< system.cpu3.dcache.SwapReq_hits::cpu3.data 13 # number of SwapReq hits
< system.cpu3.dcache.SwapReq_hits::total 13 # number of SwapReq hits
< system.cpu3.dcache.demand_hits::cpu3.data 92057 # number of demand (read+write) hits
< system.cpu3.dcache.demand_hits::total 92057 # number of demand (read+write) hits
< system.cpu3.dcache.overall_hits::cpu3.data 92057 # number of overall hits
< system.cpu3.dcache.overall_hits::total 92057 # number of overall hits
< system.cpu3.dcache.ReadReq_misses::cpu3.data 521 # number of ReadReq misses
< system.cpu3.dcache.ReadReq_misses::total 521 # number of ReadReq misses
< system.cpu3.dcache.WriteReq_misses::cpu3.data 153 # number of WriteReq misses
< system.cpu3.dcache.WriteReq_misses::total 153 # number of WriteReq misses
< system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses
< system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses
< system.cpu3.dcache.demand_misses::cpu3.data 674 # number of demand (read+write) misses
< system.cpu3.dcache.demand_misses::total 674 # number of demand (read+write) misses
< system.cpu3.dcache.overall_misses::cpu3.data 674 # number of overall misses
< system.cpu3.dcache.overall_misses::total 674 # number of overall misses
< system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 8076500 # number of ReadReq miss cycles
< system.cpu3.dcache.ReadReq_miss_latency::total 8076500 # number of ReadReq miss cycles
< system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3408500 # number of WriteReq miss cycles
< system.cpu3.dcache.WriteReq_miss_latency::total 3408500 # number of WriteReq miss cycles
< system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 574500 # number of SwapReq miss cycles
< system.cpu3.dcache.SwapReq_miss_latency::total 574500 # number of SwapReq miss cycles
< system.cpu3.dcache.demand_miss_latency::cpu3.data 11485000 # number of demand (read+write) miss cycles
< system.cpu3.dcache.demand_miss_latency::total 11485000 # number of demand (read+write) miss cycles
< system.cpu3.dcache.overall_miss_latency::cpu3.data 11485000 # number of overall miss cycles
< system.cpu3.dcache.overall_miss_latency::total 11485000 # number of overall miss cycles
< system.cpu3.dcache.ReadReq_accesses::cpu3.data 50480 # number of ReadReq accesses(hits+misses)
< system.cpu3.dcache.ReadReq_accesses::total 50480 # number of ReadReq accesses(hits+misses)
< system.cpu3.dcache.WriteReq_accesses::cpu3.data 42251 # number of WriteReq accesses(hits+misses)
< system.cpu3.dcache.WriteReq_accesses::total 42251 # number of WriteReq accesses(hits+misses)
< system.cpu3.dcache.SwapReq_accesses::cpu3.data 67 # number of SwapReq accesses(hits+misses)
< system.cpu3.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses)
< system.cpu3.dcache.demand_accesses::cpu3.data 92731 # number of demand (read+write) accesses
< system.cpu3.dcache.demand_accesses::total 92731 # number of demand (read+write) accesses
< system.cpu3.dcache.overall_accesses::cpu3.data 92731 # number of overall (read+write) accesses
< system.cpu3.dcache.overall_accesses::total 92731 # number of overall (read+write) accesses
< system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010321 # miss rate for ReadReq accesses
< system.cpu3.dcache.ReadReq_miss_rate::total 0.010321 # miss rate for ReadReq accesses
< system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003621 # miss rate for WriteReq accesses
< system.cpu3.dcache.WriteReq_miss_rate::total 0.003621 # miss rate for WriteReq accesses
< system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.805970 # miss rate for SwapReq accesses
< system.cpu3.dcache.SwapReq_miss_rate::total 0.805970 # miss rate for SwapReq accesses
< system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007268 # miss rate for demand accesses
< system.cpu3.dcache.demand_miss_rate::total 0.007268 # miss rate for demand accesses
< system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007268 # miss rate for overall accesses
< system.cpu3.dcache.overall_miss_rate::total 0.007268 # miss rate for overall accesses
< system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15501.919386 # average ReadReq miss latency
< system.cpu3.dcache.ReadReq_avg_miss_latency::total 15501.919386 # average ReadReq miss latency
< system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 22277.777778 # average WriteReq miss latency
< system.cpu3.dcache.WriteReq_avg_miss_latency::total 22277.777778 # average WriteReq miss latency
< system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 10638.888889 # average SwapReq miss latency
< system.cpu3.dcache.SwapReq_avg_miss_latency::total 10638.888889 # average SwapReq miss latency
< system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17040.059347 # average overall miss latency
< system.cpu3.dcache.demand_avg_miss_latency::total 17040.059347 # average overall miss latency
< system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17040.059347 # average overall miss latency
< system.cpu3.dcache.overall_avg_miss_latency::total 17040.059347 # average overall miss latency
---
> system.cpu3.dcache.tags.tag_accesses 226271 # Number of tag accesses
> system.cpu3.dcache.tags.data_accesses 226271 # Number of data accesses
> system.cpu3.dcache.ReadReq_hits::cpu3.data 34144 # number of ReadReq hits
> system.cpu3.dcache.ReadReq_hits::total 34144 # number of ReadReq hits
> system.cpu3.dcache.WriteReq_hits::cpu3.data 21673 # number of WriteReq hits
> system.cpu3.dcache.WriteReq_hits::total 21673 # number of WriteReq hits
> system.cpu3.dcache.SwapReq_hits::cpu3.data 19 # number of SwapReq hits
> system.cpu3.dcache.SwapReq_hits::total 19 # number of SwapReq hits
> system.cpu3.dcache.demand_hits::cpu3.data 55817 # number of demand (read+write) hits
> system.cpu3.dcache.demand_hits::total 55817 # number of demand (read+write) hits
> system.cpu3.dcache.overall_hits::cpu3.data 55817 # number of overall hits
> system.cpu3.dcache.overall_hits::total 55817 # number of overall hits
> system.cpu3.dcache.ReadReq_misses::cpu3.data 463 # number of ReadReq misses
> system.cpu3.dcache.ReadReq_misses::total 463 # number of ReadReq misses
> system.cpu3.dcache.WriteReq_misses::cpu3.data 154 # number of WriteReq misses
> system.cpu3.dcache.WriteReq_misses::total 154 # number of WriteReq misses
> system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses
> system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses
> system.cpu3.dcache.demand_misses::cpu3.data 617 # number of demand (read+write) misses
> system.cpu3.dcache.demand_misses::total 617 # number of demand (read+write) misses
> system.cpu3.dcache.overall_misses::cpu3.data 617 # number of overall misses
> system.cpu3.dcache.overall_misses::total 617 # number of overall misses
> system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 7346500 # number of ReadReq miss cycles
> system.cpu3.dcache.ReadReq_miss_latency::total 7346500 # number of ReadReq miss cycles
> system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3280500 # number of WriteReq miss cycles
> system.cpu3.dcache.WriteReq_miss_latency::total 3280500 # number of WriteReq miss cycles
> system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 658000 # number of SwapReq miss cycles
> system.cpu3.dcache.SwapReq_miss_latency::total 658000 # number of SwapReq miss cycles
> system.cpu3.dcache.demand_miss_latency::cpu3.data 10627000 # number of demand (read+write) miss cycles
> system.cpu3.dcache.demand_miss_latency::total 10627000 # number of demand (read+write) miss cycles
> system.cpu3.dcache.overall_miss_latency::cpu3.data 10627000 # number of overall miss cycles
> system.cpu3.dcache.overall_miss_latency::total 10627000 # number of overall miss cycles
> system.cpu3.dcache.ReadReq_accesses::cpu3.data 34607 # number of ReadReq accesses(hits+misses)
> system.cpu3.dcache.ReadReq_accesses::total 34607 # number of ReadReq accesses(hits+misses)
> system.cpu3.dcache.WriteReq_accesses::cpu3.data 21827 # number of WriteReq accesses(hits+misses)
> system.cpu3.dcache.WriteReq_accesses::total 21827 # number of WriteReq accesses(hits+misses)
> system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses)
> system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
> system.cpu3.dcache.demand_accesses::cpu3.data 56434 # number of demand (read+write) accesses
> system.cpu3.dcache.demand_accesses::total 56434 # number of demand (read+write) accesses
> system.cpu3.dcache.overall_accesses::cpu3.data 56434 # number of overall (read+write) accesses
> system.cpu3.dcache.overall_accesses::total 56434 # number of overall (read+write) accesses
> system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.013379 # miss rate for ReadReq accesses
> system.cpu3.dcache.ReadReq_miss_rate::total 0.013379 # miss rate for ReadReq accesses
> system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007055 # miss rate for WriteReq accesses
> system.cpu3.dcache.WriteReq_miss_rate::total 0.007055 # miss rate for WriteReq accesses
> system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.732394 # miss rate for SwapReq accesses
> system.cpu3.dcache.SwapReq_miss_rate::total 0.732394 # miss rate for SwapReq accesses
> system.cpu3.dcache.demand_miss_rate::cpu3.data 0.010933 # miss rate for demand accesses
> system.cpu3.dcache.demand_miss_rate::total 0.010933 # miss rate for demand accesses
> system.cpu3.dcache.overall_miss_rate::cpu3.data 0.010933 # miss rate for overall accesses
> system.cpu3.dcache.overall_miss_rate::total 0.010933 # miss rate for overall accesses
> system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15867.170626 # average ReadReq miss latency
> system.cpu3.dcache.ReadReq_avg_miss_latency::total 15867.170626 # average ReadReq miss latency
> system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 21301.948052 # average WriteReq miss latency
> system.cpu3.dcache.WriteReq_avg_miss_latency::total 21301.948052 # average WriteReq miss latency
> system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 12653.846154 # average SwapReq miss latency
> system.cpu3.dcache.SwapReq_avg_miss_latency::total 12653.846154 # average SwapReq miss latency
> system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17223.662885 # average overall miss latency
> system.cpu3.dcache.demand_avg_miss_latency::total 17223.662885 # average overall miss latency
> system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17223.662885 # average overall miss latency
> system.cpu3.dcache.overall_avg_miss_latency::total 17223.662885 # average overall miss latency
2229,2276c2229,2276
< system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 369 # number of ReadReq MSHR hits
< system.cpu3.dcache.ReadReq_mshr_hits::total 369 # number of ReadReq MSHR hits
< system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 48 # number of WriteReq MSHR hits
< system.cpu3.dcache.WriteReq_mshr_hits::total 48 # number of WriteReq MSHR hits
< system.cpu3.dcache.demand_mshr_hits::cpu3.data 417 # number of demand (read+write) MSHR hits
< system.cpu3.dcache.demand_mshr_hits::total 417 # number of demand (read+write) MSHR hits
< system.cpu3.dcache.overall_mshr_hits::cpu3.data 417 # number of overall MSHR hits
< system.cpu3.dcache.overall_mshr_hits::total 417 # number of overall MSHR hits
< system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 152 # number of ReadReq MSHR misses
< system.cpu3.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses
< system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses
< system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses
< system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses
< system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses
< system.cpu3.dcache.demand_mshr_misses::cpu3.data 257 # number of demand (read+write) MSHR misses
< system.cpu3.dcache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses
< system.cpu3.dcache.overall_mshr_misses::cpu3.data 257 # number of overall MSHR misses
< system.cpu3.dcache.overall_mshr_misses::total 257 # number of overall MSHR misses
< system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1413000 # number of ReadReq MSHR miss cycles
< system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1413000 # number of ReadReq MSHR miss cycles
< system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 2020500 # number of WriteReq MSHR miss cycles
< system.cpu3.dcache.WriteReq_mshr_miss_latency::total 2020500 # number of WriteReq MSHR miss cycles
< system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 520500 # number of SwapReq MSHR miss cycles
< system.cpu3.dcache.SwapReq_mshr_miss_latency::total 520500 # number of SwapReq MSHR miss cycles
< system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3433500 # number of demand (read+write) MSHR miss cycles
< system.cpu3.dcache.demand_mshr_miss_latency::total 3433500 # number of demand (read+write) MSHR miss cycles
< system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3433500 # number of overall MSHR miss cycles
< system.cpu3.dcache.overall_mshr_miss_latency::total 3433500 # number of overall MSHR miss cycles
< system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003011 # mshr miss rate for ReadReq accesses
< system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003011 # mshr miss rate for ReadReq accesses
< system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002485 # mshr miss rate for WriteReq accesses
< system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002485 # mshr miss rate for WriteReq accesses
< system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.805970 # mshr miss rate for SwapReq accesses
< system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.805970 # mshr miss rate for SwapReq accesses
< system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002771 # mshr miss rate for demand accesses
< system.cpu3.dcache.demand_mshr_miss_rate::total 0.002771 # mshr miss rate for demand accesses
< system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002771 # mshr miss rate for overall accesses
< system.cpu3.dcache.overall_mshr_miss_rate::total 0.002771 # mshr miss rate for overall accesses
< system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9296.052632 # average ReadReq mshr miss latency
< system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9296.052632 # average ReadReq mshr miss latency
< system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 19242.857143 # average WriteReq mshr miss latency
< system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 19242.857143 # average WriteReq mshr miss latency
< system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 9638.888889 # average SwapReq mshr miss latency
< system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 9638.888889 # average SwapReq mshr miss latency
< system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13359.922179 # average overall mshr miss latency
< system.cpu3.dcache.demand_avg_mshr_miss_latency::total 13359.922179 # average overall mshr miss latency
< system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13359.922179 # average overall mshr miss latency
< system.cpu3.dcache.overall_avg_mshr_miss_latency::total 13359.922179 # average overall mshr miss latency
---
> system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 299 # number of ReadReq MSHR hits
> system.cpu3.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits
> system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 52 # number of WriteReq MSHR hits
> system.cpu3.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits
> system.cpu3.dcache.demand_mshr_hits::cpu3.data 351 # number of demand (read+write) MSHR hits
> system.cpu3.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits
> system.cpu3.dcache.overall_mshr_hits::cpu3.data 351 # number of overall MSHR hits
> system.cpu3.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits
> system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 164 # number of ReadReq MSHR misses
> system.cpu3.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses
> system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 102 # number of WriteReq MSHR misses
> system.cpu3.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses
> system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 52 # number of SwapReq MSHR misses
> system.cpu3.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses
> system.cpu3.dcache.demand_mshr_misses::cpu3.data 266 # number of demand (read+write) MSHR misses
> system.cpu3.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses
> system.cpu3.dcache.overall_mshr_misses::cpu3.data 266 # number of overall MSHR misses
> system.cpu3.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses
> system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1762500 # number of ReadReq MSHR miss cycles
> system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1762500 # number of ReadReq MSHR miss cycles
> system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1886000 # number of WriteReq MSHR miss cycles
> system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1886000 # number of WriteReq MSHR miss cycles
> system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 606000 # number of SwapReq MSHR miss cycles
> system.cpu3.dcache.SwapReq_mshr_miss_latency::total 606000 # number of SwapReq MSHR miss cycles
> system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3648500 # number of demand (read+write) MSHR miss cycles
> system.cpu3.dcache.demand_mshr_miss_latency::total 3648500 # number of demand (read+write) MSHR miss cycles
> system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3648500 # number of overall MSHR miss cycles
> system.cpu3.dcache.overall_mshr_miss_latency::total 3648500 # number of overall MSHR miss cycles
> system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004739 # mshr miss rate for ReadReq accesses
> system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004739 # mshr miss rate for ReadReq accesses
> system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.004673 # mshr miss rate for WriteReq accesses
> system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.004673 # mshr miss rate for WriteReq accesses
> system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.732394 # mshr miss rate for SwapReq accesses
> system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.732394 # mshr miss rate for SwapReq accesses
> system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004713 # mshr miss rate for demand accesses
> system.cpu3.dcache.demand_mshr_miss_rate::total 0.004713 # mshr miss rate for demand accesses
> system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004713 # mshr miss rate for overall accesses
> system.cpu3.dcache.overall_mshr_miss_rate::total 0.004713 # mshr miss rate for overall accesses
> system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 10746.951220 # average ReadReq mshr miss latency
> system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 10746.951220 # average ReadReq mshr miss latency
> system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 18490.196078 # average WriteReq mshr miss latency
> system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 18490.196078 # average WriteReq mshr miss latency
> system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 11653.846154 # average SwapReq mshr miss latency
> system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 11653.846154 # average SwapReq mshr miss latency
> system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13716.165414 # average overall mshr miss latency
> system.cpu3.dcache.demand_avg_mshr_miss_latency::total 13716.165414 # average overall mshr miss latency
> system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13716.165414 # average overall mshr miss latency
> system.cpu3.dcache.overall_avg_mshr_miss_latency::total 13716.165414 # average overall mshr miss latency
2279,2280c2279,2280
< system.cpu3.icache.tags.tagsinuse 80.866510 # Cycle average of tags in use
< system.cpu3.icache.tags.total_refs 17696 # Total number of references to valid blocks.
---
> system.cpu3.icache.tags.tagsinuse 77.554391 # Cycle average of tags in use
> system.cpu3.icache.tags.total_refs 27370 # Total number of references to valid blocks.
2282c2282
< system.cpu3.icache.tags.avg_refs 35.534137 # Average number of references to valid blocks.
---
> system.cpu3.icache.tags.avg_refs 54.959839 # Average number of references to valid blocks.
2284,2286c2284,2286
< system.cpu3.icache.tags.occ_blocks::cpu3.inst 80.866510 # Average occupied blocks per requestor
< system.cpu3.icache.tags.occ_percent::cpu3.inst 0.157942 # Average percentage of cache occupancy
< system.cpu3.icache.tags.occ_percent::total 0.157942 # Average percentage of cache occupancy
---
> system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.554391 # Average occupied blocks per requestor
> system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151473 # Average percentage of cache occupancy
> system.cpu3.icache.tags.occ_percent::total 0.151473 # Average percentage of cache occupancy
2291,2328c2291,2328
< system.cpu3.icache.tags.tag_accesses 18767 # Number of tag accesses
< system.cpu3.icache.tags.data_accesses 18767 # Number of data accesses
< system.cpu3.icache.ReadReq_hits::cpu3.inst 17696 # number of ReadReq hits
< system.cpu3.icache.ReadReq_hits::total 17696 # number of ReadReq hits
< system.cpu3.icache.demand_hits::cpu3.inst 17696 # number of demand (read+write) hits
< system.cpu3.icache.demand_hits::total 17696 # number of demand (read+write) hits
< system.cpu3.icache.overall_hits::cpu3.inst 17696 # number of overall hits
< system.cpu3.icache.overall_hits::total 17696 # number of overall hits
< system.cpu3.icache.ReadReq_misses::cpu3.inst 573 # number of ReadReq misses
< system.cpu3.icache.ReadReq_misses::total 573 # number of ReadReq misses
< system.cpu3.icache.demand_misses::cpu3.inst 573 # number of demand (read+write) misses
< system.cpu3.icache.demand_misses::total 573 # number of demand (read+write) misses
< system.cpu3.icache.overall_misses::cpu3.inst 573 # number of overall misses
< system.cpu3.icache.overall_misses::total 573 # number of overall misses
< system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7430000 # number of ReadReq miss cycles
< system.cpu3.icache.ReadReq_miss_latency::total 7430000 # number of ReadReq miss cycles
< system.cpu3.icache.demand_miss_latency::cpu3.inst 7430000 # number of demand (read+write) miss cycles
< system.cpu3.icache.demand_miss_latency::total 7430000 # number of demand (read+write) miss cycles
< system.cpu3.icache.overall_miss_latency::cpu3.inst 7430000 # number of overall miss cycles
< system.cpu3.icache.overall_miss_latency::total 7430000 # number of overall miss cycles
< system.cpu3.icache.ReadReq_accesses::cpu3.inst 18269 # number of ReadReq accesses(hits+misses)
< system.cpu3.icache.ReadReq_accesses::total 18269 # number of ReadReq accesses(hits+misses)
< system.cpu3.icache.demand_accesses::cpu3.inst 18269 # number of demand (read+write) accesses
< system.cpu3.icache.demand_accesses::total 18269 # number of demand (read+write) accesses
< system.cpu3.icache.overall_accesses::cpu3.inst 18269 # number of overall (read+write) accesses
< system.cpu3.icache.overall_accesses::total 18269 # number of overall (read+write) accesses
< system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.031365 # miss rate for ReadReq accesses
< system.cpu3.icache.ReadReq_miss_rate::total 0.031365 # miss rate for ReadReq accesses
< system.cpu3.icache.demand_miss_rate::cpu3.inst 0.031365 # miss rate for demand accesses
< system.cpu3.icache.demand_miss_rate::total 0.031365 # miss rate for demand accesses
< system.cpu3.icache.overall_miss_rate::cpu3.inst 0.031365 # miss rate for overall accesses
< system.cpu3.icache.overall_miss_rate::total 0.031365 # miss rate for overall accesses
< system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 12966.841187 # average ReadReq miss latency
< system.cpu3.icache.ReadReq_avg_miss_latency::total 12966.841187 # average ReadReq miss latency
< system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 12966.841187 # average overall miss latency
< system.cpu3.icache.demand_avg_miss_latency::total 12966.841187 # average overall miss latency
< system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 12966.841187 # average overall miss latency
< system.cpu3.icache.overall_avg_miss_latency::total 12966.841187 # average overall miss latency
---
> system.cpu3.icache.tags.tag_accesses 28439 # Number of tag accesses
> system.cpu3.icache.tags.data_accesses 28439 # Number of data accesses
> system.cpu3.icache.ReadReq_hits::cpu3.inst 27370 # number of ReadReq hits
> system.cpu3.icache.ReadReq_hits::total 27370 # number of ReadReq hits
> system.cpu3.icache.demand_hits::cpu3.inst 27370 # number of demand (read+write) hits
> system.cpu3.icache.demand_hits::total 27370 # number of demand (read+write) hits
> system.cpu3.icache.overall_hits::cpu3.inst 27370 # number of overall hits
> system.cpu3.icache.overall_hits::total 27370 # number of overall hits
> system.cpu3.icache.ReadReq_misses::cpu3.inst 571 # number of ReadReq misses
> system.cpu3.icache.ReadReq_misses::total 571 # number of ReadReq misses
> system.cpu3.icache.demand_misses::cpu3.inst 571 # number of demand (read+write) misses
> system.cpu3.icache.demand_misses::total 571 # number of demand (read+write) misses
> system.cpu3.icache.overall_misses::cpu3.inst 571 # number of overall misses
> system.cpu3.icache.overall_misses::total 571 # number of overall misses
> system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7675000 # number of ReadReq miss cycles
> system.cpu3.icache.ReadReq_miss_latency::total 7675000 # number of ReadReq miss cycles
> system.cpu3.icache.demand_miss_latency::cpu3.inst 7675000 # number of demand (read+write) miss cycles
> system.cpu3.icache.demand_miss_latency::total 7675000 # number of demand (read+write) miss cycles
> system.cpu3.icache.overall_miss_latency::cpu3.inst 7675000 # number of overall miss cycles
> system.cpu3.icache.overall_miss_latency::total 7675000 # number of overall miss cycles
> system.cpu3.icache.ReadReq_accesses::cpu3.inst 27941 # number of ReadReq accesses(hits+misses)
> system.cpu3.icache.ReadReq_accesses::total 27941 # number of ReadReq accesses(hits+misses)
> system.cpu3.icache.demand_accesses::cpu3.inst 27941 # number of demand (read+write) accesses
> system.cpu3.icache.demand_accesses::total 27941 # number of demand (read+write) accesses
> system.cpu3.icache.overall_accesses::cpu3.inst 27941 # number of overall (read+write) accesses
> system.cpu3.icache.overall_accesses::total 27941 # number of overall (read+write) accesses
> system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020436 # miss rate for ReadReq accesses
> system.cpu3.icache.ReadReq_miss_rate::total 0.020436 # miss rate for ReadReq accesses
> system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020436 # miss rate for demand accesses
> system.cpu3.icache.demand_miss_rate::total 0.020436 # miss rate for demand accesses
> system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020436 # miss rate for overall accesses
> system.cpu3.icache.overall_miss_rate::total 0.020436 # miss rate for overall accesses
> system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13441.330998 # average ReadReq miss latency
> system.cpu3.icache.ReadReq_avg_miss_latency::total 13441.330998 # average ReadReq miss latency
> system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13441.330998 # average overall miss latency
> system.cpu3.icache.demand_avg_miss_latency::total 13441.330998 # average overall miss latency
> system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13441.330998 # average overall miss latency
> system.cpu3.icache.overall_avg_miss_latency::total 13441.330998 # average overall miss latency
2337,2342c2337,2342
< system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 75 # number of ReadReq MSHR hits
< system.cpu3.icache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits
< system.cpu3.icache.demand_mshr_hits::cpu3.inst 75 # number of demand (read+write) MSHR hits
< system.cpu3.icache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
< system.cpu3.icache.overall_mshr_hits::cpu3.inst 75 # number of overall MSHR hits
< system.cpu3.icache.overall_mshr_hits::total 75 # number of overall MSHR hits
---
> system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 73 # number of ReadReq MSHR hits
> system.cpu3.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
> system.cpu3.icache.demand_mshr_hits::cpu3.inst 73 # number of demand (read+write) MSHR hits
> system.cpu3.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
> system.cpu3.icache.overall_mshr_hits::cpu3.inst 73 # number of overall MSHR hits
> system.cpu3.icache.overall_mshr_hits::total 73 # number of overall MSHR hits
2349,2366c2349,2366
< system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6421000 # number of ReadReq MSHR miss cycles
< system.cpu3.icache.ReadReq_mshr_miss_latency::total 6421000 # number of ReadReq MSHR miss cycles
< system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6421000 # number of demand (read+write) MSHR miss cycles
< system.cpu3.icache.demand_mshr_miss_latency::total 6421000 # number of demand (read+write) MSHR miss cycles
< system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6421000 # number of overall MSHR miss cycles
< system.cpu3.icache.overall_mshr_miss_latency::total 6421000 # number of overall MSHR miss cycles
< system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.027259 # mshr miss rate for ReadReq accesses
< system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.027259 # mshr miss rate for ReadReq accesses
< system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.027259 # mshr miss rate for demand accesses
< system.cpu3.icache.demand_mshr_miss_rate::total 0.027259 # mshr miss rate for demand accesses
< system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.027259 # mshr miss rate for overall accesses
< system.cpu3.icache.overall_mshr_miss_rate::total 0.027259 # mshr miss rate for overall accesses
< system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12893.574297 # average ReadReq mshr miss latency
< system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12893.574297 # average ReadReq mshr miss latency
< system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12893.574297 # average overall mshr miss latency
< system.cpu3.icache.demand_avg_mshr_miss_latency::total 12893.574297 # average overall mshr miss latency
< system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12893.574297 # average overall mshr miss latency
< system.cpu3.icache.overall_avg_mshr_miss_latency::total 12893.574297 # average overall mshr miss latency
---
> system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6616000 # number of ReadReq MSHR miss cycles
> system.cpu3.icache.ReadReq_mshr_miss_latency::total 6616000 # number of ReadReq MSHR miss cycles
> system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6616000 # number of demand (read+write) MSHR miss cycles
> system.cpu3.icache.demand_mshr_miss_latency::total 6616000 # number of demand (read+write) MSHR miss cycles
> system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6616000 # number of overall MSHR miss cycles
> system.cpu3.icache.overall_mshr_miss_latency::total 6616000 # number of overall MSHR miss cycles
> system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.017823 # mshr miss rate for ReadReq accesses
> system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.017823 # mshr miss rate for ReadReq accesses
> system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.017823 # mshr miss rate for demand accesses
> system.cpu3.icache.demand_mshr_miss_rate::total 0.017823 # mshr miss rate for demand accesses
> system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.017823 # mshr miss rate for overall accesses
> system.cpu3.icache.overall_mshr_miss_rate::total 0.017823 # mshr miss rate for overall accesses
> system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13285.140562 # average ReadReq mshr miss latency
> system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13285.140562 # average ReadReq mshr miss latency
> system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13285.140562 # average overall mshr miss latency
> system.cpu3.icache.demand_avg_mshr_miss_latency::total 13285.140562 # average overall mshr miss latency
> system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13285.140562 # average overall mshr miss latency
> system.cpu3.icache.overall_avg_mshr_miss_latency::total 13285.140562 # average overall mshr miss latency
2369,2370c2369,2370
< system.l2c.tags.tagsinuse 418.779018 # Cycle average of tags in use
< system.l2c.tags.total_refs 2347 # Total number of references to valid blocks.
---
> system.l2c.tags.tagsinuse 419.148333 # Cycle average of tags in use
> system.l2c.tags.total_refs 2348 # Total number of references to valid blocks.
2372c2372
< system.l2c.tags.avg_refs 4.411654 # Average number of references to valid blocks.
---
> system.l2c.tags.avg_refs 4.413534 # Average number of references to valid blocks.
2374,2382c2374,2382
< system.l2c.tags.occ_blocks::writebacks 0.786962 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 287.801372 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 58.040061 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 61.655177 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 5.312296 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu2.inst 2.346047 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu2.data 0.677363 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu3.inst 1.443236 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu3.data 0.716504 # Average occupied blocks per requestor
---
> system.l2c.tags.occ_blocks::writebacks 0.788271 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 288.012358 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 58.076849 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 62.302913 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 5.322223 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu2.inst 3.076380 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu2.data 0.717940 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu3.inst 0.174188 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu3.data 0.677210 # Average occupied blocks per requestor
2384c2384
< system.l2c.tags.occ_percent::cpu0.inst 0.004392 # Average percentage of cache occupancy
---
> system.l2c.tags.occ_percent::cpu0.inst 0.004395 # Average percentage of cache occupancy
2386c2386
< system.l2c.tags.occ_percent::cpu1.inst 0.000941 # Average percentage of cache occupancy
---
> system.l2c.tags.occ_percent::cpu1.inst 0.000951 # Average percentage of cache occupancy
2388,2392c2388,2392
< system.l2c.tags.occ_percent::cpu2.inst 0.000036 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu2.data 0.000010 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu3.inst 0.000022 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.006390 # Average percentage of cache occupancy
---
> system.l2c.tags.occ_percent::cpu2.inst 0.000047 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu3.inst 0.000003 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu3.data 0.000010 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.006396 # Average percentage of cache occupancy
2395,2396c2395,2396
< system.l2c.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 130 # Occupied blocks per task id
---
> system.l2c.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 138 # Occupied blocks per task id
2398,2399c2398,2399
< system.l2c.tags.tag_accesses 25618 # Number of tag accesses
< system.l2c.tags.data_accesses 25618 # Number of data accesses
---
> system.l2c.tags.tag_accesses 25610 # Number of tag accesses
> system.l2c.tags.data_accesses 25610 # Number of data accesses
2405,2407c2405,2407
< system.l2c.ReadCleanReq_hits::cpu1.inst 410 # number of ReadCleanReq hits
< system.l2c.ReadCleanReq_hits::cpu2.inst 491 # number of ReadCleanReq hits
< system.l2c.ReadCleanReq_hits::cpu3.inst 491 # number of ReadCleanReq hits
---
> system.l2c.ReadCleanReq_hits::cpu1.inst 409 # number of ReadCleanReq hits
> system.l2c.ReadCleanReq_hits::cpu2.inst 490 # number of ReadCleanReq hits
> system.l2c.ReadCleanReq_hits::cpu3.inst 493 # number of ReadCleanReq hits
2416c2416
< system.l2c.demand_hits::cpu1.inst 410 # number of demand (read+write) hits
---
> system.l2c.demand_hits::cpu1.inst 409 # number of demand (read+write) hits
2418c2418
< system.l2c.demand_hits::cpu2.inst 491 # number of demand (read+write) hits
---
> system.l2c.demand_hits::cpu2.inst 490 # number of demand (read+write) hits
2420c2420
< system.l2c.demand_hits::cpu3.inst 491 # number of demand (read+write) hits
---
> system.l2c.demand_hits::cpu3.inst 493 # number of demand (read+write) hits
2425c2425
< system.l2c.overall_hits::cpu1.inst 410 # number of overall hits
---
> system.l2c.overall_hits::cpu1.inst 409 # number of overall hits
2427c2427
< system.l2c.overall_hits::cpu2.inst 491 # number of overall hits
---
> system.l2c.overall_hits::cpu2.inst 490 # number of overall hits
2429c2429
< system.l2c.overall_hits::cpu3.inst 491 # number of overall hits
---
> system.l2c.overall_hits::cpu3.inst 493 # number of overall hits
2434,2436c2434,2436
< system.l2c.UpgradeReq_misses::cpu2.data 21 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu3.data 22 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 89 # number of UpgradeReq misses
---
> system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu3.data 21 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 87 # number of UpgradeReq misses
2443,2445c2443,2445
< system.l2c.ReadCleanReq_misses::cpu1.inst 86 # number of ReadCleanReq misses
< system.l2c.ReadCleanReq_misses::cpu2.inst 9 # number of ReadCleanReq misses
< system.l2c.ReadCleanReq_misses::cpu3.inst 7 # number of ReadCleanReq misses
---
> system.l2c.ReadCleanReq_misses::cpu1.inst 87 # number of ReadCleanReq misses
> system.l2c.ReadCleanReq_misses::cpu2.inst 10 # number of ReadCleanReq misses
> system.l2c.ReadCleanReq_misses::cpu3.inst 5 # number of ReadCleanReq misses
2454c2454
< system.l2c.demand_misses::cpu1.inst 86 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu1.inst 87 # number of demand (read+write) misses
2456c2456
< system.l2c.demand_misses::cpu2.inst 9 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu2.inst 10 # number of demand (read+write) misses
2458c2458
< system.l2c.demand_misses::cpu3.inst 7 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu3.inst 5 # number of demand (read+write) misses
2463c2463
< system.l2c.overall_misses::cpu1.inst 86 # number of overall misses
---
> system.l2c.overall_misses::cpu1.inst 87 # number of overall misses
2465c2465
< system.l2c.overall_misses::cpu2.inst 9 # number of overall misses
---
> system.l2c.overall_misses::cpu2.inst 10 # number of overall misses
2467c2467
< system.l2c.overall_misses::cpu3.inst 7 # number of overall misses
---
> system.l2c.overall_misses::cpu3.inst 5 # number of overall misses
2470c2470
< system.l2c.ReadExReq_miss_latency::cpu0.data 7390000 # number of ReadExReq miss cycles
---
> system.l2c.ReadExReq_miss_latency::cpu0.data 7619000 # number of ReadExReq miss cycles
2472,2479c2472,2479
< system.l2c.ReadExReq_miss_latency::cpu2.data 956500 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu3.data 1308500 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 10714000 # number of ReadExReq miss cycles
< system.l2c.ReadCleanReq_miss_latency::cpu0.inst 27682000 # number of ReadCleanReq miss cycles
< system.l2c.ReadCleanReq_miss_latency::cpu1.inst 6449000 # number of ReadCleanReq miss cycles
< system.l2c.ReadCleanReq_miss_latency::cpu2.inst 632000 # number of ReadCleanReq miss cycles
< system.l2c.ReadCleanReq_miss_latency::cpu3.inst 514000 # number of ReadCleanReq miss cycles
< system.l2c.ReadCleanReq_miss_latency::total 35277000 # number of ReadCleanReq miss cycles
---
> system.l2c.ReadExReq_miss_latency::cpu2.data 1485500 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu3.data 1133500 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 11297000 # number of ReadExReq miss cycles
> system.l2c.ReadCleanReq_miss_latency::cpu0.inst 27679000 # number of ReadCleanReq miss cycles
> system.l2c.ReadCleanReq_miss_latency::cpu1.inst 6525500 # number of ReadCleanReq miss cycles
> system.l2c.ReadCleanReq_miss_latency::cpu2.inst 707500 # number of ReadCleanReq miss cycles
> system.l2c.ReadCleanReq_miss_latency::cpu3.inst 342000 # number of ReadCleanReq miss cycles
> system.l2c.ReadCleanReq_miss_latency::total 35254000 # number of ReadCleanReq miss cycles
2482,2483c2482,2483
< system.l2c.ReadSharedReq_miss_latency::cpu2.data 82500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu3.data 96500 # number of ReadSharedReq miss cycles
---
> system.l2c.ReadSharedReq_miss_latency::cpu2.data 96500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu3.data 82500 # number of ReadSharedReq miss cycles
2485,2487c2485,2487
< system.l2c.demand_miss_latency::cpu0.inst 27682000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 13370500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 6449000 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::cpu0.inst 27679000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 13599500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 6525500 # number of demand (read+write) miss cycles
2489,2496c2489,2496
< system.l2c.demand_miss_latency::cpu2.inst 632000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu2.data 1039000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu3.inst 514000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu3.data 1405000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 52691000 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 27682000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 13370500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 6449000 # number of overall miss cycles
---
> system.l2c.demand_miss_latency::cpu2.inst 707500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu2.data 1582000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu3.inst 342000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu3.data 1216000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 53251000 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 27679000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 13599500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 6525500 # number of overall miss cycles
2498,2502c2498,2502
< system.l2c.overall_miss_latency::cpu2.inst 632000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu2.data 1039000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu3.inst 514000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu3.data 1405000 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 52691000 # number of overall miss cycles
---
> system.l2c.overall_miss_latency::cpu2.inst 707500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu2.data 1582000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu3.inst 342000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu3.data 1216000 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 53251000 # number of overall miss cycles
2507,2509c2507,2509
< system.l2c.UpgradeReq_accesses::cpu2.data 21 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu3.data 22 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 92 # number of UpgradeReq accesses(hits+misses)
---
> system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu3.data 21 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 90 # number of UpgradeReq accesses(hits+misses)
2547c2547
< system.l2c.UpgradeReq_miss_rate::total 0.967391 # miss rate for UpgradeReq accesses
---
> system.l2c.UpgradeReq_miss_rate::total 0.966667 # miss rate for UpgradeReq accesses
2554,2556c2554,2556
< system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.173387 # miss rate for ReadCleanReq accesses
< system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.018000 # miss rate for ReadCleanReq accesses
< system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.014056 # miss rate for ReadCleanReq accesses
---
> system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.175403 # miss rate for ReadCleanReq accesses
> system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.020000 # miss rate for ReadCleanReq accesses
> system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.010040 # miss rate for ReadCleanReq accesses
2565c2565
< system.l2c.demand_miss_rate::cpu1.inst 0.173387 # miss rate for demand accesses
---
> system.l2c.demand_miss_rate::cpu1.inst 0.175403 # miss rate for demand accesses
2567c2567
< system.l2c.demand_miss_rate::cpu2.inst 0.018000 # miss rate for demand accesses
---
> system.l2c.demand_miss_rate::cpu2.inst 0.020000 # miss rate for demand accesses
2569c2569
< system.l2c.demand_miss_rate::cpu3.inst 0.014056 # miss rate for demand accesses
---
> system.l2c.demand_miss_rate::cpu3.inst 0.010040 # miss rate for demand accesses
2574c2574
< system.l2c.overall_miss_rate::cpu1.inst 0.173387 # miss rate for overall accesses
---
> system.l2c.overall_miss_rate::cpu1.inst 0.175403 # miss rate for overall accesses
2576c2576
< system.l2c.overall_miss_rate::cpu2.inst 0.018000 # miss rate for overall accesses
---
> system.l2c.overall_miss_rate::cpu2.inst 0.020000 # miss rate for overall accesses
2578c2578
< system.l2c.overall_miss_rate::cpu3.inst 0.014056 # miss rate for overall accesses
---
> system.l2c.overall_miss_rate::cpu3.inst 0.010040 # miss rate for overall accesses
2581c2581
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 78617.021277 # average ReadExReq miss latency
---
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81053.191489 # average ReadExReq miss latency
2583,2590c2583,2590
< system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79708.333333 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu3.data 109041.666667 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 81786.259542 # average ReadExReq miss latency
< system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 76469.613260 # average ReadCleanReq miss latency
< system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 74988.372093 # average ReadCleanReq miss latency
< system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 70222.222222 # average ReadCleanReq miss latency
< system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 73428.571429 # average ReadCleanReq miss latency
< system.l2c.ReadCleanReq_avg_miss_latency::total 76028.017241 # average ReadCleanReq miss latency
---
> system.l2c.ReadExReq_avg_miss_latency::cpu2.data 123791.666667 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu3.data 94458.333333 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 86236.641221 # average ReadExReq miss latency
> system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 76461.325967 # average ReadCleanReq miss latency
> system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 75005.747126 # average ReadCleanReq miss latency
> system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 70750 # average ReadCleanReq miss latency
> system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 68400 # average ReadCleanReq miss latency
> system.l2c.ReadCleanReq_avg_miss_latency::total 75978.448276 # average ReadCleanReq miss latency
2593,2594c2593,2594
< system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 82500 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 96500 # average ReadSharedReq miss latency
---
> system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 96500 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 82500 # average ReadSharedReq miss latency
2596,2598c2596,2598
< system.l2c.demand_avg_miss_latency::cpu0.inst 76469.613260 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 79115.384615 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 74988.372093 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu0.inst 76461.325967 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 80470.414201 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 75005.747126 # average overall miss latency
2600,2607c2600,2607
< system.l2c.demand_avg_miss_latency::cpu2.inst 70222.222222 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu2.data 79923.076923 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu3.inst 73428.571429 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu3.data 108076.923077 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 77600.883652 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 76469.613260 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 79115.384615 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 74988.372093 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu2.inst 70750 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu2.data 121692.307692 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu3.inst 68400 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu3.data 93538.461538 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 78425.625920 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 76461.325967 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 80470.414201 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 75005.747126 # average overall miss latency
2609,2613c2609,2613
< system.l2c.overall_avg_miss_latency::cpu2.inst 70222.222222 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu2.data 79923.076923 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu3.inst 73428.571429 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu3.data 108076.923077 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 77600.883652 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::cpu2.inst 70750 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu2.data 121692.307692 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu3.inst 68400 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu3.data 93538.461538 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 78425.625920 # average overall miss latency
2624,2625c2624,2625
< system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 6 # number of ReadCleanReq MSHR hits
< system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 2 # number of ReadCleanReq MSHR hits
---
> system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 5 # number of ReadCleanReq MSHR hits
> system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 3 # number of ReadCleanReq MSHR hits
2629,2630c2629,2630
< system.l2c.demand_mshr_hits::cpu2.inst 6 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu3.inst 2 # number of demand (read+write) MSHR hits
---
> system.l2c.demand_mshr_hits::cpu2.inst 5 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu3.inst 3 # number of demand (read+write) MSHR hits
2634,2635c2634,2635
< system.l2c.overall_mshr_hits::cpu2.inst 6 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu3.inst 2 # number of overall MSHR hits
---
> system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu3.inst 3 # number of overall MSHR hits
2639,2641c2639,2641
< system.l2c.UpgradeReq_mshr_misses::cpu2.data 21 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu3.data 22 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 89 # number of UpgradeReq MSHR misses
---
> system.l2c.UpgradeReq_mshr_misses::cpu2.data 20 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu3.data 21 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 87 # number of UpgradeReq MSHR misses
2648,2650c2648,2650
< system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 82 # number of ReadCleanReq MSHR misses
< system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 3 # number of ReadCleanReq MSHR misses
< system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 5 # number of ReadCleanReq MSHR misses
---
> system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 83 # number of ReadCleanReq MSHR misses
> system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 5 # number of ReadCleanReq MSHR misses
> system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 2 # number of ReadCleanReq MSHR misses
2659c2659
< system.l2c.demand_mshr_misses::cpu1.inst 82 # number of demand (read+write) MSHR misses
---
> system.l2c.demand_mshr_misses::cpu1.inst 83 # number of demand (read+write) MSHR misses
2661c2661
< system.l2c.demand_mshr_misses::cpu2.inst 3 # number of demand (read+write) MSHR misses
---
> system.l2c.demand_mshr_misses::cpu2.inst 5 # number of demand (read+write) MSHR misses
2663c2663
< system.l2c.demand_mshr_misses::cpu3.inst 5 # number of demand (read+write) MSHR misses
---
> system.l2c.demand_mshr_misses::cpu3.inst 2 # number of demand (read+write) MSHR misses
2668c2668
< system.l2c.overall_mshr_misses::cpu1.inst 82 # number of overall MSHR misses
---
> system.l2c.overall_mshr_misses::cpu1.inst 83 # number of overall MSHR misses
2670c2670
< system.l2c.overall_mshr_misses::cpu2.inst 3 # number of overall MSHR misses
---
> system.l2c.overall_mshr_misses::cpu2.inst 5 # number of overall MSHR misses
2672c2672
< system.l2c.overall_mshr_misses::cpu3.inst 5 # number of overall MSHR misses
---
> system.l2c.overall_mshr_misses::cpu3.inst 2 # number of overall MSHR misses
2675,2680c2675,2680
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 560500 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 396000 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 438496 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 459499 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 1854495 # number of UpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6450000 # number of ReadExReq MSHR miss cycles
---
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 586500 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 413500 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 436000 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 457997 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 1893997 # number of UpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6679000 # number of ReadExReq MSHR miss cycles
2682,2689c2682,2689
< system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 836500 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 1188500 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 9404000 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 23878500 # number of ReadCleanReq MSHR miss cycles
< system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 5430000 # number of ReadCleanReq MSHR miss cycles
< system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 217000 # number of ReadCleanReq MSHR miss cycles
< system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 364000 # number of ReadCleanReq MSHR miss cycles
< system.l2c.ReadCleanReq_mshr_miss_latency::total 29889500 # number of ReadCleanReq MSHR miss cycles
---
> system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1365500 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 1013500 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 9987000 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 23885500 # number of ReadCleanReq MSHR miss cycles
> system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 5496500 # number of ReadCleanReq MSHR miss cycles
> system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 363500 # number of ReadCleanReq MSHR miss cycles
> system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 146000 # number of ReadCleanReq MSHR miss cycles
> system.l2c.ReadCleanReq_mshr_miss_latency::total 29891500 # number of ReadCleanReq MSHR miss cycles
2692,2693c2692,2693
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 72500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 86500 # number of ReadSharedReq MSHR miss cycles
---
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 86500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 72500 # number of ReadSharedReq MSHR miss cycles
2695,2697c2695,2697
< system.l2c.demand_mshr_miss_latency::cpu0.inst 23878500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 11680500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 5430000 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu0.inst 23885500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 11909500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 5496500 # number of demand (read+write) MSHR miss cycles
2699,2706c2699,2706
< system.l2c.demand_mshr_miss_latency::cpu2.inst 217000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu2.data 909000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu3.inst 364000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu3.data 1275000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 45153500 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 23878500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 11680500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 5430000 # number of overall MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu2.inst 363500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu2.data 1452000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu3.inst 146000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu3.data 1086000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 45738500 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 23885500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 11909500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 5496500 # number of overall MSHR miss cycles
2708,2712c2708,2712
< system.l2c.overall_mshr_miss_latency::cpu2.inst 217000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu2.data 909000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu3.inst 364000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu3.data 1275000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 45153500 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::cpu2.inst 363500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu2.data 1452000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu3.inst 146000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu3.data 1086000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 45738500 # number of overall MSHR miss cycles
2717c2717
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.967391 # mshr miss rate for UpgradeReq accesses
---
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.966667 # mshr miss rate for UpgradeReq accesses
2724,2726c2724,2726
< system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for ReadCleanReq accesses
< system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for ReadCleanReq accesses
< system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for ReadCleanReq accesses
---
> system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.167339 # mshr miss rate for ReadCleanReq accesses
> system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.010000 # mshr miss rate for ReadCleanReq accesses
> system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for ReadCleanReq accesses
2735c2735
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for demand accesses
---
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.167339 # mshr miss rate for demand accesses
2737c2737
< system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for demand accesses
---
> system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010000 # mshr miss rate for demand accesses
2739c2739
< system.l2c.demand_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for demand accesses
---
> system.l2c.demand_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for demand accesses
2744c2744
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for overall accesses
---
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.167339 # mshr miss rate for overall accesses
2746c2746
< system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for overall accesses
---
> system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010000 # mshr miss rate for overall accesses
2748c2748
< system.l2c.overall_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for overall accesses
---
> system.l2c.overall_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for overall accesses
2751,2756c2751,2756
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20759.259259 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20842.105263 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20880.761905 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20886.318182 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20837.022472 # average UpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68617.021277 # average ReadExReq mshr miss latency
---
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21722.222222 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21763.157895 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 21800 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 21809.380952 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21770.080460 # average UpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 71053.191489 # average ReadExReq mshr miss latency
2758,2765c2758,2765
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69708.333333 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 99041.666667 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 71786.259542 # average ReadExReq mshr miss latency
< system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 66145.429363 # average ReadCleanReq mshr miss latency
< system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66219.512195 # average ReadCleanReq mshr miss latency
< system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72333.333333 # average ReadCleanReq mshr miss latency
< system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 72800 # average ReadCleanReq mshr miss latency
< system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 66273.835920 # average ReadCleanReq mshr miss latency
---
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 113791.666667 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 84458.333333 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 76236.641221 # average ReadExReq mshr miss latency
> system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 66164.819945 # average ReadCleanReq mshr miss latency
> system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66222.891566 # average ReadCleanReq mshr miss latency
> system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72700 # average ReadCleanReq mshr miss latency
> system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 73000 # average ReadCleanReq mshr miss latency
> system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 66278.270510 # average ReadCleanReq mshr miss latency
2768,2769c2768,2769
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72500 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 86500 # average ReadSharedReq mshr miss latency
---
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 86500 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 72500 # average ReadSharedReq mshr miss latency
2771,2773c2771,2773
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66145.429363 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 69115.384615 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66219.512195 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66164.819945 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 70470.414201 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66222.891566 # average overall mshr miss latency
2775,2782c2775,2782
< system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72333.333333 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu2.data 69923.076923 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 72800 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu3.data 98076.923077 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 67798.048048 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66145.429363 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 69115.384615 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66219.512195 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72700 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu2.data 111692.307692 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 73000 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu3.data 83538.461538 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 68676.426426 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66164.819945 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 70470.414201 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66222.891566 # average overall mshr miss latency
2784,2788c2784,2788
< system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72333.333333 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu2.data 69923.076923 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 72800 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu3.data 98076.923077 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 67798.048048 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72700 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu2.data 111692.307692 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 73000 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu3.data 83538.461538 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 68676.426426 # average overall mshr miss latency
2791,2793c2791,2793
< system.membus.trans_dist::UpgradeReq 292 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 89 # Transaction distribution
< system.membus.trans_dist::ReadExReq 161 # Transaction distribution
---
> system.membus.trans_dist::UpgradeReq 287 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 87 # Transaction distribution
> system.membus.trans_dist::ReadExReq 162 # Transaction distribution
2796,2797c2796,2797
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1742 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 1742 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1736 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1736 # Packet count per connected master and slave (bytes)
2800,2801c2800,2801
< system.membus.snoops 233 # Total snoops (count)
< system.membus.snoop_fanout::samples 988 # Request fanout histogram
---
> system.membus.snoops 231 # Total snoops (count)
> system.membus.snoop_fanout::samples 984 # Request fanout histogram
2805c2805
< system.membus.snoop_fanout::0 988 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 984 100.00% 100.00% # Request fanout histogram
2810,2811c2810,2811
< system.membus.snoop_fanout::total 988 # Request fanout histogram
< system.membus.reqLayer0.occupancy 929005 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 984 # Request fanout histogram
> system.membus.reqLayer0.occupancy 923503 # Layer occupancy (ticks)
2813,2815c2813,2821
< system.membus.respLayer1.occupancy 3712661 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 3.5 # Layer utilization (%)
< system.toL2Bus.trans_dist::ReadResp 2782 # Transaction distribution
---
> system.membus.respLayer1.occupancy 3708663 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 3.4 # Layer utilization (%)
> system.toL2Bus.snoop_filter.tot_requests 4928 # Total number of requests made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_requests 1339 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_requests 2358 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.trans_dist::ReadResp 2773 # Transaction distribution
2817,2821c2823,2827
< system.toL2Bus.trans_dist::CleanEvict 677 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 295 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 295 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 389 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 389 # Transaction distribution
---
> system.toL2Bus.trans_dist::CleanEvict 678 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 290 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 394 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 394 # Transaction distribution
2823c2829
< system.toL2Bus.trans_dist::ReadSharedReq 681 # Transaction distribution
---
> system.toL2Bus.trans_dist::ReadSharedReq 672 # Transaction distribution
2825c2831
< system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 595 # Packet count per connected master and slave (bytes)
---
> system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 592 # Packet count per connected master and slave (bytes)
2827,2832c2833,2838
< system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 380 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 374 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1141 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 357 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 6585 # Packet count per connected master and slave (bytes)
---
> system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 370 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1145 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 369 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1146 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 364 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 6575 # Packet count per connected master and slave (bytes)
2842,2845c2848,2851
< system.toL2Bus.snoops 1026 # Total snoops (count)
< system.toL2Bus.snoop_fanout::samples 4937 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.toL2Bus.snoops 1019 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 4928 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 1.293425 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 1.231126 # Request fanout histogram
2847,2854c2853,2860
< system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
< system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
< system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
< system.toL2Bus.snoop_fanout::7 4937 100.00% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::0 1910 38.76% 38.76% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 975 19.78% 58.54% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 730 14.81% 73.36% # Request fanout histogram
> system.toL2Bus.snoop_fanout::3 1313 26.64% 100.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram
2857,2860c2863,2866
< system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
< system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
< system.toL2Bus.snoop_fanout::total 4937 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 2487961 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
> system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
> system.toL2Bus.snoop_fanout::total 4928 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 2484958 # Layer occupancy (ticks)
2863,2864c2869,2870
< system.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%)
< system.toL2Bus.respLayer1.occupancy 509492 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%)
> system.toL2Bus.respLayer1.occupancy 505496 # Layer occupancy (ticks)
2868c2874
< system.toL2Bus.respLayer3.occupancy 443468 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer3.occupancy 435966 # Layer occupancy (ticks)
2870c2876
< system.toL2Bus.respLayer4.occupancy 752993 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer4.occupancy 752494 # Layer occupancy (ticks)
2872c2878
< system.toL2Bus.respLayer5.occupancy 440464 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer5.occupancy 426475 # Layer occupancy (ticks)
2874c2880
< system.toL2Bus.respLayer6.occupancy 747998 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer6.occupancy 748497 # Layer occupancy (ticks)
2876c2882
< system.toL2Bus.respLayer7.occupancy 407479 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer7.occupancy 424472 # Layer occupancy (ticks)