3,5c3,5
< sim_seconds 0.000106 # Number of seconds simulated
< sim_ticks 105542000 # Number of ticks simulated
< final_tick 105542000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000108 # Number of seconds simulated
> sim_ticks 107944000 # Number of ticks simulated
> final_tick 107944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 163449 # Simulator instruction rate (inst/s)
< host_op_rate 163449 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 17392605 # Simulator tick rate (ticks/s)
< host_mem_usage 309188 # Number of bytes of host memory used
< host_seconds 6.07 # Real time elapsed on the host
< sim_insts 991839 # Number of instructions simulated
< sim_ops 991839 # Number of ops (including micro ops) simulated
---
> host_inst_rate 162812 # Simulator instruction rate (inst/s)
> host_op_rate 162812 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 17679745 # Simulator tick rate (ticks/s)
> host_mem_usage 308116 # Number of bytes of host memory used
> host_seconds 6.11 # Real time elapsed on the host
> sim_insts 994048 # Number of instructions simulated
> sim_ops 994048 # Number of ops (including micro ops) simulated
16,22c16,22
< system.physmem.bytes_read::cpu0.inst 22976 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu2.inst 4864 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu3.inst 192 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.inst 23168 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu2.inst 448 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu3.inst 320 # Number of bytes read from this memory
24,36c24,36
< system.physmem.bytes_read::total 42496 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 22976 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu2.inst 4864 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu3.inst 192 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 28800 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu0.inst 359 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu2.inst 76 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu3.inst 3 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 42816 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 23168 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu2.inst 448 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu3.inst 320 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 29056 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu0.inst 362 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu2.inst 7 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu3.inst 5 # Number of read requests responded to by this memory
38,62c38,62
< system.physmem.num_reads::total 664 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu0.inst 217695325 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 101874135 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 7276724 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 7883118 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu2.inst 46085918 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu2.data 12127873 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu3.inst 1819181 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu3.data 7883118 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 402645392 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 217695325 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 7276724 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu2.inst 46085918 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu3.inst 1819181 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 272877148 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 217695325 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 101874135 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 7276724 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 7883118 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu2.inst 46085918 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu2.data 12127873 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu3.inst 1819181 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu3.data 7883118 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 402645392 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 665 # Number of read requests accepted
---
> system.physmem.num_reads::total 669 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu0.inst 214629808 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 100200104 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 47432002 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 11858000 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu2.inst 4150300 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu2.data 7707700 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu3.inst 2964500 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu3.data 7707700 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 396650115 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 214629808 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 47432002 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu2.inst 4150300 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu3.inst 2964500 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 269176610 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 214629808 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 100200104 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 47432002 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 11858000 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu2.inst 4150300 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu2.data 7707700 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu3.inst 2964500 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu3.data 7707700 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 396650115 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 670 # Number of read requests accepted
64c64
< system.physmem.readBursts 665 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 670 # Number of DRAM read bursts, including those serviced by the write queue
66c66
< system.physmem.bytesReadDRAM 42560 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 42880 # Total number of bytes read from DRAM
69c69
< system.physmem.bytesReadSys 42560 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 42880 # Total read bytes from the system interface side
73,74c73,74
< system.physmem.neitherReadNorWriteReqs 78 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 114 # Per bank write bursts
---
> system.physmem.neitherReadNorWriteReqs 76 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 115 # Per bank write bursts
78c78
< system.physmem.perBankRdBursts::4 65 # Per bank write bursts
---
> system.physmem.perBankRdBursts::4 66 # Per bank write bursts
83,85c83,85
< system.physmem.perBankRdBursts::9 28 # Per bank write bursts
< system.physmem.perBankRdBursts::10 22 # Per bank write bursts
< system.physmem.perBankRdBursts::11 13 # Per bank write bursts
---
> system.physmem.perBankRdBursts::9 29 # Per bank write bursts
> system.physmem.perBankRdBursts::10 23 # Per bank write bursts
> system.physmem.perBankRdBursts::11 14 # Per bank write bursts
108c108
< system.physmem.totGap 105514000 # Total gap between requests
---
> system.physmem.totGap 107916000 # Total gap between requests
115c115
< system.physmem.readPktSize::6 665 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 670 # Read request sizes (log2)
123,126c123,126
< system.physmem.rdQLenPdf::0 394 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 192 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 399 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 190 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see
219,236c219,236
< system.physmem.bytesPerActivate::samples 142 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 280.338028 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 190.767584 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 256.989000 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 41 28.87% 28.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 38 26.76% 55.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 26 18.31% 73.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 12 8.45% 82.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 6 4.23% 86.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 6 4.23% 90.85% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 6 4.23% 95.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 2 1.41% 96.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 5 3.52% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 142 # Bytes accessed per row activation
< system.physmem.totQLat 6421750 # Total ticks spent queuing
< system.physmem.totMemAccLat 18890500 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 3325000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 9656.77 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 148 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 270.702703 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 189.430987 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 234.776821 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 43 29.05% 29.05% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 39 26.35% 55.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 25 16.89% 72.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 19 12.84% 85.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 6 4.05% 89.19% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 6 4.05% 93.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 5 3.38% 96.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 2 1.35% 97.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 3 2.03% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 148 # Bytes accessed per row activation
> system.physmem.totQLat 6539750 # Total ticks spent queuing
> system.physmem.totMemAccLat 19102250 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 3350000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 9760.82 # Average queueing delay per DRAM burst
238,239c238,239
< system.physmem.avgMemAccLat 28406.77 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 403.25 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 28510.82 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 397.24 # Average DRAM read bandwidth in MiByte/s
241c241
< system.physmem.avgRdBWSys 403.25 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 397.24 # Average system read bandwidth in MiByte/s
244,245c244,245
< system.physmem.busUtil 3.15 # Data bus utilization in percentage
< system.physmem.busUtilRead 3.15 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 3.10 # Data bus utilization in percentage
> system.physmem.busUtilRead 3.10 # Data bus utilization in percentage for reads
247c247
< system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.39 # Average read queue length when enqueuing
249c249
< system.physmem.readRowHits 512 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 511 # Number of row buffer hits during reads
251c251
< system.physmem.readRowHitRate 76.99 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 76.27 # Row buffer hit rate for reads
253,257c253,257
< system.physmem.avgGap 158667.67 # Average gap between requests
< system.physmem.pageHitRate 76.99 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 687960 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 375375 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 2753400 # Energy for read commands per rank (pJ)
---
> system.physmem.avgGap 161068.66 # Average gap between requests
> system.physmem.pageHitRate 76.27 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 703080 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 383625 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 2761200 # Energy for read commands per rank (pJ)
260,264c260,264
< system.physmem_0.actBackEnergy 29877120 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 34680750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 74985885 # Total energy per rank (pJ)
< system.physmem_0.averagePower 738.913691 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 57973250 # Time in different power states
---
> system.physmem_0.actBackEnergy 39247065 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 26461500 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 76167750 # Total energy per rank (pJ)
> system.physmem_0.averagePower 750.559832 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 46478250 # Time in different power states
267c267
< system.physmem_0.memoryStateTime::ACT 40577250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 54316750 # Time in different power states
269,271c269,271
< system.physmem_1.actEnergy 355320 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 193875 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 2043600 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 385560 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 210375 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 2067000 # Energy for read commands per rank (pJ)
274,278c274,278
< system.physmem_1.actBackEnergy 27463455 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 36789750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 73457280 # Total energy per rank (pJ)
< system.physmem_1.averagePower 723.948851 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 62480000 # Time in different power states
---
> system.physmem_1.actBackEnergy 30855240 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 33814500 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 73943955 # Total energy per rank (pJ)
> system.physmem_1.averagePower 728.745214 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 59727000 # Time in different power states
281c281
< system.physmem_1.memoryStateTime::ACT 37046000 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 42022000 # Time in different power states
283,287c283,287
< system.cpu0.branchPred.lookups 81296 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 78365 # Number of conditional branches predicted
< system.cpu0.branchPred.condIncorrect 1199 # Number of conditional branches incorrect
< system.cpu0.branchPred.BTBLookups 77900 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 75117 # Number of BTB hits
---
> system.cpu0.branchPred.lookups 81450 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 78581 # Number of conditional branches predicted
> system.cpu0.branchPred.condIncorrect 1205 # Number of conditional branches incorrect
> system.cpu0.branchPred.BTBLookups 78182 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 75500 # Number of BTB hits
289,290c289,290
< system.cpu0.branchPred.BTBHitPct 96.427471 # BTB Hit Percentage
< system.cpu0.branchPred.usedRAS 763 # Number of times the RAS was used to get a target.
---
> system.cpu0.branchPred.BTBHitPct 96.569543 # BTB Hit Percentage
> system.cpu0.branchPred.usedRAS 747 # Number of times the RAS was used to get a target.
294c294
< system.cpu0.numCycles 211085 # number of cpu cycles simulated
---
> system.cpu0.numCycles 215889 # number of cpu cycles simulated
297,302c297,302
< system.cpu0.fetch.icacheStallCycles 20068 # Number of cycles fetch is stalled on an Icache miss
< system.cpu0.fetch.Insts 480268 # Number of instructions fetch has processed
< system.cpu0.fetch.Branches 81296 # Number of branches that fetch encountered
< system.cpu0.fetch.predictedBranches 75880 # Number of branches that fetch has predicted taken
< system.cpu0.fetch.Cycles 163785 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu0.fetch.SquashCycles 2699 # Number of cycles fetch has spent squashing
---
> system.cpu0.fetch.icacheStallCycles 20419 # Number of cycles fetch is stalled on an Icache miss
> system.cpu0.fetch.Insts 481443 # Number of instructions fetch has processed
> system.cpu0.fetch.Branches 81450 # Number of branches that fetch encountered
> system.cpu0.fetch.predictedBranches 76247 # Number of branches that fetch has predicted taken
> system.cpu0.fetch.Cycles 165590 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu0.fetch.SquashCycles 2709 # Number of cycles fetch has spent squashing
304,309c304,309
< system.cpu0.fetch.PendingTrapStallCycles 1916 # Number of stall cycles due to pending traps
< system.cpu0.fetch.CacheLines 7139 # Number of cache lines fetched
< system.cpu0.fetch.IcacheSquashes 648 # Number of outstanding Icache misses that were squashed
< system.cpu0.fetch.rateDist::samples 187121 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::mean 2.566617 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::stdev 2.228608 # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.PendingTrapStallCycles 2214 # Number of stall cycles due to pending traps
> system.cpu0.fetch.CacheLines 7225 # Number of cache lines fetched
> system.cpu0.fetch.IcacheSquashes 649 # Number of outstanding Icache misses that were squashed
> system.cpu0.fetch.rateDist::samples 189580 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::mean 2.539524 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::stdev 2.227640 # Number of instructions fetched each cycle (Total)
311,319c311,319
< system.cpu0.fetch.rateDist::0 30271 16.18% 16.18% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::1 77424 41.38% 57.55% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::2 764 0.41% 57.96% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::3 1076 0.58% 58.54% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::4 624 0.33% 58.87% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::5 72740 38.87% 97.74% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::6 718 0.38% 98.13% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::7 448 0.24% 98.37% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::8 3056 1.63% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.rateDist::0 32064 16.91% 16.91% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::1 77818 41.05% 57.96% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::2 818 0.43% 58.39% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::3 1146 0.60% 59.00% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::4 623 0.33% 59.33% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::5 72992 38.50% 97.83% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::6 703 0.37% 98.20% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::7 447 0.24% 98.43% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::8 2969 1.57% 100.00% # Number of instructions fetched each cycle (Total)
323,325c323,325
< system.cpu0.fetch.rateDist::total 187121 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.branchRate 0.385134 # Number of branch fetches per cycle
< system.cpu0.fetch.rate 2.275235 # Number of inst fetches per cycle
---
> system.cpu0.fetch.rateDist::total 189580 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.branchRate 0.377277 # Number of branch fetches per cycle
> system.cpu0.fetch.rate 2.230049 # Number of inst fetches per cycle
327,346c327,346
< system.cpu0.decode.BlockedCycles 17868 # Number of cycles decode is blocked
< system.cpu0.decode.RunCycles 151448 # Number of cycles decode is running
< system.cpu0.decode.UnblockCycles 678 # Number of cycles decode is unblocking
< system.cpu0.decode.SquashCycles 1349 # Number of cycles decode is squashing
< system.cpu0.decode.DecodedInsts 468198 # Number of instructions handled by decode
< system.cpu0.rename.SquashCycles 1349 # Number of cycles rename is squashing
< system.cpu0.rename.IdleCycles 16395 # Number of cycles rename is idle
< system.cpu0.rename.BlockCycles 2033 # Number of cycles rename is blocking
< system.cpu0.rename.serializeStallCycles 14616 # count of cycles rename stalled for serializing inst
< system.cpu0.rename.RunCycles 151464 # Number of cycles rename is running
< system.cpu0.rename.UnblockCycles 1264 # Number of cycles rename is unblocking
< system.cpu0.rename.RenamedInsts 464735 # Number of instructions processed by rename
< system.cpu0.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full
< system.cpu0.rename.LQFullEvents 19 # Number of times rename has blocked due to LQ full
< system.cpu0.rename.SQFullEvents 756 # Number of times rename has blocked due to SQ full
< system.cpu0.rename.RenamedOperands 318331 # Number of destination operands rename has renamed
< system.cpu0.rename.RenameLookups 926755 # Number of register rename lookups that rename has made
< system.cpu0.rename.int_rename_lookups 700443 # Number of integer rename lookups
< system.cpu0.rename.CommittedMaps 304259 # Number of HB maps that are committed
< system.cpu0.rename.UndoneMaps 14072 # Number of HB maps that are undone due to squashing
---
> system.cpu0.decode.BlockedCycles 19697 # Number of cycles decode is blocked
> system.cpu0.decode.RunCycles 152079 # Number of cycles decode is running
> system.cpu0.decode.UnblockCycles 672 # Number of cycles decode is unblocking
> system.cpu0.decode.SquashCycles 1354 # Number of cycles decode is squashing
> system.cpu0.decode.DecodedInsts 469796 # Number of instructions handled by decode
> system.cpu0.rename.SquashCycles 1354 # Number of cycles rename is squashing
> system.cpu0.rename.IdleCycles 16409 # Number of cycles rename is idle
> system.cpu0.rename.BlockCycles 2266 # Number of cycles rename is blocking
> system.cpu0.rename.serializeStallCycles 15970 # count of cycles rename stalled for serializing inst
> system.cpu0.rename.RunCycles 152076 # Number of cycles rename is running
> system.cpu0.rename.UnblockCycles 1505 # Number of cycles rename is unblocking
> system.cpu0.rename.RenamedInsts 466337 # Number of instructions processed by rename
> system.cpu0.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full
> system.cpu0.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full
> system.cpu0.rename.SQFullEvents 1001 # Number of times rename has blocked due to SQ full
> system.cpu0.rename.RenamedOperands 319451 # Number of destination operands rename has renamed
> system.cpu0.rename.RenameLookups 929999 # Number of register rename lookups that rename has made
> system.cpu0.rename.int_rename_lookups 702902 # Number of integer rename lookups
> system.cpu0.rename.CommittedMaps 305355 # Number of HB maps that are committed
> system.cpu0.rename.UndoneMaps 14096 # Number of HB maps that are undone due to squashing
348,363c348,363
< system.cpu0.rename.tempSerializingInsts 909 # count of temporary serializing insts renamed
< system.cpu0.rename.skidInsts 4585 # count of insts added to the skid buffer
< system.cpu0.memDep0.insertedLoads 148203 # Number of loads inserted to the mem dependence unit.
< system.cpu0.memDep0.insertedStores 75025 # Number of stores inserted to the mem dependence unit.
< system.cpu0.memDep0.conflictingLoads 72247 # Number of conflicting loads.
< system.cpu0.memDep0.conflictingStores 71998 # Number of conflicting stores.
< system.cpu0.iq.iqInstsAdded 388891 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu0.iq.iqNonSpecInstsAdded 968 # Number of non-speculative instructions added to the IQ
< system.cpu0.iq.iqInstsIssued 385538 # Number of instructions issued
< system.cpu0.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued
< system.cpu0.iq.iqSquashedInstsExamined 12303 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu0.iq.iqSquashedOperandsExamined 11219 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu0.iq.iqSquashedNonSpecRemoved 409 # Number of squashed non-spec instructions that were removed
< system.cpu0.iq.issued_per_cycle::samples 187121 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::mean 2.060367 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::stdev 1.127018 # Number of insts issued each cycle
---
> system.cpu0.rename.tempSerializingInsts 908 # count of temporary serializing insts renamed
> system.cpu0.rename.skidInsts 4587 # count of insts added to the skid buffer
> system.cpu0.memDep0.insertedLoads 148758 # Number of loads inserted to the mem dependence unit.
> system.cpu0.memDep0.insertedStores 75265 # Number of stores inserted to the mem dependence unit.
> system.cpu0.memDep0.conflictingLoads 72519 # Number of conflicting loads.
> system.cpu0.memDep0.conflictingStores 72258 # Number of conflicting stores.
> system.cpu0.iq.iqInstsAdded 390345 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu0.iq.iqNonSpecInstsAdded 967 # Number of non-speculative instructions added to the IQ
> system.cpu0.iq.iqInstsIssued 386997 # Number of instructions issued
> system.cpu0.iq.iqSquashedInstsIssued 24 # Number of squashed instructions issued
> system.cpu0.iq.iqSquashedInstsExamined 12329 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu0.iq.iqSquashedOperandsExamined 11208 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu0.iq.iqSquashedNonSpecRemoved 408 # Number of squashed non-spec instructions that were removed
> system.cpu0.iq.issued_per_cycle::samples 189580 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::mean 2.041339 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::stdev 1.140292 # Number of insts issued each cycle
365,373c365,373
< system.cpu0.iq.issued_per_cycle::0 33176 17.73% 17.73% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::1 4313 2.30% 20.03% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::2 73426 39.24% 59.27% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::3 72986 39.00% 98.28% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::4 1673 0.89% 99.17% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::5 893 0.48% 99.65% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::6 397 0.21% 99.86% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::7 180 0.10% 99.96% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::8 77 0.04% 100.00% # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::0 35140 18.54% 18.54% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::1 4258 2.25% 20.78% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::2 73622 38.83% 59.62% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::3 73334 38.68% 98.30% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::4 1646 0.87% 99.17% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::5 901 0.48% 99.64% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::6 423 0.22% 99.86% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::7 182 0.10% 99.96% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::8 74 0.04% 100.00% # Number of insts issued each cycle
377c377
< system.cpu0.iq.issued_per_cycle::total 187121 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::total 189580 # Number of insts issued each cycle
379,409c379,409
< system.cpu0.iq.fu_full::IntAlu 102 35.29% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntMult 0 0.00% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntDiv 0 0.00% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatAdd 0 0.00% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCmp 0 0.00% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCvt 0 0.00% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMult 0 0.00% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatDiv 0 0.00% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAdd 0 0.00% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAlu 0 0.00% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCmp 0 0.00% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCvt 0 0.00% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMisc 0 0.00% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMult 0 0.00% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShift 0 0.00% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 35.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemRead 84 29.07% 64.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemWrite 103 35.64% 100.00% # attempts to use FU when none available
---
> system.cpu0.iq.fu_full::IntAlu 91 32.73% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntMult 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntDiv 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatAdd 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCmp 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCvt 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMult 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatDiv 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAdd 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAlu 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCmp 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCvt 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMisc 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMult 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShift 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemRead 84 30.22% 62.95% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemWrite 103 37.05% 100.00% # attempts to use FU when none available
413,443c413,443
< system.cpu0.iq.FU_type_0::IntAlu 163537 42.42% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.42% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemRead 147667 38.30% 80.72% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemWrite 74334 19.28% 100.00% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::IntAlu 164205 42.43% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemRead 148197 38.29% 80.72% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemWrite 74595 19.28% 100.00% # Type of FU issued
446,452c446,452
< system.cpu0.iq.FU_type_0::total 385538 # Type of FU issued
< system.cpu0.iq.rate 1.826459 # Inst issue rate
< system.cpu0.iq.fu_busy_cnt 289 # FU busy when requested
< system.cpu0.iq.fu_busy_rate 0.000750 # FU busy rate (busy events/executed inst)
< system.cpu0.iq.int_inst_queue_reads 958509 # Number of integer instruction queue reads
< system.cpu0.iq.int_inst_queue_writes 402215 # Number of integer instruction queue writes
< system.cpu0.iq.int_inst_queue_wakeup_accesses 383670 # Number of integer instruction queue wakeup accesses
---
> system.cpu0.iq.FU_type_0::total 386997 # Type of FU issued
> system.cpu0.iq.rate 1.792574 # Inst issue rate
> system.cpu0.iq.fu_busy_cnt 278 # FU busy when requested
> system.cpu0.iq.fu_busy_rate 0.000718 # FU busy rate (busy events/executed inst)
> system.cpu0.iq.int_inst_queue_reads 963876 # Number of integer instruction queue reads
> system.cpu0.iq.int_inst_queue_writes 403692 # Number of integer instruction queue writes
> system.cpu0.iq.int_inst_queue_wakeup_accesses 385100 # Number of integer instruction queue wakeup accesses
456c456
< system.cpu0.iq.int_alu_accesses 385827 # Number of integer alu accesses
---
> system.cpu0.iq.int_alu_accesses 387275 # Number of integer alu accesses
458c458
< system.cpu0.iew.lsq.thread0.forwLoads 71619 # Number of loads that had data forwarded from stores
---
> system.cpu0.iew.lsq.thread0.forwLoads 71895 # Number of loads that had data forwarded from stores
460c460
< system.cpu0.iew.lsq.thread0.squashedLoads 2484 # Number of loads squashed
---
> system.cpu0.iew.lsq.thread0.squashedLoads 2491 # Number of loads squashed
462,463c462,463
< system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations
< system.cpu0.iew.lsq.thread0.squashedStores 1659 # Number of stores squashed
---
> system.cpu0.iew.lsq.thread0.memOrderViolation 53 # Number of memory ordering violations
> system.cpu0.iew.lsq.thread0.squashedStores 1625 # Number of stores squashed
467c467
< system.cpu0.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu0.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked
469,481c469,481
< system.cpu0.iew.iewSquashCycles 1349 # Number of cycles IEW is squashing
< system.cpu0.iew.iewBlockCycles 1995 # Number of cycles IEW is blocking
< system.cpu0.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking
< system.cpu0.iew.iewDispatchedInsts 462536 # Number of instructions dispatched to IQ
< system.cpu0.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch
< system.cpu0.iew.iewDispLoadInsts 148203 # Number of dispatched load instructions
< system.cpu0.iew.iewDispStoreInsts 75025 # Number of dispatched store instructions
< system.cpu0.iew.iewDispNonSpecInsts 847 # Number of dispatched non-speculative instructions
< system.cpu0.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall
< system.cpu0.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall
< system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations
< system.cpu0.iew.predictedTakenIncorrect 324 # Number of branches that were predicted taken incorrectly
< system.cpu0.iew.predictedNotTakenIncorrect 1113 # Number of branches that were predicted not taken incorrectly
---
> system.cpu0.iew.iewSquashCycles 1354 # Number of cycles IEW is squashing
> system.cpu0.iew.iewBlockCycles 2232 # Number of cycles IEW is blocking
> system.cpu0.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking
> system.cpu0.iew.iewDispatchedInsts 464248 # Number of instructions dispatched to IQ
> system.cpu0.iew.iewDispSquashedInsts 186 # Number of squashed instructions skipped by dispatch
> system.cpu0.iew.iewDispLoadInsts 148758 # Number of dispatched load instructions
> system.cpu0.iew.iewDispStoreInsts 75265 # Number of dispatched store instructions
> system.cpu0.iew.iewDispNonSpecInsts 846 # Number of dispatched non-speculative instructions
> system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall
> system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
> system.cpu0.iew.memOrderViolationEvents 53 # Number of memory order violations
> system.cpu0.iew.predictedTakenIncorrect 333 # Number of branches that were predicted taken incorrectly
> system.cpu0.iew.predictedNotTakenIncorrect 1104 # Number of branches that were predicted not taken incorrectly
483,485c483,485
< system.cpu0.iew.iewExecutedInsts 384525 # Number of executed instructions
< system.cpu0.iew.iewExecLoadInsts 147369 # Number of load instructions executed
< system.cpu0.iew.iewExecSquashedInsts 1013 # Number of squashed instructions skipped in execute
---
> system.cpu0.iew.iewExecutedInsts 385946 # Number of executed instructions
> system.cpu0.iew.iewExecLoadInsts 147890 # Number of load instructions executed
> system.cpu0.iew.iewExecSquashedInsts 1051 # Number of squashed instructions skipped in execute
487,495c487,495
< system.cpu0.iew.exec_nop 72677 # number of nop insts executed
< system.cpu0.iew.exec_refs 221564 # number of memory reference insts executed
< system.cpu0.iew.exec_branches 76264 # Number of branches executed
< system.cpu0.iew.exec_stores 74195 # Number of stores executed
< system.cpu0.iew.exec_rate 1.821660 # Inst execution rate
< system.cpu0.iew.wb_sent 384046 # cumulative count of insts sent to commit
< system.cpu0.iew.wb_count 383670 # cumulative count of insts written-back
< system.cpu0.iew.wb_producers 227520 # num instructions producing a value
< system.cpu0.iew.wb_consumers 230755 # num instructions consuming a value
---
> system.cpu0.iew.exec_nop 72936 # number of nop insts executed
> system.cpu0.iew.exec_refs 222349 # number of memory reference insts executed
> system.cpu0.iew.exec_branches 76534 # Number of branches executed
> system.cpu0.iew.exec_stores 74459 # Number of stores executed
> system.cpu0.iew.exec_rate 1.787706 # Inst execution rate
> system.cpu0.iew.wb_sent 385475 # cumulative count of insts sent to commit
> system.cpu0.iew.wb_count 385100 # cumulative count of insts written-back
> system.cpu0.iew.wb_producers 228400 # num instructions producing a value
> system.cpu0.iew.wb_consumers 231722 # num instructions consuming a value
497,498c497,498
< system.cpu0.iew.wb_rate 1.817609 # insts written-back per cycle
< system.cpu0.iew.wb_fanout 0.985981 # average fanout of values written-back
---
> system.cpu0.iew.wb_rate 1.783787 # insts written-back per cycle
> system.cpu0.iew.wb_fanout 0.985664 # average fanout of values written-back
500c500
< system.cpu0.commit.commitSquashedInsts 13745 # The number of squashed insts skipped by commit
---
> system.cpu0.commit.commitSquashedInsts 13801 # The number of squashed insts skipped by commit
502,505c502,505
< system.cpu0.commit.branchMispredicts 1199 # The number of times a branch was mispredicted
< system.cpu0.commit.committed_per_cycle::samples 184477 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::mean 2.432498 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::stdev 2.147629 # Number of insts commited each cycle
---
> system.cpu0.commit.branchMispredicts 1205 # The number of times a branch was mispredicted
> system.cpu0.commit.committed_per_cycle::samples 186928 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::mean 2.409398 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::stdev 2.152220 # Number of insts commited each cycle
507,515c507,515
< system.cpu0.commit.committed_per_cycle::0 33360 18.08% 18.08% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::1 75359 40.85% 58.93% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::2 2024 1.10% 60.03% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::3 644 0.35% 60.38% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::4 522 0.28% 60.66% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::5 71315 38.66% 99.32% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::6 520 0.28% 99.60% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::7 246 0.13% 99.74% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::8 487 0.26% 100.00% # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::0 35407 18.94% 18.94% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::1 75555 40.42% 59.36% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::2 1920 1.03% 60.39% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::3 633 0.34% 60.73% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::4 494 0.26% 60.99% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::5 71651 38.33% 99.32% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::6 511 0.27% 99.60% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::7 263 0.14% 99.74% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::8 494 0.26% 100.00% # Number of insts commited each cycle
519,521c519,521
< system.cpu0.commit.committed_per_cycle::total 184477 # Number of insts commited each cycle
< system.cpu0.commit.committedInsts 448740 # Number of instructions committed
< system.cpu0.commit.committedOps 448740 # Number of ops (including micro ops) committed
---
> system.cpu0.commit.committed_per_cycle::total 186928 # Number of insts commited each cycle
> system.cpu0.commit.committedInsts 450384 # Number of instructions committed
> system.cpu0.commit.committedOps 450384 # Number of ops (including micro ops) committed
523,524c523,524
< system.cpu0.commit.refs 219085 # Number of memory references committed
< system.cpu0.commit.loads 145719 # Number of loads committed
---
> system.cpu0.commit.refs 219907 # Number of memory references committed
> system.cpu0.commit.loads 146267 # Number of loads committed
526c526
< system.cpu0.commit.branches 75253 # Number of branches committed
---
> system.cpu0.commit.branches 75527 # Number of branches committed
528c528
< system.cpu0.commit.int_insts 302590 # Number of committed integer instructions.
---
> system.cpu0.commit.int_insts 303686 # Number of committed integer instructions.
530,561c530,561
< system.cpu0.commit.op_class_0::No_OpClass 71985 16.04% 16.04% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntAlu 157586 35.12% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.16% # Class of committed instruction
< system.cpu0.commit.op_class_0::MemRead 145803 32.49% 83.65% # Class of committed instruction
< system.cpu0.commit.op_class_0::MemWrite 73366 16.35% 100.00% # Class of committed instruction
---
> system.cpu0.commit.op_class_0::No_OpClass 72259 16.04% 16.04% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntAlu 158134 35.11% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemRead 146351 32.49% 83.65% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemWrite 73640 16.35% 100.00% # Class of committed instruction
564,565c564,565
< system.cpu0.commit.op_class_0::total 448740 # Class of committed instruction
< system.cpu0.commit.bw_lim_events 487 # number cycles where commit BW limit reached
---
> system.cpu0.commit.op_class_0::total 450384 # Class of committed instruction
> system.cpu0.commit.bw_lim_events 494 # number cycles where commit BW limit reached
567,578c567,578
< system.cpu0.rob.rob_reads 645314 # The number of ROB reads
< system.cpu0.rob.rob_writes 927635 # The number of ROB writes
< system.cpu0.timesIdled 318 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu0.idleCycles 23964 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu0.committedInsts 376671 # Number of Instructions Simulated
< system.cpu0.committedOps 376671 # Number of Ops (including micro ops) Simulated
< system.cpu0.cpi 0.560396 # CPI: Cycles Per Instruction
< system.cpu0.cpi_total 0.560396 # CPI: Total CPI of All Threads
< system.cpu0.ipc 1.784452 # IPC: Instructions Per Cycle
< system.cpu0.ipc_total 1.784452 # IPC: Total IPC of All Threads
< system.cpu0.int_regfile_reads 687652 # number of integer regfile reads
< system.cpu0.int_regfile_writes 310240 # number of integer regfile writes
---
> system.cpu0.rob.rob_reads 649458 # The number of ROB reads
> system.cpu0.rob.rob_writes 931043 # The number of ROB writes
> system.cpu0.timesIdled 314 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu0.idleCycles 26309 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu0.committedInsts 378041 # Number of Instructions Simulated
> system.cpu0.committedOps 378041 # Number of Ops (including micro ops) Simulated
> system.cpu0.cpi 0.571073 # CPI: Cycles Per Instruction
> system.cpu0.cpi_total 0.571073 # CPI: Total CPI of All Threads
> system.cpu0.ipc 1.751090 # IPC: Instructions Per Cycle
> system.cpu0.ipc_total 1.751090 # IPC: Total IPC of All Threads
> system.cpu0.int_regfile_reads 690199 # number of integer regfile reads
> system.cpu0.int_regfile_writes 311415 # number of integer regfile writes
580c580
< system.cpu0.misc_regfile_reads 223454 # number of misc regfile reads
---
> system.cpu0.misc_regfile_reads 224240 # number of misc regfile reads
583,586c583,586
< system.cpu0.dcache.tags.tagsinuse 141.523626 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 147885 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 869.911765 # Average number of references to valid blocks.
---
> system.cpu0.dcache.tags.tagsinuse 140.939988 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 148370 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 867.660819 # Average number of references to valid blocks.
588,631c588,631
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.523626 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.276413 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.276413 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id
< system.cpu0.dcache.tags.occ_task_id_percent::1024 0.328125 # Percentage of cache occupancy per task id
< system.cpu0.dcache.tags.tag_accesses 596477 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 596477 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 75193 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 75193 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 72780 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 72780 # number of WriteReq hits
< system.cpu0.dcache.SwapReq_hits::cpu0.data 20 # number of SwapReq hits
< system.cpu0.dcache.SwapReq_hits::total 20 # number of SwapReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 147973 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 147973 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 147973 # number of overall hits
< system.cpu0.dcache.overall_hits::total 147973 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 482 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 482 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 544 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 544 # number of WriteReq misses
< system.cpu0.dcache.SwapReq_misses::cpu0.data 22 # number of SwapReq misses
< system.cpu0.dcache.SwapReq_misses::total 22 # number of SwapReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 1026 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 1026 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 1026 # number of overall misses
< system.cpu0.dcache.overall_misses::total 1026 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 15529368 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 15529368 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32868763 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 32868763 # number of WriteReq miss cycles
< system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 428750 # number of SwapReq miss cycles
< system.cpu0.dcache.SwapReq_miss_latency::total 428750 # number of SwapReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 48398131 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 48398131 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 48398131 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 48398131 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 75675 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 75675 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 73324 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 73324 # number of WriteReq accesses(hits+misses)
---
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 140.939988 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275273 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.275273 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id
> system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 # Percentage of cache occupancy per task id
> system.cpu0.dcache.tags.tag_accesses 598524 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 598524 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 75399 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 75399 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 73059 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 73059 # number of WriteReq hits
> system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits
> system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 148458 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 148458 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 148458 # number of overall hits
> system.cpu0.dcache.overall_hits::total 148458 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 514 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 514 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 539 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 539 # number of WriteReq misses
> system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses
> system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 1053 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 1053 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 1053 # number of overall misses
> system.cpu0.dcache.overall_misses::total 1053 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17626915 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 17626915 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36442515 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 36442515 # number of WriteReq miss cycles
> system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 680000 # number of SwapReq miss cycles
> system.cpu0.dcache.SwapReq_miss_latency::total 680000 # number of SwapReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 54069430 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 54069430 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 54069430 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 54069430 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 75913 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 75913 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 73598 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 73598 # number of WriteReq accesses(hits+misses)
634,658c634,658
< system.cpu0.dcache.demand_accesses::cpu0.data 148999 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 148999 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 148999 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 148999 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006369 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.006369 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007419 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.007419 # miss rate for WriteReq accesses
< system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.523810 # miss rate for SwapReq accesses
< system.cpu0.dcache.SwapReq_miss_rate::total 0.523810 # miss rate for SwapReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006886 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.006886 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006886 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.006886 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32218.605809 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 32218.605809 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 60420.520221 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 60420.520221 # average WriteReq miss latency
< system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19488.636364 # average SwapReq miss latency
< system.cpu0.dcache.SwapReq_avg_miss_latency::total 19488.636364 # average SwapReq miss latency
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47171.667641 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 47171.667641 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47171.667641 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 47171.667641 # average overall miss latency
< system.cpu0.dcache.blocked_cycles::no_mshrs 754 # number of cycles access was blocked
---
> system.cpu0.dcache.demand_accesses::cpu0.data 149511 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 149511 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 149511 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 149511 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006771 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.006771 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007324 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.007324 # miss rate for WriteReq accesses
> system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses
> system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007043 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.007043 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007043 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.007043 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34293.608949 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 34293.608949 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67611.345083 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 67611.345083 # average WriteReq miss latency
> system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 32380.952381 # average SwapReq miss latency
> system.cpu0.dcache.SwapReq_avg_miss_latency::total 32380.952381 # average SwapReq miss latency
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 51347.986705 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 51347.986705 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 51347.986705 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 51347.986705 # average overall miss latency
> system.cpu0.dcache.blocked_cycles::no_mshrs 1036 # number of cycles access was blocked
660c660
< system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked
---
> system.cpu0.dcache.blocked::no_mshrs 13 # number of cycles access was blocked
662c662
< system.cpu0.dcache.avg_blocked_cycles::no_mshrs 27.925926 # average number of cycles each access was blocked
---
> system.cpu0.dcache.avg_blocked_cycles::no_mshrs 79.692308 # average number of cycles each access was blocked
668,715c668,715
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 299 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 365 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 365 # number of WriteReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 664 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 664 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 664 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 664 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 183 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 179 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 179 # number of WriteReq MSHR misses
< system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 22 # number of SwapReq MSHR misses
< system.cpu0.dcache.SwapReq_mshr_misses::total 22 # number of SwapReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6541511 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6541511 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7390227 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7390227 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 383250 # number of SwapReq MSHR miss cycles
< system.cpu0.dcache.SwapReq_mshr_miss_latency::total 383250 # number of SwapReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13931738 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 13931738 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13931738 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 13931738 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002418 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002418 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002441 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002441 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.523810 # mshr miss rate for SwapReq accesses
< system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.523810 # mshr miss rate for SwapReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002430 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.002430 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002430 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.002430 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 35745.961749 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 35745.961749 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41286.184358 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41286.184358 # average WriteReq mshr miss latency
< system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17420.454545 # average SwapReq mshr miss latency
< system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17420.454545 # average SwapReq mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 38485.464088 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38485.464088 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38485.464088 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38485.464088 # average overall mshr miss latency
---
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 330 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 330 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 362 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 362 # number of WriteReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 692 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 692 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 692 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 692 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 184 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 184 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 177 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 177 # number of WriteReq MSHR misses
> system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses
> system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 361 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 361 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 361 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6770753 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6770753 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8530978 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8530978 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 646500 # number of SwapReq MSHR miss cycles
> system.cpu0.dcache.SwapReq_mshr_miss_latency::total 646500 # number of SwapReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15301731 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 15301731 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15301731 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 15301731 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002424 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002424 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002405 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002405 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses
> system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002415 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.002415 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002415 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.002415 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 36797.570652 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 36797.570652 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48197.615819 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48197.615819 # average WriteReq mshr miss latency
> system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 30785.714286 # average SwapReq mshr miss latency
> system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 30785.714286 # average SwapReq mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42387.066482 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42387.066482 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42387.066482 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42387.066482 # average overall mshr miss latency
717,721c717,721
< system.cpu0.icache.tags.replacements 319 # number of replacements
< system.cpu0.icache.tags.tagsinuse 239.733862 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 6347 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 608 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 10.439145 # Average number of references to valid blocks.
---
> system.cpu0.icache.tags.replacements 323 # number of replacements
> system.cpu0.icache.tags.tagsinuse 240.188663 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 6428 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 614 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 10.469055 # Average number of references to valid blocks.
723,726c723,726
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 239.733862 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.468230 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.468230 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_task_id_blocks::1024 289 # Occupied blocks per task id
---
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 240.188663 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.469118 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.469118 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_task_id_blocks::1024 291 # Occupied blocks per task id
728,768c728,768
< system.cpu0.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id
< system.cpu0.icache.tags.occ_task_id_percent::1024 0.564453 # Percentage of cache occupancy per task id
< system.cpu0.icache.tags.tag_accesses 7747 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 7747 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 6347 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 6347 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 6347 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 6347 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 6347 # number of overall hits
< system.cpu0.icache.overall_hits::total 6347 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 792 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 792 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 792 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 792 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 792 # number of overall misses
< system.cpu0.icache.overall_misses::total 792 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 36432996 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 36432996 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 36432996 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 36432996 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 36432996 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 36432996 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 7139 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 7139 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 7139 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 7139 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 7139 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 7139 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110940 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.110940 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110940 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.110940 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110940 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.110940 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46001.257576 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 46001.257576 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46001.257576 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 46001.257576 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46001.257576 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 46001.257576 # average overall miss latency
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id
> system.cpu0.icache.tags.occ_task_id_percent::1024 0.568359 # Percentage of cache occupancy per task id
> system.cpu0.icache.tags.tag_accesses 7839 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 7839 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 6428 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 6428 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 6428 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 6428 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 6428 # number of overall hits
> system.cpu0.icache.overall_hits::total 6428 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 797 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 797 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 797 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 797 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 797 # number of overall misses
> system.cpu0.icache.overall_misses::total 797 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40514746 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 40514746 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 40514746 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 40514746 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 40514746 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 40514746 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 7225 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 7225 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 7225 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 7225 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 7225 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 7225 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110311 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.110311 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110311 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.110311 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110311 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.110311 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 50834.060226 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 50834.060226 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 50834.060226 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 50834.060226 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 50834.060226 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 50834.060226 # average overall miss latency
777,806c777,806
< system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 183 # number of ReadReq MSHR hits
< system.cpu0.icache.ReadReq_mshr_hits::total 183 # number of ReadReq MSHR hits
< system.cpu0.icache.demand_mshr_hits::cpu0.inst 183 # number of demand (read+write) MSHR hits
< system.cpu0.icache.demand_mshr_hits::total 183 # number of demand (read+write) MSHR hits
< system.cpu0.icache.overall_mshr_hits::cpu0.inst 183 # number of overall MSHR hits
< system.cpu0.icache.overall_mshr_hits::total 183 # number of overall MSHR hits
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 609 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 609 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 609 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 609 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 609 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 609 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27995751 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 27995751 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27995751 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 27995751 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27995751 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 27995751 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085306 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.085306 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.085306 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 45970.034483 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 45970.034483 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 45970.034483 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 45970.034483 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 45970.034483 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 45970.034483 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 182 # number of ReadReq MSHR hits
> system.cpu0.icache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits
> system.cpu0.icache.demand_mshr_hits::cpu0.inst 182 # number of demand (read+write) MSHR hits
> system.cpu0.icache.demand_mshr_hits::total 182 # number of demand (read+write) MSHR hits
> system.cpu0.icache.overall_mshr_hits::cpu0.inst 182 # number of overall MSHR hits
> system.cpu0.icache.overall_mshr_hits::total 182 # number of overall MSHR hits
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 615 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 615 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 615 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 615 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 615 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 615 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31043001 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 31043001 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31043001 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 31043001 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31043001 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 31043001 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.085121 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085121 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.085121 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.085121 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.085121 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.085121 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 50476.424390 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 50476.424390 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 50476.424390 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 50476.424390 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 50476.424390 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 50476.424390 # average overall mshr miss latency
808,812c808,812
< system.cpu1.branchPred.lookups 48230 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 44811 # Number of conditional branches predicted
< system.cpu1.branchPred.condIncorrect 1266 # Number of conditional branches incorrect
< system.cpu1.branchPred.BTBLookups 41091 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 39963 # Number of BTB hits
---
> system.cpu1.branchPred.lookups 52261 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 48386 # Number of conditional branches predicted
> system.cpu1.branchPred.condIncorrect 1341 # Number of conditional branches incorrect
> system.cpu1.branchPred.BTBLookups 44394 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 43169 # Number of BTB hits
814,815c814,815
< system.cpu1.branchPred.BTBHitPct 97.254873 # BTB Hit Percentage
< system.cpu1.branchPred.usedRAS 868 # Number of times the RAS was used to get a target.
---
> system.cpu1.branchPred.BTBHitPct 97.240618 # BTB Hit Percentage
> system.cpu1.branchPred.usedRAS 906 # Number of times the RAS was used to get a target.
817c817
< system.cpu1.numCycles 160735 # number of cpu cycles simulated
---
> system.cpu1.numCycles 162232 # number of cpu cycles simulated
820,825c820,825
< system.cpu1.fetch.icacheStallCycles 33641 # Number of cycles fetch is stalled on an Icache miss
< system.cpu1.fetch.Insts 261327 # Number of instructions fetch has processed
< system.cpu1.fetch.Branches 48230 # Number of branches that fetch encountered
< system.cpu1.fetch.predictedBranches 40831 # Number of branches that fetch has predicted taken
< system.cpu1.fetch.Cycles 122936 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu1.fetch.SquashCycles 2691 # Number of cycles fetch has spent squashing
---
> system.cpu1.fetch.icacheStallCycles 31153 # Number of cycles fetch is stalled on an Icache miss
> system.cpu1.fetch.Insts 288417 # Number of instructions fetch has processed
> system.cpu1.fetch.Branches 52261 # Number of branches that fetch encountered
> system.cpu1.fetch.predictedBranches 44075 # Number of branches that fetch has predicted taken
> system.cpu1.fetch.Cycles 122623 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu1.fetch.SquashCycles 2833 # Number of cycles fetch has spent squashing
828,833c828,833
< system.cpu1.fetch.PendingTrapStallCycles 1065 # Number of stall cycles due to pending traps
< system.cpu1.fetch.CacheLines 24854 # Number of cache lines fetched
< system.cpu1.fetch.IcacheSquashes 432 # Number of outstanding Icache misses that were squashed
< system.cpu1.fetch.rateDist::samples 159000 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::mean 1.643566 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::stdev 2.124362 # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.PendingTrapStallCycles 1159 # Number of stall cycles due to pending traps
> system.cpu1.fetch.CacheLines 21623 # Number of cache lines fetched
> system.cpu1.fetch.IcacheSquashes 472 # Number of outstanding Icache misses that were squashed
> system.cpu1.fetch.rateDist::samples 156364 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::mean 1.844523 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::stdev 2.218152 # Number of instructions fetched each cycle (Total)
835,843c835,843
< system.cpu1.fetch.rateDist::0 63867 40.17% 40.17% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::1 48973 30.80% 70.97% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::2 8266 5.20% 76.17% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::3 3472 2.18% 78.35% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::4 1057 0.66% 79.02% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::5 27547 17.33% 96.34% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::6 1174 0.74% 97.08% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::7 753 0.47% 97.55% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::8 3891 2.45% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::0 56063 35.85% 35.85% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::1 50599 32.36% 68.21% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::2 6236 3.99% 72.20% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::3 3531 2.26% 74.46% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::4 937 0.60% 75.06% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::5 32564 20.83% 95.89% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::6 1222 0.78% 96.67% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::7 843 0.54% 97.21% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::8 4369 2.79% 100.00% # Number of instructions fetched each cycle (Total)
847,887c847,887
< system.cpu1.fetch.rateDist::total 159000 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.branchRate 0.300059 # Number of branch fetches per cycle
< system.cpu1.fetch.rate 1.625825 # Number of inst fetches per cycle
< system.cpu1.decode.IdleCycles 17613 # Number of cycles decode is idle
< system.cpu1.decode.BlockedCycles 67674 # Number of cycles decode is blocked
< system.cpu1.decode.RunCycles 68228 # Number of cycles decode is running
< system.cpu1.decode.UnblockCycles 4130 # Number of cycles decode is unblocking
< system.cpu1.decode.SquashCycles 1345 # Number of cycles decode is squashing
< system.cpu1.decode.DecodedInsts 247069 # Number of instructions handled by decode
< system.cpu1.rename.SquashCycles 1345 # Number of cycles rename is squashing
< system.cpu1.rename.IdleCycles 18292 # Number of cycles rename is idle
< system.cpu1.rename.BlockCycles 33178 # Number of cycles rename is blocking
< system.cpu1.rename.serializeStallCycles 12317 # count of cycles rename stalled for serializing inst
< system.cpu1.rename.RunCycles 69139 # Number of cycles rename is running
< system.cpu1.rename.UnblockCycles 24719 # Number of cycles rename is unblocking
< system.cpu1.rename.RenamedInsts 243777 # Number of instructions processed by rename
< system.cpu1.rename.IQFullEvents 21468 # Number of times rename has blocked due to IQ full
< system.cpu1.rename.LQFullEvents 22 # Number of times rename has blocked due to LQ full
< system.cpu1.rename.FullRegisterEvents 3 # Number of times there has been no free registers
< system.cpu1.rename.RenamedOperands 169834 # Number of destination operands rename has renamed
< system.cpu1.rename.RenameLookups 458131 # Number of register rename lookups that rename has made
< system.cpu1.rename.int_rename_lookups 358650 # Number of integer rename lookups
< system.cpu1.rename.CommittedMaps 155489 # Number of HB maps that are committed
< system.cpu1.rename.UndoneMaps 14345 # Number of HB maps that are undone due to squashing
< system.cpu1.rename.serializingInsts 1180 # count of serializing insts renamed
< system.cpu1.rename.tempSerializingInsts 1243 # count of temporary serializing insts renamed
< system.cpu1.rename.skidInsts 29340 # count of insts added to the skid buffer
< system.cpu1.memDep0.insertedLoads 66237 # Number of loads inserted to the mem dependence unit.
< system.cpu1.memDep0.insertedStores 30368 # Number of stores inserted to the mem dependence unit.
< system.cpu1.memDep0.conflictingLoads 32190 # Number of conflicting loads.
< system.cpu1.memDep0.conflictingStores 25244 # Number of conflicting stores.
< system.cpu1.iq.iqInstsAdded 200152 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu1.iq.iqNonSpecInstsAdded 7929 # Number of non-speculative instructions added to the IQ
< system.cpu1.iq.iqInstsIssued 203048 # Number of instructions issued
< system.cpu1.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued
< system.cpu1.iq.iqSquashedInstsExamined 12672 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu1.iq.iqSquashedOperandsExamined 11906 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu1.iq.iqSquashedNonSpecRemoved 679 # Number of squashed non-spec instructions that were removed
< system.cpu1.iq.issued_per_cycle::samples 159000 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::mean 1.277031 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::stdev 1.370207 # Number of insts issued each cycle
---
> system.cpu1.fetch.rateDist::total 156364 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.branchRate 0.322137 # Number of branch fetches per cycle
> system.cpu1.fetch.rate 1.777806 # Number of inst fetches per cycle
> system.cpu1.decode.IdleCycles 18077 # Number of cycles decode is idle
> system.cpu1.decode.BlockedCycles 54814 # Number of cycles decode is blocked
> system.cpu1.decode.RunCycles 78767 # Number of cycles decode is running
> system.cpu1.decode.UnblockCycles 3280 # Number of cycles decode is unblocking
> system.cpu1.decode.SquashCycles 1416 # Number of cycles decode is squashing
> system.cpu1.decode.DecodedInsts 271927 # Number of instructions handled by decode
> system.cpu1.rename.SquashCycles 1416 # Number of cycles rename is squashing
> system.cpu1.rename.IdleCycles 18807 # Number of cycles rename is idle
> system.cpu1.rename.BlockCycles 25020 # Number of cycles rename is blocking
> system.cpu1.rename.serializeStallCycles 13667 # count of cycles rename stalled for serializing inst
> system.cpu1.rename.RunCycles 79411 # Number of cycles rename is running
> system.cpu1.rename.UnblockCycles 18033 # Number of cycles rename is unblocking
> system.cpu1.rename.RenamedInsts 268621 # Number of instructions processed by rename
> system.cpu1.rename.IQFullEvents 15397 # Number of times rename has blocked due to IQ full
> system.cpu1.rename.LQFullEvents 31 # Number of times rename has blocked due to LQ full
> system.cpu1.rename.FullRegisterEvents 6 # Number of times there has been no free registers
> system.cpu1.rename.RenamedOperands 189765 # Number of destination operands rename has renamed
> system.cpu1.rename.RenameLookups 514915 # Number of register rename lookups that rename has made
> system.cpu1.rename.int_rename_lookups 401460 # Number of integer rename lookups
> system.cpu1.rename.CommittedMaps 175087 # Number of HB maps that are committed
> system.cpu1.rename.UndoneMaps 14678 # Number of HB maps that are undone due to squashing
> system.cpu1.rename.serializingInsts 1212 # count of serializing insts renamed
> system.cpu1.rename.tempSerializingInsts 1278 # count of temporary serializing insts renamed
> system.cpu1.rename.skidInsts 22640 # count of insts added to the skid buffer
> system.cpu1.memDep0.insertedLoads 74986 # Number of loads inserted to the mem dependence unit.
> system.cpu1.memDep0.insertedStores 35614 # Number of stores inserted to the mem dependence unit.
> system.cpu1.memDep0.conflictingLoads 35483 # Number of conflicting loads.
> system.cpu1.memDep0.conflictingStores 30428 # Number of conflicting stores.
> system.cpu1.iq.iqInstsAdded 223482 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu1.iq.iqNonSpecInstsAdded 6146 # Number of non-speculative instructions added to the IQ
> system.cpu1.iq.iqInstsIssued 225009 # Number of instructions issued
> system.cpu1.iq.iqSquashedInstsIssued 16 # Number of squashed instructions issued
> system.cpu1.iq.iqSquashedInstsExamined 12719 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu1.iq.iqSquashedOperandsExamined 10743 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu1.iq.iqSquashedNonSpecRemoved 680 # Number of squashed non-spec instructions that were removed
> system.cpu1.iq.issued_per_cycle::samples 156364 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::mean 1.439008 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::stdev 1.385420 # Number of insts issued each cycle
889,897c889,897
< system.cpu1.iq.issued_per_cycle::0 67764 42.62% 42.62% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::1 26124 16.43% 59.05% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::2 29595 18.61% 77.66% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::3 29204 18.37% 96.03% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::4 3405 2.14% 98.17% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::5 1592 1.00% 99.17% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::6 880 0.55% 99.73% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::7 226 0.14% 99.87% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::8 210 0.13% 100.00% # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::0 59519 38.06% 38.06% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::1 20894 13.36% 51.43% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::2 35016 22.39% 73.82% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::3 34585 22.12% 95.94% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::4 3417 2.19% 98.12% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::5 1600 1.02% 99.15% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::6 882 0.56% 99.71% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::7 240 0.15% 99.87% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::8 211 0.13% 100.00% # Number of insts issued each cycle
901c901
< system.cpu1.iq.issued_per_cycle::total 159000 # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::total 156364 # Number of insts issued each cycle
903,933c903,933
< system.cpu1.iq.fu_full::IntAlu 87 24.30% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntMult 0 0.00% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntDiv 0 0.00% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatAdd 0 0.00% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCmp 0 0.00% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCvt 0 0.00% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMult 0 0.00% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatDiv 0 0.00% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAdd 0 0.00% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAlu 0 0.00% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCmp 0 0.00% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCvt 0 0.00% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMisc 0 0.00% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMult 0 0.00% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShift 0 0.00% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 24.30% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemRead 62 17.32% 41.62% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemWrite 209 58.38% 100.00% # attempts to use FU when none available
---
> system.cpu1.iq.fu_full::IntAlu 92 27.88% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntMult 0 0.00% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntDiv 0 0.00% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.88% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemRead 29 8.79% 36.67% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemWrite 209 63.33% 100.00% # attempts to use FU when none available
937,967c937,967
< system.cpu1.iq.FU_type_0::IntAlu 101499 49.99% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.99% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemRead 71903 35.41% 85.40% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemWrite 29646 14.60% 100.00% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::IntAlu 110922 49.30% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.30% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemRead 79078 35.14% 84.44% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemWrite 35009 15.56% 100.00% # Type of FU issued
970,976c970,976
< system.cpu1.iq.FU_type_0::total 203048 # Type of FU issued
< system.cpu1.iq.rate 1.263247 # Inst issue rate
< system.cpu1.iq.fu_busy_cnt 358 # FU busy when requested
< system.cpu1.iq.fu_busy_rate 0.001763 # FU busy rate (busy events/executed inst)
< system.cpu1.iq.int_inst_queue_reads 565493 # Number of integer instruction queue reads
< system.cpu1.iq.int_inst_queue_writes 220798 # Number of integer instruction queue writes
< system.cpu1.iq.int_inst_queue_wakeup_accesses 201375 # Number of integer instruction queue wakeup accesses
---
> system.cpu1.iq.FU_type_0::total 225009 # Type of FU issued
> system.cpu1.iq.rate 1.386958 # Inst issue rate
> system.cpu1.iq.fu_busy_cnt 330 # FU busy when requested
> system.cpu1.iq.fu_busy_rate 0.001467 # FU busy rate (busy events/executed inst)
> system.cpu1.iq.int_inst_queue_reads 606728 # Number of integer instruction queue reads
> system.cpu1.iq.int_inst_queue_writes 242381 # Number of integer instruction queue writes
> system.cpu1.iq.int_inst_queue_wakeup_accesses 223369 # Number of integer instruction queue wakeup accesses
980c980
< system.cpu1.iq.int_alu_accesses 203406 # Number of integer alu accesses
---
> system.cpu1.iq.int_alu_accesses 225339 # Number of integer alu accesses
982c982
< system.cpu1.iew.lsq.thread0.forwLoads 24951 # Number of loads that had data forwarded from stores
---
> system.cpu1.iew.lsq.thread0.forwLoads 30296 # Number of loads that had data forwarded from stores
984c984
< system.cpu1.iew.lsq.thread0.squashedLoads 2787 # Number of loads squashed
---
> system.cpu1.iew.lsq.thread0.squashedLoads 2626 # Number of loads squashed
986,987c986,987
< system.cpu1.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations
< system.cpu1.iew.lsq.thread0.squashedStores 1647 # Number of stores squashed
---
> system.cpu1.iew.lsq.thread0.memOrderViolation 34 # Number of memory ordering violations
> system.cpu1.iew.lsq.thread0.squashedStores 1552 # Number of stores squashed
993,1001c993,1001
< system.cpu1.iew.iewSquashCycles 1345 # Number of cycles IEW is squashing
< system.cpu1.iew.iewBlockCycles 8539 # Number of cycles IEW is blocking
< system.cpu1.iew.iewUnblockCycles 65 # Number of cycles IEW is unblocking
< system.cpu1.iew.iewDispatchedInsts 241028 # Number of instructions dispatched to IQ
< system.cpu1.iew.iewDispSquashedInsts 239 # Number of squashed instructions skipped by dispatch
< system.cpu1.iew.iewDispLoadInsts 66237 # Number of dispatched load instructions
< system.cpu1.iew.iewDispStoreInsts 30368 # Number of dispatched store instructions
< system.cpu1.iew.iewDispNonSpecInsts 1097 # Number of dispatched non-speculative instructions
< system.cpu1.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall
---
> system.cpu1.iew.iewSquashCycles 1416 # Number of cycles IEW is squashing
> system.cpu1.iew.iewBlockCycles 7338 # Number of cycles IEW is blocking
> system.cpu1.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking
> system.cpu1.iew.iewDispatchedInsts 266019 # Number of instructions dispatched to IQ
> system.cpu1.iew.iewDispSquashedInsts 165 # Number of squashed instructions skipped by dispatch
> system.cpu1.iew.iewDispLoadInsts 74986 # Number of dispatched load instructions
> system.cpu1.iew.iewDispStoreInsts 35614 # Number of dispatched store instructions
> system.cpu1.iew.iewDispNonSpecInsts 1143 # Number of dispatched non-speculative instructions
> system.cpu1.iew.iewIQFullEvents 24 # Number of times the IQ has become full, causing a stall
1003,1009c1003,1009
< system.cpu1.iew.memOrderViolationEvents 45 # Number of memory order violations
< system.cpu1.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly
< system.cpu1.iew.predictedNotTakenIncorrect 1009 # Number of branches that were predicted not taken incorrectly
< system.cpu1.iew.branchMispredicts 1474 # Number of branch mispredicts detected at execute
< system.cpu1.iew.iewExecutedInsts 201951 # Number of executed instructions
< system.cpu1.iew.iewExecLoadInsts 65061 # Number of load instructions executed
< system.cpu1.iew.iewExecSquashedInsts 1097 # Number of squashed instructions skipped in execute
---
> system.cpu1.iew.memOrderViolationEvents 34 # Number of memory order violations
> system.cpu1.iew.predictedTakenIncorrect 453 # Number of branches that were predicted taken incorrectly
> system.cpu1.iew.predictedNotTakenIncorrect 1125 # Number of branches that were predicted not taken incorrectly
> system.cpu1.iew.branchMispredicts 1578 # Number of branch mispredicts detected at execute
> system.cpu1.iew.iewExecutedInsts 223948 # Number of executed instructions
> system.cpu1.iew.iewExecLoadInsts 74035 # Number of load instructions executed
> system.cpu1.iew.iewExecSquashedInsts 1061 # Number of squashed instructions skipped in execute
1011,1019c1011,1019
< system.cpu1.iew.exec_nop 32947 # number of nop insts executed
< system.cpu1.iew.exec_refs 94595 # number of memory reference insts executed
< system.cpu1.iew.exec_branches 42219 # Number of branches executed
< system.cpu1.iew.exec_stores 29534 # Number of stores executed
< system.cpu1.iew.exec_rate 1.256422 # Inst execution rate
< system.cpu1.iew.wb_sent 201670 # cumulative count of insts sent to commit
< system.cpu1.iew.wb_count 201375 # cumulative count of insts written-back
< system.cpu1.iew.wb_producers 112178 # num instructions producing a value
< system.cpu1.iew.wb_consumers 118722 # num instructions consuming a value
---
> system.cpu1.iew.exec_nop 36391 # number of nop insts executed
> system.cpu1.iew.exec_refs 108940 # number of memory reference insts executed
> system.cpu1.iew.exec_branches 45914 # Number of branches executed
> system.cpu1.iew.exec_stores 34905 # Number of stores executed
> system.cpu1.iew.exec_rate 1.380418 # Inst execution rate
> system.cpu1.iew.wb_sent 223649 # cumulative count of insts sent to commit
> system.cpu1.iew.wb_count 223369 # cumulative count of insts written-back
> system.cpu1.iew.wb_producers 126652 # num instructions producing a value
> system.cpu1.iew.wb_consumers 133295 # num instructions consuming a value
1021,1022c1021,1022
< system.cpu1.iew.wb_rate 1.252839 # insts written-back per cycle
< system.cpu1.iew.wb_fanout 0.944880 # average fanout of values written-back
---
> system.cpu1.iew.wb_rate 1.376849 # insts written-back per cycle
> system.cpu1.iew.wb_fanout 0.950163 # average fanout of values written-back
1024,1029c1024,1029
< system.cpu1.commit.commitSquashedInsts 14315 # The number of squashed insts skipped by commit
< system.cpu1.commit.commitNonSpecStalls 7250 # The number of times commit has been forced to stall to communicate backwards
< system.cpu1.commit.branchMispredicts 1266 # The number of times a branch was mispredicted
< system.cpu1.commit.committed_per_cycle::samples 156398 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::mean 1.449251 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::stdev 1.979774 # Number of insts commited each cycle
---
> system.cpu1.commit.commitSquashedInsts 14380 # The number of squashed insts skipped by commit
> system.cpu1.commit.commitNonSpecStalls 5466 # The number of times commit has been forced to stall to communicate backwards
> system.cpu1.commit.branchMispredicts 1341 # The number of times a branch was mispredicted
> system.cpu1.commit.committed_per_cycle::samples 153714 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::mean 1.636819 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::stdev 2.057713 # Number of insts commited each cycle
1031,1039c1031,1039
< system.cpu1.commit.committed_per_cycle::0 74586 47.69% 47.69% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::1 38945 24.90% 72.59% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::2 5214 3.33% 75.92% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::3 8053 5.15% 81.07% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::4 1537 0.98% 82.06% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::5 24957 15.96% 98.01% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::6 851 0.54% 98.56% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::7 951 0.61% 99.17% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::8 1304 0.83% 100.00% # Number of insts commited each cycle
---
> system.cpu1.commit.committed_per_cycle::0 64759 42.13% 42.13% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::1 42554 27.68% 69.81% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::2 5173 3.37% 73.18% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::3 6281 4.09% 77.26% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::4 1529 0.99% 78.26% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::5 30355 19.75% 98.01% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::6 785 0.51% 98.52% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::7 966 0.63% 99.15% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::8 1312 0.85% 100.00% # Number of insts commited each cycle
1043,1045c1043,1045
< system.cpu1.commit.committed_per_cycle::total 156398 # Number of insts commited each cycle
< system.cpu1.commit.committedInsts 226660 # Number of instructions committed
< system.cpu1.commit.committedOps 226660 # Number of ops (including micro ops) committed
---
> system.cpu1.commit.committed_per_cycle::total 153714 # Number of insts commited each cycle
> system.cpu1.commit.committedInsts 251602 # Number of instructions committed
> system.cpu1.commit.committedOps 251602 # Number of ops (including micro ops) committed
1047,1050c1047,1050
< system.cpu1.commit.refs 92171 # Number of memory references committed
< system.cpu1.commit.loads 63450 # Number of loads committed
< system.cpu1.commit.membars 6533 # Number of memory barriers committed
< system.cpu1.commit.branches 41215 # Number of branches committed
---
> system.cpu1.commit.refs 106422 # Number of memory references committed
> system.cpu1.commit.loads 72360 # Number of loads committed
> system.cpu1.commit.membars 4751 # Number of memory barriers committed
> system.cpu1.commit.branches 44778 # Number of branches committed
1052c1052
< system.cpu1.commit.int_insts 155506 # Number of committed integer instructions.
---
> system.cpu1.commit.int_insts 173320 # Number of committed integer instructions.
1054,1085c1054,1085
< system.cpu1.commit.op_class_0::No_OpClass 32002 14.12% 14.12% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntAlu 95954 42.33% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntMult 0 0.00% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntDiv 0 0.00% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatMult 0 0.00% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMult 0 0.00% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdShift 0 0.00% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.45% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemRead 69983 30.88% 87.33% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemWrite 28721 12.67% 100.00% # Class of committed instruction
---
> system.cpu1.commit.op_class_0::No_OpClass 35567 14.14% 14.14% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntAlu 104862 41.68% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemRead 77111 30.65% 86.46% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemWrite 34062 13.54% 100.00% # Class of committed instruction
1088,1089c1088,1089
< system.cpu1.commit.op_class_0::total 226660 # Class of committed instruction
< system.cpu1.commit.bw_lim_events 1304 # number cycles where commit BW limit reached
---
> system.cpu1.commit.op_class_0::total 251602 # Class of committed instruction
> system.cpu1.commit.bw_lim_events 1312 # number cycles where commit BW limit reached
1091,1103c1091,1103
< system.cpu1.rob.rob_reads 395483 # The number of ROB reads
< system.cpu1.rob.rob_writes 484550 # The number of ROB writes
< system.cpu1.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu1.idleCycles 1735 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu1.quiesceCycles 43282 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu1.committedInsts 188125 # Number of Instructions Simulated
< system.cpu1.committedOps 188125 # Number of Ops (including micro ops) Simulated
< system.cpu1.cpi 0.854405 # CPI: Cycles Per Instruction
< system.cpu1.cpi_total 0.854405 # CPI: Total CPI of All Threads
< system.cpu1.ipc 1.170405 # IPC: Instructions Per Cycle
< system.cpu1.ipc_total 1.170405 # IPC: Total IPC of All Threads
< system.cpu1.int_regfile_reads 343348 # number of integer regfile reads
< system.cpu1.int_regfile_writes 161358 # number of integer regfile writes
---
> system.cpu1.rob.rob_reads 417798 # The number of ROB reads
> system.cpu1.rob.rob_writes 534614 # The number of ROB writes
> system.cpu1.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu1.idleCycles 5868 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu1.quiesceCycles 46290 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu1.committedInsts 211284 # Number of Instructions Simulated
> system.cpu1.committedOps 211284 # Number of Ops (including micro ops) Simulated
> system.cpu1.cpi 0.767839 # CPI: Cycles Per Instruction
> system.cpu1.cpi_total 0.767839 # CPI: Total CPI of All Threads
> system.cpu1.ipc 1.302357 # IPC: Instructions Per Cycle
> system.cpu1.ipc_total 1.302357 # IPC: Total IPC of All Threads
> system.cpu1.int_regfile_reads 386957 # number of integer regfile reads
> system.cpu1.int_regfile_writes 181537 # number of integer regfile writes
1105c1105
< system.cpu1.misc_regfile_reads 96189 # number of misc regfile reads
---
> system.cpu1.misc_regfile_reads 110600 # number of misc regfile reads
1108,1109c1108,1109
< system.cpu1.dcache.tags.tagsinuse 23.332143 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 34754 # Total number of references to valid blocks.
---
> system.cpu1.dcache.tags.tagsinuse 25.579817 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 40184 # Total number of references to valid blocks.
1111c1111
< system.cpu1.dcache.tags.avg_refs 1241.214286 # Average number of references to valid blocks.
---
> system.cpu1.dcache.tags.avg_refs 1435.142857 # Average number of references to valid blocks.
1113,1115c1113,1115
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.332143 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.045571 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.045571 # Average percentage of cache occupancy
---
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.579817 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.049961 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.049961 # Average percentage of cache occupancy
1119,1134c1119,1134
< system.cpu1.dcache.tags.tag_accesses 275515 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 275515 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 39673 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 39673 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 28513 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 28513 # number of WriteReq hits
< system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits
< system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 68186 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 68186 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 68186 # number of overall hits
< system.cpu1.dcache.overall_hits::total 68186 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 422 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 422 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 137 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 137 # number of WriteReq misses
---
> system.cpu1.dcache.tags.tag_accesses 311400 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 311400 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 43257 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 43257 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 33840 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 33840 # number of WriteReq hits
> system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits
> system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 77097 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 77097 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 77097 # number of overall hits
> system.cpu1.dcache.overall_hits::total 77097 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 466 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 466 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 153 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 153 # number of WriteReq misses
1137,1180c1137,1180
< system.cpu1.dcache.demand_misses::cpu1.data 559 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 559 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 559 # number of overall misses
< system.cpu1.dcache.overall_misses::total 559 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5603617 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 5603617 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2812761 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 2812761 # number of WriteReq miss cycles
< system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 492507 # number of SwapReq miss cycles
< system.cpu1.dcache.SwapReq_miss_latency::total 492507 # number of SwapReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 8416378 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 8416378 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 8416378 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 8416378 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 40095 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 40095 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 28650 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 28650 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses)
< system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 68745 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 68745 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 68745 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 68745 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010525 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.010525 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004782 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.004782 # miss rate for WriteReq accesses
< system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses
< system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.008132 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.008132 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.008132 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.008132 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13278.713270 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 13278.713270 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20531.102190 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 20531.102190 # average WriteReq miss latency
< system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 8640.473684 # average SwapReq miss latency
< system.cpu1.dcache.SwapReq_avg_miss_latency::total 8640.473684 # average SwapReq miss latency
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15056.132379 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 15056.132379 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15056.132379 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 15056.132379 # average overall miss latency
---
> system.cpu1.dcache.demand_misses::cpu1.data 619 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 619 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 619 # number of overall misses
> system.cpu1.dcache.overall_misses::total 619 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9865731 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 9865731 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3999011 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 3999011 # number of WriteReq miss cycles
> system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 673507 # number of SwapReq miss cycles
> system.cpu1.dcache.SwapReq_miss_latency::total 673507 # number of SwapReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 13864742 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 13864742 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 13864742 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 13864742 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 43723 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 43723 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 33993 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 33993 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses)
> system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 77716 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 77716 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 77716 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 77716 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010658 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.010658 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004501 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.004501 # miss rate for WriteReq accesses
> system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.826087 # miss rate for SwapReq accesses
> system.cpu1.dcache.SwapReq_miss_rate::total 0.826087 # miss rate for SwapReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007965 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.007965 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007965 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.007965 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 21171.096567 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 21171.096567 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26137.326797 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 26137.326797 # average WriteReq miss latency
> system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 11815.912281 # average SwapReq miss latency
> system.cpu1.dcache.SwapReq_avg_miss_latency::total 11815.912281 # average SwapReq miss latency
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22398.613893 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 22398.613893 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 22398.613893 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 22398.613893 # average overall miss latency
1189,1200c1189,1200
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 262 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 262 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 296 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 296 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 296 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 296 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 160 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses
---
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 299 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 45 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 344 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 344 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 344 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 344 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 167 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 167 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses
1203,1236c1203,1236
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1125015 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1125015 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1272489 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1272489 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 378493 # number of SwapReq MSHR miss cycles
< system.cpu1.dcache.SwapReq_mshr_miss_latency::total 378493 # number of SwapReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2397504 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 2397504 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2397504 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 2397504 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003991 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003991 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003595 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003595 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.802817 # mshr miss rate for SwapReq accesses
< system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003826 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.003826 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003826 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.003826 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 7031.343750 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 7031.343750 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12354.262136 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12354.262136 # average WriteReq mshr miss latency
< system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 6640.228070 # average SwapReq mshr miss latency
< system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 6640.228070 # average SwapReq mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9115.984791 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9115.984791 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9115.984791 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9115.984791 # average overall mshr miss latency
---
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 275 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 275 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 275 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1943270 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1943270 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1707489 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1707489 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 587993 # number of SwapReq MSHR miss cycles
> system.cpu1.dcache.SwapReq_mshr_miss_latency::total 587993 # number of SwapReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3650759 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 3650759 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3650759 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 3650759 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003820 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003820 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003177 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003177 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.826087 # mshr miss rate for SwapReq accesses
> system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.826087 # mshr miss rate for SwapReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003539 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.003539 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003539 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.003539 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11636.347305 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11636.347305 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15810.083333 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15810.083333 # average WriteReq mshr miss latency
> system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10315.666667 # average SwapReq mshr miss latency
> system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10315.666667 # average SwapReq mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13275.487273 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13275.487273 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13275.487273 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13275.487273 # average overall mshr miss latency
1238,1242c1238,1242
< system.cpu1.icache.tags.replacements 388 # number of replacements
< system.cpu1.icache.tags.tagsinuse 76.215682 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 24292 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 498 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 48.779116 # Average number of references to valid blocks.
---
> system.cpu1.icache.tags.replacements 385 # number of replacements
> system.cpu1.icache.tags.tagsinuse 83.683741 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 21045 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 497 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 42.344064 # Average number of references to valid blocks.
1244,1247c1244,1247
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.215682 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.148859 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.148859 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id
---
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 83.683741 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.163445 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.163445 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_task_id_blocks::1024 112 # Occupied blocks per task id
1249,1289c1249,1289
< system.cpu1.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id
< system.cpu1.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id
< system.cpu1.icache.tags.tag_accesses 25352 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 25352 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 24292 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 24292 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 24292 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 24292 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 24292 # number of overall hits
< system.cpu1.icache.overall_hits::total 24292 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 562 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 562 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 562 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 562 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 562 # number of overall misses
< system.cpu1.icache.overall_misses::total 562 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7960746 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 7960746 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 7960746 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 7960746 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 7960746 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 7960746 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 24854 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 24854 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 24854 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 24854 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 24854 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 24854 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022612 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.022612 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022612 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.022612 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022612 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.022612 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14165.028470 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 14165.028470 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14165.028470 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 14165.028470 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14165.028470 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 14165.028470 # average overall miss latency
< system.cpu1.icache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked
---
> system.cpu1.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id
> system.cpu1.icache.tags.occ_task_id_percent::1024 0.218750 # Percentage of cache occupancy per task id
> system.cpu1.icache.tags.tag_accesses 22120 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 22120 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 21045 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 21045 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 21045 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 21045 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 21045 # number of overall hits
> system.cpu1.icache.overall_hits::total 21045 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 578 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 578 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 578 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 578 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 578 # number of overall misses
> system.cpu1.icache.overall_misses::total 578 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14251747 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 14251747 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 14251747 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 14251747 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 14251747 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 14251747 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 21623 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 21623 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 21623 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 21623 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 21623 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 21623 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.026731 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.026731 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.026731 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.026731 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.026731 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.026731 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24657.001730 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 24657.001730 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24657.001730 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 24657.001730 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24657.001730 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 24657.001730 # average overall miss latency
> system.cpu1.icache.blocked_cycles::no_mshrs 114 # number of cycles access was blocked
1291c1291
< system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked
---
> system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked
1293c1293
< system.cpu1.icache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked
---
> system.cpu1.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked
1297,1326c1297,1326
< system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 64 # number of ReadReq MSHR hits
< system.cpu1.icache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits
< system.cpu1.icache.demand_mshr_hits::cpu1.inst 64 # number of demand (read+write) MSHR hits
< system.cpu1.icache.demand_mshr_hits::total 64 # number of demand (read+write) MSHR hits
< system.cpu1.icache.overall_mshr_hits::cpu1.inst 64 # number of overall MSHR hits
< system.cpu1.icache.overall_mshr_hits::total 64 # number of overall MSHR hits
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 498 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 498 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 498 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 498 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6368004 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 6368004 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6368004 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 6368004 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6368004 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 6368004 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.020037 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.020037 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.020037 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.020037 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.020037 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.020037 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12787.156627 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12787.156627 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12787.156627 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 12787.156627 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12787.156627 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 12787.156627 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 81 # number of ReadReq MSHR hits
> system.cpu1.icache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits
> system.cpu1.icache.demand_mshr_hits::cpu1.inst 81 # number of demand (read+write) MSHR hits
> system.cpu1.icache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits
> system.cpu1.icache.overall_mshr_hits::cpu1.inst 81 # number of overall MSHR hits
> system.cpu1.icache.overall_mshr_hits::total 81 # number of overall MSHR hits
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 497 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 497 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 497 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 497 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 497 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 497 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11245503 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 11245503 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11245503 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 11245503 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11245503 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 11245503 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022985 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022985 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022985 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.022985 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022985 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.022985 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22626.766600 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22626.766600 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22626.766600 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 22626.766600 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22626.766600 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 22626.766600 # average overall mshr miss latency
1328,1332c1328,1332
< system.cpu2.branchPred.lookups 55295 # Number of BP lookups
< system.cpu2.branchPred.condPredicted 51520 # Number of conditional branches predicted
< system.cpu2.branchPred.condIncorrect 1304 # Number of conditional branches incorrect
< system.cpu2.branchPred.BTBLookups 47890 # Number of BTB lookups
< system.cpu2.branchPred.BTBHits 46487 # Number of BTB hits
---
> system.cpu2.branchPred.lookups 51309 # Number of BP lookups
> system.cpu2.branchPred.condPredicted 47950 # Number of conditional branches predicted
> system.cpu2.branchPred.condIncorrect 1280 # Number of conditional branches incorrect
> system.cpu2.branchPred.BTBLookups 43975 # Number of BTB lookups
> system.cpu2.branchPred.BTBHits 43053 # Number of BTB hits
1334,1335c1334,1335
< system.cpu2.branchPred.BTBHitPct 97.070370 # BTB Hit Percentage
< system.cpu2.branchPred.usedRAS 899 # Number of times the RAS was used to get a target.
---
> system.cpu2.branchPred.BTBHitPct 97.903354 # BTB Hit Percentage
> system.cpu2.branchPred.usedRAS 886 # Number of times the RAS was used to get a target.
1337c1337
< system.cpu2.numCycles 160375 # number of cpu cycles simulated
---
> system.cpu2.numCycles 161860 # number of cpu cycles simulated
1340,1346c1340,1346
< system.cpu2.fetch.icacheStallCycles 28879 # Number of cycles fetch is stalled on an Icache miss
< system.cpu2.fetch.Insts 309014 # Number of instructions fetch has processed
< system.cpu2.fetch.Branches 55295 # Number of branches that fetch encountered
< system.cpu2.fetch.predictedBranches 47386 # Number of branches that fetch has predicted taken
< system.cpu2.fetch.Cycles 123906 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu2.fetch.SquashCycles 2765 # Number of cycles fetch has spent squashing
< system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
---
> system.cpu2.fetch.icacheStallCycles 31583 # Number of cycles fetch is stalled on an Icache miss
> system.cpu2.fetch.Insts 282068 # Number of instructions fetch has processed
> system.cpu2.fetch.Branches 51309 # Number of branches that fetch encountered
> system.cpu2.fetch.predictedBranches 43939 # Number of branches that fetch has predicted taken
> system.cpu2.fetch.Cycles 125716 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu2.fetch.SquashCycles 2717 # Number of cycles fetch has spent squashing
> system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1348,1354c1348,1353
< system.cpu2.fetch.PendingTrapStallCycles 1110 # Number of stall cycles due to pending traps
< system.cpu2.fetch.IcacheWaitRetryStallCycles 3 # Number of stall cycles due to full MSHR
< system.cpu2.fetch.CacheLines 19451 # Number of cache lines fetched
< system.cpu2.fetch.IcacheSquashes 461 # Number of outstanding Icache misses that were squashed
< system.cpu2.fetch.rateDist::samples 155294 # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::mean 1.989864 # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::stdev 2.243889 # Number of instructions fetched each cycle (Total)
---
> system.cpu2.fetch.PendingTrapStallCycles 1207 # Number of stall cycles due to pending traps
> system.cpu2.fetch.CacheLines 22884 # Number of cache lines fetched
> system.cpu2.fetch.IcacheSquashes 412 # Number of outstanding Icache misses that were squashed
> system.cpu2.fetch.rateDist::samples 159877 # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::mean 1.764281 # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::stdev 2.167875 # Number of instructions fetched each cycle (Total)
1356,1364c1355,1363
< system.cpu2.fetch.rateDist::0 49501 31.88% 31.88% # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::1 52893 34.06% 65.94% # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::2 5338 3.44% 69.37% # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::3 3457 2.23% 71.60% # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::4 949 0.61% 72.21% # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::5 36899 23.76% 95.97% # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::6 1216 0.78% 96.75% # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::7 841 0.54% 97.30% # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::8 4200 2.70% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu2.fetch.rateDist::0 59518 37.23% 37.23% # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::1 51095 31.96% 69.19% # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::2 7306 4.57% 73.76% # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::3 3438 2.15% 75.91% # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::4 997 0.62% 76.53% # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::5 31616 19.78% 96.31% # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::6 1254 0.78% 97.09% # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::7 769 0.48% 97.57% # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::8 3884 2.43% 100.00% # Number of instructions fetched each cycle (Total)
1368,1408c1367,1407
< system.cpu2.fetch.rateDist::total 155294 # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.branchRate 0.344786 # Number of branch fetches per cycle
< system.cpu2.fetch.rate 1.926822 # Number of inst fetches per cycle
< system.cpu2.decode.IdleCycles 17746 # Number of cycles decode is idle
< system.cpu2.decode.BlockedCycles 46456 # Number of cycles decode is blocked
< system.cpu2.decode.RunCycles 86830 # Number of cycles decode is running
< system.cpu2.decode.UnblockCycles 2870 # Number of cycles decode is unblocking
< system.cpu2.decode.SquashCycles 1382 # Number of cycles decode is squashing
< system.cpu2.decode.DecodedInsts 293603 # Number of instructions handled by decode
< system.cpu2.rename.SquashCycles 1382 # Number of cycles rename is squashing
< system.cpu2.rename.IdleCycles 18442 # Number of cycles rename is idle
< system.cpu2.rename.BlockCycles 20397 # Number of cycles rename is blocking
< system.cpu2.rename.serializeStallCycles 12871 # count of cycles rename stalled for serializing inst
< system.cpu2.rename.RunCycles 87967 # Number of cycles rename is running
< system.cpu2.rename.UnblockCycles 14225 # Number of cycles rename is unblocking
< system.cpu2.rename.RenamedInsts 290431 # Number of instructions processed by rename
< system.cpu2.rename.IQFullEvents 12472 # Number of times rename has blocked due to IQ full
< system.cpu2.rename.LQFullEvents 29 # Number of times rename has blocked due to LQ full
< system.cpu2.rename.FullRegisterEvents 6 # Number of times there has been no free registers
< system.cpu2.rename.RenamedOperands 205748 # Number of destination operands rename has renamed
< system.cpu2.rename.RenameLookups 562377 # Number of register rename lookups that rename has made
< system.cpu2.rename.int_rename_lookups 437048 # Number of integer rename lookups
< system.cpu2.rename.CommittedMaps 190737 # Number of HB maps that are committed
< system.cpu2.rename.UndoneMaps 15011 # Number of HB maps that are undone due to squashing
< system.cpu2.rename.serializingInsts 1169 # count of serializing insts renamed
< system.cpu2.rename.tempSerializingInsts 1232 # count of temporary serializing insts renamed
< system.cpu2.rename.skidInsts 18731 # count of insts added to the skid buffer
< system.cpu2.memDep0.insertedLoads 82610 # Number of loads inserted to the mem dependence unit.
< system.cpu2.memDep0.insertedStores 39860 # Number of stores inserted to the mem dependence unit.
< system.cpu2.memDep0.conflictingLoads 38981 # Number of conflicting loads.
< system.cpu2.memDep0.conflictingStores 34721 # Number of conflicting stores.
< system.cpu2.iq.iqInstsAdded 242796 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu2.iq.iqNonSpecInstsAdded 5190 # Number of non-speculative instructions added to the IQ
< system.cpu2.iq.iqInstsIssued 242904 # Number of instructions issued
< system.cpu2.iq.iqSquashedInstsIssued 29 # Number of squashed instructions issued
< system.cpu2.iq.iqSquashedInstsExamined 13134 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu2.iq.iqSquashedOperandsExamined 12157 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu2.iq.iqSquashedNonSpecRemoved 612 # Number of squashed non-spec instructions that were removed
< system.cpu2.iq.issued_per_cycle::samples 155294 # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::mean 1.564156 # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::stdev 1.378675 # Number of insts issued each cycle
---
> system.cpu2.fetch.rateDist::total 159877 # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.branchRate 0.316996 # Number of branch fetches per cycle
> system.cpu2.fetch.rate 1.742667 # Number of inst fetches per cycle
> system.cpu2.decode.IdleCycles 17468 # Number of cycles decode is idle
> system.cpu2.decode.BlockedCycles 61085 # Number of cycles decode is blocked
> system.cpu2.decode.RunCycles 76240 # Number of cycles decode is running
> system.cpu2.decode.UnblockCycles 3716 # Number of cycles decode is unblocking
> system.cpu2.decode.SquashCycles 1358 # Number of cycles decode is squashing
> system.cpu2.decode.DecodedInsts 267722 # Number of instructions handled by decode
> system.cpu2.rename.SquashCycles 1358 # Number of cycles rename is squashing
> system.cpu2.rename.IdleCycles 18170 # Number of cycles rename is idle
> system.cpu2.rename.BlockCycles 29188 # Number of cycles rename is blocking
> system.cpu2.rename.serializeStallCycles 12834 # count of cycles rename stalled for serializing inst
> system.cpu2.rename.RunCycles 77782 # Number of cycles rename is running
> system.cpu2.rename.UnblockCycles 20535 # Number of cycles rename is unblocking
> system.cpu2.rename.RenamedInsts 264399 # Number of instructions processed by rename
> system.cpu2.rename.IQFullEvents 18336 # Number of times rename has blocked due to IQ full
> system.cpu2.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full
> system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers
> system.cpu2.rename.RenamedOperands 185298 # Number of destination operands rename has renamed
> system.cpu2.rename.RenameLookups 503121 # Number of register rename lookups that rename has made
> system.cpu2.rename.int_rename_lookups 392507 # Number of integer rename lookups
> system.cpu2.rename.CommittedMaps 170476 # Number of HB maps that are committed
> system.cpu2.rename.UndoneMaps 14822 # Number of HB maps that are undone due to squashing
> system.cpu2.rename.serializingInsts 1180 # count of serializing insts renamed
> system.cpu2.rename.tempSerializingInsts 1243 # count of temporary serializing insts renamed
> system.cpu2.rename.skidInsts 25168 # count of insts added to the skid buffer
> system.cpu2.memDep0.insertedLoads 73362 # Number of loads inserted to the mem dependence unit.
> system.cpu2.memDep0.insertedStores 34382 # Number of stores inserted to the mem dependence unit.
> system.cpu2.memDep0.conflictingLoads 35300 # Number of conflicting loads.
> system.cpu2.memDep0.conflictingStores 29228 # Number of conflicting stores.
> system.cpu2.iq.iqInstsAdded 218628 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu2.iq.iqNonSpecInstsAdded 6983 # Number of non-speculative instructions added to the IQ
> system.cpu2.iq.iqInstsIssued 220497 # Number of instructions issued
> system.cpu2.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued
> system.cpu2.iq.iqSquashedInstsExamined 13020 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu2.iq.iqSquashedOperandsExamined 12313 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu2.iq.iqSquashedNonSpecRemoved 622 # Number of squashed non-spec instructions that were removed
> system.cpu2.iq.issued_per_cycle::samples 159877 # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::mean 1.379166 # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::stdev 1.379581 # Number of insts issued each cycle
1410,1418c1409,1417
< system.cpu2.iq.issued_per_cycle::0 52943 34.09% 34.09% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::1 18212 11.73% 45.82% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::2 39071 25.16% 70.98% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::3 38654 24.89% 95.87% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::4 3479 2.24% 98.11% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::5 1594 1.03% 99.14% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::6 891 0.57% 99.71% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::7 244 0.16% 99.87% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::8 206 0.13% 100.00% # Number of insts issued each cycle
---
> system.cpu2.iq.issued_per_cycle::0 63376 39.64% 39.64% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::1 23374 14.62% 54.26% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::2 33553 20.99% 75.25% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::3 33206 20.77% 96.02% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::4 3423 2.14% 98.16% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::5 1623 1.02% 99.17% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::6 877 0.55% 99.72% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::7 230 0.14% 99.87% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::8 215 0.13% 100.00% # Number of insts issued each cycle
1422c1421
< system.cpu2.iq.issued_per_cycle::total 155294 # Number of insts issued each cycle
---
> system.cpu2.iq.issued_per_cycle::total 159877 # Number of insts issued each cycle
1424,1454c1423,1453
< system.cpu2.iq.fu_full::IntAlu 90 25.64% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::IntMult 0 0.00% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::IntDiv 0 0.00% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::FloatAdd 0 0.00% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::FloatCmp 0 0.00% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::FloatCvt 0 0.00% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::FloatMult 0 0.00% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::FloatDiv 0 0.00% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdAdd 0 0.00% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdAlu 0 0.00% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdCmp 0 0.00% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdCvt 0 0.00% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdMisc 0 0.00% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdMult 0 0.00% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdShift 0 0.00% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 25.64% # attempts to use FU when none available
< system.cpu2.iq.fu_full::MemRead 52 14.81% 40.46% # attempts to use FU when none available
< system.cpu2.iq.fu_full::MemWrite 209 59.54% 100.00% # attempts to use FU when none available
---
> system.cpu2.iq.fu_full::IntAlu 86 23.69% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::IntMult 0 0.00% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.69% # attempts to use FU when none available
> system.cpu2.iq.fu_full::MemRead 68 18.73% 42.42% # attempts to use FU when none available
> system.cpu2.iq.fu_full::MemWrite 209 57.58% 100.00% # attempts to use FU when none available
1458,1488c1457,1487
< system.cpu2.iq.FU_type_0::IntAlu 118122 48.63% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.63% # Type of FU issued
< system.cpu2.iq.FU_type_0::MemRead 85639 35.26% 83.89% # Type of FU issued
< system.cpu2.iq.FU_type_0::MemWrite 39143 16.11% 100.00% # Type of FU issued
---
> system.cpu2.iq.FU_type_0::IntAlu 108751 49.32% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.32% # Type of FU issued
> system.cpu2.iq.FU_type_0::MemRead 78120 35.43% 84.75% # Type of FU issued
> system.cpu2.iq.FU_type_0::MemWrite 33626 15.25% 100.00% # Type of FU issued
1491,1497c1490,1496
< system.cpu2.iq.FU_type_0::total 242904 # Type of FU issued
< system.cpu2.iq.rate 1.514600 # Inst issue rate
< system.cpu2.iq.fu_busy_cnt 351 # FU busy when requested
< system.cpu2.iq.fu_busy_rate 0.001445 # FU busy rate (busy events/executed inst)
< system.cpu2.iq.int_inst_queue_reads 641482 # Number of integer instruction queue reads
< system.cpu2.iq.int_inst_queue_writes 261162 # Number of integer instruction queue writes
< system.cpu2.iq.int_inst_queue_wakeup_accesses 241189 # Number of integer instruction queue wakeup accesses
---
> system.cpu2.iq.FU_type_0::total 220497 # Type of FU issued
> system.cpu2.iq.rate 1.362270 # Inst issue rate
> system.cpu2.iq.fu_busy_cnt 363 # FU busy when requested
> system.cpu2.iq.fu_busy_rate 0.001646 # FU busy rate (busy events/executed inst)
> system.cpu2.iq.int_inst_queue_reads 601287 # Number of integer instruction queue reads
> system.cpu2.iq.int_inst_queue_writes 238674 # Number of integer instruction queue writes
> system.cpu2.iq.int_inst_queue_wakeup_accesses 218768 # Number of integer instruction queue wakeup accesses
1501c1500
< system.cpu2.iq.int_alu_accesses 243255 # Number of integer alu accesses
---
> system.cpu2.iq.int_alu_accesses 220860 # Number of integer alu accesses
1503c1502
< system.cpu2.iew.lsq.thread0.forwLoads 34438 # Number of loads that had data forwarded from stores
---
> system.cpu2.iew.lsq.thread0.forwLoads 28926 # Number of loads that had data forwarded from stores
1505c1504
< system.cpu2.iew.lsq.thread0.squashedLoads 2866 # Number of loads squashed
---
> system.cpu2.iew.lsq.thread0.squashedLoads 2863 # Number of loads squashed
1507,1508c1506,1507
< system.cpu2.iew.lsq.thread0.memOrderViolation 42 # Number of memory ordering violations
< system.cpu2.iew.lsq.thread0.squashedStores 1666 # Number of stores squashed
---
> system.cpu2.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations
> system.cpu2.iew.lsq.thread0.squashedStores 1691 # Number of stores squashed
1514,1522c1513,1521
< system.cpu2.iew.iewSquashCycles 1382 # Number of cycles IEW is squashing
< system.cpu2.iew.iewBlockCycles 6074 # Number of cycles IEW is blocking
< system.cpu2.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking
< system.cpu2.iew.iewDispatchedInsts 287692 # Number of instructions dispatched to IQ
< system.cpu2.iew.iewDispSquashedInsts 198 # Number of squashed instructions skipped by dispatch
< system.cpu2.iew.iewDispLoadInsts 82610 # Number of dispatched load instructions
< system.cpu2.iew.iewDispStoreInsts 39860 # Number of dispatched store instructions
< system.cpu2.iew.iewDispNonSpecInsts 1098 # Number of dispatched non-speculative instructions
< system.cpu2.iew.iewIQFullEvents 33 # Number of times the IQ has become full, causing a stall
---
> system.cpu2.iew.iewSquashCycles 1358 # Number of cycles IEW is squashing
> system.cpu2.iew.iewBlockCycles 8128 # Number of cycles IEW is blocking
> system.cpu2.iew.iewUnblockCycles 61 # Number of cycles IEW is unblocking
> system.cpu2.iew.iewDispatchedInsts 261616 # Number of instructions dispatched to IQ
> system.cpu2.iew.iewDispSquashedInsts 204 # Number of squashed instructions skipped by dispatch
> system.cpu2.iew.iewDispLoadInsts 73362 # Number of dispatched load instructions
> system.cpu2.iew.iewDispStoreInsts 34382 # Number of dispatched store instructions
> system.cpu2.iew.iewDispNonSpecInsts 1094 # Number of dispatched non-speculative instructions
> system.cpu2.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall
1524,1530c1523,1529
< system.cpu2.iew.memOrderViolationEvents 42 # Number of memory order violations
< system.cpu2.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly
< system.cpu2.iew.predictedNotTakenIncorrect 1074 # Number of branches that were predicted not taken incorrectly
< system.cpu2.iew.branchMispredicts 1544 # Number of branch mispredicts detected at execute
< system.cpu2.iew.iewExecutedInsts 241779 # Number of executed instructions
< system.cpu2.iew.iewExecLoadInsts 81452 # Number of load instructions executed
< system.cpu2.iew.iewExecSquashedInsts 1125 # Number of squashed instructions skipped in execute
---
> system.cpu2.iew.memOrderViolationEvents 43 # Number of memory order violations
> system.cpu2.iew.predictedTakenIncorrect 455 # Number of branches that were predicted taken incorrectly
> system.cpu2.iew.predictedNotTakenIncorrect 1045 # Number of branches that were predicted not taken incorrectly
> system.cpu2.iew.branchMispredicts 1500 # Number of branch mispredicts detected at execute
> system.cpu2.iew.iewExecutedInsts 219377 # Number of executed instructions
> system.cpu2.iew.iewExecLoadInsts 72164 # Number of load instructions executed
> system.cpu2.iew.iewExecSquashedInsts 1120 # Number of squashed instructions skipped in execute
1532,1540c1531,1539
< system.cpu2.iew.exec_nop 39706 # number of nop insts executed
< system.cpu2.iew.exec_refs 120488 # number of memory reference insts executed
< system.cpu2.iew.exec_branches 49059 # Number of branches executed
< system.cpu2.iew.exec_stores 39036 # Number of stores executed
< system.cpu2.iew.exec_rate 1.507585 # Inst execution rate
< system.cpu2.iew.wb_sent 241491 # cumulative count of insts sent to commit
< system.cpu2.iew.wb_count 241189 # cumulative count of insts written-back
< system.cpu2.iew.wb_producers 138145 # num instructions producing a value
< system.cpu2.iew.wb_consumers 144798 # num instructions consuming a value
---
> system.cpu2.iew.exec_nop 36005 # number of nop insts executed
> system.cpu2.iew.exec_refs 105679 # number of memory reference insts executed
> system.cpu2.iew.exec_branches 45327 # Number of branches executed
> system.cpu2.iew.exec_stores 33515 # Number of stores executed
> system.cpu2.iew.exec_rate 1.355350 # Inst execution rate
> system.cpu2.iew.wb_sent 219089 # cumulative count of insts sent to commit
> system.cpu2.iew.wb_count 218768 # cumulative count of insts written-back
> system.cpu2.iew.wb_producers 123331 # num instructions producing a value
> system.cpu2.iew.wb_consumers 129941 # num instructions consuming a value
1542,1543c1541,1542
< system.cpu2.iew.wb_rate 1.503906 # insts written-back per cycle
< system.cpu2.iew.wb_fanout 0.954053 # average fanout of values written-back
---
> system.cpu2.iew.wb_rate 1.351588 # insts written-back per cycle
> system.cpu2.iew.wb_fanout 0.949131 # average fanout of values written-back
1545,1550c1544,1549
< system.cpu2.commit.commitSquashedInsts 14779 # The number of squashed insts skipped by commit
< system.cpu2.commit.commitNonSpecStalls 4578 # The number of times commit has been forced to stall to communicate backwards
< system.cpu2.commit.branchMispredicts 1304 # The number of times a branch was mispredicted
< system.cpu2.commit.committed_per_cycle::samples 152612 # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::mean 1.787933 # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::stdev 2.101313 # Number of insts commited each cycle
---
> system.cpu2.commit.commitSquashedInsts 14642 # The number of squashed insts skipped by commit
> system.cpu2.commit.commitNonSpecStalls 6361 # The number of times commit has been forced to stall to communicate backwards
> system.cpu2.commit.branchMispredicts 1280 # The number of times a branch was mispredicted
> system.cpu2.commit.committed_per_cycle::samples 157221 # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::mean 1.570534 # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::stdev 2.031430 # Number of insts commited each cycle
1552,1560c1551,1559
< system.cpu2.commit.committed_per_cycle::0 57189 37.47% 37.47% # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::1 45780 30.00% 67.47% # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::2 5178 3.39% 70.86% # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::3 5403 3.54% 74.40% # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::4 1516 0.99% 75.40% # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::5 34396 22.54% 97.94% # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::6 886 0.58% 98.52% # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::7 957 0.63% 99.14% # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::8 1307 0.86% 100.00% # Number of insts commited each cycle
---
> system.cpu2.commit.committed_per_cycle::0 69336 44.10% 44.10% # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::1 41971 26.70% 70.80% # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::2 5151 3.28% 74.07% # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::3 7156 4.55% 78.62% # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::4 1534 0.98% 79.60% # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::5 28975 18.43% 98.03% # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::6 827 0.53% 98.56% # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::7 961 0.61% 99.17% # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::8 1310 0.83% 100.00% # Number of insts commited each cycle
1564,1566c1563,1565
< system.cpu2.commit.committed_per_cycle::total 152612 # Number of insts commited each cycle
< system.cpu2.commit.committedInsts 272860 # Number of instructions committed
< system.cpu2.commit.committedOps 272860 # Number of ops (including micro ops) committed
---
> system.cpu2.commit.committed_per_cycle::total 157221 # Number of insts commited each cycle
> system.cpu2.commit.committedInsts 246921 # Number of instructions committed
> system.cpu2.commit.committedOps 246921 # Number of ops (including micro ops) committed
1568,1571c1567,1570
< system.cpu2.commit.refs 117938 # Number of memory references committed
< system.cpu2.commit.loads 79744 # Number of loads committed
< system.cpu2.commit.membars 3865 # Number of memory barriers committed
< system.cpu2.commit.branches 48024 # Number of branches committed
---
> system.cpu2.commit.refs 103190 # Number of memory references committed
> system.cpu2.commit.loads 70499 # Number of loads committed
> system.cpu2.commit.membars 5644 # Number of memory barriers committed
> system.cpu2.commit.branches 44296 # Number of branches committed
1573c1572
< system.cpu2.commit.int_insts 188084 # Number of committed integer instructions.
---
> system.cpu2.commit.int_insts 169605 # Number of committed integer instructions.
1575,1606c1574,1605
< system.cpu2.commit.op_class_0::No_OpClass 38815 14.23% 14.23% # Class of committed instruction
< system.cpu2.commit.op_class_0::IntAlu 112242 41.14% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.36% # Class of committed instruction
< system.cpu2.commit.op_class_0::MemRead 83609 30.64% 86.00% # Class of committed instruction
< system.cpu2.commit.op_class_0::MemWrite 38194 14.00% 100.00% # Class of committed instruction
---
> system.cpu2.commit.op_class_0::No_OpClass 35083 14.21% 14.21% # Class of committed instruction
> system.cpu2.commit.op_class_0::IntAlu 103004 41.72% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.92% # Class of committed instruction
> system.cpu2.commit.op_class_0::MemRead 76143 30.84% 86.76% # Class of committed instruction
> system.cpu2.commit.op_class_0::MemWrite 32691 13.24% 100.00% # Class of committed instruction
1609,1610c1608,1609
< system.cpu2.commit.op_class_0::total 272860 # Class of committed instruction
< system.cpu2.commit.bw_lim_events 1307 # number cycles where commit BW limit reached
---
> system.cpu2.commit.op_class_0::total 246921 # Class of committed instruction
> system.cpu2.commit.bw_lim_events 1310 # number cycles where commit BW limit reached
1612,1624c1611,1623
< system.cpu2.rob.rob_reads 438358 # The number of ROB reads
< system.cpu2.rob.rob_writes 577962 # The number of ROB writes
< system.cpu2.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu2.idleCycles 5081 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu2.quiesceCycles 43644 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu2.committedInsts 230180 # Number of Instructions Simulated
< system.cpu2.committedOps 230180 # Number of Ops (including micro ops) Simulated
< system.cpu2.cpi 0.696737 # CPI: Cycles Per Instruction
< system.cpu2.cpi_total 0.696737 # CPI: Total CPI of All Threads
< system.cpu2.ipc 1.435261 # IPC: Instructions Per Cycle
< system.cpu2.ipc_total 1.435261 # IPC: Total IPC of All Threads
< system.cpu2.int_regfile_reads 421380 # number of integer regfile reads
< system.cpu2.int_regfile_writes 197053 # number of integer regfile writes
---
> system.cpu2.rob.rob_reads 416888 # The number of ROB reads
> system.cpu2.rob.rob_writes 525783 # The number of ROB writes
> system.cpu2.timesIdled 205 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu2.idleCycles 1983 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu2.quiesceCycles 46662 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu2.committedInsts 206194 # Number of Instructions Simulated
> system.cpu2.committedOps 206194 # Number of Ops (including micro ops) Simulated
> system.cpu2.cpi 0.784989 # CPI: Cycles Per Instruction
> system.cpu2.cpi_total 0.784989 # CPI: Total CPI of All Threads
> system.cpu2.ipc 1.273903 # IPC: Instructions Per Cycle
> system.cpu2.ipc_total 1.273903 # IPC: Total IPC of All Threads
> system.cpu2.int_regfile_reads 376797 # number of integer regfile reads
> system.cpu2.int_regfile_writes 176595 # number of integer regfile writes
1626c1625
< system.cpu2.misc_regfile_reads 122100 # number of misc regfile reads
---
> system.cpu2.misc_regfile_reads 107278 # number of misc regfile reads
1629,1632c1628,1631
< system.cpu2.dcache.tags.tagsinuse 25.900864 # Cycle average of tags in use
< system.cpu2.dcache.tags.total_refs 44302 # Total number of references to valid blocks.
< system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
< system.cpu2.dcache.tags.avg_refs 1582.214286 # Average number of references to valid blocks.
---
> system.cpu2.dcache.tags.tagsinuse 24.051885 # Cycle average of tags in use
> system.cpu2.dcache.tags.total_refs 38880 # Total number of references to valid blocks.
> system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
> system.cpu2.dcache.tags.avg_refs 1340.689655 # Average number of references to valid blocks.
1634,1637c1633,1637
< system.cpu2.dcache.tags.occ_blocks::cpu2.data 25.900864 # Average occupied blocks per requestor
< system.cpu2.dcache.tags.occ_percent::cpu2.data 0.050588 # Average percentage of cache occupancy
< system.cpu2.dcache.tags.occ_percent::total 0.050588 # Average percentage of cache occupancy
< system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id
---
> system.cpu2.dcache.tags.occ_blocks::cpu2.data 24.051885 # Average occupied blocks per requestor
> system.cpu2.dcache.tags.occ_percent::cpu2.data 0.046976 # Average percentage of cache occupancy
> system.cpu2.dcache.tags.occ_percent::total 0.046976 # Average percentage of cache occupancy
> system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
> system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
1639,1701c1639,1701
< system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id
< system.cpu2.dcache.tags.tag_accesses 341013 # Number of tag accesses
< system.cpu2.dcache.tags.data_accesses 341013 # Number of data accesses
< system.cpu2.dcache.ReadReq_hits::cpu2.data 46548 # number of ReadReq hits
< system.cpu2.dcache.ReadReq_hits::total 46548 # number of ReadReq hits
< system.cpu2.dcache.WriteReq_hits::cpu2.data 37978 # number of WriteReq hits
< system.cpu2.dcache.WriteReq_hits::total 37978 # number of WriteReq hits
< system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits
< system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits
< system.cpu2.dcache.demand_hits::cpu2.data 84526 # number of demand (read+write) hits
< system.cpu2.dcache.demand_hits::total 84526 # number of demand (read+write) hits
< system.cpu2.dcache.overall_hits::cpu2.data 84526 # number of overall hits
< system.cpu2.dcache.overall_hits::total 84526 # number of overall hits
< system.cpu2.dcache.ReadReq_misses::cpu2.data 448 # number of ReadReq misses
< system.cpu2.dcache.ReadReq_misses::total 448 # number of ReadReq misses
< system.cpu2.dcache.WriteReq_misses::cpu2.data 149 # number of WriteReq misses
< system.cpu2.dcache.WriteReq_misses::total 149 # number of WriteReq misses
< system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses
< system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses
< system.cpu2.dcache.demand_misses::cpu2.data 597 # number of demand (read+write) misses
< system.cpu2.dcache.demand_misses::total 597 # number of demand (read+write) misses
< system.cpu2.dcache.overall_misses::cpu2.data 597 # number of overall misses
< system.cpu2.dcache.overall_misses::total 597 # number of overall misses
< system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7705986 # number of ReadReq miss cycles
< system.cpu2.dcache.ReadReq_miss_latency::total 7705986 # number of ReadReq miss cycles
< system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3669012 # number of WriteReq miss cycles
< system.cpu2.dcache.WriteReq_miss_latency::total 3669012 # number of WriteReq miss cycles
< system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 505508 # number of SwapReq miss cycles
< system.cpu2.dcache.SwapReq_miss_latency::total 505508 # number of SwapReq miss cycles
< system.cpu2.dcache.demand_miss_latency::cpu2.data 11374998 # number of demand (read+write) miss cycles
< system.cpu2.dcache.demand_miss_latency::total 11374998 # number of demand (read+write) miss cycles
< system.cpu2.dcache.overall_miss_latency::cpu2.data 11374998 # number of overall miss cycles
< system.cpu2.dcache.overall_miss_latency::total 11374998 # number of overall miss cycles
< system.cpu2.dcache.ReadReq_accesses::cpu2.data 46996 # number of ReadReq accesses(hits+misses)
< system.cpu2.dcache.ReadReq_accesses::total 46996 # number of ReadReq accesses(hits+misses)
< system.cpu2.dcache.WriteReq_accesses::cpu2.data 38127 # number of WriteReq accesses(hits+misses)
< system.cpu2.dcache.WriteReq_accesses::total 38127 # number of WriteReq accesses(hits+misses)
< system.cpu2.dcache.SwapReq_accesses::cpu2.data 67 # number of SwapReq accesses(hits+misses)
< system.cpu2.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses)
< system.cpu2.dcache.demand_accesses::cpu2.data 85123 # number of demand (read+write) accesses
< system.cpu2.dcache.demand_accesses::total 85123 # number of demand (read+write) accesses
< system.cpu2.dcache.overall_accesses::cpu2.data 85123 # number of overall (read+write) accesses
< system.cpu2.dcache.overall_accesses::total 85123 # number of overall (read+write) accesses
< system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009533 # miss rate for ReadReq accesses
< system.cpu2.dcache.ReadReq_miss_rate::total 0.009533 # miss rate for ReadReq accesses
< system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003908 # miss rate for WriteReq accesses
< system.cpu2.dcache.WriteReq_miss_rate::total 0.003908 # miss rate for WriteReq accesses
< system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.820896 # miss rate for SwapReq accesses
< system.cpu2.dcache.SwapReq_miss_rate::total 0.820896 # miss rate for SwapReq accesses
< system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007013 # miss rate for demand accesses
< system.cpu2.dcache.demand_miss_rate::total 0.007013 # miss rate for demand accesses
< system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007013 # miss rate for overall accesses
< system.cpu2.dcache.overall_miss_rate::total 0.007013 # miss rate for overall accesses
< system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17200.861607 # average ReadReq miss latency
< system.cpu2.dcache.ReadReq_avg_miss_latency::total 17200.861607 # average ReadReq miss latency
< system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24624.241611 # average WriteReq miss latency
< system.cpu2.dcache.WriteReq_avg_miss_latency::total 24624.241611 # average WriteReq miss latency
< system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9191.054545 # average SwapReq miss latency
< system.cpu2.dcache.SwapReq_avg_miss_latency::total 9191.054545 # average SwapReq miss latency
< system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 19053.597990 # average overall miss latency
< system.cpu2.dcache.demand_avg_miss_latency::total 19053.597990 # average overall miss latency
< system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 19053.597990 # average overall miss latency
< system.cpu2.dcache.overall_avg_miss_latency::total 19053.597990 # average overall miss latency
---
> system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
> system.cpu2.dcache.tags.tag_accesses 303893 # Number of tag accesses
> system.cpu2.dcache.tags.data_accesses 303893 # Number of data accesses
> system.cpu2.dcache.ReadReq_hits::cpu2.data 42781 # number of ReadReq hits
> system.cpu2.dcache.ReadReq_hits::total 42781 # number of ReadReq hits
> system.cpu2.dcache.WriteReq_hits::cpu2.data 32487 # number of WriteReq hits
> system.cpu2.dcache.WriteReq_hits::total 32487 # number of WriteReq hits
> system.cpu2.dcache.SwapReq_hits::cpu2.data 14 # number of SwapReq hits
> system.cpu2.dcache.SwapReq_hits::total 14 # number of SwapReq hits
> system.cpu2.dcache.demand_hits::cpu2.data 75268 # number of demand (read+write) hits
> system.cpu2.dcache.demand_hits::total 75268 # number of demand (read+write) hits
> system.cpu2.dcache.overall_hits::cpu2.data 75268 # number of overall hits
> system.cpu2.dcache.overall_hits::total 75268 # number of overall hits
> system.cpu2.dcache.ReadReq_misses::cpu2.data 440 # number of ReadReq misses
> system.cpu2.dcache.ReadReq_misses::total 440 # number of ReadReq misses
> system.cpu2.dcache.WriteReq_misses::cpu2.data 133 # number of WriteReq misses
> system.cpu2.dcache.WriteReq_misses::total 133 # number of WriteReq misses
> system.cpu2.dcache.SwapReq_misses::cpu2.data 57 # number of SwapReq misses
> system.cpu2.dcache.SwapReq_misses::total 57 # number of SwapReq misses
> system.cpu2.dcache.demand_misses::cpu2.data 573 # number of demand (read+write) misses
> system.cpu2.dcache.demand_misses::total 573 # number of demand (read+write) misses
> system.cpu2.dcache.overall_misses::cpu2.data 573 # number of overall misses
> system.cpu2.dcache.overall_misses::total 573 # number of overall misses
> system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7341783 # number of ReadReq miss cycles
> system.cpu2.dcache.ReadReq_miss_latency::total 7341783 # number of ReadReq miss cycles
> system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2962762 # number of WriteReq miss cycles
> system.cpu2.dcache.WriteReq_miss_latency::total 2962762 # number of WriteReq miss cycles
> system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 594005 # number of SwapReq miss cycles
> system.cpu2.dcache.SwapReq_miss_latency::total 594005 # number of SwapReq miss cycles
> system.cpu2.dcache.demand_miss_latency::cpu2.data 10304545 # number of demand (read+write) miss cycles
> system.cpu2.dcache.demand_miss_latency::total 10304545 # number of demand (read+write) miss cycles
> system.cpu2.dcache.overall_miss_latency::cpu2.data 10304545 # number of overall miss cycles
> system.cpu2.dcache.overall_miss_latency::total 10304545 # number of overall miss cycles
> system.cpu2.dcache.ReadReq_accesses::cpu2.data 43221 # number of ReadReq accesses(hits+misses)
> system.cpu2.dcache.ReadReq_accesses::total 43221 # number of ReadReq accesses(hits+misses)
> system.cpu2.dcache.WriteReq_accesses::cpu2.data 32620 # number of WriteReq accesses(hits+misses)
> system.cpu2.dcache.WriteReq_accesses::total 32620 # number of WriteReq accesses(hits+misses)
> system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses)
> system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
> system.cpu2.dcache.demand_accesses::cpu2.data 75841 # number of demand (read+write) accesses
> system.cpu2.dcache.demand_accesses::total 75841 # number of demand (read+write) accesses
> system.cpu2.dcache.overall_accesses::cpu2.data 75841 # number of overall (read+write) accesses
> system.cpu2.dcache.overall_accesses::total 75841 # number of overall (read+write) accesses
> system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010180 # miss rate for ReadReq accesses
> system.cpu2.dcache.ReadReq_miss_rate::total 0.010180 # miss rate for ReadReq accesses
> system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004077 # miss rate for WriteReq accesses
> system.cpu2.dcache.WriteReq_miss_rate::total 0.004077 # miss rate for WriteReq accesses
> system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.802817 # miss rate for SwapReq accesses
> system.cpu2.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses
> system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007555 # miss rate for demand accesses
> system.cpu2.dcache.demand_miss_rate::total 0.007555 # miss rate for demand accesses
> system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007555 # miss rate for overall accesses
> system.cpu2.dcache.overall_miss_rate::total 0.007555 # miss rate for overall accesses
> system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16685.870455 # average ReadReq miss latency
> system.cpu2.dcache.ReadReq_avg_miss_latency::total 16685.870455 # average ReadReq miss latency
> system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22276.406015 # average WriteReq miss latency
> system.cpu2.dcache.WriteReq_avg_miss_latency::total 22276.406015 # average WriteReq miss latency
> system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10421.140351 # average SwapReq miss latency
> system.cpu2.dcache.SwapReq_avg_miss_latency::total 10421.140351 # average SwapReq miss latency
> system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17983.499127 # average overall miss latency
> system.cpu2.dcache.demand_avg_miss_latency::total 17983.499127 # average overall miss latency
> system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17983.499127 # average overall miss latency
> system.cpu2.dcache.overall_avg_miss_latency::total 17983.499127 # average overall miss latency
1710,1757c1710,1757
< system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 289 # number of ReadReq MSHR hits
< system.cpu2.dcache.ReadReq_mshr_hits::total 289 # number of ReadReq MSHR hits
< system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 41 # number of WriteReq MSHR hits
< system.cpu2.dcache.WriteReq_mshr_hits::total 41 # number of WriteReq MSHR hits
< system.cpu2.dcache.demand_mshr_hits::cpu2.data 330 # number of demand (read+write) MSHR hits
< system.cpu2.dcache.demand_mshr_hits::total 330 # number of demand (read+write) MSHR hits
< system.cpu2.dcache.overall_mshr_hits::cpu2.data 330 # number of overall MSHR hits
< system.cpu2.dcache.overall_mshr_hits::total 330 # number of overall MSHR hits
< system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 159 # number of ReadReq MSHR misses
< system.cpu2.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses
< system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses
< system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses
< system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 55 # number of SwapReq MSHR misses
< system.cpu2.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses
< system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses
< system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses
< system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses
< system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses
< system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1526276 # number of ReadReq MSHR miss cycles
< system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1526276 # number of ReadReq MSHR miss cycles
< system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1511738 # number of WriteReq MSHR miss cycles
< system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1511738 # number of WriteReq MSHR miss cycles
< system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 395492 # number of SwapReq MSHR miss cycles
< system.cpu2.dcache.SwapReq_mshr_miss_latency::total 395492 # number of SwapReq MSHR miss cycles
< system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3038014 # number of demand (read+write) MSHR miss cycles
< system.cpu2.dcache.demand_mshr_miss_latency::total 3038014 # number of demand (read+write) MSHR miss cycles
< system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3038014 # number of overall MSHR miss cycles
< system.cpu2.dcache.overall_mshr_miss_latency::total 3038014 # number of overall MSHR miss cycles
< system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003383 # mshr miss rate for ReadReq accesses
< system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003383 # mshr miss rate for ReadReq accesses
< system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002833 # mshr miss rate for WriteReq accesses
< system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002833 # mshr miss rate for WriteReq accesses
< system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.820896 # mshr miss rate for SwapReq accesses
< system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.820896 # mshr miss rate for SwapReq accesses
< system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003137 # mshr miss rate for demand accesses
< system.cpu2.dcache.demand_mshr_miss_rate::total 0.003137 # mshr miss rate for demand accesses
< system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003137 # mshr miss rate for overall accesses
< system.cpu2.dcache.overall_mshr_miss_rate::total 0.003137 # mshr miss rate for overall accesses
< system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9599.220126 # average ReadReq mshr miss latency
< system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9599.220126 # average ReadReq mshr miss latency
< system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13997.574074 # average WriteReq mshr miss latency
< system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13997.574074 # average WriteReq mshr miss latency
< system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7190.763636 # average SwapReq mshr miss latency
< system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7190.763636 # average SwapReq mshr miss latency
< system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11378.329588 # average overall mshr miss latency
< system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11378.329588 # average overall mshr miss latency
< system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11378.329588 # average overall mshr miss latency
< system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11378.329588 # average overall mshr miss latency
---
> system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 285 # number of ReadReq MSHR hits
> system.cpu2.dcache.ReadReq_mshr_hits::total 285 # number of ReadReq MSHR hits
> system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 31 # number of WriteReq MSHR hits
> system.cpu2.dcache.WriteReq_mshr_hits::total 31 # number of WriteReq MSHR hits
> system.cpu2.dcache.demand_mshr_hits::cpu2.data 316 # number of demand (read+write) MSHR hits
> system.cpu2.dcache.demand_mshr_hits::total 316 # number of demand (read+write) MSHR hits
> system.cpu2.dcache.overall_mshr_hits::cpu2.data 316 # number of overall MSHR hits
> system.cpu2.dcache.overall_mshr_hits::total 316 # number of overall MSHR hits
> system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 155 # number of ReadReq MSHR misses
> system.cpu2.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses
> system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 102 # number of WriteReq MSHR misses
> system.cpu2.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses
> system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 57 # number of SwapReq MSHR misses
> system.cpu2.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses
> system.cpu2.dcache.demand_mshr_misses::cpu2.data 257 # number of demand (read+write) MSHR misses
> system.cpu2.dcache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses
> system.cpu2.dcache.overall_mshr_misses::cpu2.data 257 # number of overall MSHR misses
> system.cpu2.dcache.overall_mshr_misses::total 257 # number of overall MSHR misses
> system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1424773 # number of ReadReq MSHR miss cycles
> system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1424773 # number of ReadReq MSHR miss cycles
> system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1555988 # number of WriteReq MSHR miss cycles
> system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1555988 # number of WriteReq MSHR miss cycles
> system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 508495 # number of SwapReq MSHR miss cycles
> system.cpu2.dcache.SwapReq_mshr_miss_latency::total 508495 # number of SwapReq MSHR miss cycles
> system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2980761 # number of demand (read+write) MSHR miss cycles
> system.cpu2.dcache.demand_mshr_miss_latency::total 2980761 # number of demand (read+write) MSHR miss cycles
> system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2980761 # number of overall MSHR miss cycles
> system.cpu2.dcache.overall_mshr_miss_latency::total 2980761 # number of overall MSHR miss cycles
> system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003586 # mshr miss rate for ReadReq accesses
> system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003586 # mshr miss rate for ReadReq accesses
> system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003127 # mshr miss rate for WriteReq accesses
> system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003127 # mshr miss rate for WriteReq accesses
> system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.802817 # mshr miss rate for SwapReq accesses
> system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses
> system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003389 # mshr miss rate for demand accesses
> system.cpu2.dcache.demand_mshr_miss_rate::total 0.003389 # mshr miss rate for demand accesses
> system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003389 # mshr miss rate for overall accesses
> system.cpu2.dcache.overall_mshr_miss_rate::total 0.003389 # mshr miss rate for overall accesses
> system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9192.083871 # average ReadReq mshr miss latency
> system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9192.083871 # average ReadReq mshr miss latency
> system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15254.784314 # average WriteReq mshr miss latency
> system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15254.784314 # average WriteReq mshr miss latency
> system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8920.964912 # average SwapReq mshr miss latency
> system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8920.964912 # average SwapReq mshr miss latency
> system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11598.291829 # average overall mshr miss latency
> system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11598.291829 # average overall mshr miss latency
> system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11598.291829 # average overall mshr miss latency
> system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11598.291829 # average overall mshr miss latency
1759,1763c1759,1763
< system.cpu2.icache.tags.replacements 378 # number of replacements
< system.cpu2.icache.tags.tagsinuse 84.872672 # Cycle average of tags in use
< system.cpu2.icache.tags.total_refs 18881 # Total number of references to valid blocks.
< system.cpu2.icache.tags.sampled_refs 490 # Sample count of references to valid blocks.
< system.cpu2.icache.tags.avg_refs 38.532653 # Average number of references to valid blocks.
---
> system.cpu2.icache.tags.replacements 384 # number of replacements
> system.cpu2.icache.tags.tagsinuse 78.035025 # Cycle average of tags in use
> system.cpu2.icache.tags.total_refs 22324 # Total number of references to valid blocks.
> system.cpu2.icache.tags.sampled_refs 494 # Sample count of references to valid blocks.
> system.cpu2.icache.tags.avg_refs 45.190283 # Average number of references to valid blocks.
1765,1768c1765,1768
< system.cpu2.icache.tags.occ_blocks::cpu2.inst 84.872672 # Average occupied blocks per requestor
< system.cpu2.icache.tags.occ_percent::cpu2.inst 0.165767 # Average percentage of cache occupancy
< system.cpu2.icache.tags.occ_percent::total 0.165767 # Average percentage of cache occupancy
< system.cpu2.icache.tags.occ_task_id_blocks::1024 112 # Occupied blocks per task id
---
> system.cpu2.icache.tags.occ_blocks::cpu2.inst 78.035025 # Average occupied blocks per requestor
> system.cpu2.icache.tags.occ_percent::cpu2.inst 0.152412 # Average percentage of cache occupancy
> system.cpu2.icache.tags.occ_percent::total 0.152412 # Average percentage of cache occupancy
> system.cpu2.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id
1770,1810c1770,1810
< system.cpu2.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id
< system.cpu2.icache.tags.occ_task_id_percent::1024 0.218750 # Percentage of cache occupancy per task id
< system.cpu2.icache.tags.tag_accesses 19941 # Number of tag accesses
< system.cpu2.icache.tags.data_accesses 19941 # Number of data accesses
< system.cpu2.icache.ReadReq_hits::cpu2.inst 18881 # number of ReadReq hits
< system.cpu2.icache.ReadReq_hits::total 18881 # number of ReadReq hits
< system.cpu2.icache.demand_hits::cpu2.inst 18881 # number of demand (read+write) hits
< system.cpu2.icache.demand_hits::total 18881 # number of demand (read+write) hits
< system.cpu2.icache.overall_hits::cpu2.inst 18881 # number of overall hits
< system.cpu2.icache.overall_hits::total 18881 # number of overall hits
< system.cpu2.icache.ReadReq_misses::cpu2.inst 570 # number of ReadReq misses
< system.cpu2.icache.ReadReq_misses::total 570 # number of ReadReq misses
< system.cpu2.icache.demand_misses::cpu2.inst 570 # number of demand (read+write) misses
< system.cpu2.icache.demand_misses::total 570 # number of demand (read+write) misses
< system.cpu2.icache.overall_misses::cpu2.inst 570 # number of overall misses
< system.cpu2.icache.overall_misses::total 570 # number of overall misses
< system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 13340243 # number of ReadReq miss cycles
< system.cpu2.icache.ReadReq_miss_latency::total 13340243 # number of ReadReq miss cycles
< system.cpu2.icache.demand_miss_latency::cpu2.inst 13340243 # number of demand (read+write) miss cycles
< system.cpu2.icache.demand_miss_latency::total 13340243 # number of demand (read+write) miss cycles
< system.cpu2.icache.overall_miss_latency::cpu2.inst 13340243 # number of overall miss cycles
< system.cpu2.icache.overall_miss_latency::total 13340243 # number of overall miss cycles
< system.cpu2.icache.ReadReq_accesses::cpu2.inst 19451 # number of ReadReq accesses(hits+misses)
< system.cpu2.icache.ReadReq_accesses::total 19451 # number of ReadReq accesses(hits+misses)
< system.cpu2.icache.demand_accesses::cpu2.inst 19451 # number of demand (read+write) accesses
< system.cpu2.icache.demand_accesses::total 19451 # number of demand (read+write) accesses
< system.cpu2.icache.overall_accesses::cpu2.inst 19451 # number of overall (read+write) accesses
< system.cpu2.icache.overall_accesses::total 19451 # number of overall (read+write) accesses
< system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.029304 # miss rate for ReadReq accesses
< system.cpu2.icache.ReadReq_miss_rate::total 0.029304 # miss rate for ReadReq accesses
< system.cpu2.icache.demand_miss_rate::cpu2.inst 0.029304 # miss rate for demand accesses
< system.cpu2.icache.demand_miss_rate::total 0.029304 # miss rate for demand accesses
< system.cpu2.icache.overall_miss_rate::cpu2.inst 0.029304 # miss rate for overall accesses
< system.cpu2.icache.overall_miss_rate::total 0.029304 # miss rate for overall accesses
< system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23403.935088 # average ReadReq miss latency
< system.cpu2.icache.ReadReq_avg_miss_latency::total 23403.935088 # average ReadReq miss latency
< system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23403.935088 # average overall miss latency
< system.cpu2.icache.demand_avg_miss_latency::total 23403.935088 # average overall miss latency
< system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23403.935088 # average overall miss latency
< system.cpu2.icache.overall_avg_miss_latency::total 23403.935088 # average overall miss latency
< system.cpu2.icache.blocked_cycles::no_mshrs 128 # number of cycles access was blocked
---
> system.cpu2.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id
> system.cpu2.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id
> system.cpu2.icache.tags.tag_accesses 23378 # Number of tag accesses
> system.cpu2.icache.tags.data_accesses 23378 # Number of data accesses
> system.cpu2.icache.ReadReq_hits::cpu2.inst 22324 # number of ReadReq hits
> system.cpu2.icache.ReadReq_hits::total 22324 # number of ReadReq hits
> system.cpu2.icache.demand_hits::cpu2.inst 22324 # number of demand (read+write) hits
> system.cpu2.icache.demand_hits::total 22324 # number of demand (read+write) hits
> system.cpu2.icache.overall_hits::cpu2.inst 22324 # number of overall hits
> system.cpu2.icache.overall_hits::total 22324 # number of overall hits
> system.cpu2.icache.ReadReq_misses::cpu2.inst 560 # number of ReadReq misses
> system.cpu2.icache.ReadReq_misses::total 560 # number of ReadReq misses
> system.cpu2.icache.demand_misses::cpu2.inst 560 # number of demand (read+write) misses
> system.cpu2.icache.demand_misses::total 560 # number of demand (read+write) misses
> system.cpu2.icache.overall_misses::cpu2.inst 560 # number of overall misses
> system.cpu2.icache.overall_misses::total 560 # number of overall misses
> system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8454990 # number of ReadReq miss cycles
> system.cpu2.icache.ReadReq_miss_latency::total 8454990 # number of ReadReq miss cycles
> system.cpu2.icache.demand_miss_latency::cpu2.inst 8454990 # number of demand (read+write) miss cycles
> system.cpu2.icache.demand_miss_latency::total 8454990 # number of demand (read+write) miss cycles
> system.cpu2.icache.overall_miss_latency::cpu2.inst 8454990 # number of overall miss cycles
> system.cpu2.icache.overall_miss_latency::total 8454990 # number of overall miss cycles
> system.cpu2.icache.ReadReq_accesses::cpu2.inst 22884 # number of ReadReq accesses(hits+misses)
> system.cpu2.icache.ReadReq_accesses::total 22884 # number of ReadReq accesses(hits+misses)
> system.cpu2.icache.demand_accesses::cpu2.inst 22884 # number of demand (read+write) accesses
> system.cpu2.icache.demand_accesses::total 22884 # number of demand (read+write) accesses
> system.cpu2.icache.overall_accesses::cpu2.inst 22884 # number of overall (read+write) accesses
> system.cpu2.icache.overall_accesses::total 22884 # number of overall (read+write) accesses
> system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024471 # miss rate for ReadReq accesses
> system.cpu2.icache.ReadReq_miss_rate::total 0.024471 # miss rate for ReadReq accesses
> system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024471 # miss rate for demand accesses
> system.cpu2.icache.demand_miss_rate::total 0.024471 # miss rate for demand accesses
> system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024471 # miss rate for overall accesses
> system.cpu2.icache.overall_miss_rate::total 0.024471 # miss rate for overall accesses
> system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15098.196429 # average ReadReq miss latency
> system.cpu2.icache.ReadReq_avg_miss_latency::total 15098.196429 # average ReadReq miss latency
> system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15098.196429 # average overall miss latency
> system.cpu2.icache.demand_avg_miss_latency::total 15098.196429 # average overall miss latency
> system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15098.196429 # average overall miss latency
> system.cpu2.icache.overall_avg_miss_latency::total 15098.196429 # average overall miss latency
> system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1812c1812
< system.cpu2.icache.blocked::no_mshrs 3 # number of cycles access was blocked
---
> system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1814c1814
< system.cpu2.icache.avg_blocked_cycles::no_mshrs 42.666667 # average number of cycles each access was blocked
---
> system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1818,1847c1818,1847
< system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 80 # number of ReadReq MSHR hits
< system.cpu2.icache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits
< system.cpu2.icache.demand_mshr_hits::cpu2.inst 80 # number of demand (read+write) MSHR hits
< system.cpu2.icache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits
< system.cpu2.icache.overall_mshr_hits::cpu2.inst 80 # number of overall MSHR hits
< system.cpu2.icache.overall_mshr_hits::total 80 # number of overall MSHR hits
< system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 490 # number of ReadReq MSHR misses
< system.cpu2.icache.ReadReq_mshr_misses::total 490 # number of ReadReq MSHR misses
< system.cpu2.icache.demand_mshr_misses::cpu2.inst 490 # number of demand (read+write) MSHR misses
< system.cpu2.icache.demand_mshr_misses::total 490 # number of demand (read+write) MSHR misses
< system.cpu2.icache.overall_mshr_misses::cpu2.inst 490 # number of overall MSHR misses
< system.cpu2.icache.overall_mshr_misses::total 490 # number of overall MSHR misses
< system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10370006 # number of ReadReq MSHR miss cycles
< system.cpu2.icache.ReadReq_mshr_miss_latency::total 10370006 # number of ReadReq MSHR miss cycles
< system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10370006 # number of demand (read+write) MSHR miss cycles
< system.cpu2.icache.demand_mshr_miss_latency::total 10370006 # number of demand (read+write) MSHR miss cycles
< system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10370006 # number of overall MSHR miss cycles
< system.cpu2.icache.overall_mshr_miss_latency::total 10370006 # number of overall MSHR miss cycles
< system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.025192 # mshr miss rate for ReadReq accesses
< system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.025192 # mshr miss rate for ReadReq accesses
< system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.025192 # mshr miss rate for demand accesses
< system.cpu2.icache.demand_mshr_miss_rate::total 0.025192 # mshr miss rate for demand accesses
< system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.025192 # mshr miss rate for overall accesses
< system.cpu2.icache.overall_mshr_miss_rate::total 0.025192 # mshr miss rate for overall accesses
< system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21163.277551 # average ReadReq mshr miss latency
< system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21163.277551 # average ReadReq mshr miss latency
< system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21163.277551 # average overall mshr miss latency
< system.cpu2.icache.demand_avg_mshr_miss_latency::total 21163.277551 # average overall mshr miss latency
< system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21163.277551 # average overall mshr miss latency
< system.cpu2.icache.overall_avg_mshr_miss_latency::total 21163.277551 # average overall mshr miss latency
---
> system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 66 # number of ReadReq MSHR hits
> system.cpu2.icache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits
> system.cpu2.icache.demand_mshr_hits::cpu2.inst 66 # number of demand (read+write) MSHR hits
> system.cpu2.icache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits
> system.cpu2.icache.overall_mshr_hits::cpu2.inst 66 # number of overall MSHR hits
> system.cpu2.icache.overall_mshr_hits::total 66 # number of overall MSHR hits
> system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 494 # number of ReadReq MSHR misses
> system.cpu2.icache.ReadReq_mshr_misses::total 494 # number of ReadReq MSHR misses
> system.cpu2.icache.demand_mshr_misses::cpu2.inst 494 # number of demand (read+write) MSHR misses
> system.cpu2.icache.demand_mshr_misses::total 494 # number of demand (read+write) MSHR misses
> system.cpu2.icache.overall_mshr_misses::cpu2.inst 494 # number of overall MSHR misses
> system.cpu2.icache.overall_mshr_misses::total 494 # number of overall MSHR misses
> system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6668508 # number of ReadReq MSHR miss cycles
> system.cpu2.icache.ReadReq_mshr_miss_latency::total 6668508 # number of ReadReq MSHR miss cycles
> system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6668508 # number of demand (read+write) MSHR miss cycles
> system.cpu2.icache.demand_mshr_miss_latency::total 6668508 # number of demand (read+write) MSHR miss cycles
> system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6668508 # number of overall MSHR miss cycles
> system.cpu2.icache.overall_mshr_miss_latency::total 6668508 # number of overall MSHR miss cycles
> system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021587 # mshr miss rate for ReadReq accesses
> system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021587 # mshr miss rate for ReadReq accesses
> system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021587 # mshr miss rate for demand accesses
> system.cpu2.icache.demand_mshr_miss_rate::total 0.021587 # mshr miss rate for demand accesses
> system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021587 # mshr miss rate for overall accesses
> system.cpu2.icache.overall_mshr_miss_rate::total 0.021587 # mshr miss rate for overall accesses
> system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13499.004049 # average ReadReq mshr miss latency
> system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13499.004049 # average ReadReq mshr miss latency
> system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13499.004049 # average overall mshr miss latency
> system.cpu2.icache.demand_avg_mshr_miss_latency::total 13499.004049 # average overall mshr miss latency
> system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13499.004049 # average overall mshr miss latency
> system.cpu2.icache.overall_avg_mshr_miss_latency::total 13499.004049 # average overall mshr miss latency
1849,1853c1849,1853
< system.cpu3.branchPred.lookups 49708 # Number of BP lookups
< system.cpu3.branchPred.condPredicted 46346 # Number of conditional branches predicted
< system.cpu3.branchPred.condIncorrect 1279 # Number of conditional branches incorrect
< system.cpu3.branchPred.BTBLookups 42456 # Number of BTB lookups
< system.cpu3.branchPred.BTBHits 41477 # Number of BTB hits
---
> system.cpu3.branchPred.lookups 49957 # Number of BP lookups
> system.cpu3.branchPred.condPredicted 46526 # Number of conditional branches predicted
> system.cpu3.branchPred.condIncorrect 1263 # Number of conditional branches incorrect
> system.cpu3.branchPred.BTBLookups 42773 # Number of BTB lookups
> system.cpu3.branchPred.BTBHits 41661 # Number of BTB hits
1855,1856c1855,1856
< system.cpu3.branchPred.BTBHitPct 97.694083 # BTB Hit Percentage
< system.cpu3.branchPred.usedRAS 887 # Number of times the RAS was used to get a target.
---
> system.cpu3.branchPred.BTBHitPct 97.400229 # BTB Hit Percentage
> system.cpu3.branchPred.usedRAS 886 # Number of times the RAS was used to get a target.
1858c1858
< system.cpu3.numCycles 160031 # number of cpu cycles simulated
---
> system.cpu3.numCycles 161075 # number of cpu cycles simulated
1861,1866c1861,1866
< system.cpu3.fetch.icacheStallCycles 32677 # Number of cycles fetch is stalled on an Icache miss
< system.cpu3.fetch.Insts 271496 # Number of instructions fetch has processed
< system.cpu3.fetch.Branches 49708 # Number of branches that fetch encountered
< system.cpu3.fetch.predictedBranches 42364 # Number of branches that fetch has predicted taken
< system.cpu3.fetch.Cycles 123781 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu3.fetch.SquashCycles 2713 # Number of cycles fetch has spent squashing
---
> system.cpu3.fetch.icacheStallCycles 32422 # Number of cycles fetch is stalled on an Icache miss
> system.cpu3.fetch.Insts 272949 # Number of instructions fetch has processed
> system.cpu3.fetch.Branches 49957 # Number of branches that fetch encountered
> system.cpu3.fetch.predictedBranches 42547 # Number of branches that fetch has predicted taken
> system.cpu3.fetch.Cycles 124988 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu3.fetch.SquashCycles 2685 # Number of cycles fetch has spent squashing
1869,1874c1869,1874
< system.cpu3.fetch.PendingTrapStallCycles 1129 # Number of stall cycles due to pending traps
< system.cpu3.fetch.CacheLines 23830 # Number of cache lines fetched
< system.cpu3.fetch.IcacheSquashes 414 # Number of outstanding Icache misses that were squashed
< system.cpu3.fetch.rateDist::samples 158956 # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::mean 1.707995 # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::stdev 2.148637 # Number of instructions fetched each cycle (Total)
---
> system.cpu3.fetch.PendingTrapStallCycles 1170 # Number of stall cycles due to pending traps
> system.cpu3.fetch.CacheLines 23669 # Number of cache lines fetched
> system.cpu3.fetch.IcacheSquashes 411 # Number of outstanding Icache misses that were squashed
> system.cpu3.fetch.rateDist::samples 159935 # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::mean 1.706625 # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::stdev 2.149562 # Number of instructions fetched each cycle (Total)
1876,1884c1876,1884
< system.cpu3.fetch.rateDist::0 61281 38.55% 38.55% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::1 50034 31.48% 70.03% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::2 7755 4.88% 74.91% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::3 3467 2.18% 77.09% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::4 1003 0.63% 77.72% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::5 29472 18.54% 96.26% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::6 1313 0.83% 97.09% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::7 747 0.47% 97.56% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::8 3884 2.44% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu3.fetch.rateDist::0 61940 38.73% 38.73% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::1 50129 31.34% 70.07% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::2 7684 4.80% 74.88% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::3 3433 2.15% 77.02% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::4 1026 0.64% 77.66% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::5 29810 18.64% 96.30% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::6 1265 0.79% 97.09% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::7 775 0.48% 97.58% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::8 3873 2.42% 100.00% # Number of instructions fetched each cycle (Total)
1888,1928c1888,1928
< system.cpu3.fetch.rateDist::total 158956 # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.branchRate 0.310615 # Number of branch fetches per cycle
< system.cpu3.fetch.rate 1.696521 # Number of inst fetches per cycle
< system.cpu3.decode.IdleCycles 17592 # Number of cycles decode is idle
< system.cpu3.decode.BlockedCycles 63734 # Number of cycles decode is blocked
< system.cpu3.decode.RunCycles 72321 # Number of cycles decode is running
< system.cpu3.decode.UnblockCycles 3943 # Number of cycles decode is unblocking
< system.cpu3.decode.SquashCycles 1356 # Number of cycles decode is squashing
< system.cpu3.decode.DecodedInsts 257189 # Number of instructions handled by decode
< system.cpu3.rename.SquashCycles 1356 # Number of cycles rename is squashing
< system.cpu3.rename.IdleCycles 18288 # Number of cycles rename is idle
< system.cpu3.rename.BlockCycles 30790 # Number of cycles rename is blocking
< system.cpu3.rename.serializeStallCycles 12415 # count of cycles rename stalled for serializing inst
< system.cpu3.rename.RunCycles 73229 # Number of cycles rename is running
< system.cpu3.rename.UnblockCycles 22868 # Number of cycles rename is unblocking
< system.cpu3.rename.RenamedInsts 253914 # Number of instructions processed by rename
< system.cpu3.rename.IQFullEvents 19808 # Number of times rename has blocked due to IQ full
< system.cpu3.rename.LQFullEvents 26 # Number of times rename has blocked due to LQ full
< system.cpu3.rename.FullRegisterEvents 3 # Number of times there has been no free registers
< system.cpu3.rename.RenamedOperands 177532 # Number of destination operands rename has renamed
< system.cpu3.rename.RenameLookups 480099 # Number of register rename lookups that rename has made
< system.cpu3.rename.int_rename_lookups 375267 # Number of integer rename lookups
< system.cpu3.rename.CommittedMaps 162743 # Number of HB maps that are committed
< system.cpu3.rename.UndoneMaps 14789 # Number of HB maps that are undone due to squashing
< system.cpu3.rename.serializingInsts 1176 # count of serializing insts renamed
< system.cpu3.rename.tempSerializingInsts 1243 # count of temporary serializing insts renamed
< system.cpu3.rename.skidInsts 27539 # count of insts added to the skid buffer
< system.cpu3.memDep0.insertedLoads 69653 # Number of loads inserted to the mem dependence unit.
< system.cpu3.memDep0.insertedStores 32298 # Number of stores inserted to the mem dependence unit.
< system.cpu3.memDep0.conflictingLoads 33633 # Number of conflicting loads.
< system.cpu3.memDep0.conflictingStores 27116 # Number of conflicting stores.
< system.cpu3.iq.iqInstsAdded 209239 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu3.iq.iqNonSpecInstsAdded 7471 # Number of non-speculative instructions added to the IQ
< system.cpu3.iq.iqInstsIssued 211679 # Number of instructions issued
< system.cpu3.iq.iqSquashedInstsIssued 49 # Number of squashed instructions issued
< system.cpu3.iq.iqSquashedInstsExamined 13005 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu3.iq.iqSquashedOperandsExamined 11959 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu3.iq.iqSquashedNonSpecRemoved 663 # Number of squashed non-spec instructions that were removed
< system.cpu3.iq.issued_per_cycle::samples 158956 # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::mean 1.331683 # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::stdev 1.377458 # Number of insts issued each cycle
---
> system.cpu3.fetch.rateDist::total 159935 # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.branchRate 0.310147 # Number of branch fetches per cycle
> system.cpu3.fetch.rate 1.694546 # Number of inst fetches per cycle
> system.cpu3.decode.IdleCycles 17524 # Number of cycles decode is idle
> system.cpu3.decode.BlockedCycles 64435 # Number of cycles decode is blocked
> system.cpu3.decode.RunCycles 72722 # Number of cycles decode is running
> system.cpu3.decode.UnblockCycles 3902 # Number of cycles decode is unblocking
> system.cpu3.decode.SquashCycles 1342 # Number of cycles decode is squashing
> system.cpu3.decode.DecodedInsts 258692 # Number of instructions handled by decode
> system.cpu3.rename.SquashCycles 1342 # Number of cycles rename is squashing
> system.cpu3.rename.IdleCycles 18198 # Number of cycles rename is idle
> system.cpu3.rename.BlockCycles 31170 # Number of cycles rename is blocking
> system.cpu3.rename.serializeStallCycles 12771 # count of cycles rename stalled for serializing inst
> system.cpu3.rename.RunCycles 73832 # Number of cycles rename is running
> system.cpu3.rename.UnblockCycles 22612 # Number of cycles rename is unblocking
> system.cpu3.rename.RenamedInsts 255419 # Number of instructions processed by rename
> system.cpu3.rename.IQFullEvents 19775 # Number of times rename has blocked due to IQ full
> system.cpu3.rename.LQFullEvents 23 # Number of times rename has blocked due to LQ full
> system.cpu3.rename.FullRegisterEvents 2 # Number of times there has been no free registers
> system.cpu3.rename.RenamedOperands 178600 # Number of destination operands rename has renamed
> system.cpu3.rename.RenameLookups 483471 # Number of register rename lookups that rename has made
> system.cpu3.rename.int_rename_lookups 377749 # Number of integer rename lookups
> system.cpu3.rename.CommittedMaps 164114 # Number of HB maps that are committed
> system.cpu3.rename.UndoneMaps 14486 # Number of HB maps that are undone due to squashing
> system.cpu3.rename.serializingInsts 1167 # count of serializing insts renamed
> system.cpu3.rename.tempSerializingInsts 1234 # count of temporary serializing insts renamed
> system.cpu3.rename.skidInsts 27248 # count of insts added to the skid buffer
> system.cpu3.memDep0.insertedLoads 70256 # Number of loads inserted to the mem dependence unit.
> system.cpu3.memDep0.insertedStores 32624 # Number of stores inserted to the mem dependence unit.
> system.cpu3.memDep0.conflictingLoads 33902 # Number of conflicting loads.
> system.cpu3.memDep0.conflictingStores 27488 # Number of conflicting stores.
> system.cpu3.iq.iqInstsAdded 210626 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu3.iq.iqNonSpecInstsAdded 7365 # Number of non-speculative instructions added to the IQ
> system.cpu3.iq.iqInstsIssued 213102 # Number of instructions issued
> system.cpu3.iq.iqSquashedInstsIssued 40 # Number of squashed instructions issued
> system.cpu3.iq.iqSquashedInstsExamined 12659 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu3.iq.iqSquashedOperandsExamined 11687 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu3.iq.iqSquashedNonSpecRemoved 617 # Number of squashed non-spec instructions that were removed
> system.cpu3.iq.issued_per_cycle::samples 159935 # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::mean 1.332429 # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::stdev 1.375890 # Number of insts issued each cycle
1930,1938c1930,1938
< system.cpu3.iq.issued_per_cycle::0 65156 40.99% 40.99% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::1 24774 15.59% 56.58% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::2 31508 19.82% 76.40% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::3 31138 19.59% 95.99% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::4 3432 2.16% 98.15% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::5 1609 1.01% 99.16% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::6 879 0.55% 99.71% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::7 252 0.16% 99.87% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::8 208 0.13% 100.00% # Number of insts issued each cycle
---
> system.cpu3.iq.issued_per_cycle::0 65625 41.03% 41.03% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::1 24603 15.38% 56.42% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::2 31869 19.93% 76.34% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::3 31495 19.69% 96.03% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::4 3384 2.12% 98.15% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::5 1646 1.03% 99.18% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::6 880 0.55% 99.73% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::7 234 0.15% 99.88% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::8 199 0.12% 100.00% # Number of insts issued each cycle
1942c1942
< system.cpu3.iq.issued_per_cycle::total 158956 # Number of insts issued each cycle
---
> system.cpu3.iq.issued_per_cycle::total 159935 # Number of insts issued each cycle
1944,1974c1944,1974
< system.cpu3.iq.fu_full::IntAlu 91 25.07% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::IntMult 0 0.00% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::IntDiv 0 0.00% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.07% # attempts to use FU when none available
< system.cpu3.iq.fu_full::MemRead 63 17.36% 42.42% # attempts to use FU when none available
< system.cpu3.iq.fu_full::MemWrite 209 57.58% 100.00% # attempts to use FU when none available
---
> system.cpu3.iq.fu_full::IntAlu 83 23.71% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::IntMult 0 0.00% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::IntDiv 0 0.00% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::FloatAdd 0 0.00% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::FloatCmp 0 0.00% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::FloatCvt 0 0.00% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::FloatMult 0 0.00% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::FloatDiv 0 0.00% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdAdd 0 0.00% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdAlu 0 0.00% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdCmp 0 0.00% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdCvt 0 0.00% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdMisc 0 0.00% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdMult 0 0.00% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdShift 0 0.00% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 23.71% # attempts to use FU when none available
> system.cpu3.iq.fu_full::MemRead 58 16.57% 40.29% # attempts to use FU when none available
> system.cpu3.iq.fu_full::MemWrite 209 59.71% 100.00% # attempts to use FU when none available
1978,2008c1978,2008
< system.cpu3.iq.FU_type_0::IntAlu 105163 49.68% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.68% # Type of FU issued
< system.cpu3.iq.FU_type_0::MemRead 74926 35.40% 85.08% # Type of FU issued
< system.cpu3.iq.FU_type_0::MemWrite 31590 14.92% 100.00% # Type of FU issued
---
> system.cpu3.iq.FU_type_0::IntAlu 105687 49.59% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.59% # Type of FU issued
> system.cpu3.iq.FU_type_0::MemRead 75490 35.42% 85.02% # Type of FU issued
> system.cpu3.iq.FU_type_0::MemWrite 31925 14.98% 100.00% # Type of FU issued
2011,2017c2011,2017
< system.cpu3.iq.FU_type_0::total 211679 # Type of FU issued
< system.cpu3.iq.rate 1.322737 # Inst issue rate
< system.cpu3.iq.fu_busy_cnt 363 # FU busy when requested
< system.cpu3.iq.fu_busy_rate 0.001715 # FU busy rate (busy events/executed inst)
< system.cpu3.iq.int_inst_queue_reads 582726 # Number of integer instruction queue reads
< system.cpu3.iq.int_inst_queue_writes 229757 # Number of integer instruction queue writes
< system.cpu3.iq.int_inst_queue_wakeup_accesses 209929 # Number of integer instruction queue wakeup accesses
---
> system.cpu3.iq.FU_type_0::total 213102 # Type of FU issued
> system.cpu3.iq.rate 1.322999 # Inst issue rate
> system.cpu3.iq.fu_busy_cnt 350 # FU busy when requested
> system.cpu3.iq.fu_busy_rate 0.001642 # FU busy rate (busy events/executed inst)
> system.cpu3.iq.int_inst_queue_reads 586529 # Number of integer instruction queue reads
> system.cpu3.iq.int_inst_queue_writes 230693 # Number of integer instruction queue writes
> system.cpu3.iq.int_inst_queue_wakeup_accesses 211399 # Number of integer instruction queue wakeup accesses
2021c2021
< system.cpu3.iq.int_alu_accesses 212042 # Number of integer alu accesses
---
> system.cpu3.iq.int_alu_accesses 213452 # Number of integer alu accesses
2023c2023
< system.cpu3.iew.lsq.thread0.forwLoads 26876 # Number of loads that had data forwarded from stores
---
> system.cpu3.iew.lsq.thread0.forwLoads 27230 # Number of loads that had data forwarded from stores
2025c2025
< system.cpu3.iew.lsq.thread0.squashedLoads 2797 # Number of loads squashed
---
> system.cpu3.iew.lsq.thread0.squashedLoads 2740 # Number of loads squashed
2027,2028c2027,2028
< system.cpu3.iew.lsq.thread0.memOrderViolation 42 # Number of memory ordering violations
< system.cpu3.iew.lsq.thread0.squashedStores 1652 # Number of stores squashed
---
> system.cpu3.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations
> system.cpu3.iew.lsq.thread0.squashedStores 1625 # Number of stores squashed
2034,2041c2034,2041
< system.cpu3.iew.iewSquashCycles 1356 # Number of cycles IEW is squashing
< system.cpu3.iew.iewBlockCycles 8047 # Number of cycles IEW is blocking
< system.cpu3.iew.iewUnblockCycles 61 # Number of cycles IEW is unblocking
< system.cpu3.iew.iewDispatchedInsts 251105 # Number of instructions dispatched to IQ
< system.cpu3.iew.iewDispSquashedInsts 176 # Number of squashed instructions skipped by dispatch
< system.cpu3.iew.iewDispLoadInsts 69653 # Number of dispatched load instructions
< system.cpu3.iew.iewDispStoreInsts 32298 # Number of dispatched store instructions
< system.cpu3.iew.iewDispNonSpecInsts 1093 # Number of dispatched non-speculative instructions
---
> system.cpu3.iew.iewSquashCycles 1342 # Number of cycles IEW is squashing
> system.cpu3.iew.iewBlockCycles 8471 # Number of cycles IEW is blocking
> system.cpu3.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking
> system.cpu3.iew.iewDispatchedInsts 252649 # Number of instructions dispatched to IQ
> system.cpu3.iew.iewDispSquashedInsts 168 # Number of squashed instructions skipped by dispatch
> system.cpu3.iew.iewDispLoadInsts 70256 # Number of dispatched load instructions
> system.cpu3.iew.iewDispStoreInsts 32624 # Number of dispatched store instructions
> system.cpu3.iew.iewDispNonSpecInsts 1081 # Number of dispatched non-speculative instructions
2044,2050c2044,2050
< system.cpu3.iew.memOrderViolationEvents 42 # Number of memory order violations
< system.cpu3.iew.predictedTakenIncorrect 461 # Number of branches that were predicted taken incorrectly
< system.cpu3.iew.predictedNotTakenIncorrect 1042 # Number of branches that were predicted not taken incorrectly
< system.cpu3.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute
< system.cpu3.iew.iewExecutedInsts 210537 # Number of executed instructions
< system.cpu3.iew.iewExecLoadInsts 68521 # Number of load instructions executed
< system.cpu3.iew.iewExecSquashedInsts 1142 # Number of squashed instructions skipped in execute
---
> system.cpu3.iew.memOrderViolationEvents 43 # Number of memory order violations
> system.cpu3.iew.predictedTakenIncorrect 466 # Number of branches that were predicted taken incorrectly
> system.cpu3.iew.predictedNotTakenIncorrect 1012 # Number of branches that were predicted not taken incorrectly
> system.cpu3.iew.branchMispredicts 1478 # Number of branch mispredicts detected at execute
> system.cpu3.iew.iewExecutedInsts 211973 # Number of executed instructions
> system.cpu3.iew.iewExecLoadInsts 69143 # Number of load instructions executed
> system.cpu3.iew.iewExecSquashedInsts 1129 # Number of squashed instructions skipped in execute
2052,2060c2052,2060
< system.cpu3.iew.exec_nop 34395 # number of nop insts executed
< system.cpu3.iew.exec_refs 99995 # number of memory reference insts executed
< system.cpu3.iew.exec_branches 43728 # Number of branches executed
< system.cpu3.iew.exec_stores 31474 # Number of stores executed
< system.cpu3.iew.exec_rate 1.315601 # Inst execution rate
< system.cpu3.iew.wb_sent 210248 # cumulative count of insts sent to commit
< system.cpu3.iew.wb_count 209929 # cumulative count of insts written-back
< system.cpu3.iew.wb_producers 117676 # num instructions producing a value
< system.cpu3.iew.wb_consumers 124324 # num instructions consuming a value
---
> system.cpu3.iew.exec_nop 34658 # number of nop insts executed
> system.cpu3.iew.exec_refs 100953 # number of memory reference insts executed
> system.cpu3.iew.exec_branches 44015 # Number of branches executed
> system.cpu3.iew.exec_stores 31810 # Number of stores executed
> system.cpu3.iew.exec_rate 1.315989 # Inst execution rate
> system.cpu3.iew.wb_sent 211700 # cumulative count of insts sent to commit
> system.cpu3.iew.wb_count 211399 # cumulative count of insts written-back
> system.cpu3.iew.wb_producers 118601 # num instructions producing a value
> system.cpu3.iew.wb_consumers 125234 # num instructions consuming a value
2062,2063c2062,2063
< system.cpu3.iew.wb_rate 1.311802 # insts written-back per cycle
< system.cpu3.iew.wb_fanout 0.946527 # average fanout of values written-back
---
> system.cpu3.iew.wb_rate 1.312426 # insts written-back per cycle
> system.cpu3.iew.wb_fanout 0.947035 # average fanout of values written-back
2065,2070c2065,2070
< system.cpu3.commit.commitSquashedInsts 14613 # The number of squashed insts skipped by commit
< system.cpu3.commit.commitNonSpecStalls 6808 # The number of times commit has been forced to stall to communicate backwards
< system.cpu3.commit.branchMispredicts 1279 # The number of times a branch was mispredicted
< system.cpu3.commit.committed_per_cycle::samples 156309 # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::mean 1.512638 # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::stdev 2.007092 # Number of insts commited each cycle
---
> system.cpu3.commit.commitSquashedInsts 14249 # The number of squashed insts skipped by commit
> system.cpu3.commit.commitNonSpecStalls 6748 # The number of times commit has been forced to stall to communicate backwards
> system.cpu3.commit.branchMispredicts 1263 # The number of times a branch was mispredicted
> system.cpu3.commit.committed_per_cycle::samples 157342 # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::mean 1.514834 # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::stdev 2.009338 # Number of insts commited each cycle
2072,2080c2072,2080
< system.cpu3.commit.committed_per_cycle::0 71539 45.77% 45.77% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::1 40455 25.88% 71.65% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::2 5161 3.30% 74.95% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::3 7618 4.87% 79.82% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::4 1540 0.99% 80.81% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::5 26903 17.21% 98.02% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::6 829 0.53% 98.55% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::7 953 0.61% 99.16% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::8 1311 0.84% 100.00% # Number of insts commited each cycle
---
> system.cpu3.commit.committed_per_cycle::0 72048 45.79% 45.79% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::1 40652 25.84% 71.63% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::2 5170 3.29% 74.91% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::3 7572 4.81% 79.73% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::4 1532 0.97% 80.70% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::5 27266 17.33% 98.03% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::6 833 0.53% 98.56% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::7 969 0.62% 99.17% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::8 1300 0.83% 100.00% # Number of insts commited each cycle
2084,2086c2084,2086
< system.cpu3.commit.committed_per_cycle::total 156309 # Number of insts commited each cycle
< system.cpu3.commit.committedInsts 236439 # Number of instructions committed
< system.cpu3.commit.committedOps 236439 # Number of ops (including micro ops) committed
---
> system.cpu3.commit.committed_per_cycle::total 157342 # Number of insts commited each cycle
> system.cpu3.commit.committedInsts 238347 # Number of instructions committed
> system.cpu3.commit.committedOps 238347 # Number of ops (including micro ops) committed
2088,2091c2088,2091
< system.cpu3.commit.refs 97502 # Number of memory references committed
< system.cpu3.commit.loads 66856 # Number of loads committed
< system.cpu3.commit.membars 6091 # Number of memory barriers committed
< system.cpu3.commit.branches 42698 # Number of branches committed
---
> system.cpu3.commit.refs 98515 # Number of memory references committed
> system.cpu3.commit.loads 67516 # Number of loads committed
> system.cpu3.commit.membars 6034 # Number of memory barriers committed
> system.cpu3.commit.branches 42994 # Number of branches committed
2093c2093
< system.cpu3.commit.int_insts 162319 # Number of committed integer instructions.
---
> system.cpu3.commit.int_insts 163632 # Number of committed integer instructions.
2095,2126c2095,2126
< system.cpu3.commit.op_class_0::No_OpClass 33485 14.16% 14.16% # Class of committed instruction
< system.cpu3.commit.op_class_0::IntAlu 99361 42.02% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.19% # Class of committed instruction
< system.cpu3.commit.op_class_0::MemRead 72947 30.85% 87.04% # Class of committed instruction
< system.cpu3.commit.op_class_0::MemWrite 30646 12.96% 100.00% # Class of committed instruction
---
> system.cpu3.commit.op_class_0::No_OpClass 33784 14.17% 14.17% # Class of committed instruction
> system.cpu3.commit.op_class_0::IntAlu 100014 41.96% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.14% # Class of committed instruction
> system.cpu3.commit.op_class_0::MemRead 73550 30.86% 86.99% # Class of committed instruction
> system.cpu3.commit.op_class_0::MemWrite 30999 13.01% 100.00% # Class of committed instruction
2129,2130c2129,2130
< system.cpu3.commit.op_class_0::total 236439 # Class of committed instruction
< system.cpu3.commit.bw_lim_events 1311 # number cycles where commit BW limit reached
---
> system.cpu3.commit.op_class_0::total 238347 # Class of committed instruction
> system.cpu3.commit.bw_lim_events 1300 # number cycles where commit BW limit reached
2132,2144c2132,2144
< system.cpu3.rob.rob_reads 405464 # The number of ROB reads
< system.cpu3.rob.rob_writes 504751 # The number of ROB writes
< system.cpu3.timesIdled 203 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu3.idleCycles 1075 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu3.quiesceCycles 43988 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu3.committedInsts 196863 # Number of Instructions Simulated
< system.cpu3.committedOps 196863 # Number of Ops (including micro ops) Simulated
< system.cpu3.cpi 0.812905 # CPI: Cycles Per Instruction
< system.cpu3.cpi_total 0.812905 # CPI: Total CPI of All Threads
< system.cpu3.ipc 1.230155 # IPC: Instructions Per Cycle
< system.cpu3.ipc_total 1.230155 # IPC: Total IPC of All Threads
< system.cpu3.int_regfile_reads 359772 # number of integer regfile reads
< system.cpu3.int_regfile_writes 168916 # number of integer regfile writes
---
> system.cpu3.rob.rob_reads 408052 # The number of ROB reads
> system.cpu3.rob.rob_writes 507784 # The number of ROB writes
> system.cpu3.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu3.idleCycles 1140 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu3.quiesceCycles 47445 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu3.committedInsts 198529 # Number of Instructions Simulated
> system.cpu3.committedOps 198529 # Number of Ops (including micro ops) Simulated
> system.cpu3.cpi 0.811342 # CPI: Cycles Per Instruction
> system.cpu3.cpi_total 0.811342 # CPI: Total CPI of All Threads
> system.cpu3.ipc 1.232525 # IPC: Instructions Per Cycle
> system.cpu3.ipc_total 1.232525 # IPC: Total IPC of All Threads
> system.cpu3.int_regfile_reads 362535 # number of integer regfile reads
> system.cpu3.int_regfile_writes 170128 # number of integer regfile writes
2146c2146
< system.cpu3.misc_regfile_reads 101608 # number of misc regfile reads
---
> system.cpu3.misc_regfile_reads 102551 # number of misc regfile reads
2149,2152c2149,2152
< system.cpu3.dcache.tags.tagsinuse 24.432858 # Cycle average of tags in use
< system.cpu3.dcache.tags.total_refs 36837 # Total number of references to valid blocks.
< system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
< system.cpu3.dcache.tags.avg_refs 1270.241379 # Average number of references to valid blocks.
---
> system.cpu3.dcache.tags.tagsinuse 23.026048 # Cycle average of tags in use
> system.cpu3.dcache.tags.total_refs 37058 # Total number of references to valid blocks.
> system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
> system.cpu3.dcache.tags.avg_refs 1323.500000 # Average number of references to valid blocks.
2154,2158c2154,2157
< system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.432858 # Average occupied blocks per requestor
< system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047720 # Average percentage of cache occupancy
< system.cpu3.dcache.tags.occ_percent::total 0.047720 # Average percentage of cache occupancy
< system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
< system.cpu3.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
---
> system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.026048 # Average occupied blocks per requestor
> system.cpu3.dcache.tags.occ_percent::cpu3.data 0.044973 # Average percentage of cache occupancy
> system.cpu3.dcache.tags.occ_percent::total 0.044973 # Average percentage of cache occupancy
> system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id
2160,2166c2159,2165
< system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
< system.cpu3.dcache.tags.tag_accesses 289352 # Number of tag accesses
< system.cpu3.dcache.tags.data_accesses 289352 # Number of data accesses
< system.cpu3.dcache.ReadReq_hits::cpu3.data 41209 # number of ReadReq hits
< system.cpu3.dcache.ReadReq_hits::total 41209 # number of ReadReq hits
< system.cpu3.dcache.WriteReq_hits::cpu3.data 30434 # number of WriteReq hits
< system.cpu3.dcache.WriteReq_hits::total 30434 # number of WriteReq hits
---
> system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id
> system.cpu3.dcache.tags.tag_accesses 291822 # Number of tag accesses
> system.cpu3.dcache.tags.data_accesses 291822 # Number of data accesses
> system.cpu3.dcache.ReadReq_hits::cpu3.data 41456 # number of ReadReq hits
> system.cpu3.dcache.ReadReq_hits::total 41456 # number of ReadReq hits
> system.cpu3.dcache.WriteReq_hits::cpu3.data 30794 # number of WriteReq hits
> system.cpu3.dcache.WriteReq_hits::total 30794 # number of WriteReq hits
2169,2222c2168,2221
< system.cpu3.dcache.demand_hits::cpu3.data 71643 # number of demand (read+write) hits
< system.cpu3.dcache.demand_hits::total 71643 # number of demand (read+write) hits
< system.cpu3.dcache.overall_hits::cpu3.data 71643 # number of overall hits
< system.cpu3.dcache.overall_hits::total 71643 # number of overall hits
< system.cpu3.dcache.ReadReq_misses::cpu3.data 419 # number of ReadReq misses
< system.cpu3.dcache.ReadReq_misses::total 419 # number of ReadReq misses
< system.cpu3.dcache.WriteReq_misses::cpu3.data 141 # number of WriteReq misses
< system.cpu3.dcache.WriteReq_misses::total 141 # number of WriteReq misses
< system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses
< system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses
< system.cpu3.dcache.demand_misses::cpu3.data 560 # number of demand (read+write) misses
< system.cpu3.dcache.demand_misses::total 560 # number of demand (read+write) misses
< system.cpu3.dcache.overall_misses::cpu3.data 560 # number of overall misses
< system.cpu3.dcache.overall_misses::total 560 # number of overall misses
< system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 5396537 # number of ReadReq miss cycles
< system.cpu3.dcache.ReadReq_miss_latency::total 5396537 # number of ReadReq miss cycles
< system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2783262 # number of WriteReq miss cycles
< system.cpu3.dcache.WriteReq_miss_latency::total 2783262 # number of WriteReq miss cycles
< system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 481005 # number of SwapReq miss cycles
< system.cpu3.dcache.SwapReq_miss_latency::total 481005 # number of SwapReq miss cycles
< system.cpu3.dcache.demand_miss_latency::cpu3.data 8179799 # number of demand (read+write) miss cycles
< system.cpu3.dcache.demand_miss_latency::total 8179799 # number of demand (read+write) miss cycles
< system.cpu3.dcache.overall_miss_latency::cpu3.data 8179799 # number of overall miss cycles
< system.cpu3.dcache.overall_miss_latency::total 8179799 # number of overall miss cycles
< system.cpu3.dcache.ReadReq_accesses::cpu3.data 41628 # number of ReadReq accesses(hits+misses)
< system.cpu3.dcache.ReadReq_accesses::total 41628 # number of ReadReq accesses(hits+misses)
< system.cpu3.dcache.WriteReq_accesses::cpu3.data 30575 # number of WriteReq accesses(hits+misses)
< system.cpu3.dcache.WriteReq_accesses::total 30575 # number of WriteReq accesses(hits+misses)
< system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses)
< system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
< system.cpu3.dcache.demand_accesses::cpu3.data 72203 # number of demand (read+write) accesses
< system.cpu3.dcache.demand_accesses::total 72203 # number of demand (read+write) accesses
< system.cpu3.dcache.overall_accesses::cpu3.data 72203 # number of overall (read+write) accesses
< system.cpu3.dcache.overall_accesses::total 72203 # number of overall (read+write) accesses
< system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010065 # miss rate for ReadReq accesses
< system.cpu3.dcache.ReadReq_miss_rate::total 0.010065 # miss rate for ReadReq accesses
< system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004612 # miss rate for WriteReq accesses
< system.cpu3.dcache.WriteReq_miss_rate::total 0.004612 # miss rate for WriteReq accesses
< system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses
< system.cpu3.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses
< system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007756 # miss rate for demand accesses
< system.cpu3.dcache.demand_miss_rate::total 0.007756 # miss rate for demand accesses
< system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007756 # miss rate for overall accesses
< system.cpu3.dcache.overall_miss_rate::total 0.007756 # miss rate for overall accesses
< system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12879.563246 # average ReadReq miss latency
< system.cpu3.dcache.ReadReq_avg_miss_latency::total 12879.563246 # average ReadReq miss latency
< system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19739.446809 # average WriteReq miss latency
< system.cpu3.dcache.WriteReq_avg_miss_latency::total 19739.446809 # average WriteReq miss latency
< system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 8438.684211 # average SwapReq miss latency
< system.cpu3.dcache.SwapReq_avg_miss_latency::total 8438.684211 # average SwapReq miss latency
< system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14606.783929 # average overall miss latency
< system.cpu3.dcache.demand_avg_miss_latency::total 14606.783929 # average overall miss latency
< system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14606.783929 # average overall miss latency
< system.cpu3.dcache.overall_avg_miss_latency::total 14606.783929 # average overall miss latency
---
> system.cpu3.dcache.demand_hits::cpu3.data 72250 # number of demand (read+write) hits
> system.cpu3.dcache.demand_hits::total 72250 # number of demand (read+write) hits
> system.cpu3.dcache.overall_hits::cpu3.data 72250 # number of overall hits
> system.cpu3.dcache.overall_hits::total 72250 # number of overall hits
> system.cpu3.dcache.ReadReq_misses::cpu3.data 440 # number of ReadReq misses
> system.cpu3.dcache.ReadReq_misses::total 440 # number of ReadReq misses
> system.cpu3.dcache.WriteReq_misses::cpu3.data 137 # number of WriteReq misses
> system.cpu3.dcache.WriteReq_misses::total 137 # number of WriteReq misses
> system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses
> system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses
> system.cpu3.dcache.demand_misses::cpu3.data 577 # number of demand (read+write) misses
> system.cpu3.dcache.demand_misses::total 577 # number of demand (read+write) misses
> system.cpu3.dcache.overall_misses::cpu3.data 577 # number of overall misses
> system.cpu3.dcache.overall_misses::total 577 # number of overall misses
> system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 7521134 # number of ReadReq miss cycles
> system.cpu3.dcache.ReadReq_miss_latency::total 7521134 # number of ReadReq miss cycles
> system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3020012 # number of WriteReq miss cycles
> system.cpu3.dcache.WriteReq_miss_latency::total 3020012 # number of WriteReq miss cycles
> system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 589507 # number of SwapReq miss cycles
> system.cpu3.dcache.SwapReq_miss_latency::total 589507 # number of SwapReq miss cycles
> system.cpu3.dcache.demand_miss_latency::cpu3.data 10541146 # number of demand (read+write) miss cycles
> system.cpu3.dcache.demand_miss_latency::total 10541146 # number of demand (read+write) miss cycles
> system.cpu3.dcache.overall_miss_latency::cpu3.data 10541146 # number of overall miss cycles
> system.cpu3.dcache.overall_miss_latency::total 10541146 # number of overall miss cycles
> system.cpu3.dcache.ReadReq_accesses::cpu3.data 41896 # number of ReadReq accesses(hits+misses)
> system.cpu3.dcache.ReadReq_accesses::total 41896 # number of ReadReq accesses(hits+misses)
> system.cpu3.dcache.WriteReq_accesses::cpu3.data 30931 # number of WriteReq accesses(hits+misses)
> system.cpu3.dcache.WriteReq_accesses::total 30931 # number of WriteReq accesses(hits+misses)
> system.cpu3.dcache.SwapReq_accesses::cpu3.data 68 # number of SwapReq accesses(hits+misses)
> system.cpu3.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses)
> system.cpu3.dcache.demand_accesses::cpu3.data 72827 # number of demand (read+write) accesses
> system.cpu3.dcache.demand_accesses::total 72827 # number of demand (read+write) accesses
> system.cpu3.dcache.overall_accesses::cpu3.data 72827 # number of overall (read+write) accesses
> system.cpu3.dcache.overall_accesses::total 72827 # number of overall (read+write) accesses
> system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010502 # miss rate for ReadReq accesses
> system.cpu3.dcache.ReadReq_miss_rate::total 0.010502 # miss rate for ReadReq accesses
> system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004429 # miss rate for WriteReq accesses
> system.cpu3.dcache.WriteReq_miss_rate::total 0.004429 # miss rate for WriteReq accesses
> system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.794118 # miss rate for SwapReq accesses
> system.cpu3.dcache.SwapReq_miss_rate::total 0.794118 # miss rate for SwapReq accesses
> system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007923 # miss rate for demand accesses
> system.cpu3.dcache.demand_miss_rate::total 0.007923 # miss rate for demand accesses
> system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007923 # miss rate for overall accesses
> system.cpu3.dcache.overall_miss_rate::total 0.007923 # miss rate for overall accesses
> system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17093.486364 # average ReadReq miss latency
> system.cpu3.dcache.ReadReq_avg_miss_latency::total 17093.486364 # average ReadReq miss latency
> system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 22043.883212 # average WriteReq miss latency
> system.cpu3.dcache.WriteReq_avg_miss_latency::total 22043.883212 # average WriteReq miss latency
> system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 10916.796296 # average SwapReq miss latency
> system.cpu3.dcache.SwapReq_avg_miss_latency::total 10916.796296 # average SwapReq miss latency
> system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18268.883882 # average overall miss latency
> system.cpu3.dcache.demand_avg_miss_latency::total 18268.883882 # average overall miss latency
> system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18268.883882 # average overall miss latency
> system.cpu3.dcache.overall_avg_miss_latency::total 18268.883882 # average overall miss latency
2231,2232c2230,2231
< system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 259 # number of ReadReq MSHR hits
< system.cpu3.dcache.ReadReq_mshr_hits::total 259 # number of ReadReq MSHR hits
---
> system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 288 # number of ReadReq MSHR hits
> system.cpu3.dcache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits
2235,2278c2234,2277
< system.cpu3.dcache.demand_mshr_hits::cpu3.data 293 # number of demand (read+write) MSHR hits
< system.cpu3.dcache.demand_mshr_hits::total 293 # number of demand (read+write) MSHR hits
< system.cpu3.dcache.overall_mshr_hits::cpu3.data 293 # number of overall MSHR hits
< system.cpu3.dcache.overall_mshr_hits::total 293 # number of overall MSHR hits
< system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 160 # number of ReadReq MSHR misses
< system.cpu3.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses
< system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses
< system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses
< system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses
< system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses
< system.cpu3.dcache.demand_mshr_misses::cpu3.data 267 # number of demand (read+write) MSHR misses
< system.cpu3.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses
< system.cpu3.dcache.overall_mshr_misses::cpu3.data 267 # number of overall MSHR misses
< system.cpu3.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses
< system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1078521 # number of ReadReq MSHR miss cycles
< system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1078521 # number of ReadReq MSHR miss cycles
< system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1312238 # number of WriteReq MSHR miss cycles
< system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1312238 # number of WriteReq MSHR miss cycles
< system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 366995 # number of SwapReq MSHR miss cycles
< system.cpu3.dcache.SwapReq_mshr_miss_latency::total 366995 # number of SwapReq MSHR miss cycles
< system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2390759 # number of demand (read+write) MSHR miss cycles
< system.cpu3.dcache.demand_mshr_miss_latency::total 2390759 # number of demand (read+write) MSHR miss cycles
< system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2390759 # number of overall MSHR miss cycles
< system.cpu3.dcache.overall_mshr_miss_latency::total 2390759 # number of overall MSHR miss cycles
< system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003844 # mshr miss rate for ReadReq accesses
< system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003844 # mshr miss rate for ReadReq accesses
< system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003500 # mshr miss rate for WriteReq accesses
< system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003500 # mshr miss rate for WriteReq accesses
< system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses
< system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses
< system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003698 # mshr miss rate for demand accesses
< system.cpu3.dcache.demand_mshr_miss_rate::total 0.003698 # mshr miss rate for demand accesses
< system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003698 # mshr miss rate for overall accesses
< system.cpu3.dcache.overall_mshr_miss_rate::total 0.003698 # mshr miss rate for overall accesses
< system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6740.756250 # average ReadReq mshr miss latency
< system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6740.756250 # average ReadReq mshr miss latency
< system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12263.906542 # average WriteReq mshr miss latency
< system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12263.906542 # average WriteReq mshr miss latency
< system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 6438.508772 # average SwapReq mshr miss latency
< system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 6438.508772 # average SwapReq mshr miss latency
< system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 8954.153558 # average overall mshr miss latency
< system.cpu3.dcache.demand_avg_mshr_miss_latency::total 8954.153558 # average overall mshr miss latency
< system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 8954.153558 # average overall mshr miss latency
< system.cpu3.dcache.overall_avg_mshr_miss_latency::total 8954.153558 # average overall mshr miss latency
---
> system.cpu3.dcache.demand_mshr_hits::cpu3.data 322 # number of demand (read+write) MSHR hits
> system.cpu3.dcache.demand_mshr_hits::total 322 # number of demand (read+write) MSHR hits
> system.cpu3.dcache.overall_mshr_hits::cpu3.data 322 # number of overall MSHR hits
> system.cpu3.dcache.overall_mshr_hits::total 322 # number of overall MSHR hits
> system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 152 # number of ReadReq MSHR misses
> system.cpu3.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses
> system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 103 # number of WriteReq MSHR misses
> system.cpu3.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses
> system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses
> system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses
> system.cpu3.dcache.demand_mshr_misses::cpu3.data 255 # number of demand (read+write) MSHR misses
> system.cpu3.dcache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses
> system.cpu3.dcache.overall_mshr_misses::cpu3.data 255 # number of overall MSHR misses
> system.cpu3.dcache.overall_mshr_misses::total 255 # number of overall MSHR misses
> system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1429011 # number of ReadReq MSHR miss cycles
> system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1429011 # number of ReadReq MSHR miss cycles
> system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1527238 # number of WriteReq MSHR miss cycles
> system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1527238 # number of WriteReq MSHR miss cycles
> system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 508493 # number of SwapReq MSHR miss cycles
> system.cpu3.dcache.SwapReq_mshr_miss_latency::total 508493 # number of SwapReq MSHR miss cycles
> system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2956249 # number of demand (read+write) MSHR miss cycles
> system.cpu3.dcache.demand_mshr_miss_latency::total 2956249 # number of demand (read+write) MSHR miss cycles
> system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2956249 # number of overall MSHR miss cycles
> system.cpu3.dcache.overall_mshr_miss_latency::total 2956249 # number of overall MSHR miss cycles
> system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003628 # mshr miss rate for ReadReq accesses
> system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003628 # mshr miss rate for ReadReq accesses
> system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003330 # mshr miss rate for WriteReq accesses
> system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003330 # mshr miss rate for WriteReq accesses
> system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.794118 # mshr miss rate for SwapReq accesses
> system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.794118 # mshr miss rate for SwapReq accesses
> system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003501 # mshr miss rate for demand accesses
> system.cpu3.dcache.demand_mshr_miss_rate::total 0.003501 # mshr miss rate for demand accesses
> system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003501 # mshr miss rate for overall accesses
> system.cpu3.dcache.overall_mshr_miss_rate::total 0.003501 # mshr miss rate for overall accesses
> system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9401.388158 # average ReadReq mshr miss latency
> system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9401.388158 # average ReadReq mshr miss latency
> system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14827.553398 # average WriteReq mshr miss latency
> system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14827.553398 # average WriteReq mshr miss latency
> system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 9416.537037 # average SwapReq mshr miss latency
> system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 9416.537037 # average SwapReq mshr miss latency
> system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 11593.133333 # average overall mshr miss latency
> system.cpu3.dcache.demand_avg_mshr_miss_latency::total 11593.133333 # average overall mshr miss latency
> system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 11593.133333 # average overall mshr miss latency
> system.cpu3.dcache.overall_avg_mshr_miss_latency::total 11593.133333 # average overall mshr miss latency
2280,2284c2279,2283
< system.cpu3.icache.tags.replacements 386 # number of replacements
< system.cpu3.icache.tags.tagsinuse 78.630086 # Cycle average of tags in use
< system.cpu3.icache.tags.total_refs 23274 # Total number of references to valid blocks.
< system.cpu3.icache.tags.sampled_refs 495 # Sample count of references to valid blocks.
< system.cpu3.icache.tags.avg_refs 47.018182 # Average number of references to valid blocks.
---
> system.cpu3.icache.tags.replacements 387 # number of replacements
> system.cpu3.icache.tags.tagsinuse 75.442206 # Cycle average of tags in use
> system.cpu3.icache.tags.total_refs 23109 # Total number of references to valid blocks.
> system.cpu3.icache.tags.sampled_refs 498 # Sample count of references to valid blocks.
> system.cpu3.icache.tags.avg_refs 46.403614 # Average number of references to valid blocks.
2286,2289c2285,2288
< system.cpu3.icache.tags.occ_blocks::cpu3.inst 78.630086 # Average occupied blocks per requestor
< system.cpu3.icache.tags.occ_percent::cpu3.inst 0.153574 # Average percentage of cache occupancy
< system.cpu3.icache.tags.occ_percent::total 0.153574 # Average percentage of cache occupancy
< system.cpu3.icache.tags.occ_task_id_blocks::1024 109 # Occupied blocks per task id
---
> system.cpu3.icache.tags.occ_blocks::cpu3.inst 75.442206 # Average occupied blocks per requestor
> system.cpu3.icache.tags.occ_percent::cpu3.inst 0.147348 # Average percentage of cache occupancy
> system.cpu3.icache.tags.occ_percent::total 0.147348 # Average percentage of cache occupancy
> system.cpu3.icache.tags.occ_task_id_blocks::1024 111 # Occupied blocks per task id
2291,2330c2290,2329
< system.cpu3.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id
< system.cpu3.icache.tags.occ_task_id_percent::1024 0.212891 # Percentage of cache occupancy per task id
< system.cpu3.icache.tags.tag_accesses 24325 # Number of tag accesses
< system.cpu3.icache.tags.data_accesses 24325 # Number of data accesses
< system.cpu3.icache.ReadReq_hits::cpu3.inst 23274 # number of ReadReq hits
< system.cpu3.icache.ReadReq_hits::total 23274 # number of ReadReq hits
< system.cpu3.icache.demand_hits::cpu3.inst 23274 # number of demand (read+write) hits
< system.cpu3.icache.demand_hits::total 23274 # number of demand (read+write) hits
< system.cpu3.icache.overall_hits::cpu3.inst 23274 # number of overall hits
< system.cpu3.icache.overall_hits::total 23274 # number of overall hits
< system.cpu3.icache.ReadReq_misses::cpu3.inst 556 # number of ReadReq misses
< system.cpu3.icache.ReadReq_misses::total 556 # number of ReadReq misses
< system.cpu3.icache.demand_misses::cpu3.inst 556 # number of demand (read+write) misses
< system.cpu3.icache.demand_misses::total 556 # number of demand (read+write) misses
< system.cpu3.icache.overall_misses::cpu3.inst 556 # number of overall misses
< system.cpu3.icache.overall_misses::total 556 # number of overall misses
< system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7666496 # number of ReadReq miss cycles
< system.cpu3.icache.ReadReq_miss_latency::total 7666496 # number of ReadReq miss cycles
< system.cpu3.icache.demand_miss_latency::cpu3.inst 7666496 # number of demand (read+write) miss cycles
< system.cpu3.icache.demand_miss_latency::total 7666496 # number of demand (read+write) miss cycles
< system.cpu3.icache.overall_miss_latency::cpu3.inst 7666496 # number of overall miss cycles
< system.cpu3.icache.overall_miss_latency::total 7666496 # number of overall miss cycles
< system.cpu3.icache.ReadReq_accesses::cpu3.inst 23830 # number of ReadReq accesses(hits+misses)
< system.cpu3.icache.ReadReq_accesses::total 23830 # number of ReadReq accesses(hits+misses)
< system.cpu3.icache.demand_accesses::cpu3.inst 23830 # number of demand (read+write) accesses
< system.cpu3.icache.demand_accesses::total 23830 # number of demand (read+write) accesses
< system.cpu3.icache.overall_accesses::cpu3.inst 23830 # number of overall (read+write) accesses
< system.cpu3.icache.overall_accesses::total 23830 # number of overall (read+write) accesses
< system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023332 # miss rate for ReadReq accesses
< system.cpu3.icache.ReadReq_miss_rate::total 0.023332 # miss rate for ReadReq accesses
< system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023332 # miss rate for demand accesses
< system.cpu3.icache.demand_miss_rate::total 0.023332 # miss rate for demand accesses
< system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023332 # miss rate for overall accesses
< system.cpu3.icache.overall_miss_rate::total 0.023332 # miss rate for overall accesses
< system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13788.661871 # average ReadReq miss latency
< system.cpu3.icache.ReadReq_avg_miss_latency::total 13788.661871 # average ReadReq miss latency
< system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13788.661871 # average overall miss latency
< system.cpu3.icache.demand_avg_miss_latency::total 13788.661871 # average overall miss latency
< system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13788.661871 # average overall miss latency
< system.cpu3.icache.overall_avg_miss_latency::total 13788.661871 # average overall miss latency
---
> system.cpu3.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id
> system.cpu3.icache.tags.occ_task_id_percent::1024 0.216797 # Percentage of cache occupancy per task id
> system.cpu3.icache.tags.tag_accesses 24167 # Number of tag accesses
> system.cpu3.icache.tags.data_accesses 24167 # Number of data accesses
> system.cpu3.icache.ReadReq_hits::cpu3.inst 23109 # number of ReadReq hits
> system.cpu3.icache.ReadReq_hits::total 23109 # number of ReadReq hits
> system.cpu3.icache.demand_hits::cpu3.inst 23109 # number of demand (read+write) hits
> system.cpu3.icache.demand_hits::total 23109 # number of demand (read+write) hits
> system.cpu3.icache.overall_hits::cpu3.inst 23109 # number of overall hits
> system.cpu3.icache.overall_hits::total 23109 # number of overall hits
> system.cpu3.icache.ReadReq_misses::cpu3.inst 560 # number of ReadReq misses
> system.cpu3.icache.ReadReq_misses::total 560 # number of ReadReq misses
> system.cpu3.icache.demand_misses::cpu3.inst 560 # number of demand (read+write) misses
> system.cpu3.icache.demand_misses::total 560 # number of demand (read+write) misses
> system.cpu3.icache.overall_misses::cpu3.inst 560 # number of overall misses
> system.cpu3.icache.overall_misses::total 560 # number of overall misses
> system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7349496 # number of ReadReq miss cycles
> system.cpu3.icache.ReadReq_miss_latency::total 7349496 # number of ReadReq miss cycles
> system.cpu3.icache.demand_miss_latency::cpu3.inst 7349496 # number of demand (read+write) miss cycles
> system.cpu3.icache.demand_miss_latency::total 7349496 # number of demand (read+write) miss cycles
> system.cpu3.icache.overall_miss_latency::cpu3.inst 7349496 # number of overall miss cycles
> system.cpu3.icache.overall_miss_latency::total 7349496 # number of overall miss cycles
> system.cpu3.icache.ReadReq_accesses::cpu3.inst 23669 # number of ReadReq accesses(hits+misses)
> system.cpu3.icache.ReadReq_accesses::total 23669 # number of ReadReq accesses(hits+misses)
> system.cpu3.icache.demand_accesses::cpu3.inst 23669 # number of demand (read+write) accesses
> system.cpu3.icache.demand_accesses::total 23669 # number of demand (read+write) accesses
> system.cpu3.icache.overall_accesses::cpu3.inst 23669 # number of overall (read+write) accesses
> system.cpu3.icache.overall_accesses::total 23669 # number of overall (read+write) accesses
> system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023660 # miss rate for ReadReq accesses
> system.cpu3.icache.ReadReq_miss_rate::total 0.023660 # miss rate for ReadReq accesses
> system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023660 # miss rate for demand accesses
> system.cpu3.icache.demand_miss_rate::total 0.023660 # miss rate for demand accesses
> system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023660 # miss rate for overall accesses
> system.cpu3.icache.overall_miss_rate::total 0.023660 # miss rate for overall accesses
> system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13124.100000 # average ReadReq miss latency
> system.cpu3.icache.ReadReq_avg_miss_latency::total 13124.100000 # average ReadReq miss latency
> system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13124.100000 # average overall miss latency
> system.cpu3.icache.demand_avg_miss_latency::total 13124.100000 # average overall miss latency
> system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13124.100000 # average overall miss latency
> system.cpu3.icache.overall_avg_miss_latency::total 13124.100000 # average overall miss latency
2339,2368c2338,2367
< system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 61 # number of ReadReq MSHR hits
< system.cpu3.icache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits
< system.cpu3.icache.demand_mshr_hits::cpu3.inst 61 # number of demand (read+write) MSHR hits
< system.cpu3.icache.demand_mshr_hits::total 61 # number of demand (read+write) MSHR hits
< system.cpu3.icache.overall_mshr_hits::cpu3.inst 61 # number of overall MSHR hits
< system.cpu3.icache.overall_mshr_hits::total 61 # number of overall MSHR hits
< system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 495 # number of ReadReq MSHR misses
< system.cpu3.icache.ReadReq_mshr_misses::total 495 # number of ReadReq MSHR misses
< system.cpu3.icache.demand_mshr_misses::cpu3.inst 495 # number of demand (read+write) MSHR misses
< system.cpu3.icache.demand_mshr_misses::total 495 # number of demand (read+write) MSHR misses
< system.cpu3.icache.overall_mshr_misses::cpu3.inst 495 # number of overall MSHR misses
< system.cpu3.icache.overall_mshr_misses::total 495 # number of overall MSHR misses
< system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5988753 # number of ReadReq MSHR miss cycles
< system.cpu3.icache.ReadReq_mshr_miss_latency::total 5988753 # number of ReadReq MSHR miss cycles
< system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5988753 # number of demand (read+write) MSHR miss cycles
< system.cpu3.icache.demand_mshr_miss_latency::total 5988753 # number of demand (read+write) MSHR miss cycles
< system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5988753 # number of overall MSHR miss cycles
< system.cpu3.icache.overall_mshr_miss_latency::total 5988753 # number of overall MSHR miss cycles
< system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020772 # mshr miss rate for ReadReq accesses
< system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020772 # mshr miss rate for ReadReq accesses
< system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020772 # mshr miss rate for demand accesses
< system.cpu3.icache.demand_mshr_miss_rate::total 0.020772 # mshr miss rate for demand accesses
< system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020772 # mshr miss rate for overall accesses
< system.cpu3.icache.overall_mshr_miss_rate::total 0.020772 # mshr miss rate for overall accesses
< system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12098.490909 # average ReadReq mshr miss latency
< system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12098.490909 # average ReadReq mshr miss latency
< system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12098.490909 # average overall mshr miss latency
< system.cpu3.icache.demand_avg_mshr_miss_latency::total 12098.490909 # average overall mshr miss latency
< system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12098.490909 # average overall mshr miss latency
< system.cpu3.icache.overall_avg_mshr_miss_latency::total 12098.490909 # average overall mshr miss latency
---
> system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 62 # number of ReadReq MSHR hits
> system.cpu3.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits
> system.cpu3.icache.demand_mshr_hits::cpu3.inst 62 # number of demand (read+write) MSHR hits
> system.cpu3.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits
> system.cpu3.icache.overall_mshr_hits::cpu3.inst 62 # number of overall MSHR hits
> system.cpu3.icache.overall_mshr_hits::total 62 # number of overall MSHR hits
> system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 498 # number of ReadReq MSHR misses
> system.cpu3.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses
> system.cpu3.icache.demand_mshr_misses::cpu3.inst 498 # number of demand (read+write) MSHR misses
> system.cpu3.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses
> system.cpu3.icache.overall_mshr_misses::cpu3.inst 498 # number of overall MSHR misses
> system.cpu3.icache.overall_mshr_misses::total 498 # number of overall MSHR misses
> system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6152504 # number of ReadReq MSHR miss cycles
> system.cpu3.icache.ReadReq_mshr_miss_latency::total 6152504 # number of ReadReq MSHR miss cycles
> system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6152504 # number of demand (read+write) MSHR miss cycles
> system.cpu3.icache.demand_mshr_miss_latency::total 6152504 # number of demand (read+write) MSHR miss cycles
> system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6152504 # number of overall MSHR miss cycles
> system.cpu3.icache.overall_mshr_miss_latency::total 6152504 # number of overall MSHR miss cycles
> system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.021040 # mshr miss rate for ReadReq accesses
> system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.021040 # mshr miss rate for ReadReq accesses
> system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.021040 # mshr miss rate for demand accesses
> system.cpu3.icache.demand_mshr_miss_rate::total 0.021040 # mshr miss rate for demand accesses
> system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.021040 # mshr miss rate for overall accesses
> system.cpu3.icache.overall_mshr_miss_rate::total 0.021040 # mshr miss rate for overall accesses
> system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12354.425703 # average ReadReq mshr miss latency
> system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12354.425703 # average ReadReq mshr miss latency
> system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12354.425703 # average overall mshr miss latency
> system.cpu3.icache.demand_avg_mshr_miss_latency::total 12354.425703 # average overall mshr miss latency
> system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12354.425703 # average overall mshr miss latency
> system.cpu3.icache.overall_avg_mshr_miss_latency::total 12354.425703 # average overall mshr miss latency
2371,2374c2370,2373
< system.l2c.tags.tagsinuse 421.782597 # Cycle average of tags in use
< system.l2c.tags.total_refs 1661 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 531 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 3.128060 # Average number of references to valid blocks.
---
> system.l2c.tags.tagsinuse 421.791819 # Cycle average of tags in use
> system.l2c.tags.total_refs 1669 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 536 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 3.113806 # Average number of references to valid blocks.
2376,2384c2375,2383
< system.l2c.tags.occ_blocks::writebacks 0.793367 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 288.136506 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 58.239710 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 7.908939 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 0.685353 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu2.inst 57.810668 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu2.data 5.358893 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu3.inst 2.126194 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu3.data 0.722968 # Average occupied blocks per requestor
---
> system.l2c.tags.occ_blocks::writebacks 0.783957 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 289.037601 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 57.982294 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 60.100309 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 5.287110 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu2.inst 5.207527 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu2.data 0.713016 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu3.inst 2.004391 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu3.data 0.675614 # Average occupied blocks per requestor
2386,2393c2385,2392
< system.l2c.tags.occ_percent::cpu0.inst 0.004397 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.000889 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.000121 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.000010 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu2.inst 0.000882 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu2.data 0.000082 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu3.inst 0.000032 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy
---
> system.l2c.tags.occ_percent::cpu0.inst 0.004410 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.000885 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.000917 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.000081 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu2.inst 0.000079 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu3.inst 0.000031 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu3.data 0.000010 # Average percentage of cache occupancy
2395,2402c2394,2401
< system.l2c.tags.occ_task_id_blocks::1024 531 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::1 367 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 114 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1024 0.008102 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 20025 # Number of tag accesses
< system.l2c.tags.data_accesses 20025 # Number of data accesses
< system.l2c.ReadReq_hits::cpu0.inst 248 # number of ReadReq hits
---
> system.l2c.tags.occ_task_id_blocks::1024 536 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::1 348 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 137 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1024 0.008179 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 20118 # Number of tag accesses
> system.l2c.tags.data_accesses 20118 # Number of data accesses
> system.l2c.ReadReq_hits::cpu0.inst 251 # number of ReadReq hits
2404,2408c2403,2407
< system.l2c.ReadReq_hits::cpu1.inst 483 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu2.inst 409 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu3.inst 489 # number of ReadReq hits
---
> system.l2c.ReadReq_hits::cpu1.inst 414 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu2.inst 481 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu3.inst 491 # number of ReadReq hits
2410c2409
< system.l2c.ReadReq_hits::total 1661 # number of ReadReq hits
---
> system.l2c.ReadReq_hits::total 1669 # number of ReadReq hits
2415c2414
< system.l2c.demand_hits::cpu0.inst 248 # number of demand (read+write) hits
---
> system.l2c.demand_hits::cpu0.inst 251 # number of demand (read+write) hits
2417,2421c2416,2420
< system.l2c.demand_hits::cpu1.inst 483 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu2.inst 409 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu3.inst 489 # number of demand (read+write) hits
---
> system.l2c.demand_hits::cpu1.inst 414 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu2.inst 481 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu3.inst 491 # number of demand (read+write) hits
2423,2424c2422,2423
< system.l2c.demand_hits::total 1661 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.inst 248 # number of overall hits
---
> system.l2c.demand_hits::total 1669 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.inst 251 # number of overall hits
2426,2430c2425,2429
< system.l2c.overall_hits::cpu1.inst 483 # number of overall hits
< system.l2c.overall_hits::cpu1.data 11 # number of overall hits
< system.l2c.overall_hits::cpu2.inst 409 # number of overall hits
< system.l2c.overall_hits::cpu2.data 5 # number of overall hits
< system.l2c.overall_hits::cpu3.inst 489 # number of overall hits
---
> system.l2c.overall_hits::cpu1.inst 414 # number of overall hits
> system.l2c.overall_hits::cpu1.data 5 # number of overall hits
> system.l2c.overall_hits::cpu2.inst 481 # number of overall hits
> system.l2c.overall_hits::cpu2.data 11 # number of overall hits
> system.l2c.overall_hits::cpu3.inst 491 # number of overall hits
2432,2439c2431,2438
< system.l2c.overall_hits::total 1661 # number of overall hits
< system.l2c.ReadReq_misses::cpu0.inst 361 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.inst 15 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu2.inst 81 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu3.inst 6 # number of ReadReq misses
---
> system.l2c.overall_hits::total 1669 # number of overall hits
> system.l2c.ReadReq_misses::cpu0.inst 364 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.data 75 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.inst 83 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu2.inst 13 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu3.inst 7 # number of ReadReq misses
2441,2442c2440,2441
< system.l2c.ReadReq_misses::total 546 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu0.data 23 # number of UpgradeReq misses
---
> system.l2c.ReadReq_misses::total 551 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses
2444,2446c2443,2445
< system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu3.data 17 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 78 # number of UpgradeReq misses
---
> system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses
2448,2449c2447,2448
< system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses
---
> system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
2452,2458c2451,2457
< system.l2c.demand_misses::cpu0.inst 361 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 15 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu2.inst 81 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu3.inst 6 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu0.inst 364 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 169 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 83 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu2.inst 13 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu3.inst 7 # number of demand (read+write) misses
2460,2467c2459,2466
< system.l2c.demand_misses::total 677 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.inst 361 # number of overall misses
< system.l2c.overall_misses::cpu0.data 168 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 15 # number of overall misses
< system.l2c.overall_misses::cpu1.data 13 # number of overall misses
< system.l2c.overall_misses::cpu2.inst 81 # number of overall misses
< system.l2c.overall_misses::cpu2.data 20 # number of overall misses
< system.l2c.overall_misses::cpu3.inst 6 # number of overall misses
---
> system.l2c.demand_misses::total 682 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.inst 364 # number of overall misses
> system.l2c.overall_misses::cpu0.data 169 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 83 # number of overall misses
> system.l2c.overall_misses::cpu1.data 20 # number of overall misses
> system.l2c.overall_misses::cpu2.inst 13 # number of overall misses
> system.l2c.overall_misses::cpu2.data 13 # number of overall misses
> system.l2c.overall_misses::cpu3.inst 7 # number of overall misses
2469,2504c2468,2503
< system.l2c.overall_misses::total 677 # number of overall misses
< system.l2c.ReadReq_miss_latency::cpu0.inst 24898500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.data 5922000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.inst 1027000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.data 75000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu2.inst 5770000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu2.data 523250 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu3.inst 593000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu3.data 75000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 38883750 # number of ReadReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 6920500 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 837000 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu2.data 1047250 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu3.data 851750 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 9656500 # number of ReadExReq miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 24898500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 12842500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 1027000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 912000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu2.inst 5770000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu2.data 1570500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu3.inst 593000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu3.data 926750 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 48540250 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 24898500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 12842500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 1027000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 912000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu2.inst 5770000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu2.data 1570500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu3.inst 593000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu3.data 926750 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 48540250 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu0.inst 609 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.inst 498 # number of ReadReq accesses(hits+misses)
---
> system.l2c.overall_misses::total 682 # number of overall misses
> system.l2c.ReadReq_miss_latency::cpu0.inst 27791500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.data 6004250 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.inst 6396000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.data 553250 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu2.inst 1121000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu2.data 96750 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu3.inst 495500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu3.data 82500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::total 42540750 # number of ReadReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 8131000 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 1125500 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu2.data 956000 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu3.data 926750 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 11139250 # number of ReadExReq miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 27791500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 14135250 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 6396000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 1678750 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu2.inst 1121000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu2.data 1052750 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu3.inst 495500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu3.data 1009250 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 53680000 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 27791500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 14135250 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 6396000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 1678750 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu2.inst 1121000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu2.data 1052750 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu3.inst 495500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu3.data 1009250 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 53680000 # number of overall miss cycles
> system.l2c.ReadReq_accesses::cpu0.inst 615 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.data 80 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.inst 497 # number of ReadReq accesses(hits+misses)
2506c2505
< system.l2c.ReadReq_accesses::cpu2.inst 490 # number of ReadReq accesses(hits+misses)
---
> system.l2c.ReadReq_accesses::cpu2.inst 494 # number of ReadReq accesses(hits+misses)
2508c2507
< system.l2c.ReadReq_accesses::cpu3.inst 495 # number of ReadReq accesses(hits+misses)
---
> system.l2c.ReadReq_accesses::cpu3.inst 498 # number of ReadReq accesses(hits+misses)
2510c2509
< system.l2c.ReadReq_accesses::total 2207 # number of ReadReq accesses(hits+misses)
---
> system.l2c.ReadReq_accesses::total 2220 # number of ReadReq accesses(hits+misses)
2513c2512
< system.l2c.UpgradeReq_accesses::cpu0.data 26 # number of UpgradeReq accesses(hits+misses)
---
> system.l2c.UpgradeReq_accesses::cpu0.data 25 # number of UpgradeReq accesses(hits+misses)
2515,2517c2514,2516
< system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu3.data 17 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 81 # number of UpgradeReq accesses(hits+misses)
---
> system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses)
2519,2520c2518,2519
< system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu2.data 13 # number of ReadExReq accesses(hits+misses)
---
> system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
2523,2529c2522,2528
< system.l2c.demand_accesses::cpu0.inst 609 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 498 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 24 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu2.inst 490 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu3.inst 495 # number of demand (read+write) accesses
---
> system.l2c.demand_accesses::cpu0.inst 615 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 174 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 497 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu2.inst 494 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu3.inst 498 # number of demand (read+write) accesses
2531,2538c2530,2537
< system.l2c.demand_accesses::total 2338 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 609 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 498 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 24 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu2.inst 490 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu3.inst 495 # number of overall (read+write) accesses
---
> system.l2c.demand_accesses::total 2351 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 615 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 174 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 497 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu2.inst 494 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu3.inst 498 # number of overall (read+write) accesses
2540,2547c2539,2546
< system.l2c.overall_accesses::total 2338 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu0.inst 0.592775 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.inst 0.030120 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.data 0.083333 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu2.inst 0.165306 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu2.data 0.583333 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu3.inst 0.012121 # miss rate for ReadReq accesses
---
> system.l2c.overall_accesses::total 2351 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu0.inst 0.591870 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.inst 0.167002 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu2.inst 0.026316 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu3.inst 0.014056 # miss rate for ReadReq accesses
2549,2550c2548,2549
< system.l2c.ReadReq_miss_rate::total 0.247395 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.884615 # miss rate for UpgradeReq accesses
---
> system.l2c.ReadReq_miss_rate::total 0.248198 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses
2554c2553
< system.l2c.UpgradeReq_miss_rate::total 0.962963 # miss rate for UpgradeReq accesses
---
> system.l2c.UpgradeReq_miss_rate::total 0.962025 # miss rate for UpgradeReq accesses
2560,2566c2559,2565
< system.l2c.demand_miss_rate::cpu0.inst 0.592775 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.030120 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.541667 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu2.inst 0.165306 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu2.data 0.800000 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu3.inst 0.012121 # miss rate for demand accesses
---
> system.l2c.demand_miss_rate::cpu0.inst 0.591870 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.167002 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu2.inst 0.026316 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu3.inst 0.014056 # miss rate for demand accesses
2568,2575c2567,2574
< system.l2c.demand_miss_rate::total 0.289564 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.592775 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.030120 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.541667 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu2.inst 0.165306 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu2.data 0.800000 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu3.inst 0.012121 # miss rate for overall accesses
---
> system.l2c.demand_miss_rate::total 0.290089 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.591870 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.971264 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.167002 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu2.inst 0.026316 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu3.inst 0.014056 # miss rate for overall accesses
2577,2609c2576,2608
< system.l2c.overall_miss_rate::total 0.289564 # miss rate for overall accesses
< system.l2c.ReadReq_avg_miss_latency::cpu0.inst 68970.914127 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.data 80027.027027 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.inst 68466.666667 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.data 75000 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu2.inst 71234.567901 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu2.data 74750 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu3.inst 98833.333333 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu3.data 75000 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::total 71215.659341 # average ReadReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 73622.340426 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 69750 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu2.data 80557.692308 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu3.data 70979.166667 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 73713.740458 # average ReadExReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 68970.914127 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 76443.452381 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 68466.666667 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 70153.846154 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu2.inst 71234.567901 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu2.data 78525 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu3.inst 98833.333333 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu3.data 71288.461538 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 71699.039882 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 68970.914127 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 76443.452381 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 68466.666667 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 70153.846154 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu2.inst 71234.567901 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu2.data 78525 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu3.inst 98833.333333 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu3.data 71288.461538 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 71699.039882 # average overall miss latency
---
> system.l2c.overall_miss_rate::total 0.290089 # miss rate for overall accesses
> system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76350.274725 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.data 80056.666667 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77060.240964 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.data 79035.714286 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu2.inst 86230.769231 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu2.data 96750 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu3.inst 70785.714286 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu3.data 82500 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::total 77206.442831 # average ReadReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 86500 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 86576.923077 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79666.666667 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu3.data 77229.166667 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 85032.442748 # average ReadExReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 76350.274725 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 83640.532544 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 77060.240964 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 83937.500000 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu2.inst 86230.769231 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu2.data 80980.769231 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu3.inst 70785.714286 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu3.data 77634.615385 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 78709.677419 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 76350.274725 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 83640.532544 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 77060.240964 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 83937.500000 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu2.inst 86230.769231 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu2.data 80980.769231 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu3.inst 70785.714286 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu3.data 77634.615385 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 78709.677419 # average overall miss latency
2620,2621c2619,2620
< system.l2c.ReadReq_mshr_hits::cpu2.inst 5 # number of ReadReq MSHR hits
< system.l2c.ReadReq_mshr_hits::cpu3.inst 3 # number of ReadReq MSHR hits
---
> system.l2c.ReadReq_mshr_hits::cpu2.inst 6 # number of ReadReq MSHR hits
> system.l2c.ReadReq_mshr_hits::cpu3.inst 2 # number of ReadReq MSHR hits
2625,2626c2624,2625
< system.l2c.demand_mshr_hits::cpu2.inst 5 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu3.inst 3 # number of demand (read+write) MSHR hits
---
> system.l2c.demand_mshr_hits::cpu2.inst 6 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu3.inst 2 # number of demand (read+write) MSHR hits
2630,2631c2629,2630
< system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu3.inst 3 # number of overall MSHR hits
---
> system.l2c.overall_mshr_hits::cpu2.inst 6 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu3.inst 2 # number of overall MSHR hits
2633,2639c2632,2638
< system.l2c.ReadReq_mshr_misses::cpu0.inst 360 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.inst 12 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu2.inst 76 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu2.data 7 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu3.inst 3 # number of ReadReq MSHR misses
---
> system.l2c.ReadReq_mshr_misses::cpu0.inst 363 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.data 75 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.inst 80 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu2.inst 7 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu3.inst 5 # number of ReadReq MSHR misses
2641,2642c2640,2641
< system.l2c.ReadReq_mshr_misses::total 534 # number of ReadReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 23 # number of UpgradeReq MSHR misses
---
> system.l2c.ReadReq_mshr_misses::total 539 # number of ReadReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 22 # number of UpgradeReq MSHR misses
2644,2646c2643,2645
< system.l2c.UpgradeReq_mshr_misses::cpu2.data 20 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu3.data 17 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 78 # number of UpgradeReq MSHR misses
---
> system.l2c.UpgradeReq_mshr_misses::cpu2.data 17 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu3.data 19 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 76 # number of UpgradeReq MSHR misses
2648,2649c2647,2648
< system.l2c.ReadExReq_mshr_misses::cpu1.data 12 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu2.data 13 # number of ReadExReq MSHR misses
---
> system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses
2652,2658c2651,2657
< system.l2c.demand_mshr_misses::cpu0.inst 360 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 12 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 13 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu2.inst 76 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu2.data 20 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu3.inst 3 # number of demand (read+write) MSHR misses
---
> system.l2c.demand_mshr_misses::cpu0.inst 363 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 169 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 80 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 20 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu2.inst 7 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu2.data 13 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu3.inst 5 # number of demand (read+write) MSHR misses
2660,2667c2659,2666
< system.l2c.demand_mshr_misses::total 665 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.inst 360 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 12 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 13 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu2.inst 76 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu2.data 20 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu3.inst 3 # number of overall MSHR misses
---
> system.l2c.demand_mshr_misses::total 670 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 363 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 169 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 80 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu2.inst 7 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu2.data 13 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu3.inst 5 # number of overall MSHR misses
2669,2713c2668,2712
< system.l2c.overall_mshr_misses::total 665 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 20340000 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.data 5009000 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 701250 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.data 62500 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 4539000 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu2.data 436250 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 390250 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu3.data 62500 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::total 31540750 # number of ReadReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 230023 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 180018 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 200020 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 170017 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 780078 # number of UpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5761500 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 687000 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 888250 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 700750 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 8037500 # number of ReadExReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 20340000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 10770500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 701250 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 749500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu2.inst 4539000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu2.data 1324500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu3.inst 390250 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu3.data 763250 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 39578250 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 20340000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 10770500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 701250 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 749500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu2.inst 4539000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu2.data 1324500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu3.inst 390250 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu3.data 763250 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 39578250 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.591133 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.024096 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083333 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.155102 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.583333 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.006061 # mshr miss rate for ReadReq accesses
---
> system.l2c.overall_mshr_misses::total 670 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 23217750 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.data 5067250 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 5227250 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.data 465250 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 423750 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu2.data 83750 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 339500 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu3.data 70000 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::total 34894500 # number of ReadReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 391522 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 320018 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 303517 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 337019 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 1352076 # number of UpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6964500 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 963500 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 806000 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 776750 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 9510750 # number of ReadExReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 23217750 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 12031750 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 5227250 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 1428750 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu2.inst 423750 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu2.data 889750 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu3.inst 339500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu3.data 846750 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 44405250 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 23217750 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 12031750 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 5227250 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 1428750 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu2.inst 423750 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu2.data 889750 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu3.inst 339500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu3.data 846750 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 44405250 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.590244 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.160966 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014170 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for ReadReq accesses
2715,2716c2714,2715
< system.l2c.ReadReq_mshr_miss_rate::total 0.241957 # mshr miss rate for ReadReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.884615 # mshr miss rate for UpgradeReq accesses
---
> system.l2c.ReadReq_mshr_miss_rate::total 0.242793 # mshr miss rate for ReadReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses
2720c2719
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.962963 # mshr miss rate for UpgradeReq accesses
---
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.962025 # mshr miss rate for UpgradeReq accesses
2726,2732c2725,2731
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.591133 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.024096 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu2.inst 0.155102 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu3.inst 0.006061 # mshr miss rate for demand accesses
---
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.590244 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.160966 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014170 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for demand accesses
2734,2741c2733,2740
< system.l2c.demand_mshr_miss_rate::total 0.284431 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.591133 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.024096 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu2.inst 0.155102 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006061 # mshr miss rate for overall accesses
---
> system.l2c.demand_mshr_miss_rate::total 0.284985 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.590244 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.160966 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014170 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for overall accesses
2743,2780c2742,2779
< system.l2c.overall_mshr_miss_rate::total 0.284431 # mshr miss rate for overall accesses
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56500 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67689.189189 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58437.500000 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62500 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 59723.684211 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62321.428571 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 130083.333333 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 62500 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::total 59065.074906 # average ReadReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61292.553191 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57250 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 68326.923077 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 58395.833333 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 61354.961832 # average ReadExReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56500 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64110.119048 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58437.500000 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57653.846154 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 59723.684211 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66225 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 130083.333333 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu3.data 58711.538462 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 59516.165414 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56500 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64110.119048 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58437.500000 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57653.846154 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 59723.684211 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66225 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 130083.333333 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu3.data 58711.538462 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 59516.165414 # average overall mshr miss latency
---
> system.l2c.overall_mshr_miss_rate::total 0.284985 # mshr miss rate for overall accesses
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63960.743802 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67563.333333 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65340.625000 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66464.285714 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 60535.714286 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 83750 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 67900 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 70000 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::total 64739.332096 # average ReadReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17796.454545 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17778.777778 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 17853.941176 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 17737.842105 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17790.473684 # average UpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74090.425532 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74115.384615 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 67166.666667 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 64729.166667 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 72601.145038 # average ReadExReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63960.743802 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 71193.786982 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65340.625000 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71437.500000 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 60535.714286 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu2.data 68442.307692 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 67900 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu3.data 65134.615385 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 66276.492537 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63960.743802 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 71193.786982 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65340.625000 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71437.500000 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 60535.714286 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu2.data 68442.307692 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 67900 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu3.data 65134.615385 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 66276.492537 # average overall mshr miss latency
2782,2786c2781,2785
< system.membus.trans_dist::ReadReq 534 # Transaction distribution
< system.membus.trans_dist::ReadResp 533 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 274 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 78 # Transaction distribution
< system.membus.trans_dist::ReadExReq 179 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 539 # Transaction distribution
> system.membus.trans_dist::ReadResp 538 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 276 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 76 # Transaction distribution
> system.membus.trans_dist::ReadExReq 171 # Transaction distribution
2788,2793c2787,2792
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1729 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 1729 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42496 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 42496 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 244 # Total snoops (count)
< system.membus.snoop_fanout::samples 987 # Request fanout histogram
---
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1731 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1731 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42816 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 42816 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 240 # Total snoops (count)
> system.membus.snoop_fanout::samples 986 # Request fanout histogram
2797c2796
< system.membus.snoop_fanout::0 987 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 986 100.00% 100.00% # Request fanout histogram
2802,2803c2801,2802
< system.membus.snoop_fanout::total 987 # Request fanout histogram
< system.membus.reqLayer0.occupancy 933500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 986 # Request fanout histogram
> system.membus.reqLayer0.occupancy 941000 # Layer occupancy (ticks)
2805,2808c2804,2807
< system.membus.respLayer1.occupancy 6348672 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 6.0 # Layer utilization (%)
< system.toL2Bus.trans_dist::ReadReq 2754 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 2753 # Transaction distribution
---
> system.membus.respLayer1.occupancy 3702674 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 3.4 # Layer utilization (%)
> system.toL2Bus.trans_dist::ReadReq 2762 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 2761 # Transaction distribution
2810,2829c2809,2828
< system.toL2Bus.trans_dist::UpgradeReq 277 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 277 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 411 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 411 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1217 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 584 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 996 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 362 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 980 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 990 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 5861 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 38912 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31360 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31680 # Cumulative packet size per connected master and slave (bytes)
---
> system.toL2Bus.trans_dist::UpgradeReq 279 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 279 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 401 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 401 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1229 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 583 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 375 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 988 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 355 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 996 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 5872 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39296 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31808 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31616 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes)
2831,2832c2830,2831
< system.toL2Bus.pkt_size::total 149632 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 1023 # Total snoops (count)
---
> system.toL2Bus.pkt_size::total 150464 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 1012 # Total snoops (count)
2850c2849
< system.toL2Bus.reqLayer0.occupancy 1734981 # Layer occupancy (ticks)
---
> system.toL2Bus.reqLayer0.occupancy 1736971 # Layer occupancy (ticks)
2852,2867c2851,2866
< system.toL2Bus.respLayer0.occupancy 2800749 # Layer occupancy (ticks)
< system.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%)
< system.toL2Bus.respLayer1.occupancy 1466512 # Layer occupancy (ticks)
< system.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
< system.toL2Bus.respLayer2.occupancy 2243496 # Layer occupancy (ticks)
< system.toL2Bus.respLayer2.utilization 2.1 # Layer utilization (%)
< system.toL2Bus.respLayer3.occupancy 1172003 # Layer occupancy (ticks)
< system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%)
< system.toL2Bus.respLayer4.occupancy 2220994 # Layer occupancy (ticks)
< system.toL2Bus.respLayer4.utilization 2.1 # Layer utilization (%)
< system.toL2Bus.respLayer5.occupancy 1183494 # Layer occupancy (ticks)
< system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%)
< system.toL2Bus.respLayer6.occupancy 2229247 # Layer occupancy (ticks)
< system.toL2Bus.respLayer6.utilization 2.1 # Layer utilization (%)
< system.toL2Bus.respLayer7.occupancy 1196246 # Layer occupancy (ticks)
< system.toL2Bus.respLayer7.utilization 1.1 # Layer utilization (%)
---
> system.toL2Bus.respLayer0.occupancy 994999 # Layer occupancy (ticks)
> system.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%)
> system.toL2Bus.respLayer1.occupancy 532769 # Layer occupancy (ticks)
> system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
> system.toL2Bus.respLayer2.occupancy 762997 # Layer occupancy (ticks)
> system.toL2Bus.respLayer2.utilization 0.7 # Layer utilization (%)
> system.toL2Bus.respLayer3.occupancy 438748 # Layer occupancy (ticks)
> system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%)
> system.toL2Bus.respLayer4.occupancy 744992 # Layer occupancy (ticks)
> system.toL2Bus.respLayer4.utilization 0.7 # Layer utilization (%)
> system.toL2Bus.respLayer5.occupancy 415244 # Layer occupancy (ticks)
> system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%)
> system.toL2Bus.respLayer6.occupancy 747996 # Layer occupancy (ticks)
> system.toL2Bus.respLayer6.utilization 0.7 # Layer utilization (%)
> system.toL2Bus.respLayer7.occupancy 406758 # Layer occupancy (ticks)
> system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%)