4,5c4,5
< sim_ticks 110955500 # Number of ticks simulated
< final_tick 110955500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 110872500 # Number of ticks simulated
> final_tick 110872500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 120250 # Simulator instruction rate (inst/s)
< host_op_rate 120250 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 12800201 # Simulator tick rate (ticks/s)
< host_mem_usage 288992 # Number of bytes of host memory used
< host_seconds 8.67 # Real time elapsed on the host
< sim_insts 1042358 # Number of instructions simulated
< sim_ops 1042358 # Number of ops (including micro ops) simulated
---
> host_inst_rate 118027 # Simulator instruction rate (inst/s)
> host_op_rate 118027 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 12557410 # Simulator tick rate (ticks/s)
> host_mem_usage 289008 # Number of bytes of host memory used
> host_seconds 8.83 # Real time elapsed on the host
> sim_insts 1042088 # Number of instructions simulated
> sim_ops 1042088 # Number of ops (including micro ops) simulated
39,61c39,61
< system.physmem.bw_read::cpu0.inst 205343584 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 96903714 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 5768078 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 7498502 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu2.inst 41530163 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu2.data 11536156 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu3.inst 4037655 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu3.data 7498502 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 380116353 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 205343584 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 5768078 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu2.inst 41530163 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu3.inst 4037655 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 256679480 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 205343584 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 96903714 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 5768078 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 7498502 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu2.inst 41530163 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu2.data 11536156 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu3.inst 4037655 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu3.data 7498502 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 380116353 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu0.inst 205497305 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 96976257 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 5772396 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 7504115 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu2.inst 41561253 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu2.data 11544792 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu3.inst 4040677 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu3.data 7504115 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 380400911 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 205497305 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 5772396 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu2.inst 41561253 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu3.inst 4040677 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 256871632 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 205497305 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 96976257 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 5772396 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 7504115 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu2.inst 41561253 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu2.data 11544792 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu3.inst 4040677 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu3.data 7504115 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 380400911 # Total bandwidth to/from this memory (bytes/s)
108c108
< system.physmem.totGap 110927500 # Total gap between requests
---
> system.physmem.totGap 110844500 # Total gap between requests
123,124c123,124
< system.physmem.rdQLenPdf::0 409 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 188 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 403 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 194 # What read queue length does an incoming req see
219,234c219,234
< system.physmem.bytesPerActivate::samples 89 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 285.483146 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 186.878201 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 280.642368 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 28 31.46% 31.46% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 26 29.21% 60.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 13 14.61% 75.28% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 5 5.62% 80.90% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 5 5.62% 86.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 3 3.37% 89.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 2 2.25% 92.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1 1.12% 93.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 6 6.74% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 89 # Bytes accessed per row activation
< system.physmem.totQLat 3793500 # Total ticks spent queuing
< system.physmem.totMemAccLat 17983500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 148 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 275.027027 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 186.656156 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 254.302887 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 45 30.41% 30.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 43 29.05% 59.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 21 14.19% 73.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 12 8.11% 81.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 10 6.76% 88.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 5 3.38% 91.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 5 3.38% 95.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1 0.68% 95.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 6 4.05% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 148 # Bytes accessed per row activation
> system.physmem.totQLat 5597750 # Total ticks spent queuing
> system.physmem.totMemAccLat 17972750 # Total ticks spent from burst creation until serviced by the DRAM
236,238c236
< system.physmem.totBankLat 10890000 # Total ticks spent accessing banks
< system.physmem.avgQLat 5747.73 # Average queueing delay per DRAM burst
< system.physmem.avgBankLat 16500.00 # Average bank access latency per DRAM burst
---
> system.physmem.avgQLat 8481.44 # Average queueing delay per DRAM burst
240,241c238,239
< system.physmem.avgMemAccLat 27247.73 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 380.69 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 27231.44 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 380.98 # Average DRAM read bandwidth in MiByte/s
243c241
< system.physmem.avgRdBWSys 380.69 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 380.98 # Average system read bandwidth in MiByte/s
246,247c244,245
< system.physmem.busUtil 2.97 # Data bus utilization in percentage
< system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 2.98 # Data bus utilization in percentage
> system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads
255c253
< system.physmem.avgGap 168071.97 # Average gap between requests
---
> system.physmem.avgGap 167946.21 # Average gap between requests
257,258c255,260
< system.physmem.prechargeAllPercent 9.12 # Percentage of time for which DRAM has all the banks in precharge state
< system.membus.throughput 380116353 # Throughput (bytes/s)
---
> system.physmem.memoryStateTime::IDLE 48028250 # Time in different power states
> system.physmem.memoryStateTime::REF 3640000 # Time in different power states
> system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
> system.physmem.memoryStateTime::ACT 57613000 # Time in different power states
> system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
> system.membus.throughput 380400911 # Throughput (bytes/s)
271c273
< system.membus.reqLayer0.occupancy 925000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 925500 # Layer occupancy (ticks)
273c275
< system.membus.respLayer1.occupancy 6291924 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 6302174 # Layer occupancy (ticks)
277c279
< system.l2c.tags.tagsinuse 417.123879 # Cycle average of tags in use
---
> system.l2c.tags.tagsinuse 417.213115 # Cycle average of tags in use
282,290c284,292
< system.l2c.tags.occ_blocks::writebacks 0.799384 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 285.051208 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 58.412458 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 7.037952 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 0.694517 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu2.inst 55.368542 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu2.data 5.407900 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu3.inst 3.619836 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu3.data 0.732082 # Average occupied blocks per requestor
---
> system.l2c.tags.occ_blocks::writebacks 0.799585 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 285.091922 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 58.421534 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 7.040102 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 0.695019 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu2.inst 55.399606 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu2.data 5.410902 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu3.inst 3.621924 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu3.data 0.732522 # Average occupied blocks per requestor
300c302
< system.l2c.tags.occ_percent::total 0.006365 # Average percentage of cache occupancy
---
> system.l2c.tags.occ_percent::total 0.006366 # Average percentage of cache occupancy
303,304c305,306
< system.l2c.tags.age_task_id_blocks_1024::1 295 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 180 # Occupied blocks per task id
---
> system.l2c.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 179 # Occupied blocks per task id
376,378c378,380
< system.l2c.ReadReq_miss_latency::cpu0.inst 24538000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.data 5612000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.inst 1134000 # number of ReadReq miss cycles
---
> system.l2c.ReadReq_miss_latency::cpu0.inst 24533250 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.data 5569000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.inst 1122250 # number of ReadReq miss cycles
380c382
< system.l2c.ReadReq_miss_latency::cpu2.inst 5318500 # number of ReadReq miss cycles
---
> system.l2c.ReadReq_miss_latency::cpu2.inst 5286500 # number of ReadReq miss cycles
384,385c386,387
< system.l2c.ReadReq_miss_latency::total 37905000 # number of ReadReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 6786000 # number of ReadExReq miss cycles
---
> system.l2c.ReadReq_miss_latency::total 37813500 # number of ReadReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 6780000 # number of ReadExReq miss cycles
388,392c390,394
< system.l2c.ReadExReq_miss_latency::cpu3.data 978750 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 9704000 # number of ReadExReq miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 24538000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 12398000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 1134000 # number of demand (read+write) miss cycles
---
> system.l2c.ReadExReq_miss_latency::cpu3.data 943000 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 9662250 # number of ReadExReq miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 24533250 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 12349000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 1122250 # number of demand (read+write) miss cycles
394c396
< system.l2c.demand_miss_latency::cpu2.inst 5318500 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::cpu2.inst 5286500 # number of demand (read+write) miss cycles
397,401c399,403
< system.l2c.demand_miss_latency::cpu3.data 1053250 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 47609000 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 24538000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 12398000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 1134000 # number of overall miss cycles
---
> system.l2c.demand_miss_latency::cpu3.data 1017500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 47475750 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 24533250 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 12349000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 1122250 # number of overall miss cycles
403c405
< system.l2c.overall_miss_latency::cpu2.inst 5318500 # number of overall miss cycles
---
> system.l2c.overall_miss_latency::cpu2.inst 5286500 # number of overall miss cycles
406,407c408,409
< system.l2c.overall_miss_latency::cpu3.data 1053250 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 47609000 # number of overall miss cycles
---
> system.l2c.overall_miss_latency::cpu3.data 1017500 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 47475750 # number of overall miss cycles
484,486c486,488
< system.l2c.ReadReq_avg_miss_latency::cpu0.inst 68350.974930 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.data 75837.837838 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75600 # average ReadReq miss latency
---
> system.l2c.ReadReq_avg_miss_latency::cpu0.inst 68337.743733 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.data 75256.756757 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74816.666667 # average ReadReq miss latency
488c490
< system.l2c.ReadReq_avg_miss_latency::cpu2.inst 69980.263158 # average ReadReq miss latency
---
> system.l2c.ReadReq_avg_miss_latency::cpu2.inst 69559.210526 # average ReadReq miss latency
492,493c494,495
< system.l2c.ReadReq_avg_miss_latency::total 69806.629834 # average ReadReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 72191.489362 # average ReadExReq miss latency
---
> system.l2c.ReadReq_avg_miss_latency::total 69638.121547 # average ReadReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 72127.659574 # average ReadExReq miss latency
496,500c498,502
< system.l2c.ReadExReq_avg_miss_latency::cpu3.data 81562.500000 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 74076.335878 # average ReadExReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 68350.974930 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 73797.619048 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 75600 # average overall miss latency
---
> system.l2c.ReadExReq_avg_miss_latency::cpu3.data 78583.333333 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 73757.633588 # average ReadExReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 68337.743733 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 73505.952381 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 74816.666667 # average overall miss latency
502c504
< system.l2c.demand_avg_miss_latency::cpu2.inst 69980.263158 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu2.inst 69559.210526 # average overall miss latency
505,509c507,511
< system.l2c.demand_avg_miss_latency::cpu3.data 81019.230769 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 70636.498516 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 68350.974930 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 73797.619048 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 75600 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu3.data 78269.230769 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 70438.798220 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 68337.743733 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 73505.952381 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 74816.666667 # average overall miss latency
511c513
< system.l2c.overall_avg_miss_latency::cpu2.inst 69980.263158 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::cpu2.inst 69559.210526 # average overall miss latency
514,515c516,517
< system.l2c.overall_avg_miss_latency::cpu3.data 81019.230769 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 70636.498516 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::cpu3.data 78269.230769 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 70438.798220 # average overall miss latency
576,578c578,580
< system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 19975750 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.data 4701500 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 711000 # number of ReadReq MSHR miss cycles
---
> system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 19962500 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.data 4657000 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 698750 # number of ReadReq MSHR miss cycles
580c582
< system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 4193250 # number of ReadReq MSHR miss cycles
---
> system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 4160750 # number of ReadReq MSHR miss cycles
584c586
< system.l2c.ReadReq_mshr_miss_latency::total 30546500 # number of ReadReq MSHR miss cycles
---
> system.l2c.ReadReq_mshr_miss_latency::total 30444000 # number of ReadReq MSHR miss cycles
590c592
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5616500 # number of ReadExReq MSHR miss cycles
---
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5606500 # number of ReadExReq MSHR miss cycles
593,597c595,599
< system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 828750 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 8075000 # number of ReadExReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 19975750 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 10318000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 711000 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 792500 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 8028750 # number of ReadExReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 19962500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 10263500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 698750 # number of demand (read+write) MSHR miss cycles
599c601
< system.l2c.demand_mshr_miss_latency::cpu2.inst 4193250 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu2.inst 4160750 # number of demand (read+write) MSHR miss cycles
602,606c604,608
< system.l2c.demand_mshr_miss_latency::cpu3.data 891250 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 38621500 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 19975750 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 10318000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 711000 # number of overall MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu3.data 855000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 38472750 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 19962500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 10263500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 698750 # number of overall MSHR miss cycles
608c610
< system.l2c.overall_mshr_miss_latency::cpu2.inst 4193250 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::cpu2.inst 4160750 # number of overall MSHR miss cycles
611,612c613,614
< system.l2c.overall_mshr_miss_latency::cpu3.data 891250 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 38621500 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::cpu3.data 855000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 38472750 # number of overall MSHR miss cycles
650,652c652,654
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55954.481793 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63533.783784 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71100 # average ReadReq mshr miss latency
---
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55917.366947 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62932.432432 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69875 # average ReadReq mshr miss latency
654c656
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 58239.583333 # average ReadReq mshr miss latency
---
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 57788.194444 # average ReadReq mshr miss latency
658c660
< system.l2c.ReadReq_avg_mshr_miss_latency::total 57743.856333 # average ReadReq mshr miss latency
---
> system.l2c.ReadReq_avg_mshr_miss_latency::total 57550.094518 # average ReadReq mshr miss latency
664c666
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59750 # average ReadExReq mshr miss latency
---
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59643.617021 # average ReadExReq mshr miss latency
667,671c669,673
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 69062.500000 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 61641.221374 # average ReadExReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55954.481793 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61416.666667 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71100 # average overall mshr miss latency
---
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 66041.666667 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 61288.167939 # average ReadExReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55917.366947 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61092.261905 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69875 # average overall mshr miss latency
673c675
< system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 58239.583333 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 57788.194444 # average overall mshr miss latency
676,680c678,682
< system.l2c.demand_avg_mshr_miss_latency::cpu3.data 68557.692308 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 58517.424242 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55954.481793 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61416.666667 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71100 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu3.data 65769.230769 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 58292.045455 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55917.366947 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61092.261905 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69875 # average overall mshr miss latency
682c684
< system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 58239.583333 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57788.194444 # average overall mshr miss latency
685,686c687,688
< system.l2c.overall_avg_mshr_miss_latency::cpu3.data 68557.692308 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 58517.424242 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu3.data 65769.230769 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 58292.045455 # average overall mshr miss latency
688c690
< system.toL2Bus.throughput 1688893295 # Throughput (bytes/s)
---
> system.toL2Bus.throughput 1690157613 # Throughput (bytes/s)
716c718
< system.toL2Bus.reqLayer0.occupancy 1624976 # Layer occupancy (ticks)
---
> system.toL2Bus.reqLayer0.occupancy 1624477 # Layer occupancy (ticks)
718c720
< system.toL2Bus.respLayer0.occupancy 2704748 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 2708498 # Layer occupancy (ticks)
720c722
< system.toL2Bus.respLayer1.occupancy 1464514 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 1467012 # Layer occupancy (ticks)
722c724
< system.toL2Bus.respLayer2.occupancy 1928496 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer2.occupancy 1928746 # Layer occupancy (ticks)
728c730
< system.toL2Bus.respLayer5.occupancy 1209236 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer5.occupancy 1209237 # Layer occupancy (ticks)
732c734
< system.toL2Bus.respLayer7.occupancy 1133252 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer7.occupancy 1133003 # Layer occupancy (ticks)
734,735c736,737
< system.cpu0.branchPred.lookups 83023 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 80825 # Number of conditional branches predicted
---
> system.cpu0.branchPred.lookups 82981 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 80783 # Number of conditional branches predicted
737,738c739,740
< system.cpu0.branchPred.BTBLookups 80352 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 78307 # Number of BTB hits
---
> system.cpu0.branchPred.BTBLookups 80310 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 78265 # Number of BTB hits
740c742
< system.cpu0.branchPred.BTBHitPct 97.454948 # BTB Hit Percentage
---
> system.cpu0.branchPred.BTBHitPct 97.453617 # BTB Hit Percentage
744c746
< system.cpu0.numCycles 221912 # number of cpu cycles simulated
---
> system.cpu0.numCycles 221746 # number of cpu cycles simulated
747,751c749,753
< system.cpu0.fetch.icacheStallCycles 17233 # Number of cycles fetch is stalled on an Icache miss
< system.cpu0.fetch.Insts 492726 # Number of instructions fetch has processed
< system.cpu0.fetch.Branches 83023 # Number of branches that fetch encountered
< system.cpu0.fetch.predictedBranches 78819 # Number of branches that fetch has predicted taken
< system.cpu0.fetch.Cycles 161746 # Number of cycles fetch has run and was not squashing or blocked
---
> system.cpu0.fetch.icacheStallCycles 17234 # Number of cycles fetch is stalled on an Icache miss
> system.cpu0.fetch.Insts 492474 # Number of instructions fetch has processed
> system.cpu0.fetch.Branches 82981 # Number of branches that fetch encountered
> system.cpu0.fetch.predictedBranches 78777 # Number of branches that fetch has predicted taken
> system.cpu0.fetch.Cycles 161662 # Number of cycles fetch has run and was not squashing or blocked
753c755
< system.cpu0.fetch.BlockedCycles 13929 # Number of cycles fetch has spent blocked
---
> system.cpu0.fetch.BlockedCycles 13862 # Number of cycles fetch has spent blocked
757,760c759,762
< system.cpu0.fetch.IcacheSquashes 493 # Number of outstanding Icache misses that were squashed
< system.cpu0.fetch.rateDist::samples 196870 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::mean 2.502799 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::stdev 2.215097 # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.IcacheSquashes 492 # Number of outstanding Icache misses that were squashed
> system.cpu0.fetch.rateDist::samples 196720 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::mean 2.503426 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::stdev 2.215057 # Number of instructions fetched each cycle (Total)
762,768c764,770
< system.cpu0.fetch.rateDist::0 35124 17.84% 17.84% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::1 80120 40.70% 58.54% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::2 578 0.29% 58.83% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::3 973 0.49% 59.33% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::4 477 0.24% 59.57% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::5 76224 38.72% 98.29% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::6 570 0.29% 98.58% # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.rateDist::0 35058 17.82% 17.82% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::1 80078 40.71% 58.53% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::2 578 0.29% 58.82% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::3 973 0.49% 59.32% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::4 477 0.24% 59.56% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::5 76182 38.73% 98.28% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::6 570 0.29% 98.57% # Number of instructions fetched each cycle (Total)
774,779c776,781
< system.cpu0.fetch.rateDist::total 196870 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.branchRate 0.374126 # Number of branch fetches per cycle
< system.cpu0.fetch.rate 2.220367 # Number of inst fetches per cycle
< system.cpu0.decode.IdleCycles 17821 # Number of cycles decode is idle
< system.cpu0.decode.BlockedCycles 15547 # Number of cycles decode is blocked
< system.cpu0.decode.RunCycles 160777 # Number of cycles decode is running
---
> system.cpu0.fetch.rateDist::total 196720 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.branchRate 0.374216 # Number of branch fetches per cycle
> system.cpu0.fetch.rate 2.220892 # Number of inst fetches per cycle
> system.cpu0.decode.IdleCycles 17819 # Number of cycles decode is idle
> system.cpu0.decode.BlockedCycles 15483 # Number of cycles decode is blocked
> system.cpu0.decode.RunCycles 160693 # Number of cycles decode is running
782c784
< system.cpu0.decode.DecodedInsts 489900 # Number of instructions handled by decode
---
> system.cpu0.decode.DecodedInsts 489648 # Number of instructions handled by decode
784,789c786,791
< system.cpu0.rename.IdleCycles 18476 # Number of cycles rename is idle
< system.cpu0.rename.BlockCycles 865 # Number of cycles rename is blocking
< system.cpu0.rename.serializeStallCycles 14063 # count of cycles rename stalled for serializing inst
< system.cpu0.rename.RunCycles 160426 # Number of cycles rename is running
< system.cpu0.rename.UnblockCycles 595 # Number of cycles rename is unblocking
< system.cpu0.rename.RenamedInsts 487057 # Number of instructions processed by rename
---
> system.cpu0.rename.IdleCycles 18474 # Number of cycles rename is idle
> system.cpu0.rename.BlockCycles 866 # Number of cycles rename is blocking
> system.cpu0.rename.serializeStallCycles 14003 # count of cycles rename stalled for serializing inst
> system.cpu0.rename.RunCycles 160341 # Number of cycles rename is running
> system.cpu0.rename.UnblockCycles 591 # Number of cycles rename is unblocking
> system.cpu0.rename.RenamedInsts 486805 # Number of instructions processed by rename
791,794c793,796
< system.cpu0.rename.RenamedOperands 333048 # Number of destination operands rename has renamed
< system.cpu0.rename.RenameLookups 971305 # Number of register rename lookups that rename has made
< system.cpu0.rename.int_rename_lookups 733660 # Number of integer rename lookups
< system.cpu0.rename.CommittedMaps 320079 # Number of HB maps that are committed
---
> system.cpu0.rename.RenamedOperands 332880 # Number of destination operands rename has renamed
> system.cpu0.rename.RenameLookups 970801 # Number of register rename lookups that rename has made
> system.cpu0.rename.int_rename_lookups 733282 # Number of integer rename lookups
> system.cpu0.rename.CommittedMaps 319911 # Number of HB maps that are committed
798,803c800,805
< system.cpu0.rename.skidInsts 3628 # count of insts added to the skid buffer
< system.cpu0.memDep0.insertedLoads 155827 # Number of loads inserted to the mem dependence unit.
< system.cpu0.memDep0.insertedStores 78749 # Number of stores inserted to the mem dependence unit.
< system.cpu0.memDep0.conflictingLoads 76001 # Number of conflicting loads.
< system.cpu0.memDep0.conflictingStores 75817 # Number of conflicting stores.
< system.cpu0.iq.iqInstsAdded 407304 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu0.rename.skidInsts 3624 # count of insts added to the skid buffer
> system.cpu0.memDep0.insertedLoads 155743 # Number of loads inserted to the mem dependence unit.
> system.cpu0.memDep0.insertedStores 78707 # Number of stores inserted to the mem dependence unit.
> system.cpu0.memDep0.conflictingLoads 75959 # Number of conflicting loads.
> system.cpu0.memDep0.conflictingStores 75775 # Number of conflicting stores.
> system.cpu0.iq.iqInstsAdded 407094 # Number of instructions added to the IQ (excludes non-spec)
805,806c807,808
< system.cpu0.iq.iqInstsIssued 404579 # Number of instructions issued
< system.cpu0.iq.iqSquashedInstsIssued 133 # Number of squashed instructions issued
---
> system.cpu0.iq.iqInstsIssued 404367 # Number of instructions issued
> system.cpu0.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued
808c810
< system.cpu0.iq.iqSquashedOperandsExamined 9747 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu0.iq.iqSquashedOperandsExamined 9755 # Number of squashed operands that are examined and possibly removed from graph
810,812c812,814
< system.cpu0.iq.issued_per_cycle::samples 196870 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::mean 2.055057 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::stdev 1.097769 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::samples 196720 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::mean 2.055546 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::stdev 1.097437 # Number of insts issued each cycle
814,819c816,821
< system.cpu0.iq.issued_per_cycle::0 34107 17.32% 17.32% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::1 4943 2.51% 19.84% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::2 77928 39.58% 59.42% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::3 77295 39.26% 98.68% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::4 1579 0.80% 99.48% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::5 650 0.33% 99.81% # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::0 34036 17.30% 17.30% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::1 4955 2.52% 19.82% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::2 77877 39.59% 59.41% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::3 77259 39.27% 98.68% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::4 1573 0.80% 99.48% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::5 652 0.33% 99.81% # Number of insts issued each cycle
826c828
< system.cpu0.iq.issued_per_cycle::total 196870 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::total 196720 # Number of insts issued each cycle
828,858c830,860
< system.cpu0.iq.fu_full::IntAlu 57 25.68% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntMult 0 0.00% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemRead 53 23.87% 49.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemWrite 112 50.45% 100.00% # attempts to use FU when none available
---
> system.cpu0.iq.fu_full::IntAlu 57 25.79% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntMult 0 0.00% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemRead 52 23.53% 49.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemWrite 112 50.68% 100.00% # attempts to use FU when none available
862c864
< system.cpu0.iq.FU_type_0::IntAlu 171055 42.28% 42.28% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::IntAlu 170970 42.28% 42.28% # Type of FU issued
891,892c893,894
< system.cpu0.iq.FU_type_0::MemRead 155363 38.40% 80.68% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemWrite 78161 19.32% 100.00% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::MemRead 155279 38.40% 80.68% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemWrite 78118 19.32% 100.00% # Type of FU issued
895,901c897,903
< system.cpu0.iq.FU_type_0::total 404579 # Type of FU issued
< system.cpu0.iq.rate 1.823151 # Inst issue rate
< system.cpu0.iq.fu_busy_cnt 222 # FU busy when requested
< system.cpu0.iq.fu_busy_rate 0.000549 # FU busy rate (busy events/executed inst)
< system.cpu0.iq.int_inst_queue_reads 1006383 # Number of integer instruction queue reads
< system.cpu0.iq.int_inst_queue_writes 419039 # Number of integer instruction queue writes
< system.cpu0.iq.int_inst_queue_wakeup_accesses 402754 # Number of integer instruction queue wakeup accesses
---
> system.cpu0.iq.FU_type_0::total 404367 # Type of FU issued
> system.cpu0.iq.rate 1.823559 # Inst issue rate
> system.cpu0.iq.fu_busy_cnt 221 # FU busy when requested
> system.cpu0.iq.fu_busy_rate 0.000547 # FU busy rate (busy events/executed inst)
> system.cpu0.iq.int_inst_queue_reads 1005807 # Number of integer instruction queue reads
> system.cpu0.iq.int_inst_queue_writes 418829 # Number of integer instruction queue writes
> system.cpu0.iq.int_inst_queue_wakeup_accesses 402541 # Number of integer instruction queue wakeup accesses
905c907
< system.cpu0.iq.int_alu_accesses 404801 # Number of integer alu accesses
---
> system.cpu0.iq.int_alu_accesses 404588 # Number of integer alu accesses
907c909
< system.cpu0.iew.lsq.thread0.forwLoads 75529 # Number of loads that had data forwarded from stores
---
> system.cpu0.iew.lsq.thread0.forwLoads 75486 # Number of loads that had data forwarded from stores
916c918
< system.cpu0.iew.lsq.thread0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu0.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked
919,924c921,926
< system.cpu0.iew.iewBlockCycles 405 # Number of cycles IEW is blocking
< system.cpu0.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking
< system.cpu0.iew.iewDispatchedInsts 484766 # Number of instructions dispatched to IQ
< system.cpu0.iew.iewDispSquashedInsts 308 # Number of squashed instructions skipped by dispatch
< system.cpu0.iew.iewDispLoadInsts 155827 # Number of dispatched load instructions
< system.cpu0.iew.iewDispStoreInsts 78749 # Number of dispatched store instructions
---
> system.cpu0.iew.iewBlockCycles 400 # Number of cycles IEW is blocking
> system.cpu0.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking
> system.cpu0.iew.iewDispatchedInsts 484514 # Number of instructions dispatched to IQ
> system.cpu0.iew.iewDispSquashedInsts 312 # Number of squashed instructions skipped by dispatch
> system.cpu0.iew.iewDispLoadInsts 155743 # Number of dispatched load instructions
> system.cpu0.iew.iewDispStoreInsts 78707 # Number of dispatched store instructions
932,933c934,935
< system.cpu0.iew.iewExecutedInsts 403510 # Number of executed instructions
< system.cpu0.iew.iewExecLoadInsts 155033 # Number of load instructions executed
---
> system.cpu0.iew.iewExecutedInsts 403298 # Number of executed instructions
> system.cpu0.iew.iewExecLoadInsts 154949 # Number of load instructions executed
936,944c938,946
< system.cpu0.iew.exec_nop 76552 # number of nop insts executed
< system.cpu0.iew.exec_refs 233092 # number of memory reference insts executed
< system.cpu0.iew.exec_branches 80162 # Number of branches executed
< system.cpu0.iew.exec_stores 78059 # Number of stores executed
< system.cpu0.iew.exec_rate 1.818333 # Inst execution rate
< system.cpu0.iew.wb_sent 403084 # cumulative count of insts sent to commit
< system.cpu0.iew.wb_count 402754 # cumulative count of insts written-back
< system.cpu0.iew.wb_producers 238663 # num instructions producing a value
< system.cpu0.iew.wb_consumers 241120 # num instructions consuming a value
---
> system.cpu0.iew.exec_nop 76510 # number of nop insts executed
> system.cpu0.iew.exec_refs 232965 # number of memory reference insts executed
> system.cpu0.iew.exec_branches 80120 # Number of branches executed
> system.cpu0.iew.exec_stores 78016 # Number of stores executed
> system.cpu0.iew.exec_rate 1.818739 # Inst execution rate
> system.cpu0.iew.wb_sent 402871 # cumulative count of insts sent to commit
> system.cpu0.iew.wb_count 402541 # cumulative count of insts written-back
> system.cpu0.iew.wb_producers 238524 # num instructions producing a value
> system.cpu0.iew.wb_consumers 240975 # num instructions consuming a value
946,947c948,949
< system.cpu0.iew.wb_rate 1.814927 # insts written-back per cycle
< system.cpu0.iew.wb_fanout 0.989810 # average fanout of values written-back
---
> system.cpu0.iew.wb_rate 1.815325 # insts written-back per cycle
> system.cpu0.iew.wb_fanout 0.989829 # average fanout of values written-back
952,954c954,956
< system.cpu0.commit.committed_per_cycle::samples 194425 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::mean 2.430089 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::stdev 2.136483 # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::samples 194275 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::mean 2.430668 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::stdev 2.136401 # Number of insts commited each cycle
956,964c958,966
< system.cpu0.commit.committed_per_cycle::0 34537 17.76% 17.76% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::1 79950 41.12% 58.88% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::2 2378 1.22% 60.11% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::3 690 0.35% 60.46% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::4 530 0.27% 60.74% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::5 75328 38.74% 99.48% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::6 457 0.24% 99.71% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::7 248 0.13% 99.84% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::8 307 0.16% 100.00% # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::0 34469 17.74% 17.74% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::1 79913 41.13% 58.88% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::2 2377 1.22% 60.10% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::3 686 0.35% 60.45% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::4 532 0.27% 60.73% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::5 75283 38.75% 99.48% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::6 460 0.24% 99.71% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::7 250 0.13% 99.84% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::8 305 0.16% 100.00% # Number of insts commited each cycle
968,970c970,972
< system.cpu0.commit.committed_per_cycle::total 194425 # Number of insts commited each cycle
< system.cpu0.commit.committedInsts 472470 # Number of instructions committed
< system.cpu0.commit.committedOps 472470 # Number of ops (including micro ops) committed
---
> system.cpu0.commit.committed_per_cycle::total 194275 # Number of insts commited each cycle
> system.cpu0.commit.committedInsts 472218 # Number of instructions committed
> system.cpu0.commit.committedOps 472218 # Number of ops (including micro ops) committed
972,973c974,975
< system.cpu0.commit.refs 230950 # Number of memory references committed
< system.cpu0.commit.loads 153629 # Number of loads committed
---
> system.cpu0.commit.refs 230824 # Number of memory references committed
> system.cpu0.commit.loads 153545 # Number of loads committed
975c977
< system.cpu0.commit.branches 79208 # Number of branches committed
---
> system.cpu0.commit.branches 79166 # Number of branches committed
977c979
< system.cpu0.commit.int_insts 318410 # Number of committed integer instructions.
---
> system.cpu0.commit.int_insts 318242 # Number of committed integer instructions.
979c981,1016
< system.cpu0.commit.bw_lim_events 307 # number cycles where commit BW limit reached
---
> system.cpu0.commit.op_class_0::No_OpClass 75898 16.07% 16.07% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntAlu 165412 35.03% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.10% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemRead 153629 32.53% 83.63% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemWrite 77279 16.37% 100.00% # Class of committed instruction
> system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
> system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
> system.cpu0.commit.op_class_0::total 472218 # Class of committed instruction
> system.cpu0.commit.bw_lim_events 305 # number cycles where commit BW limit reached
981,982c1018,1019
< system.cpu0.rob.rob_reads 677696 # The number of ROB reads
< system.cpu0.rob.rob_writes 971940 # The number of ROB writes
---
> system.cpu0.rob.rob_reads 677296 # The number of ROB reads
> system.cpu0.rob.rob_writes 971436 # The number of ROB writes
984,993c1021,1030
< system.cpu0.idleCycles 25042 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu0.committedInsts 396446 # Number of Instructions Simulated
< system.cpu0.committedOps 396446 # Number of Ops (including micro ops) Simulated
< system.cpu0.committedInsts_total 396446 # Number of Instructions Simulated
< system.cpu0.cpi 0.559753 # CPI: Cycles Per Instruction
< system.cpu0.cpi_total 0.559753 # CPI: Total CPI of All Threads
< system.cpu0.ipc 1.786501 # IPC: Instructions Per Cycle
< system.cpu0.ipc_total 1.786501 # IPC: Total IPC of All Threads
< system.cpu0.int_regfile_reads 721878 # number of integer regfile reads
< system.cpu0.int_regfile_writes 325337 # number of integer regfile writes
---
> system.cpu0.idleCycles 25026 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu0.committedInsts 396236 # Number of Instructions Simulated
> system.cpu0.committedOps 396236 # Number of Ops (including micro ops) Simulated
> system.cpu0.committedInsts_total 396236 # Number of Instructions Simulated
> system.cpu0.cpi 0.559631 # CPI: Cycles Per Instruction
> system.cpu0.cpi_total 0.559631 # CPI: Total CPI of All Threads
> system.cpu0.ipc 1.786891 # IPC: Instructions Per Cycle
> system.cpu0.ipc_total 1.786891 # IPC: Total IPC of All Threads
> system.cpu0.int_regfile_reads 721496 # number of integer regfile reads
> system.cpu0.int_regfile_writes 325166 # number of integer regfile writes
995c1032
< system.cpu0.misc_regfile_reads 234915 # number of misc regfile reads
---
> system.cpu0.misc_regfile_reads 234788 # number of misc regfile reads
998c1035
< system.cpu0.icache.tags.tagsinuse 241.280038 # Cycle average of tags in use
---
> system.cpu0.icache.tags.tagsinuse 241.323737 # Cycle average of tags in use
1003,1005c1040,1042
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.280038 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471250 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.471250 # Average percentage of cache occupancy
---
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.323737 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471335 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.471335 # Average percentage of cache occupancy
1025,1030c1062,1067
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35676245 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 35676245 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 35676245 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 35676245 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 35676245 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 35676245 # number of overall miss cycles
---
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35655495 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 35655495 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 35655495 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 35655495 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 35655495 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 35655495 # number of overall miss cycles
1043,1048c1080,1085
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47190.800265 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 47190.800265 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47190.800265 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 47190.800265 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47190.800265 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 47190.800265 # average overall miss latency
---
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47163.353175 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 47163.353175 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47163.353175 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 47163.353175 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47163.353175 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 47163.353175 # average overall miss latency
1069,1074c1106,1111
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27430752 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 27430752 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27430752 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 27430752 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27430752 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 27430752 # number of overall MSHR miss cycles
---
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27420002 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 27420002 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27420002 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 27420002 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27420002 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 27420002 # number of overall MSHR miss cycles
1081,1086c1118,1123
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46650.938776 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46650.938776 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46650.938776 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 46650.938776 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46650.938776 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 46650.938776 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46632.656463 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46632.656463 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46632.656463 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 46632.656463 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46632.656463 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 46632.656463 # average overall mshr miss latency
1089,1090c1126,1127
< system.cpu0.dcache.tags.tagsinuse 142.009454 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 155675 # Total number of references to valid blocks.
---
> system.cpu0.dcache.tags.tagsinuse 142.026535 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 155594 # Total number of references to valid blocks.
1092c1129
< system.cpu0.dcache.tags.avg_refs 915.735294 # Average number of references to valid blocks.
---
> system.cpu0.dcache.tags.avg_refs 915.258824 # Average number of references to valid blocks.
1094,1096c1131,1133
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.009454 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277362 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.277362 # Average percentage of cache occupancy
---
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.026535 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277396 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.277396 # Average percentage of cache occupancy
1102,1107c1139,1144
< system.cpu0.dcache.tags.tag_accesses 627368 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 627368 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 79025 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 79025 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 76734 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 76734 # number of WriteReq hits
---
> system.cpu0.dcache.tags.tag_accesses 627036 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 627036 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 78986 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 78986 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 76692 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 76692 # number of WriteReq hits
1110,1115c1147,1152
< system.cpu0.dcache.demand_hits::cpu0.data 155759 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 155759 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 155759 # number of overall hits
< system.cpu0.dcache.overall_hits::total 155759 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 418 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 418 # number of ReadReq misses
---
> system.cpu0.dcache.demand_hits::cpu0.data 155678 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 155678 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 155678 # number of overall hits
> system.cpu0.dcache.overall_hits::total 155678 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 416 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 416 # number of ReadReq misses
1120,1127c1157,1164
< system.cpu0.dcache.demand_misses::cpu0.data 963 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 963 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 963 # number of overall misses
< system.cpu0.dcache.overall_misses::total 963 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13454697 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 13454697 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32621759 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 32621759 # number of WriteReq miss cycles
---
> system.cpu0.dcache.demand_misses::cpu0.data 961 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 961 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 961 # number of overall misses
> system.cpu0.dcache.overall_misses::total 961 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13375931 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 13375931 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32683256 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 32683256 # number of WriteReq miss cycles
1130,1137c1167,1174
< system.cpu0.dcache.demand_miss_latency::cpu0.data 46076456 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 46076456 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 46076456 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 46076456 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 79443 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 79443 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 77279 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 77279 # number of WriteReq accesses(hits+misses)
---
> system.cpu0.dcache.demand_miss_latency::cpu0.data 46059187 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 46059187 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 46059187 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 46059187 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 79402 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 79402 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 77237 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 77237 # number of WriteReq accesses(hits+misses)
1140,1147c1177,1184
< system.cpu0.dcache.demand_accesses::cpu0.data 156722 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 156722 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 156722 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 156722 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005262 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.005262 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007052 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.007052 # miss rate for WriteReq accesses
---
> system.cpu0.dcache.demand_accesses::cpu0.data 156639 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 156639 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 156639 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 156639 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005239 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.005239 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007056 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.007056 # miss rate for WriteReq accesses
1150,1157c1187,1194
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006145 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.006145 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006145 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.006145 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32188.270335 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 32188.270335 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 59856.438532 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 59856.438532 # average WriteReq miss latency
---
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006135 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.006135 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006135 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.006135 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32153.680288 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 32153.680288 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 59969.277064 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 59969.277064 # average WriteReq miss latency
1160,1164c1197,1201
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47846.787124 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 47846.787124 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47846.787124 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 47846.787124 # average overall miss latency
< system.cpu0.dcache.blocked_cycles::no_mshrs 524 # number of cycles access was blocked
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47928.394381 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 47928.394381 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47928.394381 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 47928.394381 # average overall miss latency
> system.cpu0.dcache.blocked_cycles::no_mshrs 512 # number of cycles access was blocked
1166c1203
< system.cpu0.dcache.blocked::no_mshrs 20 # number of cycles access was blocked
---
> system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked
1168c1205
< system.cpu0.dcache.avg_blocked_cycles::no_mshrs 26.200000 # average number of cycles each access was blocked
---
> system.cpu0.dcache.avg_blocked_cycles::no_mshrs 24.380952 # average number of cycles each access was blocked
1174,1175c1211,1212
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 230 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 230 # number of ReadReq MSHR hits
---
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 228 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 228 # number of ReadReq MSHR hits
1178,1181c1215,1218
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 600 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 600 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 600 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 600 # number of overall MSHR hits
---
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 598 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 598 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 598 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 598 # number of overall MSHR hits
1192,1195c1229,1232
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6237508 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6237508 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7264228 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7264228 # number of WriteReq MSHR miss cycles
---
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6192510 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6192510 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7258228 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7258228 # number of WriteReq MSHR miss cycles
1198,1205c1235,1242
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13501736 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 13501736 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13501736 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 13501736 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002366 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002366 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002265 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002265 # mshr miss rate for WriteReq accesses
---
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13450738 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 13450738 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13450738 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 13450738 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002368 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002368 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002266 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002266 # mshr miss rate for WriteReq accesses
1208,1215c1245,1252
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002316 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.002316 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002316 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.002316 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 33178.234043 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 33178.234043 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41509.874286 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41509.874286 # average WriteReq mshr miss latency
---
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002317 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.002317 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002317 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.002317 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32938.882979 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32938.882979 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41475.588571 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41475.588571 # average WriteReq mshr miss latency
1218,1221c1255,1258
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37194.865014 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37194.865014 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37194.865014 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37194.865014 # average overall mshr miss latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37054.374656 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37054.374656 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37054.374656 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37054.374656 # average overall mshr miss latency
1223,1224c1260,1261
< system.cpu1.branchPred.lookups 49230 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 46482 # Number of conditional branches predicted
---
> system.cpu1.branchPred.lookups 49222 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 46474 # Number of conditional branches predicted
1226,1227c1263,1264
< system.cpu1.branchPred.BTBLookups 43125 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 42318 # Number of BTB hits
---
> system.cpu1.branchPred.BTBLookups 43117 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 42310 # Number of BTB hits
1229c1266
< system.cpu1.branchPred.BTBHitPct 98.128696 # BTB Hit Percentage
---
> system.cpu1.branchPred.BTBHitPct 98.128348 # BTB Hit Percentage
1232c1269
< system.cpu1.numCycles 177729 # number of cpu cycles simulated
---
> system.cpu1.numCycles 177641 # number of cpu cycles simulated
1235,1239c1272,1276
< system.cpu1.fetch.icacheStallCycles 30707 # Number of cycles fetch is stalled on an Icache miss
< system.cpu1.fetch.Insts 271510 # Number of instructions fetch has processed
< system.cpu1.fetch.Branches 49230 # Number of branches that fetch encountered
< system.cpu1.fetch.predictedBranches 42962 # Number of branches that fetch has predicted taken
< system.cpu1.fetch.Cycles 98061 # Number of cycles fetch has run and was not squashing or blocked
---
> system.cpu1.fetch.icacheStallCycles 30689 # Number of cycles fetch is stalled on an Icache miss
> system.cpu1.fetch.Insts 271480 # Number of instructions fetch has processed
> system.cpu1.fetch.Branches 49222 # Number of branches that fetch encountered
> system.cpu1.fetch.predictedBranches 42954 # Number of branches that fetch has predicted taken
> system.cpu1.fetch.Cycles 98036 # Number of cycles fetch has run and was not squashing or blocked
1241c1278
< system.cpu1.fetch.BlockedCycles 35852 # Number of cycles fetch has spent blocked
---
> system.cpu1.fetch.BlockedCycles 35816 # Number of cycles fetch has spent blocked
1243c1280
< system.cpu1.fetch.NoActiveThreadStallCycles 7757 # Number of stall cycles due to no active thread to fetch from
---
> system.cpu1.fetch.NoActiveThreadStallCycles 7751 # Number of stall cycles due to no active thread to fetch from
1245c1282
< system.cpu1.fetch.CacheLines 22354 # Number of cache lines fetched
---
> system.cpu1.fetch.CacheLines 22336 # Number of cache lines fetched
1247,1249c1284,1286
< system.cpu1.fetch.rateDist::samples 175517 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::mean 1.546916 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::stdev 2.089154 # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::samples 175432 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::mean 1.547494 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::stdev 2.089471 # Number of instructions fetched each cycle (Total)
1251,1257c1288,1294
< system.cpu1.fetch.rateDist::0 77456 44.13% 44.13% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::1 50516 28.78% 72.91% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::2 7423 4.23% 77.14% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::3 3189 1.82% 78.96% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::4 704 0.40% 79.36% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::5 30974 17.65% 97.01% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::6 1193 0.68% 97.69% # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::0 77396 44.12% 44.12% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::1 50499 28.79% 72.90% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::2 7414 4.23% 77.13% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::3 3189 1.82% 78.95% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::4 704 0.40% 79.35% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::5 30975 17.66% 97.00% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::6 1193 0.68% 97.68% # Number of instructions fetched each cycle (Total)
1263,1269c1300,1306
< system.cpu1.fetch.rateDist::total 175517 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.branchRate 0.276995 # Number of branch fetches per cycle
< system.cpu1.fetch.rate 1.527663 # Number of inst fetches per cycle
< system.cpu1.decode.IdleCycles 37188 # Number of cycles decode is idle
< system.cpu1.decode.BlockedCycles 31008 # Number of cycles decode is blocked
< system.cpu1.decode.RunCycles 90874 # Number of cycles decode is running
< system.cpu1.decode.UnblockCycles 6330 # Number of cycles decode is unblocking
---
> system.cpu1.fetch.rateDist::total 175432 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.branchRate 0.277087 # Number of branch fetches per cycle
> system.cpu1.fetch.rate 1.528251 # Number of inst fetches per cycle
> system.cpu1.decode.IdleCycles 37161 # Number of cycles decode is idle
> system.cpu1.decode.BlockedCycles 30981 # Number of cycles decode is blocked
> system.cpu1.decode.RunCycles 90858 # Number of cycles decode is running
> system.cpu1.decode.UnblockCycles 6321 # Number of cycles decode is unblocking
1271c1308
< system.cpu1.decode.DecodedInsts 267842 # Number of instructions handled by decode
---
> system.cpu1.decode.DecodedInsts 267812 # Number of instructions handled by decode
1273,1274c1310,1311
< system.cpu1.rename.IdleCycles 37871 # Number of cycles rename is idle
< system.cpu1.rename.BlockCycles 18552 # Number of cycles rename is blocking
---
> system.cpu1.rename.IdleCycles 37844 # Number of cycles rename is idle
> system.cpu1.rename.BlockCycles 18525 # Number of cycles rename is blocking
1276,1278c1313,1315
< system.cpu1.rename.RunCycles 84813 # Number of cycles rename is running
< system.cpu1.rename.UnblockCycles 12462 # Number of cycles rename is unblocking
< system.cpu1.rename.RenamedInsts 265527 # Number of instructions processed by rename
---
> system.cpu1.rename.RunCycles 84806 # Number of cycles rename is running
> system.cpu1.rename.UnblockCycles 12444 # Number of cycles rename is unblocking
> system.cpu1.rename.RenamedInsts 265497 # Number of instructions processed by rename
1281,1284c1318,1321
< system.cpu1.rename.RenamedOperands 184379 # Number of destination operands rename has renamed
< system.cpu1.rename.RenameLookups 502490 # Number of register rename lookups that rename has made
< system.cpu1.rename.int_rename_lookups 391665 # Number of integer rename lookups
< system.cpu1.rename.CommittedMaps 171551 # Number of HB maps that are committed
---
> system.cpu1.rename.RenamedOperands 184374 # Number of destination operands rename has renamed
> system.cpu1.rename.RenameLookups 502466 # Number of register rename lookups that rename has made
> system.cpu1.rename.int_rename_lookups 391647 # Number of integer rename lookups
> system.cpu1.rename.CommittedMaps 171546 # Number of HB maps that are committed
1288,1295c1325,1332
< system.cpu1.rename.skidInsts 15186 # count of insts added to the skid buffer
< system.cpu1.memDep0.insertedLoads 73774 # Number of loads inserted to the mem dependence unit.
< system.cpu1.memDep0.insertedStores 34232 # Number of stores inserted to the mem dependence unit.
< system.cpu1.memDep0.conflictingLoads 35732 # Number of conflicting loads.
< system.cpu1.memDep0.conflictingStores 29187 # Number of conflicting stores.
< system.cpu1.iq.iqInstsAdded 218298 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu1.iq.iqNonSpecInstsAdded 7639 # Number of non-speculative instructions added to the IQ
< system.cpu1.iq.iqInstsIssued 221677 # Number of instructions issued
---
> system.cpu1.rename.skidInsts 15168 # count of insts added to the skid buffer
> system.cpu1.memDep0.insertedLoads 73767 # Number of loads inserted to the mem dependence unit.
> system.cpu1.memDep0.insertedStores 34233 # Number of stores inserted to the mem dependence unit.
> system.cpu1.memDep0.conflictingLoads 35724 # Number of conflicting loads.
> system.cpu1.memDep0.conflictingStores 29188 # Number of conflicting stores.
> system.cpu1.iq.iqInstsAdded 218285 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu1.iq.iqNonSpecInstsAdded 7630 # Number of non-speculative instructions added to the IQ
> system.cpu1.iq.iqInstsIssued 221655 # Number of instructions issued
1300,1302c1337,1339
< system.cpu1.iq.issued_per_cycle::samples 175517 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::mean 1.262994 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::stdev 1.299330 # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::samples 175432 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::mean 1.263481 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::stdev 1.299438 # Number of insts issued each cycle
1304,1307c1341,1344
< system.cpu1.iq.issued_per_cycle::0 74868 42.66% 42.66% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::1 26303 14.99% 57.64% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::2 34475 19.64% 77.28% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::3 35103 20.00% 97.28% # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::0 74808 42.64% 42.64% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::1 26276 14.98% 57.62% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::2 34476 19.65% 77.27% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::3 35104 20.01% 97.28% # Number of insts issued each cycle
1316c1353
< system.cpu1.iq.issued_per_cycle::total 175517 # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::total 175432 # Number of insts issued each cycle
1352c1389
< system.cpu1.iq.FU_type_0::IntAlu 108767 49.07% 49.07% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::IntAlu 108760 49.07% 49.07% # Type of FU issued
1381,1382c1418,1419
< system.cpu1.iq.FU_type_0::MemRead 79372 35.81% 84.87% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemWrite 33538 15.13% 100.00% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::MemRead 79356 35.80% 84.87% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemWrite 33539 15.13% 100.00% # Type of FU issued
1385,1386c1422,1423
< system.cpu1.iq.FU_type_0::total 221677 # Type of FU issued
< system.cpu1.iq.rate 1.247275 # Inst issue rate
---
> system.cpu1.iq.FU_type_0::total 221655 # Type of FU issued
> system.cpu1.iq.rate 1.247769 # Inst issue rate
1389,1391c1426,1428
< system.cpu1.iq.int_inst_queue_reads 619236 # Number of integer instruction queue reads
< system.cpu1.iq.int_inst_queue_writes 236717 # Number of integer instruction queue writes
< system.cpu1.iq.int_inst_queue_wakeup_accesses 219849 # Number of integer instruction queue wakeup accesses
---
> system.cpu1.iq.int_inst_queue_reads 619107 # Number of integer instruction queue reads
> system.cpu1.iq.int_inst_queue_writes 236695 # Number of integer instruction queue writes
> system.cpu1.iq.int_inst_queue_wakeup_accesses 219827 # Number of integer instruction queue wakeup accesses
1395c1432
< system.cpu1.iq.int_alu_accesses 221943 # Number of integer alu accesses
---
> system.cpu1.iq.int_alu_accesses 221921 # Number of integer alu accesses
1397c1434
< system.cpu1.iew.lsq.thread0.forwLoads 28929 # Number of loads that had data forwarded from stores
---
> system.cpu1.iew.lsq.thread0.forwLoads 28930 # Number of loads that had data forwarded from stores
1411c1448
< system.cpu1.iew.iewDispatchedInsts 262595 # Number of instructions dispatched to IQ
---
> system.cpu1.iew.iewDispatchedInsts 262565 # Number of instructions dispatched to IQ
1413,1414c1450,1451
< system.cpu1.iew.iewDispLoadInsts 73774 # Number of dispatched load instructions
< system.cpu1.iew.iewDispStoreInsts 34232 # Number of dispatched store instructions
---
> system.cpu1.iew.iewDispLoadInsts 73767 # Number of dispatched load instructions
> system.cpu1.iew.iewDispStoreInsts 34233 # Number of dispatched store instructions
1422,1423c1459,1460
< system.cpu1.iew.iewExecutedInsts 220501 # Number of executed instructions
< system.cpu1.iew.iewExecLoadInsts 72766 # Number of load instructions executed
---
> system.cpu1.iew.iewExecutedInsts 220479 # Number of executed instructions
> system.cpu1.iew.iewExecLoadInsts 72759 # Number of load instructions executed
1426,1434c1463,1471
< system.cpu1.iew.exec_nop 36658 # number of nop insts executed
< system.cpu1.iew.exec_refs 106223 # number of memory reference insts executed
< system.cpu1.iew.exec_branches 45902 # Number of branches executed
< system.cpu1.iew.exec_stores 33457 # Number of stores executed
< system.cpu1.iew.exec_rate 1.240659 # Inst execution rate
< system.cpu1.iew.wb_sent 220134 # cumulative count of insts sent to commit
< system.cpu1.iew.wb_count 219849 # cumulative count of insts written-back
< system.cpu1.iew.wb_producers 122957 # num instructions producing a value
< system.cpu1.iew.wb_consumers 127616 # num instructions consuming a value
---
> system.cpu1.iew.exec_nop 36650 # number of nop insts executed
> system.cpu1.iew.exec_refs 106217 # number of memory reference insts executed
> system.cpu1.iew.exec_branches 45894 # Number of branches executed
> system.cpu1.iew.exec_stores 33458 # Number of stores executed
> system.cpu1.iew.exec_rate 1.241149 # Inst execution rate
> system.cpu1.iew.wb_sent 220112 # cumulative count of insts sent to commit
> system.cpu1.iew.wb_count 219827 # cumulative count of insts written-back
> system.cpu1.iew.wb_producers 122951 # num instructions producing a value
> system.cpu1.iew.wb_consumers 127610 # num instructions consuming a value
1436,1437c1473,1474
< system.cpu1.iew.wb_rate 1.236990 # insts written-back per cycle
< system.cpu1.iew.wb_fanout 0.963492 # average fanout of values written-back
---
> system.cpu1.iew.wb_rate 1.237479 # insts written-back per cycle
> system.cpu1.iew.wb_fanout 0.963490 # average fanout of values written-back
1440c1477
< system.cpu1.commit.commitNonSpecStalls 7048 # The number of times commit has been forced to stall to communicate backwards
---
> system.cpu1.commit.commitNonSpecStalls 7039 # The number of times commit has been forced to stall to communicate backwards
1442,1444c1479,1481
< system.cpu1.commit.committed_per_cycle::samples 165400 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::mean 1.513005 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::stdev 1.970213 # Number of insts commited each cycle
---
> system.cpu1.commit.committed_per_cycle::samples 165321 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::mean 1.513546 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::stdev 1.970448 # Number of insts commited each cycle
1446,1451c1483,1488
< system.cpu1.commit.committed_per_cycle::0 73929 44.70% 44.70% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::1 44053 26.63% 71.33% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::2 6103 3.69% 75.02% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::3 7962 4.81% 79.83% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::4 1564 0.95% 80.78% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::5 29500 17.84% 98.62% # Number of insts commited each cycle
---
> system.cpu1.commit.committed_per_cycle::0 73866 44.68% 44.68% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::1 44045 26.64% 71.32% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::2 6103 3.69% 75.01% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::3 7953 4.81% 79.82% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::4 1564 0.95% 80.77% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::5 29501 17.84% 98.62% # Number of insts commited each cycle
1458,1460c1495,1497
< system.cpu1.commit.committed_per_cycle::total 165400 # Number of insts commited each cycle
< system.cpu1.commit.committedInsts 250251 # Number of instructions committed
< system.cpu1.commit.committedOps 250251 # Number of ops (including micro ops) committed
---
> system.cpu1.commit.committed_per_cycle::total 165321 # Number of insts commited each cycle
> system.cpu1.commit.committedInsts 250221 # Number of instructions committed
> system.cpu1.commit.committedOps 250221 # Number of ops (including micro ops) committed
1462,1465c1499,1502
< system.cpu1.commit.refs 104168 # Number of memory references committed
< system.cpu1.commit.loads 71380 # Number of loads committed
< system.cpu1.commit.membars 6331 # Number of memory barriers committed
< system.cpu1.commit.branches 45080 # Number of branches committed
---
> system.cpu1.commit.refs 104162 # Number of memory references committed
> system.cpu1.commit.loads 71373 # Number of loads committed
> system.cpu1.commit.membars 6322 # Number of memory barriers committed
> system.cpu1.commit.branches 45072 # Number of branches committed
1467c1504
< system.cpu1.commit.int_insts 171367 # Number of committed integer instructions.
---
> system.cpu1.commit.int_insts 171353 # Number of committed integer instructions.
1468a1506,1540
> system.cpu1.commit.op_class_0::No_OpClass 35859 14.33% 14.33% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntAlu 103878 41.51% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.85% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemRead 77695 31.05% 86.90% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemWrite 32789 13.10% 100.00% # Class of committed instruction
> system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
> system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
> system.cpu1.commit.op_class_0::total 250221 # Class of committed instruction
1471,1472c1543,1544
< system.cpu1.rob.rob_reads 426586 # The number of ROB reads
< system.cpu1.rob.rob_writes 527520 # The number of ROB writes
---
> system.cpu1.rob.rob_reads 426477 # The number of ROB reads
> system.cpu1.rob.rob_writes 527460 # The number of ROB writes
1474,1484c1546,1556
< system.cpu1.idleCycles 2212 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu1.quiesceCycles 44181 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu1.committedInsts 208053 # Number of Instructions Simulated
< system.cpu1.committedOps 208053 # Number of Ops (including micro ops) Simulated
< system.cpu1.committedInsts_total 208053 # Number of Instructions Simulated
< system.cpu1.cpi 0.854249 # CPI: Cycles Per Instruction
< system.cpu1.cpi_total 0.854249 # CPI: Total CPI of All Threads
< system.cpu1.ipc 1.170619 # IPC: Instructions Per Cycle
< system.cpu1.ipc_total 1.170619 # IPC: Total IPC of All Threads
< system.cpu1.int_regfile_reads 377223 # number of integer regfile reads
< system.cpu1.int_regfile_writes 176309 # number of integer regfile writes
---
> system.cpu1.idleCycles 2209 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu1.quiesceCycles 44103 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu1.committedInsts 208040 # Number of Instructions Simulated
> system.cpu1.committedOps 208040 # Number of Ops (including micro ops) Simulated
> system.cpu1.committedInsts_total 208040 # Number of Instructions Simulated
> system.cpu1.cpi 0.853879 # CPI: Cycles Per Instruction
> system.cpu1.cpi_total 0.853879 # CPI: Total CPI of All Threads
> system.cpu1.ipc 1.171126 # IPC: Instructions Per Cycle
> system.cpu1.ipc_total 1.171126 # IPC: Total IPC of All Threads
> system.cpu1.int_regfile_reads 377205 # number of integer regfile reads
> system.cpu1.int_regfile_writes 176304 # number of integer regfile writes
1486c1558
< system.cpu1.misc_regfile_reads 107781 # number of misc regfile reads
---
> system.cpu1.misc_regfile_reads 107775 # number of misc regfile reads
1489,1490c1561,1562
< system.cpu1.icache.tags.tagsinuse 76.722565 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 21879 # Total number of references to valid blocks.
---
> system.cpu1.icache.tags.tagsinuse 76.769709 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 21861 # Total number of references to valid blocks.
1492c1564
< system.cpu1.icache.tags.avg_refs 51.119159 # Average number of references to valid blocks.
---
> system.cpu1.icache.tags.avg_refs 51.077103 # Average number of references to valid blocks.
1494,1496c1566,1568
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.722565 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149849 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.149849 # Average percentage of cache occupancy
---
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.769709 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149941 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.149941 # Average percentage of cache occupancy
1501,1508c1573,1580
< system.cpu1.icache.tags.tag_accesses 22782 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 22782 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 21879 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 21879 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 21879 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 21879 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 21879 # number of overall hits
< system.cpu1.icache.overall_hits::total 21879 # number of overall hits
---
> system.cpu1.icache.tags.tag_accesses 22764 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 22764 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 21861 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 21861 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 21861 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 21861 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 21861 # number of overall hits
> system.cpu1.icache.overall_hits::total 21861 # number of overall hits
1515,1538c1587,1610
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7157495 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 7157495 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 7157495 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 7157495 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 7157495 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 7157495 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 22354 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 22354 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 22354 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 22354 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 22354 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 22354 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.021249 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.021249 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.021249 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.021249 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.021249 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.021249 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15068.410526 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 15068.410526 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15068.410526 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 15068.410526 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15068.410526 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 15068.410526 # average overall miss latency
---
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7146245 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 7146245 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 7146245 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 7146245 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 7146245 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 7146245 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 22336 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 22336 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 22336 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 22336 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 22336 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 22336 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.021266 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.021266 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.021266 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.021266 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.021266 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.021266 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15044.726316 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 15044.726316 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15044.726316 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 15044.726316 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15044.726316 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 15044.726316 # average overall miss latency
1559,1576c1631,1648
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5706004 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 5706004 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5706004 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 5706004 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5706004 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 5706004 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019146 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019146 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019146 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.019146 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019146 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.019146 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13331.785047 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13331.785047 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13331.785047 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 13331.785047 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13331.785047 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 13331.785047 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5694254 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 5694254 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5694254 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 5694254 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5694254 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 5694254 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019162 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019162 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019162 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.019162 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019162 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.019162 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13304.331776 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13304.331776 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13304.331776 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 13304.331776 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13304.331776 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 13304.331776 # average overall mshr miss latency
1579,1580c1651,1652
< system.cpu1.dcache.tags.tagsinuse 23.630187 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 38790 # Total number of references to valid blocks.
---
> system.cpu1.dcache.tags.tagsinuse 23.645460 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 38791 # Total number of references to valid blocks.
1582c1654
< system.cpu1.dcache.tags.avg_refs 1385.357143 # Average number of references to valid blocks.
---
> system.cpu1.dcache.tags.avg_refs 1385.392857 # Average number of references to valid blocks.
1584,1586c1656,1658
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.630187 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.046153 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.046153 # Average percentage of cache occupancy
---
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.645460 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.046183 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.046183 # Average percentage of cache occupancy
1590,1595c1662,1667
< system.cpu1.dcache.tags.tag_accesses 306681 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 306681 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 43485 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 43485 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 32585 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 32585 # number of WriteReq hits
---
> system.cpu1.dcache.tags.tag_accesses 306653 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 306653 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 43477 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 43477 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 32586 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 32586 # number of WriteReq hits
1598,1601c1670,1673
< system.cpu1.dcache.demand_hits::cpu1.data 76070 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 76070 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 76070 # number of overall hits
< system.cpu1.dcache.overall_hits::total 76070 # number of overall hits
---
> system.cpu1.dcache.demand_hits::cpu1.data 76063 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 76063 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 76063 # number of overall hits
> system.cpu1.dcache.overall_hits::total 76063 # number of overall hits
1612,1613c1684,1685
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4179135 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 4179135 # number of ReadReq miss cycles
---
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4177635 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 4177635 # number of ReadReq miss cycles
1618,1625c1690,1697
< system.cpu1.dcache.demand_miss_latency::cpu1.data 6942896 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 6942896 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 6942896 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 6942896 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 43821 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 43821 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 32717 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 32717 # number of WriteReq accesses(hits+misses)
---
> system.cpu1.dcache.demand_miss_latency::cpu1.data 6941396 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 6941396 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 6941396 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 6941396 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 43813 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 43813 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 32718 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 32718 # number of WriteReq accesses(hits+misses)
1628,1635c1700,1707
< system.cpu1.dcache.demand_accesses::cpu1.data 76538 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 76538 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 76538 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 76538 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.007668 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.007668 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004035 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.004035 # miss rate for WriteReq accesses
---
> system.cpu1.dcache.demand_accesses::cpu1.data 76531 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 76531 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 76531 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 76531 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.007669 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.007669 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004034 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.004034 # miss rate for WriteReq accesses
1642,1643c1714,1715
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12437.901786 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 12437.901786 # average ReadReq miss latency
---
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12433.437500 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 12433.437500 # average ReadReq miss latency
1648,1651c1720,1723
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14835.247863 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 14835.247863 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14835.247863 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 14835.247863 # average overall miss latency
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14832.042735 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 14832.042735 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14832.042735 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 14832.042735 # average overall miss latency
1678,1679c1750,1751
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1078019 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1078019 # number of ReadReq MSHR miss cycles
---
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1076519 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1076519 # number of ReadReq MSHR miss cycles
1684,1687c1756,1759
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2391758 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 2391758 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2391758 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 2391758 # number of overall MSHR miss cycles
---
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2390258 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 2390258 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2390258 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 2390258 # number of overall MSHR miss cycles
1698,1699c1770,1771
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6822.905063 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6822.905063 # average ReadReq mshr miss latency
---
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6813.411392 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6813.411392 # average ReadReq mshr miss latency
1704,1707c1776,1779
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9199.069231 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9199.069231 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9199.069231 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9199.069231 # average overall mshr miss latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9193.300000 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9193.300000 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9193.300000 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9193.300000 # average overall mshr miss latency
1709,1710c1781,1782
< system.cpu2.branchPred.lookups 47736 # Number of BP lookups
< system.cpu2.branchPred.condPredicted 45029 # Number of conditional branches predicted
---
> system.cpu2.branchPred.lookups 47728 # Number of BP lookups
> system.cpu2.branchPred.condPredicted 45021 # Number of conditional branches predicted
1712,1713c1784,1785
< system.cpu2.branchPred.BTBLookups 41576 # Number of BTB lookups
< system.cpu2.branchPred.BTBHits 40869 # Number of BTB hits
---
> system.cpu2.branchPred.BTBLookups 41568 # Number of BTB lookups
> system.cpu2.branchPred.BTBHits 40861 # Number of BTB hits
1715c1787
< system.cpu2.branchPred.BTBHitPct 98.299500 # BTB Hit Percentage
---
> system.cpu2.branchPred.BTBHitPct 98.299172 # BTB Hit Percentage
1718c1790
< system.cpu2.numCycles 177364 # number of cpu cycles simulated
---
> system.cpu2.numCycles 177276 # number of cpu cycles simulated
1722,1725c1794,1797
< system.cpu2.fetch.Insts 263253 # Number of instructions fetch has processed
< system.cpu2.fetch.Branches 47736 # Number of branches that fetch encountered
< system.cpu2.fetch.predictedBranches 41551 # Number of branches that fetch has predicted taken
< system.cpu2.fetch.Cycles 94921 # Number of cycles fetch has run and was not squashing or blocked
---
> system.cpu2.fetch.Insts 263204 # Number of instructions fetch has processed
> system.cpu2.fetch.Branches 47728 # Number of branches that fetch encountered
> system.cpu2.fetch.predictedBranches 41543 # Number of branches that fetch has predicted taken
> system.cpu2.fetch.Cycles 94904 # Number of cycles fetch has run and was not squashing or blocked
1727c1799
< system.cpu2.fetch.BlockedCycles 35042 # Number of cycles fetch has spent blocked
---
> system.cpu2.fetch.BlockedCycles 35041 # Number of cycles fetch has spent blocked
1729c1801
< system.cpu2.fetch.NoActiveThreadStallCycles 7755 # Number of stall cycles due to no active thread to fetch from
---
> system.cpu2.fetch.NoActiveThreadStallCycles 7749 # Number of stall cycles due to no active thread to fetch from
1733,1735c1805,1807
< system.cpu2.fetch.rateDist::samples 171818 # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::mean 1.532162 # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::stdev 2.088026 # Number of instructions fetched each cycle (Total)
---
> system.cpu2.fetch.rateDist::samples 171794 # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::mean 1.532091 # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::stdev 2.088011 # Number of instructions fetched each cycle (Total)
1737,1738c1809,1810
< system.cpu2.fetch.rateDist::0 76897 44.75% 44.75% # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::1 48842 28.43% 73.18% # Number of instructions fetched each cycle (Total)
---
> system.cpu2.fetch.rateDist::0 76890 44.76% 44.76% # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::1 48833 28.43% 73.18% # Number of instructions fetched each cycle (Total)
1742,1743c1814,1815
< system.cpu2.fetch.rateDist::5 29853 17.37% 96.97% # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.rateDist::6 1160 0.68% 97.65% # Number of instructions fetched each cycle (Total)
---
> system.cpu2.fetch.rateDist::5 29845 17.37% 96.97% # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.rateDist::6 1160 0.68% 97.64% # Number of instructions fetched each cycle (Total)
1749,1751c1821,1823
< system.cpu2.fetch.rateDist::total 171818 # Number of instructions fetched each cycle (Total)
< system.cpu2.fetch.branchRate 0.269141 # Number of branch fetches per cycle
< system.cpu2.fetch.rate 1.484253 # Number of inst fetches per cycle
---
> system.cpu2.fetch.rateDist::total 171794 # Number of instructions fetched each cycle (Total)
> system.cpu2.fetch.branchRate 0.269230 # Number of branch fetches per cycle
> system.cpu2.fetch.rate 1.484713 # Number of inst fetches per cycle
1753,1754c1825,1826
< system.cpu2.decode.BlockedCycles 30807 # Number of cycles decode is blocked
< system.cpu2.decode.RunCycles 88098 # Number of cycles decode is running
---
> system.cpu2.decode.BlockedCycles 30806 # Number of cycles decode is blocked
> system.cpu2.decode.RunCycles 88081 # Number of cycles decode is running
1757c1829
< system.cpu2.decode.DecodedInsts 259780 # Number of instructions handled by decode
---
> system.cpu2.decode.DecodedInsts 259729 # Number of instructions handled by decode
1760c1832
< system.cpu2.rename.BlockCycles 17719 # Number of cycles rename is blocking
---
> system.cpu2.rename.BlockCycles 17718 # Number of cycles rename is blocking
1762c1834
< system.cpu2.rename.RunCycles 82368 # Number of cycles rename is running
---
> system.cpu2.rename.RunCycles 82351 # Number of cycles rename is running
1764c1836
< system.cpu2.rename.RenamedInsts 257506 # Number of instructions processed by rename
---
> system.cpu2.rename.RenamedInsts 257457 # Number of instructions processed by rename
1766,1769c1838,1841
< system.cpu2.rename.RenamedOperands 179566 # Number of destination operands rename has renamed
< system.cpu2.rename.RenameLookups 487666 # Number of register rename lookups that rename has made
< system.cpu2.rename.int_rename_lookups 380584 # Number of integer rename lookups
< system.cpu2.rename.CommittedMaps 166435 # Number of HB maps that are committed
---
> system.cpu2.rename.RenamedOperands 179534 # Number of destination operands rename has renamed
> system.cpu2.rename.RenameLookups 487570 # Number of register rename lookups that rename has made
> system.cpu2.rename.int_rename_lookups 380512 # Number of integer rename lookups
> system.cpu2.rename.CommittedMaps 166403 # Number of HB maps that are committed
1774,1778c1846,1850
< system.cpu2.memDep0.insertedLoads 71199 # Number of loads inserted to the mem dependence unit.
< system.cpu2.memDep0.insertedStores 33061 # Number of stores inserted to the mem dependence unit.
< system.cpu2.memDep0.conflictingLoads 34327 # Number of conflicting loads.
< system.cpu2.memDep0.conflictingStores 28016 # Number of conflicting stores.
< system.cpu2.iq.iqInstsAdded 212074 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu2.memDep0.insertedLoads 71183 # Number of loads inserted to the mem dependence unit.
> system.cpu2.memDep0.insertedStores 33053 # Number of stores inserted to the mem dependence unit.
> system.cpu2.memDep0.conflictingLoads 34319 # Number of conflicting loads.
> system.cpu2.memDep0.conflictingStores 28008 # Number of conflicting stores.
> system.cpu2.iq.iqInstsAdded 212034 # Number of instructions added to the IQ (excludes non-spec)
1780c1852
< system.cpu2.iq.iqInstsIssued 214906 # Number of instructions issued
---
> system.cpu2.iq.iqInstsIssued 214866 # Number of instructions issued
1785,1787c1857,1859
< system.cpu2.iq.issued_per_cycle::samples 171818 # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::mean 1.250777 # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::stdev 1.303706 # Number of insts issued each cycle
---
> system.cpu2.iq.issued_per_cycle::samples 171794 # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::mean 1.250719 # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::stdev 1.303691 # Number of insts issued each cycle
1789,1794c1861,1866
< system.cpu2.iq.issued_per_cycle::0 74494 43.36% 43.36% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::1 25338 14.75% 58.10% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::2 33284 19.37% 77.48% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::3 33913 19.74% 97.21% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::4 3241 1.89% 99.10% # Number of insts issued each cycle
< system.cpu2.iq.issued_per_cycle::5 1161 0.68% 99.77% # Number of insts issued each cycle
---
> system.cpu2.iq.issued_per_cycle::0 74486 43.36% 43.36% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::1 25336 14.75% 58.11% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::2 33280 19.37% 77.48% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::3 33902 19.73% 97.21% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::4 3243 1.89% 99.10% # Number of insts issued each cycle
> system.cpu2.iq.issued_per_cycle::5 1160 0.68% 99.77% # Number of insts issued each cycle
1801c1873
< system.cpu2.iq.issued_per_cycle::total 171818 # Number of insts issued each cycle
---
> system.cpu2.iq.issued_per_cycle::total 171794 # Number of insts issued each cycle
1837c1909
< system.cpu2.iq.FU_type_0::IntAlu 106166 49.40% 49.40% # Type of FU issued
---
> system.cpu2.iq.FU_type_0::IntAlu 106150 49.40% 49.40% # Type of FU issued
1866,1867c1938,1939
< system.cpu2.iq.FU_type_0::MemRead 76377 35.54% 84.94% # Type of FU issued
< system.cpu2.iq.FU_type_0::MemWrite 32363 15.06% 100.00% # Type of FU issued
---
> system.cpu2.iq.FU_type_0::MemRead 76361 35.54% 84.94% # Type of FU issued
> system.cpu2.iq.FU_type_0::MemWrite 32355 15.06% 100.00% # Type of FU issued
1870,1871c1942,1943
< system.cpu2.iq.FU_type_0::total 214906 # Type of FU issued
< system.cpu2.iq.rate 1.211666 # Inst issue rate
---
> system.cpu2.iq.FU_type_0::total 214866 # Type of FU issued
> system.cpu2.iq.rate 1.212042 # Inst issue rate
1874,1876c1946,1948
< system.cpu2.iq.int_inst_queue_reads 602011 # Number of integer instruction queue reads
< system.cpu2.iq.int_inst_queue_writes 230706 # Number of integer instruction queue writes
< system.cpu2.iq.int_inst_queue_wakeup_accesses 213087 # Number of integer instruction queue wakeup accesses
---
> system.cpu2.iq.int_inst_queue_reads 601907 # Number of integer instruction queue reads
> system.cpu2.iq.int_inst_queue_writes 230666 # Number of integer instruction queue writes
> system.cpu2.iq.int_inst_queue_wakeup_accesses 213047 # Number of integer instruction queue wakeup accesses
1880c1952
< system.cpu2.iq.int_alu_accesses 215181 # Number of integer alu accesses
---
> system.cpu2.iq.int_alu_accesses 215141 # Number of integer alu accesses
1882c1954
< system.cpu2.iew.lsq.thread0.forwLoads 27728 # Number of loads that had data forwarded from stores
---
> system.cpu2.iew.lsq.thread0.forwLoads 27720 # Number of loads that had data forwarded from stores
1894c1966
< system.cpu2.iew.iewBlockCycles 917 # Number of cycles IEW is blocking
---
> system.cpu2.iew.iewBlockCycles 916 # Number of cycles IEW is blocking
1896c1968
< system.cpu2.iew.iewDispatchedInsts 254656 # Number of instructions dispatched to IQ
---
> system.cpu2.iew.iewDispatchedInsts 254607 # Number of instructions dispatched to IQ
1898,1899c1970,1971
< system.cpu2.iew.iewDispLoadInsts 71199 # Number of dispatched load instructions
< system.cpu2.iew.iewDispStoreInsts 33061 # Number of dispatched store instructions
---
> system.cpu2.iew.iewDispLoadInsts 71183 # Number of dispatched load instructions
> system.cpu2.iew.iewDispStoreInsts 33053 # Number of dispatched store instructions
1907,1908c1979,1980
< system.cpu2.iew.iewExecutedInsts 213756 # Number of executed instructions
< system.cpu2.iew.iewExecLoadInsts 70098 # Number of load instructions executed
---
> system.cpu2.iew.iewExecutedInsts 213716 # Number of executed instructions
> system.cpu2.iew.iewExecLoadInsts 70082 # Number of load instructions executed
1911,1919c1983,1991
< system.cpu2.iew.exec_nop 35212 # number of nop insts executed
< system.cpu2.iew.exec_refs 102378 # number of memory reference insts executed
< system.cpu2.iew.exec_branches 44395 # Number of branches executed
< system.cpu2.iew.exec_stores 32280 # Number of stores executed
< system.cpu2.iew.exec_rate 1.205183 # Inst execution rate
< system.cpu2.iew.wb_sent 213374 # cumulative count of insts sent to commit
< system.cpu2.iew.wb_count 213087 # cumulative count of insts written-back
< system.cpu2.iew.wb_producers 119148 # num instructions producing a value
< system.cpu2.iew.wb_consumers 123853 # num instructions consuming a value
---
> system.cpu2.iew.exec_nop 35203 # number of nop insts executed
> system.cpu2.iew.exec_refs 102354 # number of memory reference insts executed
> system.cpu2.iew.exec_branches 44387 # Number of branches executed
> system.cpu2.iew.exec_stores 32272 # Number of stores executed
> system.cpu2.iew.exec_rate 1.205555 # Inst execution rate
> system.cpu2.iew.wb_sent 213334 # cumulative count of insts sent to commit
> system.cpu2.iew.wb_count 213047 # cumulative count of insts written-back
> system.cpu2.iew.wb_producers 119124 # num instructions producing a value
> system.cpu2.iew.wb_consumers 123829 # num instructions consuming a value
1921,1922c1993,1994
< system.cpu2.iew.wb_rate 1.201411 # insts written-back per cycle
< system.cpu2.iew.wb_fanout 0.962011 # average fanout of values written-back
---
> system.cpu2.iew.wb_rate 1.201781 # insts written-back per cycle
> system.cpu2.iew.wb_fanout 0.962004 # average fanout of values written-back
1924c1996
< system.cpu2.commit.commitSquashedInsts 12898 # The number of squashed insts skipped by commit
---
> system.cpu2.commit.commitSquashedInsts 12897 # The number of squashed insts skipped by commit
1927,1929c1999,2001
< system.cpu2.commit.committed_per_cycle::samples 161617 # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::mean 1.495857 # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::stdev 1.966536 # Number of insts commited each cycle
---
> system.cpu2.commit.committed_per_cycle::samples 161599 # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::mean 1.495727 # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::stdev 1.966465 # Number of insts commited each cycle
1931,1932c2003,2004
< system.cpu2.commit.committed_per_cycle::0 73208 45.30% 45.30% # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::1 42532 26.32% 71.61% # Number of insts commited each cycle
---
> system.cpu2.commit.committed_per_cycle::0 73205 45.30% 45.30% # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::1 42525 26.32% 71.62% # Number of insts commited each cycle
1934c2006
< system.cpu2.commit.committed_per_cycle::3 7628 4.72% 80.10% # Number of insts commited each cycle
---
> system.cpu2.commit.committed_per_cycle::3 7628 4.72% 80.11% # Number of insts commited each cycle
1936,1937c2008,2009
< system.cpu2.commit.committed_per_cycle::5 28303 17.51% 98.58% # Number of insts commited each cycle
< system.cpu2.commit.committed_per_cycle::6 470 0.29% 98.87% # Number of insts commited each cycle
---
> system.cpu2.commit.committed_per_cycle::5 28296 17.51% 98.58% # Number of insts commited each cycle
> system.cpu2.commit.committed_per_cycle::6 469 0.29% 98.87% # Number of insts commited each cycle
1943,1945c2015,2017
< system.cpu2.commit.committed_per_cycle::total 161617 # Number of insts commited each cycle
< system.cpu2.commit.committedInsts 241756 # Number of instructions committed
< system.cpu2.commit.committedOps 241756 # Number of ops (including micro ops) committed
---
> system.cpu2.commit.committed_per_cycle::total 161599 # Number of insts commited each cycle
> system.cpu2.commit.committedInsts 241708 # Number of instructions committed
> system.cpu2.commit.committedOps 241708 # Number of ops (including micro ops) committed
1947,1948c2019,2020
< system.cpu2.commit.refs 100248 # Number of memory references committed
< system.cpu2.commit.loads 68656 # Number of loads committed
---
> system.cpu2.commit.refs 100224 # Number of memory references committed
> system.cpu2.commit.loads 68640 # Number of loads committed
1950c2022
< system.cpu2.commit.branches 43556 # Number of branches committed
---
> system.cpu2.commit.branches 43548 # Number of branches committed
1952c2024
< system.cpu2.commit.int_insts 165922 # Number of committed integer instructions.
---
> system.cpu2.commit.int_insts 165890 # Number of committed integer instructions.
1953a2026,2060
> system.cpu2.commit.op_class_0::No_OpClass 34333 14.20% 14.20% # Class of committed instruction
> system.cpu2.commit.op_class_0::IntAlu 101148 41.85% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::IntMult 0 0.00% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::IntDiv 0 0.00% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::FloatMult 0 0.00% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdMult 0 0.00% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdShift 0 0.00% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.05% # Class of committed instruction
> system.cpu2.commit.op_class_0::MemRead 74643 30.88% 86.93% # Class of committed instruction
> system.cpu2.commit.op_class_0::MemWrite 31584 13.07% 100.00% # Class of committed instruction
> system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
> system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
> system.cpu2.commit.op_class_0::total 241708 # Class of committed instruction
1956,1957c2063,2064
< system.cpu2.rob.rob_reads 414862 # The number of ROB reads
< system.cpu2.rob.rob_writes 511759 # The number of ROB writes
---
> system.cpu2.rob.rob_reads 414795 # The number of ROB reads
> system.cpu2.rob.rob_writes 511661 # The number of ROB writes
1959,1969c2066,2076
< system.cpu2.idleCycles 5546 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu2.quiesceCycles 44546 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu2.committedInsts 201412 # Number of Instructions Simulated
< system.cpu2.committedOps 201412 # Number of Ops (including micro ops) Simulated
< system.cpu2.committedInsts_total 201412 # Number of Instructions Simulated
< system.cpu2.cpi 0.880603 # CPI: Cycles Per Instruction
< system.cpu2.cpi_total 0.880603 # CPI: Total CPI of All Threads
< system.cpu2.ipc 1.135586 # IPC: Instructions Per Cycle
< system.cpu2.ipc_total 1.135586 # IPC: Total IPC of All Threads
< system.cpu2.int_regfile_reads 365854 # number of integer regfile reads
< system.cpu2.int_regfile_writes 171387 # number of integer regfile writes
---
> system.cpu2.idleCycles 5482 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu2.quiesceCycles 44468 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu2.committedInsts 201372 # Number of Instructions Simulated
> system.cpu2.committedOps 201372 # Number of Ops (including micro ops) Simulated
> system.cpu2.committedInsts_total 201372 # Number of Instructions Simulated
> system.cpu2.cpi 0.880341 # CPI: Cycles Per Instruction
> system.cpu2.cpi_total 0.880341 # CPI: Total CPI of All Threads
> system.cpu2.ipc 1.135924 # IPC: Instructions Per Cycle
> system.cpu2.ipc_total 1.135924 # IPC: Total IPC of All Threads
> system.cpu2.int_regfile_reads 365782 # number of integer regfile reads
> system.cpu2.int_regfile_writes 171355 # number of integer regfile writes
1971c2078
< system.cpu2.misc_regfile_reads 103940 # number of misc regfile reads
---
> system.cpu2.misc_regfile_reads 103916 # number of misc regfile reads
1974c2081
< system.cpu2.icache.tags.tagsinuse 82.194037 # Cycle average of tags in use
---
> system.cpu2.icache.tags.tagsinuse 82.236907 # Cycle average of tags in use
1979,1981c2086,2088
< system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.194037 # Average occupied blocks per requestor
< system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160535 # Average percentage of cache occupancy
< system.cpu2.icache.tags.occ_percent::total 0.160535 # Average percentage of cache occupancy
---
> system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.236907 # Average occupied blocks per requestor
> system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160619 # Average percentage of cache occupancy
> system.cpu2.icache.tags.occ_percent::total 0.160619 # Average percentage of cache occupancy
2000,2005c2107,2112
< system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11553239 # number of ReadReq miss cycles
< system.cpu2.icache.ReadReq_miss_latency::total 11553239 # number of ReadReq miss cycles
< system.cpu2.icache.demand_miss_latency::cpu2.inst 11553239 # number of demand (read+write) miss cycles
< system.cpu2.icache.demand_miss_latency::total 11553239 # number of demand (read+write) miss cycles
< system.cpu2.icache.overall_miss_latency::cpu2.inst 11553239 # number of overall miss cycles
< system.cpu2.icache.overall_miss_latency::total 11553239 # number of overall miss cycles
---
> system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11521239 # number of ReadReq miss cycles
> system.cpu2.icache.ReadReq_miss_latency::total 11521239 # number of ReadReq miss cycles
> system.cpu2.icache.demand_miss_latency::cpu2.inst 11521239 # number of demand (read+write) miss cycles
> system.cpu2.icache.demand_miss_latency::total 11521239 # number of demand (read+write) miss cycles
> system.cpu2.icache.overall_miss_latency::cpu2.inst 11521239 # number of overall miss cycles
> system.cpu2.icache.overall_miss_latency::total 11521239 # number of overall miss cycles
2018,2023c2125,2130
< system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23723.283368 # average ReadReq miss latency
< system.cpu2.icache.ReadReq_avg_miss_latency::total 23723.283368 # average ReadReq miss latency
< system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23723.283368 # average overall miss latency
< system.cpu2.icache.demand_avg_miss_latency::total 23723.283368 # average overall miss latency
< system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23723.283368 # average overall miss latency
< system.cpu2.icache.overall_avg_miss_latency::total 23723.283368 # average overall miss latency
---
> system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23657.574949 # average ReadReq miss latency
> system.cpu2.icache.ReadReq_avg_miss_latency::total 23657.574949 # average ReadReq miss latency
> system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23657.574949 # average overall miss latency
> system.cpu2.icache.demand_avg_miss_latency::total 23657.574949 # average overall miss latency
> system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23657.574949 # average overall miss latency
> system.cpu2.icache.overall_avg_miss_latency::total 23657.574949 # average overall miss latency
2044,2049c2151,2156
< system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9258007 # number of ReadReq MSHR miss cycles
< system.cpu2.icache.ReadReq_mshr_miss_latency::total 9258007 # number of ReadReq MSHR miss cycles
< system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9258007 # number of demand (read+write) MSHR miss cycles
< system.cpu2.icache.demand_mshr_miss_latency::total 9258007 # number of demand (read+write) MSHR miss cycles
< system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9258007 # number of overall MSHR miss cycles
< system.cpu2.icache.overall_mshr_miss_latency::total 9258007 # number of overall MSHR miss cycles
---
> system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9226007 # number of ReadReq MSHR miss cycles
> system.cpu2.icache.ReadReq_mshr_miss_latency::total 9226007 # number of ReadReq MSHR miss cycles
> system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9226007 # number of demand (read+write) MSHR miss cycles
> system.cpu2.icache.demand_mshr_miss_latency::total 9226007 # number of demand (read+write) MSHR miss cycles
> system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9226007 # number of overall MSHR miss cycles
> system.cpu2.icache.overall_mshr_miss_latency::total 9226007 # number of overall MSHR miss cycles
2056,2061c2163,2168
< system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21783.545882 # average ReadReq mshr miss latency
< system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21783.545882 # average ReadReq mshr miss latency
< system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21783.545882 # average overall mshr miss latency
< system.cpu2.icache.demand_avg_mshr_miss_latency::total 21783.545882 # average overall mshr miss latency
< system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21783.545882 # average overall mshr miss latency
< system.cpu2.icache.overall_avg_mshr_miss_latency::total 21783.545882 # average overall mshr miss latency
---
> system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21708.251765 # average ReadReq mshr miss latency
> system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21708.251765 # average ReadReq mshr miss latency
> system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21708.251765 # average overall mshr miss latency
> system.cpu2.icache.demand_avg_mshr_miss_latency::total 21708.251765 # average overall mshr miss latency
> system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21708.251765 # average overall mshr miss latency
> system.cpu2.icache.overall_avg_mshr_miss_latency::total 21708.251765 # average overall mshr miss latency
2064,2065c2171,2172
< system.cpu2.dcache.tags.tagsinuse 26.156826 # Cycle average of tags in use
< system.cpu2.dcache.tags.total_refs 37738 # Total number of references to valid blocks.
---
> system.cpu2.dcache.tags.tagsinuse 26.169210 # Cycle average of tags in use
> system.cpu2.dcache.tags.total_refs 37730 # Total number of references to valid blocks.
2067c2174
< system.cpu2.dcache.tags.avg_refs 1301.310345 # Average number of references to valid blocks.
---
> system.cpu2.dcache.tags.avg_refs 1301.034483 # Average number of references to valid blocks.
2069,2071c2176,2178
< system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.156826 # Average occupied blocks per requestor
< system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051088 # Average percentage of cache occupancy
< system.cpu2.dcache.tags.occ_percent::total 0.051088 # Average percentage of cache occupancy
---
> system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.169210 # Average occupied blocks per requestor
> system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051112 # Average percentage of cache occupancy
> system.cpu2.dcache.tags.occ_percent::total 0.051112 # Average percentage of cache occupancy
2076,2081c2183,2188
< system.cpu2.dcache.tags.tag_accesses 296038 # Number of tag accesses
< system.cpu2.dcache.tags.data_accesses 296038 # Number of data accesses
< system.cpu2.dcache.ReadReq_hits::cpu2.data 42011 # number of ReadReq hits
< system.cpu2.dcache.ReadReq_hits::total 42011 # number of ReadReq hits
< system.cpu2.dcache.WriteReq_hits::cpu2.data 31379 # number of WriteReq hits
< system.cpu2.dcache.WriteReq_hits::total 31379 # number of WriteReq hits
---
> system.cpu2.dcache.tags.tag_accesses 295974 # Number of tag accesses
> system.cpu2.dcache.tags.data_accesses 295974 # Number of data accesses
> system.cpu2.dcache.ReadReq_hits::cpu2.data 42003 # number of ReadReq hits
> system.cpu2.dcache.ReadReq_hits::total 42003 # number of ReadReq hits
> system.cpu2.dcache.WriteReq_hits::cpu2.data 31371 # number of WriteReq hits
> system.cpu2.dcache.WriteReq_hits::total 31371 # number of WriteReq hits
2084,2087c2191,2194
< system.cpu2.dcache.demand_hits::cpu2.data 73390 # number of demand (read+write) hits
< system.cpu2.dcache.demand_hits::total 73390 # number of demand (read+write) hits
< system.cpu2.dcache.overall_hits::cpu2.data 73390 # number of overall hits
< system.cpu2.dcache.overall_hits::total 73390 # number of overall hits
---
> system.cpu2.dcache.demand_hits::cpu2.data 73374 # number of demand (read+write) hits
> system.cpu2.dcache.demand_hits::total 73374 # number of demand (read+write) hits
> system.cpu2.dcache.overall_hits::cpu2.data 73374 # number of overall hits
> system.cpu2.dcache.overall_hits::total 73374 # number of overall hits
2098,2099c2205,2206
< system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5441573 # number of ReadReq miss cycles
< system.cpu2.dcache.ReadReq_miss_latency::total 5441573 # number of ReadReq miss cycles
---
> system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5435581 # number of ReadReq miss cycles
> system.cpu2.dcache.ReadReq_miss_latency::total 5435581 # number of ReadReq miss cycles
2104,2111c2211,2218
< system.cpu2.dcache.demand_miss_latency::cpu2.data 8580583 # number of demand (read+write) miss cycles
< system.cpu2.dcache.demand_miss_latency::total 8580583 # number of demand (read+write) miss cycles
< system.cpu2.dcache.overall_miss_latency::cpu2.data 8580583 # number of overall miss cycles
< system.cpu2.dcache.overall_miss_latency::total 8580583 # number of overall miss cycles
< system.cpu2.dcache.ReadReq_accesses::cpu2.data 42353 # number of ReadReq accesses(hits+misses)
< system.cpu2.dcache.ReadReq_accesses::total 42353 # number of ReadReq accesses(hits+misses)
< system.cpu2.dcache.WriteReq_accesses::cpu2.data 31519 # number of WriteReq accesses(hits+misses)
< system.cpu2.dcache.WriteReq_accesses::total 31519 # number of WriteReq accesses(hits+misses)
---
> system.cpu2.dcache.demand_miss_latency::cpu2.data 8574591 # number of demand (read+write) miss cycles
> system.cpu2.dcache.demand_miss_latency::total 8574591 # number of demand (read+write) miss cycles
> system.cpu2.dcache.overall_miss_latency::cpu2.data 8574591 # number of overall miss cycles
> system.cpu2.dcache.overall_miss_latency::total 8574591 # number of overall miss cycles
> system.cpu2.dcache.ReadReq_accesses::cpu2.data 42345 # number of ReadReq accesses(hits+misses)
> system.cpu2.dcache.ReadReq_accesses::total 42345 # number of ReadReq accesses(hits+misses)
> system.cpu2.dcache.WriteReq_accesses::cpu2.data 31511 # number of WriteReq accesses(hits+misses)
> system.cpu2.dcache.WriteReq_accesses::total 31511 # number of WriteReq accesses(hits+misses)
2114,2121c2221,2228
< system.cpu2.dcache.demand_accesses::cpu2.data 73872 # number of demand (read+write) accesses
< system.cpu2.dcache.demand_accesses::total 73872 # number of demand (read+write) accesses
< system.cpu2.dcache.overall_accesses::cpu2.data 73872 # number of overall (read+write) accesses
< system.cpu2.dcache.overall_accesses::total 73872 # number of overall (read+write) accesses
< system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.008075 # miss rate for ReadReq accesses
< system.cpu2.dcache.ReadReq_miss_rate::total 0.008075 # miss rate for ReadReq accesses
< system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004442 # miss rate for WriteReq accesses
< system.cpu2.dcache.WriteReq_miss_rate::total 0.004442 # miss rate for WriteReq accesses
---
> system.cpu2.dcache.demand_accesses::cpu2.data 73856 # number of demand (read+write) accesses
> system.cpu2.dcache.demand_accesses::total 73856 # number of demand (read+write) accesses
> system.cpu2.dcache.overall_accesses::cpu2.data 73856 # number of overall (read+write) accesses
> system.cpu2.dcache.overall_accesses::total 73856 # number of overall (read+write) accesses
> system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.008077 # miss rate for ReadReq accesses
> system.cpu2.dcache.ReadReq_miss_rate::total 0.008077 # miss rate for ReadReq accesses
> system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004443 # miss rate for WriteReq accesses
> system.cpu2.dcache.WriteReq_miss_rate::total 0.004443 # miss rate for WriteReq accesses
2124,2129c2231,2236
< system.cpu2.dcache.demand_miss_rate::cpu2.data 0.006525 # miss rate for demand accesses
< system.cpu2.dcache.demand_miss_rate::total 0.006525 # miss rate for demand accesses
< system.cpu2.dcache.overall_miss_rate::cpu2.data 0.006525 # miss rate for overall accesses
< system.cpu2.dcache.overall_miss_rate::total 0.006525 # miss rate for overall accesses
< system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15911.032164 # average ReadReq miss latency
< system.cpu2.dcache.ReadReq_avg_miss_latency::total 15911.032164 # average ReadReq miss latency
---
> system.cpu2.dcache.demand_miss_rate::cpu2.data 0.006526 # miss rate for demand accesses
> system.cpu2.dcache.demand_miss_rate::total 0.006526 # miss rate for demand accesses
> system.cpu2.dcache.overall_miss_rate::cpu2.data 0.006526 # miss rate for overall accesses
> system.cpu2.dcache.overall_miss_rate::total 0.006526 # miss rate for overall accesses
> system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15893.511696 # average ReadReq miss latency
> system.cpu2.dcache.ReadReq_avg_miss_latency::total 15893.511696 # average ReadReq miss latency
2134,2137c2241,2244
< system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17802.039419 # average overall miss latency
< system.cpu2.dcache.demand_avg_miss_latency::total 17802.039419 # average overall miss latency
< system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17802.039419 # average overall miss latency
< system.cpu2.dcache.overall_avg_miss_latency::total 17802.039419 # average overall miss latency
---
> system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17789.607884 # average overall miss latency
> system.cpu2.dcache.demand_avg_miss_latency::total 17789.607884 # average overall miss latency
> system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17789.607884 # average overall miss latency
> system.cpu2.dcache.overall_avg_miss_latency::total 17789.607884 # average overall miss latency
2164,2165c2271,2272
< system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1516779 # number of ReadReq MSHR miss cycles
< system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1516779 # number of ReadReq MSHR miss cycles
---
> system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1515278 # number of ReadReq MSHR miss cycles
> system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1515278 # number of ReadReq MSHR miss cycles
2170,2177c2277,2284
< system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3044769 # number of demand (read+write) MSHR miss cycles
< system.cpu2.dcache.demand_mshr_miss_latency::total 3044769 # number of demand (read+write) MSHR miss cycles
< system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3044769 # number of overall MSHR miss cycles
< system.cpu2.dcache.overall_mshr_miss_latency::total 3044769 # number of overall MSHR miss cycles
< system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003896 # mshr miss rate for ReadReq accesses
< system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003896 # mshr miss rate for ReadReq accesses
< system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003363 # mshr miss rate for WriteReq accesses
< system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003363 # mshr miss rate for WriteReq accesses
---
> system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3043268 # number of demand (read+write) MSHR miss cycles
> system.cpu2.dcache.demand_mshr_miss_latency::total 3043268 # number of demand (read+write) MSHR miss cycles
> system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3043268 # number of overall MSHR miss cycles
> system.cpu2.dcache.overall_mshr_miss_latency::total 3043268 # number of overall MSHR miss cycles
> system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003897 # mshr miss rate for ReadReq accesses
> system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003897 # mshr miss rate for ReadReq accesses
> system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003364 # mshr miss rate for WriteReq accesses
> system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003364 # mshr miss rate for WriteReq accesses
2184,2185c2291,2292
< system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9192.600000 # average ReadReq mshr miss latency
< system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9192.600000 # average ReadReq mshr miss latency
---
> system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9183.503030 # average ReadReq mshr miss latency
> system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9183.503030 # average ReadReq mshr miss latency
2190,2193c2297,2300
< system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11235.309963 # average overall mshr miss latency
< system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11235.309963 # average overall mshr miss latency
< system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11235.309963 # average overall mshr miss latency
< system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11235.309963 # average overall mshr miss latency
---
> system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11229.771218 # average overall mshr miss latency
> system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11229.771218 # average overall mshr miss latency
> system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11229.771218 # average overall mshr miss latency
> system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11229.771218 # average overall mshr miss latency
2195,2196c2302,2303
< system.cpu3.branchPred.lookups 53969 # Number of BP lookups
< system.cpu3.branchPred.condPredicted 51237 # Number of conditional branches predicted
---
> system.cpu3.branchPred.lookups 53964 # Number of BP lookups
> system.cpu3.branchPred.condPredicted 51232 # Number of conditional branches predicted
2198,2199c2305,2306
< system.cpu3.branchPred.BTBLookups 47879 # Number of BTB lookups
< system.cpu3.branchPred.BTBHits 47122 # Number of BTB hits
---
> system.cpu3.branchPred.BTBLookups 47874 # Number of BTB lookups
> system.cpu3.branchPred.BTBHits 47117 # Number of BTB hits
2201c2308
< system.cpu3.branchPred.BTBHitPct 98.418931 # BTB Hit Percentage
---
> system.cpu3.branchPred.BTBHitPct 98.418766 # BTB Hit Percentage
2204c2311
< system.cpu3.numCycles 177018 # number of cpu cycles simulated
---
> system.cpu3.numCycles 176930 # number of cpu cycles simulated
2207,2211c2314,2318
< system.cpu3.fetch.icacheStallCycles 27849 # Number of cycles fetch is stalled on an Icache miss
< system.cpu3.fetch.Insts 302683 # Number of instructions fetch has processed
< system.cpu3.fetch.Branches 53969 # Number of branches that fetch encountered
< system.cpu3.fetch.predictedBranches 47767 # Number of branches that fetch has predicted taken
< system.cpu3.fetch.Cycles 106238 # Number of cycles fetch has run and was not squashing or blocked
---
> system.cpu3.fetch.icacheStallCycles 27837 # Number of cycles fetch is stalled on an Icache miss
> system.cpu3.fetch.Insts 302665 # Number of instructions fetch has processed
> system.cpu3.fetch.Branches 53964 # Number of branches that fetch encountered
> system.cpu3.fetch.predictedBranches 47762 # Number of branches that fetch has predicted taken
> system.cpu3.fetch.Cycles 106222 # Number of cycles fetch has run and was not squashing or blocked
2213c2320
< system.cpu3.fetch.BlockedCycles 30687 # Number of cycles fetch has spent blocked
---
> system.cpu3.fetch.BlockedCycles 30631 # Number of cycles fetch has spent blocked
2215c2322
< system.cpu3.fetch.NoActiveThreadStallCycles 7755 # Number of stall cycles due to no active thread to fetch from
---
> system.cpu3.fetch.NoActiveThreadStallCycles 7749 # Number of stall cycles due to no active thread to fetch from
2217c2324
< system.cpu3.fetch.CacheLines 19589 # Number of cache lines fetched
---
> system.cpu3.fetch.CacheLines 19577 # Number of cache lines fetched
2219,2221c2326,2328
< system.cpu3.fetch.rateDist::samples 175633 # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::mean 1.723383 # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::stdev 2.153093 # Number of instructions fetched each cycle (Total)
---
> system.cpu3.fetch.rateDist::samples 175543 # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::mean 1.724164 # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::stdev 2.153360 # Number of instructions fetched each cycle (Total)
2223,2228c2330,2335
< system.cpu3.fetch.rateDist::0 69395 39.51% 39.51% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::1 53961 30.72% 70.24% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::2 6037 3.44% 73.67% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::3 3206 1.83% 75.50% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::4 696 0.40% 75.89% # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.rateDist::5 37090 21.12% 97.01% # Number of instructions fetched each cycle (Total)
---
> system.cpu3.fetch.rateDist::0 69321 39.49% 39.49% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::1 53950 30.73% 70.22% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::2 6031 3.44% 73.66% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::3 3206 1.83% 75.48% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::4 696 0.40% 75.88% # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.rateDist::5 37091 21.13% 97.01% # Number of instructions fetched each cycle (Total)
2235,2241c2342,2348
< system.cpu3.fetch.rateDist::total 175633 # Number of instructions fetched each cycle (Total)
< system.cpu3.fetch.branchRate 0.304879 # Number of branch fetches per cycle
< system.cpu3.fetch.rate 1.709900 # Number of inst fetches per cycle
< system.cpu3.decode.IdleCycles 32991 # Number of cycles decode is idle
< system.cpu3.decode.BlockedCycles 27180 # Number of cycles decode is blocked
< system.cpu3.decode.RunCycles 100358 # Number of cycles decode is running
< system.cpu3.decode.UnblockCycles 5049 # Number of cycles decode is unblocking
---
> system.cpu3.fetch.rateDist::total 175543 # Number of instructions fetched each cycle (Total)
> system.cpu3.fetch.branchRate 0.305002 # Number of branch fetches per cycle
> system.cpu3.fetch.rate 1.710648 # Number of inst fetches per cycle
> system.cpu3.decode.IdleCycles 32973 # Number of cycles decode is idle
> system.cpu3.decode.BlockedCycles 27130 # Number of cycles decode is blocked
> system.cpu3.decode.RunCycles 100348 # Number of cycles decode is running
> system.cpu3.decode.UnblockCycles 5043 # Number of cycles decode is unblocking
2243c2350
< system.cpu3.decode.DecodedInsts 299127 # Number of instructions handled by decode
---
> system.cpu3.decode.DecodedInsts 299109 # Number of instructions handled by decode
2245,2250c2352,2357
< system.cpu3.rename.IdleCycles 33666 # Number of cycles rename is idle
< system.cpu3.rename.BlockCycles 14636 # Number of cycles rename is blocking
< system.cpu3.rename.serializeStallCycles 11796 # count of cycles rename stalled for serializing inst
< system.cpu3.rename.RunCycles 95593 # Number of cycles rename is running
< system.cpu3.rename.UnblockCycles 9887 # Number of cycles rename is unblocking
< system.cpu3.rename.RenamedInsts 297010 # Number of instructions processed by rename
---
> system.cpu3.rename.IdleCycles 33648 # Number of cycles rename is idle
> system.cpu3.rename.BlockCycles 14616 # Number of cycles rename is blocking
> system.cpu3.rename.serializeStallCycles 11766 # count of cycles rename stalled for serializing inst
> system.cpu3.rename.RunCycles 95589 # Number of cycles rename is running
> system.cpu3.rename.UnblockCycles 9875 # Number of cycles rename is unblocking
> system.cpu3.rename.RenamedInsts 296992 # Number of instructions processed by rename
2253,2256c2360,2363
< system.cpu3.rename.RenamedOperands 207704 # Number of destination operands rename has renamed
< system.cpu3.rename.RenameLookups 570857 # Number of register rename lookups that rename has made
< system.cpu3.rename.int_rename_lookups 442944 # Number of integer rename lookups
< system.cpu3.rename.CommittedMaps 195081 # Number of HB maps that are committed
---
> system.cpu3.rename.RenamedOperands 207702 # Number of destination operands rename has renamed
> system.cpu3.rename.RenameLookups 570845 # Number of register rename lookups that rename has made
> system.cpu3.rename.int_rename_lookups 442935 # Number of integer rename lookups
> system.cpu3.rename.CommittedMaps 195079 # Number of HB maps that are committed
2260,2268c2367,2375
< system.cpu3.rename.skidInsts 12502 # count of insts added to the skid buffer
< system.cpu3.memDep0.insertedLoads 84726 # Number of loads inserted to the mem dependence unit.
< system.cpu3.memDep0.insertedStores 40382 # Number of stores inserted to the mem dependence unit.
< system.cpu3.memDep0.conflictingLoads 40460 # Number of conflicting loads.
< system.cpu3.memDep0.conflictingStores 35337 # Number of conflicting stores.
< system.cpu3.iq.iqInstsAdded 246420 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu3.iq.iqNonSpecInstsAdded 6261 # Number of non-speculative instructions added to the IQ
< system.cpu3.iq.iqInstsIssued 248749 # Number of instructions issued
< system.cpu3.iq.iqSquashedInstsIssued 57 # Number of squashed instructions issued
---
> system.cpu3.rename.skidInsts 12490 # count of insts added to the skid buffer
> system.cpu3.memDep0.insertedLoads 84722 # Number of loads inserted to the mem dependence unit.
> system.cpu3.memDep0.insertedStores 40383 # Number of stores inserted to the mem dependence unit.
> system.cpu3.memDep0.conflictingLoads 40455 # Number of conflicting loads.
> system.cpu3.memDep0.conflictingStores 35338 # Number of conflicting stores.
> system.cpu3.iq.iqInstsAdded 246413 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu3.iq.iqNonSpecInstsAdded 6255 # Number of non-speculative instructions added to the IQ
> system.cpu3.iq.iqInstsIssued 248738 # Number of instructions issued
> system.cpu3.iq.iqSquashedInstsIssued 58 # Number of squashed instructions issued
2270c2377
< system.cpu3.iq.iqSquashedOperandsExamined 9956 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu3.iq.iqSquashedOperandsExamined 9948 # Number of squashed operands that are examined and possibly removed from graph
2272,2274c2379,2381
< system.cpu3.iq.issued_per_cycle::samples 175633 # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::mean 1.416300 # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::stdev 1.309117 # Number of insts issued each cycle
---
> system.cpu3.iq.issued_per_cycle::samples 175543 # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::mean 1.416963 # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::stdev 1.309147 # Number of insts issued each cycle
2276,2280c2383,2387
< system.cpu3.iq.issued_per_cycle::0 66575 37.91% 37.91% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::1 22292 12.69% 50.60% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::2 40685 23.16% 73.76% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::3 41298 23.51% 97.28% # Number of insts issued each cycle
< system.cpu3.iq.issued_per_cycle::4 3252 1.85% 99.13% # Number of insts issued each cycle
---
> system.cpu3.iq.issued_per_cycle::0 66501 37.88% 37.88% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::1 22275 12.69% 50.57% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::2 40683 23.18% 73.75% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::3 41300 23.53% 97.27% # Number of insts issued each cycle
> system.cpu3.iq.issued_per_cycle::4 3253 1.85% 99.13% # Number of insts issued each cycle
2288c2395
< system.cpu3.iq.issued_per_cycle::total 175633 # Number of insts issued each cycle
---
> system.cpu3.iq.issued_per_cycle::total 175543 # Number of insts issued each cycle
2290,2320c2397,2427
< system.cpu3.iq.fu_full::IntAlu 17 6.46% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::IntMult 0 0.00% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.46% # attempts to use FU when none available
< system.cpu3.iq.fu_full::MemRead 36 13.69% 20.15% # attempts to use FU when none available
< system.cpu3.iq.fu_full::MemWrite 210 79.85% 100.00% # attempts to use FU when none available
---
> system.cpu3.iq.fu_full::IntAlu 17 6.44% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::IntMult 0 0.00% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.44% # attempts to use FU when none available
> system.cpu3.iq.fu_full::MemRead 37 14.02% 20.45% # attempts to use FU when none available
> system.cpu3.iq.fu_full::MemWrite 210 79.55% 100.00% # attempts to use FU when none available
2324c2431
< system.cpu3.iq.FU_type_0::IntAlu 119915 48.21% 48.21% # Type of FU issued
---
> system.cpu3.iq.FU_type_0::IntAlu 119912 48.21% 48.21% # Type of FU issued
2353,2354c2460,2461
< system.cpu3.iq.FU_type_0::MemRead 89111 35.82% 84.03% # Type of FU issued
< system.cpu3.iq.FU_type_0::MemWrite 39723 15.97% 100.00% # Type of FU issued
---
> system.cpu3.iq.FU_type_0::MemRead 89101 35.82% 84.03% # Type of FU issued
> system.cpu3.iq.FU_type_0::MemWrite 39725 15.97% 100.00% # Type of FU issued
2357,2363c2464,2470
< system.cpu3.iq.FU_type_0::total 248749 # Type of FU issued
< system.cpu3.iq.rate 1.405219 # Inst issue rate
< system.cpu3.iq.fu_busy_cnt 263 # FU busy when requested
< system.cpu3.iq.fu_busy_rate 0.001057 # FU busy rate (busy events/executed inst)
< system.cpu3.iq.int_inst_queue_reads 673451 # Number of integer instruction queue reads
< system.cpu3.iq.int_inst_queue_writes 263132 # Number of integer instruction queue writes
< system.cpu3.iq.int_inst_queue_wakeup_accesses 246950 # Number of integer instruction queue wakeup accesses
---
> system.cpu3.iq.FU_type_0::total 248738 # Type of FU issued
> system.cpu3.iq.rate 1.405855 # Inst issue rate
> system.cpu3.iq.fu_busy_cnt 264 # FU busy when requested
> system.cpu3.iq.fu_busy_rate 0.001061 # FU busy rate (busy events/executed inst)
> system.cpu3.iq.int_inst_queue_reads 673341 # Number of integer instruction queue reads
> system.cpu3.iq.int_inst_queue_writes 263119 # Number of integer instruction queue writes
> system.cpu3.iq.int_inst_queue_wakeup_accesses 246940 # Number of integer instruction queue wakeup accesses
2367c2474
< system.cpu3.iq.int_alu_accesses 249012 # Number of integer alu accesses
---
> system.cpu3.iq.int_alu_accesses 249002 # Number of integer alu accesses
2369c2476
< system.cpu3.iew.lsq.thread0.forwLoads 35153 # Number of loads that had data forwarded from stores
---
> system.cpu3.iew.lsq.thread0.forwLoads 35155 # Number of loads that had data forwarded from stores
2381c2488
< system.cpu3.iew.iewBlockCycles 645 # Number of cycles IEW is blocking
---
> system.cpu3.iew.iewBlockCycles 643 # Number of cycles IEW is blocking
2383c2490
< system.cpu3.iew.iewDispatchedInsts 294144 # Number of instructions dispatched to IQ
---
> system.cpu3.iew.iewDispatchedInsts 294126 # Number of instructions dispatched to IQ
2385,2386c2492,2493
< system.cpu3.iew.iewDispLoadInsts 84726 # Number of dispatched load instructions
< system.cpu3.iew.iewDispStoreInsts 40382 # Number of dispatched store instructions
---
> system.cpu3.iew.iewDispLoadInsts 84722 # Number of dispatched load instructions
> system.cpu3.iew.iewDispStoreInsts 40383 # Number of dispatched store instructions
2394,2395c2501,2502
< system.cpu3.iew.iewExecutedInsts 247595 # Number of executed instructions
< system.cpu3.iew.iewExecLoadInsts 83855 # Number of load instructions executed
---
> system.cpu3.iew.iewExecutedInsts 247584 # Number of executed instructions
> system.cpu3.iew.iewExecLoadInsts 83851 # Number of load instructions executed
2398,2406c2505,2513
< system.cpu3.iew.exec_nop 41463 # number of nop insts executed
< system.cpu3.iew.exec_refs 123509 # number of memory reference insts executed
< system.cpu3.iew.exec_branches 50804 # Number of branches executed
< system.cpu3.iew.exec_stores 39654 # Number of stores executed
< system.cpu3.iew.exec_rate 1.398700 # Inst execution rate
< system.cpu3.iew.wb_sent 247239 # cumulative count of insts sent to commit
< system.cpu3.iew.wb_count 246950 # cumulative count of insts written-back
< system.cpu3.iew.wb_producers 140249 # num instructions producing a value
< system.cpu3.iew.wb_consumers 144916 # num instructions consuming a value
---
> system.cpu3.iew.exec_nop 41458 # number of nop insts executed
> system.cpu3.iew.exec_refs 123507 # number of memory reference insts executed
> system.cpu3.iew.exec_branches 50799 # Number of branches executed
> system.cpu3.iew.exec_stores 39656 # Number of stores executed
> system.cpu3.iew.exec_rate 1.399333 # Inst execution rate
> system.cpu3.iew.wb_sent 247229 # cumulative count of insts sent to commit
> system.cpu3.iew.wb_count 246940 # cumulative count of insts written-back
> system.cpu3.iew.wb_producers 140247 # num instructions producing a value
> system.cpu3.iew.wb_consumers 144914 # num instructions consuming a value
2408c2515
< system.cpu3.iew.wb_rate 1.395056 # insts written-back per cycle
---
> system.cpu3.iew.wb_rate 1.395693 # insts written-back per cycle
2412c2519
< system.cpu3.commit.commitNonSpecStalls 5695 # The number of times commit has been forced to stall to communicate backwards
---
> system.cpu3.commit.commitNonSpecStalls 5689 # The number of times commit has been forced to stall to communicate backwards
2414,2416c2521,2523
< system.cpu3.commit.committed_per_cycle::samples 165578 # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::mean 1.704170 # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::stdev 2.038930 # Number of insts commited each cycle
---
> system.cpu3.commit.committed_per_cycle::samples 165494 # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::mean 1.704926 # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::stdev 2.039126 # Number of insts commited each cycle
2418,2423c2525,2530
< system.cpu3.commit.committed_per_cycle::0 64386 38.89% 38.89% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::1 48906 29.54% 68.42% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::2 6087 3.68% 72.10% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::3 6642 4.01% 76.11% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::4 1574 0.95% 77.06% # Number of insts commited each cycle
< system.cpu3.commit.committed_per_cycle::5 35662 21.54% 98.60% # Number of insts commited each cycle
---
> system.cpu3.commit.committed_per_cycle::0 64312 38.86% 38.86% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::1 48901 29.55% 68.41% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::2 6087 3.68% 72.09% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::3 6636 4.01% 76.10% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::4 1574 0.95% 77.05% # Number of insts commited each cycle
> system.cpu3.commit.committed_per_cycle::5 35663 21.55% 98.60% # Number of insts commited each cycle
2430,2432c2537,2539
< system.cpu3.commit.committed_per_cycle::total 165578 # Number of insts commited each cycle
< system.cpu3.commit.committedInsts 282173 # Number of instructions committed
< system.cpu3.commit.committedOps 282173 # Number of ops (including micro ops) committed
---
> system.cpu3.commit.committed_per_cycle::total 165494 # Number of insts commited each cycle
> system.cpu3.commit.committedInsts 282155 # Number of instructions committed
> system.cpu3.commit.committedOps 282155 # Number of ops (including micro ops) committed
2434,2437c2541,2544
< system.cpu3.commit.refs 121476 # Number of memory references committed
< system.cpu3.commit.loads 82479 # Number of loads committed
< system.cpu3.commit.membars 4985 # Number of memory barriers committed
< system.cpu3.commit.branches 49947 # Number of branches committed
---
> system.cpu3.commit.refs 121473 # Number of memory references committed
> system.cpu3.commit.loads 82475 # Number of loads committed
> system.cpu3.commit.membars 4979 # Number of memory barriers committed
> system.cpu3.commit.branches 49942 # Number of branches committed
2439c2546
< system.cpu3.commit.int_insts 193548 # Number of committed integer instructions.
---
> system.cpu3.commit.int_insts 193540 # Number of committed integer instructions.
2440a2548,2582
> system.cpu3.commit.op_class_0::No_OpClass 40736 14.44% 14.44% # Class of committed instruction
> system.cpu3.commit.op_class_0::IntAlu 114967 40.75% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::MemRead 87454 31.00% 86.18% # Class of committed instruction
> system.cpu3.commit.op_class_0::MemWrite 38998 13.82% 100.00% # Class of committed instruction
> system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
> system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
> system.cpu3.commit.op_class_0::total 282155 # Class of committed instruction
2443,2444c2585,2586
< system.cpu3.rob.rob_reads 458297 # The number of ROB reads
< system.cpu3.rob.rob_writes 590554 # The number of ROB writes
---
> system.cpu3.rob.rob_reads 458195 # The number of ROB reads
> system.cpu3.rob.rob_writes 590518 # The number of ROB writes
2446,2456c2588,2598
< system.cpu3.idleCycles 1385 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu3.quiesceCycles 44892 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu3.committedInsts 236447 # Number of Instructions Simulated
< system.cpu3.committedOps 236447 # Number of Ops (including micro ops) Simulated
< system.cpu3.committedInsts_total 236447 # Number of Instructions Simulated
< system.cpu3.cpi 0.748658 # CPI: Cycles Per Instruction
< system.cpu3.cpi_total 0.748658 # CPI: Total CPI of All Threads
< system.cpu3.ipc 1.335723 # IPC: Instructions Per Cycle
< system.cpu3.ipc_total 1.335723 # IPC: Total IPC of All Threads
< system.cpu3.int_regfile_reads 429146 # number of integer regfile reads
< system.cpu3.int_regfile_writes 199911 # number of integer regfile writes
---
> system.cpu3.idleCycles 1387 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu3.quiesceCycles 44814 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu3.committedInsts 236440 # Number of Instructions Simulated
> system.cpu3.committedOps 236440 # Number of Ops (including micro ops) Simulated
> system.cpu3.committedInsts_total 236440 # Number of Instructions Simulated
> system.cpu3.cpi 0.748308 # CPI: Cycles Per Instruction
> system.cpu3.cpi_total 0.748308 # CPI: Total CPI of All Threads
> system.cpu3.ipc 1.336348 # IPC: Instructions Per Cycle
> system.cpu3.ipc_total 1.336348 # IPC: Total IPC of All Threads
> system.cpu3.int_regfile_reads 429141 # number of integer regfile reads
> system.cpu3.int_regfile_writes 199912 # number of integer regfile writes
2458c2600
< system.cpu3.misc_regfile_reads 125103 # number of misc regfile reads
---
> system.cpu3.misc_regfile_reads 125101 # number of misc regfile reads
2461,2462c2603,2604
< system.cpu3.icache.tags.tagsinuse 80.480006 # Cycle average of tags in use
< system.cpu3.icache.tags.total_refs 19114 # Total number of references to valid blocks.
---
> system.cpu3.icache.tags.tagsinuse 80.524551 # Cycle average of tags in use
> system.cpu3.icache.tags.total_refs 19102 # Total number of references to valid blocks.
2464c2606
< system.cpu3.icache.tags.avg_refs 44.451163 # Average number of references to valid blocks.
---
> system.cpu3.icache.tags.avg_refs 44.423256 # Average number of references to valid blocks.
2466,2468c2608,2610
< system.cpu3.icache.tags.occ_blocks::cpu3.inst 80.480006 # Average occupied blocks per requestor
< system.cpu3.icache.tags.occ_percent::cpu3.inst 0.157188 # Average percentage of cache occupancy
< system.cpu3.icache.tags.occ_percent::total 0.157188 # Average percentage of cache occupancy
---
> system.cpu3.icache.tags.occ_blocks::cpu3.inst 80.524551 # Average occupied blocks per requestor
> system.cpu3.icache.tags.occ_percent::cpu3.inst 0.157275 # Average percentage of cache occupancy
> system.cpu3.icache.tags.occ_percent::total 0.157275 # Average percentage of cache occupancy
2473,2480c2615,2622
< system.cpu3.icache.tags.tag_accesses 20019 # Number of tag accesses
< system.cpu3.icache.tags.data_accesses 20019 # Number of data accesses
< system.cpu3.icache.ReadReq_hits::cpu3.inst 19114 # number of ReadReq hits
< system.cpu3.icache.ReadReq_hits::total 19114 # number of ReadReq hits
< system.cpu3.icache.demand_hits::cpu3.inst 19114 # number of demand (read+write) hits
< system.cpu3.icache.demand_hits::total 19114 # number of demand (read+write) hits
< system.cpu3.icache.overall_hits::cpu3.inst 19114 # number of overall hits
< system.cpu3.icache.overall_hits::total 19114 # number of overall hits
---
> system.cpu3.icache.tags.tag_accesses 20007 # Number of tag accesses
> system.cpu3.icache.tags.data_accesses 20007 # Number of data accesses
> system.cpu3.icache.ReadReq_hits::cpu3.inst 19102 # number of ReadReq hits
> system.cpu3.icache.ReadReq_hits::total 19102 # number of ReadReq hits
> system.cpu3.icache.demand_hits::cpu3.inst 19102 # number of demand (read+write) hits
> system.cpu3.icache.demand_hits::total 19102 # number of demand (read+write) hits
> system.cpu3.icache.overall_hits::cpu3.inst 19102 # number of overall hits
> system.cpu3.icache.overall_hits::total 19102 # number of overall hits
2493,2504c2635,2646
< system.cpu3.icache.ReadReq_accesses::cpu3.inst 19589 # number of ReadReq accesses(hits+misses)
< system.cpu3.icache.ReadReq_accesses::total 19589 # number of ReadReq accesses(hits+misses)
< system.cpu3.icache.demand_accesses::cpu3.inst 19589 # number of demand (read+write) accesses
< system.cpu3.icache.demand_accesses::total 19589 # number of demand (read+write) accesses
< system.cpu3.icache.overall_accesses::cpu3.inst 19589 # number of overall (read+write) accesses
< system.cpu3.icache.overall_accesses::total 19589 # number of overall (read+write) accesses
< system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.024248 # miss rate for ReadReq accesses
< system.cpu3.icache.ReadReq_miss_rate::total 0.024248 # miss rate for ReadReq accesses
< system.cpu3.icache.demand_miss_rate::cpu3.inst 0.024248 # miss rate for demand accesses
< system.cpu3.icache.demand_miss_rate::total 0.024248 # miss rate for demand accesses
< system.cpu3.icache.overall_miss_rate::cpu3.inst 0.024248 # miss rate for overall accesses
< system.cpu3.icache.overall_miss_rate::total 0.024248 # miss rate for overall accesses
---
> system.cpu3.icache.ReadReq_accesses::cpu3.inst 19577 # number of ReadReq accesses(hits+misses)
> system.cpu3.icache.ReadReq_accesses::total 19577 # number of ReadReq accesses(hits+misses)
> system.cpu3.icache.demand_accesses::cpu3.inst 19577 # number of demand (read+write) accesses
> system.cpu3.icache.demand_accesses::total 19577 # number of demand (read+write) accesses
> system.cpu3.icache.overall_accesses::cpu3.inst 19577 # number of overall (read+write) accesses
> system.cpu3.icache.overall_accesses::total 19577 # number of overall (read+write) accesses
> system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.024263 # miss rate for ReadReq accesses
> system.cpu3.icache.ReadReq_miss_rate::total 0.024263 # miss rate for ReadReq accesses
> system.cpu3.icache.demand_miss_rate::cpu3.inst 0.024263 # miss rate for demand accesses
> system.cpu3.icache.demand_miss_rate::total 0.024263 # miss rate for demand accesses
> system.cpu3.icache.overall_miss_rate::cpu3.inst 0.024263 # miss rate for overall accesses
> system.cpu3.icache.overall_miss_rate::total 0.024263 # miss rate for overall accesses
2537,2542c2679,2684
< system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.021951 # mshr miss rate for ReadReq accesses
< system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.021951 # mshr miss rate for ReadReq accesses
< system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.021951 # mshr miss rate for demand accesses
< system.cpu3.icache.demand_mshr_miss_rate::total 0.021951 # mshr miss rate for demand accesses
< system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.021951 # mshr miss rate for overall accesses
< system.cpu3.icache.overall_mshr_miss_rate::total 0.021951 # mshr miss rate for overall accesses
---
> system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.021965 # mshr miss rate for ReadReq accesses
> system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.021965 # mshr miss rate for ReadReq accesses
> system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.021965 # mshr miss rate for demand accesses
> system.cpu3.icache.demand_mshr_miss_rate::total 0.021965 # mshr miss rate for demand accesses
> system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.021965 # mshr miss rate for overall accesses
> system.cpu3.icache.overall_mshr_miss_rate::total 0.021965 # mshr miss rate for overall accesses
2551,2552c2693,2694
< system.cpu3.dcache.tags.tagsinuse 24.751493 # Cycle average of tags in use
< system.cpu3.dcache.tags.total_refs 44991 # Total number of references to valid blocks.
---
> system.cpu3.dcache.tags.tagsinuse 24.706550 # Cycle average of tags in use
> system.cpu3.dcache.tags.total_refs 44992 # Total number of references to valid blocks.
2554c2696
< system.cpu3.dcache.tags.avg_refs 1606.821429 # Average number of references to valid blocks.
---
> system.cpu3.dcache.tags.avg_refs 1606.857143 # Average number of references to valid blocks.
2556,2558c2698,2700
< system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.751493 # Average occupied blocks per requestor
< system.cpu3.dcache.tags.occ_percent::cpu3.data 0.048343 # Average percentage of cache occupancy
< system.cpu3.dcache.tags.occ_percent::total 0.048343 # Average percentage of cache occupancy
---
> system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.706550 # Average occupied blocks per requestor
> system.cpu3.dcache.tags.occ_percent::cpu3.data 0.048255 # Average percentage of cache occupancy
> system.cpu3.dcache.tags.occ_percent::total 0.048255 # Average percentage of cache occupancy
2562,2567c2704,2709
< system.cpu3.dcache.tags.tag_accesses 350966 # Number of tag accesses
< system.cpu3.dcache.tags.data_accesses 350966 # Number of data accesses
< system.cpu3.dcache.ReadReq_hits::cpu3.data 48333 # number of ReadReq hits
< system.cpu3.dcache.ReadReq_hits::total 48333 # number of ReadReq hits
< system.cpu3.dcache.WriteReq_hits::cpu3.data 38794 # number of WriteReq hits
< system.cpu3.dcache.WriteReq_hits::total 38794 # number of WriteReq hits
---
> system.cpu3.dcache.tags.tag_accesses 350946 # Number of tag accesses
> system.cpu3.dcache.tags.data_accesses 350946 # Number of data accesses
> system.cpu3.dcache.ReadReq_hits::cpu3.data 48327 # number of ReadReq hits
> system.cpu3.dcache.ReadReq_hits::total 48327 # number of ReadReq hits
> system.cpu3.dcache.WriteReq_hits::cpu3.data 38795 # number of WriteReq hits
> system.cpu3.dcache.WriteReq_hits::total 38795 # number of WriteReq hits
2570,2573c2712,2715
< system.cpu3.dcache.demand_hits::cpu3.data 87127 # number of demand (read+write) hits
< system.cpu3.dcache.demand_hits::total 87127 # number of demand (read+write) hits
< system.cpu3.dcache.overall_hits::cpu3.data 87127 # number of overall hits
< system.cpu3.dcache.overall_hits::total 87127 # number of overall hits
---
> system.cpu3.dcache.demand_hits::cpu3.data 87122 # number of demand (read+write) hits
> system.cpu3.dcache.demand_hits::total 87122 # number of demand (read+write) hits
> system.cpu3.dcache.overall_hits::cpu3.data 87122 # number of overall hits
> system.cpu3.dcache.overall_hits::total 87122 # number of overall hits
2584,2597c2726,2739
< system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4639136 # number of ReadReq miss cycles
< system.cpu3.dcache.ReadReq_miss_latency::total 4639136 # number of ReadReq miss cycles
< system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3479012 # number of WriteReq miss cycles
< system.cpu3.dcache.WriteReq_miss_latency::total 3479012 # number of WriteReq miss cycles
< system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 512008 # number of SwapReq miss cycles
< system.cpu3.dcache.SwapReq_miss_latency::total 512008 # number of SwapReq miss cycles
< system.cpu3.dcache.demand_miss_latency::cpu3.data 8118148 # number of demand (read+write) miss cycles
< system.cpu3.dcache.demand_miss_latency::total 8118148 # number of demand (read+write) miss cycles
< system.cpu3.dcache.overall_miss_latency::cpu3.data 8118148 # number of overall miss cycles
< system.cpu3.dcache.overall_miss_latency::total 8118148 # number of overall miss cycles
< system.cpu3.dcache.ReadReq_accesses::cpu3.data 48684 # number of ReadReq accesses(hits+misses)
< system.cpu3.dcache.ReadReq_accesses::total 48684 # number of ReadReq accesses(hits+misses)
< system.cpu3.dcache.WriteReq_accesses::cpu3.data 38933 # number of WriteReq accesses(hits+misses)
< system.cpu3.dcache.WriteReq_accesses::total 38933 # number of WriteReq accesses(hits+misses)
---
> system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4621144 # number of ReadReq miss cycles
> system.cpu3.dcache.ReadReq_miss_latency::total 4621144 # number of ReadReq miss cycles
> system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3311512 # number of WriteReq miss cycles
> system.cpu3.dcache.WriteReq_miss_latency::total 3311512 # number of WriteReq miss cycles
> system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 513008 # number of SwapReq miss cycles
> system.cpu3.dcache.SwapReq_miss_latency::total 513008 # number of SwapReq miss cycles
> system.cpu3.dcache.demand_miss_latency::cpu3.data 7932656 # number of demand (read+write) miss cycles
> system.cpu3.dcache.demand_miss_latency::total 7932656 # number of demand (read+write) miss cycles
> system.cpu3.dcache.overall_miss_latency::cpu3.data 7932656 # number of overall miss cycles
> system.cpu3.dcache.overall_miss_latency::total 7932656 # number of overall miss cycles
> system.cpu3.dcache.ReadReq_accesses::cpu3.data 48678 # number of ReadReq accesses(hits+misses)
> system.cpu3.dcache.ReadReq_accesses::total 48678 # number of ReadReq accesses(hits+misses)
> system.cpu3.dcache.WriteReq_accesses::cpu3.data 38934 # number of WriteReq accesses(hits+misses)
> system.cpu3.dcache.WriteReq_accesses::total 38934 # number of WriteReq accesses(hits+misses)
2600,2605c2742,2747
< system.cpu3.dcache.demand_accesses::cpu3.data 87617 # number of demand (read+write) accesses
< system.cpu3.dcache.demand_accesses::total 87617 # number of demand (read+write) accesses
< system.cpu3.dcache.overall_accesses::cpu3.data 87617 # number of overall (read+write) accesses
< system.cpu3.dcache.overall_accesses::total 87617 # number of overall (read+write) accesses
< system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.007210 # miss rate for ReadReq accesses
< system.cpu3.dcache.ReadReq_miss_rate::total 0.007210 # miss rate for ReadReq accesses
---
> system.cpu3.dcache.demand_accesses::cpu3.data 87612 # number of demand (read+write) accesses
> system.cpu3.dcache.demand_accesses::total 87612 # number of demand (read+write) accesses
> system.cpu3.dcache.overall_accesses::cpu3.data 87612 # number of overall (read+write) accesses
> system.cpu3.dcache.overall_accesses::total 87612 # number of overall (read+write) accesses
> system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.007211 # miss rate for ReadReq accesses
> system.cpu3.dcache.ReadReq_miss_rate::total 0.007211 # miss rate for ReadReq accesses
2614,2623c2756,2765
< system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 13216.911681 # average ReadReq miss latency
< system.cpu3.dcache.ReadReq_avg_miss_latency::total 13216.911681 # average ReadReq miss latency
< system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25028.863309 # average WriteReq miss latency
< system.cpu3.dcache.WriteReq_avg_miss_latency::total 25028.863309 # average WriteReq miss latency
< system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9846.307692 # average SwapReq miss latency
< system.cpu3.dcache.SwapReq_avg_miss_latency::total 9846.307692 # average SwapReq miss latency
< system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16567.648980 # average overall miss latency
< system.cpu3.dcache.demand_avg_miss_latency::total 16567.648980 # average overall miss latency
< system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16567.648980 # average overall miss latency
< system.cpu3.dcache.overall_avg_miss_latency::total 16567.648980 # average overall miss latency
---
> system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 13165.652422 # average ReadReq miss latency
> system.cpu3.dcache.ReadReq_avg_miss_latency::total 13165.652422 # average ReadReq miss latency
> system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 23823.827338 # average WriteReq miss latency
> system.cpu3.dcache.WriteReq_avg_miss_latency::total 23823.827338 # average WriteReq miss latency
> system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9865.538462 # average SwapReq miss latency
> system.cpu3.dcache.SwapReq_avg_miss_latency::total 9865.538462 # average SwapReq miss latency
> system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16189.093878 # average overall miss latency
> system.cpu3.dcache.demand_avg_miss_latency::total 16189.093878 # average overall miss latency
> system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16189.093878 # average overall miss latency
> system.cpu3.dcache.overall_avg_miss_latency::total 16189.093878 # average overall miss latency
2650,2661c2792,2803
< system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1051018 # number of ReadReq MSHR miss cycles
< system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1051018 # number of ReadReq MSHR miss cycles
< system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1439238 # number of WriteReq MSHR miss cycles
< system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1439238 # number of WriteReq MSHR miss cycles
< system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 407992 # number of SwapReq MSHR miss cycles
< system.cpu3.dcache.SwapReq_mshr_miss_latency::total 407992 # number of SwapReq MSHR miss cycles
< system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2490256 # number of demand (read+write) MSHR miss cycles
< system.cpu3.dcache.demand_mshr_miss_latency::total 2490256 # number of demand (read+write) MSHR miss cycles
< system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2490256 # number of overall MSHR miss cycles
< system.cpu3.dcache.overall_mshr_miss_latency::total 2490256 # number of overall MSHR miss cycles
< system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003163 # mshr miss rate for ReadReq accesses
< system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003163 # mshr miss rate for ReadReq accesses
---
> system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1052517 # number of ReadReq MSHR miss cycles
> system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1052517 # number of ReadReq MSHR miss cycles
> system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1403488 # number of WriteReq MSHR miss cycles
> system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1403488 # number of WriteReq MSHR miss cycles
> system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 408992 # number of SwapReq MSHR miss cycles
> system.cpu3.dcache.SwapReq_mshr_miss_latency::total 408992 # number of SwapReq MSHR miss cycles
> system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2456005 # number of demand (read+write) MSHR miss cycles
> system.cpu3.dcache.demand_mshr_miss_latency::total 2456005 # number of demand (read+write) MSHR miss cycles
> system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2456005 # number of overall MSHR miss cycles
> system.cpu3.dcache.overall_mshr_miss_latency::total 2456005 # number of overall MSHR miss cycles
> system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003164 # mshr miss rate for ReadReq accesses
> system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003164 # mshr miss rate for ReadReq accesses
2666,2679c2808,2821
< system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002967 # mshr miss rate for demand accesses
< system.cpu3.dcache.demand_mshr_miss_rate::total 0.002967 # mshr miss rate for demand accesses
< system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002967 # mshr miss rate for overall accesses
< system.cpu3.dcache.overall_mshr_miss_rate::total 0.002967 # mshr miss rate for overall accesses
< system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6824.792208 # average ReadReq mshr miss latency
< system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6824.792208 # average ReadReq mshr miss latency
< system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13577.716981 # average WriteReq mshr miss latency
< system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13577.716981 # average WriteReq mshr miss latency
< system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7846 # average SwapReq mshr miss latency
< system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7846 # average SwapReq mshr miss latency
< system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9577.907692 # average overall mshr miss latency
< system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9577.907692 # average overall mshr miss latency
< system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9577.907692 # average overall mshr miss latency
< system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9577.907692 # average overall mshr miss latency
---
> system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002968 # mshr miss rate for demand accesses
> system.cpu3.dcache.demand_mshr_miss_rate::total 0.002968 # mshr miss rate for demand accesses
> system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002968 # mshr miss rate for overall accesses
> system.cpu3.dcache.overall_mshr_miss_rate::total 0.002968 # mshr miss rate for overall accesses
> system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6834.525974 # average ReadReq mshr miss latency
> system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6834.525974 # average ReadReq mshr miss latency
> system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13240.452830 # average WriteReq mshr miss latency
> system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13240.452830 # average WriteReq mshr miss latency
> system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7865.230769 # average SwapReq mshr miss latency
> system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7865.230769 # average SwapReq mshr miss latency
> system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9446.173077 # average overall mshr miss latency
> system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9446.173077 # average overall mshr miss latency
> system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9446.173077 # average overall mshr miss latency
> system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9446.173077 # average overall mshr miss latency