1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000111 # Number of seconds simulated
4sim_ticks 111402500 # Number of ticks simulated
5final_tick 111402500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000111 # Number of seconds simulated
4sim_ticks 111402500 # Number of ticks simulated
5final_tick 111402500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 79928 # Simulator instruction rate (inst/s)
8host_op_rate 79928 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 8175729 # Simulator tick rate (ticks/s)
10host_mem_usage 236248 # Number of bytes of host memory used
11host_seconds 13.63 # Real time elapsed on the host
| 7host_inst_rate 133234 # Simulator instruction rate (inst/s)
8host_op_rate 133234 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 13628365 # Simulator tick rate (ticks/s)
10host_mem_usage 236536 # Number of bytes of host memory used
11host_seconds 8.17 # Real time elapsed on the host
|
12sim_insts 1089093 # Number of instructions simulated
13sim_ops 1089093 # Number of ops (including micro ops) simulated
| 12sim_insts 1089093 # Number of instructions simulated
13sim_ops 1089093 # Number of ops (including micro ops) simulated
|
14system.physmem.bytes_read 43072 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 29312 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 0 # Number of bytes written to this memory
17system.physmem.num_reads 673 # Number of read requests responded to by this memory
18system.physmem.num_writes 0 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 386634052 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 263117973 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_total 386634052 # Total bandwidth to/from this memory (bytes/s)
| 14system.physmem.bytes_read::cpu0.inst 23232 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory
16system.physmem.bytes_read::cpu1.inst 896 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu2.inst 5120 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
22system.physmem.bytes_read::total 43072 # Number of bytes read from this memory
23system.physmem.bytes_inst_read::cpu0.inst 23232 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::cpu1.inst 896 # Number of instructions bytes read from this memory
25system.physmem.bytes_inst_read::cpu2.inst 5120 # Number of instructions bytes read from this memory
26system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory
27system.physmem.bytes_inst_read::total 29312 # Number of instructions bytes read from this memory
28system.physmem.num_reads::cpu0.inst 363 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu1.inst 14 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory
32system.physmem.num_reads::cpu2.inst 80 # Number of read requests responded to by this memory
33system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
36system.physmem.num_reads::total 673 # Number of read requests responded to by this memory
37system.physmem.bw_read::cpu0.inst 208541101 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu0.data 97089383 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu1.inst 8042907 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::cpu1.data 7468414 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::cpu2.inst 45959471 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_read::cpu2.data 11489868 # Total read bandwidth from this memory (bytes/s)
43system.physmem.bw_read::cpu3.inst 574493 # Total read bandwidth from this memory (bytes/s)
44system.physmem.bw_read::cpu3.data 7468414 # Total read bandwidth from this memory (bytes/s)
45system.physmem.bw_read::total 386634052 # Total read bandwidth from this memory (bytes/s)
46system.physmem.bw_inst_read::cpu0.inst 208541101 # Instruction read bandwidth from this memory (bytes/s)
47system.physmem.bw_inst_read::cpu1.inst 8042907 # Instruction read bandwidth from this memory (bytes/s)
48system.physmem.bw_inst_read::cpu2.inst 45959471 # Instruction read bandwidth from this memory (bytes/s)
49system.physmem.bw_inst_read::cpu3.inst 574493 # Instruction read bandwidth from this memory (bytes/s)
50system.physmem.bw_inst_read::total 263117973 # Instruction read bandwidth from this memory (bytes/s)
51system.physmem.bw_total::cpu0.inst 208541101 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::cpu0.data 97089383 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.bw_total::cpu1.inst 8042907 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.bw_total::cpu1.data 7468414 # Total bandwidth to/from this memory (bytes/s)
55system.physmem.bw_total::cpu2.inst 45959471 # Total bandwidth to/from this memory (bytes/s)
56system.physmem.bw_total::cpu2.data 11489868 # Total bandwidth to/from this memory (bytes/s)
57system.physmem.bw_total::cpu3.inst 574493 # Total bandwidth to/from this memory (bytes/s)
58system.physmem.bw_total::cpu3.data 7468414 # Total bandwidth to/from this memory (bytes/s)
59system.physmem.bw_total::total 386634052 # Total bandwidth to/from this memory (bytes/s)
|
23system.cpu0.workload.num_syscalls 89 # Number of system calls
24system.cpu0.numCycles 222806 # number of cpu cycles simulated
25system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
26system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
27system.cpu0.BPredUnit.lookups 87253 # Number of BP lookups
28system.cpu0.BPredUnit.condPredicted 84917 # Number of conditional branches predicted
29system.cpu0.BPredUnit.condIncorrect 1303 # Number of conditional branches incorrect
30system.cpu0.BPredUnit.BTBLookups 84794 # Number of BTB lookups
31system.cpu0.BPredUnit.BTBHits 82358 # Number of BTB hits
32system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
33system.cpu0.BPredUnit.usedRAS 518 # Number of times the RAS was used to get a target.
34system.cpu0.BPredUnit.RASInCorrect 136 # Number of incorrect RAS predictions.
35system.cpu0.fetch.icacheStallCycles 17579 # Number of cycles fetch is stalled on an Icache miss
36system.cpu0.fetch.Insts 517995 # Number of instructions fetch has processed
37system.cpu0.fetch.Branches 87253 # Number of branches that fetch encountered
38system.cpu0.fetch.predictedBranches 82876 # Number of branches that fetch has predicted taken
39system.cpu0.fetch.Cycles 170053 # Number of cycles fetch has run and was not squashing or blocked
40system.cpu0.fetch.SquashCycles 3992 # Number of cycles fetch has spent squashing
41system.cpu0.fetch.BlockedCycles 13261 # Number of cycles fetch has spent blocked
42system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
43system.cpu0.fetch.PendingTrapStallCycles 1318 # Number of stall cycles due to pending traps
44system.cpu0.fetch.CacheLines 6218 # Number of cache lines fetched
45system.cpu0.fetch.IcacheSquashes 521 # Number of outstanding Icache misses that were squashed
46system.cpu0.fetch.rateDist::samples 204756 # Number of instructions fetched each cycle (Total)
47system.cpu0.fetch.rateDist::mean 2.529816 # Number of instructions fetched each cycle (Total)
48system.cpu0.fetch.rateDist::stdev 2.210666 # Number of instructions fetched each cycle (Total)
49system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
50system.cpu0.fetch.rateDist::0 34703 16.95% 16.95% # Number of instructions fetched each cycle (Total)
51system.cpu0.fetch.rateDist::1 84234 41.14% 58.09% # Number of instructions fetched each cycle (Total)
52system.cpu0.fetch.rateDist::2 594 0.29% 58.38% # Number of instructions fetched each cycle (Total)
53system.cpu0.fetch.rateDist::3 959 0.47% 58.85% # Number of instructions fetched each cycle (Total)
54system.cpu0.fetch.rateDist::4 591 0.29% 59.13% # Number of instructions fetched each cycle (Total)
55system.cpu0.fetch.rateDist::5 80169 39.15% 98.29% # Number of instructions fetched each cycle (Total)
56system.cpu0.fetch.rateDist::6 594 0.29% 98.58% # Number of instructions fetched each cycle (Total)
57system.cpu0.fetch.rateDist::7 373 0.18% 98.76% # Number of instructions fetched each cycle (Total)
58system.cpu0.fetch.rateDist::8 2539 1.24% 100.00% # Number of instructions fetched each cycle (Total)
59system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
60system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
61system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
62system.cpu0.fetch.rateDist::total 204756 # Number of instructions fetched each cycle (Total)
63system.cpu0.fetch.branchRate 0.391610 # Number of branch fetches per cycle
64system.cpu0.fetch.rate 2.324870 # Number of inst fetches per cycle
65system.cpu0.decode.IdleCycles 18003 # Number of cycles decode is idle
66system.cpu0.decode.BlockedCycles 14874 # Number of cycles decode is blocked
67system.cpu0.decode.RunCycles 169024 # Number of cycles decode is running
68system.cpu0.decode.UnblockCycles 315 # Number of cycles decode is unblocking
69system.cpu0.decode.SquashCycles 2540 # Number of cycles decode is squashing
70system.cpu0.decode.DecodedInsts 515001 # Number of instructions handled by decode
71system.cpu0.rename.SquashCycles 2540 # Number of cycles rename is squashing
72system.cpu0.rename.IdleCycles 18709 # Number of cycles rename is idle
73system.cpu0.rename.BlockCycles 1371 # Number of cycles rename is blocking
74system.cpu0.rename.serializeStallCycles 12822 # count of cycles rename stalled for serializing inst
75system.cpu0.rename.RunCycles 168665 # Number of cycles rename is running
76system.cpu0.rename.UnblockCycles 649 # Number of cycles rename is unblocking
77system.cpu0.rename.RenamedInsts 511590 # Number of instructions processed by rename
78system.cpu0.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full
79system.cpu0.rename.LSQFullEvents 235 # Number of times rename has blocked due to LSQ full
80system.cpu0.rename.RenamedOperands 349678 # Number of destination operands rename has renamed
81system.cpu0.rename.RenameLookups 1020456 # Number of register rename lookups that rename has made
82system.cpu0.rename.int_rename_lookups 1020456 # Number of integer rename lookups
83system.cpu0.rename.CommittedMaps 335896 # Number of HB maps that are committed
84system.cpu0.rename.UndoneMaps 13782 # Number of HB maps that are undone due to squashing
85system.cpu0.rename.serializingInsts 911 # count of serializing insts renamed
86system.cpu0.rename.tempSerializingInsts 939 # count of temporary serializing insts renamed
87system.cpu0.rename.skidInsts 4054 # count of insts added to the skid buffer
88system.cpu0.memDep0.insertedLoads 163918 # Number of loads inserted to the mem dependence unit.
89system.cpu0.memDep0.insertedStores 82754 # Number of stores inserted to the mem dependence unit.
90system.cpu0.memDep0.conflictingLoads 79985 # Number of conflicting loads.
91system.cpu0.memDep0.conflictingStores 79744 # Number of conflicting stores.
92system.cpu0.iq.iqInstsAdded 427655 # Number of instructions added to the IQ (excludes non-spec)
93system.cpu0.iq.iqNonSpecInstsAdded 948 # Number of non-speculative instructions added to the IQ
94system.cpu0.iq.iqInstsIssued 424795 # Number of instructions issued
95system.cpu0.iq.iqSquashedInstsIssued 156 # Number of squashed instructions issued
96system.cpu0.iq.iqSquashedInstsExamined 11264 # Number of squashed instructions iterated over during squash; mainly for profiling
97system.cpu0.iq.iqSquashedOperandsExamined 10234 # Number of squashed operands that are examined and possibly removed from graph
98system.cpu0.iq.iqSquashedNonSpecRemoved 389 # Number of squashed non-spec instructions that were removed
99system.cpu0.iq.issued_per_cycle::samples 204756 # Number of insts issued each cycle
100system.cpu0.iq.issued_per_cycle::mean 2.074640 # Number of insts issued each cycle
101system.cpu0.iq.issued_per_cycle::stdev 1.085274 # Number of insts issued each cycle
102system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
103system.cpu0.iq.issued_per_cycle::0 33869 16.54% 16.54% # Number of insts issued each cycle
104system.cpu0.iq.issued_per_cycle::1 5212 2.55% 19.09% # Number of insts issued each cycle
105system.cpu0.iq.issued_per_cycle::2 81806 39.95% 59.04% # Number of insts issued each cycle
106system.cpu0.iq.issued_per_cycle::3 81161 39.64% 98.68% # Number of insts issued each cycle
107system.cpu0.iq.issued_per_cycle::4 1586 0.77% 99.45% # Number of insts issued each cycle
108system.cpu0.iq.issued_per_cycle::5 710 0.35% 99.80% # Number of insts issued each cycle
109system.cpu0.iq.issued_per_cycle::6 306 0.15% 99.95% # Number of insts issued each cycle
110system.cpu0.iq.issued_per_cycle::7 90 0.04% 99.99% # Number of insts issued each cycle
111system.cpu0.iq.issued_per_cycle::8 16 0.01% 100.00% # Number of insts issued each cycle
112system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
113system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
114system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
115system.cpu0.iq.issued_per_cycle::total 204756 # Number of insts issued each cycle
116system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
117system.cpu0.iq.fu_full::IntAlu 53 21.81% 21.81% # attempts to use FU when none available
118system.cpu0.iq.fu_full::IntMult 0 0.00% 21.81% # attempts to use FU when none available
119system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.81% # attempts to use FU when none available
120system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.81% # attempts to use FU when none available
121system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.81% # attempts to use FU when none available
122system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.81% # attempts to use FU when none available
123system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.81% # attempts to use FU when none available
124system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.81% # attempts to use FU when none available
125system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.81% # attempts to use FU when none available
126system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.81% # attempts to use FU when none available
127system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.81% # attempts to use FU when none available
128system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.81% # attempts to use FU when none available
129system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.81% # attempts to use FU when none available
130system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.81% # attempts to use FU when none available
131system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.81% # attempts to use FU when none available
132system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.81% # attempts to use FU when none available
133system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.81% # attempts to use FU when none available
134system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.81% # attempts to use FU when none available
135system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.81% # attempts to use FU when none available
136system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.81% # attempts to use FU when none available
137system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.81% # attempts to use FU when none available
138system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.81% # attempts to use FU when none available
139system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.81% # attempts to use FU when none available
140system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.81% # attempts to use FU when none available
141system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.81% # attempts to use FU when none available
142system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.81% # attempts to use FU when none available
143system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.81% # attempts to use FU when none available
144system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.81% # attempts to use FU when none available
145system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.81% # attempts to use FU when none available
146system.cpu0.iq.fu_full::MemRead 78 32.10% 53.91% # attempts to use FU when none available
147system.cpu0.iq.fu_full::MemWrite 112 46.09% 100.00% # attempts to use FU when none available
148system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
149system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
150system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
151system.cpu0.iq.FU_type_0::IntAlu 179222 42.19% 42.19% # Type of FU issued
152system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.19% # Type of FU issued
153system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.19% # Type of FU issued
154system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.19% # Type of FU issued
155system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.19% # Type of FU issued
156system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.19% # Type of FU issued
157system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.19% # Type of FU issued
158system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.19% # Type of FU issued
159system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.19% # Type of FU issued
160system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.19% # Type of FU issued
161system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.19% # Type of FU issued
162system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.19% # Type of FU issued
163system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.19% # Type of FU issued
164system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.19% # Type of FU issued
165system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.19% # Type of FU issued
166system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.19% # Type of FU issued
167system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.19% # Type of FU issued
168system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.19% # Type of FU issued
169system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.19% # Type of FU issued
170system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.19% # Type of FU issued
171system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.19% # Type of FU issued
172system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.19% # Type of FU issued
173system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.19% # Type of FU issued
174system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.19% # Type of FU issued
175system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.19% # Type of FU issued
176system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.19% # Type of FU issued
177system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.19% # Type of FU issued
178system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.19% # Type of FU issued
179system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.19% # Type of FU issued
180system.cpu0.iq.FU_type_0::MemRead 163383 38.46% 80.65% # Type of FU issued
181system.cpu0.iq.FU_type_0::MemWrite 82190 19.35% 100.00% # Type of FU issued
182system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
183system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
184system.cpu0.iq.FU_type_0::total 424795 # Type of FU issued
185system.cpu0.iq.rate 1.906569 # Inst issue rate
186system.cpu0.iq.fu_busy_cnt 243 # FU busy when requested
187system.cpu0.iq.fu_busy_rate 0.000572 # FU busy rate (busy events/executed inst)
188system.cpu0.iq.int_inst_queue_reads 1054745 # Number of integer instruction queue reads
189system.cpu0.iq.int_inst_queue_writes 439928 # Number of integer instruction queue writes
190system.cpu0.iq.int_inst_queue_wakeup_accesses 422836 # Number of integer instruction queue wakeup accesses
191system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
192system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
193system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
194system.cpu0.iq.int_alu_accesses 425038 # Number of integer alu accesses
195system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
196system.cpu0.iew.lsq.thread0.forwLoads 79492 # Number of loads that had data forwarded from stores
197system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
198system.cpu0.iew.lsq.thread0.squashedLoads 2386 # Number of loads squashed
199system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
200system.cpu0.iew.lsq.thread0.memOrderViolation 61 # Number of memory ordering violations
201system.cpu0.iew.lsq.thread0.squashedStores 1482 # Number of stores squashed
202system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
203system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
204system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
205system.cpu0.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked
206system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
207system.cpu0.iew.iewSquashCycles 2540 # Number of cycles IEW is squashing
208system.cpu0.iew.iewBlockCycles 996 # Number of cycles IEW is blocking
209system.cpu0.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking
210system.cpu0.iew.iewDispatchedInsts 509141 # Number of instructions dispatched to IQ
211system.cpu0.iew.iewDispSquashedInsts 346 # Number of squashed instructions skipped by dispatch
212system.cpu0.iew.iewDispLoadInsts 163918 # Number of dispatched load instructions
213system.cpu0.iew.iewDispStoreInsts 82754 # Number of dispatched store instructions
214system.cpu0.iew.iewDispNonSpecInsts 837 # Number of dispatched non-speculative instructions
215system.cpu0.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall
216system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
217system.cpu0.iew.memOrderViolationEvents 61 # Number of memory order violations
218system.cpu0.iew.predictedTakenIncorrect 382 # Number of branches that were predicted taken incorrectly
219system.cpu0.iew.predictedNotTakenIncorrect 1141 # Number of branches that were predicted not taken incorrectly
220system.cpu0.iew.branchMispredicts 1523 # Number of branch mispredicts detected at execute
221system.cpu0.iew.iewExecutedInsts 423658 # Number of executed instructions
222system.cpu0.iew.iewExecLoadInsts 163081 # Number of load instructions executed
223system.cpu0.iew.iewExecSquashedInsts 1137 # Number of squashed instructions skipped in execute
224system.cpu0.iew.exec_swp 0 # number of swp insts executed
225system.cpu0.iew.exec_nop 80538 # number of nop insts executed
226system.cpu0.iew.exec_refs 245123 # number of memory reference insts executed
227system.cpu0.iew.exec_branches 84187 # Number of branches executed
228system.cpu0.iew.exec_stores 82042 # Number of stores executed
229system.cpu0.iew.exec_rate 1.901466 # Inst execution rate
230system.cpu0.iew.wb_sent 423189 # cumulative count of insts sent to commit
231system.cpu0.iew.wb_count 422836 # cumulative count of insts written-back
232system.cpu0.iew.wb_producers 250585 # num instructions producing a value
233system.cpu0.iew.wb_consumers 253105 # num instructions consuming a value
234system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
235system.cpu0.iew.wb_rate 1.897777 # insts written-back per cycle
236system.cpu0.iew.wb_fanout 0.990044 # average fanout of values written-back
237system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
238system.cpu0.commit.commitCommittedInsts 496189 # The number of committed instructions
239system.cpu0.commit.commitCommittedOps 496189 # The number of committed instructions
240system.cpu0.commit.commitSquashedInsts 12929 # The number of squashed insts skipped by commit
241system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
242system.cpu0.commit.branchMispredicts 1303 # The number of times a branch was mispredicted
243system.cpu0.commit.committed_per_cycle::samples 202233 # Number of insts commited each cycle
244system.cpu0.commit.committed_per_cycle::mean 2.453551 # Number of insts commited each cycle
245system.cpu0.commit.committed_per_cycle::stdev 2.134267 # Number of insts commited each cycle
246system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
247system.cpu0.commit.committed_per_cycle::0 34442 17.03% 17.03% # Number of insts commited each cycle
248system.cpu0.commit.committed_per_cycle::1 83893 41.48% 58.51% # Number of insts commited each cycle
249system.cpu0.commit.committed_per_cycle::2 2396 1.18% 59.70% # Number of insts commited each cycle
250system.cpu0.commit.committed_per_cycle::3 690 0.34% 60.04% # Number of insts commited each cycle
251system.cpu0.commit.committed_per_cycle::4 548 0.27% 60.31% # Number of insts commited each cycle
252system.cpu0.commit.committed_per_cycle::5 79225 39.18% 99.49% # Number of insts commited each cycle
253system.cpu0.commit.committed_per_cycle::6 480 0.24% 99.72% # Number of insts commited each cycle
254system.cpu0.commit.committed_per_cycle::7 235 0.12% 99.84% # Number of insts commited each cycle
255system.cpu0.commit.committed_per_cycle::8 324 0.16% 100.00% # Number of insts commited each cycle
256system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
257system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
258system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
259system.cpu0.commit.committed_per_cycle::total 202233 # Number of insts commited each cycle
260system.cpu0.commit.committedInsts 496189 # Number of instructions committed
261system.cpu0.commit.committedOps 496189 # Number of ops (including micro ops) committed
262system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
263system.cpu0.commit.refs 242804 # Number of memory references committed
264system.cpu0.commit.loads 161532 # Number of loads committed
265system.cpu0.commit.membars 84 # Number of memory barriers committed
266system.cpu0.commit.branches 83160 # Number of branches committed
267system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
268system.cpu0.commit.int_insts 334226 # Number of committed integer instructions.
269system.cpu0.commit.function_calls 223 # Number of function calls committed.
270system.cpu0.commit.bw_lim_events 324 # number cycles where commit BW limit reached
271system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
272system.cpu0.rob.rob_reads 709866 # The number of ROB reads
273system.cpu0.rob.rob_writes 1020791 # The number of ROB writes
274system.cpu0.timesIdled 320 # Number of times that the entire CPU went into an idle state and unscheduled itself
275system.cpu0.idleCycles 18050 # Total number of cycles that the CPU has spent unscheduled due to idling
276system.cpu0.committedInsts 416214 # Number of Instructions Simulated
277system.cpu0.committedOps 416214 # Number of Ops (including micro ops) Simulated
278system.cpu0.committedInsts_total 416214 # Number of Instructions Simulated
279system.cpu0.cpi 0.535316 # CPI: Cycles Per Instruction
280system.cpu0.cpi_total 0.535316 # CPI: Total CPI of All Threads
281system.cpu0.ipc 1.868056 # IPC: Instructions Per Cycle
282system.cpu0.ipc_total 1.868056 # IPC: Total IPC of All Threads
283system.cpu0.int_regfile_reads 757980 # number of integer regfile reads
284system.cpu0.int_regfile_writes 341432 # number of integer regfile writes
285system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
286system.cpu0.misc_regfile_reads 246952 # number of misc regfile reads
287system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
288system.cpu0.icache.replacements 300 # number of replacements
289system.cpu0.icache.tagsinuse 248.673809 # Cycle average of tags in use
290system.cpu0.icache.total_refs 5459 # Total number of references to valid blocks.
291system.cpu0.icache.sampled_refs 593 # Sample count of references to valid blocks.
292system.cpu0.icache.avg_refs 9.205734 # Average number of references to valid blocks.
293system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
294system.cpu0.icache.occ_blocks::cpu0.inst 248.673809 # Average occupied blocks per requestor
295system.cpu0.icache.occ_percent::cpu0.inst 0.485691 # Average percentage of cache occupancy
296system.cpu0.icache.occ_percent::total 0.485691 # Average percentage of cache occupancy
297system.cpu0.icache.ReadReq_hits::cpu0.inst 5459 # number of ReadReq hits
298system.cpu0.icache.ReadReq_hits::total 5459 # number of ReadReq hits
299system.cpu0.icache.demand_hits::cpu0.inst 5459 # number of demand (read+write) hits
300system.cpu0.icache.demand_hits::total 5459 # number of demand (read+write) hits
301system.cpu0.icache.overall_hits::cpu0.inst 5459 # number of overall hits
302system.cpu0.icache.overall_hits::total 5459 # number of overall hits
303system.cpu0.icache.ReadReq_misses::cpu0.inst 759 # number of ReadReq misses
304system.cpu0.icache.ReadReq_misses::total 759 # number of ReadReq misses
305system.cpu0.icache.demand_misses::cpu0.inst 759 # number of demand (read+write) misses
306system.cpu0.icache.demand_misses::total 759 # number of demand (read+write) misses
307system.cpu0.icache.overall_misses::cpu0.inst 759 # number of overall misses
308system.cpu0.icache.overall_misses::total 759 # number of overall misses
309system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 29159500 # number of ReadReq miss cycles
310system.cpu0.icache.ReadReq_miss_latency::total 29159500 # number of ReadReq miss cycles
311system.cpu0.icache.demand_miss_latency::cpu0.inst 29159500 # number of demand (read+write) miss cycles
312system.cpu0.icache.demand_miss_latency::total 29159500 # number of demand (read+write) miss cycles
313system.cpu0.icache.overall_miss_latency::cpu0.inst 29159500 # number of overall miss cycles
314system.cpu0.icache.overall_miss_latency::total 29159500 # number of overall miss cycles
315system.cpu0.icache.ReadReq_accesses::cpu0.inst 6218 # number of ReadReq accesses(hits+misses)
316system.cpu0.icache.ReadReq_accesses::total 6218 # number of ReadReq accesses(hits+misses)
317system.cpu0.icache.demand_accesses::cpu0.inst 6218 # number of demand (read+write) accesses
318system.cpu0.icache.demand_accesses::total 6218 # number of demand (read+write) accesses
319system.cpu0.icache.overall_accesses::cpu0.inst 6218 # number of overall (read+write) accesses
320system.cpu0.icache.overall_accesses::total 6218 # number of overall (read+write) accesses
321system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.122065 # miss rate for ReadReq accesses
| 60system.cpu0.workload.num_syscalls 89 # Number of system calls
61system.cpu0.numCycles 222806 # number of cpu cycles simulated
62system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
63system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
64system.cpu0.BPredUnit.lookups 87253 # Number of BP lookups
65system.cpu0.BPredUnit.condPredicted 84917 # Number of conditional branches predicted
66system.cpu0.BPredUnit.condIncorrect 1303 # Number of conditional branches incorrect
67system.cpu0.BPredUnit.BTBLookups 84794 # Number of BTB lookups
68system.cpu0.BPredUnit.BTBHits 82358 # Number of BTB hits
69system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
70system.cpu0.BPredUnit.usedRAS 518 # Number of times the RAS was used to get a target.
71system.cpu0.BPredUnit.RASInCorrect 136 # Number of incorrect RAS predictions.
72system.cpu0.fetch.icacheStallCycles 17579 # Number of cycles fetch is stalled on an Icache miss
73system.cpu0.fetch.Insts 517995 # Number of instructions fetch has processed
74system.cpu0.fetch.Branches 87253 # Number of branches that fetch encountered
75system.cpu0.fetch.predictedBranches 82876 # Number of branches that fetch has predicted taken
76system.cpu0.fetch.Cycles 170053 # Number of cycles fetch has run and was not squashing or blocked
77system.cpu0.fetch.SquashCycles 3992 # Number of cycles fetch has spent squashing
78system.cpu0.fetch.BlockedCycles 13261 # Number of cycles fetch has spent blocked
79system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
80system.cpu0.fetch.PendingTrapStallCycles 1318 # Number of stall cycles due to pending traps
81system.cpu0.fetch.CacheLines 6218 # Number of cache lines fetched
82system.cpu0.fetch.IcacheSquashes 521 # Number of outstanding Icache misses that were squashed
83system.cpu0.fetch.rateDist::samples 204756 # Number of instructions fetched each cycle (Total)
84system.cpu0.fetch.rateDist::mean 2.529816 # Number of instructions fetched each cycle (Total)
85system.cpu0.fetch.rateDist::stdev 2.210666 # Number of instructions fetched each cycle (Total)
86system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
87system.cpu0.fetch.rateDist::0 34703 16.95% 16.95% # Number of instructions fetched each cycle (Total)
88system.cpu0.fetch.rateDist::1 84234 41.14% 58.09% # Number of instructions fetched each cycle (Total)
89system.cpu0.fetch.rateDist::2 594 0.29% 58.38% # Number of instructions fetched each cycle (Total)
90system.cpu0.fetch.rateDist::3 959 0.47% 58.85% # Number of instructions fetched each cycle (Total)
91system.cpu0.fetch.rateDist::4 591 0.29% 59.13% # Number of instructions fetched each cycle (Total)
92system.cpu0.fetch.rateDist::5 80169 39.15% 98.29% # Number of instructions fetched each cycle (Total)
93system.cpu0.fetch.rateDist::6 594 0.29% 98.58% # Number of instructions fetched each cycle (Total)
94system.cpu0.fetch.rateDist::7 373 0.18% 98.76% # Number of instructions fetched each cycle (Total)
95system.cpu0.fetch.rateDist::8 2539 1.24% 100.00% # Number of instructions fetched each cycle (Total)
96system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
97system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
98system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
99system.cpu0.fetch.rateDist::total 204756 # Number of instructions fetched each cycle (Total)
100system.cpu0.fetch.branchRate 0.391610 # Number of branch fetches per cycle
101system.cpu0.fetch.rate 2.324870 # Number of inst fetches per cycle
102system.cpu0.decode.IdleCycles 18003 # Number of cycles decode is idle
103system.cpu0.decode.BlockedCycles 14874 # Number of cycles decode is blocked
104system.cpu0.decode.RunCycles 169024 # Number of cycles decode is running
105system.cpu0.decode.UnblockCycles 315 # Number of cycles decode is unblocking
106system.cpu0.decode.SquashCycles 2540 # Number of cycles decode is squashing
107system.cpu0.decode.DecodedInsts 515001 # Number of instructions handled by decode
108system.cpu0.rename.SquashCycles 2540 # Number of cycles rename is squashing
109system.cpu0.rename.IdleCycles 18709 # Number of cycles rename is idle
110system.cpu0.rename.BlockCycles 1371 # Number of cycles rename is blocking
111system.cpu0.rename.serializeStallCycles 12822 # count of cycles rename stalled for serializing inst
112system.cpu0.rename.RunCycles 168665 # Number of cycles rename is running
113system.cpu0.rename.UnblockCycles 649 # Number of cycles rename is unblocking
114system.cpu0.rename.RenamedInsts 511590 # Number of instructions processed by rename
115system.cpu0.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full
116system.cpu0.rename.LSQFullEvents 235 # Number of times rename has blocked due to LSQ full
117system.cpu0.rename.RenamedOperands 349678 # Number of destination operands rename has renamed
118system.cpu0.rename.RenameLookups 1020456 # Number of register rename lookups that rename has made
119system.cpu0.rename.int_rename_lookups 1020456 # Number of integer rename lookups
120system.cpu0.rename.CommittedMaps 335896 # Number of HB maps that are committed
121system.cpu0.rename.UndoneMaps 13782 # Number of HB maps that are undone due to squashing
122system.cpu0.rename.serializingInsts 911 # count of serializing insts renamed
123system.cpu0.rename.tempSerializingInsts 939 # count of temporary serializing insts renamed
124system.cpu0.rename.skidInsts 4054 # count of insts added to the skid buffer
125system.cpu0.memDep0.insertedLoads 163918 # Number of loads inserted to the mem dependence unit.
126system.cpu0.memDep0.insertedStores 82754 # Number of stores inserted to the mem dependence unit.
127system.cpu0.memDep0.conflictingLoads 79985 # Number of conflicting loads.
128system.cpu0.memDep0.conflictingStores 79744 # Number of conflicting stores.
129system.cpu0.iq.iqInstsAdded 427655 # Number of instructions added to the IQ (excludes non-spec)
130system.cpu0.iq.iqNonSpecInstsAdded 948 # Number of non-speculative instructions added to the IQ
131system.cpu0.iq.iqInstsIssued 424795 # Number of instructions issued
132system.cpu0.iq.iqSquashedInstsIssued 156 # Number of squashed instructions issued
133system.cpu0.iq.iqSquashedInstsExamined 11264 # Number of squashed instructions iterated over during squash; mainly for profiling
134system.cpu0.iq.iqSquashedOperandsExamined 10234 # Number of squashed operands that are examined and possibly removed from graph
135system.cpu0.iq.iqSquashedNonSpecRemoved 389 # Number of squashed non-spec instructions that were removed
136system.cpu0.iq.issued_per_cycle::samples 204756 # Number of insts issued each cycle
137system.cpu0.iq.issued_per_cycle::mean 2.074640 # Number of insts issued each cycle
138system.cpu0.iq.issued_per_cycle::stdev 1.085274 # Number of insts issued each cycle
139system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
140system.cpu0.iq.issued_per_cycle::0 33869 16.54% 16.54% # Number of insts issued each cycle
141system.cpu0.iq.issued_per_cycle::1 5212 2.55% 19.09% # Number of insts issued each cycle
142system.cpu0.iq.issued_per_cycle::2 81806 39.95% 59.04% # Number of insts issued each cycle
143system.cpu0.iq.issued_per_cycle::3 81161 39.64% 98.68% # Number of insts issued each cycle
144system.cpu0.iq.issued_per_cycle::4 1586 0.77% 99.45% # Number of insts issued each cycle
145system.cpu0.iq.issued_per_cycle::5 710 0.35% 99.80% # Number of insts issued each cycle
146system.cpu0.iq.issued_per_cycle::6 306 0.15% 99.95% # Number of insts issued each cycle
147system.cpu0.iq.issued_per_cycle::7 90 0.04% 99.99% # Number of insts issued each cycle
148system.cpu0.iq.issued_per_cycle::8 16 0.01% 100.00% # Number of insts issued each cycle
149system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
150system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
151system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
152system.cpu0.iq.issued_per_cycle::total 204756 # Number of insts issued each cycle
153system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
154system.cpu0.iq.fu_full::IntAlu 53 21.81% 21.81% # attempts to use FU when none available
155system.cpu0.iq.fu_full::IntMult 0 0.00% 21.81% # attempts to use FU when none available
156system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.81% # attempts to use FU when none available
157system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.81% # attempts to use FU when none available
158system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.81% # attempts to use FU when none available
159system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.81% # attempts to use FU when none available
160system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.81% # attempts to use FU when none available
161system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.81% # attempts to use FU when none available
162system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.81% # attempts to use FU when none available
163system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.81% # attempts to use FU when none available
164system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.81% # attempts to use FU when none available
165system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.81% # attempts to use FU when none available
166system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.81% # attempts to use FU when none available
167system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.81% # attempts to use FU when none available
168system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.81% # attempts to use FU when none available
169system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.81% # attempts to use FU when none available
170system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.81% # attempts to use FU when none available
171system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.81% # attempts to use FU when none available
172system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.81% # attempts to use FU when none available
173system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.81% # attempts to use FU when none available
174system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.81% # attempts to use FU when none available
175system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.81% # attempts to use FU when none available
176system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.81% # attempts to use FU when none available
177system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.81% # attempts to use FU when none available
178system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.81% # attempts to use FU when none available
179system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.81% # attempts to use FU when none available
180system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.81% # attempts to use FU when none available
181system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.81% # attempts to use FU when none available
182system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.81% # attempts to use FU when none available
183system.cpu0.iq.fu_full::MemRead 78 32.10% 53.91% # attempts to use FU when none available
184system.cpu0.iq.fu_full::MemWrite 112 46.09% 100.00% # attempts to use FU when none available
185system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
186system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
187system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
188system.cpu0.iq.FU_type_0::IntAlu 179222 42.19% 42.19% # Type of FU issued
189system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.19% # Type of FU issued
190system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.19% # Type of FU issued
191system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.19% # Type of FU issued
192system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.19% # Type of FU issued
193system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.19% # Type of FU issued
194system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.19% # Type of FU issued
195system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.19% # Type of FU issued
196system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.19% # Type of FU issued
197system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.19% # Type of FU issued
198system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.19% # Type of FU issued
199system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.19% # Type of FU issued
200system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.19% # Type of FU issued
201system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.19% # Type of FU issued
202system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.19% # Type of FU issued
203system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.19% # Type of FU issued
204system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.19% # Type of FU issued
205system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.19% # Type of FU issued
206system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.19% # Type of FU issued
207system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.19% # Type of FU issued
208system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.19% # Type of FU issued
209system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.19% # Type of FU issued
210system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.19% # Type of FU issued
211system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.19% # Type of FU issued
212system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.19% # Type of FU issued
213system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.19% # Type of FU issued
214system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.19% # Type of FU issued
215system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.19% # Type of FU issued
216system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.19% # Type of FU issued
217system.cpu0.iq.FU_type_0::MemRead 163383 38.46% 80.65% # Type of FU issued
218system.cpu0.iq.FU_type_0::MemWrite 82190 19.35% 100.00% # Type of FU issued
219system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
220system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
221system.cpu0.iq.FU_type_0::total 424795 # Type of FU issued
222system.cpu0.iq.rate 1.906569 # Inst issue rate
223system.cpu0.iq.fu_busy_cnt 243 # FU busy when requested
224system.cpu0.iq.fu_busy_rate 0.000572 # FU busy rate (busy events/executed inst)
225system.cpu0.iq.int_inst_queue_reads 1054745 # Number of integer instruction queue reads
226system.cpu0.iq.int_inst_queue_writes 439928 # Number of integer instruction queue writes
227system.cpu0.iq.int_inst_queue_wakeup_accesses 422836 # Number of integer instruction queue wakeup accesses
228system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
229system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
230system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
231system.cpu0.iq.int_alu_accesses 425038 # Number of integer alu accesses
232system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
233system.cpu0.iew.lsq.thread0.forwLoads 79492 # Number of loads that had data forwarded from stores
234system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
235system.cpu0.iew.lsq.thread0.squashedLoads 2386 # Number of loads squashed
236system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
237system.cpu0.iew.lsq.thread0.memOrderViolation 61 # Number of memory ordering violations
238system.cpu0.iew.lsq.thread0.squashedStores 1482 # Number of stores squashed
239system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
240system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
241system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
242system.cpu0.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked
243system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
244system.cpu0.iew.iewSquashCycles 2540 # Number of cycles IEW is squashing
245system.cpu0.iew.iewBlockCycles 996 # Number of cycles IEW is blocking
246system.cpu0.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking
247system.cpu0.iew.iewDispatchedInsts 509141 # Number of instructions dispatched to IQ
248system.cpu0.iew.iewDispSquashedInsts 346 # Number of squashed instructions skipped by dispatch
249system.cpu0.iew.iewDispLoadInsts 163918 # Number of dispatched load instructions
250system.cpu0.iew.iewDispStoreInsts 82754 # Number of dispatched store instructions
251system.cpu0.iew.iewDispNonSpecInsts 837 # Number of dispatched non-speculative instructions
252system.cpu0.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall
253system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
254system.cpu0.iew.memOrderViolationEvents 61 # Number of memory order violations
255system.cpu0.iew.predictedTakenIncorrect 382 # Number of branches that were predicted taken incorrectly
256system.cpu0.iew.predictedNotTakenIncorrect 1141 # Number of branches that were predicted not taken incorrectly
257system.cpu0.iew.branchMispredicts 1523 # Number of branch mispredicts detected at execute
258system.cpu0.iew.iewExecutedInsts 423658 # Number of executed instructions
259system.cpu0.iew.iewExecLoadInsts 163081 # Number of load instructions executed
260system.cpu0.iew.iewExecSquashedInsts 1137 # Number of squashed instructions skipped in execute
261system.cpu0.iew.exec_swp 0 # number of swp insts executed
262system.cpu0.iew.exec_nop 80538 # number of nop insts executed
263system.cpu0.iew.exec_refs 245123 # number of memory reference insts executed
264system.cpu0.iew.exec_branches 84187 # Number of branches executed
265system.cpu0.iew.exec_stores 82042 # Number of stores executed
266system.cpu0.iew.exec_rate 1.901466 # Inst execution rate
267system.cpu0.iew.wb_sent 423189 # cumulative count of insts sent to commit
268system.cpu0.iew.wb_count 422836 # cumulative count of insts written-back
269system.cpu0.iew.wb_producers 250585 # num instructions producing a value
270system.cpu0.iew.wb_consumers 253105 # num instructions consuming a value
271system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
272system.cpu0.iew.wb_rate 1.897777 # insts written-back per cycle
273system.cpu0.iew.wb_fanout 0.990044 # average fanout of values written-back
274system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
275system.cpu0.commit.commitCommittedInsts 496189 # The number of committed instructions
276system.cpu0.commit.commitCommittedOps 496189 # The number of committed instructions
277system.cpu0.commit.commitSquashedInsts 12929 # The number of squashed insts skipped by commit
278system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
279system.cpu0.commit.branchMispredicts 1303 # The number of times a branch was mispredicted
280system.cpu0.commit.committed_per_cycle::samples 202233 # Number of insts commited each cycle
281system.cpu0.commit.committed_per_cycle::mean 2.453551 # Number of insts commited each cycle
282system.cpu0.commit.committed_per_cycle::stdev 2.134267 # Number of insts commited each cycle
283system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
284system.cpu0.commit.committed_per_cycle::0 34442 17.03% 17.03% # Number of insts commited each cycle
285system.cpu0.commit.committed_per_cycle::1 83893 41.48% 58.51% # Number of insts commited each cycle
286system.cpu0.commit.committed_per_cycle::2 2396 1.18% 59.70% # Number of insts commited each cycle
287system.cpu0.commit.committed_per_cycle::3 690 0.34% 60.04% # Number of insts commited each cycle
288system.cpu0.commit.committed_per_cycle::4 548 0.27% 60.31% # Number of insts commited each cycle
289system.cpu0.commit.committed_per_cycle::5 79225 39.18% 99.49% # Number of insts commited each cycle
290system.cpu0.commit.committed_per_cycle::6 480 0.24% 99.72% # Number of insts commited each cycle
291system.cpu0.commit.committed_per_cycle::7 235 0.12% 99.84% # Number of insts commited each cycle
292system.cpu0.commit.committed_per_cycle::8 324 0.16% 100.00% # Number of insts commited each cycle
293system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
294system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
295system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
296system.cpu0.commit.committed_per_cycle::total 202233 # Number of insts commited each cycle
297system.cpu0.commit.committedInsts 496189 # Number of instructions committed
298system.cpu0.commit.committedOps 496189 # Number of ops (including micro ops) committed
299system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
300system.cpu0.commit.refs 242804 # Number of memory references committed
301system.cpu0.commit.loads 161532 # Number of loads committed
302system.cpu0.commit.membars 84 # Number of memory barriers committed
303system.cpu0.commit.branches 83160 # Number of branches committed
304system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
305system.cpu0.commit.int_insts 334226 # Number of committed integer instructions.
306system.cpu0.commit.function_calls 223 # Number of function calls committed.
307system.cpu0.commit.bw_lim_events 324 # number cycles where commit BW limit reached
308system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
309system.cpu0.rob.rob_reads 709866 # The number of ROB reads
310system.cpu0.rob.rob_writes 1020791 # The number of ROB writes
311system.cpu0.timesIdled 320 # Number of times that the entire CPU went into an idle state and unscheduled itself
312system.cpu0.idleCycles 18050 # Total number of cycles that the CPU has spent unscheduled due to idling
313system.cpu0.committedInsts 416214 # Number of Instructions Simulated
314system.cpu0.committedOps 416214 # Number of Ops (including micro ops) Simulated
315system.cpu0.committedInsts_total 416214 # Number of Instructions Simulated
316system.cpu0.cpi 0.535316 # CPI: Cycles Per Instruction
317system.cpu0.cpi_total 0.535316 # CPI: Total CPI of All Threads
318system.cpu0.ipc 1.868056 # IPC: Instructions Per Cycle
319system.cpu0.ipc_total 1.868056 # IPC: Total IPC of All Threads
320system.cpu0.int_regfile_reads 757980 # number of integer regfile reads
321system.cpu0.int_regfile_writes 341432 # number of integer regfile writes
322system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
323system.cpu0.misc_regfile_reads 246952 # number of misc regfile reads
324system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
325system.cpu0.icache.replacements 300 # number of replacements
326system.cpu0.icache.tagsinuse 248.673809 # Cycle average of tags in use
327system.cpu0.icache.total_refs 5459 # Total number of references to valid blocks.
328system.cpu0.icache.sampled_refs 593 # Sample count of references to valid blocks.
329system.cpu0.icache.avg_refs 9.205734 # Average number of references to valid blocks.
330system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
331system.cpu0.icache.occ_blocks::cpu0.inst 248.673809 # Average occupied blocks per requestor
332system.cpu0.icache.occ_percent::cpu0.inst 0.485691 # Average percentage of cache occupancy
333system.cpu0.icache.occ_percent::total 0.485691 # Average percentage of cache occupancy
334system.cpu0.icache.ReadReq_hits::cpu0.inst 5459 # number of ReadReq hits
335system.cpu0.icache.ReadReq_hits::total 5459 # number of ReadReq hits
336system.cpu0.icache.demand_hits::cpu0.inst 5459 # number of demand (read+write) hits
337system.cpu0.icache.demand_hits::total 5459 # number of demand (read+write) hits
338system.cpu0.icache.overall_hits::cpu0.inst 5459 # number of overall hits
339system.cpu0.icache.overall_hits::total 5459 # number of overall hits
340system.cpu0.icache.ReadReq_misses::cpu0.inst 759 # number of ReadReq misses
341system.cpu0.icache.ReadReq_misses::total 759 # number of ReadReq misses
342system.cpu0.icache.demand_misses::cpu0.inst 759 # number of demand (read+write) misses
343system.cpu0.icache.demand_misses::total 759 # number of demand (read+write) misses
344system.cpu0.icache.overall_misses::cpu0.inst 759 # number of overall misses
345system.cpu0.icache.overall_misses::total 759 # number of overall misses
346system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 29159500 # number of ReadReq miss cycles
347system.cpu0.icache.ReadReq_miss_latency::total 29159500 # number of ReadReq miss cycles
348system.cpu0.icache.demand_miss_latency::cpu0.inst 29159500 # number of demand (read+write) miss cycles
349system.cpu0.icache.demand_miss_latency::total 29159500 # number of demand (read+write) miss cycles
350system.cpu0.icache.overall_miss_latency::cpu0.inst 29159500 # number of overall miss cycles
351system.cpu0.icache.overall_miss_latency::total 29159500 # number of overall miss cycles
352system.cpu0.icache.ReadReq_accesses::cpu0.inst 6218 # number of ReadReq accesses(hits+misses)
353system.cpu0.icache.ReadReq_accesses::total 6218 # number of ReadReq accesses(hits+misses)
354system.cpu0.icache.demand_accesses::cpu0.inst 6218 # number of demand (read+write) accesses
355system.cpu0.icache.demand_accesses::total 6218 # number of demand (read+write) accesses
356system.cpu0.icache.overall_accesses::cpu0.inst 6218 # number of overall (read+write) accesses
357system.cpu0.icache.overall_accesses::total 6218 # number of overall (read+write) accesses
358system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.122065 # miss rate for ReadReq accesses
|
| 359system.cpu0.icache.ReadReq_miss_rate::total 0.122065 # miss rate for ReadReq accesses
|
322system.cpu0.icache.demand_miss_rate::cpu0.inst 0.122065 # miss rate for demand accesses
| 360system.cpu0.icache.demand_miss_rate::cpu0.inst 0.122065 # miss rate for demand accesses
|
| 361system.cpu0.icache.demand_miss_rate::total 0.122065 # miss rate for demand accesses
|
323system.cpu0.icache.overall_miss_rate::cpu0.inst 0.122065 # miss rate for overall accesses
| 362system.cpu0.icache.overall_miss_rate::cpu0.inst 0.122065 # miss rate for overall accesses
|
| 363system.cpu0.icache.overall_miss_rate::total 0.122065 # miss rate for overall accesses
|
324system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38418.313570 # average ReadReq miss latency
| 364system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38418.313570 # average ReadReq miss latency
|
| 365system.cpu0.icache.ReadReq_avg_miss_latency::total 38418.313570 # average ReadReq miss latency
|
325system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38418.313570 # average overall miss latency
| 366system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38418.313570 # average overall miss latency
|
| 367system.cpu0.icache.demand_avg_miss_latency::total 38418.313570 # average overall miss latency
|
326system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38418.313570 # average overall miss latency
| 368system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38418.313570 # average overall miss latency
|
| 369system.cpu0.icache.overall_avg_miss_latency::total 38418.313570 # average overall miss latency
|
327system.cpu0.icache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked
328system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
329system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked
330system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
331system.cpu0.icache.avg_blocked_cycles::no_mshrs 15500 # average number of cycles each access was blocked
332system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
333system.cpu0.icache.fast_writes 0 # number of fast writes performed
334system.cpu0.icache.cache_copies 0 # number of cache copies performed
335system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 165 # number of ReadReq MSHR hits
336system.cpu0.icache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits
337system.cpu0.icache.demand_mshr_hits::cpu0.inst 165 # number of demand (read+write) MSHR hits
338system.cpu0.icache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits
339system.cpu0.icache.overall_mshr_hits::cpu0.inst 165 # number of overall MSHR hits
340system.cpu0.icache.overall_mshr_hits::total 165 # number of overall MSHR hits
341system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 594 # number of ReadReq MSHR misses
342system.cpu0.icache.ReadReq_mshr_misses::total 594 # number of ReadReq MSHR misses
343system.cpu0.icache.demand_mshr_misses::cpu0.inst 594 # number of demand (read+write) MSHR misses
344system.cpu0.icache.demand_mshr_misses::total 594 # number of demand (read+write) MSHR misses
345system.cpu0.icache.overall_mshr_misses::cpu0.inst 594 # number of overall MSHR misses
346system.cpu0.icache.overall_mshr_misses::total 594 # number of overall MSHR misses
347system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21891000 # number of ReadReq MSHR miss cycles
348system.cpu0.icache.ReadReq_mshr_miss_latency::total 21891000 # number of ReadReq MSHR miss cycles
349system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21891000 # number of demand (read+write) MSHR miss cycles
350system.cpu0.icache.demand_mshr_miss_latency::total 21891000 # number of demand (read+write) MSHR miss cycles
351system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21891000 # number of overall MSHR miss cycles
352system.cpu0.icache.overall_mshr_miss_latency::total 21891000 # number of overall MSHR miss cycles
353system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for ReadReq accesses
| 370system.cpu0.icache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked
371system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
372system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked
373system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
374system.cpu0.icache.avg_blocked_cycles::no_mshrs 15500 # average number of cycles each access was blocked
375system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
376system.cpu0.icache.fast_writes 0 # number of fast writes performed
377system.cpu0.icache.cache_copies 0 # number of cache copies performed
378system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 165 # number of ReadReq MSHR hits
379system.cpu0.icache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits
380system.cpu0.icache.demand_mshr_hits::cpu0.inst 165 # number of demand (read+write) MSHR hits
381system.cpu0.icache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits
382system.cpu0.icache.overall_mshr_hits::cpu0.inst 165 # number of overall MSHR hits
383system.cpu0.icache.overall_mshr_hits::total 165 # number of overall MSHR hits
384system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 594 # number of ReadReq MSHR misses
385system.cpu0.icache.ReadReq_mshr_misses::total 594 # number of ReadReq MSHR misses
386system.cpu0.icache.demand_mshr_misses::cpu0.inst 594 # number of demand (read+write) MSHR misses
387system.cpu0.icache.demand_mshr_misses::total 594 # number of demand (read+write) MSHR misses
388system.cpu0.icache.overall_mshr_misses::cpu0.inst 594 # number of overall MSHR misses
389system.cpu0.icache.overall_mshr_misses::total 594 # number of overall MSHR misses
390system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21891000 # number of ReadReq MSHR miss cycles
391system.cpu0.icache.ReadReq_mshr_miss_latency::total 21891000 # number of ReadReq MSHR miss cycles
392system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21891000 # number of demand (read+write) MSHR miss cycles
393system.cpu0.icache.demand_mshr_miss_latency::total 21891000 # number of demand (read+write) MSHR miss cycles
394system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21891000 # number of overall MSHR miss cycles
395system.cpu0.icache.overall_mshr_miss_latency::total 21891000 # number of overall MSHR miss cycles
396system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for ReadReq accesses
|
| 397system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.095529 # mshr miss rate for ReadReq accesses
|
354system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for demand accesses
| 398system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for demand accesses
|
| 399system.cpu0.icache.demand_mshr_miss_rate::total 0.095529 # mshr miss rate for demand accesses
|
355system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for overall accesses
| 400system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for overall accesses
|
| 401system.cpu0.icache.overall_mshr_miss_rate::total 0.095529 # mshr miss rate for overall accesses
|
356system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average ReadReq mshr miss latency
| 402system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average ReadReq mshr miss latency
|
| 403system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36853.535354 # average ReadReq mshr miss latency
|
357system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average overall mshr miss latency
| 404system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average overall mshr miss latency
|
| 405system.cpu0.icache.demand_avg_mshr_miss_latency::total 36853.535354 # average overall mshr miss latency
|
358system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average overall mshr miss latency
| 406system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average overall mshr miss latency
|
| 407system.cpu0.icache.overall_avg_mshr_miss_latency::total 36853.535354 # average overall mshr miss latency
|
359system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
360system.cpu0.dcache.replacements 8 # number of replacements
361system.cpu0.dcache.tagsinuse 141.285775 # Cycle average of tags in use
362system.cpu0.dcache.total_refs 100453 # Total number of references to valid blocks.
363system.cpu0.dcache.sampled_refs 174 # Sample count of references to valid blocks.
364system.cpu0.dcache.avg_refs 577.316092 # Average number of references to valid blocks.
365system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
366system.cpu0.dcache.occ_blocks::cpu0.data 141.285775 # Average occupied blocks per requestor
367system.cpu0.dcache.occ_percent::cpu0.data 0.275949 # Average percentage of cache occupancy
368system.cpu0.dcache.occ_percent::total 0.275949 # Average percentage of cache occupancy
369system.cpu0.dcache.ReadReq_hits::cpu0.data 83026 # number of ReadReq hits
370system.cpu0.dcache.ReadReq_hits::total 83026 # number of ReadReq hits
371system.cpu0.dcache.WriteReq_hits::cpu0.data 80684 # number of WriteReq hits
372system.cpu0.dcache.WriteReq_hits::total 80684 # number of WriteReq hits
373system.cpu0.dcache.SwapReq_hits::cpu0.data 22 # number of SwapReq hits
374system.cpu0.dcache.SwapReq_hits::total 22 # number of SwapReq hits
375system.cpu0.dcache.demand_hits::cpu0.data 163710 # number of demand (read+write) hits
376system.cpu0.dcache.demand_hits::total 163710 # number of demand (read+write) hits
377system.cpu0.dcache.overall_hits::cpu0.data 163710 # number of overall hits
378system.cpu0.dcache.overall_hits::total 163710 # number of overall hits
379system.cpu0.dcache.ReadReq_misses::cpu0.data 495 # number of ReadReq misses
380system.cpu0.dcache.ReadReq_misses::total 495 # number of ReadReq misses
381system.cpu0.dcache.WriteReq_misses::cpu0.data 546 # number of WriteReq misses
382system.cpu0.dcache.WriteReq_misses::total 546 # number of WriteReq misses
383system.cpu0.dcache.SwapReq_misses::cpu0.data 20 # number of SwapReq misses
384system.cpu0.dcache.SwapReq_misses::total 20 # number of SwapReq misses
385system.cpu0.dcache.demand_misses::cpu0.data 1041 # number of demand (read+write) misses
386system.cpu0.dcache.demand_misses::total 1041 # number of demand (read+write) misses
387system.cpu0.dcache.overall_misses::cpu0.data 1041 # number of overall misses
388system.cpu0.dcache.overall_misses::total 1041 # number of overall misses
389system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13976000 # number of ReadReq miss cycles
390system.cpu0.dcache.ReadReq_miss_latency::total 13976000 # number of ReadReq miss cycles
391system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24361986 # number of WriteReq miss cycles
392system.cpu0.dcache.WriteReq_miss_latency::total 24361986 # number of WriteReq miss cycles
393system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 380500 # number of SwapReq miss cycles
394system.cpu0.dcache.SwapReq_miss_latency::total 380500 # number of SwapReq miss cycles
395system.cpu0.dcache.demand_miss_latency::cpu0.data 38337986 # number of demand (read+write) miss cycles
396system.cpu0.dcache.demand_miss_latency::total 38337986 # number of demand (read+write) miss cycles
397system.cpu0.dcache.overall_miss_latency::cpu0.data 38337986 # number of overall miss cycles
398system.cpu0.dcache.overall_miss_latency::total 38337986 # number of overall miss cycles
399system.cpu0.dcache.ReadReq_accesses::cpu0.data 83521 # number of ReadReq accesses(hits+misses)
400system.cpu0.dcache.ReadReq_accesses::total 83521 # number of ReadReq accesses(hits+misses)
401system.cpu0.dcache.WriteReq_accesses::cpu0.data 81230 # number of WriteReq accesses(hits+misses)
402system.cpu0.dcache.WriteReq_accesses::total 81230 # number of WriteReq accesses(hits+misses)
403system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
404system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
405system.cpu0.dcache.demand_accesses::cpu0.data 164751 # number of demand (read+write) accesses
406system.cpu0.dcache.demand_accesses::total 164751 # number of demand (read+write) accesses
407system.cpu0.dcache.overall_accesses::cpu0.data 164751 # number of overall (read+write) accesses
408system.cpu0.dcache.overall_accesses::total 164751 # number of overall (read+write) accesses
409system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005927 # miss rate for ReadReq accesses
| 408system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
409system.cpu0.dcache.replacements 8 # number of replacements
410system.cpu0.dcache.tagsinuse 141.285775 # Cycle average of tags in use
411system.cpu0.dcache.total_refs 100453 # Total number of references to valid blocks.
412system.cpu0.dcache.sampled_refs 174 # Sample count of references to valid blocks.
413system.cpu0.dcache.avg_refs 577.316092 # Average number of references to valid blocks.
414system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
415system.cpu0.dcache.occ_blocks::cpu0.data 141.285775 # Average occupied blocks per requestor
416system.cpu0.dcache.occ_percent::cpu0.data 0.275949 # Average percentage of cache occupancy
417system.cpu0.dcache.occ_percent::total 0.275949 # Average percentage of cache occupancy
418system.cpu0.dcache.ReadReq_hits::cpu0.data 83026 # number of ReadReq hits
419system.cpu0.dcache.ReadReq_hits::total 83026 # number of ReadReq hits
420system.cpu0.dcache.WriteReq_hits::cpu0.data 80684 # number of WriteReq hits
421system.cpu0.dcache.WriteReq_hits::total 80684 # number of WriteReq hits
422system.cpu0.dcache.SwapReq_hits::cpu0.data 22 # number of SwapReq hits
423system.cpu0.dcache.SwapReq_hits::total 22 # number of SwapReq hits
424system.cpu0.dcache.demand_hits::cpu0.data 163710 # number of demand (read+write) hits
425system.cpu0.dcache.demand_hits::total 163710 # number of demand (read+write) hits
426system.cpu0.dcache.overall_hits::cpu0.data 163710 # number of overall hits
427system.cpu0.dcache.overall_hits::total 163710 # number of overall hits
428system.cpu0.dcache.ReadReq_misses::cpu0.data 495 # number of ReadReq misses
429system.cpu0.dcache.ReadReq_misses::total 495 # number of ReadReq misses
430system.cpu0.dcache.WriteReq_misses::cpu0.data 546 # number of WriteReq misses
431system.cpu0.dcache.WriteReq_misses::total 546 # number of WriteReq misses
432system.cpu0.dcache.SwapReq_misses::cpu0.data 20 # number of SwapReq misses
433system.cpu0.dcache.SwapReq_misses::total 20 # number of SwapReq misses
434system.cpu0.dcache.demand_misses::cpu0.data 1041 # number of demand (read+write) misses
435system.cpu0.dcache.demand_misses::total 1041 # number of demand (read+write) misses
436system.cpu0.dcache.overall_misses::cpu0.data 1041 # number of overall misses
437system.cpu0.dcache.overall_misses::total 1041 # number of overall misses
438system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13976000 # number of ReadReq miss cycles
439system.cpu0.dcache.ReadReq_miss_latency::total 13976000 # number of ReadReq miss cycles
440system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24361986 # number of WriteReq miss cycles
441system.cpu0.dcache.WriteReq_miss_latency::total 24361986 # number of WriteReq miss cycles
442system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 380500 # number of SwapReq miss cycles
443system.cpu0.dcache.SwapReq_miss_latency::total 380500 # number of SwapReq miss cycles
444system.cpu0.dcache.demand_miss_latency::cpu0.data 38337986 # number of demand (read+write) miss cycles
445system.cpu0.dcache.demand_miss_latency::total 38337986 # number of demand (read+write) miss cycles
446system.cpu0.dcache.overall_miss_latency::cpu0.data 38337986 # number of overall miss cycles
447system.cpu0.dcache.overall_miss_latency::total 38337986 # number of overall miss cycles
448system.cpu0.dcache.ReadReq_accesses::cpu0.data 83521 # number of ReadReq accesses(hits+misses)
449system.cpu0.dcache.ReadReq_accesses::total 83521 # number of ReadReq accesses(hits+misses)
450system.cpu0.dcache.WriteReq_accesses::cpu0.data 81230 # number of WriteReq accesses(hits+misses)
451system.cpu0.dcache.WriteReq_accesses::total 81230 # number of WriteReq accesses(hits+misses)
452system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
453system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
454system.cpu0.dcache.demand_accesses::cpu0.data 164751 # number of demand (read+write) accesses
455system.cpu0.dcache.demand_accesses::total 164751 # number of demand (read+write) accesses
456system.cpu0.dcache.overall_accesses::cpu0.data 164751 # number of overall (read+write) accesses
457system.cpu0.dcache.overall_accesses::total 164751 # number of overall (read+write) accesses
458system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005927 # miss rate for ReadReq accesses
|
| 459system.cpu0.dcache.ReadReq_miss_rate::total 0.005927 # miss rate for ReadReq accesses
|
410system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006722 # miss rate for WriteReq accesses
| 460system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006722 # miss rate for WriteReq accesses
|
| 461system.cpu0.dcache.WriteReq_miss_rate::total 0.006722 # miss rate for WriteReq accesses
|
411system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.476190 # miss rate for SwapReq accesses
| 462system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.476190 # miss rate for SwapReq accesses
|
| 463system.cpu0.dcache.SwapReq_miss_rate::total 0.476190 # miss rate for SwapReq accesses
|
412system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006319 # miss rate for demand accesses
| 464system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006319 # miss rate for demand accesses
|
| 465system.cpu0.dcache.demand_miss_rate::total 0.006319 # miss rate for demand accesses
|
413system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006319 # miss rate for overall accesses
| 466system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006319 # miss rate for overall accesses
|
| 467system.cpu0.dcache.overall_miss_rate::total 0.006319 # miss rate for overall accesses
|
414system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28234.343434 # average ReadReq miss latency
| 468system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28234.343434 # average ReadReq miss latency
|
| 469system.cpu0.dcache.ReadReq_avg_miss_latency::total 28234.343434 # average ReadReq miss latency
|
415system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44619.021978 # average WriteReq miss latency
| 470system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44619.021978 # average WriteReq miss latency
|
| 471system.cpu0.dcache.WriteReq_avg_miss_latency::total 44619.021978 # average WriteReq miss latency
|
416system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19025 # average SwapReq miss latency
| 472system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19025 # average SwapReq miss latency
|
| 473system.cpu0.dcache.SwapReq_avg_miss_latency::total 19025 # average SwapReq miss latency
|
417system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36828.036503 # average overall miss latency
| 474system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36828.036503 # average overall miss latency
|
| 475system.cpu0.dcache.demand_avg_miss_latency::total 36828.036503 # average overall miss latency
|
418system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36828.036503 # average overall miss latency
| 476system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36828.036503 # average overall miss latency
|
| 477system.cpu0.dcache.overall_avg_miss_latency::total 36828.036503 # average overall miss latency
|
419system.cpu0.dcache.blocked_cycles::no_mshrs 194000 # number of cycles access was blocked
420system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
421system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked
422system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
423system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10210.526316 # average number of cycles each access was blocked
424system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
425system.cpu0.dcache.fast_writes 0 # number of fast writes performed
426system.cpu0.dcache.cache_copies 0 # number of cache copies performed
427system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks
428system.cpu0.dcache.writebacks::total 6 # number of writebacks
429system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 313 # number of ReadReq MSHR hits
430system.cpu0.dcache.ReadReq_mshr_hits::total 313 # number of ReadReq MSHR hits
431system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits
432system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits
433system.cpu0.dcache.demand_mshr_hits::cpu0.data 683 # number of demand (read+write) MSHR hits
434system.cpu0.dcache.demand_mshr_hits::total 683 # number of demand (read+write) MSHR hits
435system.cpu0.dcache.overall_mshr_hits::cpu0.data 683 # number of overall MSHR hits
436system.cpu0.dcache.overall_mshr_hits::total 683 # number of overall MSHR hits
437system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182 # number of ReadReq MSHR misses
438system.cpu0.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses
439system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176 # number of WriteReq MSHR misses
440system.cpu0.dcache.WriteReq_mshr_misses::total 176 # number of WriteReq MSHR misses
441system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 20 # number of SwapReq MSHR misses
442system.cpu0.dcache.SwapReq_mshr_misses::total 20 # number of SwapReq MSHR misses
443system.cpu0.dcache.demand_mshr_misses::cpu0.data 358 # number of demand (read+write) MSHR misses
444system.cpu0.dcache.demand_mshr_misses::total 358 # number of demand (read+write) MSHR misses
445system.cpu0.dcache.overall_mshr_misses::cpu0.data 358 # number of overall MSHR misses
446system.cpu0.dcache.overall_mshr_misses::total 358 # number of overall MSHR misses
447system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4954500 # number of ReadReq MSHR miss cycles
448system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4954500 # number of ReadReq MSHR miss cycles
449system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6250000 # number of WriteReq MSHR miss cycles
450system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6250000 # number of WriteReq MSHR miss cycles
451system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 320500 # number of SwapReq MSHR miss cycles
452system.cpu0.dcache.SwapReq_mshr_miss_latency::total 320500 # number of SwapReq MSHR miss cycles
453system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11204500 # number of demand (read+write) MSHR miss cycles
454system.cpu0.dcache.demand_mshr_miss_latency::total 11204500 # number of demand (read+write) MSHR miss cycles
455system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11204500 # number of overall MSHR miss cycles
456system.cpu0.dcache.overall_mshr_miss_latency::total 11204500 # number of overall MSHR miss cycles
457system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002179 # mshr miss rate for ReadReq accesses
| 478system.cpu0.dcache.blocked_cycles::no_mshrs 194000 # number of cycles access was blocked
479system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
480system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked
481system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
482system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10210.526316 # average number of cycles each access was blocked
483system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
484system.cpu0.dcache.fast_writes 0 # number of fast writes performed
485system.cpu0.dcache.cache_copies 0 # number of cache copies performed
486system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks
487system.cpu0.dcache.writebacks::total 6 # number of writebacks
488system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 313 # number of ReadReq MSHR hits
489system.cpu0.dcache.ReadReq_mshr_hits::total 313 # number of ReadReq MSHR hits
490system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits
491system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits
492system.cpu0.dcache.demand_mshr_hits::cpu0.data 683 # number of demand (read+write) MSHR hits
493system.cpu0.dcache.demand_mshr_hits::total 683 # number of demand (read+write) MSHR hits
494system.cpu0.dcache.overall_mshr_hits::cpu0.data 683 # number of overall MSHR hits
495system.cpu0.dcache.overall_mshr_hits::total 683 # number of overall MSHR hits
496system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182 # number of ReadReq MSHR misses
497system.cpu0.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses
498system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176 # number of WriteReq MSHR misses
499system.cpu0.dcache.WriteReq_mshr_misses::total 176 # number of WriteReq MSHR misses
500system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 20 # number of SwapReq MSHR misses
501system.cpu0.dcache.SwapReq_mshr_misses::total 20 # number of SwapReq MSHR misses
502system.cpu0.dcache.demand_mshr_misses::cpu0.data 358 # number of demand (read+write) MSHR misses
503system.cpu0.dcache.demand_mshr_misses::total 358 # number of demand (read+write) MSHR misses
504system.cpu0.dcache.overall_mshr_misses::cpu0.data 358 # number of overall MSHR misses
505system.cpu0.dcache.overall_mshr_misses::total 358 # number of overall MSHR misses
506system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4954500 # number of ReadReq MSHR miss cycles
507system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4954500 # number of ReadReq MSHR miss cycles
508system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6250000 # number of WriteReq MSHR miss cycles
509system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6250000 # number of WriteReq MSHR miss cycles
510system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 320500 # number of SwapReq MSHR miss cycles
511system.cpu0.dcache.SwapReq_mshr_miss_latency::total 320500 # number of SwapReq MSHR miss cycles
512system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11204500 # number of demand (read+write) MSHR miss cycles
513system.cpu0.dcache.demand_mshr_miss_latency::total 11204500 # number of demand (read+write) MSHR miss cycles
514system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11204500 # number of overall MSHR miss cycles
515system.cpu0.dcache.overall_mshr_miss_latency::total 11204500 # number of overall MSHR miss cycles
516system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002179 # mshr miss rate for ReadReq accesses
|
| 517system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002179 # mshr miss rate for ReadReq accesses
|
458system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002167 # mshr miss rate for WriteReq accesses
| 518system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002167 # mshr miss rate for WriteReq accesses
|
| 519system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002167 # mshr miss rate for WriteReq accesses
|
459system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.476190 # mshr miss rate for SwapReq accesses
| 520system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.476190 # mshr miss rate for SwapReq accesses
|
| 521system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.476190 # mshr miss rate for SwapReq accesses
|
460system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002173 # mshr miss rate for demand accesses
| 522system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002173 # mshr miss rate for demand accesses
|
| 523system.cpu0.dcache.demand_mshr_miss_rate::total 0.002173 # mshr miss rate for demand accesses
|
461system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002173 # mshr miss rate for overall accesses
| 524system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002173 # mshr miss rate for overall accesses
|
| 525system.cpu0.dcache.overall_mshr_miss_rate::total 0.002173 # mshr miss rate for overall accesses
|
462system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27222.527473 # average ReadReq mshr miss latency
| 526system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27222.527473 # average ReadReq mshr miss latency
|
| 527system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27222.527473 # average ReadReq mshr miss latency
|
463system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35511.363636 # average WriteReq mshr miss latency
| 528system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35511.363636 # average WriteReq mshr miss latency
|
| 529system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35511.363636 # average WriteReq mshr miss latency
|
464system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 16025 # average SwapReq mshr miss latency
| 530system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 16025 # average SwapReq mshr miss latency
|
| 531system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 16025 # average SwapReq mshr miss latency
|
465system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31297.486034 # average overall mshr miss latency
| 532system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31297.486034 # average overall mshr miss latency
|
| 533system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31297.486034 # average overall mshr miss latency
|
466system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31297.486034 # average overall mshr miss latency
| 534system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31297.486034 # average overall mshr miss latency
|
| 535system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31297.486034 # average overall mshr miss latency
|
467system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
468system.cpu1.numCycles 187393 # number of cpu cycles simulated
469system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
470system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
471system.cpu1.BPredUnit.lookups 57495 # Number of BP lookups
472system.cpu1.BPredUnit.condPredicted 54509 # Number of conditional branches predicted
473system.cpu1.BPredUnit.condIncorrect 1432 # Number of conditional branches incorrect
474system.cpu1.BPredUnit.BTBLookups 50945 # Number of BTB lookups
475system.cpu1.BPredUnit.BTBHits 49902 # Number of BTB hits
476system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
477system.cpu1.BPredUnit.usedRAS 759 # Number of times the RAS was used to get a target.
478system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
479system.cpu1.fetch.icacheStallCycles 28506 # Number of cycles fetch is stalled on an Icache miss
480system.cpu1.fetch.Insts 323137 # Number of instructions fetch has processed
481system.cpu1.fetch.Branches 57495 # Number of branches that fetch encountered
482system.cpu1.fetch.predictedBranches 50661 # Number of branches that fetch has predicted taken
483system.cpu1.fetch.Cycles 112599 # Number of cycles fetch has run and was not squashing or blocked
484system.cpu1.fetch.SquashCycles 4204 # Number of cycles fetch has spent squashing
485system.cpu1.fetch.BlockedCycles 33253 # Number of cycles fetch has spent blocked
486system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
487system.cpu1.fetch.NoActiveThreadStallCycles 6513 # Number of stall cycles due to no active thread to fetch from
488system.cpu1.fetch.PendingTrapStallCycles 1058 # Number of stall cycles due to pending traps
489system.cpu1.fetch.CacheLines 19809 # Number of cache lines fetched
490system.cpu1.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed
491system.cpu1.fetch.rateDist::samples 184628 # Number of instructions fetched each cycle (Total)
492system.cpu1.fetch.rateDist::mean 1.750206 # Number of instructions fetched each cycle (Total)
493system.cpu1.fetch.rateDist::stdev 2.168540 # Number of instructions fetched each cycle (Total)
494system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
495system.cpu1.fetch.rateDist::0 72029 39.01% 39.01% # Number of instructions fetched each cycle (Total)
496system.cpu1.fetch.rateDist::1 57027 30.89% 69.90% # Number of instructions fetched each cycle (Total)
497system.cpu1.fetch.rateDist::2 6026 3.26% 73.16% # Number of instructions fetched each cycle (Total)
498system.cpu1.fetch.rateDist::3 3313 1.79% 74.96% # Number of instructions fetched each cycle (Total)
499system.cpu1.fetch.rateDist::4 681 0.37% 75.33% # Number of instructions fetched each cycle (Total)
500system.cpu1.fetch.rateDist::5 39928 21.63% 96.95% # Number of instructions fetched each cycle (Total)
501system.cpu1.fetch.rateDist::6 1176 0.64% 97.59% # Number of instructions fetched each cycle (Total)
502system.cpu1.fetch.rateDist::7 885 0.48% 98.07% # Number of instructions fetched each cycle (Total)
503system.cpu1.fetch.rateDist::8 3563 1.93% 100.00% # Number of instructions fetched each cycle (Total)
504system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
505system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
506system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
507system.cpu1.fetch.rateDist::total 184628 # Number of instructions fetched each cycle (Total)
508system.cpu1.fetch.branchRate 0.306815 # Number of branch fetches per cycle
509system.cpu1.fetch.rate 1.724381 # Number of inst fetches per cycle
510system.cpu1.decode.IdleCycles 34082 # Number of cycles decode is idle
511system.cpu1.decode.BlockedCycles 29678 # Number of cycles decode is blocked
512system.cpu1.decode.RunCycles 106549 # Number of cycles decode is running
513system.cpu1.decode.UnblockCycles 5112 # Number of cycles decode is unblocking
514system.cpu1.decode.SquashCycles 2694 # Number of cycles decode is squashing
515system.cpu1.decode.DecodedInsts 318863 # Number of instructions handled by decode
516system.cpu1.rename.SquashCycles 2694 # Number of cycles rename is squashing
517system.cpu1.rename.IdleCycles 34823 # Number of cycles rename is idle
518system.cpu1.rename.BlockCycles 15756 # Number of cycles rename is blocking
519system.cpu1.rename.serializeStallCycles 13064 # count of cycles rename stalled for serializing inst
520system.cpu1.rename.RunCycles 101771 # Number of cycles rename is running
521system.cpu1.rename.UnblockCycles 10007 # Number of cycles rename is unblocking
522system.cpu1.rename.RenamedInsts 316589 # Number of instructions processed by rename
523system.cpu1.rename.IQFullEvents 26 # Number of times rename has blocked due to IQ full
524system.cpu1.rename.LSQFullEvents 63 # Number of times rename has blocked due to LSQ full
525system.cpu1.rename.RenamedOperands 221379 # Number of destination operands rename has renamed
526system.cpu1.rename.RenameLookups 610170 # Number of register rename lookups that rename has made
527system.cpu1.rename.int_rename_lookups 610170 # Number of integer rename lookups
528system.cpu1.rename.CommittedMaps 206274 # Number of HB maps that are committed
529system.cpu1.rename.UndoneMaps 15105 # Number of HB maps that are undone due to squashing
530system.cpu1.rename.serializingInsts 1171 # count of serializing insts renamed
531system.cpu1.rename.tempSerializingInsts 1292 # count of temporary serializing insts renamed
532system.cpu1.rename.skidInsts 12551 # count of insts added to the skid buffer
533system.cpu1.memDep0.insertedLoads 90746 # Number of loads inserted to the mem dependence unit.
534system.cpu1.memDep0.insertedStores 43396 # Number of stores inserted to the mem dependence unit.
535system.cpu1.memDep0.conflictingLoads 43483 # Number of conflicting loads.
536system.cpu1.memDep0.conflictingStores 38230 # Number of conflicting stores.
537system.cpu1.iq.iqInstsAdded 262560 # Number of instructions added to the IQ (excludes non-spec)
538system.cpu1.iq.iqNonSpecInstsAdded 6300 # Number of non-speculative instructions added to the IQ
539system.cpu1.iq.iqInstsIssued 264126 # Number of instructions issued
540system.cpu1.iq.iqSquashedInstsIssued 64 # Number of squashed instructions issued
541system.cpu1.iq.iqSquashedInstsExamined 12570 # Number of squashed instructions iterated over during squash; mainly for profiling
542system.cpu1.iq.iqSquashedOperandsExamined 11522 # Number of squashed operands that are examined and possibly removed from graph
543system.cpu1.iq.iqSquashedNonSpecRemoved 654 # Number of squashed non-spec instructions that were removed
544system.cpu1.iq.issued_per_cycle::samples 184628 # Number of insts issued each cycle
545system.cpu1.iq.issued_per_cycle::mean 1.430585 # Number of insts issued each cycle
546system.cpu1.iq.issued_per_cycle::stdev 1.313833 # Number of insts issued each cycle
547system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
548system.cpu1.iq.issued_per_cycle::0 69552 37.67% 37.67% # Number of insts issued each cycle
549system.cpu1.iq.issued_per_cycle::1 22561 12.22% 49.89% # Number of insts issued each cycle
550system.cpu1.iq.issued_per_cycle::2 43412 23.51% 73.40% # Number of insts issued each cycle
551system.cpu1.iq.issued_per_cycle::3 44019 23.84% 97.25% # Number of insts issued each cycle
552system.cpu1.iq.issued_per_cycle::4 3358 1.82% 99.07% # Number of insts issued each cycle
553system.cpu1.iq.issued_per_cycle::5 1272 0.69% 99.75% # Number of insts issued each cycle
554system.cpu1.iq.issued_per_cycle::6 343 0.19% 99.94% # Number of insts issued each cycle
555system.cpu1.iq.issued_per_cycle::7 54 0.03% 99.97% # Number of insts issued each cycle
556system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle
557system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
558system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
559system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
560system.cpu1.iq.issued_per_cycle::total 184628 # Number of insts issued each cycle
561system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
562system.cpu1.iq.fu_full::IntAlu 21 6.65% 6.65% # attempts to use FU when none available
563system.cpu1.iq.fu_full::IntMult 0 0.00% 6.65% # attempts to use FU when none available
564system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.65% # attempts to use FU when none available
565system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.65% # attempts to use FU when none available
566system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.65% # attempts to use FU when none available
567system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.65% # attempts to use FU when none available
568system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.65% # attempts to use FU when none available
569system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.65% # attempts to use FU when none available
570system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.65% # attempts to use FU when none available
571system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.65% # attempts to use FU when none available
572system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.65% # attempts to use FU when none available
573system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.65% # attempts to use FU when none available
574system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.65% # attempts to use FU when none available
575system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.65% # attempts to use FU when none available
576system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.65% # attempts to use FU when none available
577system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.65% # attempts to use FU when none available
578system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.65% # attempts to use FU when none available
579system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.65% # attempts to use FU when none available
580system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.65% # attempts to use FU when none available
581system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.65% # attempts to use FU when none available
582system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.65% # attempts to use FU when none available
583system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.65% # attempts to use FU when none available
584system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.65% # attempts to use FU when none available
585system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.65% # attempts to use FU when none available
586system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.65% # attempts to use FU when none available
587system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.65% # attempts to use FU when none available
588system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.65% # attempts to use FU when none available
589system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.65% # attempts to use FU when none available
590system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.65% # attempts to use FU when none available
591system.cpu1.iq.fu_full::MemRead 85 26.90% 33.54% # attempts to use FU when none available
592system.cpu1.iq.fu_full::MemWrite 210 66.46% 100.00% # attempts to use FU when none available
593system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
594system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
595system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
596system.cpu1.iq.FU_type_0::IntAlu 126488 47.89% 47.89% # Type of FU issued
597system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.89% # Type of FU issued
598system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.89% # Type of FU issued
599system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.89% # Type of FU issued
600system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.89% # Type of FU issued
601system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.89% # Type of FU issued
602system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.89% # Type of FU issued
603system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.89% # Type of FU issued
604system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.89% # Type of FU issued
605system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.89% # Type of FU issued
606system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.89% # Type of FU issued
607system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.89% # Type of FU issued
608system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.89% # Type of FU issued
609system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.89% # Type of FU issued
610system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.89% # Type of FU issued
611system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.89% # Type of FU issued
612system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.89% # Type of FU issued
613system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.89% # Type of FU issued
614system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.89% # Type of FU issued
615system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.89% # Type of FU issued
616system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.89% # Type of FU issued
617system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.89% # Type of FU issued
618system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.89% # Type of FU issued
619system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.89% # Type of FU issued
620system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.89% # Type of FU issued
621system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.89% # Type of FU issued
622system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.89% # Type of FU issued
623system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.89% # Type of FU issued
624system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.89% # Type of FU issued
625system.cpu1.iq.FU_type_0::MemRead 94921 35.94% 83.83% # Type of FU issued
626system.cpu1.iq.FU_type_0::MemWrite 42717 16.17% 100.00% # Type of FU issued
627system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
628system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
629system.cpu1.iq.FU_type_0::total 264126 # Type of FU issued
630system.cpu1.iq.rate 1.409476 # Inst issue rate
631system.cpu1.iq.fu_busy_cnt 316 # FU busy when requested
632system.cpu1.iq.fu_busy_rate 0.001196 # FU busy rate (busy events/executed inst)
633system.cpu1.iq.int_inst_queue_reads 713260 # Number of integer instruction queue reads
634system.cpu1.iq.int_inst_queue_writes 281477 # Number of integer instruction queue writes
635system.cpu1.iq.int_inst_queue_wakeup_accesses 262161 # Number of integer instruction queue wakeup accesses
636system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
637system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
638system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
639system.cpu1.iq.int_alu_accesses 264442 # Number of integer alu accesses
640system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
641system.cpu1.iew.lsq.thread0.forwLoads 37998 # Number of loads that had data forwarded from stores
642system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
643system.cpu1.iew.lsq.thread0.squashedLoads 2692 # Number of loads squashed
644system.cpu1.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
645system.cpu1.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations
646system.cpu1.iew.lsq.thread0.squashedStores 1591 # Number of stores squashed
647system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
648system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
649system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
650system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
651system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
652system.cpu1.iew.iewSquashCycles 2694 # Number of cycles IEW is squashing
653system.cpu1.iew.iewBlockCycles 1681 # Number of cycles IEW is blocking
654system.cpu1.iew.iewUnblockCycles 49 # Number of cycles IEW is unblocking
655system.cpu1.iew.iewDispatchedInsts 313238 # Number of instructions dispatched to IQ
656system.cpu1.iew.iewDispSquashedInsts 386 # Number of squashed instructions skipped by dispatch
657system.cpu1.iew.iewDispLoadInsts 90746 # Number of dispatched load instructions
658system.cpu1.iew.iewDispStoreInsts 43396 # Number of dispatched store instructions
659system.cpu1.iew.iewDispNonSpecInsts 1094 # Number of dispatched non-speculative instructions
660system.cpu1.iew.iewIQFullEvents 45 # Number of times the IQ has become full, causing a stall
661system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
662system.cpu1.iew.memOrderViolationEvents 47 # Number of memory order violations
663system.cpu1.iew.predictedTakenIncorrect 484 # Number of branches that were predicted taken incorrectly
664system.cpu1.iew.predictedNotTakenIncorrect 1109 # Number of branches that were predicted not taken incorrectly
665system.cpu1.iew.branchMispredicts 1593 # Number of branch mispredicts detected at execute
666system.cpu1.iew.iewExecutedInsts 262830 # Number of executed instructions
667system.cpu1.iew.iewExecLoadInsts 89694 # Number of load instructions executed
668system.cpu1.iew.iewExecSquashedInsts 1296 # Number of squashed instructions skipped in execute
669system.cpu1.iew.exec_swp 0 # number of swp insts executed
670system.cpu1.iew.exec_nop 44378 # number of nop insts executed
671system.cpu1.iew.exec_refs 132319 # number of memory reference insts executed
672system.cpu1.iew.exec_branches 53738 # Number of branches executed
673system.cpu1.iew.exec_stores 42625 # Number of stores executed
674system.cpu1.iew.exec_rate 1.402560 # Inst execution rate
675system.cpu1.iew.wb_sent 262446 # cumulative count of insts sent to commit
676system.cpu1.iew.wb_count 262161 # cumulative count of insts written-back
677system.cpu1.iew.wb_producers 149144 # num instructions producing a value
678system.cpu1.iew.wb_consumers 154061 # num instructions consuming a value
679system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
680system.cpu1.iew.wb_rate 1.398990 # insts written-back per cycle
681system.cpu1.iew.wb_fanout 0.968084 # average fanout of values written-back
682system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
683system.cpu1.commit.commitCommittedInsts 298843 # The number of committed instructions
684system.cpu1.commit.commitCommittedOps 298843 # The number of committed instructions
685system.cpu1.commit.commitSquashedInsts 14389 # The number of squashed insts skipped by commit
686system.cpu1.commit.commitNonSpecStalls 5646 # The number of times commit has been forced to stall to communicate backwards
687system.cpu1.commit.branchMispredicts 1432 # The number of times a branch was mispredicted
688system.cpu1.commit.committed_per_cycle::samples 175422 # Number of insts commited each cycle
689system.cpu1.commit.committed_per_cycle::mean 1.703566 # Number of insts commited each cycle
690system.cpu1.commit.committed_per_cycle::stdev 2.044466 # Number of insts commited each cycle
691system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
692system.cpu1.commit.committed_per_cycle::0 68710 39.17% 39.17% # Number of insts commited each cycle
693system.cpu1.commit.committed_per_cycle::1 51651 29.44% 68.61% # Number of insts commited each cycle
694system.cpu1.commit.committed_per_cycle::2 6180 3.52% 72.14% # Number of insts commited each cycle
695system.cpu1.commit.committed_per_cycle::3 6549 3.73% 75.87% # Number of insts commited each cycle
696system.cpu1.commit.committed_per_cycle::4 1541 0.88% 76.75% # Number of insts commited each cycle
697system.cpu1.commit.committed_per_cycle::5 38344 21.86% 98.61% # Number of insts commited each cycle
698system.cpu1.commit.committed_per_cycle::6 640 0.36% 98.97% # Number of insts commited each cycle
699system.cpu1.commit.committed_per_cycle::7 995 0.57% 99.54% # Number of insts commited each cycle
700system.cpu1.commit.committed_per_cycle::8 812 0.46% 100.00% # Number of insts commited each cycle
701system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
702system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
703system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
704system.cpu1.commit.committed_per_cycle::total 175422 # Number of insts commited each cycle
705system.cpu1.commit.committedInsts 298843 # Number of instructions committed
706system.cpu1.commit.committedOps 298843 # Number of ops (including micro ops) committed
707system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
708system.cpu1.commit.refs 129859 # Number of memory references committed
709system.cpu1.commit.loads 88054 # Number of loads committed
710system.cpu1.commit.membars 4938 # Number of memory barriers committed
711system.cpu1.commit.branches 52708 # Number of branches committed
712system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
713system.cpu1.commit.int_insts 204694 # Number of committed integer instructions.
714system.cpu1.commit.function_calls 322 # Number of function calls committed.
715system.cpu1.commit.bw_lim_events 812 # number cycles where commit BW limit reached
716system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
717system.cpu1.rob.rob_reads 487255 # The number of ROB reads
718system.cpu1.rob.rob_writes 629168 # The number of ROB writes
719system.cpu1.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself
720system.cpu1.idleCycles 2765 # Total number of cycles that the CPU has spent unscheduled due to idling
721system.cpu1.quiesceCycles 35411 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
722system.cpu1.committedInsts 250401 # Number of Instructions Simulated
723system.cpu1.committedOps 250401 # Number of Ops (including micro ops) Simulated
724system.cpu1.committedInsts_total 250401 # Number of Instructions Simulated
725system.cpu1.cpi 0.748372 # CPI: Cycles Per Instruction
726system.cpu1.cpi_total 0.748372 # CPI: Total CPI of All Threads
727system.cpu1.ipc 1.336235 # IPC: Instructions Per Cycle
728system.cpu1.ipc_total 1.336235 # IPC: Total IPC of All Threads
729system.cpu1.int_regfile_reads 456552 # number of integer regfile reads
730system.cpu1.int_regfile_writes 212248 # number of integer regfile writes
731system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
732system.cpu1.misc_regfile_reads 133945 # number of misc regfile reads
733system.cpu1.misc_regfile_writes 646 # number of misc regfile writes
734system.cpu1.icache.replacements 322 # number of replacements
735system.cpu1.icache.tagsinuse 82.769076 # Cycle average of tags in use
736system.cpu1.icache.total_refs 19304 # Total number of references to valid blocks.
737system.cpu1.icache.sampled_refs 435 # Sample count of references to valid blocks.
738system.cpu1.icache.avg_refs 44.377011 # Average number of references to valid blocks.
739system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
740system.cpu1.icache.occ_blocks::cpu1.inst 82.769076 # Average occupied blocks per requestor
741system.cpu1.icache.occ_percent::cpu1.inst 0.161658 # Average percentage of cache occupancy
742system.cpu1.icache.occ_percent::total 0.161658 # Average percentage of cache occupancy
743system.cpu1.icache.ReadReq_hits::cpu1.inst 19304 # number of ReadReq hits
744system.cpu1.icache.ReadReq_hits::total 19304 # number of ReadReq hits
745system.cpu1.icache.demand_hits::cpu1.inst 19304 # number of demand (read+write) hits
746system.cpu1.icache.demand_hits::total 19304 # number of demand (read+write) hits
747system.cpu1.icache.overall_hits::cpu1.inst 19304 # number of overall hits
748system.cpu1.icache.overall_hits::total 19304 # number of overall hits
749system.cpu1.icache.ReadReq_misses::cpu1.inst 505 # number of ReadReq misses
750system.cpu1.icache.ReadReq_misses::total 505 # number of ReadReq misses
751system.cpu1.icache.demand_misses::cpu1.inst 505 # number of demand (read+write) misses
752system.cpu1.icache.demand_misses::total 505 # number of demand (read+write) misses
753system.cpu1.icache.overall_misses::cpu1.inst 505 # number of overall misses
754system.cpu1.icache.overall_misses::total 505 # number of overall misses
755system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7500500 # number of ReadReq miss cycles
756system.cpu1.icache.ReadReq_miss_latency::total 7500500 # number of ReadReq miss cycles
757system.cpu1.icache.demand_miss_latency::cpu1.inst 7500500 # number of demand (read+write) miss cycles
758system.cpu1.icache.demand_miss_latency::total 7500500 # number of demand (read+write) miss cycles
759system.cpu1.icache.overall_miss_latency::cpu1.inst 7500500 # number of overall miss cycles
760system.cpu1.icache.overall_miss_latency::total 7500500 # number of overall miss cycles
761system.cpu1.icache.ReadReq_accesses::cpu1.inst 19809 # number of ReadReq accesses(hits+misses)
762system.cpu1.icache.ReadReq_accesses::total 19809 # number of ReadReq accesses(hits+misses)
763system.cpu1.icache.demand_accesses::cpu1.inst 19809 # number of demand (read+write) accesses
764system.cpu1.icache.demand_accesses::total 19809 # number of demand (read+write) accesses
765system.cpu1.icache.overall_accesses::cpu1.inst 19809 # number of overall (read+write) accesses
766system.cpu1.icache.overall_accesses::total 19809 # number of overall (read+write) accesses
767system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.025493 # miss rate for ReadReq accesses
| 536system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
537system.cpu1.numCycles 187393 # number of cpu cycles simulated
538system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
539system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
540system.cpu1.BPredUnit.lookups 57495 # Number of BP lookups
541system.cpu1.BPredUnit.condPredicted 54509 # Number of conditional branches predicted
542system.cpu1.BPredUnit.condIncorrect 1432 # Number of conditional branches incorrect
543system.cpu1.BPredUnit.BTBLookups 50945 # Number of BTB lookups
544system.cpu1.BPredUnit.BTBHits 49902 # Number of BTB hits
545system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
546system.cpu1.BPredUnit.usedRAS 759 # Number of times the RAS was used to get a target.
547system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
548system.cpu1.fetch.icacheStallCycles 28506 # Number of cycles fetch is stalled on an Icache miss
549system.cpu1.fetch.Insts 323137 # Number of instructions fetch has processed
550system.cpu1.fetch.Branches 57495 # Number of branches that fetch encountered
551system.cpu1.fetch.predictedBranches 50661 # Number of branches that fetch has predicted taken
552system.cpu1.fetch.Cycles 112599 # Number of cycles fetch has run and was not squashing or blocked
553system.cpu1.fetch.SquashCycles 4204 # Number of cycles fetch has spent squashing
554system.cpu1.fetch.BlockedCycles 33253 # Number of cycles fetch has spent blocked
555system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
556system.cpu1.fetch.NoActiveThreadStallCycles 6513 # Number of stall cycles due to no active thread to fetch from
557system.cpu1.fetch.PendingTrapStallCycles 1058 # Number of stall cycles due to pending traps
558system.cpu1.fetch.CacheLines 19809 # Number of cache lines fetched
559system.cpu1.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed
560system.cpu1.fetch.rateDist::samples 184628 # Number of instructions fetched each cycle (Total)
561system.cpu1.fetch.rateDist::mean 1.750206 # Number of instructions fetched each cycle (Total)
562system.cpu1.fetch.rateDist::stdev 2.168540 # Number of instructions fetched each cycle (Total)
563system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
564system.cpu1.fetch.rateDist::0 72029 39.01% 39.01% # Number of instructions fetched each cycle (Total)
565system.cpu1.fetch.rateDist::1 57027 30.89% 69.90% # Number of instructions fetched each cycle (Total)
566system.cpu1.fetch.rateDist::2 6026 3.26% 73.16% # Number of instructions fetched each cycle (Total)
567system.cpu1.fetch.rateDist::3 3313 1.79% 74.96% # Number of instructions fetched each cycle (Total)
568system.cpu1.fetch.rateDist::4 681 0.37% 75.33% # Number of instructions fetched each cycle (Total)
569system.cpu1.fetch.rateDist::5 39928 21.63% 96.95% # Number of instructions fetched each cycle (Total)
570system.cpu1.fetch.rateDist::6 1176 0.64% 97.59% # Number of instructions fetched each cycle (Total)
571system.cpu1.fetch.rateDist::7 885 0.48% 98.07% # Number of instructions fetched each cycle (Total)
572system.cpu1.fetch.rateDist::8 3563 1.93% 100.00% # Number of instructions fetched each cycle (Total)
573system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
574system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
575system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
576system.cpu1.fetch.rateDist::total 184628 # Number of instructions fetched each cycle (Total)
577system.cpu1.fetch.branchRate 0.306815 # Number of branch fetches per cycle
578system.cpu1.fetch.rate 1.724381 # Number of inst fetches per cycle
579system.cpu1.decode.IdleCycles 34082 # Number of cycles decode is idle
580system.cpu1.decode.BlockedCycles 29678 # Number of cycles decode is blocked
581system.cpu1.decode.RunCycles 106549 # Number of cycles decode is running
582system.cpu1.decode.UnblockCycles 5112 # Number of cycles decode is unblocking
583system.cpu1.decode.SquashCycles 2694 # Number of cycles decode is squashing
584system.cpu1.decode.DecodedInsts 318863 # Number of instructions handled by decode
585system.cpu1.rename.SquashCycles 2694 # Number of cycles rename is squashing
586system.cpu1.rename.IdleCycles 34823 # Number of cycles rename is idle
587system.cpu1.rename.BlockCycles 15756 # Number of cycles rename is blocking
588system.cpu1.rename.serializeStallCycles 13064 # count of cycles rename stalled for serializing inst
589system.cpu1.rename.RunCycles 101771 # Number of cycles rename is running
590system.cpu1.rename.UnblockCycles 10007 # Number of cycles rename is unblocking
591system.cpu1.rename.RenamedInsts 316589 # Number of instructions processed by rename
592system.cpu1.rename.IQFullEvents 26 # Number of times rename has blocked due to IQ full
593system.cpu1.rename.LSQFullEvents 63 # Number of times rename has blocked due to LSQ full
594system.cpu1.rename.RenamedOperands 221379 # Number of destination operands rename has renamed
595system.cpu1.rename.RenameLookups 610170 # Number of register rename lookups that rename has made
596system.cpu1.rename.int_rename_lookups 610170 # Number of integer rename lookups
597system.cpu1.rename.CommittedMaps 206274 # Number of HB maps that are committed
598system.cpu1.rename.UndoneMaps 15105 # Number of HB maps that are undone due to squashing
599system.cpu1.rename.serializingInsts 1171 # count of serializing insts renamed
600system.cpu1.rename.tempSerializingInsts 1292 # count of temporary serializing insts renamed
601system.cpu1.rename.skidInsts 12551 # count of insts added to the skid buffer
602system.cpu1.memDep0.insertedLoads 90746 # Number of loads inserted to the mem dependence unit.
603system.cpu1.memDep0.insertedStores 43396 # Number of stores inserted to the mem dependence unit.
604system.cpu1.memDep0.conflictingLoads 43483 # Number of conflicting loads.
605system.cpu1.memDep0.conflictingStores 38230 # Number of conflicting stores.
606system.cpu1.iq.iqInstsAdded 262560 # Number of instructions added to the IQ (excludes non-spec)
607system.cpu1.iq.iqNonSpecInstsAdded 6300 # Number of non-speculative instructions added to the IQ
608system.cpu1.iq.iqInstsIssued 264126 # Number of instructions issued
609system.cpu1.iq.iqSquashedInstsIssued 64 # Number of squashed instructions issued
610system.cpu1.iq.iqSquashedInstsExamined 12570 # Number of squashed instructions iterated over during squash; mainly for profiling
611system.cpu1.iq.iqSquashedOperandsExamined 11522 # Number of squashed operands that are examined and possibly removed from graph
612system.cpu1.iq.iqSquashedNonSpecRemoved 654 # Number of squashed non-spec instructions that were removed
613system.cpu1.iq.issued_per_cycle::samples 184628 # Number of insts issued each cycle
614system.cpu1.iq.issued_per_cycle::mean 1.430585 # Number of insts issued each cycle
615system.cpu1.iq.issued_per_cycle::stdev 1.313833 # Number of insts issued each cycle
616system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
617system.cpu1.iq.issued_per_cycle::0 69552 37.67% 37.67% # Number of insts issued each cycle
618system.cpu1.iq.issued_per_cycle::1 22561 12.22% 49.89% # Number of insts issued each cycle
619system.cpu1.iq.issued_per_cycle::2 43412 23.51% 73.40% # Number of insts issued each cycle
620system.cpu1.iq.issued_per_cycle::3 44019 23.84% 97.25% # Number of insts issued each cycle
621system.cpu1.iq.issued_per_cycle::4 3358 1.82% 99.07% # Number of insts issued each cycle
622system.cpu1.iq.issued_per_cycle::5 1272 0.69% 99.75% # Number of insts issued each cycle
623system.cpu1.iq.issued_per_cycle::6 343 0.19% 99.94% # Number of insts issued each cycle
624system.cpu1.iq.issued_per_cycle::7 54 0.03% 99.97% # Number of insts issued each cycle
625system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle
626system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
627system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
628system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
629system.cpu1.iq.issued_per_cycle::total 184628 # Number of insts issued each cycle
630system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
631system.cpu1.iq.fu_full::IntAlu 21 6.65% 6.65% # attempts to use FU when none available
632system.cpu1.iq.fu_full::IntMult 0 0.00% 6.65% # attempts to use FU when none available
633system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.65% # attempts to use FU when none available
634system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.65% # attempts to use FU when none available
635system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.65% # attempts to use FU when none available
636system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.65% # attempts to use FU when none available
637system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.65% # attempts to use FU when none available
638system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.65% # attempts to use FU when none available
639system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.65% # attempts to use FU when none available
640system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.65% # attempts to use FU when none available
641system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.65% # attempts to use FU when none available
642system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.65% # attempts to use FU when none available
643system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.65% # attempts to use FU when none available
644system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.65% # attempts to use FU when none available
645system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.65% # attempts to use FU when none available
646system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.65% # attempts to use FU when none available
647system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.65% # attempts to use FU when none available
648system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.65% # attempts to use FU when none available
649system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.65% # attempts to use FU when none available
650system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.65% # attempts to use FU when none available
651system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.65% # attempts to use FU when none available
652system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.65% # attempts to use FU when none available
653system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.65% # attempts to use FU when none available
654system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.65% # attempts to use FU when none available
655system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.65% # attempts to use FU when none available
656system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.65% # attempts to use FU when none available
657system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.65% # attempts to use FU when none available
658system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.65% # attempts to use FU when none available
659system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.65% # attempts to use FU when none available
660system.cpu1.iq.fu_full::MemRead 85 26.90% 33.54% # attempts to use FU when none available
661system.cpu1.iq.fu_full::MemWrite 210 66.46% 100.00% # attempts to use FU when none available
662system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
663system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
664system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
665system.cpu1.iq.FU_type_0::IntAlu 126488 47.89% 47.89% # Type of FU issued
666system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.89% # Type of FU issued
667system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.89% # Type of FU issued
668system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.89% # Type of FU issued
669system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.89% # Type of FU issued
670system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.89% # Type of FU issued
671system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.89% # Type of FU issued
672system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.89% # Type of FU issued
673system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.89% # Type of FU issued
674system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.89% # Type of FU issued
675system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.89% # Type of FU issued
676system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.89% # Type of FU issued
677system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.89% # Type of FU issued
678system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.89% # Type of FU issued
679system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.89% # Type of FU issued
680system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.89% # Type of FU issued
681system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.89% # Type of FU issued
682system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.89% # Type of FU issued
683system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.89% # Type of FU issued
684system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.89% # Type of FU issued
685system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.89% # Type of FU issued
686system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.89% # Type of FU issued
687system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.89% # Type of FU issued
688system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.89% # Type of FU issued
689system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.89% # Type of FU issued
690system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.89% # Type of FU issued
691system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.89% # Type of FU issued
692system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.89% # Type of FU issued
693system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.89% # Type of FU issued
694system.cpu1.iq.FU_type_0::MemRead 94921 35.94% 83.83% # Type of FU issued
695system.cpu1.iq.FU_type_0::MemWrite 42717 16.17% 100.00% # Type of FU issued
696system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
697system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
698system.cpu1.iq.FU_type_0::total 264126 # Type of FU issued
699system.cpu1.iq.rate 1.409476 # Inst issue rate
700system.cpu1.iq.fu_busy_cnt 316 # FU busy when requested
701system.cpu1.iq.fu_busy_rate 0.001196 # FU busy rate (busy events/executed inst)
702system.cpu1.iq.int_inst_queue_reads 713260 # Number of integer instruction queue reads
703system.cpu1.iq.int_inst_queue_writes 281477 # Number of integer instruction queue writes
704system.cpu1.iq.int_inst_queue_wakeup_accesses 262161 # Number of integer instruction queue wakeup accesses
705system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
706system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
707system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
708system.cpu1.iq.int_alu_accesses 264442 # Number of integer alu accesses
709system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
710system.cpu1.iew.lsq.thread0.forwLoads 37998 # Number of loads that had data forwarded from stores
711system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
712system.cpu1.iew.lsq.thread0.squashedLoads 2692 # Number of loads squashed
713system.cpu1.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
714system.cpu1.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations
715system.cpu1.iew.lsq.thread0.squashedStores 1591 # Number of stores squashed
716system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
717system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
718system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
719system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
720system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
721system.cpu1.iew.iewSquashCycles 2694 # Number of cycles IEW is squashing
722system.cpu1.iew.iewBlockCycles 1681 # Number of cycles IEW is blocking
723system.cpu1.iew.iewUnblockCycles 49 # Number of cycles IEW is unblocking
724system.cpu1.iew.iewDispatchedInsts 313238 # Number of instructions dispatched to IQ
725system.cpu1.iew.iewDispSquashedInsts 386 # Number of squashed instructions skipped by dispatch
726system.cpu1.iew.iewDispLoadInsts 90746 # Number of dispatched load instructions
727system.cpu1.iew.iewDispStoreInsts 43396 # Number of dispatched store instructions
728system.cpu1.iew.iewDispNonSpecInsts 1094 # Number of dispatched non-speculative instructions
729system.cpu1.iew.iewIQFullEvents 45 # Number of times the IQ has become full, causing a stall
730system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
731system.cpu1.iew.memOrderViolationEvents 47 # Number of memory order violations
732system.cpu1.iew.predictedTakenIncorrect 484 # Number of branches that were predicted taken incorrectly
733system.cpu1.iew.predictedNotTakenIncorrect 1109 # Number of branches that were predicted not taken incorrectly
734system.cpu1.iew.branchMispredicts 1593 # Number of branch mispredicts detected at execute
735system.cpu1.iew.iewExecutedInsts 262830 # Number of executed instructions
736system.cpu1.iew.iewExecLoadInsts 89694 # Number of load instructions executed
737system.cpu1.iew.iewExecSquashedInsts 1296 # Number of squashed instructions skipped in execute
738system.cpu1.iew.exec_swp 0 # number of swp insts executed
739system.cpu1.iew.exec_nop 44378 # number of nop insts executed
740system.cpu1.iew.exec_refs 132319 # number of memory reference insts executed
741system.cpu1.iew.exec_branches 53738 # Number of branches executed
742system.cpu1.iew.exec_stores 42625 # Number of stores executed
743system.cpu1.iew.exec_rate 1.402560 # Inst execution rate
744system.cpu1.iew.wb_sent 262446 # cumulative count of insts sent to commit
745system.cpu1.iew.wb_count 262161 # cumulative count of insts written-back
746system.cpu1.iew.wb_producers 149144 # num instructions producing a value
747system.cpu1.iew.wb_consumers 154061 # num instructions consuming a value
748system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
749system.cpu1.iew.wb_rate 1.398990 # insts written-back per cycle
750system.cpu1.iew.wb_fanout 0.968084 # average fanout of values written-back
751system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
752system.cpu1.commit.commitCommittedInsts 298843 # The number of committed instructions
753system.cpu1.commit.commitCommittedOps 298843 # The number of committed instructions
754system.cpu1.commit.commitSquashedInsts 14389 # The number of squashed insts skipped by commit
755system.cpu1.commit.commitNonSpecStalls 5646 # The number of times commit has been forced to stall to communicate backwards
756system.cpu1.commit.branchMispredicts 1432 # The number of times a branch was mispredicted
757system.cpu1.commit.committed_per_cycle::samples 175422 # Number of insts commited each cycle
758system.cpu1.commit.committed_per_cycle::mean 1.703566 # Number of insts commited each cycle
759system.cpu1.commit.committed_per_cycle::stdev 2.044466 # Number of insts commited each cycle
760system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
761system.cpu1.commit.committed_per_cycle::0 68710 39.17% 39.17% # Number of insts commited each cycle
762system.cpu1.commit.committed_per_cycle::1 51651 29.44% 68.61% # Number of insts commited each cycle
763system.cpu1.commit.committed_per_cycle::2 6180 3.52% 72.14% # Number of insts commited each cycle
764system.cpu1.commit.committed_per_cycle::3 6549 3.73% 75.87% # Number of insts commited each cycle
765system.cpu1.commit.committed_per_cycle::4 1541 0.88% 76.75% # Number of insts commited each cycle
766system.cpu1.commit.committed_per_cycle::5 38344 21.86% 98.61% # Number of insts commited each cycle
767system.cpu1.commit.committed_per_cycle::6 640 0.36% 98.97% # Number of insts commited each cycle
768system.cpu1.commit.committed_per_cycle::7 995 0.57% 99.54% # Number of insts commited each cycle
769system.cpu1.commit.committed_per_cycle::8 812 0.46% 100.00% # Number of insts commited each cycle
770system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
771system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
772system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
773system.cpu1.commit.committed_per_cycle::total 175422 # Number of insts commited each cycle
774system.cpu1.commit.committedInsts 298843 # Number of instructions committed
775system.cpu1.commit.committedOps 298843 # Number of ops (including micro ops) committed
776system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
777system.cpu1.commit.refs 129859 # Number of memory references committed
778system.cpu1.commit.loads 88054 # Number of loads committed
779system.cpu1.commit.membars 4938 # Number of memory barriers committed
780system.cpu1.commit.branches 52708 # Number of branches committed
781system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
782system.cpu1.commit.int_insts 204694 # Number of committed integer instructions.
783system.cpu1.commit.function_calls 322 # Number of function calls committed.
784system.cpu1.commit.bw_lim_events 812 # number cycles where commit BW limit reached
785system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
786system.cpu1.rob.rob_reads 487255 # The number of ROB reads
787system.cpu1.rob.rob_writes 629168 # The number of ROB writes
788system.cpu1.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself
789system.cpu1.idleCycles 2765 # Total number of cycles that the CPU has spent unscheduled due to idling
790system.cpu1.quiesceCycles 35411 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
791system.cpu1.committedInsts 250401 # Number of Instructions Simulated
792system.cpu1.committedOps 250401 # Number of Ops (including micro ops) Simulated
793system.cpu1.committedInsts_total 250401 # Number of Instructions Simulated
794system.cpu1.cpi 0.748372 # CPI: Cycles Per Instruction
795system.cpu1.cpi_total 0.748372 # CPI: Total CPI of All Threads
796system.cpu1.ipc 1.336235 # IPC: Instructions Per Cycle
797system.cpu1.ipc_total 1.336235 # IPC: Total IPC of All Threads
798system.cpu1.int_regfile_reads 456552 # number of integer regfile reads
799system.cpu1.int_regfile_writes 212248 # number of integer regfile writes
800system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
801system.cpu1.misc_regfile_reads 133945 # number of misc regfile reads
802system.cpu1.misc_regfile_writes 646 # number of misc regfile writes
803system.cpu1.icache.replacements 322 # number of replacements
804system.cpu1.icache.tagsinuse 82.769076 # Cycle average of tags in use
805system.cpu1.icache.total_refs 19304 # Total number of references to valid blocks.
806system.cpu1.icache.sampled_refs 435 # Sample count of references to valid blocks.
807system.cpu1.icache.avg_refs 44.377011 # Average number of references to valid blocks.
808system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
809system.cpu1.icache.occ_blocks::cpu1.inst 82.769076 # Average occupied blocks per requestor
810system.cpu1.icache.occ_percent::cpu1.inst 0.161658 # Average percentage of cache occupancy
811system.cpu1.icache.occ_percent::total 0.161658 # Average percentage of cache occupancy
812system.cpu1.icache.ReadReq_hits::cpu1.inst 19304 # number of ReadReq hits
813system.cpu1.icache.ReadReq_hits::total 19304 # number of ReadReq hits
814system.cpu1.icache.demand_hits::cpu1.inst 19304 # number of demand (read+write) hits
815system.cpu1.icache.demand_hits::total 19304 # number of demand (read+write) hits
816system.cpu1.icache.overall_hits::cpu1.inst 19304 # number of overall hits
817system.cpu1.icache.overall_hits::total 19304 # number of overall hits
818system.cpu1.icache.ReadReq_misses::cpu1.inst 505 # number of ReadReq misses
819system.cpu1.icache.ReadReq_misses::total 505 # number of ReadReq misses
820system.cpu1.icache.demand_misses::cpu1.inst 505 # number of demand (read+write) misses
821system.cpu1.icache.demand_misses::total 505 # number of demand (read+write) misses
822system.cpu1.icache.overall_misses::cpu1.inst 505 # number of overall misses
823system.cpu1.icache.overall_misses::total 505 # number of overall misses
824system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7500500 # number of ReadReq miss cycles
825system.cpu1.icache.ReadReq_miss_latency::total 7500500 # number of ReadReq miss cycles
826system.cpu1.icache.demand_miss_latency::cpu1.inst 7500500 # number of demand (read+write) miss cycles
827system.cpu1.icache.demand_miss_latency::total 7500500 # number of demand (read+write) miss cycles
828system.cpu1.icache.overall_miss_latency::cpu1.inst 7500500 # number of overall miss cycles
829system.cpu1.icache.overall_miss_latency::total 7500500 # number of overall miss cycles
830system.cpu1.icache.ReadReq_accesses::cpu1.inst 19809 # number of ReadReq accesses(hits+misses)
831system.cpu1.icache.ReadReq_accesses::total 19809 # number of ReadReq accesses(hits+misses)
832system.cpu1.icache.demand_accesses::cpu1.inst 19809 # number of demand (read+write) accesses
833system.cpu1.icache.demand_accesses::total 19809 # number of demand (read+write) accesses
834system.cpu1.icache.overall_accesses::cpu1.inst 19809 # number of overall (read+write) accesses
835system.cpu1.icache.overall_accesses::total 19809 # number of overall (read+write) accesses
836system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.025493 # miss rate for ReadReq accesses
|
| 837system.cpu1.icache.ReadReq_miss_rate::total 0.025493 # miss rate for ReadReq accesses
|
768system.cpu1.icache.demand_miss_rate::cpu1.inst 0.025493 # miss rate for demand accesses
| 838system.cpu1.icache.demand_miss_rate::cpu1.inst 0.025493 # miss rate for demand accesses
|
| 839system.cpu1.icache.demand_miss_rate::total 0.025493 # miss rate for demand accesses
|
769system.cpu1.icache.overall_miss_rate::cpu1.inst 0.025493 # miss rate for overall accesses
| 840system.cpu1.icache.overall_miss_rate::cpu1.inst 0.025493 # miss rate for overall accesses
|
| 841system.cpu1.icache.overall_miss_rate::total 0.025493 # miss rate for overall accesses
|
770system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14852.475248 # average ReadReq miss latency
| 842system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14852.475248 # average ReadReq miss latency
|
| 843system.cpu1.icache.ReadReq_avg_miss_latency::total 14852.475248 # average ReadReq miss latency
|
771system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14852.475248 # average overall miss latency
| 844system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14852.475248 # average overall miss latency
|
| 845system.cpu1.icache.demand_avg_miss_latency::total 14852.475248 # average overall miss latency
|
772system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14852.475248 # average overall miss latency
| 846system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14852.475248 # average overall miss latency
|
| 847system.cpu1.icache.overall_avg_miss_latency::total 14852.475248 # average overall miss latency
|
773system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
774system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
775system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
776system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
777system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
778system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
779system.cpu1.icache.fast_writes 0 # number of fast writes performed
780system.cpu1.icache.cache_copies 0 # number of cache copies performed
781system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 70 # number of ReadReq MSHR hits
782system.cpu1.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits
783system.cpu1.icache.demand_mshr_hits::cpu1.inst 70 # number of demand (read+write) MSHR hits
784system.cpu1.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits
785system.cpu1.icache.overall_mshr_hits::cpu1.inst 70 # number of overall MSHR hits
786system.cpu1.icache.overall_mshr_hits::total 70 # number of overall MSHR hits
787system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 435 # number of ReadReq MSHR misses
788system.cpu1.icache.ReadReq_mshr_misses::total 435 # number of ReadReq MSHR misses
789system.cpu1.icache.demand_mshr_misses::cpu1.inst 435 # number of demand (read+write) MSHR misses
790system.cpu1.icache.demand_mshr_misses::total 435 # number of demand (read+write) MSHR misses
791system.cpu1.icache.overall_mshr_misses::cpu1.inst 435 # number of overall MSHR misses
792system.cpu1.icache.overall_mshr_misses::total 435 # number of overall MSHR misses
793system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5474500 # number of ReadReq MSHR miss cycles
794system.cpu1.icache.ReadReq_mshr_miss_latency::total 5474500 # number of ReadReq MSHR miss cycles
795system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5474500 # number of demand (read+write) MSHR miss cycles
796system.cpu1.icache.demand_mshr_miss_latency::total 5474500 # number of demand (read+write) MSHR miss cycles
797system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5474500 # number of overall MSHR miss cycles
798system.cpu1.icache.overall_mshr_miss_latency::total 5474500 # number of overall MSHR miss cycles
799system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for ReadReq accesses
| 848system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
849system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
850system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
851system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
852system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
853system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
854system.cpu1.icache.fast_writes 0 # number of fast writes performed
855system.cpu1.icache.cache_copies 0 # number of cache copies performed
856system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 70 # number of ReadReq MSHR hits
857system.cpu1.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits
858system.cpu1.icache.demand_mshr_hits::cpu1.inst 70 # number of demand (read+write) MSHR hits
859system.cpu1.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits
860system.cpu1.icache.overall_mshr_hits::cpu1.inst 70 # number of overall MSHR hits
861system.cpu1.icache.overall_mshr_hits::total 70 # number of overall MSHR hits
862system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 435 # number of ReadReq MSHR misses
863system.cpu1.icache.ReadReq_mshr_misses::total 435 # number of ReadReq MSHR misses
864system.cpu1.icache.demand_mshr_misses::cpu1.inst 435 # number of demand (read+write) MSHR misses
865system.cpu1.icache.demand_mshr_misses::total 435 # number of demand (read+write) MSHR misses
866system.cpu1.icache.overall_mshr_misses::cpu1.inst 435 # number of overall MSHR misses
867system.cpu1.icache.overall_mshr_misses::total 435 # number of overall MSHR misses
868system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5474500 # number of ReadReq MSHR miss cycles
869system.cpu1.icache.ReadReq_mshr_miss_latency::total 5474500 # number of ReadReq MSHR miss cycles
870system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5474500 # number of demand (read+write) MSHR miss cycles
871system.cpu1.icache.demand_mshr_miss_latency::total 5474500 # number of demand (read+write) MSHR miss cycles
872system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5474500 # number of overall MSHR miss cycles
873system.cpu1.icache.overall_mshr_miss_latency::total 5474500 # number of overall MSHR miss cycles
874system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for ReadReq accesses
|
| 875system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.021960 # mshr miss rate for ReadReq accesses
|
800system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for demand accesses
| 876system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for demand accesses
|
| 877system.cpu1.icache.demand_mshr_miss_rate::total 0.021960 # mshr miss rate for demand accesses
|
801system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for overall accesses
| 878system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for overall accesses
|
| 879system.cpu1.icache.overall_mshr_miss_rate::total 0.021960 # mshr miss rate for overall accesses
|
802system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average ReadReq mshr miss latency
| 880system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average ReadReq mshr miss latency
|
| 881system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12585.057471 # average ReadReq mshr miss latency
|
803system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average overall mshr miss latency
| 882system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average overall mshr miss latency
|
| 883system.cpu1.icache.demand_avg_mshr_miss_latency::total 12585.057471 # average overall mshr miss latency
|
804system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average overall mshr miss latency
| 884system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average overall mshr miss latency
|
| 885system.cpu1.icache.overall_avg_mshr_miss_latency::total 12585.057471 # average overall mshr miss latency
|
805system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
806system.cpu1.dcache.replacements 2 # number of replacements
807system.cpu1.dcache.tagsinuse 24.070551 # Cycle average of tags in use
808system.cpu1.dcache.total_refs 48111 # Total number of references to valid blocks.
809system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks.
810system.cpu1.dcache.avg_refs 1603.700000 # Average number of references to valid blocks.
811system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
812system.cpu1.dcache.occ_blocks::cpu1.data 24.070551 # Average occupied blocks per requestor
813system.cpu1.dcache.occ_percent::cpu1.data 0.047013 # Average percentage of cache occupancy
814system.cpu1.dcache.occ_percent::total 0.047013 # Average percentage of cache occupancy
815system.cpu1.dcache.ReadReq_hits::cpu1.data 51204 # number of ReadReq hits
816system.cpu1.dcache.ReadReq_hits::total 51204 # number of ReadReq hits
817system.cpu1.dcache.WriteReq_hits::cpu1.data 41589 # number of WriteReq hits
818system.cpu1.dcache.WriteReq_hits::total 41589 # number of WriteReq hits
819system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits
820system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits
821system.cpu1.dcache.demand_hits::cpu1.data 92793 # number of demand (read+write) hits
822system.cpu1.dcache.demand_hits::total 92793 # number of demand (read+write) hits
823system.cpu1.dcache.overall_hits::cpu1.data 92793 # number of overall hits
824system.cpu1.dcache.overall_hits::total 92793 # number of overall hits
825system.cpu1.dcache.ReadReq_misses::cpu1.data 475 # number of ReadReq misses
826system.cpu1.dcache.ReadReq_misses::total 475 # number of ReadReq misses
827system.cpu1.dcache.WriteReq_misses::cpu1.data 154 # number of WriteReq misses
828system.cpu1.dcache.WriteReq_misses::total 154 # number of WriteReq misses
829system.cpu1.dcache.SwapReq_misses::cpu1.data 50 # number of SwapReq misses
830system.cpu1.dcache.SwapReq_misses::total 50 # number of SwapReq misses
831system.cpu1.dcache.demand_misses::cpu1.data 629 # number of demand (read+write) misses
832system.cpu1.dcache.demand_misses::total 629 # number of demand (read+write) misses
833system.cpu1.dcache.overall_misses::cpu1.data 629 # number of overall misses
834system.cpu1.dcache.overall_misses::total 629 # number of overall misses
835system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9635500 # number of ReadReq miss cycles
836system.cpu1.dcache.ReadReq_miss_latency::total 9635500 # number of ReadReq miss cycles
837system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2967500 # number of WriteReq miss cycles
838system.cpu1.dcache.WriteReq_miss_latency::total 2967500 # number of WriteReq miss cycles
839system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 1038500 # number of SwapReq miss cycles
840system.cpu1.dcache.SwapReq_miss_latency::total 1038500 # number of SwapReq miss cycles
841system.cpu1.dcache.demand_miss_latency::cpu1.data 12603000 # number of demand (read+write) miss cycles
842system.cpu1.dcache.demand_miss_latency::total 12603000 # number of demand (read+write) miss cycles
843system.cpu1.dcache.overall_miss_latency::cpu1.data 12603000 # number of overall miss cycles
844system.cpu1.dcache.overall_miss_latency::total 12603000 # number of overall miss cycles
845system.cpu1.dcache.ReadReq_accesses::cpu1.data 51679 # number of ReadReq accesses(hits+misses)
846system.cpu1.dcache.ReadReq_accesses::total 51679 # number of ReadReq accesses(hits+misses)
847system.cpu1.dcache.WriteReq_accesses::cpu1.data 41743 # number of WriteReq accesses(hits+misses)
848system.cpu1.dcache.WriteReq_accesses::total 41743 # number of WriteReq accesses(hits+misses)
849system.cpu1.dcache.SwapReq_accesses::cpu1.data 62 # number of SwapReq accesses(hits+misses)
850system.cpu1.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses)
851system.cpu1.dcache.demand_accesses::cpu1.data 93422 # number of demand (read+write) accesses
852system.cpu1.dcache.demand_accesses::total 93422 # number of demand (read+write) accesses
853system.cpu1.dcache.overall_accesses::cpu1.data 93422 # number of overall (read+write) accesses
854system.cpu1.dcache.overall_accesses::total 93422 # number of overall (read+write) accesses
855system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009191 # miss rate for ReadReq accesses
| 886system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
887system.cpu1.dcache.replacements 2 # number of replacements
888system.cpu1.dcache.tagsinuse 24.070551 # Cycle average of tags in use
889system.cpu1.dcache.total_refs 48111 # Total number of references to valid blocks.
890system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks.
891system.cpu1.dcache.avg_refs 1603.700000 # Average number of references to valid blocks.
892system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
893system.cpu1.dcache.occ_blocks::cpu1.data 24.070551 # Average occupied blocks per requestor
894system.cpu1.dcache.occ_percent::cpu1.data 0.047013 # Average percentage of cache occupancy
895system.cpu1.dcache.occ_percent::total 0.047013 # Average percentage of cache occupancy
896system.cpu1.dcache.ReadReq_hits::cpu1.data 51204 # number of ReadReq hits
897system.cpu1.dcache.ReadReq_hits::total 51204 # number of ReadReq hits
898system.cpu1.dcache.WriteReq_hits::cpu1.data 41589 # number of WriteReq hits
899system.cpu1.dcache.WriteReq_hits::total 41589 # number of WriteReq hits
900system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits
901system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits
902system.cpu1.dcache.demand_hits::cpu1.data 92793 # number of demand (read+write) hits
903system.cpu1.dcache.demand_hits::total 92793 # number of demand (read+write) hits
904system.cpu1.dcache.overall_hits::cpu1.data 92793 # number of overall hits
905system.cpu1.dcache.overall_hits::total 92793 # number of overall hits
906system.cpu1.dcache.ReadReq_misses::cpu1.data 475 # number of ReadReq misses
907system.cpu1.dcache.ReadReq_misses::total 475 # number of ReadReq misses
908system.cpu1.dcache.WriteReq_misses::cpu1.data 154 # number of WriteReq misses
909system.cpu1.dcache.WriteReq_misses::total 154 # number of WriteReq misses
910system.cpu1.dcache.SwapReq_misses::cpu1.data 50 # number of SwapReq misses
911system.cpu1.dcache.SwapReq_misses::total 50 # number of SwapReq misses
912system.cpu1.dcache.demand_misses::cpu1.data 629 # number of demand (read+write) misses
913system.cpu1.dcache.demand_misses::total 629 # number of demand (read+write) misses
914system.cpu1.dcache.overall_misses::cpu1.data 629 # number of overall misses
915system.cpu1.dcache.overall_misses::total 629 # number of overall misses
916system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9635500 # number of ReadReq miss cycles
917system.cpu1.dcache.ReadReq_miss_latency::total 9635500 # number of ReadReq miss cycles
918system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2967500 # number of WriteReq miss cycles
919system.cpu1.dcache.WriteReq_miss_latency::total 2967500 # number of WriteReq miss cycles
920system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 1038500 # number of SwapReq miss cycles
921system.cpu1.dcache.SwapReq_miss_latency::total 1038500 # number of SwapReq miss cycles
922system.cpu1.dcache.demand_miss_latency::cpu1.data 12603000 # number of demand (read+write) miss cycles
923system.cpu1.dcache.demand_miss_latency::total 12603000 # number of demand (read+write) miss cycles
924system.cpu1.dcache.overall_miss_latency::cpu1.data 12603000 # number of overall miss cycles
925system.cpu1.dcache.overall_miss_latency::total 12603000 # number of overall miss cycles
926system.cpu1.dcache.ReadReq_accesses::cpu1.data 51679 # number of ReadReq accesses(hits+misses)
927system.cpu1.dcache.ReadReq_accesses::total 51679 # number of ReadReq accesses(hits+misses)
928system.cpu1.dcache.WriteReq_accesses::cpu1.data 41743 # number of WriteReq accesses(hits+misses)
929system.cpu1.dcache.WriteReq_accesses::total 41743 # number of WriteReq accesses(hits+misses)
930system.cpu1.dcache.SwapReq_accesses::cpu1.data 62 # number of SwapReq accesses(hits+misses)
931system.cpu1.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses)
932system.cpu1.dcache.demand_accesses::cpu1.data 93422 # number of demand (read+write) accesses
933system.cpu1.dcache.demand_accesses::total 93422 # number of demand (read+write) accesses
934system.cpu1.dcache.overall_accesses::cpu1.data 93422 # number of overall (read+write) accesses
935system.cpu1.dcache.overall_accesses::total 93422 # number of overall (read+write) accesses
936system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009191 # miss rate for ReadReq accesses
|
| 937system.cpu1.dcache.ReadReq_miss_rate::total 0.009191 # miss rate for ReadReq accesses
|
856system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003689 # miss rate for WriteReq accesses
| 938system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003689 # miss rate for WriteReq accesses
|
| 939system.cpu1.dcache.WriteReq_miss_rate::total 0.003689 # miss rate for WriteReq accesses
|
857system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.806452 # miss rate for SwapReq accesses
| 940system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.806452 # miss rate for SwapReq accesses
|
| 941system.cpu1.dcache.SwapReq_miss_rate::total 0.806452 # miss rate for SwapReq accesses
|
858system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006733 # miss rate for demand accesses
| 942system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006733 # miss rate for demand accesses
|
| 943system.cpu1.dcache.demand_miss_rate::total 0.006733 # miss rate for demand accesses
|
859system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006733 # miss rate for overall accesses
| 944system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006733 # miss rate for overall accesses
|
| 945system.cpu1.dcache.overall_miss_rate::total 0.006733 # miss rate for overall accesses
|
860system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20285.263158 # average ReadReq miss latency
| 946system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20285.263158 # average ReadReq miss latency
|
| 947system.cpu1.dcache.ReadReq_avg_miss_latency::total 20285.263158 # average ReadReq miss latency
|
861system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19269.480519 # average WriteReq miss latency
| 948system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19269.480519 # average WriteReq miss latency
|
| 949system.cpu1.dcache.WriteReq_avg_miss_latency::total 19269.480519 # average WriteReq miss latency
|
862system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 20770 # average SwapReq miss latency
| 950system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 20770 # average SwapReq miss latency
|
| 951system.cpu1.dcache.SwapReq_avg_miss_latency::total 20770 # average SwapReq miss latency
|
863system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20036.565978 # average overall miss latency
| 952system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20036.565978 # average overall miss latency
|
| 953system.cpu1.dcache.demand_avg_miss_latency::total 20036.565978 # average overall miss latency
|
864system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20036.565978 # average overall miss latency
| 954system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20036.565978 # average overall miss latency
|
| 955system.cpu1.dcache.overall_avg_miss_latency::total 20036.565978 # average overall miss latency
|
865system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
866system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
867system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
868system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
869system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
870system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
871system.cpu1.dcache.fast_writes 0 # number of fast writes performed
872system.cpu1.dcache.cache_copies 0 # number of cache copies performed
873system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks
874system.cpu1.dcache.writebacks::total 1 # number of writebacks
875system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 319 # number of ReadReq MSHR hits
876system.cpu1.dcache.ReadReq_mshr_hits::total 319 # number of ReadReq MSHR hits
877system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 45 # number of WriteReq MSHR hits
878system.cpu1.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits
879system.cpu1.dcache.demand_mshr_hits::cpu1.data 364 # number of demand (read+write) MSHR hits
880system.cpu1.dcache.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits
881system.cpu1.dcache.overall_mshr_hits::cpu1.data 364 # number of overall MSHR hits
882system.cpu1.dcache.overall_mshr_hits::total 364 # number of overall MSHR hits
883system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 156 # number of ReadReq MSHR misses
884system.cpu1.dcache.ReadReq_mshr_misses::total 156 # number of ReadReq MSHR misses
885system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 109 # number of WriteReq MSHR misses
886system.cpu1.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses
887system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 50 # number of SwapReq MSHR misses
888system.cpu1.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses
889system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses
890system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses
891system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses
892system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses
893system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2052000 # number of ReadReq MSHR miss cycles
894system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2052000 # number of ReadReq MSHR miss cycles
895system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1523500 # number of WriteReq MSHR miss cycles
896system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1523500 # number of WriteReq MSHR miss cycles
897system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 888500 # number of SwapReq MSHR miss cycles
898system.cpu1.dcache.SwapReq_mshr_miss_latency::total 888500 # number of SwapReq MSHR miss cycles
899system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3575500 # number of demand (read+write) MSHR miss cycles
900system.cpu1.dcache.demand_mshr_miss_latency::total 3575500 # number of demand (read+write) MSHR miss cycles
901system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3575500 # number of overall MSHR miss cycles
902system.cpu1.dcache.overall_mshr_miss_latency::total 3575500 # number of overall MSHR miss cycles
903system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003019 # mshr miss rate for ReadReq accesses
| 956system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
957system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
958system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
959system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
960system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
961system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
962system.cpu1.dcache.fast_writes 0 # number of fast writes performed
963system.cpu1.dcache.cache_copies 0 # number of cache copies performed
964system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks
965system.cpu1.dcache.writebacks::total 1 # number of writebacks
966system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 319 # number of ReadReq MSHR hits
967system.cpu1.dcache.ReadReq_mshr_hits::total 319 # number of ReadReq MSHR hits
968system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 45 # number of WriteReq MSHR hits
969system.cpu1.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits
970system.cpu1.dcache.demand_mshr_hits::cpu1.data 364 # number of demand (read+write) MSHR hits
971system.cpu1.dcache.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits
972system.cpu1.dcache.overall_mshr_hits::cpu1.data 364 # number of overall MSHR hits
973system.cpu1.dcache.overall_mshr_hits::total 364 # number of overall MSHR hits
974system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 156 # number of ReadReq MSHR misses
975system.cpu1.dcache.ReadReq_mshr_misses::total 156 # number of ReadReq MSHR misses
976system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 109 # number of WriteReq MSHR misses
977system.cpu1.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses
978system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 50 # number of SwapReq MSHR misses
979system.cpu1.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses
980system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses
981system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses
982system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses
983system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses
984system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2052000 # number of ReadReq MSHR miss cycles
985system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2052000 # number of ReadReq MSHR miss cycles
986system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1523500 # number of WriteReq MSHR miss cycles
987system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1523500 # number of WriteReq MSHR miss cycles
988system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 888500 # number of SwapReq MSHR miss cycles
989system.cpu1.dcache.SwapReq_mshr_miss_latency::total 888500 # number of SwapReq MSHR miss cycles
990system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3575500 # number of demand (read+write) MSHR miss cycles
991system.cpu1.dcache.demand_mshr_miss_latency::total 3575500 # number of demand (read+write) MSHR miss cycles
992system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3575500 # number of overall MSHR miss cycles
993system.cpu1.dcache.overall_mshr_miss_latency::total 3575500 # number of overall MSHR miss cycles
994system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003019 # mshr miss rate for ReadReq accesses
|
| 995system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003019 # mshr miss rate for ReadReq accesses
|
904system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002611 # mshr miss rate for WriteReq accesses
| 996system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002611 # mshr miss rate for WriteReq accesses
|
| 997system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002611 # mshr miss rate for WriteReq accesses
|
905system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.806452 # mshr miss rate for SwapReq accesses
| 998system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.806452 # mshr miss rate for SwapReq accesses
|
| 999system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.806452 # mshr miss rate for SwapReq accesses
|
906system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002837 # mshr miss rate for demand accesses
| 1000system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002837 # mshr miss rate for demand accesses
|
| 1001system.cpu1.dcache.demand_mshr_miss_rate::total 0.002837 # mshr miss rate for demand accesses
|
907system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002837 # mshr miss rate for overall accesses
| 1002system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002837 # mshr miss rate for overall accesses
|
| 1003system.cpu1.dcache.overall_mshr_miss_rate::total 0.002837 # mshr miss rate for overall accesses
|
908system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13153.846154 # average ReadReq mshr miss latency
| 1004system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13153.846154 # average ReadReq mshr miss latency
|
| 1005system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13153.846154 # average ReadReq mshr miss latency
|
909system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13977.064220 # average WriteReq mshr miss latency
| 1006system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13977.064220 # average WriteReq mshr miss latency
|
| 1007system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13977.064220 # average WriteReq mshr miss latency
|
910system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 17770 # average SwapReq mshr miss latency
| 1008system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 17770 # average SwapReq mshr miss latency
|
| 1009system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 17770 # average SwapReq mshr miss latency
|
911system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13492.452830 # average overall mshr miss latency
| 1010system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13492.452830 # average overall mshr miss latency
|
| 1011system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13492.452830 # average overall mshr miss latency
|
912system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13492.452830 # average overall mshr miss latency
| 1012system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13492.452830 # average overall mshr miss latency
|
| 1013system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13492.452830 # average overall mshr miss latency
|
913system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
914system.cpu2.numCycles 187102 # number of cpu cycles simulated
915system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
916system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
917system.cpu2.BPredUnit.lookups 52366 # Number of BP lookups
918system.cpu2.BPredUnit.condPredicted 49346 # Number of conditional branches predicted
919system.cpu2.BPredUnit.condIncorrect 1501 # Number of conditional branches incorrect
920system.cpu2.BPredUnit.BTBLookups 45884 # Number of BTB lookups
921system.cpu2.BPredUnit.BTBHits 44697 # Number of BTB hits
922system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
923system.cpu2.BPredUnit.usedRAS 764 # Number of times the RAS was used to get a target.
924system.cpu2.BPredUnit.RASInCorrect 230 # Number of incorrect RAS predictions.
925system.cpu2.fetch.icacheStallCycles 30829 # Number of cycles fetch is stalled on an Icache miss
926system.cpu2.fetch.Insts 289891 # Number of instructions fetch has processed
927system.cpu2.fetch.Branches 52366 # Number of branches that fetch encountered
928system.cpu2.fetch.predictedBranches 45461 # Number of branches that fetch has predicted taken
929system.cpu2.fetch.Cycles 103159 # Number of cycles fetch has run and was not squashing or blocked
930system.cpu2.fetch.SquashCycles 4491 # Number of cycles fetch has spent squashing
931system.cpu2.fetch.BlockedCycles 37226 # Number of cycles fetch has spent blocked
932system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
933system.cpu2.fetch.NoActiveThreadStallCycles 6501 # Number of stall cycles due to no active thread to fetch from
934system.cpu2.fetch.PendingTrapStallCycles 1096 # Number of stall cycles due to pending traps
935system.cpu2.fetch.CacheLines 21870 # Number of cache lines fetched
936system.cpu2.fetch.IcacheSquashes 331 # Number of outstanding Icache misses that were squashed
937system.cpu2.fetch.rateDist::samples 181728 # Number of instructions fetched each cycle (Total)
938system.cpu2.fetch.rateDist::mean 1.595192 # Number of instructions fetched each cycle (Total)
939system.cpu2.fetch.rateDist::stdev 2.120038 # Number of instructions fetched each cycle (Total)
940system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
941system.cpu2.fetch.rateDist::0 78569 43.23% 43.23% # Number of instructions fetched each cycle (Total)
942system.cpu2.fetch.rateDist::1 52779 29.04% 72.28% # Number of instructions fetched each cycle (Total)
943system.cpu2.fetch.rateDist::2 6971 3.84% 76.11% # Number of instructions fetched each cycle (Total)
944system.cpu2.fetch.rateDist::3 3518 1.94% 78.05% # Number of instructions fetched each cycle (Total)
945system.cpu2.fetch.rateDist::4 702 0.39% 78.44% # Number of instructions fetched each cycle (Total)
946system.cpu2.fetch.rateDist::5 33444 18.40% 96.84% # Number of instructions fetched each cycle (Total)
947system.cpu2.fetch.rateDist::6 1229 0.68% 97.51% # Number of instructions fetched each cycle (Total)
948system.cpu2.fetch.rateDist::7 914 0.50% 98.02% # Number of instructions fetched each cycle (Total)
949system.cpu2.fetch.rateDist::8 3602 1.98% 100.00% # Number of instructions fetched each cycle (Total)
950system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
951system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
952system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
953system.cpu2.fetch.rateDist::total 181728 # Number of instructions fetched each cycle (Total)
954system.cpu2.fetch.branchRate 0.279879 # Number of branch fetches per cycle
955system.cpu2.fetch.rate 1.549374 # Number of inst fetches per cycle
956system.cpu2.decode.IdleCycles 37176 # Number of cycles decode is idle
957system.cpu2.decode.BlockedCycles 32970 # Number of cycles decode is blocked
958system.cpu2.decode.RunCycles 96308 # Number of cycles decode is running
959system.cpu2.decode.UnblockCycles 5861 # Number of cycles decode is unblocking
960system.cpu2.decode.SquashCycles 2912 # Number of cycles decode is squashing
961system.cpu2.decode.DecodedInsts 285362 # Number of instructions handled by decode
962system.cpu2.rename.SquashCycles 2912 # Number of cycles rename is squashing
963system.cpu2.rename.IdleCycles 37970 # Number of cycles rename is idle
964system.cpu2.rename.BlockCycles 18336 # Number of cycles rename is blocking
965system.cpu2.rename.serializeStallCycles 13742 # count of cycles rename stalled for serializing inst
966system.cpu2.rename.RunCycles 90714 # Number of cycles rename is running
967system.cpu2.rename.UnblockCycles 11553 # Number of cycles rename is unblocking
968system.cpu2.rename.RenamedInsts 283108 # Number of instructions processed by rename
969system.cpu2.rename.IQFullEvents 27 # Number of times rename has blocked due to IQ full
970system.cpu2.rename.LSQFullEvents 56 # Number of times rename has blocked due to LSQ full
971system.cpu2.rename.RenamedOperands 197373 # Number of destination operands rename has renamed
972system.cpu2.rename.RenameLookups 538438 # Number of register rename lookups that rename has made
973system.cpu2.rename.int_rename_lookups 538438 # Number of integer rename lookups
974system.cpu2.rename.CommittedMaps 181356 # Number of HB maps that are committed
975system.cpu2.rename.UndoneMaps 16017 # Number of HB maps that are undone due to squashing
976system.cpu2.rename.serializingInsts 1193 # count of serializing insts renamed
977system.cpu2.rename.tempSerializingInsts 1308 # count of temporary serializing insts renamed
978system.cpu2.rename.skidInsts 14181 # count of insts added to the skid buffer
979system.cpu2.memDep0.insertedLoads 79045 # Number of loads inserted to the mem dependence unit.
980system.cpu2.memDep0.insertedStores 36977 # Number of stores inserted to the mem dependence unit.
981system.cpu2.memDep0.conflictingLoads 38155 # Number of conflicting loads.
982system.cpu2.memDep0.conflictingStores 31746 # Number of conflicting stores.
983system.cpu2.iq.iqInstsAdded 233020 # Number of instructions added to the IQ (excludes non-spec)
984system.cpu2.iq.iqNonSpecInstsAdded 7475 # Number of non-speculative instructions added to the IQ
985system.cpu2.iq.iqInstsIssued 234915 # Number of instructions issued
986system.cpu2.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued
987system.cpu2.iq.iqSquashedInstsExamined 13691 # Number of squashed instructions iterated over during squash; mainly for profiling
988system.cpu2.iq.iqSquashedOperandsExamined 12875 # Number of squashed operands that are examined and possibly removed from graph
989system.cpu2.iq.iqSquashedNonSpecRemoved 913 # Number of squashed non-spec instructions that were removed
990system.cpu2.iq.issued_per_cycle::samples 181728 # Number of insts issued each cycle
991system.cpu2.iq.issued_per_cycle::mean 1.292674 # Number of insts issued each cycle
992system.cpu2.iq.issued_per_cycle::stdev 1.310296 # Number of insts issued each cycle
993system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
994system.cpu2.iq.issued_per_cycle::0 76657 42.18% 42.18% # Number of insts issued each cycle
995system.cpu2.iq.issued_per_cycle::1 25237 13.89% 56.07% # Number of insts issued each cycle
996system.cpu2.iq.issued_per_cycle::2 37132 20.43% 76.50% # Number of insts issued each cycle
997system.cpu2.iq.issued_per_cycle::3 37732 20.76% 97.27% # Number of insts issued each cycle
998system.cpu2.iq.issued_per_cycle::4 3274 1.80% 99.07% # Number of insts issued each cycle
999system.cpu2.iq.issued_per_cycle::5 1229 0.68% 99.74% # Number of insts issued each cycle
1000system.cpu2.iq.issued_per_cycle::6 353 0.19% 99.94% # Number of insts issued each cycle
1001system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle
1002system.cpu2.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle
1003system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1004system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1005system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
1006system.cpu2.iq.issued_per_cycle::total 181728 # Number of insts issued each cycle
1007system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1008system.cpu2.iq.fu_full::IntAlu 21 6.69% 6.69% # attempts to use FU when none available
1009system.cpu2.iq.fu_full::IntMult 0 0.00% 6.69% # attempts to use FU when none available
1010system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.69% # attempts to use FU when none available
1011system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.69% # attempts to use FU when none available
1012system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.69% # attempts to use FU when none available
1013system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.69% # attempts to use FU when none available
1014system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.69% # attempts to use FU when none available
1015system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.69% # attempts to use FU when none available
1016system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.69% # attempts to use FU when none available
1017system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.69% # attempts to use FU when none available
1018system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.69% # attempts to use FU when none available
1019system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.69% # attempts to use FU when none available
1020system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.69% # attempts to use FU when none available
1021system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.69% # attempts to use FU when none available
1022system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.69% # attempts to use FU when none available
1023system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.69% # attempts to use FU when none available
1024system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.69% # attempts to use FU when none available
1025system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.69% # attempts to use FU when none available
1026system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.69% # attempts to use FU when none available
1027system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.69% # attempts to use FU when none available
1028system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.69% # attempts to use FU when none available
1029system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.69% # attempts to use FU when none available
1030system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.69% # attempts to use FU when none available
1031system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.69% # attempts to use FU when none available
1032system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.69% # attempts to use FU when none available
1033system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.69% # attempts to use FU when none available
1034system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.69% # attempts to use FU when none available
1035system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.69% # attempts to use FU when none available
1036system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.69% # attempts to use FU when none available
1037system.cpu2.iq.fu_full::MemRead 83 26.43% 33.12% # attempts to use FU when none available
1038system.cpu2.iq.fu_full::MemWrite 210 66.88% 100.00% # attempts to use FU when none available
1039system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1040system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1041system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
1042system.cpu2.iq.FU_type_0::IntAlu 114779 48.86% 48.86% # Type of FU issued
1043system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.86% # Type of FU issued
1044system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.86% # Type of FU issued
1045system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.86% # Type of FU issued
1046system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.86% # Type of FU issued
1047system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.86% # Type of FU issued
1048system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.86% # Type of FU issued
1049system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.86% # Type of FU issued
1050system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.86% # Type of FU issued
1051system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.86% # Type of FU issued
1052system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.86% # Type of FU issued
1053system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.86% # Type of FU issued
1054system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.86% # Type of FU issued
1055system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.86% # Type of FU issued
1056system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.86% # Type of FU issued
1057system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.86% # Type of FU issued
1058system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.86% # Type of FU issued
1059system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.86% # Type of FU issued
1060system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.86% # Type of FU issued
1061system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.86% # Type of FU issued
1062system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.86% # Type of FU issued
1063system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.86% # Type of FU issued
1064system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.86% # Type of FU issued
1065system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.86% # Type of FU issued
1066system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.86% # Type of FU issued
1067system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.86% # Type of FU issued
1068system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.86% # Type of FU issued
1069system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.86% # Type of FU issued
1070system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.86% # Type of FU issued
1071system.cpu2.iq.FU_type_0::MemRead 83862 35.70% 84.56% # Type of FU issued
1072system.cpu2.iq.FU_type_0::MemWrite 36274 15.44% 100.00% # Type of FU issued
1073system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1074system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1075system.cpu2.iq.FU_type_0::total 234915 # Type of FU issued
1076system.cpu2.iq.rate 1.255545 # Inst issue rate
1077system.cpu2.iq.fu_busy_cnt 314 # FU busy when requested
1078system.cpu2.iq.fu_busy_rate 0.001337 # FU busy rate (busy events/executed inst)
1079system.cpu2.iq.int_inst_queue_reads 651945 # Number of integer instruction queue reads
1080system.cpu2.iq.int_inst_queue_writes 254231 # Number of integer instruction queue writes
1081system.cpu2.iq.int_inst_queue_wakeup_accesses 232815 # Number of integer instruction queue wakeup accesses
1082system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
1083system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
1084system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
1085system.cpu2.iq.int_alu_accesses 235229 # Number of integer alu accesses
1086system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
1087system.cpu2.iew.lsq.thread0.forwLoads 31545 # Number of loads that had data forwarded from stores
1088system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1089system.cpu2.iew.lsq.thread0.squashedLoads 3013 # Number of loads squashed
1090system.cpu2.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
1091system.cpu2.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations
1092system.cpu2.iew.lsq.thread0.squashedStores 1611 # Number of stores squashed
1093system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1094system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1095system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
1096system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
1097system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1098system.cpu2.iew.iewSquashCycles 2912 # Number of cycles IEW is squashing
1099system.cpu2.iew.iewBlockCycles 1924 # Number of cycles IEW is blocking
1100system.cpu2.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking
1101system.cpu2.iew.iewDispatchedInsts 279572 # Number of instructions dispatched to IQ
1102system.cpu2.iew.iewDispSquashedInsts 369 # Number of squashed instructions skipped by dispatch
1103system.cpu2.iew.iewDispLoadInsts 79045 # Number of dispatched load instructions
1104system.cpu2.iew.iewDispStoreInsts 36977 # Number of dispatched store instructions
1105system.cpu2.iew.iewDispNonSpecInsts 1114 # Number of dispatched non-speculative instructions
1106system.cpu2.iew.iewIQFullEvents 62 # Number of times the IQ has become full, causing a stall
1107system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
1108system.cpu2.iew.memOrderViolationEvents 45 # Number of memory order violations
1109system.cpu2.iew.predictedTakenIncorrect 517 # Number of branches that were predicted taken incorrectly
1110system.cpu2.iew.predictedNotTakenIncorrect 1138 # Number of branches that were predicted not taken incorrectly
1111system.cpu2.iew.branchMispredicts 1655 # Number of branch mispredicts detected at execute
1112system.cpu2.iew.iewExecutedInsts 233532 # Number of executed instructions
1113system.cpu2.iew.iewExecLoadInsts 77718 # Number of load instructions executed
1114system.cpu2.iew.iewExecSquashedInsts 1383 # Number of squashed instructions skipped in execute
1115system.cpu2.iew.exec_swp 0 # number of swp insts executed
1116system.cpu2.iew.exec_nop 39077 # number of nop insts executed
1117system.cpu2.iew.exec_refs 113896 # number of memory reference insts executed
1118system.cpu2.iew.exec_branches 48223 # Number of branches executed
1119system.cpu2.iew.exec_stores 36178 # Number of stores executed
1120system.cpu2.iew.exec_rate 1.248153 # Inst execution rate
1121system.cpu2.iew.wb_sent 233124 # cumulative count of insts sent to commit
1122system.cpu2.iew.wb_count 232815 # cumulative count of insts written-back
1123system.cpu2.iew.wb_producers 130712 # num instructions producing a value
1124system.cpu2.iew.wb_consumers 135609 # num instructions consuming a value
1125system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1126system.cpu2.iew.wb_rate 1.244321 # insts written-back per cycle
1127system.cpu2.iew.wb_fanout 0.963889 # average fanout of values written-back
1128system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1129system.cpu2.commit.commitCommittedInsts 263733 # The number of committed instructions
1130system.cpu2.commit.commitCommittedOps 263733 # The number of committed instructions
1131system.cpu2.commit.commitSquashedInsts 15844 # The number of squashed insts skipped by commit
1132system.cpu2.commit.commitNonSpecStalls 6562 # The number of times commit has been forced to stall to communicate backwards
1133system.cpu2.commit.branchMispredicts 1501 # The number of times a branch was mispredicted
1134system.cpu2.commit.committed_per_cycle::samples 172316 # Number of insts commited each cycle
1135system.cpu2.commit.committed_per_cycle::mean 1.530520 # Number of insts commited each cycle
1136system.cpu2.commit.committed_per_cycle::stdev 1.983884 # Number of insts commited each cycle
1137system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1138system.cpu2.commit.committed_per_cycle::0 76563 44.43% 44.43% # Number of insts commited each cycle
1139system.cpu2.commit.committed_per_cycle::1 46194 26.81% 71.24% # Number of insts commited each cycle
1140system.cpu2.commit.committed_per_cycle::2 6230 3.62% 74.85% # Number of insts commited each cycle
1141system.cpu2.commit.committed_per_cycle::3 7466 4.33% 79.19% # Number of insts commited each cycle
1142system.cpu2.commit.committed_per_cycle::4 1536 0.89% 80.08% # Number of insts commited each cycle
1143system.cpu2.commit.committed_per_cycle::5 32043 18.60% 98.67% # Number of insts commited each cycle
1144system.cpu2.commit.committed_per_cycle::6 480 0.28% 98.95% # Number of insts commited each cycle
1145system.cpu2.commit.committed_per_cycle::7 990 0.57% 99.53% # Number of insts commited each cycle
1146system.cpu2.commit.committed_per_cycle::8 814 0.47% 100.00% # Number of insts commited each cycle
1147system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1148system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1149system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1150system.cpu2.commit.committed_per_cycle::total 172316 # Number of insts commited each cycle
1151system.cpu2.commit.committedInsts 263733 # Number of instructions committed
1152system.cpu2.commit.committedOps 263733 # Number of ops (including micro ops) committed
1153system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
1154system.cpu2.commit.refs 111398 # Number of memory references committed
1155system.cpu2.commit.loads 76032 # Number of loads committed
1156system.cpu2.commit.membars 5840 # Number of memory barriers committed
1157system.cpu2.commit.branches 47167 # Number of branches committed
1158system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
1159system.cpu2.commit.int_insts 180680 # Number of committed integer instructions.
1160system.cpu2.commit.function_calls 322 # Number of function calls committed.
1161system.cpu2.commit.bw_lim_events 814 # number cycles where commit BW limit reached
1162system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
1163system.cpu2.rob.rob_reads 450492 # The number of ROB reads
1164system.cpu2.rob.rob_writes 562082 # The number of ROB writes
1165system.cpu2.timesIdled 233 # Number of times that the entire CPU went into an idle state and unscheduled itself
1166system.cpu2.idleCycles 5374 # Total number of cycles that the CPU has spent unscheduled due to idling
1167system.cpu2.quiesceCycles 35702 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1168system.cpu2.committedInsts 219944 # Number of Instructions Simulated
1169system.cpu2.committedOps 219944 # Number of Ops (including micro ops) Simulated
1170system.cpu2.committedInsts_total 219944 # Number of Instructions Simulated
1171system.cpu2.cpi 0.850680 # CPI: Cycles Per Instruction
1172system.cpu2.cpi_total 0.850680 # CPI: Total CPI of All Threads
1173system.cpu2.ipc 1.175530 # IPC: Instructions Per Cycle
1174system.cpu2.ipc_total 1.175530 # IPC: Total IPC of All Threads
1175system.cpu2.int_regfile_reads 401453 # number of integer regfile reads
1176system.cpu2.int_regfile_writes 187612 # number of integer regfile writes
1177system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
1178system.cpu2.misc_regfile_reads 115545 # number of misc regfile reads
1179system.cpu2.misc_regfile_writes 646 # number of misc regfile writes
1180system.cpu2.icache.replacements 325 # number of replacements
1181system.cpu2.icache.tagsinuse 91.851117 # Cycle average of tags in use
1182system.cpu2.icache.total_refs 21358 # Total number of references to valid blocks.
1183system.cpu2.icache.sampled_refs 440 # Sample count of references to valid blocks.
1184system.cpu2.icache.avg_refs 48.540909 # Average number of references to valid blocks.
1185system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1186system.cpu2.icache.occ_blocks::cpu2.inst 91.851117 # Average occupied blocks per requestor
1187system.cpu2.icache.occ_percent::cpu2.inst 0.179397 # Average percentage of cache occupancy
1188system.cpu2.icache.occ_percent::total 0.179397 # Average percentage of cache occupancy
1189system.cpu2.icache.ReadReq_hits::cpu2.inst 21358 # number of ReadReq hits
1190system.cpu2.icache.ReadReq_hits::total 21358 # number of ReadReq hits
1191system.cpu2.icache.demand_hits::cpu2.inst 21358 # number of demand (read+write) hits
1192system.cpu2.icache.demand_hits::total 21358 # number of demand (read+write) hits
1193system.cpu2.icache.overall_hits::cpu2.inst 21358 # number of overall hits
1194system.cpu2.icache.overall_hits::total 21358 # number of overall hits
1195system.cpu2.icache.ReadReq_misses::cpu2.inst 512 # number of ReadReq misses
1196system.cpu2.icache.ReadReq_misses::total 512 # number of ReadReq misses
1197system.cpu2.icache.demand_misses::cpu2.inst 512 # number of demand (read+write) misses
1198system.cpu2.icache.demand_misses::total 512 # number of demand (read+write) misses
1199system.cpu2.icache.overall_misses::cpu2.inst 512 # number of overall misses
1200system.cpu2.icache.overall_misses::total 512 # number of overall misses
1201system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11141500 # number of ReadReq miss cycles
1202system.cpu2.icache.ReadReq_miss_latency::total 11141500 # number of ReadReq miss cycles
1203system.cpu2.icache.demand_miss_latency::cpu2.inst 11141500 # number of demand (read+write) miss cycles
1204system.cpu2.icache.demand_miss_latency::total 11141500 # number of demand (read+write) miss cycles
1205system.cpu2.icache.overall_miss_latency::cpu2.inst 11141500 # number of overall miss cycles
1206system.cpu2.icache.overall_miss_latency::total 11141500 # number of overall miss cycles
1207system.cpu2.icache.ReadReq_accesses::cpu2.inst 21870 # number of ReadReq accesses(hits+misses)
1208system.cpu2.icache.ReadReq_accesses::total 21870 # number of ReadReq accesses(hits+misses)
1209system.cpu2.icache.demand_accesses::cpu2.inst 21870 # number of demand (read+write) accesses
1210system.cpu2.icache.demand_accesses::total 21870 # number of demand (read+write) accesses
1211system.cpu2.icache.overall_accesses::cpu2.inst 21870 # number of overall (read+write) accesses
1212system.cpu2.icache.overall_accesses::total 21870 # number of overall (read+write) accesses
1213system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.023411 # miss rate for ReadReq accesses
| 1014system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1015system.cpu2.numCycles 187102 # number of cpu cycles simulated
1016system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
1017system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
1018system.cpu2.BPredUnit.lookups 52366 # Number of BP lookups
1019system.cpu2.BPredUnit.condPredicted 49346 # Number of conditional branches predicted
1020system.cpu2.BPredUnit.condIncorrect 1501 # Number of conditional branches incorrect
1021system.cpu2.BPredUnit.BTBLookups 45884 # Number of BTB lookups
1022system.cpu2.BPredUnit.BTBHits 44697 # Number of BTB hits
1023system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1024system.cpu2.BPredUnit.usedRAS 764 # Number of times the RAS was used to get a target.
1025system.cpu2.BPredUnit.RASInCorrect 230 # Number of incorrect RAS predictions.
1026system.cpu2.fetch.icacheStallCycles 30829 # Number of cycles fetch is stalled on an Icache miss
1027system.cpu2.fetch.Insts 289891 # Number of instructions fetch has processed
1028system.cpu2.fetch.Branches 52366 # Number of branches that fetch encountered
1029system.cpu2.fetch.predictedBranches 45461 # Number of branches that fetch has predicted taken
1030system.cpu2.fetch.Cycles 103159 # Number of cycles fetch has run and was not squashing or blocked
1031system.cpu2.fetch.SquashCycles 4491 # Number of cycles fetch has spent squashing
1032system.cpu2.fetch.BlockedCycles 37226 # Number of cycles fetch has spent blocked
1033system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1034system.cpu2.fetch.NoActiveThreadStallCycles 6501 # Number of stall cycles due to no active thread to fetch from
1035system.cpu2.fetch.PendingTrapStallCycles 1096 # Number of stall cycles due to pending traps
1036system.cpu2.fetch.CacheLines 21870 # Number of cache lines fetched
1037system.cpu2.fetch.IcacheSquashes 331 # Number of outstanding Icache misses that were squashed
1038system.cpu2.fetch.rateDist::samples 181728 # Number of instructions fetched each cycle (Total)
1039system.cpu2.fetch.rateDist::mean 1.595192 # Number of instructions fetched each cycle (Total)
1040system.cpu2.fetch.rateDist::stdev 2.120038 # Number of instructions fetched each cycle (Total)
1041system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1042system.cpu2.fetch.rateDist::0 78569 43.23% 43.23% # Number of instructions fetched each cycle (Total)
1043system.cpu2.fetch.rateDist::1 52779 29.04% 72.28% # Number of instructions fetched each cycle (Total)
1044system.cpu2.fetch.rateDist::2 6971 3.84% 76.11% # Number of instructions fetched each cycle (Total)
1045system.cpu2.fetch.rateDist::3 3518 1.94% 78.05% # Number of instructions fetched each cycle (Total)
1046system.cpu2.fetch.rateDist::4 702 0.39% 78.44% # Number of instructions fetched each cycle (Total)
1047system.cpu2.fetch.rateDist::5 33444 18.40% 96.84% # Number of instructions fetched each cycle (Total)
1048system.cpu2.fetch.rateDist::6 1229 0.68% 97.51% # Number of instructions fetched each cycle (Total)
1049system.cpu2.fetch.rateDist::7 914 0.50% 98.02% # Number of instructions fetched each cycle (Total)
1050system.cpu2.fetch.rateDist::8 3602 1.98% 100.00% # Number of instructions fetched each cycle (Total)
1051system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1052system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1053system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
1054system.cpu2.fetch.rateDist::total 181728 # Number of instructions fetched each cycle (Total)
1055system.cpu2.fetch.branchRate 0.279879 # Number of branch fetches per cycle
1056system.cpu2.fetch.rate 1.549374 # Number of inst fetches per cycle
1057system.cpu2.decode.IdleCycles 37176 # Number of cycles decode is idle
1058system.cpu2.decode.BlockedCycles 32970 # Number of cycles decode is blocked
1059system.cpu2.decode.RunCycles 96308 # Number of cycles decode is running
1060system.cpu2.decode.UnblockCycles 5861 # Number of cycles decode is unblocking
1061system.cpu2.decode.SquashCycles 2912 # Number of cycles decode is squashing
1062system.cpu2.decode.DecodedInsts 285362 # Number of instructions handled by decode
1063system.cpu2.rename.SquashCycles 2912 # Number of cycles rename is squashing
1064system.cpu2.rename.IdleCycles 37970 # Number of cycles rename is idle
1065system.cpu2.rename.BlockCycles 18336 # Number of cycles rename is blocking
1066system.cpu2.rename.serializeStallCycles 13742 # count of cycles rename stalled for serializing inst
1067system.cpu2.rename.RunCycles 90714 # Number of cycles rename is running
1068system.cpu2.rename.UnblockCycles 11553 # Number of cycles rename is unblocking
1069system.cpu2.rename.RenamedInsts 283108 # Number of instructions processed by rename
1070system.cpu2.rename.IQFullEvents 27 # Number of times rename has blocked due to IQ full
1071system.cpu2.rename.LSQFullEvents 56 # Number of times rename has blocked due to LSQ full
1072system.cpu2.rename.RenamedOperands 197373 # Number of destination operands rename has renamed
1073system.cpu2.rename.RenameLookups 538438 # Number of register rename lookups that rename has made
1074system.cpu2.rename.int_rename_lookups 538438 # Number of integer rename lookups
1075system.cpu2.rename.CommittedMaps 181356 # Number of HB maps that are committed
1076system.cpu2.rename.UndoneMaps 16017 # Number of HB maps that are undone due to squashing
1077system.cpu2.rename.serializingInsts 1193 # count of serializing insts renamed
1078system.cpu2.rename.tempSerializingInsts 1308 # count of temporary serializing insts renamed
1079system.cpu2.rename.skidInsts 14181 # count of insts added to the skid buffer
1080system.cpu2.memDep0.insertedLoads 79045 # Number of loads inserted to the mem dependence unit.
1081system.cpu2.memDep0.insertedStores 36977 # Number of stores inserted to the mem dependence unit.
1082system.cpu2.memDep0.conflictingLoads 38155 # Number of conflicting loads.
1083system.cpu2.memDep0.conflictingStores 31746 # Number of conflicting stores.
1084system.cpu2.iq.iqInstsAdded 233020 # Number of instructions added to the IQ (excludes non-spec)
1085system.cpu2.iq.iqNonSpecInstsAdded 7475 # Number of non-speculative instructions added to the IQ
1086system.cpu2.iq.iqInstsIssued 234915 # Number of instructions issued
1087system.cpu2.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued
1088system.cpu2.iq.iqSquashedInstsExamined 13691 # Number of squashed instructions iterated over during squash; mainly for profiling
1089system.cpu2.iq.iqSquashedOperandsExamined 12875 # Number of squashed operands that are examined and possibly removed from graph
1090system.cpu2.iq.iqSquashedNonSpecRemoved 913 # Number of squashed non-spec instructions that were removed
1091system.cpu2.iq.issued_per_cycle::samples 181728 # Number of insts issued each cycle
1092system.cpu2.iq.issued_per_cycle::mean 1.292674 # Number of insts issued each cycle
1093system.cpu2.iq.issued_per_cycle::stdev 1.310296 # Number of insts issued each cycle
1094system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1095system.cpu2.iq.issued_per_cycle::0 76657 42.18% 42.18% # Number of insts issued each cycle
1096system.cpu2.iq.issued_per_cycle::1 25237 13.89% 56.07% # Number of insts issued each cycle
1097system.cpu2.iq.issued_per_cycle::2 37132 20.43% 76.50% # Number of insts issued each cycle
1098system.cpu2.iq.issued_per_cycle::3 37732 20.76% 97.27% # Number of insts issued each cycle
1099system.cpu2.iq.issued_per_cycle::4 3274 1.80% 99.07% # Number of insts issued each cycle
1100system.cpu2.iq.issued_per_cycle::5 1229 0.68% 99.74% # Number of insts issued each cycle
1101system.cpu2.iq.issued_per_cycle::6 353 0.19% 99.94% # Number of insts issued each cycle
1102system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle
1103system.cpu2.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle
1104system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1105system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1106system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
1107system.cpu2.iq.issued_per_cycle::total 181728 # Number of insts issued each cycle
1108system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1109system.cpu2.iq.fu_full::IntAlu 21 6.69% 6.69% # attempts to use FU when none available
1110system.cpu2.iq.fu_full::IntMult 0 0.00% 6.69% # attempts to use FU when none available
1111system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.69% # attempts to use FU when none available
1112system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.69% # attempts to use FU when none available
1113system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.69% # attempts to use FU when none available
1114system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.69% # attempts to use FU when none available
1115system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.69% # attempts to use FU when none available
1116system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.69% # attempts to use FU when none available
1117system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.69% # attempts to use FU when none available
1118system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.69% # attempts to use FU when none available
1119system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.69% # attempts to use FU when none available
1120system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.69% # attempts to use FU when none available
1121system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.69% # attempts to use FU when none available
1122system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.69% # attempts to use FU when none available
1123system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.69% # attempts to use FU when none available
1124system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.69% # attempts to use FU when none available
1125system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.69% # attempts to use FU when none available
1126system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.69% # attempts to use FU when none available
1127system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.69% # attempts to use FU when none available
1128system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.69% # attempts to use FU when none available
1129system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.69% # attempts to use FU when none available
1130system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.69% # attempts to use FU when none available
1131system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.69% # attempts to use FU when none available
1132system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.69% # attempts to use FU when none available
1133system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.69% # attempts to use FU when none available
1134system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.69% # attempts to use FU when none available
1135system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.69% # attempts to use FU when none available
1136system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.69% # attempts to use FU when none available
1137system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.69% # attempts to use FU when none available
1138system.cpu2.iq.fu_full::MemRead 83 26.43% 33.12% # attempts to use FU when none available
1139system.cpu2.iq.fu_full::MemWrite 210 66.88% 100.00% # attempts to use FU when none available
1140system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1141system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1142system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
1143system.cpu2.iq.FU_type_0::IntAlu 114779 48.86% 48.86% # Type of FU issued
1144system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.86% # Type of FU issued
1145system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.86% # Type of FU issued
1146system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.86% # Type of FU issued
1147system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.86% # Type of FU issued
1148system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.86% # Type of FU issued
1149system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.86% # Type of FU issued
1150system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.86% # Type of FU issued
1151system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.86% # Type of FU issued
1152system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.86% # Type of FU issued
1153system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.86% # Type of FU issued
1154system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.86% # Type of FU issued
1155system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.86% # Type of FU issued
1156system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.86% # Type of FU issued
1157system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.86% # Type of FU issued
1158system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.86% # Type of FU issued
1159system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.86% # Type of FU issued
1160system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.86% # Type of FU issued
1161system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.86% # Type of FU issued
1162system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.86% # Type of FU issued
1163system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.86% # Type of FU issued
1164system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.86% # Type of FU issued
1165system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.86% # Type of FU issued
1166system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.86% # Type of FU issued
1167system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.86% # Type of FU issued
1168system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.86% # Type of FU issued
1169system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.86% # Type of FU issued
1170system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.86% # Type of FU issued
1171system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.86% # Type of FU issued
1172system.cpu2.iq.FU_type_0::MemRead 83862 35.70% 84.56% # Type of FU issued
1173system.cpu2.iq.FU_type_0::MemWrite 36274 15.44% 100.00% # Type of FU issued
1174system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1175system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1176system.cpu2.iq.FU_type_0::total 234915 # Type of FU issued
1177system.cpu2.iq.rate 1.255545 # Inst issue rate
1178system.cpu2.iq.fu_busy_cnt 314 # FU busy when requested
1179system.cpu2.iq.fu_busy_rate 0.001337 # FU busy rate (busy events/executed inst)
1180system.cpu2.iq.int_inst_queue_reads 651945 # Number of integer instruction queue reads
1181system.cpu2.iq.int_inst_queue_writes 254231 # Number of integer instruction queue writes
1182system.cpu2.iq.int_inst_queue_wakeup_accesses 232815 # Number of integer instruction queue wakeup accesses
1183system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
1184system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
1185system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
1186system.cpu2.iq.int_alu_accesses 235229 # Number of integer alu accesses
1187system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
1188system.cpu2.iew.lsq.thread0.forwLoads 31545 # Number of loads that had data forwarded from stores
1189system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1190system.cpu2.iew.lsq.thread0.squashedLoads 3013 # Number of loads squashed
1191system.cpu2.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
1192system.cpu2.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations
1193system.cpu2.iew.lsq.thread0.squashedStores 1611 # Number of stores squashed
1194system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1195system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1196system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
1197system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
1198system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1199system.cpu2.iew.iewSquashCycles 2912 # Number of cycles IEW is squashing
1200system.cpu2.iew.iewBlockCycles 1924 # Number of cycles IEW is blocking
1201system.cpu2.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking
1202system.cpu2.iew.iewDispatchedInsts 279572 # Number of instructions dispatched to IQ
1203system.cpu2.iew.iewDispSquashedInsts 369 # Number of squashed instructions skipped by dispatch
1204system.cpu2.iew.iewDispLoadInsts 79045 # Number of dispatched load instructions
1205system.cpu2.iew.iewDispStoreInsts 36977 # Number of dispatched store instructions
1206system.cpu2.iew.iewDispNonSpecInsts 1114 # Number of dispatched non-speculative instructions
1207system.cpu2.iew.iewIQFullEvents 62 # Number of times the IQ has become full, causing a stall
1208system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
1209system.cpu2.iew.memOrderViolationEvents 45 # Number of memory order violations
1210system.cpu2.iew.predictedTakenIncorrect 517 # Number of branches that were predicted taken incorrectly
1211system.cpu2.iew.predictedNotTakenIncorrect 1138 # Number of branches that were predicted not taken incorrectly
1212system.cpu2.iew.branchMispredicts 1655 # Number of branch mispredicts detected at execute
1213system.cpu2.iew.iewExecutedInsts 233532 # Number of executed instructions
1214system.cpu2.iew.iewExecLoadInsts 77718 # Number of load instructions executed
1215system.cpu2.iew.iewExecSquashedInsts 1383 # Number of squashed instructions skipped in execute
1216system.cpu2.iew.exec_swp 0 # number of swp insts executed
1217system.cpu2.iew.exec_nop 39077 # number of nop insts executed
1218system.cpu2.iew.exec_refs 113896 # number of memory reference insts executed
1219system.cpu2.iew.exec_branches 48223 # Number of branches executed
1220system.cpu2.iew.exec_stores 36178 # Number of stores executed
1221system.cpu2.iew.exec_rate 1.248153 # Inst execution rate
1222system.cpu2.iew.wb_sent 233124 # cumulative count of insts sent to commit
1223system.cpu2.iew.wb_count 232815 # cumulative count of insts written-back
1224system.cpu2.iew.wb_producers 130712 # num instructions producing a value
1225system.cpu2.iew.wb_consumers 135609 # num instructions consuming a value
1226system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1227system.cpu2.iew.wb_rate 1.244321 # insts written-back per cycle
1228system.cpu2.iew.wb_fanout 0.963889 # average fanout of values written-back
1229system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1230system.cpu2.commit.commitCommittedInsts 263733 # The number of committed instructions
1231system.cpu2.commit.commitCommittedOps 263733 # The number of committed instructions
1232system.cpu2.commit.commitSquashedInsts 15844 # The number of squashed insts skipped by commit
1233system.cpu2.commit.commitNonSpecStalls 6562 # The number of times commit has been forced to stall to communicate backwards
1234system.cpu2.commit.branchMispredicts 1501 # The number of times a branch was mispredicted
1235system.cpu2.commit.committed_per_cycle::samples 172316 # Number of insts commited each cycle
1236system.cpu2.commit.committed_per_cycle::mean 1.530520 # Number of insts commited each cycle
1237system.cpu2.commit.committed_per_cycle::stdev 1.983884 # Number of insts commited each cycle
1238system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1239system.cpu2.commit.committed_per_cycle::0 76563 44.43% 44.43% # Number of insts commited each cycle
1240system.cpu2.commit.committed_per_cycle::1 46194 26.81% 71.24% # Number of insts commited each cycle
1241system.cpu2.commit.committed_per_cycle::2 6230 3.62% 74.85% # Number of insts commited each cycle
1242system.cpu2.commit.committed_per_cycle::3 7466 4.33% 79.19% # Number of insts commited each cycle
1243system.cpu2.commit.committed_per_cycle::4 1536 0.89% 80.08% # Number of insts commited each cycle
1244system.cpu2.commit.committed_per_cycle::5 32043 18.60% 98.67% # Number of insts commited each cycle
1245system.cpu2.commit.committed_per_cycle::6 480 0.28% 98.95% # Number of insts commited each cycle
1246system.cpu2.commit.committed_per_cycle::7 990 0.57% 99.53% # Number of insts commited each cycle
1247system.cpu2.commit.committed_per_cycle::8 814 0.47% 100.00% # Number of insts commited each cycle
1248system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1249system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1250system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1251system.cpu2.commit.committed_per_cycle::total 172316 # Number of insts commited each cycle
1252system.cpu2.commit.committedInsts 263733 # Number of instructions committed
1253system.cpu2.commit.committedOps 263733 # Number of ops (including micro ops) committed
1254system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
1255system.cpu2.commit.refs 111398 # Number of memory references committed
1256system.cpu2.commit.loads 76032 # Number of loads committed
1257system.cpu2.commit.membars 5840 # Number of memory barriers committed
1258system.cpu2.commit.branches 47167 # Number of branches committed
1259system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
1260system.cpu2.commit.int_insts 180680 # Number of committed integer instructions.
1261system.cpu2.commit.function_calls 322 # Number of function calls committed.
1262system.cpu2.commit.bw_lim_events 814 # number cycles where commit BW limit reached
1263system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
1264system.cpu2.rob.rob_reads 450492 # The number of ROB reads
1265system.cpu2.rob.rob_writes 562082 # The number of ROB writes
1266system.cpu2.timesIdled 233 # Number of times that the entire CPU went into an idle state and unscheduled itself
1267system.cpu2.idleCycles 5374 # Total number of cycles that the CPU has spent unscheduled due to idling
1268system.cpu2.quiesceCycles 35702 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1269system.cpu2.committedInsts 219944 # Number of Instructions Simulated
1270system.cpu2.committedOps 219944 # Number of Ops (including micro ops) Simulated
1271system.cpu2.committedInsts_total 219944 # Number of Instructions Simulated
1272system.cpu2.cpi 0.850680 # CPI: Cycles Per Instruction
1273system.cpu2.cpi_total 0.850680 # CPI: Total CPI of All Threads
1274system.cpu2.ipc 1.175530 # IPC: Instructions Per Cycle
1275system.cpu2.ipc_total 1.175530 # IPC: Total IPC of All Threads
1276system.cpu2.int_regfile_reads 401453 # number of integer regfile reads
1277system.cpu2.int_regfile_writes 187612 # number of integer regfile writes
1278system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
1279system.cpu2.misc_regfile_reads 115545 # number of misc regfile reads
1280system.cpu2.misc_regfile_writes 646 # number of misc regfile writes
1281system.cpu2.icache.replacements 325 # number of replacements
1282system.cpu2.icache.tagsinuse 91.851117 # Cycle average of tags in use
1283system.cpu2.icache.total_refs 21358 # Total number of references to valid blocks.
1284system.cpu2.icache.sampled_refs 440 # Sample count of references to valid blocks.
1285system.cpu2.icache.avg_refs 48.540909 # Average number of references to valid blocks.
1286system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1287system.cpu2.icache.occ_blocks::cpu2.inst 91.851117 # Average occupied blocks per requestor
1288system.cpu2.icache.occ_percent::cpu2.inst 0.179397 # Average percentage of cache occupancy
1289system.cpu2.icache.occ_percent::total 0.179397 # Average percentage of cache occupancy
1290system.cpu2.icache.ReadReq_hits::cpu2.inst 21358 # number of ReadReq hits
1291system.cpu2.icache.ReadReq_hits::total 21358 # number of ReadReq hits
1292system.cpu2.icache.demand_hits::cpu2.inst 21358 # number of demand (read+write) hits
1293system.cpu2.icache.demand_hits::total 21358 # number of demand (read+write) hits
1294system.cpu2.icache.overall_hits::cpu2.inst 21358 # number of overall hits
1295system.cpu2.icache.overall_hits::total 21358 # number of overall hits
1296system.cpu2.icache.ReadReq_misses::cpu2.inst 512 # number of ReadReq misses
1297system.cpu2.icache.ReadReq_misses::total 512 # number of ReadReq misses
1298system.cpu2.icache.demand_misses::cpu2.inst 512 # number of demand (read+write) misses
1299system.cpu2.icache.demand_misses::total 512 # number of demand (read+write) misses
1300system.cpu2.icache.overall_misses::cpu2.inst 512 # number of overall misses
1301system.cpu2.icache.overall_misses::total 512 # number of overall misses
1302system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11141500 # number of ReadReq miss cycles
1303system.cpu2.icache.ReadReq_miss_latency::total 11141500 # number of ReadReq miss cycles
1304system.cpu2.icache.demand_miss_latency::cpu2.inst 11141500 # number of demand (read+write) miss cycles
1305system.cpu2.icache.demand_miss_latency::total 11141500 # number of demand (read+write) miss cycles
1306system.cpu2.icache.overall_miss_latency::cpu2.inst 11141500 # number of overall miss cycles
1307system.cpu2.icache.overall_miss_latency::total 11141500 # number of overall miss cycles
1308system.cpu2.icache.ReadReq_accesses::cpu2.inst 21870 # number of ReadReq accesses(hits+misses)
1309system.cpu2.icache.ReadReq_accesses::total 21870 # number of ReadReq accesses(hits+misses)
1310system.cpu2.icache.demand_accesses::cpu2.inst 21870 # number of demand (read+write) accesses
1311system.cpu2.icache.demand_accesses::total 21870 # number of demand (read+write) accesses
1312system.cpu2.icache.overall_accesses::cpu2.inst 21870 # number of overall (read+write) accesses
1313system.cpu2.icache.overall_accesses::total 21870 # number of overall (read+write) accesses
1314system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.023411 # miss rate for ReadReq accesses
|
| 1315system.cpu2.icache.ReadReq_miss_rate::total 0.023411 # miss rate for ReadReq accesses
|
1214system.cpu2.icache.demand_miss_rate::cpu2.inst 0.023411 # miss rate for demand accesses
| 1316system.cpu2.icache.demand_miss_rate::cpu2.inst 0.023411 # miss rate for demand accesses
|
| 1317system.cpu2.icache.demand_miss_rate::total 0.023411 # miss rate for demand accesses
|
1215system.cpu2.icache.overall_miss_rate::cpu2.inst 0.023411 # miss rate for overall accesses
| 1318system.cpu2.icache.overall_miss_rate::cpu2.inst 0.023411 # miss rate for overall accesses
|
| 1319system.cpu2.icache.overall_miss_rate::total 0.023411 # miss rate for overall accesses
|
1216system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 21760.742188 # average ReadReq miss latency
| 1320system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 21760.742188 # average ReadReq miss latency
|
| 1321system.cpu2.icache.ReadReq_avg_miss_latency::total 21760.742188 # average ReadReq miss latency
|
1217system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 21760.742188 # average overall miss latency
| 1322system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 21760.742188 # average overall miss latency
|
| 1323system.cpu2.icache.demand_avg_miss_latency::total 21760.742188 # average overall miss latency
|
1218system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 21760.742188 # average overall miss latency
| 1324system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 21760.742188 # average overall miss latency
|
| 1325system.cpu2.icache.overall_avg_miss_latency::total 21760.742188 # average overall miss latency
|
1219system.cpu2.icache.blocked_cycles::no_mshrs 33000 # number of cycles access was blocked
1220system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1221system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked
1222system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
1223system.cpu2.icache.avg_blocked_cycles::no_mshrs 33000 # average number of cycles each access was blocked
1224system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1225system.cpu2.icache.fast_writes 0 # number of fast writes performed
1226system.cpu2.icache.cache_copies 0 # number of cache copies performed
1227system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 72 # number of ReadReq MSHR hits
1228system.cpu2.icache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits
1229system.cpu2.icache.demand_mshr_hits::cpu2.inst 72 # number of demand (read+write) MSHR hits
1230system.cpu2.icache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits
1231system.cpu2.icache.overall_mshr_hits::cpu2.inst 72 # number of overall MSHR hits
1232system.cpu2.icache.overall_mshr_hits::total 72 # number of overall MSHR hits
1233system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 440 # number of ReadReq MSHR misses
1234system.cpu2.icache.ReadReq_mshr_misses::total 440 # number of ReadReq MSHR misses
1235system.cpu2.icache.demand_mshr_misses::cpu2.inst 440 # number of demand (read+write) MSHR misses
1236system.cpu2.icache.demand_mshr_misses::total 440 # number of demand (read+write) MSHR misses
1237system.cpu2.icache.overall_mshr_misses::cpu2.inst 440 # number of overall MSHR misses
1238system.cpu2.icache.overall_mshr_misses::total 440 # number of overall MSHR misses
1239system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 8467000 # number of ReadReq MSHR miss cycles
1240system.cpu2.icache.ReadReq_mshr_miss_latency::total 8467000 # number of ReadReq MSHR miss cycles
1241system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 8467000 # number of demand (read+write) MSHR miss cycles
1242system.cpu2.icache.demand_mshr_miss_latency::total 8467000 # number of demand (read+write) MSHR miss cycles
1243system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 8467000 # number of overall MSHR miss cycles
1244system.cpu2.icache.overall_mshr_miss_latency::total 8467000 # number of overall MSHR miss cycles
1245system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for ReadReq accesses
| 1326system.cpu2.icache.blocked_cycles::no_mshrs 33000 # number of cycles access was blocked
1327system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1328system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked
1329system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
1330system.cpu2.icache.avg_blocked_cycles::no_mshrs 33000 # average number of cycles each access was blocked
1331system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1332system.cpu2.icache.fast_writes 0 # number of fast writes performed
1333system.cpu2.icache.cache_copies 0 # number of cache copies performed
1334system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 72 # number of ReadReq MSHR hits
1335system.cpu2.icache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits
1336system.cpu2.icache.demand_mshr_hits::cpu2.inst 72 # number of demand (read+write) MSHR hits
1337system.cpu2.icache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits
1338system.cpu2.icache.overall_mshr_hits::cpu2.inst 72 # number of overall MSHR hits
1339system.cpu2.icache.overall_mshr_hits::total 72 # number of overall MSHR hits
1340system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 440 # number of ReadReq MSHR misses
1341system.cpu2.icache.ReadReq_mshr_misses::total 440 # number of ReadReq MSHR misses
1342system.cpu2.icache.demand_mshr_misses::cpu2.inst 440 # number of demand (read+write) MSHR misses
1343system.cpu2.icache.demand_mshr_misses::total 440 # number of demand (read+write) MSHR misses
1344system.cpu2.icache.overall_mshr_misses::cpu2.inst 440 # number of overall MSHR misses
1345system.cpu2.icache.overall_mshr_misses::total 440 # number of overall MSHR misses
1346system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 8467000 # number of ReadReq MSHR miss cycles
1347system.cpu2.icache.ReadReq_mshr_miss_latency::total 8467000 # number of ReadReq MSHR miss cycles
1348system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 8467000 # number of demand (read+write) MSHR miss cycles
1349system.cpu2.icache.demand_mshr_miss_latency::total 8467000 # number of demand (read+write) MSHR miss cycles
1350system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 8467000 # number of overall MSHR miss cycles
1351system.cpu2.icache.overall_mshr_miss_latency::total 8467000 # number of overall MSHR miss cycles
1352system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for ReadReq accesses
|
| 1353system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.020119 # mshr miss rate for ReadReq accesses
|
1246system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for demand accesses
| 1354system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for demand accesses
|
| 1355system.cpu2.icache.demand_mshr_miss_rate::total 0.020119 # mshr miss rate for demand accesses
|
1247system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for overall accesses
| 1356system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for overall accesses
|
| 1357system.cpu2.icache.overall_mshr_miss_rate::total 0.020119 # mshr miss rate for overall accesses
|
1248system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average ReadReq mshr miss latency
| 1358system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average ReadReq mshr miss latency
|
| 1359system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 19243.181818 # average ReadReq mshr miss latency
|
1249system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average overall mshr miss latency
| 1360system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average overall mshr miss latency
|
| 1361system.cpu2.icache.demand_avg_mshr_miss_latency::total 19243.181818 # average overall mshr miss latency
|
1250system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average overall mshr miss latency
| 1362system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average overall mshr miss latency
|
| 1363system.cpu2.icache.overall_avg_mshr_miss_latency::total 19243.181818 # average overall mshr miss latency
|
1251system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1252system.cpu2.dcache.replacements 2 # number of replacements
1253system.cpu2.dcache.tagsinuse 26.720433 # Cycle average of tags in use
1254system.cpu2.dcache.total_refs 41712 # Total number of references to valid blocks.
1255system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks.
1256system.cpu2.dcache.avg_refs 1345.548387 # Average number of references to valid blocks.
1257system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1258system.cpu2.dcache.occ_blocks::cpu2.data 26.720433 # Average occupied blocks per requestor
1259system.cpu2.dcache.occ_percent::cpu2.data 0.052188 # Average percentage of cache occupancy
1260system.cpu2.dcache.occ_percent::total 0.052188 # Average percentage of cache occupancy
1261system.cpu2.dcache.ReadReq_hits::cpu2.data 45716 # number of ReadReq hits
1262system.cpu2.dcache.ReadReq_hits::total 45716 # number of ReadReq hits
1263system.cpu2.dcache.WriteReq_hits::cpu2.data 35144 # number of WriteReq hits
1264system.cpu2.dcache.WriteReq_hits::total 35144 # number of WriteReq hits
1265system.cpu2.dcache.SwapReq_hits::cpu2.data 14 # number of SwapReq hits
1266system.cpu2.dcache.SwapReq_hits::total 14 # number of SwapReq hits
1267system.cpu2.dcache.demand_hits::cpu2.data 80860 # number of demand (read+write) hits
1268system.cpu2.dcache.demand_hits::total 80860 # number of demand (read+write) hits
1269system.cpu2.dcache.overall_hits::cpu2.data 80860 # number of overall hits
1270system.cpu2.dcache.overall_hits::total 80860 # number of overall hits
1271system.cpu2.dcache.ReadReq_misses::cpu2.data 438 # number of ReadReq misses
1272system.cpu2.dcache.ReadReq_misses::total 438 # number of ReadReq misses
1273system.cpu2.dcache.WriteReq_misses::cpu2.data 146 # number of WriteReq misses
1274system.cpu2.dcache.WriteReq_misses::total 146 # number of WriteReq misses
1275system.cpu2.dcache.SwapReq_misses::cpu2.data 62 # number of SwapReq misses
1276system.cpu2.dcache.SwapReq_misses::total 62 # number of SwapReq misses
1277system.cpu2.dcache.demand_misses::cpu2.data 584 # number of demand (read+write) misses
1278system.cpu2.dcache.demand_misses::total 584 # number of demand (read+write) misses
1279system.cpu2.dcache.overall_misses::cpu2.data 584 # number of overall misses
1280system.cpu2.dcache.overall_misses::total 584 # number of overall misses
1281system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 10255000 # number of ReadReq miss cycles
1282system.cpu2.dcache.ReadReq_miss_latency::total 10255000 # number of ReadReq miss cycles
1283system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2937000 # number of WriteReq miss cycles
1284system.cpu2.dcache.WriteReq_miss_latency::total 2937000 # number of WriteReq miss cycles
1285system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 1181000 # number of SwapReq miss cycles
1286system.cpu2.dcache.SwapReq_miss_latency::total 1181000 # number of SwapReq miss cycles
1287system.cpu2.dcache.demand_miss_latency::cpu2.data 13192000 # number of demand (read+write) miss cycles
1288system.cpu2.dcache.demand_miss_latency::total 13192000 # number of demand (read+write) miss cycles
1289system.cpu2.dcache.overall_miss_latency::cpu2.data 13192000 # number of overall miss cycles
1290system.cpu2.dcache.overall_miss_latency::total 13192000 # number of overall miss cycles
1291system.cpu2.dcache.ReadReq_accesses::cpu2.data 46154 # number of ReadReq accesses(hits+misses)
1292system.cpu2.dcache.ReadReq_accesses::total 46154 # number of ReadReq accesses(hits+misses)
1293system.cpu2.dcache.WriteReq_accesses::cpu2.data 35290 # number of WriteReq accesses(hits+misses)
1294system.cpu2.dcache.WriteReq_accesses::total 35290 # number of WriteReq accesses(hits+misses)
1295system.cpu2.dcache.SwapReq_accesses::cpu2.data 76 # number of SwapReq accesses(hits+misses)
1296system.cpu2.dcache.SwapReq_accesses::total 76 # number of SwapReq accesses(hits+misses)
1297system.cpu2.dcache.demand_accesses::cpu2.data 81444 # number of demand (read+write) accesses
1298system.cpu2.dcache.demand_accesses::total 81444 # number of demand (read+write) accesses
1299system.cpu2.dcache.overall_accesses::cpu2.data 81444 # number of overall (read+write) accesses
1300system.cpu2.dcache.overall_accesses::total 81444 # number of overall (read+write) accesses
1301system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009490 # miss rate for ReadReq accesses
| 1364system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1365system.cpu2.dcache.replacements 2 # number of replacements
1366system.cpu2.dcache.tagsinuse 26.720433 # Cycle average of tags in use
1367system.cpu2.dcache.total_refs 41712 # Total number of references to valid blocks.
1368system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks.
1369system.cpu2.dcache.avg_refs 1345.548387 # Average number of references to valid blocks.
1370system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1371system.cpu2.dcache.occ_blocks::cpu2.data 26.720433 # Average occupied blocks per requestor
1372system.cpu2.dcache.occ_percent::cpu2.data 0.052188 # Average percentage of cache occupancy
1373system.cpu2.dcache.occ_percent::total 0.052188 # Average percentage of cache occupancy
1374system.cpu2.dcache.ReadReq_hits::cpu2.data 45716 # number of ReadReq hits
1375system.cpu2.dcache.ReadReq_hits::total 45716 # number of ReadReq hits
1376system.cpu2.dcache.WriteReq_hits::cpu2.data 35144 # number of WriteReq hits
1377system.cpu2.dcache.WriteReq_hits::total 35144 # number of WriteReq hits
1378system.cpu2.dcache.SwapReq_hits::cpu2.data 14 # number of SwapReq hits
1379system.cpu2.dcache.SwapReq_hits::total 14 # number of SwapReq hits
1380system.cpu2.dcache.demand_hits::cpu2.data 80860 # number of demand (read+write) hits
1381system.cpu2.dcache.demand_hits::total 80860 # number of demand (read+write) hits
1382system.cpu2.dcache.overall_hits::cpu2.data 80860 # number of overall hits
1383system.cpu2.dcache.overall_hits::total 80860 # number of overall hits
1384system.cpu2.dcache.ReadReq_misses::cpu2.data 438 # number of ReadReq misses
1385system.cpu2.dcache.ReadReq_misses::total 438 # number of ReadReq misses
1386system.cpu2.dcache.WriteReq_misses::cpu2.data 146 # number of WriteReq misses
1387system.cpu2.dcache.WriteReq_misses::total 146 # number of WriteReq misses
1388system.cpu2.dcache.SwapReq_misses::cpu2.data 62 # number of SwapReq misses
1389system.cpu2.dcache.SwapReq_misses::total 62 # number of SwapReq misses
1390system.cpu2.dcache.demand_misses::cpu2.data 584 # number of demand (read+write) misses
1391system.cpu2.dcache.demand_misses::total 584 # number of demand (read+write) misses
1392system.cpu2.dcache.overall_misses::cpu2.data 584 # number of overall misses
1393system.cpu2.dcache.overall_misses::total 584 # number of overall misses
1394system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 10255000 # number of ReadReq miss cycles
1395system.cpu2.dcache.ReadReq_miss_latency::total 10255000 # number of ReadReq miss cycles
1396system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2937000 # number of WriteReq miss cycles
1397system.cpu2.dcache.WriteReq_miss_latency::total 2937000 # number of WriteReq miss cycles
1398system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 1181000 # number of SwapReq miss cycles
1399system.cpu2.dcache.SwapReq_miss_latency::total 1181000 # number of SwapReq miss cycles
1400system.cpu2.dcache.demand_miss_latency::cpu2.data 13192000 # number of demand (read+write) miss cycles
1401system.cpu2.dcache.demand_miss_latency::total 13192000 # number of demand (read+write) miss cycles
1402system.cpu2.dcache.overall_miss_latency::cpu2.data 13192000 # number of overall miss cycles
1403system.cpu2.dcache.overall_miss_latency::total 13192000 # number of overall miss cycles
1404system.cpu2.dcache.ReadReq_accesses::cpu2.data 46154 # number of ReadReq accesses(hits+misses)
1405system.cpu2.dcache.ReadReq_accesses::total 46154 # number of ReadReq accesses(hits+misses)
1406system.cpu2.dcache.WriteReq_accesses::cpu2.data 35290 # number of WriteReq accesses(hits+misses)
1407system.cpu2.dcache.WriteReq_accesses::total 35290 # number of WriteReq accesses(hits+misses)
1408system.cpu2.dcache.SwapReq_accesses::cpu2.data 76 # number of SwapReq accesses(hits+misses)
1409system.cpu2.dcache.SwapReq_accesses::total 76 # number of SwapReq accesses(hits+misses)
1410system.cpu2.dcache.demand_accesses::cpu2.data 81444 # number of demand (read+write) accesses
1411system.cpu2.dcache.demand_accesses::total 81444 # number of demand (read+write) accesses
1412system.cpu2.dcache.overall_accesses::cpu2.data 81444 # number of overall (read+write) accesses
1413system.cpu2.dcache.overall_accesses::total 81444 # number of overall (read+write) accesses
1414system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009490 # miss rate for ReadReq accesses
|
| 1415system.cpu2.dcache.ReadReq_miss_rate::total 0.009490 # miss rate for ReadReq accesses
|
1302system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004137 # miss rate for WriteReq accesses
| 1416system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004137 # miss rate for WriteReq accesses
|
| 1417system.cpu2.dcache.WriteReq_miss_rate::total 0.004137 # miss rate for WriteReq accesses
|
1303system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.815789 # miss rate for SwapReq accesses
| 1418system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.815789 # miss rate for SwapReq accesses
|
| 1419system.cpu2.dcache.SwapReq_miss_rate::total 0.815789 # miss rate for SwapReq accesses
|
1304system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007171 # miss rate for demand accesses
| 1420system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007171 # miss rate for demand accesses
|
| 1421system.cpu2.dcache.demand_miss_rate::total 0.007171 # miss rate for demand accesses
|
1305system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007171 # miss rate for overall accesses
| 1422system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007171 # miss rate for overall accesses
|
| 1423system.cpu2.dcache.overall_miss_rate::total 0.007171 # miss rate for overall accesses
|
1306system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23413.242009 # average ReadReq miss latency
| 1424system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23413.242009 # average ReadReq miss latency
|
| 1425system.cpu2.dcache.ReadReq_avg_miss_latency::total 23413.242009 # average ReadReq miss latency
|
1307system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20116.438356 # average WriteReq miss latency
| 1426system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20116.438356 # average WriteReq miss latency
|
| 1427system.cpu2.dcache.WriteReq_avg_miss_latency::total 20116.438356 # average WriteReq miss latency
|
1308system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 19048.387097 # average SwapReq miss latency
| 1428system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 19048.387097 # average SwapReq miss latency
|
| 1429system.cpu2.dcache.SwapReq_avg_miss_latency::total 19048.387097 # average SwapReq miss latency
|
1309system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22589.041096 # average overall miss latency
| 1430system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22589.041096 # average overall miss latency
|
| 1431system.cpu2.dcache.demand_avg_miss_latency::total 22589.041096 # average overall miss latency
|
1310system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22589.041096 # average overall miss latency
| 1432system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22589.041096 # average overall miss latency
|
| 1433system.cpu2.dcache.overall_avg_miss_latency::total 22589.041096 # average overall miss latency
|
1311system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1312system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1313system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1314system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
1315system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1316system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1317system.cpu2.dcache.fast_writes 0 # number of fast writes performed
1318system.cpu2.dcache.cache_copies 0 # number of cache copies performed
1319system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks
1320system.cpu2.dcache.writebacks::total 1 # number of writebacks
1321system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 267 # number of ReadReq MSHR hits
1322system.cpu2.dcache.ReadReq_mshr_hits::total 267 # number of ReadReq MSHR hits
1323system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 45 # number of WriteReq MSHR hits
1324system.cpu2.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits
1325system.cpu2.dcache.demand_mshr_hits::cpu2.data 312 # number of demand (read+write) MSHR hits
1326system.cpu2.dcache.demand_mshr_hits::total 312 # number of demand (read+write) MSHR hits
1327system.cpu2.dcache.overall_mshr_hits::cpu2.data 312 # number of overall MSHR hits
1328system.cpu2.dcache.overall_mshr_hits::total 312 # number of overall MSHR hits
1329system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 171 # number of ReadReq MSHR misses
1330system.cpu2.dcache.ReadReq_mshr_misses::total 171 # number of ReadReq MSHR misses
1331system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 101 # number of WriteReq MSHR misses
1332system.cpu2.dcache.WriteReq_mshr_misses::total 101 # number of WriteReq MSHR misses
1333system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 62 # number of SwapReq MSHR misses
1334system.cpu2.dcache.SwapReq_mshr_misses::total 62 # number of SwapReq MSHR misses
1335system.cpu2.dcache.demand_mshr_misses::cpu2.data 272 # number of demand (read+write) MSHR misses
1336system.cpu2.dcache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses
1337system.cpu2.dcache.overall_mshr_misses::cpu2.data 272 # number of overall MSHR misses
1338system.cpu2.dcache.overall_mshr_misses::total 272 # number of overall MSHR misses
1339system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2480000 # number of ReadReq MSHR miss cycles
1340system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2480000 # number of ReadReq MSHR miss cycles
1341system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1516500 # number of WriteReq MSHR miss cycles
1342system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1516500 # number of WriteReq MSHR miss cycles
1343system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 995000 # number of SwapReq MSHR miss cycles
1344system.cpu2.dcache.SwapReq_mshr_miss_latency::total 995000 # number of SwapReq MSHR miss cycles
1345system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3996500 # number of demand (read+write) MSHR miss cycles
1346system.cpu2.dcache.demand_mshr_miss_latency::total 3996500 # number of demand (read+write) MSHR miss cycles
1347system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3996500 # number of overall MSHR miss cycles
1348system.cpu2.dcache.overall_mshr_miss_latency::total 3996500 # number of overall MSHR miss cycles
1349system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003705 # mshr miss rate for ReadReq accesses
| 1434system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1435system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1436system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1437system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
1438system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1439system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1440system.cpu2.dcache.fast_writes 0 # number of fast writes performed
1441system.cpu2.dcache.cache_copies 0 # number of cache copies performed
1442system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks
1443system.cpu2.dcache.writebacks::total 1 # number of writebacks
1444system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 267 # number of ReadReq MSHR hits
1445system.cpu2.dcache.ReadReq_mshr_hits::total 267 # number of ReadReq MSHR hits
1446system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 45 # number of WriteReq MSHR hits
1447system.cpu2.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits
1448system.cpu2.dcache.demand_mshr_hits::cpu2.data 312 # number of demand (read+write) MSHR hits
1449system.cpu2.dcache.demand_mshr_hits::total 312 # number of demand (read+write) MSHR hits
1450system.cpu2.dcache.overall_mshr_hits::cpu2.data 312 # number of overall MSHR hits
1451system.cpu2.dcache.overall_mshr_hits::total 312 # number of overall MSHR hits
1452system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 171 # number of ReadReq MSHR misses
1453system.cpu2.dcache.ReadReq_mshr_misses::total 171 # number of ReadReq MSHR misses
1454system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 101 # number of WriteReq MSHR misses
1455system.cpu2.dcache.WriteReq_mshr_misses::total 101 # number of WriteReq MSHR misses
1456system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 62 # number of SwapReq MSHR misses
1457system.cpu2.dcache.SwapReq_mshr_misses::total 62 # number of SwapReq MSHR misses
1458system.cpu2.dcache.demand_mshr_misses::cpu2.data 272 # number of demand (read+write) MSHR misses
1459system.cpu2.dcache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses
1460system.cpu2.dcache.overall_mshr_misses::cpu2.data 272 # number of overall MSHR misses
1461system.cpu2.dcache.overall_mshr_misses::total 272 # number of overall MSHR misses
1462system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2480000 # number of ReadReq MSHR miss cycles
1463system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2480000 # number of ReadReq MSHR miss cycles
1464system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1516500 # number of WriteReq MSHR miss cycles
1465system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1516500 # number of WriteReq MSHR miss cycles
1466system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 995000 # number of SwapReq MSHR miss cycles
1467system.cpu2.dcache.SwapReq_mshr_miss_latency::total 995000 # number of SwapReq MSHR miss cycles
1468system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3996500 # number of demand (read+write) MSHR miss cycles
1469system.cpu2.dcache.demand_mshr_miss_latency::total 3996500 # number of demand (read+write) MSHR miss cycles
1470system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3996500 # number of overall MSHR miss cycles
1471system.cpu2.dcache.overall_mshr_miss_latency::total 3996500 # number of overall MSHR miss cycles
1472system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003705 # mshr miss rate for ReadReq accesses
|
| 1473system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003705 # mshr miss rate for ReadReq accesses
|
1350system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002862 # mshr miss rate for WriteReq accesses
| 1474system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002862 # mshr miss rate for WriteReq accesses
|
| 1475system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002862 # mshr miss rate for WriteReq accesses
|
1351system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.815789 # mshr miss rate for SwapReq accesses
| 1476system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.815789 # mshr miss rate for SwapReq accesses
|
| 1477system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.815789 # mshr miss rate for SwapReq accesses
|
1352system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003340 # mshr miss rate for demand accesses
| 1478system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003340 # mshr miss rate for demand accesses
|
| 1479system.cpu2.dcache.demand_mshr_miss_rate::total 0.003340 # mshr miss rate for demand accesses
|
1353system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003340 # mshr miss rate for overall accesses
| 1480system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003340 # mshr miss rate for overall accesses
|
| 1481system.cpu2.dcache.overall_mshr_miss_rate::total 0.003340 # mshr miss rate for overall accesses
|
1354system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14502.923977 # average ReadReq mshr miss latency
| 1482system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14502.923977 # average ReadReq mshr miss latency
|
| 1483system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 14502.923977 # average ReadReq mshr miss latency
|
1355system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15014.851485 # average WriteReq mshr miss latency
| 1484system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15014.851485 # average WriteReq mshr miss latency
|
| 1485system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15014.851485 # average WriteReq mshr miss latency
|
1356system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 16048.387097 # average SwapReq mshr miss latency
| 1486system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 16048.387097 # average SwapReq mshr miss latency
|
| 1487system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 16048.387097 # average SwapReq mshr miss latency
|
1357system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14693.014706 # average overall mshr miss latency
| 1488system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14693.014706 # average overall mshr miss latency
|
| 1489system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14693.014706 # average overall mshr miss latency
|
1358system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14693.014706 # average overall mshr miss latency
| 1490system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14693.014706 # average overall mshr miss latency
|
| 1491system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14693.014706 # average overall mshr miss latency
|
1359system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1360system.cpu3.numCycles 186832 # number of cpu cycles simulated
1361system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
1362system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
1363system.cpu3.BPredUnit.lookups 49447 # Number of BP lookups
1364system.cpu3.BPredUnit.condPredicted 46344 # Number of conditional branches predicted
1365system.cpu3.BPredUnit.condIncorrect 1525 # Number of conditional branches incorrect
1366system.cpu3.BPredUnit.BTBLookups 42752 # Number of BTB lookups
1367system.cpu3.BPredUnit.BTBHits 41712 # Number of BTB hits
1368system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1369system.cpu3.BPredUnit.usedRAS 813 # Number of times the RAS was used to get a target.
1370system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
1371system.cpu3.fetch.icacheStallCycles 32933 # Number of cycles fetch is stalled on an Icache miss
1372system.cpu3.fetch.Insts 270157 # Number of instructions fetch has processed
1373system.cpu3.fetch.Branches 49447 # Number of branches that fetch encountered
1374system.cpu3.fetch.predictedBranches 42525 # Number of branches that fetch has predicted taken
1375system.cpu3.fetch.Cycles 98584 # Number of cycles fetch has run and was not squashing or blocked
1376system.cpu3.fetch.SquashCycles 4439 # Number of cycles fetch has spent squashing
1377system.cpu3.fetch.BlockedCycles 41922 # Number of cycles fetch has spent blocked
1378system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1379system.cpu3.fetch.NoActiveThreadStallCycles 6509 # Number of stall cycles due to no active thread to fetch from
1380system.cpu3.fetch.PendingTrapStallCycles 1070 # Number of stall cycles due to pending traps
1381system.cpu3.fetch.CacheLines 24454 # Number of cache lines fetched
1382system.cpu3.fetch.IcacheSquashes 317 # Number of outstanding Icache misses that were squashed
1383system.cpu3.fetch.rateDist::samples 183862 # Number of instructions fetched each cycle (Total)
1384system.cpu3.fetch.rateDist::mean 1.469347 # Number of instructions fetched each cycle (Total)
1385system.cpu3.fetch.rateDist::stdev 2.064581 # Number of instructions fetched each cycle (Total)
1386system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1387system.cpu3.fetch.rateDist::0 85278 46.38% 46.38% # Number of instructions fetched each cycle (Total)
1388system.cpu3.fetch.rateDist::1 51117 27.80% 74.18% # Number of instructions fetched each cycle (Total)
1389system.cpu3.fetch.rateDist::2 8231 4.48% 78.66% # Number of instructions fetched each cycle (Total)
1390system.cpu3.fetch.rateDist::3 3382 1.84% 80.50% # Number of instructions fetched each cycle (Total)
1391system.cpu3.fetch.rateDist::4 704 0.38% 80.88% # Number of instructions fetched each cycle (Total)
1392system.cpu3.fetch.rateDist::5 29457 16.02% 96.90% # Number of instructions fetched each cycle (Total)
1393system.cpu3.fetch.rateDist::6 1168 0.64% 97.54% # Number of instructions fetched each cycle (Total)
1394system.cpu3.fetch.rateDist::7 877 0.48% 98.02% # Number of instructions fetched each cycle (Total)
1395system.cpu3.fetch.rateDist::8 3648 1.98% 100.00% # Number of instructions fetched each cycle (Total)
1396system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1397system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1398system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
1399system.cpu3.fetch.rateDist::total 183862 # Number of instructions fetched each cycle (Total)
1400system.cpu3.fetch.branchRate 0.264660 # Number of branch fetches per cycle
1401system.cpu3.fetch.rate 1.445989 # Number of inst fetches per cycle
1402system.cpu3.decode.IdleCycles 40520 # Number of cycles decode is idle
1403system.cpu3.decode.BlockedCycles 36424 # Number of cycles decode is blocked
1404system.cpu3.decode.RunCycles 90525 # Number of cycles decode is running
1405system.cpu3.decode.UnblockCycles 7045 # Number of cycles decode is unblocking
1406system.cpu3.decode.SquashCycles 2839 # Number of cycles decode is squashing
1407system.cpu3.decode.DecodedInsts 265643 # Number of instructions handled by decode
1408system.cpu3.rename.SquashCycles 2839 # Number of cycles rename is squashing
1409system.cpu3.rename.IdleCycles 41308 # Number of cycles rename is idle
1410system.cpu3.rename.BlockCycles 21637 # Number of cycles rename is blocking
1411system.cpu3.rename.serializeStallCycles 13915 # count of cycles rename stalled for serializing inst
1412system.cpu3.rename.RunCycles 83785 # Number of cycles rename is running
1413system.cpu3.rename.UnblockCycles 13869 # Number of cycles rename is unblocking
1414system.cpu3.rename.RenamedInsts 263122 # Number of instructions processed by rename
1415system.cpu3.rename.IQFullEvents 18 # Number of times rename has blocked due to IQ full
1416system.cpu3.rename.LSQFullEvents 51 # Number of times rename has blocked due to LSQ full
1417system.cpu3.rename.RenamedOperands 182223 # Number of destination operands rename has renamed
1418system.cpu3.rename.RenameLookups 494224 # Number of register rename lookups that rename has made
1419system.cpu3.rename.int_rename_lookups 494224 # Number of integer rename lookups
1420system.cpu3.rename.CommittedMaps 166723 # Number of HB maps that are committed
1421system.cpu3.rename.UndoneMaps 15500 # Number of HB maps that are undone due to squashing
1422system.cpu3.rename.serializingInsts 1230 # count of serializing insts renamed
1423system.cpu3.rename.tempSerializingInsts 1367 # count of temporary serializing insts renamed
1424system.cpu3.rename.skidInsts 16602 # count of insts added to the skid buffer
1425system.cpu3.memDep0.insertedLoads 72088 # Number of loads inserted to the mem dependence unit.
1426system.cpu3.memDep0.insertedStores 32971 # Number of stores inserted to the mem dependence unit.
1427system.cpu3.memDep0.conflictingLoads 35168 # Number of conflicting loads.
1428system.cpu3.memDep0.conflictingStores 27743 # Number of conflicting stores.
1429system.cpu3.iq.iqInstsAdded 215022 # Number of instructions added to the IQ (excludes non-spec)
1430system.cpu3.iq.iqNonSpecInstsAdded 8560 # Number of non-speculative instructions added to the IQ
1431system.cpu3.iq.iqInstsIssued 218529 # Number of instructions issued
1432system.cpu3.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued
1433system.cpu3.iq.iqSquashedInstsExamined 12998 # Number of squashed instructions iterated over during squash; mainly for profiling
1434system.cpu3.iq.iqSquashedOperandsExamined 11805 # Number of squashed operands that are examined and possibly removed from graph
1435system.cpu3.iq.iqSquashedNonSpecRemoved 824 # Number of squashed non-spec instructions that were removed
1436system.cpu3.iq.issued_per_cycle::samples 183862 # Number of insts issued each cycle
1437system.cpu3.iq.issued_per_cycle::mean 1.188549 # Number of insts issued each cycle
1438system.cpu3.iq.issued_per_cycle::stdev 1.293380 # Number of insts issued each cycle
1439system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1440system.cpu3.iq.issued_per_cycle::0 83207 45.26% 45.26% # Number of insts issued each cycle
1441system.cpu3.iq.issued_per_cycle::1 28783 15.65% 60.91% # Number of insts issued each cycle
1442system.cpu3.iq.issued_per_cycle::2 33187 18.05% 78.96% # Number of insts issued each cycle
1443system.cpu3.iq.issued_per_cycle::3 33716 18.34% 97.30% # Number of insts issued each cycle
1444system.cpu3.iq.issued_per_cycle::4 3245 1.76% 99.06% # Number of insts issued each cycle
1445system.cpu3.iq.issued_per_cycle::5 1264 0.69% 99.75% # Number of insts issued each cycle
1446system.cpu3.iq.issued_per_cycle::6 353 0.19% 99.94% # Number of insts issued each cycle
1447system.cpu3.iq.issued_per_cycle::7 50 0.03% 99.97% # Number of insts issued each cycle
1448system.cpu3.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle
1449system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1450system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1451system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
1452system.cpu3.iq.issued_per_cycle::total 183862 # Number of insts issued each cycle
1453system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1454system.cpu3.iq.fu_full::IntAlu 21 7.02% 7.02% # attempts to use FU when none available
1455system.cpu3.iq.fu_full::IntMult 0 0.00% 7.02% # attempts to use FU when none available
1456system.cpu3.iq.fu_full::IntDiv 0 0.00% 7.02% # attempts to use FU when none available
1457system.cpu3.iq.fu_full::FloatAdd 0 0.00% 7.02% # attempts to use FU when none available
1458system.cpu3.iq.fu_full::FloatCmp 0 0.00% 7.02% # attempts to use FU when none available
1459system.cpu3.iq.fu_full::FloatCvt 0 0.00% 7.02% # attempts to use FU when none available
1460system.cpu3.iq.fu_full::FloatMult 0 0.00% 7.02% # attempts to use FU when none available
1461system.cpu3.iq.fu_full::FloatDiv 0 0.00% 7.02% # attempts to use FU when none available
1462system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 7.02% # attempts to use FU when none available
1463system.cpu3.iq.fu_full::SimdAdd 0 0.00% 7.02% # attempts to use FU when none available
1464system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 7.02% # attempts to use FU when none available
1465system.cpu3.iq.fu_full::SimdAlu 0 0.00% 7.02% # attempts to use FU when none available
1466system.cpu3.iq.fu_full::SimdCmp 0 0.00% 7.02% # attempts to use FU when none available
1467system.cpu3.iq.fu_full::SimdCvt 0 0.00% 7.02% # attempts to use FU when none available
1468system.cpu3.iq.fu_full::SimdMisc 0 0.00% 7.02% # attempts to use FU when none available
1469system.cpu3.iq.fu_full::SimdMult 0 0.00% 7.02% # attempts to use FU when none available
1470system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 7.02% # attempts to use FU when none available
1471system.cpu3.iq.fu_full::SimdShift 0 0.00% 7.02% # attempts to use FU when none available
1472system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 7.02% # attempts to use FU when none available
1473system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 7.02% # attempts to use FU when none available
1474system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 7.02% # attempts to use FU when none available
1475system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 7.02% # attempts to use FU when none available
1476system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 7.02% # attempts to use FU when none available
1477system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 7.02% # attempts to use FU when none available
1478system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 7.02% # attempts to use FU when none available
1479system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 7.02% # attempts to use FU when none available
1480system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 7.02% # attempts to use FU when none available
1481system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.02% # attempts to use FU when none available
1482system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 7.02% # attempts to use FU when none available
1483system.cpu3.iq.fu_full::MemRead 68 22.74% 29.77% # attempts to use FU when none available
1484system.cpu3.iq.fu_full::MemWrite 210 70.23% 100.00% # attempts to use FU when none available
1485system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1486system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1487system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
1488system.cpu3.iq.FU_type_0::IntAlu 107929 49.39% 49.39% # Type of FU issued
1489system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.39% # Type of FU issued
1490system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.39% # Type of FU issued
1491system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.39% # Type of FU issued
1492system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.39% # Type of FU issued
1493system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.39% # Type of FU issued
1494system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.39% # Type of FU issued
1495system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.39% # Type of FU issued
1496system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.39% # Type of FU issued
1497system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.39% # Type of FU issued
1498system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.39% # Type of FU issued
1499system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.39% # Type of FU issued
1500system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.39% # Type of FU issued
1501system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.39% # Type of FU issued
1502system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.39% # Type of FU issued
1503system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.39% # Type of FU issued
1504system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.39% # Type of FU issued
1505system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.39% # Type of FU issued
1506system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.39% # Type of FU issued
1507system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.39% # Type of FU issued
1508system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.39% # Type of FU issued
1509system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.39% # Type of FU issued
1510system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.39% # Type of FU issued
1511system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.39% # Type of FU issued
1512system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.39% # Type of FU issued
1513system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.39% # Type of FU issued
1514system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.39% # Type of FU issued
1515system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.39% # Type of FU issued
1516system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.39% # Type of FU issued
1517system.cpu3.iq.FU_type_0::MemRead 78286 35.82% 85.21% # Type of FU issued
1518system.cpu3.iq.FU_type_0::MemWrite 32314 14.79% 100.00% # Type of FU issued
1519system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1520system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1521system.cpu3.iq.FU_type_0::total 218529 # Type of FU issued
1522system.cpu3.iq.rate 1.169655 # Inst issue rate
1523system.cpu3.iq.fu_busy_cnt 299 # FU busy when requested
1524system.cpu3.iq.fu_busy_rate 0.001368 # FU busy rate (busy events/executed inst)
1525system.cpu3.iq.int_inst_queue_reads 621265 # Number of integer instruction queue reads
1526system.cpu3.iq.int_inst_queue_writes 236621 # Number of integer instruction queue writes
1527system.cpu3.iq.int_inst_queue_wakeup_accesses 216530 # Number of integer instruction queue wakeup accesses
1528system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
1529system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
1530system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
1531system.cpu3.iq.int_alu_accesses 218828 # Number of integer alu accesses
1532system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
1533system.cpu3.iew.lsq.thread0.forwLoads 27592 # Number of loads that had data forwarded from stores
1534system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1535system.cpu3.iew.lsq.thread0.squashedLoads 2778 # Number of loads squashed
1536system.cpu3.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
1537system.cpu3.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations
1538system.cpu3.iew.lsq.thread0.squashedStores 1562 # Number of stores squashed
1539system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1540system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1541system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
1542system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
1543system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1544system.cpu3.iew.iewSquashCycles 2839 # Number of cycles IEW is squashing
1545system.cpu3.iew.iewBlockCycles 1746 # Number of cycles IEW is blocking
1546system.cpu3.iew.iewUnblockCycles 57 # Number of cycles IEW is unblocking
1547system.cpu3.iew.iewDispatchedInsts 259780 # Number of instructions dispatched to IQ
1548system.cpu3.iew.iewDispSquashedInsts 389 # Number of squashed instructions skipped by dispatch
1549system.cpu3.iew.iewDispLoadInsts 72088 # Number of dispatched load instructions
1550system.cpu3.iew.iewDispStoreInsts 32971 # Number of dispatched store instructions
1551system.cpu3.iew.iewDispNonSpecInsts 1143 # Number of dispatched non-speculative instructions
1552system.cpu3.iew.iewIQFullEvents 55 # Number of times the IQ has become full, causing a stall
1553system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
1554system.cpu3.iew.memOrderViolationEvents 41 # Number of memory order violations
1555system.cpu3.iew.predictedTakenIncorrect 513 # Number of branches that were predicted taken incorrectly
1556system.cpu3.iew.predictedNotTakenIncorrect 1186 # Number of branches that were predicted not taken incorrectly
1557system.cpu3.iew.branchMispredicts 1699 # Number of branch mispredicts detected at execute
1558system.cpu3.iew.iewExecutedInsts 217228 # Number of executed instructions
1559system.cpu3.iew.iewExecLoadInsts 70964 # Number of load instructions executed
1560system.cpu3.iew.iewExecSquashedInsts 1301 # Number of squashed instructions skipped in execute
1561system.cpu3.iew.exec_swp 0 # number of swp insts executed
1562system.cpu3.iew.exec_nop 36198 # number of nop insts executed
1563system.cpu3.iew.exec_refs 103196 # number of memory reference insts executed
1564system.cpu3.iew.exec_branches 45494 # Number of branches executed
1565system.cpu3.iew.exec_stores 32232 # Number of stores executed
1566system.cpu3.iew.exec_rate 1.162692 # Inst execution rate
1567system.cpu3.iew.wb_sent 216841 # cumulative count of insts sent to commit
1568system.cpu3.iew.wb_count 216530 # cumulative count of insts written-back
1569system.cpu3.iew.wb_producers 119982 # num instructions producing a value
1570system.cpu3.iew.wb_consumers 124874 # num instructions consuming a value
1571system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1572system.cpu3.iew.wb_rate 1.158956 # insts written-back per cycle
1573system.cpu3.iew.wb_fanout 0.960825 # average fanout of values written-back
1574system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1575system.cpu3.commit.commitCommittedInsts 244729 # The number of committed instructions
1576system.cpu3.commit.commitCommittedOps 244729 # The number of committed instructions
1577system.cpu3.commit.commitSquashedInsts 15046 # The number of squashed insts skipped by commit
1578system.cpu3.commit.commitNonSpecStalls 7736 # The number of times commit has been forced to stall to communicate backwards
1579system.cpu3.commit.branchMispredicts 1525 # The number of times a branch was mispredicted
1580system.cpu3.commit.committed_per_cycle::samples 174515 # Number of insts commited each cycle
1581system.cpu3.commit.committed_per_cycle::mean 1.402338 # Number of insts commited each cycle
1582system.cpu3.commit.committed_per_cycle::stdev 1.927125 # Number of insts commited each cycle
1583system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1584system.cpu3.commit.committed_per_cycle::0 84328 48.32% 48.32% # Number of insts commited each cycle
1585system.cpu3.commit.committed_per_cycle::1 43439 24.89% 73.21% # Number of insts commited each cycle
1586system.cpu3.commit.committed_per_cycle::2 6199 3.55% 76.76% # Number of insts commited each cycle
1587system.cpu3.commit.committed_per_cycle::3 8632 4.95% 81.71% # Number of insts commited each cycle
1588system.cpu3.commit.committed_per_cycle::4 1540 0.88% 82.59% # Number of insts commited each cycle
1589system.cpu3.commit.committed_per_cycle::5 28042 16.07% 98.66% # Number of insts commited each cycle
1590system.cpu3.commit.committed_per_cycle::6 531 0.30% 98.97% # Number of insts commited each cycle
1591system.cpu3.commit.committed_per_cycle::7 992 0.57% 99.53% # Number of insts commited each cycle
1592system.cpu3.commit.committed_per_cycle::8 812 0.47% 100.00% # Number of insts commited each cycle
1593system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1594system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1595system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1596system.cpu3.commit.committed_per_cycle::total 174515 # Number of insts commited each cycle
1597system.cpu3.commit.committedInsts 244729 # Number of instructions committed
1598system.cpu3.commit.committedOps 244729 # Number of ops (including micro ops) committed
1599system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
1600system.cpu3.commit.refs 100719 # Number of memory references committed
1601system.cpu3.commit.loads 69310 # Number of loads committed
1602system.cpu3.commit.membars 7019 # Number of memory barriers committed
1603system.cpu3.commit.branches 44389 # Number of branches committed
1604system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
1605system.cpu3.commit.int_insts 167227 # Number of committed integer instructions.
1606system.cpu3.commit.function_calls 322 # Number of function calls committed.
1607system.cpu3.commit.bw_lim_events 812 # number cycles where commit BW limit reached
1608system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits
1609system.cpu3.rob.rob_reads 432891 # The number of ROB reads
1610system.cpu3.rob.rob_writes 522404 # The number of ROB writes
1611system.cpu3.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself
1612system.cpu3.idleCycles 2970 # Total number of cycles that the CPU has spent unscheduled due to idling
1613system.cpu3.quiesceCycles 35972 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1614system.cpu3.committedInsts 202534 # Number of Instructions Simulated
1615system.cpu3.committedOps 202534 # Number of Ops (including micro ops) Simulated
1616system.cpu3.committedInsts_total 202534 # Number of Instructions Simulated
1617system.cpu3.cpi 0.922472 # CPI: Cycles Per Instruction
1618system.cpu3.cpi_total 0.922472 # CPI: Total CPI of All Threads
1619system.cpu3.ipc 1.084043 # IPC: Instructions Per Cycle
1620system.cpu3.ipc_total 1.084043 # IPC: Total IPC of All Threads
1621system.cpu3.int_regfile_reads 369217 # number of integer regfile reads
1622system.cpu3.int_regfile_writes 172842 # number of integer regfile writes
1623system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
1624system.cpu3.misc_regfile_reads 104868 # number of misc regfile reads
1625system.cpu3.misc_regfile_writes 646 # number of misc regfile writes
1626system.cpu3.icache.replacements 320 # number of replacements
1627system.cpu3.icache.tagsinuse 85.923076 # Cycle average of tags in use
1628system.cpu3.icache.total_refs 23951 # Total number of references to valid blocks.
1629system.cpu3.icache.sampled_refs 432 # Sample count of references to valid blocks.
1630system.cpu3.icache.avg_refs 55.442130 # Average number of references to valid blocks.
1631system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1632system.cpu3.icache.occ_blocks::cpu3.inst 85.923076 # Average occupied blocks per requestor
1633system.cpu3.icache.occ_percent::cpu3.inst 0.167819 # Average percentage of cache occupancy
1634system.cpu3.icache.occ_percent::total 0.167819 # Average percentage of cache occupancy
1635system.cpu3.icache.ReadReq_hits::cpu3.inst 23951 # number of ReadReq hits
1636system.cpu3.icache.ReadReq_hits::total 23951 # number of ReadReq hits
1637system.cpu3.icache.demand_hits::cpu3.inst 23951 # number of demand (read+write) hits
1638system.cpu3.icache.demand_hits::total 23951 # number of demand (read+write) hits
1639system.cpu3.icache.overall_hits::cpu3.inst 23951 # number of overall hits
1640system.cpu3.icache.overall_hits::total 23951 # number of overall hits
1641system.cpu3.icache.ReadReq_misses::cpu3.inst 503 # number of ReadReq misses
1642system.cpu3.icache.ReadReq_misses::total 503 # number of ReadReq misses
1643system.cpu3.icache.demand_misses::cpu3.inst 503 # number of demand (read+write) misses
1644system.cpu3.icache.demand_misses::total 503 # number of demand (read+write) misses
1645system.cpu3.icache.overall_misses::cpu3.inst 503 # number of overall misses
1646system.cpu3.icache.overall_misses::total 503 # number of overall misses
1647system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6843000 # number of ReadReq miss cycles
1648system.cpu3.icache.ReadReq_miss_latency::total 6843000 # number of ReadReq miss cycles
1649system.cpu3.icache.demand_miss_latency::cpu3.inst 6843000 # number of demand (read+write) miss cycles
1650system.cpu3.icache.demand_miss_latency::total 6843000 # number of demand (read+write) miss cycles
1651system.cpu3.icache.overall_miss_latency::cpu3.inst 6843000 # number of overall miss cycles
1652system.cpu3.icache.overall_miss_latency::total 6843000 # number of overall miss cycles
1653system.cpu3.icache.ReadReq_accesses::cpu3.inst 24454 # number of ReadReq accesses(hits+misses)
1654system.cpu3.icache.ReadReq_accesses::total 24454 # number of ReadReq accesses(hits+misses)
1655system.cpu3.icache.demand_accesses::cpu3.inst 24454 # number of demand (read+write) accesses
1656system.cpu3.icache.demand_accesses::total 24454 # number of demand (read+write) accesses
1657system.cpu3.icache.overall_accesses::cpu3.inst 24454 # number of overall (read+write) accesses
1658system.cpu3.icache.overall_accesses::total 24454 # number of overall (read+write) accesses
1659system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020569 # miss rate for ReadReq accesses
| 1492system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1493system.cpu3.numCycles 186832 # number of cpu cycles simulated
1494system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
1495system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
1496system.cpu3.BPredUnit.lookups 49447 # Number of BP lookups
1497system.cpu3.BPredUnit.condPredicted 46344 # Number of conditional branches predicted
1498system.cpu3.BPredUnit.condIncorrect 1525 # Number of conditional branches incorrect
1499system.cpu3.BPredUnit.BTBLookups 42752 # Number of BTB lookups
1500system.cpu3.BPredUnit.BTBHits 41712 # Number of BTB hits
1501system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1502system.cpu3.BPredUnit.usedRAS 813 # Number of times the RAS was used to get a target.
1503system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
1504system.cpu3.fetch.icacheStallCycles 32933 # Number of cycles fetch is stalled on an Icache miss
1505system.cpu3.fetch.Insts 270157 # Number of instructions fetch has processed
1506system.cpu3.fetch.Branches 49447 # Number of branches that fetch encountered
1507system.cpu3.fetch.predictedBranches 42525 # Number of branches that fetch has predicted taken
1508system.cpu3.fetch.Cycles 98584 # Number of cycles fetch has run and was not squashing or blocked
1509system.cpu3.fetch.SquashCycles 4439 # Number of cycles fetch has spent squashing
1510system.cpu3.fetch.BlockedCycles 41922 # Number of cycles fetch has spent blocked
1511system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1512system.cpu3.fetch.NoActiveThreadStallCycles 6509 # Number of stall cycles due to no active thread to fetch from
1513system.cpu3.fetch.PendingTrapStallCycles 1070 # Number of stall cycles due to pending traps
1514system.cpu3.fetch.CacheLines 24454 # Number of cache lines fetched
1515system.cpu3.fetch.IcacheSquashes 317 # Number of outstanding Icache misses that were squashed
1516system.cpu3.fetch.rateDist::samples 183862 # Number of instructions fetched each cycle (Total)
1517system.cpu3.fetch.rateDist::mean 1.469347 # Number of instructions fetched each cycle (Total)
1518system.cpu3.fetch.rateDist::stdev 2.064581 # Number of instructions fetched each cycle (Total)
1519system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1520system.cpu3.fetch.rateDist::0 85278 46.38% 46.38% # Number of instructions fetched each cycle (Total)
1521system.cpu3.fetch.rateDist::1 51117 27.80% 74.18% # Number of instructions fetched each cycle (Total)
1522system.cpu3.fetch.rateDist::2 8231 4.48% 78.66% # Number of instructions fetched each cycle (Total)
1523system.cpu3.fetch.rateDist::3 3382 1.84% 80.50% # Number of instructions fetched each cycle (Total)
1524system.cpu3.fetch.rateDist::4 704 0.38% 80.88% # Number of instructions fetched each cycle (Total)
1525system.cpu3.fetch.rateDist::5 29457 16.02% 96.90% # Number of instructions fetched each cycle (Total)
1526system.cpu3.fetch.rateDist::6 1168 0.64% 97.54% # Number of instructions fetched each cycle (Total)
1527system.cpu3.fetch.rateDist::7 877 0.48% 98.02% # Number of instructions fetched each cycle (Total)
1528system.cpu3.fetch.rateDist::8 3648 1.98% 100.00% # Number of instructions fetched each cycle (Total)
1529system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1530system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1531system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
1532system.cpu3.fetch.rateDist::total 183862 # Number of instructions fetched each cycle (Total)
1533system.cpu3.fetch.branchRate 0.264660 # Number of branch fetches per cycle
1534system.cpu3.fetch.rate 1.445989 # Number of inst fetches per cycle
1535system.cpu3.decode.IdleCycles 40520 # Number of cycles decode is idle
1536system.cpu3.decode.BlockedCycles 36424 # Number of cycles decode is blocked
1537system.cpu3.decode.RunCycles 90525 # Number of cycles decode is running
1538system.cpu3.decode.UnblockCycles 7045 # Number of cycles decode is unblocking
1539system.cpu3.decode.SquashCycles 2839 # Number of cycles decode is squashing
1540system.cpu3.decode.DecodedInsts 265643 # Number of instructions handled by decode
1541system.cpu3.rename.SquashCycles 2839 # Number of cycles rename is squashing
1542system.cpu3.rename.IdleCycles 41308 # Number of cycles rename is idle
1543system.cpu3.rename.BlockCycles 21637 # Number of cycles rename is blocking
1544system.cpu3.rename.serializeStallCycles 13915 # count of cycles rename stalled for serializing inst
1545system.cpu3.rename.RunCycles 83785 # Number of cycles rename is running
1546system.cpu3.rename.UnblockCycles 13869 # Number of cycles rename is unblocking
1547system.cpu3.rename.RenamedInsts 263122 # Number of instructions processed by rename
1548system.cpu3.rename.IQFullEvents 18 # Number of times rename has blocked due to IQ full
1549system.cpu3.rename.LSQFullEvents 51 # Number of times rename has blocked due to LSQ full
1550system.cpu3.rename.RenamedOperands 182223 # Number of destination operands rename has renamed
1551system.cpu3.rename.RenameLookups 494224 # Number of register rename lookups that rename has made
1552system.cpu3.rename.int_rename_lookups 494224 # Number of integer rename lookups
1553system.cpu3.rename.CommittedMaps 166723 # Number of HB maps that are committed
1554system.cpu3.rename.UndoneMaps 15500 # Number of HB maps that are undone due to squashing
1555system.cpu3.rename.serializingInsts 1230 # count of serializing insts renamed
1556system.cpu3.rename.tempSerializingInsts 1367 # count of temporary serializing insts renamed
1557system.cpu3.rename.skidInsts 16602 # count of insts added to the skid buffer
1558system.cpu3.memDep0.insertedLoads 72088 # Number of loads inserted to the mem dependence unit.
1559system.cpu3.memDep0.insertedStores 32971 # Number of stores inserted to the mem dependence unit.
1560system.cpu3.memDep0.conflictingLoads 35168 # Number of conflicting loads.
1561system.cpu3.memDep0.conflictingStores 27743 # Number of conflicting stores.
1562system.cpu3.iq.iqInstsAdded 215022 # Number of instructions added to the IQ (excludes non-spec)
1563system.cpu3.iq.iqNonSpecInstsAdded 8560 # Number of non-speculative instructions added to the IQ
1564system.cpu3.iq.iqInstsIssued 218529 # Number of instructions issued
1565system.cpu3.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued
1566system.cpu3.iq.iqSquashedInstsExamined 12998 # Number of squashed instructions iterated over during squash; mainly for profiling
1567system.cpu3.iq.iqSquashedOperandsExamined 11805 # Number of squashed operands that are examined and possibly removed from graph
1568system.cpu3.iq.iqSquashedNonSpecRemoved 824 # Number of squashed non-spec instructions that were removed
1569system.cpu3.iq.issued_per_cycle::samples 183862 # Number of insts issued each cycle
1570system.cpu3.iq.issued_per_cycle::mean 1.188549 # Number of insts issued each cycle
1571system.cpu3.iq.issued_per_cycle::stdev 1.293380 # Number of insts issued each cycle
1572system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1573system.cpu3.iq.issued_per_cycle::0 83207 45.26% 45.26% # Number of insts issued each cycle
1574system.cpu3.iq.issued_per_cycle::1 28783 15.65% 60.91% # Number of insts issued each cycle
1575system.cpu3.iq.issued_per_cycle::2 33187 18.05% 78.96% # Number of insts issued each cycle
1576system.cpu3.iq.issued_per_cycle::3 33716 18.34% 97.30% # Number of insts issued each cycle
1577system.cpu3.iq.issued_per_cycle::4 3245 1.76% 99.06% # Number of insts issued each cycle
1578system.cpu3.iq.issued_per_cycle::5 1264 0.69% 99.75% # Number of insts issued each cycle
1579system.cpu3.iq.issued_per_cycle::6 353 0.19% 99.94% # Number of insts issued each cycle
1580system.cpu3.iq.issued_per_cycle::7 50 0.03% 99.97% # Number of insts issued each cycle
1581system.cpu3.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle
1582system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1583system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1584system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
1585system.cpu3.iq.issued_per_cycle::total 183862 # Number of insts issued each cycle
1586system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1587system.cpu3.iq.fu_full::IntAlu 21 7.02% 7.02% # attempts to use FU when none available
1588system.cpu3.iq.fu_full::IntMult 0 0.00% 7.02% # attempts to use FU when none available
1589system.cpu3.iq.fu_full::IntDiv 0 0.00% 7.02% # attempts to use FU when none available
1590system.cpu3.iq.fu_full::FloatAdd 0 0.00% 7.02% # attempts to use FU when none available
1591system.cpu3.iq.fu_full::FloatCmp 0 0.00% 7.02% # attempts to use FU when none available
1592system.cpu3.iq.fu_full::FloatCvt 0 0.00% 7.02% # attempts to use FU when none available
1593system.cpu3.iq.fu_full::FloatMult 0 0.00% 7.02% # attempts to use FU when none available
1594system.cpu3.iq.fu_full::FloatDiv 0 0.00% 7.02% # attempts to use FU when none available
1595system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 7.02% # attempts to use FU when none available
1596system.cpu3.iq.fu_full::SimdAdd 0 0.00% 7.02% # attempts to use FU when none available
1597system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 7.02% # attempts to use FU when none available
1598system.cpu3.iq.fu_full::SimdAlu 0 0.00% 7.02% # attempts to use FU when none available
1599system.cpu3.iq.fu_full::SimdCmp 0 0.00% 7.02% # attempts to use FU when none available
1600system.cpu3.iq.fu_full::SimdCvt 0 0.00% 7.02% # attempts to use FU when none available
1601system.cpu3.iq.fu_full::SimdMisc 0 0.00% 7.02% # attempts to use FU when none available
1602system.cpu3.iq.fu_full::SimdMult 0 0.00% 7.02% # attempts to use FU when none available
1603system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 7.02% # attempts to use FU when none available
1604system.cpu3.iq.fu_full::SimdShift 0 0.00% 7.02% # attempts to use FU when none available
1605system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 7.02% # attempts to use FU when none available
1606system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 7.02% # attempts to use FU when none available
1607system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 7.02% # attempts to use FU when none available
1608system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 7.02% # attempts to use FU when none available
1609system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 7.02% # attempts to use FU when none available
1610system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 7.02% # attempts to use FU when none available
1611system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 7.02% # attempts to use FU when none available
1612system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 7.02% # attempts to use FU when none available
1613system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 7.02% # attempts to use FU when none available
1614system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.02% # attempts to use FU when none available
1615system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 7.02% # attempts to use FU when none available
1616system.cpu3.iq.fu_full::MemRead 68 22.74% 29.77% # attempts to use FU when none available
1617system.cpu3.iq.fu_full::MemWrite 210 70.23% 100.00% # attempts to use FU when none available
1618system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1619system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1620system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
1621system.cpu3.iq.FU_type_0::IntAlu 107929 49.39% 49.39% # Type of FU issued
1622system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.39% # Type of FU issued
1623system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.39% # Type of FU issued
1624system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.39% # Type of FU issued
1625system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.39% # Type of FU issued
1626system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.39% # Type of FU issued
1627system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.39% # Type of FU issued
1628system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.39% # Type of FU issued
1629system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.39% # Type of FU issued
1630system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.39% # Type of FU issued
1631system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.39% # Type of FU issued
1632system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.39% # Type of FU issued
1633system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.39% # Type of FU issued
1634system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.39% # Type of FU issued
1635system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.39% # Type of FU issued
1636system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.39% # Type of FU issued
1637system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.39% # Type of FU issued
1638system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.39% # Type of FU issued
1639system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.39% # Type of FU issued
1640system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.39% # Type of FU issued
1641system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.39% # Type of FU issued
1642system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.39% # Type of FU issued
1643system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.39% # Type of FU issued
1644system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.39% # Type of FU issued
1645system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.39% # Type of FU issued
1646system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.39% # Type of FU issued
1647system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.39% # Type of FU issued
1648system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.39% # Type of FU issued
1649system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.39% # Type of FU issued
1650system.cpu3.iq.FU_type_0::MemRead 78286 35.82% 85.21% # Type of FU issued
1651system.cpu3.iq.FU_type_0::MemWrite 32314 14.79% 100.00% # Type of FU issued
1652system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1653system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1654system.cpu3.iq.FU_type_0::total 218529 # Type of FU issued
1655system.cpu3.iq.rate 1.169655 # Inst issue rate
1656system.cpu3.iq.fu_busy_cnt 299 # FU busy when requested
1657system.cpu3.iq.fu_busy_rate 0.001368 # FU busy rate (busy events/executed inst)
1658system.cpu3.iq.int_inst_queue_reads 621265 # Number of integer instruction queue reads
1659system.cpu3.iq.int_inst_queue_writes 236621 # Number of integer instruction queue writes
1660system.cpu3.iq.int_inst_queue_wakeup_accesses 216530 # Number of integer instruction queue wakeup accesses
1661system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
1662system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
1663system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
1664system.cpu3.iq.int_alu_accesses 218828 # Number of integer alu accesses
1665system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
1666system.cpu3.iew.lsq.thread0.forwLoads 27592 # Number of loads that had data forwarded from stores
1667system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1668system.cpu3.iew.lsq.thread0.squashedLoads 2778 # Number of loads squashed
1669system.cpu3.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
1670system.cpu3.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations
1671system.cpu3.iew.lsq.thread0.squashedStores 1562 # Number of stores squashed
1672system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1673system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1674system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
1675system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
1676system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1677system.cpu3.iew.iewSquashCycles 2839 # Number of cycles IEW is squashing
1678system.cpu3.iew.iewBlockCycles 1746 # Number of cycles IEW is blocking
1679system.cpu3.iew.iewUnblockCycles 57 # Number of cycles IEW is unblocking
1680system.cpu3.iew.iewDispatchedInsts 259780 # Number of instructions dispatched to IQ
1681system.cpu3.iew.iewDispSquashedInsts 389 # Number of squashed instructions skipped by dispatch
1682system.cpu3.iew.iewDispLoadInsts 72088 # Number of dispatched load instructions
1683system.cpu3.iew.iewDispStoreInsts 32971 # Number of dispatched store instructions
1684system.cpu3.iew.iewDispNonSpecInsts 1143 # Number of dispatched non-speculative instructions
1685system.cpu3.iew.iewIQFullEvents 55 # Number of times the IQ has become full, causing a stall
1686system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
1687system.cpu3.iew.memOrderViolationEvents 41 # Number of memory order violations
1688system.cpu3.iew.predictedTakenIncorrect 513 # Number of branches that were predicted taken incorrectly
1689system.cpu3.iew.predictedNotTakenIncorrect 1186 # Number of branches that were predicted not taken incorrectly
1690system.cpu3.iew.branchMispredicts 1699 # Number of branch mispredicts detected at execute
1691system.cpu3.iew.iewExecutedInsts 217228 # Number of executed instructions
1692system.cpu3.iew.iewExecLoadInsts 70964 # Number of load instructions executed
1693system.cpu3.iew.iewExecSquashedInsts 1301 # Number of squashed instructions skipped in execute
1694system.cpu3.iew.exec_swp 0 # number of swp insts executed
1695system.cpu3.iew.exec_nop 36198 # number of nop insts executed
1696system.cpu3.iew.exec_refs 103196 # number of memory reference insts executed
1697system.cpu3.iew.exec_branches 45494 # Number of branches executed
1698system.cpu3.iew.exec_stores 32232 # Number of stores executed
1699system.cpu3.iew.exec_rate 1.162692 # Inst execution rate
1700system.cpu3.iew.wb_sent 216841 # cumulative count of insts sent to commit
1701system.cpu3.iew.wb_count 216530 # cumulative count of insts written-back
1702system.cpu3.iew.wb_producers 119982 # num instructions producing a value
1703system.cpu3.iew.wb_consumers 124874 # num instructions consuming a value
1704system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1705system.cpu3.iew.wb_rate 1.158956 # insts written-back per cycle
1706system.cpu3.iew.wb_fanout 0.960825 # average fanout of values written-back
1707system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1708system.cpu3.commit.commitCommittedInsts 244729 # The number of committed instructions
1709system.cpu3.commit.commitCommittedOps 244729 # The number of committed instructions
1710system.cpu3.commit.commitSquashedInsts 15046 # The number of squashed insts skipped by commit
1711system.cpu3.commit.commitNonSpecStalls 7736 # The number of times commit has been forced to stall to communicate backwards
1712system.cpu3.commit.branchMispredicts 1525 # The number of times a branch was mispredicted
1713system.cpu3.commit.committed_per_cycle::samples 174515 # Number of insts commited each cycle
1714system.cpu3.commit.committed_per_cycle::mean 1.402338 # Number of insts commited each cycle
1715system.cpu3.commit.committed_per_cycle::stdev 1.927125 # Number of insts commited each cycle
1716system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1717system.cpu3.commit.committed_per_cycle::0 84328 48.32% 48.32% # Number of insts commited each cycle
1718system.cpu3.commit.committed_per_cycle::1 43439 24.89% 73.21% # Number of insts commited each cycle
1719system.cpu3.commit.committed_per_cycle::2 6199 3.55% 76.76% # Number of insts commited each cycle
1720system.cpu3.commit.committed_per_cycle::3 8632 4.95% 81.71% # Number of insts commited each cycle
1721system.cpu3.commit.committed_per_cycle::4 1540 0.88% 82.59% # Number of insts commited each cycle
1722system.cpu3.commit.committed_per_cycle::5 28042 16.07% 98.66% # Number of insts commited each cycle
1723system.cpu3.commit.committed_per_cycle::6 531 0.30% 98.97% # Number of insts commited each cycle
1724system.cpu3.commit.committed_per_cycle::7 992 0.57% 99.53% # Number of insts commited each cycle
1725system.cpu3.commit.committed_per_cycle::8 812 0.47% 100.00% # Number of insts commited each cycle
1726system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1727system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1728system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1729system.cpu3.commit.committed_per_cycle::total 174515 # Number of insts commited each cycle
1730system.cpu3.commit.committedInsts 244729 # Number of instructions committed
1731system.cpu3.commit.committedOps 244729 # Number of ops (including micro ops) committed
1732system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
1733system.cpu3.commit.refs 100719 # Number of memory references committed
1734system.cpu3.commit.loads 69310 # Number of loads committed
1735system.cpu3.commit.membars 7019 # Number of memory barriers committed
1736system.cpu3.commit.branches 44389 # Number of branches committed
1737system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
1738system.cpu3.commit.int_insts 167227 # Number of committed integer instructions.
1739system.cpu3.commit.function_calls 322 # Number of function calls committed.
1740system.cpu3.commit.bw_lim_events 812 # number cycles where commit BW limit reached
1741system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits
1742system.cpu3.rob.rob_reads 432891 # The number of ROB reads
1743system.cpu3.rob.rob_writes 522404 # The number of ROB writes
1744system.cpu3.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself
1745system.cpu3.idleCycles 2970 # Total number of cycles that the CPU has spent unscheduled due to idling
1746system.cpu3.quiesceCycles 35972 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1747system.cpu3.committedInsts 202534 # Number of Instructions Simulated
1748system.cpu3.committedOps 202534 # Number of Ops (including micro ops) Simulated
1749system.cpu3.committedInsts_total 202534 # Number of Instructions Simulated
1750system.cpu3.cpi 0.922472 # CPI: Cycles Per Instruction
1751system.cpu3.cpi_total 0.922472 # CPI: Total CPI of All Threads
1752system.cpu3.ipc 1.084043 # IPC: Instructions Per Cycle
1753system.cpu3.ipc_total 1.084043 # IPC: Total IPC of All Threads
1754system.cpu3.int_regfile_reads 369217 # number of integer regfile reads
1755system.cpu3.int_regfile_writes 172842 # number of integer regfile writes
1756system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
1757system.cpu3.misc_regfile_reads 104868 # number of misc regfile reads
1758system.cpu3.misc_regfile_writes 646 # number of misc regfile writes
1759system.cpu3.icache.replacements 320 # number of replacements
1760system.cpu3.icache.tagsinuse 85.923076 # Cycle average of tags in use
1761system.cpu3.icache.total_refs 23951 # Total number of references to valid blocks.
1762system.cpu3.icache.sampled_refs 432 # Sample count of references to valid blocks.
1763system.cpu3.icache.avg_refs 55.442130 # Average number of references to valid blocks.
1764system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1765system.cpu3.icache.occ_blocks::cpu3.inst 85.923076 # Average occupied blocks per requestor
1766system.cpu3.icache.occ_percent::cpu3.inst 0.167819 # Average percentage of cache occupancy
1767system.cpu3.icache.occ_percent::total 0.167819 # Average percentage of cache occupancy
1768system.cpu3.icache.ReadReq_hits::cpu3.inst 23951 # number of ReadReq hits
1769system.cpu3.icache.ReadReq_hits::total 23951 # number of ReadReq hits
1770system.cpu3.icache.demand_hits::cpu3.inst 23951 # number of demand (read+write) hits
1771system.cpu3.icache.demand_hits::total 23951 # number of demand (read+write) hits
1772system.cpu3.icache.overall_hits::cpu3.inst 23951 # number of overall hits
1773system.cpu3.icache.overall_hits::total 23951 # number of overall hits
1774system.cpu3.icache.ReadReq_misses::cpu3.inst 503 # number of ReadReq misses
1775system.cpu3.icache.ReadReq_misses::total 503 # number of ReadReq misses
1776system.cpu3.icache.demand_misses::cpu3.inst 503 # number of demand (read+write) misses
1777system.cpu3.icache.demand_misses::total 503 # number of demand (read+write) misses
1778system.cpu3.icache.overall_misses::cpu3.inst 503 # number of overall misses
1779system.cpu3.icache.overall_misses::total 503 # number of overall misses
1780system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6843000 # number of ReadReq miss cycles
1781system.cpu3.icache.ReadReq_miss_latency::total 6843000 # number of ReadReq miss cycles
1782system.cpu3.icache.demand_miss_latency::cpu3.inst 6843000 # number of demand (read+write) miss cycles
1783system.cpu3.icache.demand_miss_latency::total 6843000 # number of demand (read+write) miss cycles
1784system.cpu3.icache.overall_miss_latency::cpu3.inst 6843000 # number of overall miss cycles
1785system.cpu3.icache.overall_miss_latency::total 6843000 # number of overall miss cycles
1786system.cpu3.icache.ReadReq_accesses::cpu3.inst 24454 # number of ReadReq accesses(hits+misses)
1787system.cpu3.icache.ReadReq_accesses::total 24454 # number of ReadReq accesses(hits+misses)
1788system.cpu3.icache.demand_accesses::cpu3.inst 24454 # number of demand (read+write) accesses
1789system.cpu3.icache.demand_accesses::total 24454 # number of demand (read+write) accesses
1790system.cpu3.icache.overall_accesses::cpu3.inst 24454 # number of overall (read+write) accesses
1791system.cpu3.icache.overall_accesses::total 24454 # number of overall (read+write) accesses
1792system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020569 # miss rate for ReadReq accesses
|
| 1793system.cpu3.icache.ReadReq_miss_rate::total 0.020569 # miss rate for ReadReq accesses
|
1660system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020569 # miss rate for demand accesses
| 1794system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020569 # miss rate for demand accesses
|
| 1795system.cpu3.icache.demand_miss_rate::total 0.020569 # miss rate for demand accesses
|
1661system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020569 # miss rate for overall accesses
| 1796system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020569 # miss rate for overall accesses
|
| 1797system.cpu3.icache.overall_miss_rate::total 0.020569 # miss rate for overall accesses
|
1662system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13604.373757 # average ReadReq miss latency
| 1798system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13604.373757 # average ReadReq miss latency
|
| 1799system.cpu3.icache.ReadReq_avg_miss_latency::total 13604.373757 # average ReadReq miss latency
|
1663system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13604.373757 # average overall miss latency
| 1800system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13604.373757 # average overall miss latency
|
| 1801system.cpu3.icache.demand_avg_miss_latency::total 13604.373757 # average overall miss latency
|
1664system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13604.373757 # average overall miss latency
| 1802system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13604.373757 # average overall miss latency
|
| 1803system.cpu3.icache.overall_avg_miss_latency::total 13604.373757 # average overall miss latency
|
1665system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1666system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1667system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1668system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
1669system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1670system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1671system.cpu3.icache.fast_writes 0 # number of fast writes performed
1672system.cpu3.icache.cache_copies 0 # number of cache copies performed
1673system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 71 # number of ReadReq MSHR hits
1674system.cpu3.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits
1675system.cpu3.icache.demand_mshr_hits::cpu3.inst 71 # number of demand (read+write) MSHR hits
1676system.cpu3.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits
1677system.cpu3.icache.overall_mshr_hits::cpu3.inst 71 # number of overall MSHR hits
1678system.cpu3.icache.overall_mshr_hits::total 71 # number of overall MSHR hits
1679system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 432 # number of ReadReq MSHR misses
1680system.cpu3.icache.ReadReq_mshr_misses::total 432 # number of ReadReq MSHR misses
1681system.cpu3.icache.demand_mshr_misses::cpu3.inst 432 # number of demand (read+write) MSHR misses
1682system.cpu3.icache.demand_mshr_misses::total 432 # number of demand (read+write) MSHR misses
1683system.cpu3.icache.overall_mshr_misses::cpu3.inst 432 # number of overall MSHR misses
1684system.cpu3.icache.overall_mshr_misses::total 432 # number of overall MSHR misses
1685system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4912000 # number of ReadReq MSHR miss cycles
1686system.cpu3.icache.ReadReq_mshr_miss_latency::total 4912000 # number of ReadReq MSHR miss cycles
1687system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4912000 # number of demand (read+write) MSHR miss cycles
1688system.cpu3.icache.demand_mshr_miss_latency::total 4912000 # number of demand (read+write) MSHR miss cycles
1689system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4912000 # number of overall MSHR miss cycles
1690system.cpu3.icache.overall_mshr_miss_latency::total 4912000 # number of overall MSHR miss cycles
1691system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for ReadReq accesses
| 1804system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1805system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1806system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1807system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
1808system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1809system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1810system.cpu3.icache.fast_writes 0 # number of fast writes performed
1811system.cpu3.icache.cache_copies 0 # number of cache copies performed
1812system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 71 # number of ReadReq MSHR hits
1813system.cpu3.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits
1814system.cpu3.icache.demand_mshr_hits::cpu3.inst 71 # number of demand (read+write) MSHR hits
1815system.cpu3.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits
1816system.cpu3.icache.overall_mshr_hits::cpu3.inst 71 # number of overall MSHR hits
1817system.cpu3.icache.overall_mshr_hits::total 71 # number of overall MSHR hits
1818system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 432 # number of ReadReq MSHR misses
1819system.cpu3.icache.ReadReq_mshr_misses::total 432 # number of ReadReq MSHR misses
1820system.cpu3.icache.demand_mshr_misses::cpu3.inst 432 # number of demand (read+write) MSHR misses
1821system.cpu3.icache.demand_mshr_misses::total 432 # number of demand (read+write) MSHR misses
1822system.cpu3.icache.overall_mshr_misses::cpu3.inst 432 # number of overall MSHR misses
1823system.cpu3.icache.overall_mshr_misses::total 432 # number of overall MSHR misses
1824system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4912000 # number of ReadReq MSHR miss cycles
1825system.cpu3.icache.ReadReq_mshr_miss_latency::total 4912000 # number of ReadReq MSHR miss cycles
1826system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4912000 # number of demand (read+write) MSHR miss cycles
1827system.cpu3.icache.demand_mshr_miss_latency::total 4912000 # number of demand (read+write) MSHR miss cycles
1828system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4912000 # number of overall MSHR miss cycles
1829system.cpu3.icache.overall_mshr_miss_latency::total 4912000 # number of overall MSHR miss cycles
1830system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for ReadReq accesses
|
| 1831system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.017666 # mshr miss rate for ReadReq accesses
|
1692system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for demand accesses
| 1832system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for demand accesses
|
| 1833system.cpu3.icache.demand_mshr_miss_rate::total 0.017666 # mshr miss rate for demand accesses
|
1693system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for overall accesses
| 1834system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for overall accesses
|
| 1835system.cpu3.icache.overall_mshr_miss_rate::total 0.017666 # mshr miss rate for overall accesses
|
1694system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average ReadReq mshr miss latency
| 1836system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average ReadReq mshr miss latency
|
| 1837system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11370.370370 # average ReadReq mshr miss latency
|
1695system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average overall mshr miss latency
| 1838system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average overall mshr miss latency
|
| 1839system.cpu3.icache.demand_avg_mshr_miss_latency::total 11370.370370 # average overall mshr miss latency
|
1696system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average overall mshr miss latency
| 1840system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average overall mshr miss latency
|
| 1841system.cpu3.icache.overall_avg_mshr_miss_latency::total 11370.370370 # average overall mshr miss latency
|
1697system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1698system.cpu3.dcache.replacements 2 # number of replacements
1699system.cpu3.dcache.tagsinuse 25.290478 # Cycle average of tags in use
1700system.cpu3.dcache.total_refs 37716 # Total number of references to valid blocks.
1701system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks.
1702system.cpu3.dcache.avg_refs 1257.200000 # Average number of references to valid blocks.
1703system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1704system.cpu3.dcache.occ_blocks::cpu3.data 25.290478 # Average occupied blocks per requestor
1705system.cpu3.dcache.occ_percent::cpu3.data 0.049395 # Average percentage of cache occupancy
1706system.cpu3.dcache.occ_percent::total 0.049395 # Average percentage of cache occupancy
1707system.cpu3.dcache.ReadReq_hits::cpu3.data 42933 # number of ReadReq hits
1708system.cpu3.dcache.ReadReq_hits::total 42933 # number of ReadReq hits
1709system.cpu3.dcache.WriteReq_hits::cpu3.data 31189 # number of WriteReq hits
1710system.cpu3.dcache.WriteReq_hits::total 31189 # number of WriteReq hits
1711system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits
1712system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits
1713system.cpu3.dcache.demand_hits::cpu3.data 74122 # number of demand (read+write) hits
1714system.cpu3.dcache.demand_hits::total 74122 # number of demand (read+write) hits
1715system.cpu3.dcache.overall_hits::cpu3.data 74122 # number of overall hits
1716system.cpu3.dcache.overall_hits::total 74122 # number of overall hits
1717system.cpu3.dcache.ReadReq_misses::cpu3.data 420 # number of ReadReq misses
1718system.cpu3.dcache.ReadReq_misses::total 420 # number of ReadReq misses
1719system.cpu3.dcache.WriteReq_misses::cpu3.data 149 # number of WriteReq misses
1720system.cpu3.dcache.WriteReq_misses::total 149 # number of WriteReq misses
1721system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses
1722system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses
1723system.cpu3.dcache.demand_misses::cpu3.data 569 # number of demand (read+write) misses
1724system.cpu3.dcache.demand_misses::total 569 # number of demand (read+write) misses
1725system.cpu3.dcache.overall_misses::cpu3.data 569 # number of overall misses
1726system.cpu3.dcache.overall_misses::total 569 # number of overall misses
1727system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 8616000 # number of ReadReq miss cycles
1728system.cpu3.dcache.ReadReq_miss_latency::total 8616000 # number of ReadReq miss cycles
1729system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3007500 # number of WriteReq miss cycles
1730system.cpu3.dcache.WriteReq_miss_latency::total 3007500 # number of WriteReq miss cycles
1731system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 1198000 # number of SwapReq miss cycles
1732system.cpu3.dcache.SwapReq_miss_latency::total 1198000 # number of SwapReq miss cycles
1733system.cpu3.dcache.demand_miss_latency::cpu3.data 11623500 # number of demand (read+write) miss cycles
1734system.cpu3.dcache.demand_miss_latency::total 11623500 # number of demand (read+write) miss cycles
1735system.cpu3.dcache.overall_miss_latency::cpu3.data 11623500 # number of overall miss cycles
1736system.cpu3.dcache.overall_miss_latency::total 11623500 # number of overall miss cycles
1737system.cpu3.dcache.ReadReq_accesses::cpu3.data 43353 # number of ReadReq accesses(hits+misses)
1738system.cpu3.dcache.ReadReq_accesses::total 43353 # number of ReadReq accesses(hits+misses)
1739system.cpu3.dcache.WriteReq_accesses::cpu3.data 31338 # number of WriteReq accesses(hits+misses)
1740system.cpu3.dcache.WriteReq_accesses::total 31338 # number of WriteReq accesses(hits+misses)
1741system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses)
1742system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
1743system.cpu3.dcache.demand_accesses::cpu3.data 74691 # number of demand (read+write) accesses
1744system.cpu3.dcache.demand_accesses::total 74691 # number of demand (read+write) accesses
1745system.cpu3.dcache.overall_accesses::cpu3.data 74691 # number of overall (read+write) accesses
1746system.cpu3.dcache.overall_accesses::total 74691 # number of overall (read+write) accesses
1747system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009688 # miss rate for ReadReq accesses
| 1842system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1843system.cpu3.dcache.replacements 2 # number of replacements
1844system.cpu3.dcache.tagsinuse 25.290478 # Cycle average of tags in use
1845system.cpu3.dcache.total_refs 37716 # Total number of references to valid blocks.
1846system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks.
1847system.cpu3.dcache.avg_refs 1257.200000 # Average number of references to valid blocks.
1848system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1849system.cpu3.dcache.occ_blocks::cpu3.data 25.290478 # Average occupied blocks per requestor
1850system.cpu3.dcache.occ_percent::cpu3.data 0.049395 # Average percentage of cache occupancy
1851system.cpu3.dcache.occ_percent::total 0.049395 # Average percentage of cache occupancy
1852system.cpu3.dcache.ReadReq_hits::cpu3.data 42933 # number of ReadReq hits
1853system.cpu3.dcache.ReadReq_hits::total 42933 # number of ReadReq hits
1854system.cpu3.dcache.WriteReq_hits::cpu3.data 31189 # number of WriteReq hits
1855system.cpu3.dcache.WriteReq_hits::total 31189 # number of WriteReq hits
1856system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits
1857system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits
1858system.cpu3.dcache.demand_hits::cpu3.data 74122 # number of demand (read+write) hits
1859system.cpu3.dcache.demand_hits::total 74122 # number of demand (read+write) hits
1860system.cpu3.dcache.overall_hits::cpu3.data 74122 # number of overall hits
1861system.cpu3.dcache.overall_hits::total 74122 # number of overall hits
1862system.cpu3.dcache.ReadReq_misses::cpu3.data 420 # number of ReadReq misses
1863system.cpu3.dcache.ReadReq_misses::total 420 # number of ReadReq misses
1864system.cpu3.dcache.WriteReq_misses::cpu3.data 149 # number of WriteReq misses
1865system.cpu3.dcache.WriteReq_misses::total 149 # number of WriteReq misses
1866system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses
1867system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses
1868system.cpu3.dcache.demand_misses::cpu3.data 569 # number of demand (read+write) misses
1869system.cpu3.dcache.demand_misses::total 569 # number of demand (read+write) misses
1870system.cpu3.dcache.overall_misses::cpu3.data 569 # number of overall misses
1871system.cpu3.dcache.overall_misses::total 569 # number of overall misses
1872system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 8616000 # number of ReadReq miss cycles
1873system.cpu3.dcache.ReadReq_miss_latency::total 8616000 # number of ReadReq miss cycles
1874system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3007500 # number of WriteReq miss cycles
1875system.cpu3.dcache.WriteReq_miss_latency::total 3007500 # number of WriteReq miss cycles
1876system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 1198000 # number of SwapReq miss cycles
1877system.cpu3.dcache.SwapReq_miss_latency::total 1198000 # number of SwapReq miss cycles
1878system.cpu3.dcache.demand_miss_latency::cpu3.data 11623500 # number of demand (read+write) miss cycles
1879system.cpu3.dcache.demand_miss_latency::total 11623500 # number of demand (read+write) miss cycles
1880system.cpu3.dcache.overall_miss_latency::cpu3.data 11623500 # number of overall miss cycles
1881system.cpu3.dcache.overall_miss_latency::total 11623500 # number of overall miss cycles
1882system.cpu3.dcache.ReadReq_accesses::cpu3.data 43353 # number of ReadReq accesses(hits+misses)
1883system.cpu3.dcache.ReadReq_accesses::total 43353 # number of ReadReq accesses(hits+misses)
1884system.cpu3.dcache.WriteReq_accesses::cpu3.data 31338 # number of WriteReq accesses(hits+misses)
1885system.cpu3.dcache.WriteReq_accesses::total 31338 # number of WriteReq accesses(hits+misses)
1886system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses)
1887system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
1888system.cpu3.dcache.demand_accesses::cpu3.data 74691 # number of demand (read+write) accesses
1889system.cpu3.dcache.demand_accesses::total 74691 # number of demand (read+write) accesses
1890system.cpu3.dcache.overall_accesses::cpu3.data 74691 # number of overall (read+write) accesses
1891system.cpu3.dcache.overall_accesses::total 74691 # number of overall (read+write) accesses
1892system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009688 # miss rate for ReadReq accesses
|
| 1893system.cpu3.dcache.ReadReq_miss_rate::total 0.009688 # miss rate for ReadReq accesses
|
1748system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004755 # miss rate for WriteReq accesses
| 1894system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004755 # miss rate for WriteReq accesses
|
| 1895system.cpu3.dcache.WriteReq_miss_rate::total 0.004755 # miss rate for WriteReq accesses
|
1749system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses
| 1896system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses
|
| 1897system.cpu3.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses
|
1750system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007618 # miss rate for demand accesses
| 1898system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007618 # miss rate for demand accesses
|
| 1899system.cpu3.dcache.demand_miss_rate::total 0.007618 # miss rate for demand accesses
|
1751system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007618 # miss rate for overall accesses
| 1900system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007618 # miss rate for overall accesses
|
| 1901system.cpu3.dcache.overall_miss_rate::total 0.007618 # miss rate for overall accesses
|
1752system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 20514.285714 # average ReadReq miss latency
| 1902system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 20514.285714 # average ReadReq miss latency
|
| 1903system.cpu3.dcache.ReadReq_avg_miss_latency::total 20514.285714 # average ReadReq miss latency
|
1753system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20184.563758 # average WriteReq miss latency
| 1904system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20184.563758 # average WriteReq miss latency
|
| 1905system.cpu3.dcache.WriteReq_avg_miss_latency::total 20184.563758 # average WriteReq miss latency
|
1754system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 21017.543860 # average SwapReq miss latency
| 1906system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 21017.543860 # average SwapReq miss latency
|
| 1907system.cpu3.dcache.SwapReq_avg_miss_latency::total 21017.543860 # average SwapReq miss latency
|
1755system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 20427.943761 # average overall miss latency
| 1908system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 20427.943761 # average overall miss latency
|
| 1909system.cpu3.dcache.demand_avg_miss_latency::total 20427.943761 # average overall miss latency
|
1756system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 20427.943761 # average overall miss latency
| 1910system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 20427.943761 # average overall miss latency
|
| 1911system.cpu3.dcache.overall_avg_miss_latency::total 20427.943761 # average overall miss latency
|
1757system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1758system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1759system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1760system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
1761system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1762system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1763system.cpu3.dcache.fast_writes 0 # number of fast writes performed
1764system.cpu3.dcache.cache_copies 0 # number of cache copies performed
1765system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks
1766system.cpu3.dcache.writebacks::total 1 # number of writebacks
1767system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 257 # number of ReadReq MSHR hits
1768system.cpu3.dcache.ReadReq_mshr_hits::total 257 # number of ReadReq MSHR hits
1769system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 45 # number of WriteReq MSHR hits
1770system.cpu3.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits
1771system.cpu3.dcache.demand_mshr_hits::cpu3.data 302 # number of demand (read+write) MSHR hits
1772system.cpu3.dcache.demand_mshr_hits::total 302 # number of demand (read+write) MSHR hits
1773system.cpu3.dcache.overall_mshr_hits::cpu3.data 302 # number of overall MSHR hits
1774system.cpu3.dcache.overall_mshr_hits::total 302 # number of overall MSHR hits
1775system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses
1776system.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses
1777system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 104 # number of WriteReq MSHR misses
1778system.cpu3.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses
1779system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses
1780system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses
1781system.cpu3.dcache.demand_mshr_misses::cpu3.data 267 # number of demand (read+write) MSHR misses
1782system.cpu3.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses
1783system.cpu3.dcache.overall_mshr_misses::cpu3.data 267 # number of overall MSHR misses
1784system.cpu3.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses
1785system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2151000 # number of ReadReq MSHR miss cycles
1786system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2151000 # number of ReadReq MSHR miss cycles
1787system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1621000 # number of WriteReq MSHR miss cycles
1788system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1621000 # number of WriteReq MSHR miss cycles
1789system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 1027000 # number of SwapReq MSHR miss cycles
1790system.cpu3.dcache.SwapReq_mshr_miss_latency::total 1027000 # number of SwapReq MSHR miss cycles
1791system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3772000 # number of demand (read+write) MSHR miss cycles
1792system.cpu3.dcache.demand_mshr_miss_latency::total 3772000 # number of demand (read+write) MSHR miss cycles
1793system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3772000 # number of overall MSHR miss cycles
1794system.cpu3.dcache.overall_mshr_miss_latency::total 3772000 # number of overall MSHR miss cycles
1795system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003760 # mshr miss rate for ReadReq accesses
| 1912system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1913system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1914system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1915system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
1916system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1917system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1918system.cpu3.dcache.fast_writes 0 # number of fast writes performed
1919system.cpu3.dcache.cache_copies 0 # number of cache copies performed
1920system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks
1921system.cpu3.dcache.writebacks::total 1 # number of writebacks
1922system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 257 # number of ReadReq MSHR hits
1923system.cpu3.dcache.ReadReq_mshr_hits::total 257 # number of ReadReq MSHR hits
1924system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 45 # number of WriteReq MSHR hits
1925system.cpu3.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits
1926system.cpu3.dcache.demand_mshr_hits::cpu3.data 302 # number of demand (read+write) MSHR hits
1927system.cpu3.dcache.demand_mshr_hits::total 302 # number of demand (read+write) MSHR hits
1928system.cpu3.dcache.overall_mshr_hits::cpu3.data 302 # number of overall MSHR hits
1929system.cpu3.dcache.overall_mshr_hits::total 302 # number of overall MSHR hits
1930system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses
1931system.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses
1932system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 104 # number of WriteReq MSHR misses
1933system.cpu3.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses
1934system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses
1935system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses
1936system.cpu3.dcache.demand_mshr_misses::cpu3.data 267 # number of demand (read+write) MSHR misses
1937system.cpu3.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses
1938system.cpu3.dcache.overall_mshr_misses::cpu3.data 267 # number of overall MSHR misses
1939system.cpu3.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses
1940system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2151000 # number of ReadReq MSHR miss cycles
1941system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2151000 # number of ReadReq MSHR miss cycles
1942system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1621000 # number of WriteReq MSHR miss cycles
1943system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1621000 # number of WriteReq MSHR miss cycles
1944system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 1027000 # number of SwapReq MSHR miss cycles
1945system.cpu3.dcache.SwapReq_mshr_miss_latency::total 1027000 # number of SwapReq MSHR miss cycles
1946system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3772000 # number of demand (read+write) MSHR miss cycles
1947system.cpu3.dcache.demand_mshr_miss_latency::total 3772000 # number of demand (read+write) MSHR miss cycles
1948system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3772000 # number of overall MSHR miss cycles
1949system.cpu3.dcache.overall_mshr_miss_latency::total 3772000 # number of overall MSHR miss cycles
1950system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003760 # mshr miss rate for ReadReq accesses
|
| 1951system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003760 # mshr miss rate for ReadReq accesses
|
1796system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003319 # mshr miss rate for WriteReq accesses
| 1952system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003319 # mshr miss rate for WriteReq accesses
|
| 1953system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003319 # mshr miss rate for WriteReq accesses
|
1797system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses
| 1954system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses
|
| 1955system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses
|
1798system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003575 # mshr miss rate for demand accesses
| 1956system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003575 # mshr miss rate for demand accesses
|
| 1957system.cpu3.dcache.demand_mshr_miss_rate::total 0.003575 # mshr miss rate for demand accesses
|
1799system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003575 # mshr miss rate for overall accesses
| 1958system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003575 # mshr miss rate for overall accesses
|
| 1959system.cpu3.dcache.overall_mshr_miss_rate::total 0.003575 # mshr miss rate for overall accesses
|
1800system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13196.319018 # average ReadReq mshr miss latency
| 1960system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13196.319018 # average ReadReq mshr miss latency
|
| 1961system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 13196.319018 # average ReadReq mshr miss latency
|
1801system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15586.538462 # average WriteReq mshr miss latency
| 1962system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15586.538462 # average WriteReq mshr miss latency
|
| 1963system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15586.538462 # average WriteReq mshr miss latency
|
1802system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 18017.543860 # average SwapReq mshr miss latency
| 1964system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 18017.543860 # average SwapReq mshr miss latency
|
| 1965system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 18017.543860 # average SwapReq mshr miss latency
|
1803system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14127.340824 # average overall mshr miss latency
| 1966system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14127.340824 # average overall mshr miss latency
|
| 1967system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14127.340824 # average overall mshr miss latency
|
1804system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14127.340824 # average overall mshr miss latency
| 1968system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14127.340824 # average overall mshr miss latency
|
| 1969system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14127.340824 # average overall mshr miss latency
|
1805system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1806system.l2c.replacements 0 # number of replacements
1807system.l2c.tagsinuse 441.136869 # Cycle average of tags in use
1808system.l2c.total_refs 1471 # Total number of references to valid blocks.
1809system.l2c.sampled_refs 544 # Sample count of references to valid blocks.
1810system.l2c.avg_refs 2.704044 # Average number of references to valid blocks.
1811system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1812system.l2c.occ_blocks::writebacks 4.878414 # Average occupied blocks per requestor
1813system.l2c.occ_blocks::cpu0.inst 294.783080 # Average occupied blocks per requestor
1814system.l2c.occ_blocks::cpu0.data 59.595754 # Average occupied blocks per requestor
1815system.l2c.occ_blocks::cpu1.inst 9.493651 # Average occupied blocks per requestor
1816system.l2c.occ_blocks::cpu1.data 0.732946 # Average occupied blocks per requestor
1817system.l2c.occ_blocks::cpu2.inst 64.319288 # Average occupied blocks per requestor
1818system.l2c.occ_blocks::cpu2.data 5.723296 # Average occupied blocks per requestor
1819system.l2c.occ_blocks::cpu3.inst 0.834559 # Average occupied blocks per requestor
1820system.l2c.occ_blocks::cpu3.data 0.775880 # Average occupied blocks per requestor
1821system.l2c.occ_percent::writebacks 0.000074 # Average percentage of cache occupancy
1822system.l2c.occ_percent::cpu0.inst 0.004498 # Average percentage of cache occupancy
1823system.l2c.occ_percent::cpu0.data 0.000909 # Average percentage of cache occupancy
1824system.l2c.occ_percent::cpu1.inst 0.000145 # Average percentage of cache occupancy
1825system.l2c.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy
1826system.l2c.occ_percent::cpu2.inst 0.000981 # Average percentage of cache occupancy
1827system.l2c.occ_percent::cpu2.data 0.000087 # Average percentage of cache occupancy
1828system.l2c.occ_percent::cpu3.inst 0.000013 # Average percentage of cache occupancy
1829system.l2c.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy
1830system.l2c.occ_percent::total 0.006731 # Average percentage of cache occupancy
1831system.l2c.ReadReq_hits::cpu0.inst 231 # number of ReadReq hits
1832system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
1833system.l2c.ReadReq_hits::cpu1.inst 420 # number of ReadReq hits
1834system.l2c.ReadReq_hits::cpu1.data 13 # number of ReadReq hits
1835system.l2c.ReadReq_hits::cpu2.inst 355 # number of ReadReq hits
1836system.l2c.ReadReq_hits::cpu2.data 7 # number of ReadReq hits
1837system.l2c.ReadReq_hits::cpu3.inst 430 # number of ReadReq hits
1838system.l2c.ReadReq_hits::cpu3.data 13 # number of ReadReq hits
1839system.l2c.ReadReq_hits::total 1474 # number of ReadReq hits
1840system.l2c.Writeback_hits::writebacks 9 # number of Writeback hits
1841system.l2c.Writeback_hits::total 9 # number of Writeback hits
1842system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
1843system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits
1844system.l2c.demand_hits::cpu0.inst 231 # number of demand (read+write) hits
1845system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
1846system.l2c.demand_hits::cpu1.inst 420 # number of demand (read+write) hits
1847system.l2c.demand_hits::cpu1.data 13 # number of demand (read+write) hits
1848system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits
1849system.l2c.demand_hits::cpu2.data 7 # number of demand (read+write) hits
1850system.l2c.demand_hits::cpu3.inst 430 # number of demand (read+write) hits
1851system.l2c.demand_hits::cpu3.data 13 # number of demand (read+write) hits
1852system.l2c.demand_hits::total 1474 # number of demand (read+write) hits
1853system.l2c.overall_hits::cpu0.inst 231 # number of overall hits
1854system.l2c.overall_hits::cpu0.data 5 # number of overall hits
1855system.l2c.overall_hits::cpu1.inst 420 # number of overall hits
1856system.l2c.overall_hits::cpu1.data 13 # number of overall hits
1857system.l2c.overall_hits::cpu2.inst 355 # number of overall hits
1858system.l2c.overall_hits::cpu2.data 7 # number of overall hits
1859system.l2c.overall_hits::cpu3.inst 430 # number of overall hits
1860system.l2c.overall_hits::cpu3.data 13 # number of overall hits
1861system.l2c.overall_hits::total 1474 # number of overall hits
1862system.l2c.ReadReq_misses::cpu0.inst 363 # number of ReadReq misses
1863system.l2c.ReadReq_misses::cpu0.data 75 # number of ReadReq misses
1864system.l2c.ReadReq_misses::cpu1.inst 15 # number of ReadReq misses
1865system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses
1866system.l2c.ReadReq_misses::cpu2.inst 85 # number of ReadReq misses
1867system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses
1868system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses
1869system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses
1870system.l2c.ReadReq_misses::total 549 # number of ReadReq misses
1871system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses
1872system.l2c.UpgradeReq_misses::cpu1.data 21 # number of UpgradeReq misses
1873system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses
1874system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses
1875system.l2c.UpgradeReq_misses::total 80 # number of UpgradeReq misses
1876system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses
1877system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses
1878system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses
1879system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
1880system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses
1881system.l2c.demand_misses::cpu0.inst 363 # number of demand (read+write) misses
1882system.l2c.demand_misses::cpu0.data 169 # number of demand (read+write) misses
1883system.l2c.demand_misses::cpu1.inst 15 # number of demand (read+write) misses
1884system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses
1885system.l2c.demand_misses::cpu2.inst 85 # number of demand (read+write) misses
1886system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses
1887system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses
1888system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
1889system.l2c.demand_misses::total 680 # number of demand (read+write) misses
1890system.l2c.overall_misses::cpu0.inst 363 # number of overall misses
1891system.l2c.overall_misses::cpu0.data 169 # number of overall misses
1892system.l2c.overall_misses::cpu1.inst 15 # number of overall misses
1893system.l2c.overall_misses::cpu1.data 13 # number of overall misses
1894system.l2c.overall_misses::cpu2.inst 85 # number of overall misses
1895system.l2c.overall_misses::cpu2.data 20 # number of overall misses
1896system.l2c.overall_misses::cpu3.inst 2 # number of overall misses
1897system.l2c.overall_misses::cpu3.data 13 # number of overall misses
1898system.l2c.overall_misses::total 680 # number of overall misses
1899system.l2c.ReadReq_miss_latency::cpu0.inst 18919500 # number of ReadReq miss cycles
1900system.l2c.ReadReq_miss_latency::cpu0.data 3929500 # number of ReadReq miss cycles
1901system.l2c.ReadReq_miss_latency::cpu1.inst 744500 # number of ReadReq miss cycles
1902system.l2c.ReadReq_miss_latency::cpu1.data 52500 # number of ReadReq miss cycles
1903system.l2c.ReadReq_miss_latency::cpu2.inst 4376000 # number of ReadReq miss cycles
1904system.l2c.ReadReq_miss_latency::cpu2.data 366000 # number of ReadReq miss cycles
1905system.l2c.ReadReq_miss_latency::cpu3.inst 99500 # number of ReadReq miss cycles
1906system.l2c.ReadReq_miss_latency::cpu3.data 52500 # number of ReadReq miss cycles
1907system.l2c.ReadReq_miss_latency::total 28540000 # number of ReadReq miss cycles
1908system.l2c.UpgradeReq_miss_latency::cpu1.data 52500 # number of UpgradeReq miss cycles
1909system.l2c.UpgradeReq_miss_latency::cpu2.data 52500 # number of UpgradeReq miss cycles
1910system.l2c.UpgradeReq_miss_latency::cpu3.data 52500 # number of UpgradeReq miss cycles
1911system.l2c.UpgradeReq_miss_latency::total 157500 # number of UpgradeReq miss cycles
1912system.l2c.ReadExReq_miss_latency::cpu0.data 4939500 # number of ReadExReq miss cycles
1913system.l2c.ReadExReq_miss_latency::cpu1.data 627500 # number of ReadExReq miss cycles
1914system.l2c.ReadExReq_miss_latency::cpu2.data 680500 # number of ReadExReq miss cycles
1915system.l2c.ReadExReq_miss_latency::cpu3.data 627500 # number of ReadExReq miss cycles
1916system.l2c.ReadExReq_miss_latency::total 6875000 # number of ReadExReq miss cycles
1917system.l2c.demand_miss_latency::cpu0.inst 18919500 # number of demand (read+write) miss cycles
1918system.l2c.demand_miss_latency::cpu0.data 8869000 # number of demand (read+write) miss cycles
1919system.l2c.demand_miss_latency::cpu1.inst 744500 # number of demand (read+write) miss cycles
1920system.l2c.demand_miss_latency::cpu1.data 680000 # number of demand (read+write) miss cycles
1921system.l2c.demand_miss_latency::cpu2.inst 4376000 # number of demand (read+write) miss cycles
1922system.l2c.demand_miss_latency::cpu2.data 1046500 # number of demand (read+write) miss cycles
1923system.l2c.demand_miss_latency::cpu3.inst 99500 # number of demand (read+write) miss cycles
1924system.l2c.demand_miss_latency::cpu3.data 680000 # number of demand (read+write) miss cycles
1925system.l2c.demand_miss_latency::total 35415000 # number of demand (read+write) miss cycles
1926system.l2c.overall_miss_latency::cpu0.inst 18919500 # number of overall miss cycles
1927system.l2c.overall_miss_latency::cpu0.data 8869000 # number of overall miss cycles
1928system.l2c.overall_miss_latency::cpu1.inst 744500 # number of overall miss cycles
1929system.l2c.overall_miss_latency::cpu1.data 680000 # number of overall miss cycles
1930system.l2c.overall_miss_latency::cpu2.inst 4376000 # number of overall miss cycles
1931system.l2c.overall_miss_latency::cpu2.data 1046500 # number of overall miss cycles
1932system.l2c.overall_miss_latency::cpu3.inst 99500 # number of overall miss cycles
1933system.l2c.overall_miss_latency::cpu3.data 680000 # number of overall miss cycles
1934system.l2c.overall_miss_latency::total 35415000 # number of overall miss cycles
1935system.l2c.ReadReq_accesses::cpu0.inst 594 # number of ReadReq accesses(hits+misses)
1936system.l2c.ReadReq_accesses::cpu0.data 80 # number of ReadReq accesses(hits+misses)
1937system.l2c.ReadReq_accesses::cpu1.inst 435 # number of ReadReq accesses(hits+misses)
1938system.l2c.ReadReq_accesses::cpu1.data 14 # number of ReadReq accesses(hits+misses)
1939system.l2c.ReadReq_accesses::cpu2.inst 440 # number of ReadReq accesses(hits+misses)
1940system.l2c.ReadReq_accesses::cpu2.data 14 # number of ReadReq accesses(hits+misses)
1941system.l2c.ReadReq_accesses::cpu3.inst 432 # number of ReadReq accesses(hits+misses)
1942system.l2c.ReadReq_accesses::cpu3.data 14 # number of ReadReq accesses(hits+misses)
1943system.l2c.ReadReq_accesses::total 2023 # number of ReadReq accesses(hits+misses)
1944system.l2c.Writeback_accesses::writebacks 9 # number of Writeback accesses(hits+misses)
1945system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses)
1946system.l2c.UpgradeReq_accesses::cpu0.data 25 # number of UpgradeReq accesses(hits+misses)
1947system.l2c.UpgradeReq_accesses::cpu1.data 21 # number of UpgradeReq accesses(hits+misses)
1948system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses)
1949system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses)
1950system.l2c.UpgradeReq_accesses::total 83 # number of UpgradeReq accesses(hits+misses)
1951system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses)
1952system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses)
1953system.l2c.ReadExReq_accesses::cpu2.data 13 # number of ReadExReq accesses(hits+misses)
1954system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
1955system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)
1956system.l2c.demand_accesses::cpu0.inst 594 # number of demand (read+write) accesses
1957system.l2c.demand_accesses::cpu0.data 174 # number of demand (read+write) accesses
1958system.l2c.demand_accesses::cpu1.inst 435 # number of demand (read+write) accesses
1959system.l2c.demand_accesses::cpu1.data 26 # number of demand (read+write) accesses
1960system.l2c.demand_accesses::cpu2.inst 440 # number of demand (read+write) accesses
1961system.l2c.demand_accesses::cpu2.data 27 # number of demand (read+write) accesses
1962system.l2c.demand_accesses::cpu3.inst 432 # number of demand (read+write) accesses
1963system.l2c.demand_accesses::cpu3.data 26 # number of demand (read+write) accesses
1964system.l2c.demand_accesses::total 2154 # number of demand (read+write) accesses
1965system.l2c.overall_accesses::cpu0.inst 594 # number of overall (read+write) accesses
1966system.l2c.overall_accesses::cpu0.data 174 # number of overall (read+write) accesses
1967system.l2c.overall_accesses::cpu1.inst 435 # number of overall (read+write) accesses
1968system.l2c.overall_accesses::cpu1.data 26 # number of overall (read+write) accesses
1969system.l2c.overall_accesses::cpu2.inst 440 # number of overall (read+write) accesses
1970system.l2c.overall_accesses::cpu2.data 27 # number of overall (read+write) accesses
1971system.l2c.overall_accesses::cpu3.inst 432 # number of overall (read+write) accesses
1972system.l2c.overall_accesses::cpu3.data 26 # number of overall (read+write) accesses
1973system.l2c.overall_accesses::total 2154 # number of overall (read+write) accesses
1974system.l2c.ReadReq_miss_rate::cpu0.inst 0.611111 # miss rate for ReadReq accesses
1975system.l2c.ReadReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadReq accesses
1976system.l2c.ReadReq_miss_rate::cpu1.inst 0.034483 # miss rate for ReadReq accesses
1977system.l2c.ReadReq_miss_rate::cpu1.data 0.071429 # miss rate for ReadReq accesses
1978system.l2c.ReadReq_miss_rate::cpu2.inst 0.193182 # miss rate for ReadReq accesses
1979system.l2c.ReadReq_miss_rate::cpu2.data 0.500000 # miss rate for ReadReq accesses
1980system.l2c.ReadReq_miss_rate::cpu3.inst 0.004630 # miss rate for ReadReq accesses
1981system.l2c.ReadReq_miss_rate::cpu3.data 0.071429 # miss rate for ReadReq accesses
| 1970system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1971system.l2c.replacements 0 # number of replacements
1972system.l2c.tagsinuse 441.136869 # Cycle average of tags in use
1973system.l2c.total_refs 1471 # Total number of references to valid blocks.
1974system.l2c.sampled_refs 544 # Sample count of references to valid blocks.
1975system.l2c.avg_refs 2.704044 # Average number of references to valid blocks.
1976system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1977system.l2c.occ_blocks::writebacks 4.878414 # Average occupied blocks per requestor
1978system.l2c.occ_blocks::cpu0.inst 294.783080 # Average occupied blocks per requestor
1979system.l2c.occ_blocks::cpu0.data 59.595754 # Average occupied blocks per requestor
1980system.l2c.occ_blocks::cpu1.inst 9.493651 # Average occupied blocks per requestor
1981system.l2c.occ_blocks::cpu1.data 0.732946 # Average occupied blocks per requestor
1982system.l2c.occ_blocks::cpu2.inst 64.319288 # Average occupied blocks per requestor
1983system.l2c.occ_blocks::cpu2.data 5.723296 # Average occupied blocks per requestor
1984system.l2c.occ_blocks::cpu3.inst 0.834559 # Average occupied blocks per requestor
1985system.l2c.occ_blocks::cpu3.data 0.775880 # Average occupied blocks per requestor
1986system.l2c.occ_percent::writebacks 0.000074 # Average percentage of cache occupancy
1987system.l2c.occ_percent::cpu0.inst 0.004498 # Average percentage of cache occupancy
1988system.l2c.occ_percent::cpu0.data 0.000909 # Average percentage of cache occupancy
1989system.l2c.occ_percent::cpu1.inst 0.000145 # Average percentage of cache occupancy
1990system.l2c.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy
1991system.l2c.occ_percent::cpu2.inst 0.000981 # Average percentage of cache occupancy
1992system.l2c.occ_percent::cpu2.data 0.000087 # Average percentage of cache occupancy
1993system.l2c.occ_percent::cpu3.inst 0.000013 # Average percentage of cache occupancy
1994system.l2c.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy
1995system.l2c.occ_percent::total 0.006731 # Average percentage of cache occupancy
1996system.l2c.ReadReq_hits::cpu0.inst 231 # number of ReadReq hits
1997system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
1998system.l2c.ReadReq_hits::cpu1.inst 420 # number of ReadReq hits
1999system.l2c.ReadReq_hits::cpu1.data 13 # number of ReadReq hits
2000system.l2c.ReadReq_hits::cpu2.inst 355 # number of ReadReq hits
2001system.l2c.ReadReq_hits::cpu2.data 7 # number of ReadReq hits
2002system.l2c.ReadReq_hits::cpu3.inst 430 # number of ReadReq hits
2003system.l2c.ReadReq_hits::cpu3.data 13 # number of ReadReq hits
2004system.l2c.ReadReq_hits::total 1474 # number of ReadReq hits
2005system.l2c.Writeback_hits::writebacks 9 # number of Writeback hits
2006system.l2c.Writeback_hits::total 9 # number of Writeback hits
2007system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
2008system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits
2009system.l2c.demand_hits::cpu0.inst 231 # number of demand (read+write) hits
2010system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
2011system.l2c.demand_hits::cpu1.inst 420 # number of demand (read+write) hits
2012system.l2c.demand_hits::cpu1.data 13 # number of demand (read+write) hits
2013system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits
2014system.l2c.demand_hits::cpu2.data 7 # number of demand (read+write) hits
2015system.l2c.demand_hits::cpu3.inst 430 # number of demand (read+write) hits
2016system.l2c.demand_hits::cpu3.data 13 # number of demand (read+write) hits
2017system.l2c.demand_hits::total 1474 # number of demand (read+write) hits
2018system.l2c.overall_hits::cpu0.inst 231 # number of overall hits
2019system.l2c.overall_hits::cpu0.data 5 # number of overall hits
2020system.l2c.overall_hits::cpu1.inst 420 # number of overall hits
2021system.l2c.overall_hits::cpu1.data 13 # number of overall hits
2022system.l2c.overall_hits::cpu2.inst 355 # number of overall hits
2023system.l2c.overall_hits::cpu2.data 7 # number of overall hits
2024system.l2c.overall_hits::cpu3.inst 430 # number of overall hits
2025system.l2c.overall_hits::cpu3.data 13 # number of overall hits
2026system.l2c.overall_hits::total 1474 # number of overall hits
2027system.l2c.ReadReq_misses::cpu0.inst 363 # number of ReadReq misses
2028system.l2c.ReadReq_misses::cpu0.data 75 # number of ReadReq misses
2029system.l2c.ReadReq_misses::cpu1.inst 15 # number of ReadReq misses
2030system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses
2031system.l2c.ReadReq_misses::cpu2.inst 85 # number of ReadReq misses
2032system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses
2033system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses
2034system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses
2035system.l2c.ReadReq_misses::total 549 # number of ReadReq misses
2036system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses
2037system.l2c.UpgradeReq_misses::cpu1.data 21 # number of UpgradeReq misses
2038system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses
2039system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses
2040system.l2c.UpgradeReq_misses::total 80 # number of UpgradeReq misses
2041system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses
2042system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses
2043system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses
2044system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
2045system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses
2046system.l2c.demand_misses::cpu0.inst 363 # number of demand (read+write) misses
2047system.l2c.demand_misses::cpu0.data 169 # number of demand (read+write) misses
2048system.l2c.demand_misses::cpu1.inst 15 # number of demand (read+write) misses
2049system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses
2050system.l2c.demand_misses::cpu2.inst 85 # number of demand (read+write) misses
2051system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses
2052system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses
2053system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
2054system.l2c.demand_misses::total 680 # number of demand (read+write) misses
2055system.l2c.overall_misses::cpu0.inst 363 # number of overall misses
2056system.l2c.overall_misses::cpu0.data 169 # number of overall misses
2057system.l2c.overall_misses::cpu1.inst 15 # number of overall misses
2058system.l2c.overall_misses::cpu1.data 13 # number of overall misses
2059system.l2c.overall_misses::cpu2.inst 85 # number of overall misses
2060system.l2c.overall_misses::cpu2.data 20 # number of overall misses
2061system.l2c.overall_misses::cpu3.inst 2 # number of overall misses
2062system.l2c.overall_misses::cpu3.data 13 # number of overall misses
2063system.l2c.overall_misses::total 680 # number of overall misses
2064system.l2c.ReadReq_miss_latency::cpu0.inst 18919500 # number of ReadReq miss cycles
2065system.l2c.ReadReq_miss_latency::cpu0.data 3929500 # number of ReadReq miss cycles
2066system.l2c.ReadReq_miss_latency::cpu1.inst 744500 # number of ReadReq miss cycles
2067system.l2c.ReadReq_miss_latency::cpu1.data 52500 # number of ReadReq miss cycles
2068system.l2c.ReadReq_miss_latency::cpu2.inst 4376000 # number of ReadReq miss cycles
2069system.l2c.ReadReq_miss_latency::cpu2.data 366000 # number of ReadReq miss cycles
2070system.l2c.ReadReq_miss_latency::cpu3.inst 99500 # number of ReadReq miss cycles
2071system.l2c.ReadReq_miss_latency::cpu3.data 52500 # number of ReadReq miss cycles
2072system.l2c.ReadReq_miss_latency::total 28540000 # number of ReadReq miss cycles
2073system.l2c.UpgradeReq_miss_latency::cpu1.data 52500 # number of UpgradeReq miss cycles
2074system.l2c.UpgradeReq_miss_latency::cpu2.data 52500 # number of UpgradeReq miss cycles
2075system.l2c.UpgradeReq_miss_latency::cpu3.data 52500 # number of UpgradeReq miss cycles
2076system.l2c.UpgradeReq_miss_latency::total 157500 # number of UpgradeReq miss cycles
2077system.l2c.ReadExReq_miss_latency::cpu0.data 4939500 # number of ReadExReq miss cycles
2078system.l2c.ReadExReq_miss_latency::cpu1.data 627500 # number of ReadExReq miss cycles
2079system.l2c.ReadExReq_miss_latency::cpu2.data 680500 # number of ReadExReq miss cycles
2080system.l2c.ReadExReq_miss_latency::cpu3.data 627500 # number of ReadExReq miss cycles
2081system.l2c.ReadExReq_miss_latency::total 6875000 # number of ReadExReq miss cycles
2082system.l2c.demand_miss_latency::cpu0.inst 18919500 # number of demand (read+write) miss cycles
2083system.l2c.demand_miss_latency::cpu0.data 8869000 # number of demand (read+write) miss cycles
2084system.l2c.demand_miss_latency::cpu1.inst 744500 # number of demand (read+write) miss cycles
2085system.l2c.demand_miss_latency::cpu1.data 680000 # number of demand (read+write) miss cycles
2086system.l2c.demand_miss_latency::cpu2.inst 4376000 # number of demand (read+write) miss cycles
2087system.l2c.demand_miss_latency::cpu2.data 1046500 # number of demand (read+write) miss cycles
2088system.l2c.demand_miss_latency::cpu3.inst 99500 # number of demand (read+write) miss cycles
2089system.l2c.demand_miss_latency::cpu3.data 680000 # number of demand (read+write) miss cycles
2090system.l2c.demand_miss_latency::total 35415000 # number of demand (read+write) miss cycles
2091system.l2c.overall_miss_latency::cpu0.inst 18919500 # number of overall miss cycles
2092system.l2c.overall_miss_latency::cpu0.data 8869000 # number of overall miss cycles
2093system.l2c.overall_miss_latency::cpu1.inst 744500 # number of overall miss cycles
2094system.l2c.overall_miss_latency::cpu1.data 680000 # number of overall miss cycles
2095system.l2c.overall_miss_latency::cpu2.inst 4376000 # number of overall miss cycles
2096system.l2c.overall_miss_latency::cpu2.data 1046500 # number of overall miss cycles
2097system.l2c.overall_miss_latency::cpu3.inst 99500 # number of overall miss cycles
2098system.l2c.overall_miss_latency::cpu3.data 680000 # number of overall miss cycles
2099system.l2c.overall_miss_latency::total 35415000 # number of overall miss cycles
2100system.l2c.ReadReq_accesses::cpu0.inst 594 # number of ReadReq accesses(hits+misses)
2101system.l2c.ReadReq_accesses::cpu0.data 80 # number of ReadReq accesses(hits+misses)
2102system.l2c.ReadReq_accesses::cpu1.inst 435 # number of ReadReq accesses(hits+misses)
2103system.l2c.ReadReq_accesses::cpu1.data 14 # number of ReadReq accesses(hits+misses)
2104system.l2c.ReadReq_accesses::cpu2.inst 440 # number of ReadReq accesses(hits+misses)
2105system.l2c.ReadReq_accesses::cpu2.data 14 # number of ReadReq accesses(hits+misses)
2106system.l2c.ReadReq_accesses::cpu3.inst 432 # number of ReadReq accesses(hits+misses)
2107system.l2c.ReadReq_accesses::cpu3.data 14 # number of ReadReq accesses(hits+misses)
2108system.l2c.ReadReq_accesses::total 2023 # number of ReadReq accesses(hits+misses)
2109system.l2c.Writeback_accesses::writebacks 9 # number of Writeback accesses(hits+misses)
2110system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses)
2111system.l2c.UpgradeReq_accesses::cpu0.data 25 # number of UpgradeReq accesses(hits+misses)
2112system.l2c.UpgradeReq_accesses::cpu1.data 21 # number of UpgradeReq accesses(hits+misses)
2113system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses)
2114system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses)
2115system.l2c.UpgradeReq_accesses::total 83 # number of UpgradeReq accesses(hits+misses)
2116system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses)
2117system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses)
2118system.l2c.ReadExReq_accesses::cpu2.data 13 # number of ReadExReq accesses(hits+misses)
2119system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
2120system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)
2121system.l2c.demand_accesses::cpu0.inst 594 # number of demand (read+write) accesses
2122system.l2c.demand_accesses::cpu0.data 174 # number of demand (read+write) accesses
2123system.l2c.demand_accesses::cpu1.inst 435 # number of demand (read+write) accesses
2124system.l2c.demand_accesses::cpu1.data 26 # number of demand (read+write) accesses
2125system.l2c.demand_accesses::cpu2.inst 440 # number of demand (read+write) accesses
2126system.l2c.demand_accesses::cpu2.data 27 # number of demand (read+write) accesses
2127system.l2c.demand_accesses::cpu3.inst 432 # number of demand (read+write) accesses
2128system.l2c.demand_accesses::cpu3.data 26 # number of demand (read+write) accesses
2129system.l2c.demand_accesses::total 2154 # number of demand (read+write) accesses
2130system.l2c.overall_accesses::cpu0.inst 594 # number of overall (read+write) accesses
2131system.l2c.overall_accesses::cpu0.data 174 # number of overall (read+write) accesses
2132system.l2c.overall_accesses::cpu1.inst 435 # number of overall (read+write) accesses
2133system.l2c.overall_accesses::cpu1.data 26 # number of overall (read+write) accesses
2134system.l2c.overall_accesses::cpu2.inst 440 # number of overall (read+write) accesses
2135system.l2c.overall_accesses::cpu2.data 27 # number of overall (read+write) accesses
2136system.l2c.overall_accesses::cpu3.inst 432 # number of overall (read+write) accesses
2137system.l2c.overall_accesses::cpu3.data 26 # number of overall (read+write) accesses
2138system.l2c.overall_accesses::total 2154 # number of overall (read+write) accesses
2139system.l2c.ReadReq_miss_rate::cpu0.inst 0.611111 # miss rate for ReadReq accesses
2140system.l2c.ReadReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadReq accesses
2141system.l2c.ReadReq_miss_rate::cpu1.inst 0.034483 # miss rate for ReadReq accesses
2142system.l2c.ReadReq_miss_rate::cpu1.data 0.071429 # miss rate for ReadReq accesses
2143system.l2c.ReadReq_miss_rate::cpu2.inst 0.193182 # miss rate for ReadReq accesses
2144system.l2c.ReadReq_miss_rate::cpu2.data 0.500000 # miss rate for ReadReq accesses
2145system.l2c.ReadReq_miss_rate::cpu3.inst 0.004630 # miss rate for ReadReq accesses
2146system.l2c.ReadReq_miss_rate::cpu3.data 0.071429 # miss rate for ReadReq accesses
|
| 2147system.l2c.ReadReq_miss_rate::total 0.271379 # miss rate for ReadReq accesses
|
1982system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses
1983system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
1984system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
1985system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
| 2148system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses
2149system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
2150system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
2151system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
|
| 2152system.l2c.UpgradeReq_miss_rate::total 0.963855 # miss rate for UpgradeReq accesses
|
1986system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
1987system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
1988system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
1989system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
| 2153system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
2154system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
2155system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
2156system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
|
| 2157system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
1990system.l2c.demand_miss_rate::cpu0.inst 0.611111 # miss rate for demand accesses
1991system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses
1992system.l2c.demand_miss_rate::cpu1.inst 0.034483 # miss rate for demand accesses
1993system.l2c.demand_miss_rate::cpu1.data 0.500000 # miss rate for demand accesses
1994system.l2c.demand_miss_rate::cpu2.inst 0.193182 # miss rate for demand accesses
1995system.l2c.demand_miss_rate::cpu2.data 0.740741 # miss rate for demand accesses
1996system.l2c.demand_miss_rate::cpu3.inst 0.004630 # miss rate for demand accesses
1997system.l2c.demand_miss_rate::cpu3.data 0.500000 # miss rate for demand accesses
| 2158system.l2c.demand_miss_rate::cpu0.inst 0.611111 # miss rate for demand accesses
2159system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses
2160system.l2c.demand_miss_rate::cpu1.inst 0.034483 # miss rate for demand accesses
2161system.l2c.demand_miss_rate::cpu1.data 0.500000 # miss rate for demand accesses
2162system.l2c.demand_miss_rate::cpu2.inst 0.193182 # miss rate for demand accesses
2163system.l2c.demand_miss_rate::cpu2.data 0.740741 # miss rate for demand accesses
2164system.l2c.demand_miss_rate::cpu3.inst 0.004630 # miss rate for demand accesses
2165system.l2c.demand_miss_rate::cpu3.data 0.500000 # miss rate for demand accesses
|
| 2166system.l2c.demand_miss_rate::total 0.315692 # miss rate for demand accesses
|
1998system.l2c.overall_miss_rate::cpu0.inst 0.611111 # miss rate for overall accesses
1999system.l2c.overall_miss_rate::cpu0.data 0.971264 # miss rate for overall accesses
2000system.l2c.overall_miss_rate::cpu1.inst 0.034483 # miss rate for overall accesses
2001system.l2c.overall_miss_rate::cpu1.data 0.500000 # miss rate for overall accesses
2002system.l2c.overall_miss_rate::cpu2.inst 0.193182 # miss rate for overall accesses
2003system.l2c.overall_miss_rate::cpu2.data 0.740741 # miss rate for overall accesses
2004system.l2c.overall_miss_rate::cpu3.inst 0.004630 # miss rate for overall accesses
2005system.l2c.overall_miss_rate::cpu3.data 0.500000 # miss rate for overall accesses
| 2167system.l2c.overall_miss_rate::cpu0.inst 0.611111 # miss rate for overall accesses
2168system.l2c.overall_miss_rate::cpu0.data 0.971264 # miss rate for overall accesses
2169system.l2c.overall_miss_rate::cpu1.inst 0.034483 # miss rate for overall accesses
2170system.l2c.overall_miss_rate::cpu1.data 0.500000 # miss rate for overall accesses
2171system.l2c.overall_miss_rate::cpu2.inst 0.193182 # miss rate for overall accesses
2172system.l2c.overall_miss_rate::cpu2.data 0.740741 # miss rate for overall accesses
2173system.l2c.overall_miss_rate::cpu3.inst 0.004630 # miss rate for overall accesses
2174system.l2c.overall_miss_rate::cpu3.data 0.500000 # miss rate for overall accesses
|
| 2175system.l2c.overall_miss_rate::total 0.315692 # miss rate for overall accesses
|
2006system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52119.834711 # average ReadReq miss latency
2007system.l2c.ReadReq_avg_miss_latency::cpu0.data 52393.333333 # average ReadReq miss latency
2008system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49633.333333 # average ReadReq miss latency
2009system.l2c.ReadReq_avg_miss_latency::cpu1.data 52500 # average ReadReq miss latency
2010system.l2c.ReadReq_avg_miss_latency::cpu2.inst 51482.352941 # average ReadReq miss latency
2011system.l2c.ReadReq_avg_miss_latency::cpu2.data 52285.714286 # average ReadReq miss latency
2012system.l2c.ReadReq_avg_miss_latency::cpu3.inst 49750 # average ReadReq miss latency
2013system.l2c.ReadReq_avg_miss_latency::cpu3.data 52500 # average ReadReq miss latency
| 2176system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52119.834711 # average ReadReq miss latency
2177system.l2c.ReadReq_avg_miss_latency::cpu0.data 52393.333333 # average ReadReq miss latency
2178system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49633.333333 # average ReadReq miss latency
2179system.l2c.ReadReq_avg_miss_latency::cpu1.data 52500 # average ReadReq miss latency
2180system.l2c.ReadReq_avg_miss_latency::cpu2.inst 51482.352941 # average ReadReq miss latency
2181system.l2c.ReadReq_avg_miss_latency::cpu2.data 52285.714286 # average ReadReq miss latency
2182system.l2c.ReadReq_avg_miss_latency::cpu3.inst 49750 # average ReadReq miss latency
2183system.l2c.ReadReq_avg_miss_latency::cpu3.data 52500 # average ReadReq miss latency
|
| 2184system.l2c.ReadReq_avg_miss_latency::total 51985.428051 # average ReadReq miss latency
|
2014system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2500 # average UpgradeReq miss latency
2015system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 3088.235294 # average UpgradeReq miss latency
2016system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 2625 # average UpgradeReq miss latency
| 2185system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2500 # average UpgradeReq miss latency
2186system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 3088.235294 # average UpgradeReq miss latency
2187system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 2625 # average UpgradeReq miss latency
|
| 2188system.l2c.UpgradeReq_avg_miss_latency::total 1968.750000 # average UpgradeReq miss latency
|
2017system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52547.872340 # average ReadExReq miss latency
2018system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52291.666667 # average ReadExReq miss latency
2019system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52346.153846 # average ReadExReq miss latency
2020system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52291.666667 # average ReadExReq miss latency
| 2189system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52547.872340 # average ReadExReq miss latency
2190system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52291.666667 # average ReadExReq miss latency
2191system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52346.153846 # average ReadExReq miss latency
2192system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52291.666667 # average ReadExReq miss latency
|
| 2193system.l2c.ReadExReq_avg_miss_latency::total 52480.916031 # average ReadExReq miss latency
|
2021system.l2c.demand_avg_miss_latency::cpu0.inst 52119.834711 # average overall miss latency
2022system.l2c.demand_avg_miss_latency::cpu0.data 52479.289941 # average overall miss latency
2023system.l2c.demand_avg_miss_latency::cpu1.inst 49633.333333 # average overall miss latency
2024system.l2c.demand_avg_miss_latency::cpu1.data 52307.692308 # average overall miss latency
2025system.l2c.demand_avg_miss_latency::cpu2.inst 51482.352941 # average overall miss latency
2026system.l2c.demand_avg_miss_latency::cpu2.data 52325 # average overall miss latency
2027system.l2c.demand_avg_miss_latency::cpu3.inst 49750 # average overall miss latency
2028system.l2c.demand_avg_miss_latency::cpu3.data 52307.692308 # average overall miss latency
| 2194system.l2c.demand_avg_miss_latency::cpu0.inst 52119.834711 # average overall miss latency
2195system.l2c.demand_avg_miss_latency::cpu0.data 52479.289941 # average overall miss latency
2196system.l2c.demand_avg_miss_latency::cpu1.inst 49633.333333 # average overall miss latency
2197system.l2c.demand_avg_miss_latency::cpu1.data 52307.692308 # average overall miss latency
2198system.l2c.demand_avg_miss_latency::cpu2.inst 51482.352941 # average overall miss latency
2199system.l2c.demand_avg_miss_latency::cpu2.data 52325 # average overall miss latency
2200system.l2c.demand_avg_miss_latency::cpu3.inst 49750 # average overall miss latency
2201system.l2c.demand_avg_miss_latency::cpu3.data 52307.692308 # average overall miss latency
|
| 2202system.l2c.demand_avg_miss_latency::total 52080.882353 # average overall miss latency
|
2029system.l2c.overall_avg_miss_latency::cpu0.inst 52119.834711 # average overall miss latency
2030system.l2c.overall_avg_miss_latency::cpu0.data 52479.289941 # average overall miss latency
2031system.l2c.overall_avg_miss_latency::cpu1.inst 49633.333333 # average overall miss latency
2032system.l2c.overall_avg_miss_latency::cpu1.data 52307.692308 # average overall miss latency
2033system.l2c.overall_avg_miss_latency::cpu2.inst 51482.352941 # average overall miss latency
2034system.l2c.overall_avg_miss_latency::cpu2.data 52325 # average overall miss latency
2035system.l2c.overall_avg_miss_latency::cpu3.inst 49750 # average overall miss latency
2036system.l2c.overall_avg_miss_latency::cpu3.data 52307.692308 # average overall miss latency
| 2203system.l2c.overall_avg_miss_latency::cpu0.inst 52119.834711 # average overall miss latency
2204system.l2c.overall_avg_miss_latency::cpu0.data 52479.289941 # average overall miss latency
2205system.l2c.overall_avg_miss_latency::cpu1.inst 49633.333333 # average overall miss latency
2206system.l2c.overall_avg_miss_latency::cpu1.data 52307.692308 # average overall miss latency
2207system.l2c.overall_avg_miss_latency::cpu2.inst 51482.352941 # average overall miss latency
2208system.l2c.overall_avg_miss_latency::cpu2.data 52325 # average overall miss latency
2209system.l2c.overall_avg_miss_latency::cpu3.inst 49750 # average overall miss latency
2210system.l2c.overall_avg_miss_latency::cpu3.data 52307.692308 # average overall miss latency
|
| 2211system.l2c.overall_avg_miss_latency::total 52080.882353 # average overall miss latency
|
2037system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2038system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2039system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
2040system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2041system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2042system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2043system.l2c.fast_writes 0 # number of fast writes performed
2044system.l2c.cache_copies 0 # number of cache copies performed
2045system.l2c.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits
2046system.l2c.ReadReq_mshr_hits::cpu2.inst 5 # number of ReadReq MSHR hits
2047system.l2c.ReadReq_mshr_hits::cpu3.inst 1 # number of ReadReq MSHR hits
2048system.l2c.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits
2049system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits
2050system.l2c.demand_mshr_hits::cpu2.inst 5 # number of demand (read+write) MSHR hits
2051system.l2c.demand_mshr_hits::cpu3.inst 1 # number of demand (read+write) MSHR hits
2052system.l2c.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits
2053system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits
2054system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits
2055system.l2c.overall_mshr_hits::cpu3.inst 1 # number of overall MSHR hits
2056system.l2c.overall_mshr_hits::total 7 # number of overall MSHR hits
2057system.l2c.ReadReq_mshr_misses::cpu0.inst 363 # number of ReadReq MSHR misses
2058system.l2c.ReadReq_mshr_misses::cpu0.data 75 # number of ReadReq MSHR misses
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2060system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses
2061system.l2c.ReadReq_mshr_misses::cpu2.inst 80 # number of ReadReq MSHR misses
2062system.l2c.ReadReq_mshr_misses::cpu2.data 7 # number of ReadReq MSHR misses
2063system.l2c.ReadReq_mshr_misses::cpu3.inst 1 # number of ReadReq MSHR misses
2064system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses
2065system.l2c.ReadReq_mshr_misses::total 542 # number of ReadReq MSHR misses
2066system.l2c.UpgradeReq_mshr_misses::cpu0.data 22 # number of UpgradeReq MSHR misses
2067system.l2c.UpgradeReq_mshr_misses::cpu1.data 21 # number of UpgradeReq MSHR misses
2068system.l2c.UpgradeReq_mshr_misses::cpu2.data 17 # number of UpgradeReq MSHR misses
2069system.l2c.UpgradeReq_mshr_misses::cpu3.data 20 # number of UpgradeReq MSHR misses
2070system.l2c.UpgradeReq_mshr_misses::total 80 # number of UpgradeReq MSHR misses
2071system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses
2072system.l2c.ReadExReq_mshr_misses::cpu1.data 12 # number of ReadExReq MSHR misses
2073system.l2c.ReadExReq_mshr_misses::cpu2.data 13 # number of ReadExReq MSHR misses
2074system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses
2075system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses
2076system.l2c.demand_mshr_misses::cpu0.inst 363 # number of demand (read+write) MSHR misses
2077system.l2c.demand_mshr_misses::cpu0.data 169 # number of demand (read+write) MSHR misses
2078system.l2c.demand_mshr_misses::cpu1.inst 14 # number of demand (read+write) MSHR misses
2079system.l2c.demand_mshr_misses::cpu1.data 13 # number of demand (read+write) MSHR misses
2080system.l2c.demand_mshr_misses::cpu2.inst 80 # number of demand (read+write) MSHR misses
2081system.l2c.demand_mshr_misses::cpu2.data 20 # number of demand (read+write) MSHR misses
2082system.l2c.demand_mshr_misses::cpu3.inst 1 # number of demand (read+write) MSHR misses
2083system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses
2084system.l2c.demand_mshr_misses::total 673 # number of demand (read+write) MSHR misses
2085system.l2c.overall_mshr_misses::cpu0.inst 363 # number of overall MSHR misses
2086system.l2c.overall_mshr_misses::cpu0.data 169 # number of overall MSHR misses
2087system.l2c.overall_mshr_misses::cpu1.inst 14 # number of overall MSHR misses
2088system.l2c.overall_mshr_misses::cpu1.data 13 # number of overall MSHR misses
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2090system.l2c.overall_mshr_misses::cpu2.data 20 # number of overall MSHR misses
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2092system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses
2093system.l2c.overall_mshr_misses::total 673 # number of overall MSHR misses
2094system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 14492500 # number of ReadReq MSHR miss cycles
2095system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3016500 # number of ReadReq MSHR miss cycles
2096system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 560000 # number of ReadReq MSHR miss cycles
2097system.l2c.ReadReq_mshr_miss_latency::cpu1.data 40000 # number of ReadReq MSHR miss cycles
2098system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 3200000 # number of ReadReq MSHR miss cycles
2099system.l2c.ReadReq_mshr_miss_latency::cpu2.data 280000 # number of ReadReq MSHR miss cycles
2100system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 40000 # number of ReadReq MSHR miss cycles
2101system.l2c.ReadReq_mshr_miss_latency::cpu3.data 40000 # number of ReadReq MSHR miss cycles
2102system.l2c.ReadReq_mshr_miss_latency::total 21669000 # number of ReadReq MSHR miss cycles
2103system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 880000 # number of UpgradeReq MSHR miss cycles
2104system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 840000 # number of UpgradeReq MSHR miss cycles
2105system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 680000 # number of UpgradeReq MSHR miss cycles
2106system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 800000 # number of UpgradeReq MSHR miss cycles
2107system.l2c.UpgradeReq_mshr_miss_latency::total 3200000 # number of UpgradeReq MSHR miss cycles
2108system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3793000 # number of ReadExReq MSHR miss cycles
2109system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 481500 # number of ReadExReq MSHR miss cycles
2110system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 522500 # number of ReadExReq MSHR miss cycles
2111system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 481500 # number of ReadExReq MSHR miss cycles
2112system.l2c.ReadExReq_mshr_miss_latency::total 5278500 # number of ReadExReq MSHR miss cycles
2113system.l2c.demand_mshr_miss_latency::cpu0.inst 14492500 # number of demand (read+write) MSHR miss cycles
2114system.l2c.demand_mshr_miss_latency::cpu0.data 6809500 # number of demand (read+write) MSHR miss cycles
2115system.l2c.demand_mshr_miss_latency::cpu1.inst 560000 # number of demand (read+write) MSHR miss cycles
2116system.l2c.demand_mshr_miss_latency::cpu1.data 521500 # number of demand (read+write) MSHR miss cycles
2117system.l2c.demand_mshr_miss_latency::cpu2.inst 3200000 # number of demand (read+write) MSHR miss cycles
2118system.l2c.demand_mshr_miss_latency::cpu2.data 802500 # number of demand (read+write) MSHR miss cycles
2119system.l2c.demand_mshr_miss_latency::cpu3.inst 40000 # number of demand (read+write) MSHR miss cycles
2120system.l2c.demand_mshr_miss_latency::cpu3.data 521500 # number of demand (read+write) MSHR miss cycles
2121system.l2c.demand_mshr_miss_latency::total 26947500 # number of demand (read+write) MSHR miss cycles
2122system.l2c.overall_mshr_miss_latency::cpu0.inst 14492500 # number of overall MSHR miss cycles
2123system.l2c.overall_mshr_miss_latency::cpu0.data 6809500 # number of overall MSHR miss cycles
2124system.l2c.overall_mshr_miss_latency::cpu1.inst 560000 # number of overall MSHR miss cycles
2125system.l2c.overall_mshr_miss_latency::cpu1.data 521500 # number of overall MSHR miss cycles
2126system.l2c.overall_mshr_miss_latency::cpu2.inst 3200000 # number of overall MSHR miss cycles
2127system.l2c.overall_mshr_miss_latency::cpu2.data 802500 # number of overall MSHR miss cycles
2128system.l2c.overall_mshr_miss_latency::cpu3.inst 40000 # number of overall MSHR miss cycles
2129system.l2c.overall_mshr_miss_latency::cpu3.data 521500 # number of overall MSHR miss cycles
2130system.l2c.overall_mshr_miss_latency::total 26947500 # number of overall MSHR miss cycles
2131system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for ReadReq accesses
2132system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadReq accesses
2133system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for ReadReq accesses
2134system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.071429 # mshr miss rate for ReadReq accesses
2135system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.181818 # mshr miss rate for ReadReq accesses
2136system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.500000 # mshr miss rate for ReadReq accesses
2137system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for ReadReq accesses
2138system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.071429 # mshr miss rate for ReadReq accesses
| 2212system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2213system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2214system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
2215system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2216system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2217system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2218system.l2c.fast_writes 0 # number of fast writes performed
2219system.l2c.cache_copies 0 # number of cache copies performed
2220system.l2c.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits
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2222system.l2c.ReadReq_mshr_hits::cpu3.inst 1 # number of ReadReq MSHR hits
2223system.l2c.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits
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2226system.l2c.demand_mshr_hits::cpu3.inst 1 # number of demand (read+write) MSHR hits
2227system.l2c.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits
2228system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits
2229system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits
2230system.l2c.overall_mshr_hits::cpu3.inst 1 # number of overall MSHR hits
2231system.l2c.overall_mshr_hits::total 7 # number of overall MSHR hits
2232system.l2c.ReadReq_mshr_misses::cpu0.inst 363 # number of ReadReq MSHR misses
2233system.l2c.ReadReq_mshr_misses::cpu0.data 75 # number of ReadReq MSHR misses
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2235system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses
2236system.l2c.ReadReq_mshr_misses::cpu2.inst 80 # number of ReadReq MSHR misses
2237system.l2c.ReadReq_mshr_misses::cpu2.data 7 # number of ReadReq MSHR misses
2238system.l2c.ReadReq_mshr_misses::cpu3.inst 1 # number of ReadReq MSHR misses
2239system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses
2240system.l2c.ReadReq_mshr_misses::total 542 # number of ReadReq MSHR misses
2241system.l2c.UpgradeReq_mshr_misses::cpu0.data 22 # number of UpgradeReq MSHR misses
2242system.l2c.UpgradeReq_mshr_misses::cpu1.data 21 # number of UpgradeReq MSHR misses
2243system.l2c.UpgradeReq_mshr_misses::cpu2.data 17 # number of UpgradeReq MSHR misses
2244system.l2c.UpgradeReq_mshr_misses::cpu3.data 20 # number of UpgradeReq MSHR misses
2245system.l2c.UpgradeReq_mshr_misses::total 80 # number of UpgradeReq MSHR misses
2246system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses
2247system.l2c.ReadExReq_mshr_misses::cpu1.data 12 # number of ReadExReq MSHR misses
2248system.l2c.ReadExReq_mshr_misses::cpu2.data 13 # number of ReadExReq MSHR misses
2249system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses
2250system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses
2251system.l2c.demand_mshr_misses::cpu0.inst 363 # number of demand (read+write) MSHR misses
2252system.l2c.demand_mshr_misses::cpu0.data 169 # number of demand (read+write) MSHR misses
2253system.l2c.demand_mshr_misses::cpu1.inst 14 # number of demand (read+write) MSHR misses
2254system.l2c.demand_mshr_misses::cpu1.data 13 # number of demand (read+write) MSHR misses
2255system.l2c.demand_mshr_misses::cpu2.inst 80 # number of demand (read+write) MSHR misses
2256system.l2c.demand_mshr_misses::cpu2.data 20 # number of demand (read+write) MSHR misses
2257system.l2c.demand_mshr_misses::cpu3.inst 1 # number of demand (read+write) MSHR misses
2258system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses
2259system.l2c.demand_mshr_misses::total 673 # number of demand (read+write) MSHR misses
2260system.l2c.overall_mshr_misses::cpu0.inst 363 # number of overall MSHR misses
2261system.l2c.overall_mshr_misses::cpu0.data 169 # number of overall MSHR misses
2262system.l2c.overall_mshr_misses::cpu1.inst 14 # number of overall MSHR misses
2263system.l2c.overall_mshr_misses::cpu1.data 13 # number of overall MSHR misses
2264system.l2c.overall_mshr_misses::cpu2.inst 80 # number of overall MSHR misses
2265system.l2c.overall_mshr_misses::cpu2.data 20 # number of overall MSHR misses
2266system.l2c.overall_mshr_misses::cpu3.inst 1 # number of overall MSHR misses
2267system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses
2268system.l2c.overall_mshr_misses::total 673 # number of overall MSHR misses
2269system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 14492500 # number of ReadReq MSHR miss cycles
2270system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3016500 # number of ReadReq MSHR miss cycles
2271system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 560000 # number of ReadReq MSHR miss cycles
2272system.l2c.ReadReq_mshr_miss_latency::cpu1.data 40000 # number of ReadReq MSHR miss cycles
2273system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 3200000 # number of ReadReq MSHR miss cycles
2274system.l2c.ReadReq_mshr_miss_latency::cpu2.data 280000 # number of ReadReq MSHR miss cycles
2275system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 40000 # number of ReadReq MSHR miss cycles
2276system.l2c.ReadReq_mshr_miss_latency::cpu3.data 40000 # number of ReadReq MSHR miss cycles
2277system.l2c.ReadReq_mshr_miss_latency::total 21669000 # number of ReadReq MSHR miss cycles
2278system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 880000 # number of UpgradeReq MSHR miss cycles
2279system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 840000 # number of UpgradeReq MSHR miss cycles
2280system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 680000 # number of UpgradeReq MSHR miss cycles
2281system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 800000 # number of UpgradeReq MSHR miss cycles
2282system.l2c.UpgradeReq_mshr_miss_latency::total 3200000 # number of UpgradeReq MSHR miss cycles
2283system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3793000 # number of ReadExReq MSHR miss cycles
2284system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 481500 # number of ReadExReq MSHR miss cycles
2285system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 522500 # number of ReadExReq MSHR miss cycles
2286system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 481500 # number of ReadExReq MSHR miss cycles
2287system.l2c.ReadExReq_mshr_miss_latency::total 5278500 # number of ReadExReq MSHR miss cycles
2288system.l2c.demand_mshr_miss_latency::cpu0.inst 14492500 # number of demand (read+write) MSHR miss cycles
2289system.l2c.demand_mshr_miss_latency::cpu0.data 6809500 # number of demand (read+write) MSHR miss cycles
2290system.l2c.demand_mshr_miss_latency::cpu1.inst 560000 # number of demand (read+write) MSHR miss cycles
2291system.l2c.demand_mshr_miss_latency::cpu1.data 521500 # number of demand (read+write) MSHR miss cycles
2292system.l2c.demand_mshr_miss_latency::cpu2.inst 3200000 # number of demand (read+write) MSHR miss cycles
2293system.l2c.demand_mshr_miss_latency::cpu2.data 802500 # number of demand (read+write) MSHR miss cycles
2294system.l2c.demand_mshr_miss_latency::cpu3.inst 40000 # number of demand (read+write) MSHR miss cycles
2295system.l2c.demand_mshr_miss_latency::cpu3.data 521500 # number of demand (read+write) MSHR miss cycles
2296system.l2c.demand_mshr_miss_latency::total 26947500 # number of demand (read+write) MSHR miss cycles
2297system.l2c.overall_mshr_miss_latency::cpu0.inst 14492500 # number of overall MSHR miss cycles
2298system.l2c.overall_mshr_miss_latency::cpu0.data 6809500 # number of overall MSHR miss cycles
2299system.l2c.overall_mshr_miss_latency::cpu1.inst 560000 # number of overall MSHR miss cycles
2300system.l2c.overall_mshr_miss_latency::cpu1.data 521500 # number of overall MSHR miss cycles
2301system.l2c.overall_mshr_miss_latency::cpu2.inst 3200000 # number of overall MSHR miss cycles
2302system.l2c.overall_mshr_miss_latency::cpu2.data 802500 # number of overall MSHR miss cycles
2303system.l2c.overall_mshr_miss_latency::cpu3.inst 40000 # number of overall MSHR miss cycles
2304system.l2c.overall_mshr_miss_latency::cpu3.data 521500 # number of overall MSHR miss cycles
2305system.l2c.overall_mshr_miss_latency::total 26947500 # number of overall MSHR miss cycles
2306system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for ReadReq accesses
2307system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadReq accesses
2308system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for ReadReq accesses
2309system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.071429 # mshr miss rate for ReadReq accesses
2310system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.181818 # mshr miss rate for ReadReq accesses
2311system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.500000 # mshr miss rate for ReadReq accesses
2312system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for ReadReq accesses
2313system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.071429 # mshr miss rate for ReadReq accesses
|
| 2314system.l2c.ReadReq_mshr_miss_rate::total 0.267919 # mshr miss rate for ReadReq accesses
|
2139system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses
2140system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2141system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
2142system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
| 2315system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses
2316system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2317system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
2318system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
|
| 2319system.l2c.UpgradeReq_mshr_miss_rate::total 0.963855 # mshr miss rate for UpgradeReq accesses
|
2143system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
2144system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
2145system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
2146system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
| 2320system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
2321system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
2322system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
2323system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
|
| 2324system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
2147system.l2c.demand_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for demand accesses
2148system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses
2149system.l2c.demand_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for demand accesses
2150system.l2c.demand_mshr_miss_rate::cpu1.data 0.500000 # mshr miss rate for demand accesses
2151system.l2c.demand_mshr_miss_rate::cpu2.inst 0.181818 # mshr miss rate for demand accesses
2152system.l2c.demand_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for demand accesses
2153system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for demand accesses
2154system.l2c.demand_mshr_miss_rate::cpu3.data 0.500000 # mshr miss rate for demand accesses
| 2325system.l2c.demand_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for demand accesses
2326system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses
2327system.l2c.demand_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for demand accesses
2328system.l2c.demand_mshr_miss_rate::cpu1.data 0.500000 # mshr miss rate for demand accesses
2329system.l2c.demand_mshr_miss_rate::cpu2.inst 0.181818 # mshr miss rate for demand accesses
2330system.l2c.demand_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for demand accesses
2331system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for demand accesses
2332system.l2c.demand_mshr_miss_rate::cpu3.data 0.500000 # mshr miss rate for demand accesses
|
| 2333system.l2c.demand_mshr_miss_rate::total 0.312442 # mshr miss rate for demand accesses
|
2155system.l2c.overall_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for overall accesses
2156system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses
2157system.l2c.overall_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for overall accesses
2158system.l2c.overall_mshr_miss_rate::cpu1.data 0.500000 # mshr miss rate for overall accesses
2159system.l2c.overall_mshr_miss_rate::cpu2.inst 0.181818 # mshr miss rate for overall accesses
2160system.l2c.overall_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for overall accesses
2161system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for overall accesses
2162system.l2c.overall_mshr_miss_rate::cpu3.data 0.500000 # mshr miss rate for overall accesses
| 2334system.l2c.overall_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for overall accesses
2335system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses
2336system.l2c.overall_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for overall accesses
2337system.l2c.overall_mshr_miss_rate::cpu1.data 0.500000 # mshr miss rate for overall accesses
2338system.l2c.overall_mshr_miss_rate::cpu2.inst 0.181818 # mshr miss rate for overall accesses
2339system.l2c.overall_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for overall accesses
2340system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for overall accesses
2341system.l2c.overall_mshr_miss_rate::cpu3.data 0.500000 # mshr miss rate for overall accesses
|
| 2342system.l2c.overall_mshr_miss_rate::total 0.312442 # mshr miss rate for overall accesses
|
2163system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average ReadReq mshr miss latency
2164system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40220 # average ReadReq mshr miss latency
2165system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency
2166system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency
2167system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency
2168system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency
2169system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency
2170system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency
| 2343system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average ReadReq mshr miss latency
2344system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40220 # average ReadReq mshr miss latency
2345system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency
2346system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency
2347system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency
2348system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency
2349system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency
2350system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency
|
| 2351system.l2c.ReadReq_avg_mshr_miss_latency::total 39979.704797 # average ReadReq mshr miss latency
|
2171system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency
2172system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency
2173system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency
2174system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency
| 2352system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency
2353system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency
2354system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency
2355system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency
|
| 2356system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40000 # average UpgradeReq mshr miss latency
|
2175system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40351.063830 # average ReadExReq mshr miss latency
2176system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40125 # average ReadExReq mshr miss latency
2177system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40192.307692 # average ReadExReq mshr miss latency
2178system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40125 # average ReadExReq mshr miss latency
| 2357system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40351.063830 # average ReadExReq mshr miss latency
2358system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40125 # average ReadExReq mshr miss latency
2359system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40192.307692 # average ReadExReq mshr miss latency
2360system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40125 # average ReadExReq mshr miss latency
|
| 2361system.l2c.ReadExReq_avg_mshr_miss_latency::total 40293.893130 # average ReadExReq mshr miss latency
|
2179system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average overall mshr miss latency
2180system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40292.899408 # average overall mshr miss latency
2181system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency
2182system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40115.384615 # average overall mshr miss latency
2183system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
2184system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40125 # average overall mshr miss latency
2185system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
2186system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency
| 2362system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average overall mshr miss latency
2363system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40292.899408 # average overall mshr miss latency
2364system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency
2365system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40115.384615 # average overall mshr miss latency
2366system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
2367system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40125 # average overall mshr miss latency
2368system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
2369system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency
|
| 2370system.l2c.demand_avg_mshr_miss_latency::total 40040.861813 # average overall mshr miss latency
|
2187system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average overall mshr miss latency
2188system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40292.899408 # average overall mshr miss latency
2189system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency
2190system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40115.384615 # average overall mshr miss latency
2191system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
2192system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40125 # average overall mshr miss latency
2193system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
2194system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency
| 2371system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average overall mshr miss latency
2372system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40292.899408 # average overall mshr miss latency
2373system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency
2374system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40115.384615 # average overall mshr miss latency
2375system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
2376system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40125 # average overall mshr miss latency
2377system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
2378system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency
|
| 2379system.l2c.overall_avg_mshr_miss_latency::total 40040.861813 # average overall mshr miss latency
|
2195system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2196
2197---------- End Simulation Statistics ----------
| 2380system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2381
2382---------- End Simulation Statistics ----------
|