1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000111 # Number of seconds simulated
4sim_ticks 110804500 # Number of ticks simulated
5final_tick 110804500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 91896 # Simulator instruction rate (inst/s)
8host_op_rate 91896 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 9765210 # Simulator tick rate (ticks/s)
10host_mem_usage 250112 # Number of bytes of host memory used
11host_seconds 11.35 # Real time elapsed on the host
12sim_insts 1042724 # Number of instructions simulated
13sim_ops 1042724 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory
16system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu2.inst 4672 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu3.inst 384 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory

--- 7 unchanged lines hidden (view full) ---

29system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory
32system.physmem.num_reads::cpu2.inst 73 # Number of read requests responded to by this memory
33system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu3.inst 6 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
36system.physmem.num_reads::total 659 # Number of read requests responded to by this memory
37system.physmem.bw_read::cpu0.inst 205623418 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu0.data 97035770 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu1.inst 5775939 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::cpu1.data 7508720 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::cpu2.inst 42164353 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_read::cpu2.data 11551877 # Total read bandwidth from this memory (bytes/s)
43system.physmem.bw_read::cpu3.inst 3465563 # Total read bandwidth from this memory (bytes/s)
44system.physmem.bw_read::cpu3.data 7508720 # Total read bandwidth from this memory (bytes/s)
45system.physmem.bw_read::total 380634361 # Total read bandwidth from this memory (bytes/s)
46system.physmem.bw_inst_read::cpu0.inst 205623418 # Instruction read bandwidth from this memory (bytes/s)
47system.physmem.bw_inst_read::cpu1.inst 5775939 # Instruction read bandwidth from this memory (bytes/s)
48system.physmem.bw_inst_read::cpu2.inst 42164353 # Instruction read bandwidth from this memory (bytes/s)
49system.physmem.bw_inst_read::cpu3.inst 3465563 # Instruction read bandwidth from this memory (bytes/s)
50system.physmem.bw_inst_read::total 257029272 # Instruction read bandwidth from this memory (bytes/s)
51system.physmem.bw_total::cpu0.inst 205623418 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::cpu0.data 97035770 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.bw_total::cpu1.inst 5775939 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.bw_total::cpu1.data 7508720 # Total bandwidth to/from this memory (bytes/s)
55system.physmem.bw_total::cpu2.inst 42164353 # Total bandwidth to/from this memory (bytes/s)
56system.physmem.bw_total::cpu2.data 11551877 # Total bandwidth to/from this memory (bytes/s)
57system.physmem.bw_total::cpu3.inst 3465563 # Total bandwidth to/from this memory (bytes/s)
58system.physmem.bw_total::cpu3.data 7508720 # Total bandwidth to/from this memory (bytes/s)
59system.physmem.bw_total::total 380634361 # Total bandwidth to/from this memory (bytes/s)
60system.physmem.readReqs 660 # Total number of read requests accepted by DRAM controller
61system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
62system.physmem.readBursts 660 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
63system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
64system.physmem.bytesRead 42176 # Total number of bytes read from memory
65system.physmem.bytesWritten 0 # Total number of bytes written to memory
66system.physmem.bytesConsumedRd 42176 # bytesRead derated as per pkt->getSize()
67system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
68system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
69system.physmem.neitherReadNorWrite 76 # Reqs where no action is needed
70system.physmem.perBankRdReqs::0 115 # Track reads on a per bank basis
71system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis
72system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis
73system.physmem.perBankRdReqs::3 60 # Track reads on a per bank basis
74system.physmem.perBankRdReqs::4 65 # Track reads on a per bank basis
75system.physmem.perBankRdReqs::5 27 # Track reads on a per bank basis
76system.physmem.perBankRdReqs::6 18 # Track reads on a per bank basis
77system.physmem.perBankRdReqs::7 24 # Track reads on a per bank basis
78system.physmem.perBankRdReqs::8 7 # Track reads on a per bank basis
79system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis
80system.physmem.perBankRdReqs::10 23 # Track reads on a per bank basis
81system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis
82system.physmem.perBankRdReqs::12 60 # Track reads on a per bank basis
83system.physmem.perBankRdReqs::13 38 # Track reads on a per bank basis
84system.physmem.perBankRdReqs::14 17 # Track reads on a per bank basis
85system.physmem.perBankRdReqs::15 98 # Track reads on a per bank basis
86system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
87system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
88system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
89system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
90system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
91system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
92system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
93system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
94system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
95system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
96system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
97system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
98system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
99system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
100system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
101system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
102system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
103system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
104system.physmem.totGap 110776500 # Total gap between requests
105system.physmem.readPktSize::0 0 # Categorize read packet sizes
106system.physmem.readPktSize::1 0 # Categorize read packet sizes
107system.physmem.readPktSize::2 0 # Categorize read packet sizes
108system.physmem.readPktSize::3 0 # Categorize read packet sizes
109system.physmem.readPktSize::4 0 # Categorize read packet sizes
110system.physmem.readPktSize::5 0 # Categorize read packet sizes
111system.physmem.readPktSize::6 660 # Categorize read packet sizes
112system.physmem.writePktSize::0 0 # Categorize write packet sizes
113system.physmem.writePktSize::1 0 # Categorize write packet sizes
114system.physmem.writePktSize::2 0 # Categorize write packet sizes
115system.physmem.writePktSize::3 0 # Categorize write packet sizes
116system.physmem.writePktSize::4 0 # Categorize write packet sizes
117system.physmem.writePktSize::5 0 # Categorize write packet sizes
118system.physmem.writePktSize::6 0 # Categorize write packet sizes
119system.physmem.rdQLenPdf::0 404 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::1 193 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see

--- 44 unchanged lines hidden (view full) ---

175system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
183system.physmem.bytesPerActivate::samples 128 # Bytes accessed per row activation
184system.physmem.bytesPerActivate::mean 281.500000 # Bytes accessed per row activation
185system.physmem.bytesPerActivate::gmean 172.723314 # Bytes accessed per row activation
186system.physmem.bytesPerActivate::stdev 317.555625 # Bytes accessed per row activation
187system.physmem.bytesPerActivate::64 51 39.84% 39.84% # Bytes accessed per row activation
188system.physmem.bytesPerActivate::128 11 8.59% 48.44% # Bytes accessed per row activation
189system.physmem.bytesPerActivate::192 15 11.72% 60.16% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::256 9 7.03% 67.19% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::320 10 7.81% 75.00% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::384 5 3.91% 78.91% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::448 3 2.34% 81.25% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::512 4 3.12% 84.38% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::576 3 2.34% 86.72% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::640 4 3.12% 89.84% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::704 2 1.56% 91.41% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::768 2 1.56% 92.97% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::832 2 1.56% 94.53% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::1024 4 3.12% 97.66% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::1152 1 0.78% 98.44% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::1536 1 0.78% 99.22% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::1984 1 0.78% 100.00% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::total 128 # Bytes accessed per row activation
205system.physmem.totQLat 3818750 # Total cycles spent in queuing delays
206system.physmem.totMemAccLat 18118750 # Sum of mem lat for all requests
207system.physmem.totBusLat 3300000 # Total cycles spent in databus access
208system.physmem.totBankLat 11000000 # Total cycles spent in bank access
209system.physmem.avgQLat 5785.98 # Average queueing delay per request
210system.physmem.avgBankLat 16666.67 # Average bank access latency per request
211system.physmem.avgBusLat 5000.00 # Average bus latency per request
212system.physmem.avgMemAccLat 27452.65 # Average memory access latency
213system.physmem.avgRdBW 380.63 # Average achieved read bandwidth in MB/s
214system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
215system.physmem.avgConsumedRdBW 380.63 # Average consumed read bandwidth in MB/s
216system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
217system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
218system.physmem.busUtil 2.97 # Data bus utilization in percentage
219system.physmem.avgRdQLen 0.16 # Average read queue length over time
220system.physmem.avgWrQLen 0.00 # Average write queue length over time
221system.physmem.readRowHits 532 # Number of row buffer hits during reads
222system.physmem.writeRowHits 0 # Number of row buffer hits during writes
223system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads
224system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
225system.physmem.avgGap 167843.18 # Average gap between requests
226system.membus.throughput 380634361 # Throughput (bytes/s)
227system.membus.trans_dist::ReadReq 529 # Transaction distribution
228system.membus.trans_dist::ReadResp 528 # Transaction distribution
229system.membus.trans_dist::UpgradeReq 287 # Transaction distribution
230system.membus.trans_dist::UpgradeResp 76 # Transaction distribution
231system.membus.trans_dist::ReadExReq 163 # Transaction distribution
232system.membus.trans_dist::ReadExResp 131 # Transaction distribution
233system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes)
234system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes)
235system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42176 # Cumulative packet size per connected master and slave (bytes)
236system.membus.tot_pkt_size::total 42176 # Cumulative packet size per connected master and slave (bytes)
237system.membus.data_through_bus 42176 # Total data (bytes)
238system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
239system.membus.reqLayer0.occupancy 929000 # Layer occupancy (ticks)
240system.membus.reqLayer0.utilization 0.8 # Layer utilization (%)
241system.membus.respLayer1.occupancy 6308925 # Layer occupancy (ticks)
242system.membus.respLayer1.utilization 5.7 # Layer utilization (%)
243system.l2c.tags.replacements 0 # number of replacements
244system.l2c.tags.tagsinuse 416.979851 # Cycle average of tags in use
245system.l2c.tags.total_refs 1443 # Total number of references to valid blocks.
246system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks.
247system.l2c.tags.avg_refs 2.743346 # Average number of references to valid blocks.
248system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
249system.l2c.tags.occ_blocks::writebacks 0.800256 # Average occupied blocks per requestor
250system.l2c.tags.occ_blocks::cpu0.inst 284.888559 # Average occupied blocks per requestor
251system.l2c.tags.occ_blocks::cpu0.data 58.382327 # Average occupied blocks per requestor
252system.l2c.tags.occ_blocks::cpu1.inst 7.813679 # Average occupied blocks per requestor
253system.l2c.tags.occ_blocks::cpu1.data 0.733163 # Average occupied blocks per requestor
254system.l2c.tags.occ_blocks::cpu2.inst 55.504569 # Average occupied blocks per requestor
255system.l2c.tags.occ_blocks::cpu2.data 5.417548 # Average occupied blocks per requestor
256system.l2c.tags.occ_blocks::cpu3.inst 2.743977 # Average occupied blocks per requestor
257system.l2c.tags.occ_blocks::cpu3.data 0.695773 # Average occupied blocks per requestor
258system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy
259system.l2c.tags.occ_percent::cpu0.inst 0.004347 # Average percentage of cache occupancy
260system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy
261system.l2c.tags.occ_percent::cpu1.inst 0.000119 # Average percentage of cache occupancy
262system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy
263system.l2c.tags.occ_percent::cpu2.inst 0.000847 # Average percentage of cache occupancy
264system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy
265system.l2c.tags.occ_percent::cpu3.inst 0.000042 # Average percentage of cache occupancy
266system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy
267system.l2c.tags.occ_percent::total 0.006363 # Average percentage of cache occupancy
268system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits
269system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
270system.l2c.ReadReq_hits::cpu1.inst 412 # number of ReadReq hits
271system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits
272system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits
273system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits
274system.l2c.ReadReq_hits::cpu3.inst 421 # number of ReadReq hits
275system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits
276system.l2c.ReadReq_hits::total 1443 # number of ReadReq hits
277system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
278system.l2c.Writeback_hits::total 1 # number of Writeback hits
279system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
280system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits
281system.l2c.demand_hits::cpu0.inst 229 # number of demand (read+write) hits
282system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
283system.l2c.demand_hits::cpu1.inst 412 # number of demand (read+write) hits
284system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits
285system.l2c.demand_hits::cpu2.inst 349 # number of demand (read+write) hits
286system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits
287system.l2c.demand_hits::cpu3.inst 421 # number of demand (read+write) hits
288system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits
289system.l2c.demand_hits::total 1443 # number of demand (read+write) hits
290system.l2c.overall_hits::cpu0.inst 229 # number of overall hits
291system.l2c.overall_hits::cpu0.data 5 # number of overall hits
292system.l2c.overall_hits::cpu1.inst 412 # number of overall hits
293system.l2c.overall_hits::cpu1.data 11 # number of overall hits
294system.l2c.overall_hits::cpu2.inst 349 # number of overall hits
295system.l2c.overall_hits::cpu2.data 5 # number of overall hits
296system.l2c.overall_hits::cpu3.inst 421 # number of overall hits
297system.l2c.overall_hits::cpu3.data 11 # number of overall hits
298system.l2c.overall_hits::total 1443 # number of overall hits
299system.l2c.ReadReq_misses::cpu0.inst 359 # number of ReadReq misses
300system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses
301system.l2c.ReadReq_misses::cpu1.inst 16 # number of ReadReq misses
302system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses
303system.l2c.ReadReq_misses::cpu2.inst 76 # number of ReadReq misses
304system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses
305system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses
306system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses
307system.l2c.ReadReq_misses::total 543 # number of ReadReq misses
308system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses
309system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses
310system.l2c.UpgradeReq_misses::cpu2.data 18 # number of UpgradeReq misses
311system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses
312system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses
313system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses
314system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses
315system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses
316system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
317system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses
318system.l2c.demand_misses::cpu0.inst 359 # number of demand (read+write) misses
319system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses

--- 8 unchanged lines hidden (view full) ---

328system.l2c.overall_misses::cpu0.data 168 # number of overall misses
329system.l2c.overall_misses::cpu1.inst 16 # number of overall misses
330system.l2c.overall_misses::cpu1.data 13 # number of overall misses
331system.l2c.overall_misses::cpu2.inst 76 # number of overall misses
332system.l2c.overall_misses::cpu2.data 20 # number of overall misses
333system.l2c.overall_misses::cpu3.inst 9 # number of overall misses
334system.l2c.overall_misses::cpu3.data 13 # number of overall misses
335system.l2c.overall_misses::total 674 # number of overall misses
336system.l2c.ReadReq_miss_latency::cpu0.inst 24362500 # number of ReadReq miss cycles
337system.l2c.ReadReq_miss_latency::cpu0.data 5673000 # number of ReadReq miss cycles
338system.l2c.ReadReq_miss_latency::cpu1.inst 1205500 # number of ReadReq miss cycles
339system.l2c.ReadReq_miss_latency::cpu1.data 88750 # number of ReadReq miss cycles
340system.l2c.ReadReq_miss_latency::cpu2.inst 5263750 # number of ReadReq miss cycles
341system.l2c.ReadReq_miss_latency::cpu2.data 523750 # number of ReadReq miss cycles
342system.l2c.ReadReq_miss_latency::cpu3.inst 570250 # number of ReadReq miss cycles
343system.l2c.ReadReq_miss_latency::cpu3.data 88750 # number of ReadReq miss cycles
344system.l2c.ReadReq_miss_latency::total 37776250 # number of ReadReq miss cycles
345system.l2c.ReadExReq_miss_latency::cpu0.data 7324500 # number of ReadExReq miss cycles
346system.l2c.ReadExReq_miss_latency::cpu1.data 823750 # number of ReadExReq miss cycles
347system.l2c.ReadExReq_miss_latency::cpu2.data 1067249 # number of ReadExReq miss cycles
348system.l2c.ReadExReq_miss_latency::cpu3.data 882250 # number of ReadExReq miss cycles
349system.l2c.ReadExReq_miss_latency::total 10097749 # number of ReadExReq miss cycles
350system.l2c.demand_miss_latency::cpu0.inst 24362500 # number of demand (read+write) miss cycles
351system.l2c.demand_miss_latency::cpu0.data 12997500 # number of demand (read+write) miss cycles
352system.l2c.demand_miss_latency::cpu1.inst 1205500 # number of demand (read+write) miss cycles
353system.l2c.demand_miss_latency::cpu1.data 912500 # number of demand (read+write) miss cycles
354system.l2c.demand_miss_latency::cpu2.inst 5263750 # number of demand (read+write) miss cycles
355system.l2c.demand_miss_latency::cpu2.data 1590999 # number of demand (read+write) miss cycles
356system.l2c.demand_miss_latency::cpu3.inst 570250 # number of demand (read+write) miss cycles
357system.l2c.demand_miss_latency::cpu3.data 971000 # number of demand (read+write) miss cycles
358system.l2c.demand_miss_latency::total 47873999 # number of demand (read+write) miss cycles
359system.l2c.overall_miss_latency::cpu0.inst 24362500 # number of overall miss cycles
360system.l2c.overall_miss_latency::cpu0.data 12997500 # number of overall miss cycles
361system.l2c.overall_miss_latency::cpu1.inst 1205500 # number of overall miss cycles
362system.l2c.overall_miss_latency::cpu1.data 912500 # number of overall miss cycles
363system.l2c.overall_miss_latency::cpu2.inst 5263750 # number of overall miss cycles
364system.l2c.overall_miss_latency::cpu2.data 1590999 # number of overall miss cycles
365system.l2c.overall_miss_latency::cpu3.inst 570250 # number of overall miss cycles
366system.l2c.overall_miss_latency::cpu3.data 971000 # number of overall miss cycles
367system.l2c.overall_miss_latency::total 47873999 # number of overall miss cycles
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--- 16 unchanged lines hidden (view full) ---

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--- 8 unchanged lines hidden (view full) ---

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627system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 60937.500000 # average ReadExReq mshr miss latency
628system.l2c.ReadExReq_avg_mshr_miss_latency::total 64574.419847 # average ReadExReq mshr miss latency
629system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency
630system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency
631system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency
632system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency
633system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency
634system.l2c.demand_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency
635system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency
636system.l2c.demand_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency
637system.l2c.demand_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency
638system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency
639system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency
640system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency
641system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency
642system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency
643system.l2c.overall_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency
644system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency
645system.l2c.overall_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency
646system.l2c.overall_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency
647system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
648system.toL2Bus.throughput 1691772446 # Throughput (bytes/s)
649system.toL2Bus.trans_dist::ReadReq 2536 # Transaction distribution
650system.toL2Bus.trans_dist::ReadResp 2535 # Transaction distribution
651system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
652system.toL2Bus.trans_dist::UpgradeReq 290 # Transaction distribution
653system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution
654system.toL2Bus.trans_dist::ReadExReq 393 # Transaction distribution
655system.toL2Bus.trans_dist::ReadExResp 393 # Transaction distribution
656system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1175 # Packet count per connected master and slave (bytes)
657system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 586 # Packet count per connected master and slave (bytes)
658system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 856 # Packet count per connected master and slave (bytes)
659system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes)
660system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 850 # Packet count per connected master and slave (bytes)
661system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 371 # Packet count per connected master and slave (bytes)
662system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 860 # Packet count per connected master and slave (bytes)
663system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes)
664system.toL2Bus.pkt_count::total 5415 # Packet count per connected master and slave (bytes)
665system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 37568 # Cumulative packet size per connected master and slave (bytes)
666system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes)
667system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 27392 # Cumulative packet size per connected master and slave (bytes)
668system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
669system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 27200 # Cumulative packet size per connected master and slave (bytes)
670system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
671system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 27520 # Cumulative packet size per connected master and slave (bytes)
672system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
673system.toL2Bus.tot_pkt_size::total 135488 # Cumulative packet size per connected master and slave (bytes)
674system.toL2Bus.data_through_bus 135488 # Total data (bytes)
675system.toL2Bus.snoop_data_through_bus 51968 # Total snoop data (bytes)
676system.toL2Bus.reqLayer0.occupancy 1623982 # Layer occupancy (ticks)
677system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%)
678system.toL2Bus.respLayer0.occupancy 2710248 # Layer occupancy (ticks)
679system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%)
680system.toL2Bus.respLayer1.occupancy 1462515 # Layer occupancy (ticks)
681system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
682system.toL2Bus.respLayer2.occupancy 1929494 # Layer occupancy (ticks)
683system.toL2Bus.respLayer2.utilization 1.7 # Layer utilization (%)
684system.toL2Bus.respLayer3.occupancy 1189495 # Layer occupancy (ticks)
685system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%)
686system.toL2Bus.respLayer4.occupancy 1927246 # Layer occupancy (ticks)
687system.toL2Bus.respLayer4.utilization 1.7 # Layer utilization (%)
688system.toL2Bus.respLayer5.occupancy 1192987 # Layer occupancy (ticks)
689system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%)
690system.toL2Bus.respLayer6.occupancy 1937245 # Layer occupancy (ticks)
691system.toL2Bus.respLayer6.utilization 1.7 # Layer utilization (%)
692system.toL2Bus.respLayer7.occupancy 1118007 # Layer occupancy (ticks)
693system.toL2Bus.respLayer7.utilization 1.0 # Layer utilization (%)
694system.cpu0.branchPred.lookups 82992 # Number of BP lookups
695system.cpu0.branchPred.condPredicted 80791 # Number of conditional branches predicted
696system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect
697system.cpu0.branchPred.BTBLookups 80321 # Number of BTB lookups
698system.cpu0.branchPred.BTBHits 78273 # Number of BTB hits
699system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
700system.cpu0.branchPred.BTBHitPct 97.450231 # BTB Hit Percentage
701system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target.
702system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions.
703system.cpu0.workload.num_syscalls 89 # Number of system calls
704system.cpu0.numCycles 221610 # number of cpu cycles simulated
705system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
706system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
707system.cpu0.fetch.icacheStallCycles 17247 # Number of cycles fetch is stalled on an Icache miss
708system.cpu0.fetch.Insts 492529 # Number of instructions fetch has processed
709system.cpu0.fetch.Branches 82992 # Number of branches that fetch encountered
710system.cpu0.fetch.predictedBranches 78785 # Number of branches that fetch has predicted taken
711system.cpu0.fetch.Cycles 161677 # Number of cycles fetch has run and was not squashing or blocked
712system.cpu0.fetch.SquashCycles 3808 # Number of cycles fetch has spent squashing
713system.cpu0.fetch.BlockedCycles 13819 # Number of cycles fetch has spent blocked
714system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
715system.cpu0.fetch.PendingTrapStallCycles 1570 # Number of stall cycles due to pending traps
716system.cpu0.fetch.CacheLines 5835 # Number of cache lines fetched
717system.cpu0.fetch.IcacheSquashes 493 # Number of outstanding Icache misses that were squashed
718system.cpu0.fetch.rateDist::samples 196760 # Number of instructions fetched each cycle (Total)
719system.cpu0.fetch.rateDist::mean 2.503197 # Number of instructions fetched each cycle (Total)
720system.cpu0.fetch.rateDist::stdev 2.215126 # Number of instructions fetched each cycle (Total)
721system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
722system.cpu0.fetch.rateDist::0 35083 17.83% 17.83% # Number of instructions fetched each cycle (Total)
723system.cpu0.fetch.rateDist::1 80084 40.70% 58.53% # Number of instructions fetched each cycle (Total)
724system.cpu0.fetch.rateDist::2 578 0.29% 58.83% # Number of instructions fetched each cycle (Total)
725system.cpu0.fetch.rateDist::3 973 0.49% 59.32% # Number of instructions fetched each cycle (Total)
726system.cpu0.fetch.rateDist::4 477 0.24% 59.56% # Number of instructions fetched each cycle (Total)
727system.cpu0.fetch.rateDist::5 76189 38.72% 98.28% # Number of instructions fetched each cycle (Total)
728system.cpu0.fetch.rateDist::6 571 0.29% 98.57% # Number of instructions fetched each cycle (Total)
729system.cpu0.fetch.rateDist::7 349 0.18% 98.75% # Number of instructions fetched each cycle (Total)
730system.cpu0.fetch.rateDist::8 2456 1.25% 100.00% # Number of instructions fetched each cycle (Total)
731system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
732system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
733system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
734system.cpu0.fetch.rateDist::total 196760 # Number of instructions fetched each cycle (Total)
735system.cpu0.fetch.branchRate 0.374496 # Number of branch fetches per cycle
736system.cpu0.fetch.rate 2.222503 # Number of inst fetches per cycle
737system.cpu0.decode.IdleCycles 17898 # Number of cycles decode is idle
738system.cpu0.decode.BlockedCycles 15432 # Number of cycles decode is blocked
739system.cpu0.decode.RunCycles 160701 # Number of cycles decode is running
740system.cpu0.decode.UnblockCycles 287 # Number of cycles decode is unblocking
741system.cpu0.decode.SquashCycles 2442 # Number of cycles decode is squashing
742system.cpu0.decode.DecodedInsts 489694 # Number of instructions handled by decode
743system.cpu0.rename.SquashCycles 2442 # Number of cycles rename is squashing
744system.cpu0.rename.IdleCycles 18563 # Number of cycles rename is idle
745system.cpu0.rename.BlockCycles 848 # Number of cycles rename is blocking
746system.cpu0.rename.serializeStallCycles 13994 # count of cycles rename stalled for serializing inst
747system.cpu0.rename.RunCycles 160355 # Number of cycles rename is running
748system.cpu0.rename.UnblockCycles 558 # Number of cycles rename is unblocking
749system.cpu0.rename.RenamedInsts 486837 # Number of instructions processed by rename
750system.cpu0.rename.LSQFullEvents 188 # Number of times rename has blocked due to LSQ full
751system.cpu0.rename.RenamedOperands 332900 # Number of destination operands rename has renamed
752system.cpu0.rename.RenameLookups 970872 # Number of register rename lookups that rename has made
753system.cpu0.rename.int_rename_lookups 733333 # Number of integer rename lookups
754system.cpu0.rename.CommittedMaps 319955 # Number of HB maps that are committed
755system.cpu0.rename.UndoneMaps 12945 # Number of HB maps that are undone due to squashing
756system.cpu0.rename.serializingInsts 867 # count of serializing insts renamed
757system.cpu0.rename.tempSerializingInsts 888 # count of temporary serializing insts renamed
758system.cpu0.rename.skidInsts 3605 # count of insts added to the skid buffer
759system.cpu0.memDep0.insertedLoads 155755 # Number of loads inserted to the mem dependence unit.
760system.cpu0.memDep0.insertedStores 78714 # Number of stores inserted to the mem dependence unit.
761system.cpu0.memDep0.conflictingLoads 75965 # Number of conflicting loads.
762system.cpu0.memDep0.conflictingStores 75781 # Number of conflicting stores.
763system.cpu0.iq.iqInstsAdded 407125 # Number of instructions added to the IQ (excludes non-spec)
764system.cpu0.iq.iqNonSpecInstsAdded 911 # Number of non-speculative instructions added to the IQ
765system.cpu0.iq.iqInstsIssued 404423 # Number of instructions issued
766system.cpu0.iq.iqSquashedInstsIssued 128 # Number of squashed instructions issued
767system.cpu0.iq.iqSquashedInstsExamined 10748 # Number of squashed instructions iterated over during squash; mainly for profiling
768system.cpu0.iq.iqSquashedOperandsExamined 9686 # Number of squashed operands that are examined and possibly removed from graph
769system.cpu0.iq.iqSquashedNonSpecRemoved 352 # Number of squashed non-spec instructions that were removed
770system.cpu0.iq.issued_per_cycle::samples 196760 # Number of insts issued each cycle
771system.cpu0.iq.issued_per_cycle::mean 2.055413 # Number of insts issued each cycle
772system.cpu0.iq.issued_per_cycle::stdev 1.097364 # Number of insts issued each cycle
773system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
774system.cpu0.iq.issued_per_cycle::0 34065 17.31% 17.31% # Number of insts issued each cycle
775system.cpu0.iq.issued_per_cycle::1 4908 2.49% 19.81% # Number of insts issued each cycle
776system.cpu0.iq.issued_per_cycle::2 77935 39.61% 59.42% # Number of insts issued each cycle
777system.cpu0.iq.issued_per_cycle::3 77266 39.27% 98.69% # Number of insts issued each cycle
778system.cpu0.iq.issued_per_cycle::4 1571 0.80% 99.48% # Number of insts issued each cycle
779system.cpu0.iq.issued_per_cycle::5 648 0.33% 99.81% # Number of insts issued each cycle
780system.cpu0.iq.issued_per_cycle::6 262 0.13% 99.95% # Number of insts issued each cycle
781system.cpu0.iq.issued_per_cycle::7 89 0.05% 99.99% # Number of insts issued each cycle
782system.cpu0.iq.issued_per_cycle::8 16 0.01% 100.00% # Number of insts issued each cycle
783system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
784system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
785system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
786system.cpu0.iq.issued_per_cycle::total 196760 # Number of insts issued each cycle
787system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
788system.cpu0.iq.fu_full::IntAlu 57 25.91% 25.91% # attempts to use FU when none available
789system.cpu0.iq.fu_full::IntMult 0 0.00% 25.91% # attempts to use FU when none available
790system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.91% # attempts to use FU when none available
791system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.91% # attempts to use FU when none available
792system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.91% # attempts to use FU when none available
793system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.91% # attempts to use FU when none available
794system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.91% # attempts to use FU when none available
795system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.91% # attempts to use FU when none available
796system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.91% # attempts to use FU when none available
797system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.91% # attempts to use FU when none available
798system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.91% # attempts to use FU when none available
799system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.91% # attempts to use FU when none available
800system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.91% # attempts to use FU when none available
801system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.91% # attempts to use FU when none available
802system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.91% # attempts to use FU when none available
803system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.91% # attempts to use FU when none available
804system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.91% # attempts to use FU when none available
805system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.91% # attempts to use FU when none available
806system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.91% # attempts to use FU when none available
807system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.91% # attempts to use FU when none available
808system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.91% # attempts to use FU when none available
809system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.91% # attempts to use FU when none available
810system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.91% # attempts to use FU when none available
811system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.91% # attempts to use FU when none available
812system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.91% # attempts to use FU when none available
813system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.91% # attempts to use FU when none available
814system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.91% # attempts to use FU when none available
815system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.91% # attempts to use FU when none available
816system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.91% # attempts to use FU when none available
817system.cpu0.iq.fu_full::MemRead 51 23.18% 49.09% # attempts to use FU when none available
818system.cpu0.iq.fu_full::MemWrite 112 50.91% 100.00% # attempts to use FU when none available
819system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
820system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
821system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
822system.cpu0.iq.FU_type_0::IntAlu 170994 42.28% 42.28% # Type of FU issued
823system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.28% # Type of FU issued
824system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.28% # Type of FU issued
825system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.28% # Type of FU issued
826system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.28% # Type of FU issued
827system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.28% # Type of FU issued
828system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.28% # Type of FU issued
829system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.28% # Type of FU issued
830system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.28% # Type of FU issued
831system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.28% # Type of FU issued
832system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.28% # Type of FU issued
833system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.28% # Type of FU issued
834system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.28% # Type of FU issued
835system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.28% # Type of FU issued
836system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.28% # Type of FU issued
837system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.28% # Type of FU issued
838system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.28% # Type of FU issued
839system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.28% # Type of FU issued
840system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.28% # Type of FU issued
841system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.28% # Type of FU issued
842system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.28% # Type of FU issued
843system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.28% # Type of FU issued
844system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.28% # Type of FU issued
845system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.28% # Type of FU issued
846system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.28% # Type of FU issued
847system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.28% # Type of FU issued
848system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.28% # Type of FU issued
849system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.28% # Type of FU issued
850system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.28% # Type of FU issued
851system.cpu0.iq.FU_type_0::MemRead 155300 38.40% 80.68% # Type of FU issued
852system.cpu0.iq.FU_type_0::MemWrite 78129 19.32% 100.00% # Type of FU issued
853system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
854system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
855system.cpu0.iq.FU_type_0::total 404423 # Type of FU issued
856system.cpu0.iq.rate 1.824931 # Inst issue rate
857system.cpu0.iq.fu_busy_cnt 220 # FU busy when requested
858system.cpu0.iq.fu_busy_rate 0.000544 # FU busy rate (busy events/executed inst)
859system.cpu0.iq.int_inst_queue_reads 1005954 # Number of integer instruction queue reads
860system.cpu0.iq.int_inst_queue_writes 418838 # Number of integer instruction queue writes
861system.cpu0.iq.int_inst_queue_wakeup_accesses 402603 # Number of integer instruction queue wakeup accesses
862system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
863system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
864system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
865system.cpu0.iq.int_alu_accesses 404643 # Number of integer alu accesses
866system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
867system.cpu0.iew.lsq.thread0.forwLoads 75498 # Number of loads that had data forwarded from stores
868system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
869system.cpu0.iew.lsq.thread0.squashedLoads 2188 # Number of loads squashed
870system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
871system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations
872system.cpu0.iew.lsq.thread0.squashedStores 1424 # Number of stores squashed
873system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
874system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
875system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
876system.cpu0.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked
877system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
878system.cpu0.iew.iewSquashCycles 2442 # Number of cycles IEW is squashing
879system.cpu0.iew.iewBlockCycles 391 # Number of cycles IEW is blocking
880system.cpu0.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking
881system.cpu0.iew.iewDispatchedInsts 484551 # Number of instructions dispatched to IQ
882system.cpu0.iew.iewDispSquashedInsts 313 # Number of squashed instructions skipped by dispatch
883system.cpu0.iew.iewDispLoadInsts 155755 # Number of dispatched load instructions
884system.cpu0.iew.iewDispStoreInsts 78714 # Number of dispatched store instructions
885system.cpu0.iew.iewDispNonSpecInsts 799 # Number of dispatched non-speculative instructions
886system.cpu0.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall
887system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
888system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations
889system.cpu0.iew.predictedTakenIncorrect 343 # Number of branches that were predicted taken incorrectly
890system.cpu0.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly
891system.cpu0.iew.branchMispredicts 1449 # Number of branch mispredicts detected at execute
892system.cpu0.iew.iewExecutedInsts 403352 # Number of executed instructions
893system.cpu0.iew.iewExecLoadInsts 154964 # Number of load instructions executed
894system.cpu0.iew.iewExecSquashedInsts 1071 # Number of squashed instructions skipped in execute
895system.cpu0.iew.exec_swp 0 # number of swp insts executed
896system.cpu0.iew.exec_nop 76515 # number of nop insts executed
897system.cpu0.iew.exec_refs 232993 # number of memory reference insts executed
898system.cpu0.iew.exec_branches 80132 # Number of branches executed
899system.cpu0.iew.exec_stores 78029 # Number of stores executed
900system.cpu0.iew.exec_rate 1.820098 # Inst execution rate
901system.cpu0.iew.wb_sent 402944 # cumulative count of insts sent to commit
902system.cpu0.iew.wb_count 402603 # cumulative count of insts written-back
903system.cpu0.iew.wb_producers 238549 # num instructions producing a value
904system.cpu0.iew.wb_consumers 241004 # num instructions consuming a value
905system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
906system.cpu0.iew.wb_rate 1.816719 # insts written-back per cycle
907system.cpu0.iew.wb_fanout 0.989813 # average fanout of values written-back
908system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
909system.cpu0.commit.commitSquashedInsts 12240 # The number of squashed insts skipped by commit
910system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
911system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted
912system.cpu0.commit.committed_per_cycle::samples 194318 # Number of insts commited each cycle
913system.cpu0.commit.committed_per_cycle::mean 2.430470 # Number of insts commited each cycle
914system.cpu0.commit.committed_per_cycle::stdev 2.136197 # Number of insts commited each cycle
915system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
916system.cpu0.commit.committed_per_cycle::0 34493 17.75% 17.75% # Number of insts commited each cycle
917system.cpu0.commit.committed_per_cycle::1 79895 41.12% 58.87% # Number of insts commited each cycle
918system.cpu0.commit.committed_per_cycle::2 2401 1.24% 60.10% # Number of insts commited each cycle
919system.cpu0.commit.committed_per_cycle::3 689 0.35% 60.46% # Number of insts commited each cycle
920system.cpu0.commit.committed_per_cycle::4 530 0.27% 60.73% # Number of insts commited each cycle
921system.cpu0.commit.committed_per_cycle::5 75316 38.76% 99.49% # Number of insts commited each cycle
922system.cpu0.commit.committed_per_cycle::6 445 0.23% 99.72% # Number of insts commited each cycle
923system.cpu0.commit.committed_per_cycle::7 242 0.12% 99.84% # Number of insts commited each cycle
924system.cpu0.commit.committed_per_cycle::8 307 0.16% 100.00% # Number of insts commited each cycle
925system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
926system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
927system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
928system.cpu0.commit.committed_per_cycle::total 194318 # Number of insts commited each cycle
929system.cpu0.commit.committedInsts 472284 # Number of instructions committed
930system.cpu0.commit.committedOps 472284 # Number of ops (including micro ops) committed
931system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
932system.cpu0.commit.refs 230857 # Number of memory references committed
933system.cpu0.commit.loads 153567 # Number of loads committed
934system.cpu0.commit.membars 84 # Number of memory barriers committed
935system.cpu0.commit.branches 79177 # Number of branches committed
936system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
937system.cpu0.commit.int_insts 318286 # Number of committed integer instructions.
938system.cpu0.commit.function_calls 223 # Number of function calls committed.
939system.cpu0.commit.bw_lim_events 307 # number cycles where commit BW limit reached
940system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
941system.cpu0.rob.rob_reads 677374 # The number of ROB reads
942system.cpu0.rob.rob_writes 971507 # The number of ROB writes
943system.cpu0.timesIdled 326 # Number of times that the entire CPU went into an idle state and unscheduled itself
944system.cpu0.idleCycles 24850 # Total number of cycles that the CPU has spent unscheduled due to idling
945system.cpu0.committedInsts 396291 # Number of Instructions Simulated
946system.cpu0.committedOps 396291 # Number of Ops (including micro ops) Simulated
947system.cpu0.committedInsts_total 396291 # Number of Instructions Simulated
948system.cpu0.cpi 0.559210 # CPI: Cycles Per Instruction
949system.cpu0.cpi_total 0.559210 # CPI: Total CPI of All Threads
950system.cpu0.ipc 1.788236 # IPC: Instructions Per Cycle
951system.cpu0.ipc_total 1.788236 # IPC: Total IPC of All Threads
952system.cpu0.int_regfile_reads 721592 # number of integer regfile reads
953system.cpu0.int_regfile_writes 325227 # number of integer regfile writes
954system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
955system.cpu0.misc_regfile_reads 234817 # number of misc regfile reads
956system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
957system.cpu0.icache.tags.replacements 297 # number of replacements
958system.cpu0.icache.tags.tagsinuse 241.148232 # Cycle average of tags in use
959system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks.
960system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks.
961system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks.
962system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
963system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.148232 # Average occupied blocks per requestor
964system.cpu0.icache.tags.occ_percent::cpu0.inst 0.470993 # Average percentage of cache occupancy
965system.cpu0.icache.tags.occ_percent::total 0.470993 # Average percentage of cache occupancy
966system.cpu0.icache.ReadReq_hits::cpu0.inst 5079 # number of ReadReq hits
967system.cpu0.icache.ReadReq_hits::total 5079 # number of ReadReq hits
968system.cpu0.icache.demand_hits::cpu0.inst 5079 # number of demand (read+write) hits
969system.cpu0.icache.demand_hits::total 5079 # number of demand (read+write) hits
970system.cpu0.icache.overall_hits::cpu0.inst 5079 # number of overall hits
971system.cpu0.icache.overall_hits::total 5079 # number of overall hits
972system.cpu0.icache.ReadReq_misses::cpu0.inst 756 # number of ReadReq misses
973system.cpu0.icache.ReadReq_misses::total 756 # number of ReadReq misses
974system.cpu0.icache.demand_misses::cpu0.inst 756 # number of demand (read+write) misses
975system.cpu0.icache.demand_misses::total 756 # number of demand (read+write) misses
976system.cpu0.icache.overall_misses::cpu0.inst 756 # number of overall misses
977system.cpu0.icache.overall_misses::total 756 # number of overall misses
978system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35147245 # number of ReadReq miss cycles
979system.cpu0.icache.ReadReq_miss_latency::total 35147245 # number of ReadReq miss cycles
980system.cpu0.icache.demand_miss_latency::cpu0.inst 35147245 # number of demand (read+write) miss cycles
981system.cpu0.icache.demand_miss_latency::total 35147245 # number of demand (read+write) miss cycles
982system.cpu0.icache.overall_miss_latency::cpu0.inst 35147245 # number of overall miss cycles
983system.cpu0.icache.overall_miss_latency::total 35147245 # number of overall miss cycles
984system.cpu0.icache.ReadReq_accesses::cpu0.inst 5835 # number of ReadReq accesses(hits+misses)
985system.cpu0.icache.ReadReq_accesses::total 5835 # number of ReadReq accesses(hits+misses)
986system.cpu0.icache.demand_accesses::cpu0.inst 5835 # number of demand (read+write) accesses
987system.cpu0.icache.demand_accesses::total 5835 # number of demand (read+write) accesses
988system.cpu0.icache.overall_accesses::cpu0.inst 5835 # number of overall (read+write) accesses
989system.cpu0.icache.overall_accesses::total 5835 # number of overall (read+write) accesses
990system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.129563 # miss rate for ReadReq accesses
991system.cpu0.icache.ReadReq_miss_rate::total 0.129563 # miss rate for ReadReq accesses
992system.cpu0.icache.demand_miss_rate::cpu0.inst 0.129563 # miss rate for demand accesses
993system.cpu0.icache.demand_miss_rate::total 0.129563 # miss rate for demand accesses
994system.cpu0.icache.overall_miss_rate::cpu0.inst 0.129563 # miss rate for overall accesses
995system.cpu0.icache.overall_miss_rate::total 0.129563 # miss rate for overall accesses
996system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46491.064815 # average ReadReq miss latency
997system.cpu0.icache.ReadReq_avg_miss_latency::total 46491.064815 # average ReadReq miss latency
998system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46491.064815 # average overall miss latency
999system.cpu0.icache.demand_avg_miss_latency::total 46491.064815 # average overall miss latency
1000system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46491.064815 # average overall miss latency
1001system.cpu0.icache.overall_avg_miss_latency::total 46491.064815 # average overall miss latency
1002system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1003system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1004system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1005system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
1006system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1007system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1008system.cpu0.icache.fast_writes 0 # number of fast writes performed
1009system.cpu0.icache.cache_copies 0 # number of cache copies performed

--- 4 unchanged lines hidden (view full) ---

1014system.cpu0.icache.overall_mshr_hits::cpu0.inst 168 # number of overall MSHR hits
1015system.cpu0.icache.overall_mshr_hits::total 168 # number of overall MSHR hits
1016system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 588 # number of ReadReq MSHR misses
1017system.cpu0.icache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses
1018system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 # number of demand (read+write) MSHR misses
1019system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses
1020system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses
1021system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses
1022system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27250252 # number of ReadReq MSHR miss cycles
1023system.cpu0.icache.ReadReq_mshr_miss_latency::total 27250252 # number of ReadReq MSHR miss cycles
1024system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27250252 # number of demand (read+write) MSHR miss cycles
1025system.cpu0.icache.demand_mshr_miss_latency::total 27250252 # number of demand (read+write) MSHR miss cycles
1026system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27250252 # number of overall MSHR miss cycles
1027system.cpu0.icache.overall_mshr_miss_latency::total 27250252 # number of overall MSHR miss cycles
1028system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for ReadReq accesses
1029system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100771 # mshr miss rate for ReadReq accesses
1030system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for demand accesses
1031system.cpu0.icache.demand_mshr_miss_rate::total 0.100771 # mshr miss rate for demand accesses
1032system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for overall accesses
1033system.cpu0.icache.overall_mshr_miss_rate::total 0.100771 # mshr miss rate for overall accesses
1034system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average ReadReq mshr miss latency
1035system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46343.965986 # average ReadReq mshr miss latency
1036system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average overall mshr miss latency
1037system.cpu0.icache.demand_avg_mshr_miss_latency::total 46343.965986 # average overall mshr miss latency
1038system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average overall mshr miss latency
1039system.cpu0.icache.overall_avg_mshr_miss_latency::total 46343.965986 # average overall mshr miss latency
1040system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1041system.cpu0.dcache.tags.replacements 2 # number of replacements
1042system.cpu0.dcache.tags.tagsinuse 141.869283 # Cycle average of tags in use
1043system.cpu0.dcache.tags.total_refs 155614 # Total number of references to valid blocks.
1044system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks.
1045system.cpu0.dcache.tags.avg_refs 915.376471 # Average number of references to valid blocks.
1046system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1047system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.869283 # Average occupied blocks per requestor
1048system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277088 # Average percentage of cache occupancy
1049system.cpu0.dcache.tags.occ_percent::total 0.277088 # Average percentage of cache occupancy
1050system.cpu0.dcache.ReadReq_hits::cpu0.data 78995 # number of ReadReq hits
1051system.cpu0.dcache.ReadReq_hits::total 78995 # number of ReadReq hits
1052system.cpu0.dcache.WriteReq_hits::cpu0.data 76703 # number of WriteReq hits
1053system.cpu0.dcache.WriteReq_hits::total 76703 # number of WriteReq hits
1054system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits
1055system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits
1056system.cpu0.dcache.demand_hits::cpu0.data 155698 # number of demand (read+write) hits
1057system.cpu0.dcache.demand_hits::total 155698 # number of demand (read+write) hits
1058system.cpu0.dcache.overall_hits::cpu0.data 155698 # number of overall hits
1059system.cpu0.dcache.overall_hits::total 155698 # number of overall hits
1060system.cpu0.dcache.ReadReq_misses::cpu0.data 410 # number of ReadReq misses
1061system.cpu0.dcache.ReadReq_misses::total 410 # number of ReadReq misses
1062system.cpu0.dcache.WriteReq_misses::cpu0.data 545 # number of WriteReq misses
1063system.cpu0.dcache.WriteReq_misses::total 545 # number of WriteReq misses
1064system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses
1065system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses
1066system.cpu0.dcache.demand_misses::cpu0.data 955 # number of demand (read+write) misses
1067system.cpu0.dcache.demand_misses::total 955 # number of demand (read+write) misses
1068system.cpu0.dcache.overall_misses::cpu0.data 955 # number of overall misses
1069system.cpu0.dcache.overall_misses::total 955 # number of overall misses
1070system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13319205 # number of ReadReq miss cycles
1071system.cpu0.dcache.ReadReq_miss_latency::total 13319205 # number of ReadReq miss cycles
1072system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35150505 # number of WriteReq miss cycles
1073system.cpu0.dcache.WriteReq_miss_latency::total 35150505 # number of WriteReq miss cycles
1074system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 418750 # number of SwapReq miss cycles
1075system.cpu0.dcache.SwapReq_miss_latency::total 418750 # number of SwapReq miss cycles
1076system.cpu0.dcache.demand_miss_latency::cpu0.data 48469710 # number of demand (read+write) miss cycles
1077system.cpu0.dcache.demand_miss_latency::total 48469710 # number of demand (read+write) miss cycles
1078system.cpu0.dcache.overall_miss_latency::cpu0.data 48469710 # number of overall miss cycles
1079system.cpu0.dcache.overall_miss_latency::total 48469710 # number of overall miss cycles
1080system.cpu0.dcache.ReadReq_accesses::cpu0.data 79405 # number of ReadReq accesses(hits+misses)
1081system.cpu0.dcache.ReadReq_accesses::total 79405 # number of ReadReq accesses(hits+misses)
1082system.cpu0.dcache.WriteReq_accesses::cpu0.data 77248 # number of WriteReq accesses(hits+misses)
1083system.cpu0.dcache.WriteReq_accesses::total 77248 # number of WriteReq accesses(hits+misses)
1084system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
1085system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
1086system.cpu0.dcache.demand_accesses::cpu0.data 156653 # number of demand (read+write) accesses
1087system.cpu0.dcache.demand_accesses::total 156653 # number of demand (read+write) accesses
1088system.cpu0.dcache.overall_accesses::cpu0.data 156653 # number of overall (read+write) accesses
1089system.cpu0.dcache.overall_accesses::total 156653 # number of overall (read+write) accesses
1090system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005163 # miss rate for ReadReq accesses
1091system.cpu0.dcache.ReadReq_miss_rate::total 0.005163 # miss rate for ReadReq accesses
1092system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007055 # miss rate for WriteReq accesses
1093system.cpu0.dcache.WriteReq_miss_rate::total 0.007055 # miss rate for WriteReq accesses
1094system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses
1095system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses
1096system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006096 # miss rate for demand accesses
1097system.cpu0.dcache.demand_miss_rate::total 0.006096 # miss rate for demand accesses
1098system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006096 # miss rate for overall accesses
1099system.cpu0.dcache.overall_miss_rate::total 0.006096 # miss rate for overall accesses
1100system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32485.865854 # average ReadReq miss latency
1101system.cpu0.dcache.ReadReq_avg_miss_latency::total 32485.865854 # average ReadReq miss latency
1102system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64496.339450 # average WriteReq miss latency
1103system.cpu0.dcache.WriteReq_avg_miss_latency::total 64496.339450 # average WriteReq miss latency
1104system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19940.476190 # average SwapReq miss latency
1105system.cpu0.dcache.SwapReq_avg_miss_latency::total 19940.476190 # average SwapReq miss latency
1106system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50753.623037 # average overall miss latency
1107system.cpu0.dcache.demand_avg_miss_latency::total 50753.623037 # average overall miss latency
1108system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50753.623037 # average overall miss latency
1109system.cpu0.dcache.overall_avg_miss_latency::total 50753.623037 # average overall miss latency
1110system.cpu0.dcache.blocked_cycles::no_mshrs 503 # number of cycles access was blocked
1111system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1112system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked
1113system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
1114system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.952381 # average number of cycles each access was blocked
1115system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1116system.cpu0.dcache.fast_writes 0 # number of fast writes performed
1117system.cpu0.dcache.cache_copies 0 # number of cache copies performed
1118system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
1119system.cpu0.dcache.writebacks::total 1 # number of writebacks
1120system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 223 # number of ReadReq MSHR hits
1121system.cpu0.dcache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits
1122system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits
1123system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits
1124system.cpu0.dcache.demand_mshr_hits::cpu0.data 593 # number of demand (read+write) MSHR hits
1125system.cpu0.dcache.demand_mshr_hits::total 593 # number of demand (read+write) MSHR hits
1126system.cpu0.dcache.overall_mshr_hits::cpu0.data 593 # number of overall MSHR hits
1127system.cpu0.dcache.overall_mshr_hits::total 593 # number of overall MSHR hits
1128system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 187 # number of ReadReq MSHR misses
1129system.cpu0.dcache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses
1130system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses
1131system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses
1132system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses
1133system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses
1134system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses
1135system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses
1136system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses
1137system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses
1138system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6285007 # number of ReadReq MSHR miss cycles
1139system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6285007 # number of ReadReq MSHR miss cycles
1140system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7788228 # number of WriteReq MSHR miss cycles
1141system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7788228 # number of WriteReq MSHR miss cycles
1142system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 375250 # number of SwapReq MSHR miss cycles
1143system.cpu0.dcache.SwapReq_mshr_miss_latency::total 375250 # number of SwapReq MSHR miss cycles
1144system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 14073235 # number of demand (read+write) MSHR miss cycles
1145system.cpu0.dcache.demand_mshr_miss_latency::total 14073235 # number of demand (read+write) MSHR miss cycles
1146system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14073235 # number of overall MSHR miss cycles
1147system.cpu0.dcache.overall_mshr_miss_latency::total 14073235 # number of overall MSHR miss cycles
1148system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002355 # mshr miss rate for ReadReq accesses
1149system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses
1150system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002265 # mshr miss rate for WriteReq accesses
1151system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002265 # mshr miss rate for WriteReq accesses
1152system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses
1153system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses
1154system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002311 # mshr miss rate for demand accesses
1155system.cpu0.dcache.demand_mshr_miss_rate::total 0.002311 # mshr miss rate for demand accesses
1156system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002311 # mshr miss rate for overall accesses
1157system.cpu0.dcache.overall_mshr_miss_rate::total 0.002311 # mshr miss rate for overall accesses
1158system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 33609.663102 # average ReadReq mshr miss latency
1159system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 33609.663102 # average ReadReq mshr miss latency
1160system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44504.160000 # average WriteReq mshr miss latency
1161system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44504.160000 # average WriteReq mshr miss latency
1162system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17869.047619 # average SwapReq mshr miss latency
1163system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17869.047619 # average SwapReq mshr miss latency
1164system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 38876.339779 # average overall mshr miss latency
1165system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38876.339779 # average overall mshr miss latency
1166system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38876.339779 # average overall mshr miss latency
1167system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38876.339779 # average overall mshr miss latency
1168system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1169system.cpu1.branchPred.lookups 43495 # Number of BP lookups
1170system.cpu1.branchPred.condPredicted 40766 # Number of conditional branches predicted
1171system.cpu1.branchPred.condIncorrect 1279 # Number of conditional branches incorrect
1172system.cpu1.branchPred.BTBLookups 37360 # Number of BTB lookups
1173system.cpu1.branchPred.BTBHits 36580 # Number of BTB hits
1174system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1175system.cpu1.branchPred.BTBHitPct 97.912206 # BTB Hit Percentage
1176system.cpu1.branchPred.usedRAS 665 # Number of times the RAS was used to get a target.
1177system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
1178system.cpu1.numCycles 177681 # number of cpu cycles simulated
1179system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1180system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1181system.cpu1.fetch.icacheStallCycles 34028 # Number of cycles fetch is stalled on an Icache miss
1182system.cpu1.fetch.Insts 233746 # Number of instructions fetch has processed
1183system.cpu1.fetch.Branches 43495 # Number of branches that fetch encountered
1184system.cpu1.fetch.predictedBranches 37245 # Number of branches that fetch has predicted taken
1185system.cpu1.fetch.Cycles 88254 # Number of cycles fetch has run and was not squashing or blocked
1186system.cpu1.fetch.SquashCycles 3762 # Number of cycles fetch has spent squashing
1187system.cpu1.fetch.BlockedCycles 42089 # Number of cycles fetch has spent blocked
1188system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1189system.cpu1.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from
1190system.cpu1.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps
1191system.cpu1.fetch.CacheLines 25656 # Number of cache lines fetched
1192system.cpu1.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed
1193system.cpu1.fetch.rateDist::samples 175306 # Number of instructions fetched each cycle (Total)
1194system.cpu1.fetch.rateDist::mean 1.333360 # Number of instructions fetched each cycle (Total)
1195system.cpu1.fetch.rateDist::stdev 1.985884 # Number of instructions fetched each cycle (Total)
1196system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1197system.cpu1.fetch.rateDist::0 87052 49.66% 49.66% # Number of instructions fetched each cycle (Total)
1198system.cpu1.fetch.rateDist::1 46435 26.49% 76.15% # Number of instructions fetched each cycle (Total)
1199system.cpu1.fetch.rateDist::2 9084 5.18% 81.33% # Number of instructions fetched each cycle (Total)
1200system.cpu1.fetch.rateDist::3 3194 1.82% 83.15% # Number of instructions fetched each cycle (Total)
1201system.cpu1.fetch.rateDist::4 686 0.39% 83.54% # Number of instructions fetched each cycle (Total)
1202system.cpu1.fetch.rateDist::5 23635 13.48% 97.02% # Number of instructions fetched each cycle (Total)
1203system.cpu1.fetch.rateDist::6 1173 0.67% 97.69% # Number of instructions fetched each cycle (Total)
1204system.cpu1.fetch.rateDist::7 772 0.44% 98.13% # Number of instructions fetched each cycle (Total)
1205system.cpu1.fetch.rateDist::8 3275 1.87% 100.00% # Number of instructions fetched each cycle (Total)
1206system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1207system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1208system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
1209system.cpu1.fetch.rateDist::total 175306 # Number of instructions fetched each cycle (Total)
1210system.cpu1.fetch.branchRate 0.244793 # Number of branch fetches per cycle
1211system.cpu1.fetch.rate 1.315537 # Number of inst fetches per cycle
1212system.cpu1.decode.IdleCycles 41969 # Number of cycles decode is idle
1213system.cpu1.decode.BlockedCycles 35783 # Number of cycles decode is blocked
1214system.cpu1.decode.RunCycles 79597 # Number of cycles decode is running
1215system.cpu1.decode.UnblockCycles 7812 # Number of cycles decode is unblocking
1216system.cpu1.decode.SquashCycles 2406 # Number of cycles decode is squashing
1217system.cpu1.decode.DecodedInsts 230200 # Number of instructions handled by decode
1218system.cpu1.rename.SquashCycles 2406 # Number of cycles rename is squashing
1219system.cpu1.rename.IdleCycles 42677 # Number of cycles rename is idle
1220system.cpu1.rename.BlockCycles 23059 # Number of cycles rename is blocking
1221system.cpu1.rename.serializeStallCycles 11946 # count of cycles rename stalled for serializing inst
1222system.cpu1.rename.RunCycles 72053 # Number of cycles rename is running
1223system.cpu1.rename.UnblockCycles 15426 # Number of cycles rename is unblocking
1224system.cpu1.rename.RenamedInsts 227940 # Number of instructions processed by rename
1225system.cpu1.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
1226system.cpu1.rename.LSQFullEvents 19 # Number of times rename has blocked due to LSQ full
1227system.cpu1.rename.RenamedOperands 156532 # Number of destination operands rename has renamed
1228system.cpu1.rename.RenameLookups 420697 # Number of register rename lookups that rename has made
1229system.cpu1.rename.int_rename_lookups 330316 # Number of integer rename lookups
1230system.cpu1.rename.CommittedMaps 143693 # Number of HB maps that are committed
1231system.cpu1.rename.UndoneMaps 12839 # Number of HB maps that are undone due to squashing
1232system.cpu1.rename.serializingInsts 1114 # count of serializing insts renamed
1233system.cpu1.rename.tempSerializingInsts 1240 # count of temporary serializing insts renamed
1234system.cpu1.rename.skidInsts 18203 # count of insts added to the skid buffer
1235system.cpu1.memDep0.insertedLoads 60713 # Number of loads inserted to the mem dependence unit.
1236system.cpu1.memDep0.insertedStores 26873 # Number of stores inserted to the mem dependence unit.
1237system.cpu1.memDep0.conflictingLoads 30033 # Number of conflicting loads.
1238system.cpu1.memDep0.conflictingStores 21821 # Number of conflicting stores.
1239system.cpu1.iq.iqInstsAdded 184781 # Number of instructions added to the IQ (excludes non-spec)
1240system.cpu1.iq.iqNonSpecInstsAdded 9329 # Number of non-speculative instructions added to the IQ
1241system.cpu1.iq.iqInstsIssued 189617 # Number of instructions issued
1242system.cpu1.iq.iqSquashedInstsIssued 108 # Number of squashed instructions issued
1243system.cpu1.iq.iqSquashedInstsExamined 10957 # Number of squashed instructions iterated over during squash; mainly for profiling
1244system.cpu1.iq.iqSquashedOperandsExamined 10934 # Number of squashed operands that are examined and possibly removed from graph
1245system.cpu1.iq.iqSquashedNonSpecRemoved 690 # Number of squashed non-spec instructions that were removed
1246system.cpu1.iq.issued_per_cycle::samples 175306 # Number of insts issued each cycle
1247system.cpu1.iq.issued_per_cycle::mean 1.081634 # Number of insts issued each cycle
1248system.cpu1.iq.issued_per_cycle::stdev 1.264768 # Number of insts issued each cycle
1249system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1250system.cpu1.iq.issued_per_cycle::0 84668 48.30% 48.30% # Number of insts issued each cycle
1251system.cpu1.iq.issued_per_cycle::1 30997 17.68% 65.98% # Number of insts issued each cycle
1252system.cpu1.iq.issued_per_cycle::2 27119 15.47% 81.45% # Number of insts issued each cycle
1253system.cpu1.iq.issued_per_cycle::3 27768 15.84% 97.29% # Number of insts issued each cycle
1254system.cpu1.iq.issued_per_cycle::4 3226 1.84% 99.13% # Number of insts issued each cycle
1255system.cpu1.iq.issued_per_cycle::5 1160 0.66% 99.79% # Number of insts issued each cycle
1256system.cpu1.iq.issued_per_cycle::6 259 0.15% 99.94% # Number of insts issued each cycle
1257system.cpu1.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle
1258system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle
1259system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1260system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1261system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
1262system.cpu1.iq.issued_per_cycle::total 175306 # Number of insts issued each cycle
1263system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1264system.cpu1.iq.fu_full::IntAlu 12 4.55% 4.55% # attempts to use FU when none available
1265system.cpu1.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available
1266system.cpu1.iq.fu_full::IntDiv 0 0.00% 4.55% # attempts to use FU when none available
1267system.cpu1.iq.fu_full::FloatAdd 0 0.00% 4.55% # attempts to use FU when none available
1268system.cpu1.iq.fu_full::FloatCmp 0 0.00% 4.55% # attempts to use FU when none available
1269system.cpu1.iq.fu_full::FloatCvt 0 0.00% 4.55% # attempts to use FU when none available
1270system.cpu1.iq.fu_full::FloatMult 0 0.00% 4.55% # attempts to use FU when none available
1271system.cpu1.iq.fu_full::FloatDiv 0 0.00% 4.55% # attempts to use FU when none available
1272system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 4.55% # attempts to use FU when none available
1273system.cpu1.iq.fu_full::SimdAdd 0 0.00% 4.55% # attempts to use FU when none available
1274system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 4.55% # attempts to use FU when none available
1275system.cpu1.iq.fu_full::SimdAlu 0 0.00% 4.55% # attempts to use FU when none available
1276system.cpu1.iq.fu_full::SimdCmp 0 0.00% 4.55% # attempts to use FU when none available
1277system.cpu1.iq.fu_full::SimdCvt 0 0.00% 4.55% # attempts to use FU when none available
1278system.cpu1.iq.fu_full::SimdMisc 0 0.00% 4.55% # attempts to use FU when none available
1279system.cpu1.iq.fu_full::SimdMult 0 0.00% 4.55% # attempts to use FU when none available
1280system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 4.55% # attempts to use FU when none available
1281system.cpu1.iq.fu_full::SimdShift 0 0.00% 4.55% # attempts to use FU when none available
1282system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 4.55% # attempts to use FU when none available
1283system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 4.55% # attempts to use FU when none available
1284system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 4.55% # attempts to use FU when none available
1285system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 4.55% # attempts to use FU when none available
1286system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 4.55% # attempts to use FU when none available
1287system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 4.55% # attempts to use FU when none available
1288system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 4.55% # attempts to use FU when none available
1289system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 4.55% # attempts to use FU when none available
1290system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 4.55% # attempts to use FU when none available
1291system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.55% # attempts to use FU when none available
1292system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 4.55% # attempts to use FU when none available
1293system.cpu1.iq.fu_full::MemRead 42 15.91% 20.45% # attempts to use FU when none available
1294system.cpu1.iq.fu_full::MemWrite 210 79.55% 100.00% # attempts to use FU when none available
1295system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1296system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1297system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
1298system.cpu1.iq.FU_type_0::IntAlu 95616 50.43% 50.43% # Type of FU issued
1299system.cpu1.iq.FU_type_0::IntMult 0 0.00% 50.43% # Type of FU issued
1300system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 50.43% # Type of FU issued
1301system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 50.43% # Type of FU issued
1302system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 50.43% # Type of FU issued
1303system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 50.43% # Type of FU issued
1304system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 50.43% # Type of FU issued
1305system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 50.43% # Type of FU issued
1306system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 50.43% # Type of FU issued
1307system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 50.43% # Type of FU issued
1308system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 50.43% # Type of FU issued
1309system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 50.43% # Type of FU issued
1310system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 50.43% # Type of FU issued
1311system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 50.43% # Type of FU issued
1312system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 50.43% # Type of FU issued
1313system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 50.43% # Type of FU issued
1314system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 50.43% # Type of FU issued
1315system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 50.43% # Type of FU issued
1316system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.43% # Type of FU issued
1317system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 50.43% # Type of FU issued
1318system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.43% # Type of FU issued
1319system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.43% # Type of FU issued
1320system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.43% # Type of FU issued
1321system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.43% # Type of FU issued
1322system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.43% # Type of FU issued
1323system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.43% # Type of FU issued
1324system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 50.43% # Type of FU issued
1325system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.43% # Type of FU issued
1326system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.43% # Type of FU issued
1327system.cpu1.iq.FU_type_0::MemRead 67820 35.77% 86.19% # Type of FU issued
1328system.cpu1.iq.FU_type_0::MemWrite 26181 13.81% 100.00% # Type of FU issued
1329system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1330system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1331system.cpu1.iq.FU_type_0::total 189617 # Type of FU issued
1332system.cpu1.iq.rate 1.067177 # Inst issue rate
1333system.cpu1.iq.fu_busy_cnt 264 # FU busy when requested
1334system.cpu1.iq.fu_busy_rate 0.001392 # FU busy rate (busy events/executed inst)
1335system.cpu1.iq.int_inst_queue_reads 554912 # Number of integer instruction queue reads
1336system.cpu1.iq.int_inst_queue_writes 205110 # Number of integer instruction queue writes
1337system.cpu1.iq.int_inst_queue_wakeup_accesses 187814 # Number of integer instruction queue wakeup accesses
1338system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
1339system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
1340system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
1341system.cpu1.iq.int_alu_accesses 189881 # Number of integer alu accesses
1342system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
1343system.cpu1.iew.lsq.thread0.forwLoads 21562 # Number of loads that had data forwarded from stores
1344system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1345system.cpu1.iew.lsq.thread0.squashedLoads 2474 # Number of loads squashed
1346system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
1347system.cpu1.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations
1348system.cpu1.iew.lsq.thread0.squashedStores 1439 # Number of stores squashed
1349system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1350system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1351system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
1352system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
1353system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1354system.cpu1.iew.iewSquashCycles 2406 # Number of cycles IEW is squashing
1355system.cpu1.iew.iewBlockCycles 736 # Number of cycles IEW is blocking
1356system.cpu1.iew.iewUnblockCycles 43 # Number of cycles IEW is unblocking
1357system.cpu1.iew.iewDispatchedInsts 225068 # Number of instructions dispatched to IQ
1358system.cpu1.iew.iewDispSquashedInsts 373 # Number of squashed instructions skipped by dispatch
1359system.cpu1.iew.iewDispLoadInsts 60713 # Number of dispatched load instructions
1360system.cpu1.iew.iewDispStoreInsts 26873 # Number of dispatched store instructions
1361system.cpu1.iew.iewDispNonSpecInsts 1076 # Number of dispatched non-speculative instructions
1362system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall
1363system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
1364system.cpu1.iew.memOrderViolationEvents 43 # Number of memory order violations
1365system.cpu1.iew.predictedTakenIncorrect 453 # Number of branches that were predicted taken incorrectly
1366system.cpu1.iew.predictedNotTakenIncorrect 939 # Number of branches that were predicted not taken incorrectly
1367system.cpu1.iew.branchMispredicts 1392 # Number of branch mispredicts detected at execute
1368system.cpu1.iew.iewExecutedInsts 188449 # Number of executed instructions
1369system.cpu1.iew.iewExecLoadInsts 59619 # Number of load instructions executed
1370system.cpu1.iew.iewExecSquashedInsts 1168 # Number of squashed instructions skipped in execute
1371system.cpu1.iew.exec_swp 0 # number of swp insts executed
1372system.cpu1.iew.exec_nop 30958 # number of nop insts executed
1373system.cpu1.iew.exec_refs 85720 # number of memory reference insts executed
1374system.cpu1.iew.exec_branches 40129 # Number of branches executed
1375system.cpu1.iew.exec_stores 26101 # Number of stores executed
1376system.cpu1.iew.exec_rate 1.060603 # Inst execution rate
1377system.cpu1.iew.wb_sent 188127 # cumulative count of insts sent to commit
1378system.cpu1.iew.wb_count 187814 # cumulative count of insts written-back
1379system.cpu1.iew.wb_producers 102456 # num instructions producing a value
1380system.cpu1.iew.wb_consumers 107134 # num instructions consuming a value
1381system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1382system.cpu1.iew.wb_rate 1.057029 # insts written-back per cycle
1383system.cpu1.iew.wb_fanout 0.956335 # average fanout of values written-back
1384system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1385system.cpu1.commit.commitSquashedInsts 12618 # The number of squashed insts skipped by commit
1386system.cpu1.commit.commitNonSpecStalls 8639 # The number of times commit has been forced to stall to communicate backwards
1387system.cpu1.commit.branchMispredicts 1279 # The number of times a branch was mispredicted
1388system.cpu1.commit.committed_per_cycle::samples 165161 # Number of insts commited each cycle
1389system.cpu1.commit.committed_per_cycle::mean 1.286212 # Number of insts commited each cycle
1390system.cpu1.commit.committed_per_cycle::stdev 1.860966 # Number of insts commited each cycle
1391system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1392system.cpu1.commit.committed_per_cycle::0 85256 51.62% 51.62% # Number of insts commited each cycle
1393system.cpu1.commit.committed_per_cycle::1 38272 23.17% 74.79% # Number of insts commited each cycle
1394system.cpu1.commit.committed_per_cycle::2 6084 3.68% 78.48% # Number of insts commited each cycle
1395system.cpu1.commit.committed_per_cycle::3 9527 5.77% 84.24% # Number of insts commited each cycle
1396system.cpu1.commit.committed_per_cycle::4 1571 0.95% 85.20% # Number of insts commited each cycle
1397system.cpu1.commit.committed_per_cycle::5 22201 13.44% 98.64% # Number of insts commited each cycle
1398system.cpu1.commit.committed_per_cycle::6 436 0.26% 98.90% # Number of insts commited each cycle
1399system.cpu1.commit.committed_per_cycle::7 1006 0.61% 99.51% # Number of insts commited each cycle
1400system.cpu1.commit.committed_per_cycle::8 808 0.49% 100.00% # Number of insts commited each cycle
1401system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1402system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1403system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1404system.cpu1.commit.committed_per_cycle::total 165161 # Number of insts commited each cycle
1405system.cpu1.commit.committedInsts 212432 # Number of instructions committed
1406system.cpu1.commit.committedOps 212432 # Number of ops (including micro ops) committed
1407system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
1408system.cpu1.commit.refs 83673 # Number of memory references committed
1409system.cpu1.commit.loads 58239 # Number of loads committed
1410system.cpu1.commit.membars 7917 # Number of memory barriers committed
1411system.cpu1.commit.branches 39308 # Number of branches committed
1412system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
1413system.cpu1.commit.int_insts 145097 # Number of committed integer instructions.
1414system.cpu1.commit.function_calls 322 # Number of function calls committed.
1415system.cpu1.commit.bw_lim_events 808 # number cycles where commit BW limit reached
1416system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
1417system.cpu1.rob.rob_reads 388816 # The number of ROB reads
1418system.cpu1.rob.rob_writes 452512 # The number of ROB writes
1419system.cpu1.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself
1420system.cpu1.idleCycles 2375 # Total number of cycles that the CPU has spent unscheduled due to idling
1421system.cpu1.quiesceCycles 43927 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1422system.cpu1.committedInsts 174425 # Number of Instructions Simulated
1423system.cpu1.committedOps 174425 # Number of Ops (including micro ops) Simulated
1424system.cpu1.committedInsts_total 174425 # Number of Instructions Simulated
1425system.cpu1.cpi 1.018667 # CPI: Cycles Per Instruction
1426system.cpu1.cpi_total 1.018667 # CPI: Total CPI of All Threads
1427system.cpu1.ipc 0.981675 # IPC: Instructions Per Cycle
1428system.cpu1.ipc_total 0.981675 # IPC: Total IPC of All Threads
1429system.cpu1.int_regfile_reads 315718 # number of integer regfile reads
1430system.cpu1.int_regfile_writes 148477 # number of integer regfile writes
1431system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
1432system.cpu1.misc_regfile_reads 87269 # number of misc regfile reads
1433system.cpu1.misc_regfile_writes 648 # number of misc regfile writes
1434system.cpu1.icache.tags.replacements 318 # number of replacements
1435system.cpu1.icache.tags.tagsinuse 79.958659 # Cycle average of tags in use
1436system.cpu1.icache.tags.total_refs 25178 # Total number of references to valid blocks.
1437system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks.
1438system.cpu1.icache.tags.avg_refs 58.827103 # Average number of references to valid blocks.
1439system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1440system.cpu1.icache.tags.occ_blocks::cpu1.inst 79.958659 # Average occupied blocks per requestor
1441system.cpu1.icache.tags.occ_percent::cpu1.inst 0.156169 # Average percentage of cache occupancy
1442system.cpu1.icache.tags.occ_percent::total 0.156169 # Average percentage of cache occupancy
1443system.cpu1.icache.ReadReq_hits::cpu1.inst 25178 # number of ReadReq hits
1444system.cpu1.icache.ReadReq_hits::total 25178 # number of ReadReq hits
1445system.cpu1.icache.demand_hits::cpu1.inst 25178 # number of demand (read+write) hits
1446system.cpu1.icache.demand_hits::total 25178 # number of demand (read+write) hits
1447system.cpu1.icache.overall_hits::cpu1.inst 25178 # number of overall hits
1448system.cpu1.icache.overall_hits::total 25178 # number of overall hits
1449system.cpu1.icache.ReadReq_misses::cpu1.inst 478 # number of ReadReq misses
1450system.cpu1.icache.ReadReq_misses::total 478 # number of ReadReq misses
1451system.cpu1.icache.demand_misses::cpu1.inst 478 # number of demand (read+write) misses
1452system.cpu1.icache.demand_misses::total 478 # number of demand (read+write) misses
1453system.cpu1.icache.overall_misses::cpu1.inst 478 # number of overall misses
1454system.cpu1.icache.overall_misses::total 478 # number of overall misses
1455system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7224243 # number of ReadReq miss cycles
1456system.cpu1.icache.ReadReq_miss_latency::total 7224243 # number of ReadReq miss cycles
1457system.cpu1.icache.demand_miss_latency::cpu1.inst 7224243 # number of demand (read+write) miss cycles
1458system.cpu1.icache.demand_miss_latency::total 7224243 # number of demand (read+write) miss cycles
1459system.cpu1.icache.overall_miss_latency::cpu1.inst 7224243 # number of overall miss cycles
1460system.cpu1.icache.overall_miss_latency::total 7224243 # number of overall miss cycles
1461system.cpu1.icache.ReadReq_accesses::cpu1.inst 25656 # number of ReadReq accesses(hits+misses)
1462system.cpu1.icache.ReadReq_accesses::total 25656 # number of ReadReq accesses(hits+misses)
1463system.cpu1.icache.demand_accesses::cpu1.inst 25656 # number of demand (read+write) accesses
1464system.cpu1.icache.demand_accesses::total 25656 # number of demand (read+write) accesses
1465system.cpu1.icache.overall_accesses::cpu1.inst 25656 # number of overall (read+write) accesses
1466system.cpu1.icache.overall_accesses::total 25656 # number of overall (read+write) accesses
1467system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018631 # miss rate for ReadReq accesses
1468system.cpu1.icache.ReadReq_miss_rate::total 0.018631 # miss rate for ReadReq accesses
1469system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018631 # miss rate for demand accesses
1470system.cpu1.icache.demand_miss_rate::total 0.018631 # miss rate for demand accesses
1471system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018631 # miss rate for overall accesses
1472system.cpu1.icache.overall_miss_rate::total 0.018631 # miss rate for overall accesses
1473system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15113.479079 # average ReadReq miss latency
1474system.cpu1.icache.ReadReq_avg_miss_latency::total 15113.479079 # average ReadReq miss latency
1475system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15113.479079 # average overall miss latency
1476system.cpu1.icache.demand_avg_miss_latency::total 15113.479079 # average overall miss latency
1477system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15113.479079 # average overall miss latency
1478system.cpu1.icache.overall_avg_miss_latency::total 15113.479079 # average overall miss latency
1479system.cpu1.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked
1480system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1481system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked
1482system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1483system.cpu1.icache.avg_blocked_cycles::no_mshrs 13 # average number of cycles each access was blocked
1484system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1485system.cpu1.icache.fast_writes 0 # number of fast writes performed
1486system.cpu1.icache.cache_copies 0 # number of cache copies performed
1487system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 50 # number of ReadReq MSHR hits
1488system.cpu1.icache.ReadReq_mshr_hits::total 50 # number of ReadReq MSHR hits
1489system.cpu1.icache.demand_mshr_hits::cpu1.inst 50 # number of demand (read+write) MSHR hits
1490system.cpu1.icache.demand_mshr_hits::total 50 # number of demand (read+write) MSHR hits
1491system.cpu1.icache.overall_mshr_hits::cpu1.inst 50 # number of overall MSHR hits
1492system.cpu1.icache.overall_mshr_hits::total 50 # number of overall MSHR hits
1493system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 428 # number of ReadReq MSHR misses
1494system.cpu1.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses
1495system.cpu1.icache.demand_mshr_misses::cpu1.inst 428 # number of demand (read+write) MSHR misses
1496system.cpu1.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses
1497system.cpu1.icache.overall_mshr_misses::cpu1.inst 428 # number of overall MSHR misses
1498system.cpu1.icache.overall_mshr_misses::total 428 # number of overall MSHR misses
1499system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5769006 # number of ReadReq MSHR miss cycles
1500system.cpu1.icache.ReadReq_mshr_miss_latency::total 5769006 # number of ReadReq MSHR miss cycles
1501system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5769006 # number of demand (read+write) MSHR miss cycles
1502system.cpu1.icache.demand_mshr_miss_latency::total 5769006 # number of demand (read+write) MSHR miss cycles
1503system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5769006 # number of overall MSHR miss cycles
1504system.cpu1.icache.overall_mshr_miss_latency::total 5769006 # number of overall MSHR miss cycles
1505system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for ReadReq accesses
1506system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016682 # mshr miss rate for ReadReq accesses
1507system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for demand accesses
1508system.cpu1.icache.demand_mshr_miss_rate::total 0.016682 # mshr miss rate for demand accesses
1509system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for overall accesses
1510system.cpu1.icache.overall_mshr_miss_rate::total 0.016682 # mshr miss rate for overall accesses
1511system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average ReadReq mshr miss latency
1512system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13478.985981 # average ReadReq mshr miss latency
1513system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency
1514system.cpu1.icache.demand_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency
1515system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency
1516system.cpu1.icache.overall_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency
1517system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1518system.cpu1.dcache.tags.replacements 0 # number of replacements
1519system.cpu1.dcache.tags.tagsinuse 24.742100 # Cycle average of tags in use
1520system.cpu1.dcache.tags.total_refs 31558 # Total number of references to valid blocks.
1521system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
1522system.cpu1.dcache.tags.avg_refs 1088.206897 # Average number of references to valid blocks.
1523system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1524system.cpu1.dcache.tags.occ_blocks::cpu1.data 24.742100 # Average occupied blocks per requestor
1525system.cpu1.dcache.tags.occ_percent::cpu1.data 0.048324 # Average percentage of cache occupancy
1526system.cpu1.dcache.tags.occ_percent::total 0.048324 # Average percentage of cache occupancy
1527system.cpu1.dcache.ReadReq_hits::cpu1.data 37722 # number of ReadReq hits
1528system.cpu1.dcache.ReadReq_hits::total 37722 # number of ReadReq hits
1529system.cpu1.dcache.WriteReq_hits::cpu1.data 25226 # number of WriteReq hits
1530system.cpu1.dcache.WriteReq_hits::total 25226 # number of WriteReq hits
1531system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits
1532system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits
1533system.cpu1.dcache.demand_hits::cpu1.data 62948 # number of demand (read+write) hits
1534system.cpu1.dcache.demand_hits::total 62948 # number of demand (read+write) hits
1535system.cpu1.dcache.overall_hits::cpu1.data 62948 # number of overall hits
1536system.cpu1.dcache.overall_hits::total 62948 # number of overall hits
1537system.cpu1.dcache.ReadReq_misses::cpu1.data 319 # number of ReadReq misses
1538system.cpu1.dcache.ReadReq_misses::total 319 # number of ReadReq misses
1539system.cpu1.dcache.WriteReq_misses::cpu1.data 132 # number of WriteReq misses
1540system.cpu1.dcache.WriteReq_misses::total 132 # number of WriteReq misses
1541system.cpu1.dcache.SwapReq_misses::cpu1.data 60 # number of SwapReq misses
1542system.cpu1.dcache.SwapReq_misses::total 60 # number of SwapReq misses
1543system.cpu1.dcache.demand_misses::cpu1.data 451 # number of demand (read+write) misses
1544system.cpu1.dcache.demand_misses::total 451 # number of demand (read+write) misses
1545system.cpu1.dcache.overall_misses::cpu1.data 451 # number of overall misses
1546system.cpu1.dcache.overall_misses::total 451 # number of overall misses
1547system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3919891 # number of ReadReq miss cycles
1548system.cpu1.dcache.ReadReq_miss_latency::total 3919891 # number of ReadReq miss cycles
1549system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2617261 # number of WriteReq miss cycles
1550system.cpu1.dcache.WriteReq_miss_latency::total 2617261 # number of WriteReq miss cycles
1551system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 548504 # number of SwapReq miss cycles
1552system.cpu1.dcache.SwapReq_miss_latency::total 548504 # number of SwapReq miss cycles
1553system.cpu1.dcache.demand_miss_latency::cpu1.data 6537152 # number of demand (read+write) miss cycles
1554system.cpu1.dcache.demand_miss_latency::total 6537152 # number of demand (read+write) miss cycles
1555system.cpu1.dcache.overall_miss_latency::cpu1.data 6537152 # number of overall miss cycles
1556system.cpu1.dcache.overall_miss_latency::total 6537152 # number of overall miss cycles
1557system.cpu1.dcache.ReadReq_accesses::cpu1.data 38041 # number of ReadReq accesses(hits+misses)
1558system.cpu1.dcache.ReadReq_accesses::total 38041 # number of ReadReq accesses(hits+misses)
1559system.cpu1.dcache.WriteReq_accesses::cpu1.data 25358 # number of WriteReq accesses(hits+misses)
1560system.cpu1.dcache.WriteReq_accesses::total 25358 # number of WriteReq accesses(hits+misses)
1561system.cpu1.dcache.SwapReq_accesses::cpu1.data 76 # number of SwapReq accesses(hits+misses)
1562system.cpu1.dcache.SwapReq_accesses::total 76 # number of SwapReq accesses(hits+misses)
1563system.cpu1.dcache.demand_accesses::cpu1.data 63399 # number of demand (read+write) accesses
1564system.cpu1.dcache.demand_accesses::total 63399 # number of demand (read+write) accesses
1565system.cpu1.dcache.overall_accesses::cpu1.data 63399 # number of overall (read+write) accesses
1566system.cpu1.dcache.overall_accesses::total 63399 # number of overall (read+write) accesses
1567system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008386 # miss rate for ReadReq accesses
1568system.cpu1.dcache.ReadReq_miss_rate::total 0.008386 # miss rate for ReadReq accesses
1569system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.005205 # miss rate for WriteReq accesses
1570system.cpu1.dcache.WriteReq_miss_rate::total 0.005205 # miss rate for WriteReq accesses
1571system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.789474 # miss rate for SwapReq accesses
1572system.cpu1.dcache.SwapReq_miss_rate::total 0.789474 # miss rate for SwapReq accesses
1573system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007114 # miss rate for demand accesses
1574system.cpu1.dcache.demand_miss_rate::total 0.007114 # miss rate for demand accesses
1575system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007114 # miss rate for overall accesses
1576system.cpu1.dcache.overall_miss_rate::total 0.007114 # miss rate for overall accesses
1577system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12288.059561 # average ReadReq miss latency
1578system.cpu1.dcache.ReadReq_avg_miss_latency::total 12288.059561 # average ReadReq miss latency
1579system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19827.734848 # average WriteReq miss latency
1580system.cpu1.dcache.WriteReq_avg_miss_latency::total 19827.734848 # average WriteReq miss latency
1581system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9141.733333 # average SwapReq miss latency
1582system.cpu1.dcache.SwapReq_avg_miss_latency::total 9141.733333 # average SwapReq miss latency
1583system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14494.793792 # average overall miss latency
1584system.cpu1.dcache.demand_avg_miss_latency::total 14494.793792 # average overall miss latency
1585system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14494.793792 # average overall miss latency
1586system.cpu1.dcache.overall_avg_miss_latency::total 14494.793792 # average overall miss latency
1587system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1588system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1589system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1590system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1591system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1592system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1593system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1594system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1595system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 154 # number of ReadReq MSHR hits
1596system.cpu1.dcache.ReadReq_mshr_hits::total 154 # number of ReadReq MSHR hits
1597system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits
1598system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits
1599system.cpu1.dcache.demand_mshr_hits::cpu1.data 186 # number of demand (read+write) MSHR hits
1600system.cpu1.dcache.demand_mshr_hits::total 186 # number of demand (read+write) MSHR hits
1601system.cpu1.dcache.overall_mshr_hits::cpu1.data 186 # number of overall MSHR hits
1602system.cpu1.dcache.overall_mshr_hits::total 186 # number of overall MSHR hits
1603system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 165 # number of ReadReq MSHR misses
1604system.cpu1.dcache.ReadReq_mshr_misses::total 165 # number of ReadReq MSHR misses
1605system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 100 # number of WriteReq MSHR misses
1606system.cpu1.dcache.WriteReq_mshr_misses::total 100 # number of WriteReq MSHR misses
1607system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 60 # number of SwapReq MSHR misses
1608system.cpu1.dcache.SwapReq_mshr_misses::total 60 # number of SwapReq MSHR misses
1609system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses
1610system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses
1611system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses
1612system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses
1613system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1138770 # number of ReadReq MSHR miss cycles
1614system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1138770 # number of ReadReq MSHR miss cycles
1615system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1290739 # number of WriteReq MSHR miss cycles
1616system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1290739 # number of WriteReq MSHR miss cycles
1617system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 428496 # number of SwapReq MSHR miss cycles
1618system.cpu1.dcache.SwapReq_mshr_miss_latency::total 428496 # number of SwapReq MSHR miss cycles
1619system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2429509 # number of demand (read+write) MSHR miss cycles
1620system.cpu1.dcache.demand_mshr_miss_latency::total 2429509 # number of demand (read+write) MSHR miss cycles
1621system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2429509 # number of overall MSHR miss cycles
1622system.cpu1.dcache.overall_mshr_miss_latency::total 2429509 # number of overall MSHR miss cycles
1623system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004337 # mshr miss rate for ReadReq accesses
1624system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004337 # mshr miss rate for ReadReq accesses
1625system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003944 # mshr miss rate for WriteReq accesses
1626system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003944 # mshr miss rate for WriteReq accesses
1627system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.789474 # mshr miss rate for SwapReq accesses
1628system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.789474 # mshr miss rate for SwapReq accesses
1629system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004180 # mshr miss rate for demand accesses
1630system.cpu1.dcache.demand_mshr_miss_rate::total 0.004180 # mshr miss rate for demand accesses
1631system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004180 # mshr miss rate for overall accesses
1632system.cpu1.dcache.overall_mshr_miss_rate::total 0.004180 # mshr miss rate for overall accesses
1633system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6901.636364 # average ReadReq mshr miss latency
1634system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6901.636364 # average ReadReq mshr miss latency
1635system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12907.390000 # average WriteReq mshr miss latency
1636system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12907.390000 # average WriteReq mshr miss latency
1637system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7141.600000 # average SwapReq mshr miss latency
1638system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7141.600000 # average SwapReq mshr miss latency
1639system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9167.958491 # average overall mshr miss latency
1640system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9167.958491 # average overall mshr miss latency
1641system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9167.958491 # average overall mshr miss latency
1642system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9167.958491 # average overall mshr miss latency
1643system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1644system.cpu2.branchPred.lookups 51236 # Number of BP lookups
1645system.cpu2.branchPred.condPredicted 48519 # Number of conditional branches predicted
1646system.cpu2.branchPred.condIncorrect 1308 # Number of conditional branches incorrect
1647system.cpu2.branchPred.BTBLookups 45052 # Number of BTB lookups
1648system.cpu2.branchPred.BTBHits 44357 # Number of BTB hits
1649system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1650system.cpu2.branchPred.BTBHitPct 98.457338 # BTB Hit Percentage
1651system.cpu2.branchPred.usedRAS 684 # Number of times the RAS was used to get a target.
1652system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
1653system.cpu2.numCycles 177316 # number of cpu cycles simulated
1654system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
1655system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
1656system.cpu2.fetch.icacheStallCycles 28846 # Number of cycles fetch is stalled on an Icache miss
1657system.cpu2.fetch.Insts 286216 # Number of instructions fetch has processed
1658system.cpu2.fetch.Branches 51236 # Number of branches that fetch encountered
1659system.cpu2.fetch.predictedBranches 45041 # Number of branches that fetch has predicted taken
1660system.cpu2.fetch.Cycles 100902 # Number of cycles fetch has run and was not squashing or blocked
1661system.cpu2.fetch.SquashCycles 3805 # Number of cycles fetch has spent squashing
1662system.cpu2.fetch.BlockedCycles 31210 # Number of cycles fetch has spent blocked
1663system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1664system.cpu2.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from
1665system.cpu2.fetch.PendingTrapStallCycles 775 # Number of stall cycles due to pending traps
1666system.cpu2.fetch.CacheLines 19767 # Number of cache lines fetched
1667system.cpu2.fetch.IcacheSquashes 276 # Number of outstanding Icache misses that were squashed
1668system.cpu2.fetch.rateDist::samples 171898 # Number of instructions fetched each cycle (Total)
1669system.cpu2.fetch.rateDist::mean 1.665034 # Number of instructions fetched each cycle (Total)
1670system.cpu2.fetch.rateDist::stdev 2.139289 # Number of instructions fetched each cycle (Total)
1671system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1672system.cpu2.fetch.rateDist::0 70996 41.30% 41.30% # Number of instructions fetched each cycle (Total)
1673system.cpu2.fetch.rateDist::1 51338 29.87% 71.17% # Number of instructions fetched each cycle (Total)
1674system.cpu2.fetch.rateDist::2 6125 3.56% 74.73% # Number of instructions fetched each cycle (Total)
1675system.cpu2.fetch.rateDist::3 3190 1.86% 76.59% # Number of instructions fetched each cycle (Total)
1676system.cpu2.fetch.rateDist::4 695 0.40% 76.99% # Number of instructions fetched each cycle (Total)
1677system.cpu2.fetch.rateDist::5 34353 19.98% 96.97% # Number of instructions fetched each cycle (Total)
1678system.cpu2.fetch.rateDist::6 1162 0.68% 97.65% # Number of instructions fetched each cycle (Total)
1679system.cpu2.fetch.rateDist::7 771 0.45% 98.10% # Number of instructions fetched each cycle (Total)
1680system.cpu2.fetch.rateDist::8 3268 1.90% 100.00% # Number of instructions fetched each cycle (Total)
1681system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1682system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1683system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
1684system.cpu2.fetch.rateDist::total 171898 # Number of instructions fetched each cycle (Total)
1685system.cpu2.fetch.branchRate 0.288953 # Number of branch fetches per cycle
1686system.cpu2.fetch.rate 1.614158 # Number of inst fetches per cycle
1687system.cpu2.decode.IdleCycles 33770 # Number of cycles decode is idle
1688system.cpu2.decode.BlockedCycles 27924 # Number of cycles decode is blocked
1689system.cpu2.decode.RunCycles 94988 # Number of cycles decode is running
1690system.cpu2.decode.UnblockCycles 5055 # Number of cycles decode is unblocking
1691system.cpu2.decode.SquashCycles 2422 # Number of cycles decode is squashing
1692system.cpu2.decode.DecodedInsts 282690 # Number of instructions handled by decode
1693system.cpu2.rename.SquashCycles 2422 # Number of cycles rename is squashing
1694system.cpu2.rename.IdleCycles 34480 # Number of cycles rename is idle
1695system.cpu2.rename.BlockCycles 14885 # Number of cycles rename is blocking
1696system.cpu2.rename.serializeStallCycles 12280 # count of cycles rename stalled for serializing inst
1697system.cpu2.rename.RunCycles 90190 # Number of cycles rename is running
1698system.cpu2.rename.UnblockCycles 9902 # Number of cycles rename is unblocking
1699system.cpu2.rename.RenamedInsts 280450 # Number of instructions processed by rename
1700system.cpu2.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
1701system.cpu2.rename.LSQFullEvents 24 # Number of times rename has blocked due to LSQ full
1702system.cpu2.rename.RenamedOperands 196553 # Number of destination operands rename has renamed
1703system.cpu2.rename.RenameLookups 537620 # Number of register rename lookups that rename has made
1704system.cpu2.rename.int_rename_lookups 418050 # Number of integer rename lookups
1705system.cpu2.rename.CommittedMaps 183508 # Number of HB maps that are committed
1706system.cpu2.rename.UndoneMaps 13045 # Number of HB maps that are undone due to squashing
1707system.cpu2.rename.serializingInsts 1112 # count of serializing insts renamed
1708system.cpu2.rename.tempSerializingInsts 1237 # count of temporary serializing insts renamed
1709system.cpu2.rename.skidInsts 12513 # count of insts added to the skid buffer
1710system.cpu2.memDep0.insertedLoads 79191 # Number of loads inserted to the mem dependence unit.
1711system.cpu2.memDep0.insertedStores 37564 # Number of stores inserted to the mem dependence unit.
1712system.cpu2.memDep0.conflictingLoads 37796 # Number of conflicting loads.
1713system.cpu2.memDep0.conflictingStores 32512 # Number of conflicting stores.
1714system.cpu2.iq.iqInstsAdded 232563 # Number of instructions added to the IQ (excludes non-spec)
1715system.cpu2.iq.iqNonSpecInstsAdded 6341 # Number of non-speculative instructions added to the IQ
1716system.cpu2.iq.iqInstsIssued 234561 # Number of instructions issued
1717system.cpu2.iq.iqSquashedInstsIssued 83 # Number of squashed instructions issued
1718system.cpu2.iq.iqSquashedInstsExamined 11040 # Number of squashed instructions iterated over during squash; mainly for profiling
1719system.cpu2.iq.iqSquashedOperandsExamined 10888 # Number of squashed operands that are examined and possibly removed from graph
1720system.cpu2.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed
1721system.cpu2.iq.issued_per_cycle::samples 171898 # Number of insts issued each cycle
1722system.cpu2.iq.issued_per_cycle::mean 1.364536 # Number of insts issued each cycle
1723system.cpu2.iq.issued_per_cycle::stdev 1.313534 # Number of insts issued each cycle
1724system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1725system.cpu2.iq.issued_per_cycle::0 68441 39.81% 39.81% # Number of insts issued each cycle
1726system.cpu2.iq.issued_per_cycle::1 22472 13.07% 52.89% # Number of insts issued each cycle
1727system.cpu2.iq.issued_per_cycle::2 37788 21.98% 74.87% # Number of insts issued each cycle
1728system.cpu2.iq.issued_per_cycle::3 38389 22.33% 97.20% # Number of insts issued each cycle
1729system.cpu2.iq.issued_per_cycle::4 3254 1.89% 99.10% # Number of insts issued each cycle
1730system.cpu2.iq.issued_per_cycle::5 1164 0.68% 99.77% # Number of insts issued each cycle
1731system.cpu2.iq.issued_per_cycle::6 277 0.16% 99.93% # Number of insts issued each cycle
1732system.cpu2.iq.issued_per_cycle::7 56 0.03% 99.97% # Number of insts issued each cycle
1733system.cpu2.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle
1734system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1735system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1736system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
1737system.cpu2.iq.issued_per_cycle::total 171898 # Number of insts issued each cycle
1738system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1739system.cpu2.iq.fu_full::IntAlu 17 6.14% 6.14% # attempts to use FU when none available
1740system.cpu2.iq.fu_full::IntMult 0 0.00% 6.14% # attempts to use FU when none available
1741system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.14% # attempts to use FU when none available
1742system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.14% # attempts to use FU when none available
1743system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.14% # attempts to use FU when none available
1744system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.14% # attempts to use FU when none available
1745system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.14% # attempts to use FU when none available
1746system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.14% # attempts to use FU when none available
1747system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.14% # attempts to use FU when none available
1748system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.14% # attempts to use FU when none available
1749system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.14% # attempts to use FU when none available
1750system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.14% # attempts to use FU when none available
1751system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.14% # attempts to use FU when none available
1752system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.14% # attempts to use FU when none available
1753system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.14% # attempts to use FU when none available
1754system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.14% # attempts to use FU when none available
1755system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.14% # attempts to use FU when none available
1756system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.14% # attempts to use FU when none available
1757system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.14% # attempts to use FU when none available
1758system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.14% # attempts to use FU when none available
1759system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.14% # attempts to use FU when none available
1760system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.14% # attempts to use FU when none available
1761system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.14% # attempts to use FU when none available
1762system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.14% # attempts to use FU when none available
1763system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.14% # attempts to use FU when none available
1764system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.14% # attempts to use FU when none available
1765system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.14% # attempts to use FU when none available
1766system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.14% # attempts to use FU when none available
1767system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.14% # attempts to use FU when none available
1768system.cpu2.iq.fu_full::MemRead 50 18.05% 24.19% # attempts to use FU when none available
1769system.cpu2.iq.fu_full::MemWrite 210 75.81% 100.00% # attempts to use FU when none available
1770system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1771system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1772system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
1773system.cpu2.iq.FU_type_0::IntAlu 114217 48.69% 48.69% # Type of FU issued
1774system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.69% # Type of FU issued
1775system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.69% # Type of FU issued
1776system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.69% # Type of FU issued
1777system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.69% # Type of FU issued
1778system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.69% # Type of FU issued
1779system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.69% # Type of FU issued
1780system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.69% # Type of FU issued
1781system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.69% # Type of FU issued
1782system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.69% # Type of FU issued
1783system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.69% # Type of FU issued
1784system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.69% # Type of FU issued
1785system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.69% # Type of FU issued
1786system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.69% # Type of FU issued
1787system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.69% # Type of FU issued
1788system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.69% # Type of FU issued
1789system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.69% # Type of FU issued
1790system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.69% # Type of FU issued
1791system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.69% # Type of FU issued
1792system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.69% # Type of FU issued
1793system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.69% # Type of FU issued
1794system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.69% # Type of FU issued
1795system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.69% # Type of FU issued
1796system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.69% # Type of FU issued
1797system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.69% # Type of FU issued
1798system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.69% # Type of FU issued
1799system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.69% # Type of FU issued
1800system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.69% # Type of FU issued
1801system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.69% # Type of FU issued
1802system.cpu2.iq.FU_type_0::MemRead 83468 35.58% 84.28% # Type of FU issued
1803system.cpu2.iq.FU_type_0::MemWrite 36876 15.72% 100.00% # Type of FU issued
1804system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1805system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1806system.cpu2.iq.FU_type_0::total 234561 # Type of FU issued
1807system.cpu2.iq.rate 1.322842 # Inst issue rate
1808system.cpu2.iq.fu_busy_cnt 277 # FU busy when requested
1809system.cpu2.iq.fu_busy_rate 0.001181 # FU busy rate (busy events/executed inst)
1810system.cpu2.iq.int_inst_queue_reads 641380 # Number of integer instruction queue reads
1811system.cpu2.iq.int_inst_queue_writes 249989 # Number of integer instruction queue writes
1812system.cpu2.iq.int_inst_queue_wakeup_accesses 232740 # Number of integer instruction queue wakeup accesses
1813system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
1814system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
1815system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
1816system.cpu2.iq.int_alu_accesses 234838 # Number of integer alu accesses
1817system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
1818system.cpu2.iew.lsq.thread0.forwLoads 32248 # Number of loads that had data forwarded from stores
1819system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1820system.cpu2.iew.lsq.thread0.squashedLoads 2484 # Number of loads squashed
1821system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
1822system.cpu2.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations
1823system.cpu2.iew.lsq.thread0.squashedStores 1465 # Number of stores squashed
1824system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1825system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1826system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
1827system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
1828system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1829system.cpu2.iew.iewSquashCycles 2422 # Number of cycles IEW is squashing
1830system.cpu2.iew.iewBlockCycles 851 # Number of cycles IEW is blocking
1831system.cpu2.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking
1832system.cpu2.iew.iewDispatchedInsts 277610 # Number of instructions dispatched to IQ
1833system.cpu2.iew.iewDispSquashedInsts 365 # Number of squashed instructions skipped by dispatch
1834system.cpu2.iew.iewDispLoadInsts 79191 # Number of dispatched load instructions
1835system.cpu2.iew.iewDispStoreInsts 37564 # Number of dispatched store instructions
1836system.cpu2.iew.iewDispNonSpecInsts 1068 # Number of dispatched non-speculative instructions
1837system.cpu2.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall
1838system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
1839system.cpu2.iew.memOrderViolationEvents 45 # Number of memory order violations
1840system.cpu2.iew.predictedTakenIncorrect 466 # Number of branches that were predicted taken incorrectly
1841system.cpu2.iew.predictedNotTakenIncorrect 970 # Number of branches that were predicted not taken incorrectly
1842system.cpu2.iew.branchMispredicts 1436 # Number of branch mispredicts detected at execute
1843system.cpu2.iew.iewExecutedInsts 233403 # Number of executed instructions
1844system.cpu2.iew.iewExecLoadInsts 78158 # Number of load instructions executed
1845system.cpu2.iew.iewExecSquashedInsts 1158 # Number of squashed instructions skipped in execute
1846system.cpu2.iew.exec_swp 0 # number of swp insts executed
1847system.cpu2.iew.exec_nop 38706 # number of nop insts executed
1848system.cpu2.iew.exec_refs 114950 # number of memory reference insts executed
1849system.cpu2.iew.exec_branches 47927 # Number of branches executed
1850system.cpu2.iew.exec_stores 36792 # Number of stores executed
1851system.cpu2.iew.exec_rate 1.316311 # Inst execution rate
1852system.cpu2.iew.wb_sent 233070 # cumulative count of insts sent to commit
1853system.cpu2.iew.wb_count 232740 # cumulative count of insts written-back
1854system.cpu2.iew.wb_producers 131730 # num instructions producing a value
1855system.cpu2.iew.wb_consumers 136434 # num instructions consuming a value
1856system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1857system.cpu2.iew.wb_rate 1.312572 # insts written-back per cycle
1858system.cpu2.iew.wb_fanout 0.965522 # average fanout of values written-back
1859system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1860system.cpu2.commit.commitSquashedInsts 12692 # The number of squashed insts skipped by commit
1861system.cpu2.commit.commitNonSpecStalls 5739 # The number of times commit has been forced to stall to communicate backwards
1862system.cpu2.commit.branchMispredicts 1308 # The number of times a branch was mispredicted
1863system.cpu2.commit.committed_per_cycle::samples 161737 # Number of insts commited each cycle
1864system.cpu2.commit.committed_per_cycle::mean 1.637943 # Number of insts commited each cycle
1865system.cpu2.commit.committed_per_cycle::stdev 2.020354 # Number of insts commited each cycle
1866system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1867system.cpu2.commit.committed_per_cycle::0 66243 40.96% 40.96% # Number of insts commited each cycle
1868system.cpu2.commit.committed_per_cycle::1 46082 28.49% 69.45% # Number of insts commited each cycle
1869system.cpu2.commit.committed_per_cycle::2 6100 3.77% 73.22% # Number of insts commited each cycle
1870system.cpu2.commit.committed_per_cycle::3 6659 4.12% 77.34% # Number of insts commited each cycle
1871system.cpu2.commit.committed_per_cycle::4 1556 0.96% 78.30% # Number of insts commited each cycle
1872system.cpu2.commit.committed_per_cycle::5 32794 20.28% 98.58% # Number of insts commited each cycle
1873system.cpu2.commit.committed_per_cycle::6 480 0.30% 98.87% # Number of insts commited each cycle
1874system.cpu2.commit.committed_per_cycle::7 1001 0.62% 99.49% # Number of insts commited each cycle
1875system.cpu2.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle
1876system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1877system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1878system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1879system.cpu2.commit.committed_per_cycle::total 161737 # Number of insts commited each cycle
1880system.cpu2.commit.committedInsts 264916 # Number of instructions committed
1881system.cpu2.commit.committedOps 264916 # Number of ops (including micro ops) committed
1882system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
1883system.cpu2.commit.refs 112806 # Number of memory references committed
1884system.cpu2.commit.loads 76707 # Number of loads committed
1885system.cpu2.commit.membars 5024 # Number of memory barriers committed
1886system.cpu2.commit.branches 47088 # Number of branches committed
1887system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
1888system.cpu2.commit.int_insts 182014 # Number of committed integer instructions.
1889system.cpu2.commit.function_calls 322 # Number of function calls committed.
1890system.cpu2.commit.bw_lim_events 822 # number cycles where commit BW limit reached
1891system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
1892system.cpu2.rob.rob_reads 437936 # The number of ROB reads
1893system.cpu2.rob.rob_writes 557643 # The number of ROB writes
1894system.cpu2.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself
1895system.cpu2.idleCycles 5418 # Total number of cycles that the CPU has spent unscheduled due to idling
1896system.cpu2.quiesceCycles 44292 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1897system.cpu2.committedInsts 222015 # Number of Instructions Simulated
1898system.cpu2.committedOps 222015 # Number of Ops (including micro ops) Simulated
1899system.cpu2.committedInsts_total 222015 # Number of Instructions Simulated
1900system.cpu2.cpi 0.798667 # CPI: Cycles Per Instruction
1901system.cpu2.cpi_total 0.798667 # CPI: Total CPI of All Threads
1902system.cpu2.ipc 1.252087 # IPC: Instructions Per Cycle
1903system.cpu2.ipc_total 1.252087 # IPC: Total IPC of All Threads
1904system.cpu2.int_regfile_reads 403571 # number of integer regfile reads
1905system.cpu2.int_regfile_writes 188531 # number of integer regfile writes
1906system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
1907system.cpu2.misc_regfile_reads 116514 # number of misc regfile reads
1908system.cpu2.misc_regfile_writes 648 # number of misc regfile writes
1909system.cpu2.icache.tags.replacements 317 # number of replacements
1910system.cpu2.icache.tags.tagsinuse 82.351710 # Cycle average of tags in use
1911system.cpu2.icache.tags.total_refs 19274 # Total number of references to valid blocks.
1912system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks.
1913system.cpu2.icache.tags.avg_refs 45.350588 # Average number of references to valid blocks.
1914system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1915system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.351710 # Average occupied blocks per requestor
1916system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160843 # Average percentage of cache occupancy
1917system.cpu2.icache.tags.occ_percent::total 0.160843 # Average percentage of cache occupancy
1918system.cpu2.icache.ReadReq_hits::cpu2.inst 19274 # number of ReadReq hits
1919system.cpu2.icache.ReadReq_hits::total 19274 # number of ReadReq hits
1920system.cpu2.icache.demand_hits::cpu2.inst 19274 # number of demand (read+write) hits
1921system.cpu2.icache.demand_hits::total 19274 # number of demand (read+write) hits
1922system.cpu2.icache.overall_hits::cpu2.inst 19274 # number of overall hits
1923system.cpu2.icache.overall_hits::total 19274 # number of overall hits
1924system.cpu2.icache.ReadReq_misses::cpu2.inst 493 # number of ReadReq misses
1925system.cpu2.icache.ReadReq_misses::total 493 # number of ReadReq misses
1926system.cpu2.icache.demand_misses::cpu2.inst 493 # number of demand (read+write) misses
1927system.cpu2.icache.demand_misses::total 493 # number of demand (read+write) misses
1928system.cpu2.icache.overall_misses::cpu2.inst 493 # number of overall misses
1929system.cpu2.icache.overall_misses::total 493 # number of overall misses
1930system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11521742 # number of ReadReq miss cycles
1931system.cpu2.icache.ReadReq_miss_latency::total 11521742 # number of ReadReq miss cycles
1932system.cpu2.icache.demand_miss_latency::cpu2.inst 11521742 # number of demand (read+write) miss cycles
1933system.cpu2.icache.demand_miss_latency::total 11521742 # number of demand (read+write) miss cycles
1934system.cpu2.icache.overall_miss_latency::cpu2.inst 11521742 # number of overall miss cycles
1935system.cpu2.icache.overall_miss_latency::total 11521742 # number of overall miss cycles
1936system.cpu2.icache.ReadReq_accesses::cpu2.inst 19767 # number of ReadReq accesses(hits+misses)
1937system.cpu2.icache.ReadReq_accesses::total 19767 # number of ReadReq accesses(hits+misses)
1938system.cpu2.icache.demand_accesses::cpu2.inst 19767 # number of demand (read+write) accesses
1939system.cpu2.icache.demand_accesses::total 19767 # number of demand (read+write) accesses
1940system.cpu2.icache.overall_accesses::cpu2.inst 19767 # number of overall (read+write) accesses
1941system.cpu2.icache.overall_accesses::total 19767 # number of overall (read+write) accesses
1942system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024941 # miss rate for ReadReq accesses
1943system.cpu2.icache.ReadReq_miss_rate::total 0.024941 # miss rate for ReadReq accesses
1944system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024941 # miss rate for demand accesses
1945system.cpu2.icache.demand_miss_rate::total 0.024941 # miss rate for demand accesses
1946system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024941 # miss rate for overall accesses
1947system.cpu2.icache.overall_miss_rate::total 0.024941 # miss rate for overall accesses
1948system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23370.673428 # average ReadReq miss latency
1949system.cpu2.icache.ReadReq_avg_miss_latency::total 23370.673428 # average ReadReq miss latency
1950system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23370.673428 # average overall miss latency
1951system.cpu2.icache.demand_avg_miss_latency::total 23370.673428 # average overall miss latency
1952system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23370.673428 # average overall miss latency
1953system.cpu2.icache.overall_avg_miss_latency::total 23370.673428 # average overall miss latency
1954system.cpu2.icache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked
1955system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1956system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked
1957system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
1958system.cpu2.icache.avg_blocked_cycles::no_mshrs 85 # average number of cycles each access was blocked
1959system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1960system.cpu2.icache.fast_writes 0 # number of fast writes performed
1961system.cpu2.icache.cache_copies 0 # number of cache copies performed

--- 4 unchanged lines hidden (view full) ---

1966system.cpu2.icache.overall_mshr_hits::cpu2.inst 68 # number of overall MSHR hits
1967system.cpu2.icache.overall_mshr_hits::total 68 # number of overall MSHR hits
1968system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 425 # number of ReadReq MSHR misses
1969system.cpu2.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses
1970system.cpu2.icache.demand_mshr_misses::cpu2.inst 425 # number of demand (read+write) MSHR misses
1971system.cpu2.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses
1972system.cpu2.icache.overall_mshr_misses::cpu2.inst 425 # number of overall MSHR misses
1973system.cpu2.icache.overall_mshr_misses::total 425 # number of overall MSHR misses
1974system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9201754 # number of ReadReq MSHR miss cycles
1975system.cpu2.icache.ReadReq_mshr_miss_latency::total 9201754 # number of ReadReq MSHR miss cycles
1976system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9201754 # number of demand (read+write) MSHR miss cycles
1977system.cpu2.icache.demand_mshr_miss_latency::total 9201754 # number of demand (read+write) MSHR miss cycles
1978system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9201754 # number of overall MSHR miss cycles
1979system.cpu2.icache.overall_mshr_miss_latency::total 9201754 # number of overall MSHR miss cycles
1980system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021500 # mshr miss rate for ReadReq accesses
1981system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021500 # mshr miss rate for ReadReq accesses
1982system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021500 # mshr miss rate for demand accesses
1983system.cpu2.icache.demand_mshr_miss_rate::total 0.021500 # mshr miss rate for demand accesses
1984system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021500 # mshr miss rate for overall accesses
1985system.cpu2.icache.overall_mshr_miss_rate::total 0.021500 # mshr miss rate for overall accesses
1986system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21651.185882 # average ReadReq mshr miss latency
1987system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21651.185882 # average ReadReq mshr miss latency
1988system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21651.185882 # average overall mshr miss latency
1989system.cpu2.icache.demand_avg_mshr_miss_latency::total 21651.185882 # average overall mshr miss latency
1990system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21651.185882 # average overall mshr miss latency
1991system.cpu2.icache.overall_avg_mshr_miss_latency::total 21651.185882 # average overall mshr miss latency
1992system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1993system.cpu2.dcache.tags.replacements 0 # number of replacements
1994system.cpu2.dcache.tags.tagsinuse 26.191522 # Cycle average of tags in use
1995system.cpu2.dcache.tags.total_refs 42135 # Total number of references to valid blocks.
1996system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
1997system.cpu2.dcache.tags.avg_refs 1504.821429 # Average number of references to valid blocks.
1998system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1999system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.191522 # Average occupied blocks per requestor
2000system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051155 # Average percentage of cache occupancy
2001system.cpu2.dcache.tags.occ_percent::total 0.051155 # Average percentage of cache occupancy
2002system.cpu2.dcache.ReadReq_hits::cpu2.data 45549 # number of ReadReq hits
2003system.cpu2.dcache.ReadReq_hits::total 45549 # number of ReadReq hits
2004system.cpu2.dcache.WriteReq_hits::cpu2.data 35887 # number of WriteReq hits
2005system.cpu2.dcache.WriteReq_hits::total 35887 # number of WriteReq hits
2006system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits
2007system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits
2008system.cpu2.dcache.demand_hits::cpu2.data 81436 # number of demand (read+write) hits
2009system.cpu2.dcache.demand_hits::total 81436 # number of demand (read+write) hits
2010system.cpu2.dcache.overall_hits::cpu2.data 81436 # number of overall hits
2011system.cpu2.dcache.overall_hits::total 81436 # number of overall hits
2012system.cpu2.dcache.ReadReq_misses::cpu2.data 344 # number of ReadReq misses
2013system.cpu2.dcache.ReadReq_misses::total 344 # number of ReadReq misses
2014system.cpu2.dcache.WriteReq_misses::cpu2.data 143 # number of WriteReq misses
2015system.cpu2.dcache.WriteReq_misses::total 143 # number of WriteReq misses
2016system.cpu2.dcache.SwapReq_misses::cpu2.data 57 # number of SwapReq misses
2017system.cpu2.dcache.SwapReq_misses::total 57 # number of SwapReq misses
2018system.cpu2.dcache.demand_misses::cpu2.data 487 # number of demand (read+write) misses
2019system.cpu2.dcache.demand_misses::total 487 # number of demand (read+write) misses
2020system.cpu2.dcache.overall_misses::cpu2.data 487 # number of overall misses
2021system.cpu2.dcache.overall_misses::total 487 # number of overall misses
2022system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5599802 # number of ReadReq miss cycles
2023system.cpu2.dcache.ReadReq_miss_latency::total 5599802 # number of ReadReq miss cycles
2024system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3105260 # number of WriteReq miss cycles
2025system.cpu2.dcache.WriteReq_miss_latency::total 3105260 # number of WriteReq miss cycles
2026system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 575007 # number of SwapReq miss cycles
2027system.cpu2.dcache.SwapReq_miss_latency::total 575007 # number of SwapReq miss cycles
2028system.cpu2.dcache.demand_miss_latency::cpu2.data 8705062 # number of demand (read+write) miss cycles
2029system.cpu2.dcache.demand_miss_latency::total 8705062 # number of demand (read+write) miss cycles
2030system.cpu2.dcache.overall_miss_latency::cpu2.data 8705062 # number of overall miss cycles
2031system.cpu2.dcache.overall_miss_latency::total 8705062 # number of overall miss cycles
2032system.cpu2.dcache.ReadReq_accesses::cpu2.data 45893 # number of ReadReq accesses(hits+misses)
2033system.cpu2.dcache.ReadReq_accesses::total 45893 # number of ReadReq accesses(hits+misses)
2034system.cpu2.dcache.WriteReq_accesses::cpu2.data 36030 # number of WriteReq accesses(hits+misses)
2035system.cpu2.dcache.WriteReq_accesses::total 36030 # number of WriteReq accesses(hits+misses)
2036system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses)
2037system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses)
2038system.cpu2.dcache.demand_accesses::cpu2.data 81923 # number of demand (read+write) accesses
2039system.cpu2.dcache.demand_accesses::total 81923 # number of demand (read+write) accesses
2040system.cpu2.dcache.overall_accesses::cpu2.data 81923 # number of overall (read+write) accesses
2041system.cpu2.dcache.overall_accesses::total 81923 # number of overall (read+write) accesses
2042system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.007496 # miss rate for ReadReq accesses
2043system.cpu2.dcache.ReadReq_miss_rate::total 0.007496 # miss rate for ReadReq accesses
2044system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003969 # miss rate for WriteReq accesses
2045system.cpu2.dcache.WriteReq_miss_rate::total 0.003969 # miss rate for WriteReq accesses
2046system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.826087 # miss rate for SwapReq accesses
2047system.cpu2.dcache.SwapReq_miss_rate::total 0.826087 # miss rate for SwapReq accesses
2048system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005945 # miss rate for demand accesses
2049system.cpu2.dcache.demand_miss_rate::total 0.005945 # miss rate for demand accesses
2050system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005945 # miss rate for overall accesses
2051system.cpu2.dcache.overall_miss_rate::total 0.005945 # miss rate for overall accesses
2052system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16278.494186 # average ReadReq miss latency
2053system.cpu2.dcache.ReadReq_avg_miss_latency::total 16278.494186 # average ReadReq miss latency
2054system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21715.104895 # average WriteReq miss latency
2055system.cpu2.dcache.WriteReq_avg_miss_latency::total 21715.104895 # average WriteReq miss latency
2056system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10087.842105 # average SwapReq miss latency
2057system.cpu2.dcache.SwapReq_avg_miss_latency::total 10087.842105 # average SwapReq miss latency
2058system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17874.870637 # average overall miss latency
2059system.cpu2.dcache.demand_avg_miss_latency::total 17874.870637 # average overall miss latency
2060system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17874.870637 # average overall miss latency
2061system.cpu2.dcache.overall_avg_miss_latency::total 17874.870637 # average overall miss latency
2062system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2063system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2064system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
2065system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
2066system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2067system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2068system.cpu2.dcache.fast_writes 0 # number of fast writes performed
2069system.cpu2.dcache.cache_copies 0 # number of cache copies performed
2070system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 182 # number of ReadReq MSHR hits
2071system.cpu2.dcache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits
2072system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 34 # number of WriteReq MSHR hits
2073system.cpu2.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits
2074system.cpu2.dcache.demand_mshr_hits::cpu2.data 216 # number of demand (read+write) MSHR hits
2075system.cpu2.dcache.demand_mshr_hits::total 216 # number of demand (read+write) MSHR hits
2076system.cpu2.dcache.overall_mshr_hits::cpu2.data 216 # number of overall MSHR hits
2077system.cpu2.dcache.overall_mshr_hits::total 216 # number of overall MSHR hits
2078system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses
2079system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses
2080system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses
2081system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses
2082system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 57 # number of SwapReq MSHR misses
2083system.cpu2.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses
2084system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses
2085system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses
2086system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses
2087system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses
2088system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1526780 # number of ReadReq MSHR miss cycles
2089system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1526780 # number of ReadReq MSHR miss cycles
2090system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1514240 # number of WriteReq MSHR miss cycles
2091system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1514240 # number of WriteReq MSHR miss cycles
2092system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 460993 # number of SwapReq MSHR miss cycles
2093system.cpu2.dcache.SwapReq_mshr_miss_latency::total 460993 # number of SwapReq MSHR miss cycles
2094system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3041020 # number of demand (read+write) MSHR miss cycles
2095system.cpu2.dcache.demand_mshr_miss_latency::total 3041020 # number of demand (read+write) MSHR miss cycles
2096system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3041020 # number of overall MSHR miss cycles
2097system.cpu2.dcache.overall_mshr_miss_latency::total 3041020 # number of overall MSHR miss cycles
2098system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003530 # mshr miss rate for ReadReq accesses
2099system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003530 # mshr miss rate for ReadReq accesses
2100system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003025 # mshr miss rate for WriteReq accesses
2101system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003025 # mshr miss rate for WriteReq accesses
2102system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.826087 # mshr miss rate for SwapReq accesses
2103system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.826087 # mshr miss rate for SwapReq accesses
2104system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003308 # mshr miss rate for demand accesses
2105system.cpu2.dcache.demand_mshr_miss_rate::total 0.003308 # mshr miss rate for demand accesses
2106system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003308 # mshr miss rate for overall accesses
2107system.cpu2.dcache.overall_mshr_miss_rate::total 0.003308 # mshr miss rate for overall accesses
2108system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9424.567901 # average ReadReq mshr miss latency
2109system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9424.567901 # average ReadReq mshr miss latency
2110system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13892.110092 # average WriteReq mshr miss latency
2111system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13892.110092 # average WriteReq mshr miss latency
2112system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8087.596491 # average SwapReq mshr miss latency
2113system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8087.596491 # average SwapReq mshr miss latency
2114system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11221.476015 # average overall mshr miss latency
2115system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11221.476015 # average overall mshr miss latency
2116system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11221.476015 # average overall mshr miss latency
2117system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11221.476015 # average overall mshr miss latency
2118system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2119system.cpu3.branchPred.lookups 56317 # Number of BP lookups
2120system.cpu3.branchPred.condPredicted 53592 # Number of conditional branches predicted
2121system.cpu3.branchPred.condIncorrect 1257 # Number of conditional branches incorrect
2122system.cpu3.branchPred.BTBLookups 50318 # Number of BTB lookups
2123system.cpu3.branchPred.BTBHits 49441 # Number of BTB hits
2124system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2125system.cpu3.branchPred.BTBHitPct 98.257085 # BTB Hit Percentage
2126system.cpu3.branchPred.usedRAS 649 # Number of times the RAS was used to get a target.
2127system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
2128system.cpu3.numCycles 176970 # number of cpu cycles simulated
2129system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
2130system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
2131system.cpu3.fetch.icacheStallCycles 26467 # Number of cycles fetch is stalled on an Icache miss
2132system.cpu3.fetch.Insts 318235 # Number of instructions fetch has processed
2133system.cpu3.fetch.Branches 56317 # Number of branches that fetch encountered
2134system.cpu3.fetch.predictedBranches 50090 # Number of branches that fetch has predicted taken
2135system.cpu3.fetch.Cycles 110248 # Number of cycles fetch has run and was not squashing or blocked
2136system.cpu3.fetch.SquashCycles 3629 # Number of cycles fetch has spent squashing
2137system.cpu3.fetch.BlockedCycles 28039 # Number of cycles fetch has spent blocked
2138system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
2139system.cpu3.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from
2140system.cpu3.fetch.PendingTrapStallCycles 790 # Number of stall cycles due to pending traps
2141system.cpu3.fetch.CacheLines 18199 # Number of cache lines fetched
2142system.cpu3.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed
2143system.cpu3.fetch.rateDist::samples 175582 # Number of instructions fetched each cycle (Total)
2144system.cpu3.fetch.rateDist::mean 1.812458 # Number of instructions fetched each cycle (Total)
2145system.cpu3.fetch.rateDist::stdev 2.180606 # Number of instructions fetched each cycle (Total)
2146system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2147system.cpu3.fetch.rateDist::0 65334 37.21% 37.21% # Number of instructions fetched each cycle (Total)
2148system.cpu3.fetch.rateDist::1 55610 31.67% 68.88% # Number of instructions fetched each cycle (Total)
2149system.cpu3.fetch.rateDist::2 5389 3.07% 71.95% # Number of instructions fetched each cycle (Total)
2150system.cpu3.fetch.rateDist::3 3177 1.81% 73.76% # Number of instructions fetched each cycle (Total)
2151system.cpu3.fetch.rateDist::4 669 0.38% 74.14% # Number of instructions fetched each cycle (Total)
2152system.cpu3.fetch.rateDist::5 40119 22.85% 96.99% # Number of instructions fetched each cycle (Total)
2153system.cpu3.fetch.rateDist::6 1237 0.70% 97.70% # Number of instructions fetched each cycle (Total)
2154system.cpu3.fetch.rateDist::7 753 0.43% 98.12% # Number of instructions fetched each cycle (Total)
2155system.cpu3.fetch.rateDist::8 3294 1.88% 100.00% # Number of instructions fetched each cycle (Total)
2156system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
2157system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
2158system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
2159system.cpu3.fetch.rateDist::total 175582 # Number of instructions fetched each cycle (Total)
2160system.cpu3.fetch.branchRate 0.318229 # Number of branch fetches per cycle
2161system.cpu3.fetch.rate 1.798243 # Number of inst fetches per cycle
2162system.cpu3.decode.IdleCycles 31057 # Number of cycles decode is idle
2163system.cpu3.decode.BlockedCycles 25106 # Number of cycles decode is blocked
2164system.cpu3.decode.RunCycles 104911 # Number of cycles decode is running
2165system.cpu3.decode.UnblockCycles 4475 # Number of cycles decode is unblocking
2166system.cpu3.decode.SquashCycles 2294 # Number of cycles decode is squashing
2167system.cpu3.decode.DecodedInsts 314540 # Number of instructions handled by decode
2168system.cpu3.rename.SquashCycles 2294 # Number of cycles rename is squashing
2169system.cpu3.rename.IdleCycles 31713 # Number of cycles rename is idle
2170system.cpu3.rename.BlockCycles 12844 # Number of cycles rename is blocking
2171system.cpu3.rename.serializeStallCycles 11527 # count of cycles rename stalled for serializing inst
2172system.cpu3.rename.RunCycles 100723 # Number of cycles rename is running
2173system.cpu3.rename.UnblockCycles 8742 # Number of cycles rename is unblocking
2174system.cpu3.rename.RenamedInsts 312369 # Number of instructions processed by rename
2175system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
2176system.cpu3.rename.LSQFullEvents 22 # Number of times rename has blocked due to LSQ full
2177system.cpu3.rename.RenamedOperands 219058 # Number of destination operands rename has renamed
2178system.cpu3.rename.RenameLookups 604346 # Number of register rename lookups that rename has made
2179system.cpu3.rename.int_rename_lookups 468076 # Number of integer rename lookups
2180system.cpu3.rename.CommittedMaps 206290 # Number of HB maps that are committed
2181system.cpu3.rename.UndoneMaps 12768 # Number of HB maps that are undone due to squashing
2182system.cpu3.rename.serializingInsts 1082 # count of serializing insts renamed
2183system.cpu3.rename.tempSerializingInsts 1202 # count of temporary serializing insts renamed
2184system.cpu3.rename.skidInsts 11332 # count of insts added to the skid buffer
2185system.cpu3.memDep0.insertedLoads 90084 # Number of loads inserted to the mem dependence unit.
2186system.cpu3.memDep0.insertedStores 43367 # Number of stores inserted to the mem dependence unit.
2187system.cpu3.memDep0.conflictingLoads 42837 # Number of conflicting loads.
2188system.cpu3.memDep0.conflictingStores 38342 # Number of conflicting stores.
2189system.cpu3.iq.iqInstsAdded 260031 # Number of instructions added to the IQ (excludes non-spec)
2190system.cpu3.iq.iqNonSpecInstsAdded 5573 # Number of non-speculative instructions added to the IQ
2191system.cpu3.iq.iqInstsIssued 261645 # Number of instructions issued
2192system.cpu3.iq.iqSquashedInstsIssued 62 # Number of squashed instructions issued
2193system.cpu3.iq.iqSquashedInstsExamined 10424 # Number of squashed instructions iterated over during squash; mainly for profiling
2194system.cpu3.iq.iqSquashedOperandsExamined 10297 # Number of squashed operands that are examined and possibly removed from graph
2195system.cpu3.iq.iqSquashedNonSpecRemoved 498 # Number of squashed non-spec instructions that were removed
2196system.cpu3.iq.issued_per_cycle::samples 175582 # Number of insts issued each cycle
2197system.cpu3.iq.issued_per_cycle::mean 1.490158 # Number of insts issued each cycle
2198system.cpu3.iq.issued_per_cycle::stdev 1.307816 # Number of insts issued each cycle
2199system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2200system.cpu3.iq.issued_per_cycle::0 62519 35.61% 35.61% # Number of insts issued each cycle
2201system.cpu3.iq.issued_per_cycle::1 20435 11.64% 47.25% # Number of insts issued each cycle
2202system.cpu3.iq.issued_per_cycle::2 43580 24.82% 72.07% # Number of insts issued each cycle
2203system.cpu3.iq.issued_per_cycle::3 44218 25.18% 97.25% # Number of insts issued each cycle
2204system.cpu3.iq.issued_per_cycle::4 3288 1.87% 99.12% # Number of insts issued each cycle
2205system.cpu3.iq.issued_per_cycle::5 1176 0.67% 99.79% # Number of insts issued each cycle
2206system.cpu3.iq.issued_per_cycle::6 257 0.15% 99.94% # Number of insts issued each cycle
2207system.cpu3.iq.issued_per_cycle::7 50 0.03% 99.97% # Number of insts issued each cycle
2208system.cpu3.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle
2209system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
2210system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2211system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
2212system.cpu3.iq.issued_per_cycle::total 175582 # Number of insts issued each cycle
2213system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2214system.cpu3.iq.fu_full::IntAlu 17 6.25% 6.25% # attempts to use FU when none available
2215system.cpu3.iq.fu_full::IntMult 0 0.00% 6.25% # attempts to use FU when none available
2216system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.25% # attempts to use FU when none available
2217system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.25% # attempts to use FU when none available
2218system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.25% # attempts to use FU when none available
2219system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.25% # attempts to use FU when none available
2220system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.25% # attempts to use FU when none available
2221system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.25% # attempts to use FU when none available
2222system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.25% # attempts to use FU when none available
2223system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.25% # attempts to use FU when none available
2224system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.25% # attempts to use FU when none available
2225system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.25% # attempts to use FU when none available
2226system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.25% # attempts to use FU when none available
2227system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.25% # attempts to use FU when none available
2228system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.25% # attempts to use FU when none available
2229system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.25% # attempts to use FU when none available
2230system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.25% # attempts to use FU when none available
2231system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.25% # attempts to use FU when none available
2232system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.25% # attempts to use FU when none available
2233system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.25% # attempts to use FU when none available
2234system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.25% # attempts to use FU when none available
2235system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.25% # attempts to use FU when none available
2236system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.25% # attempts to use FU when none available
2237system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.25% # attempts to use FU when none available
2238system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.25% # attempts to use FU when none available
2239system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.25% # attempts to use FU when none available
2240system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.25% # attempts to use FU when none available
2241system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.25% # attempts to use FU when none available
2242system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.25% # attempts to use FU when none available
2243system.cpu3.iq.fu_full::MemRead 45 16.54% 22.79% # attempts to use FU when none available
2244system.cpu3.iq.fu_full::MemWrite 210 77.21% 100.00% # attempts to use FU when none available
2245system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
2246system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2247system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
2248system.cpu3.iq.FU_type_0::IntAlu 125105 47.81% 47.81% # Type of FU issued
2249system.cpu3.iq.FU_type_0::IntMult 0 0.00% 47.81% # Type of FU issued
2250system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 47.81% # Type of FU issued
2251system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 47.81% # Type of FU issued
2252system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 47.81% # Type of FU issued
2253system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 47.81% # Type of FU issued
2254system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 47.81% # Type of FU issued
2255system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 47.81% # Type of FU issued
2256system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 47.81% # Type of FU issued
2257system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 47.81% # Type of FU issued
2258system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 47.81% # Type of FU issued
2259system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 47.81% # Type of FU issued
2260system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 47.81% # Type of FU issued
2261system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 47.81% # Type of FU issued
2262system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 47.81% # Type of FU issued
2263system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 47.81% # Type of FU issued
2264system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 47.81% # Type of FU issued
2265system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 47.81% # Type of FU issued
2266system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.81% # Type of FU issued
2267system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 47.81% # Type of FU issued
2268system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.81% # Type of FU issued
2269system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.81% # Type of FU issued
2270system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.81% # Type of FU issued
2271system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.81% # Type of FU issued
2272system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.81% # Type of FU issued
2273system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.81% # Type of FU issued
2274system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 47.81% # Type of FU issued
2275system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.81% # Type of FU issued
2276system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.81% # Type of FU issued
2277system.cpu3.iq.FU_type_0::MemRead 93850 35.87% 83.68% # Type of FU issued
2278system.cpu3.iq.FU_type_0::MemWrite 42690 16.32% 100.00% # Type of FU issued
2279system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
2280system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2281system.cpu3.iq.FU_type_0::total 261645 # Type of FU issued
2282system.cpu3.iq.rate 1.478471 # Inst issue rate
2283system.cpu3.iq.fu_busy_cnt 272 # FU busy when requested
2284system.cpu3.iq.fu_busy_rate 0.001040 # FU busy rate (busy events/executed inst)
2285system.cpu3.iq.int_inst_queue_reads 699206 # Number of integer instruction queue reads
2286system.cpu3.iq.int_inst_queue_writes 276071 # Number of integer instruction queue writes
2287system.cpu3.iq.int_inst_queue_wakeup_accesses 259793 # Number of integer instruction queue wakeup accesses
2288system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
2289system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
2290system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
2291system.cpu3.iq.int_alu_accesses 261917 # Number of integer alu accesses
2292system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
2293system.cpu3.iew.lsq.thread0.forwLoads 38112 # Number of loads that had data forwarded from stores
2294system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2295system.cpu3.iew.lsq.thread0.squashedLoads 2309 # Number of loads squashed
2296system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
2297system.cpu3.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations
2298system.cpu3.iew.lsq.thread0.squashedStores 1414 # Number of stores squashed
2299system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
2300system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2301system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
2302system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
2303system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2304system.cpu3.iew.iewSquashCycles 2294 # Number of cycles IEW is squashing
2305system.cpu3.iew.iewBlockCycles 580 # Number of cycles IEW is blocking
2306system.cpu3.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking
2307system.cpu3.iew.iewDispatchedInsts 309373 # Number of instructions dispatched to IQ
2308system.cpu3.iew.iewDispSquashedInsts 369 # Number of squashed instructions skipped by dispatch
2309system.cpu3.iew.iewDispLoadInsts 90084 # Number of dispatched load instructions
2310system.cpu3.iew.iewDispStoreInsts 43367 # Number of dispatched store instructions
2311system.cpu3.iew.iewDispNonSpecInsts 1034 # Number of dispatched non-speculative instructions
2312system.cpu3.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall
2313system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
2314system.cpu3.iew.memOrderViolationEvents 43 # Number of memory order violations
2315system.cpu3.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly
2316system.cpu3.iew.predictedNotTakenIncorrect 904 # Number of branches that were predicted not taken incorrectly
2317system.cpu3.iew.branchMispredicts 1369 # Number of branch mispredicts detected at execute
2318system.cpu3.iew.iewExecutedInsts 260458 # Number of executed instructions
2319system.cpu3.iew.iewExecLoadInsts 89199 # Number of load instructions executed
2320system.cpu3.iew.iewExecSquashedInsts 1187 # Number of squashed instructions skipped in execute
2321system.cpu3.iew.exec_swp 0 # number of swp insts executed
2322system.cpu3.iew.exec_nop 43769 # number of nop insts executed
2323system.cpu3.iew.exec_refs 131812 # number of memory reference insts executed
2324system.cpu3.iew.exec_branches 53091 # Number of branches executed
2325system.cpu3.iew.exec_stores 42613 # Number of stores executed
2326system.cpu3.iew.exec_rate 1.471764 # Inst execution rate
2327system.cpu3.iew.wb_sent 260118 # cumulative count of insts sent to commit
2328system.cpu3.iew.wb_count 259793 # cumulative count of insts written-back
2329system.cpu3.iew.wb_producers 148532 # num instructions producing a value
2330system.cpu3.iew.wb_consumers 153197 # num instructions consuming a value
2331system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
2332system.cpu3.iew.wb_rate 1.468006 # insts written-back per cycle
2333system.cpu3.iew.wb_fanout 0.969549 # average fanout of values written-back
2334system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
2335system.cpu3.commit.commitSquashedInsts 11915 # The number of squashed insts skipped by commit
2336system.cpu3.commit.commitNonSpecStalls 5075 # The number of times commit has been forced to stall to communicate backwards
2337system.cpu3.commit.branchMispredicts 1257 # The number of times a branch was mispredicted
2338system.cpu3.commit.committed_per_cycle::samples 165549 # Number of insts commited each cycle
2339system.cpu3.commit.committed_per_cycle::mean 1.796677 # Number of insts commited each cycle
2340system.cpu3.commit.committed_per_cycle::stdev 2.064793 # Number of insts commited each cycle
2341system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2342system.cpu3.commit.committed_per_cycle::0 59727 36.08% 36.08% # Number of insts commited each cycle
2343system.cpu3.commit.committed_per_cycle::1 51190 30.92% 67.00% # Number of insts commited each cycle
2344system.cpu3.commit.committed_per_cycle::2 6085 3.68% 70.68% # Number of insts commited each cycle
2345system.cpu3.commit.committed_per_cycle::3 6030 3.64% 74.32% # Number of insts commited each cycle
2346system.cpu3.commit.committed_per_cycle::4 1572 0.95% 75.27% # Number of insts commited each cycle
2347system.cpu3.commit.committed_per_cycle::5 38600 23.32% 98.58% # Number of insts commited each cycle
2348system.cpu3.commit.committed_per_cycle::6 530 0.32% 98.90% # Number of insts commited each cycle
2349system.cpu3.commit.committed_per_cycle::7 1000 0.60% 99.51% # Number of insts commited each cycle
2350system.cpu3.commit.committed_per_cycle::8 815 0.49% 100.00% # Number of insts commited each cycle
2351system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
2352system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
2353system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2354system.cpu3.commit.committed_per_cycle::total 165549 # Number of insts commited each cycle
2355system.cpu3.commit.committedInsts 297438 # Number of instructions committed
2356system.cpu3.commit.committedOps 297438 # Number of ops (including micro ops) committed
2357system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
2358system.cpu3.commit.refs 129728 # Number of memory references committed
2359system.cpu3.commit.loads 87775 # Number of loads committed
2360system.cpu3.commit.membars 4366 # Number of memory barriers committed
2361system.cpu3.commit.branches 52284 # Number of branches committed
2362system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
2363system.cpu3.commit.int_insts 204138 # Number of committed integer instructions.
2364system.cpu3.commit.function_calls 322 # Number of function calls committed.
2365system.cpu3.commit.bw_lim_events 815 # number cycles where commit BW limit reached
2366system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits
2367system.cpu3.rob.rob_reads 473500 # The number of ROB reads
2368system.cpu3.rob.rob_writes 621006 # The number of ROB writes
2369system.cpu3.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself
2370system.cpu3.idleCycles 1388 # Total number of cycles that the CPU has spent unscheduled due to idling
2371system.cpu3.quiesceCycles 44638 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
2372system.cpu3.committedInsts 249993 # Number of Instructions Simulated
2373system.cpu3.committedOps 249993 # Number of Ops (including micro ops) Simulated
2374system.cpu3.committedInsts_total 249993 # Number of Instructions Simulated
2375system.cpu3.cpi 0.707900 # CPI: Cycles Per Instruction
2376system.cpu3.cpi_total 0.707900 # CPI: Total CPI of All Threads
2377system.cpu3.ipc 1.412629 # IPC: Instructions Per Cycle
2378system.cpu3.ipc_total 1.412629 # IPC: Total IPC of All Threads
2379system.cpu3.int_regfile_reads 453881 # number of integer regfile reads
2380system.cpu3.int_regfile_writes 211087 # number of integer regfile writes
2381system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
2382system.cpu3.misc_regfile_reads 133368 # number of misc regfile reads
2383system.cpu3.misc_regfile_writes 648 # number of misc regfile writes
2384system.cpu3.icache.tags.replacements 319 # number of replacements
2385system.cpu3.icache.tags.tagsinuse 77.348761 # Cycle average of tags in use
2386system.cpu3.icache.tags.total_refs 17724 # Total number of references to valid blocks.
2387system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks.
2388system.cpu3.icache.tags.avg_refs 41.218605 # Average number of references to valid blocks.
2389system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2390system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.348761 # Average occupied blocks per requestor
2391system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151072 # Average percentage of cache occupancy
2392system.cpu3.icache.tags.occ_percent::total 0.151072 # Average percentage of cache occupancy
2393system.cpu3.icache.ReadReq_hits::cpu3.inst 17724 # number of ReadReq hits
2394system.cpu3.icache.ReadReq_hits::total 17724 # number of ReadReq hits
2395system.cpu3.icache.demand_hits::cpu3.inst 17724 # number of demand (read+write) hits
2396system.cpu3.icache.demand_hits::total 17724 # number of demand (read+write) hits
2397system.cpu3.icache.overall_hits::cpu3.inst 17724 # number of overall hits
2398system.cpu3.icache.overall_hits::total 17724 # number of overall hits
2399system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses
2400system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses
2401system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses
2402system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses
2403system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses
2404system.cpu3.icache.overall_misses::total 475 # number of overall misses
2405system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6467995 # number of ReadReq miss cycles
2406system.cpu3.icache.ReadReq_miss_latency::total 6467995 # number of ReadReq miss cycles
2407system.cpu3.icache.demand_miss_latency::cpu3.inst 6467995 # number of demand (read+write) miss cycles
2408system.cpu3.icache.demand_miss_latency::total 6467995 # number of demand (read+write) miss cycles
2409system.cpu3.icache.overall_miss_latency::cpu3.inst 6467995 # number of overall miss cycles
2410system.cpu3.icache.overall_miss_latency::total 6467995 # number of overall miss cycles
2411system.cpu3.icache.ReadReq_accesses::cpu3.inst 18199 # number of ReadReq accesses(hits+misses)
2412system.cpu3.icache.ReadReq_accesses::total 18199 # number of ReadReq accesses(hits+misses)
2413system.cpu3.icache.demand_accesses::cpu3.inst 18199 # number of demand (read+write) accesses
2414system.cpu3.icache.demand_accesses::total 18199 # number of demand (read+write) accesses
2415system.cpu3.icache.overall_accesses::cpu3.inst 18199 # number of overall (read+write) accesses
2416system.cpu3.icache.overall_accesses::total 18199 # number of overall (read+write) accesses
2417system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.026100 # miss rate for ReadReq accesses
2418system.cpu3.icache.ReadReq_miss_rate::total 0.026100 # miss rate for ReadReq accesses
2419system.cpu3.icache.demand_miss_rate::cpu3.inst 0.026100 # miss rate for demand accesses
2420system.cpu3.icache.demand_miss_rate::total 0.026100 # miss rate for demand accesses
2421system.cpu3.icache.overall_miss_rate::cpu3.inst 0.026100 # miss rate for overall accesses
2422system.cpu3.icache.overall_miss_rate::total 0.026100 # miss rate for overall accesses
2423system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13616.831579 # average ReadReq miss latency
2424system.cpu3.icache.ReadReq_avg_miss_latency::total 13616.831579 # average ReadReq miss latency
2425system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13616.831579 # average overall miss latency
2426system.cpu3.icache.demand_avg_miss_latency::total 13616.831579 # average overall miss latency
2427system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13616.831579 # average overall miss latency
2428system.cpu3.icache.overall_avg_miss_latency::total 13616.831579 # average overall miss latency
2429system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2430system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2431system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
2432system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
2433system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2434system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2435system.cpu3.icache.fast_writes 0 # number of fast writes performed
2436system.cpu3.icache.cache_copies 0 # number of cache copies performed
2437system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 45 # number of ReadReq MSHR hits
2438system.cpu3.icache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits
2439system.cpu3.icache.demand_mshr_hits::cpu3.inst 45 # number of demand (read+write) MSHR hits
2440system.cpu3.icache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits
2441system.cpu3.icache.overall_mshr_hits::cpu3.inst 45 # number of overall MSHR hits
2442system.cpu3.icache.overall_mshr_hits::total 45 # number of overall MSHR hits
2443system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 430 # number of ReadReq MSHR misses
2444system.cpu3.icache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses
2445system.cpu3.icache.demand_mshr_misses::cpu3.inst 430 # number of demand (read+write) MSHR misses
2446system.cpu3.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses
2447system.cpu3.icache.overall_mshr_misses::cpu3.inst 430 # number of overall MSHR misses
2448system.cpu3.icache.overall_mshr_misses::total 430 # number of overall MSHR misses
2449system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5219755 # number of ReadReq MSHR miss cycles
2450system.cpu3.icache.ReadReq_mshr_miss_latency::total 5219755 # number of ReadReq MSHR miss cycles
2451system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5219755 # number of demand (read+write) MSHR miss cycles
2452system.cpu3.icache.demand_mshr_miss_latency::total 5219755 # number of demand (read+write) MSHR miss cycles
2453system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5219755 # number of overall MSHR miss cycles
2454system.cpu3.icache.overall_mshr_miss_latency::total 5219755 # number of overall MSHR miss cycles
2455system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for ReadReq accesses
2456system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.023628 # mshr miss rate for ReadReq accesses
2457system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for demand accesses
2458system.cpu3.icache.demand_mshr_miss_rate::total 0.023628 # mshr miss rate for demand accesses
2459system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for overall accesses
2460system.cpu3.icache.overall_mshr_miss_rate::total 0.023628 # mshr miss rate for overall accesses
2461system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average ReadReq mshr miss latency
2462system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12138.965116 # average ReadReq mshr miss latency
2463system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency
2464system.cpu3.icache.demand_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency
2465system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency
2466system.cpu3.icache.overall_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency
2467system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2468system.cpu3.dcache.tags.replacements 0 # number of replacements
2469system.cpu3.dcache.tags.tagsinuse 23.659946 # Cycle average of tags in use
2470system.cpu3.dcache.tags.total_refs 47957 # Total number of references to valid blocks.
2471system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
2472system.cpu3.dcache.tags.avg_refs 1712.750000 # Average number of references to valid blocks.
2473system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2474system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.659946 # Average occupied blocks per requestor
2475system.cpu3.dcache.tags.occ_percent::cpu3.data 0.046211 # Average percentage of cache occupancy
2476system.cpu3.dcache.tags.occ_percent::total 0.046211 # Average percentage of cache occupancy
2477system.cpu3.dcache.ReadReq_hits::cpu3.data 50723 # number of ReadReq hits
2478system.cpu3.dcache.ReadReq_hits::total 50723 # number of ReadReq hits
2479system.cpu3.dcache.WriteReq_hits::cpu3.data 41752 # number of WriteReq hits
2480system.cpu3.dcache.WriteReq_hits::total 41752 # number of WriteReq hits
2481system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits
2482system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits
2483system.cpu3.dcache.demand_hits::cpu3.data 92475 # number of demand (read+write) hits
2484system.cpu3.dcache.demand_hits::total 92475 # number of demand (read+write) hits
2485system.cpu3.dcache.overall_hits::cpu3.data 92475 # number of overall hits
2486system.cpu3.dcache.overall_hits::total 92475 # number of overall hits
2487system.cpu3.dcache.ReadReq_misses::cpu3.data 346 # number of ReadReq misses
2488system.cpu3.dcache.ReadReq_misses::total 346 # number of ReadReq misses
2489system.cpu3.dcache.WriteReq_misses::cpu3.data 138 # number of WriteReq misses
2490system.cpu3.dcache.WriteReq_misses::total 138 # number of WriteReq misses
2491system.cpu3.dcache.SwapReq_misses::cpu3.data 51 # number of SwapReq misses
2492system.cpu3.dcache.SwapReq_misses::total 51 # number of SwapReq misses
2493system.cpu3.dcache.demand_misses::cpu3.data 484 # number of demand (read+write) misses
2494system.cpu3.dcache.demand_misses::total 484 # number of demand (read+write) misses
2495system.cpu3.dcache.overall_misses::cpu3.data 484 # number of overall misses
2496system.cpu3.dcache.overall_misses::total 484 # number of overall misses
2497system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4449419 # number of ReadReq miss cycles
2498system.cpu3.dcache.ReadReq_miss_latency::total 4449419 # number of ReadReq miss cycles
2499system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2879011 # number of WriteReq miss cycles
2500system.cpu3.dcache.WriteReq_miss_latency::total 2879011 # number of WriteReq miss cycles
2501system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 478509 # number of SwapReq miss cycles
2502system.cpu3.dcache.SwapReq_miss_latency::total 478509 # number of SwapReq miss cycles
2503system.cpu3.dcache.demand_miss_latency::cpu3.data 7328430 # number of demand (read+write) miss cycles
2504system.cpu3.dcache.demand_miss_latency::total 7328430 # number of demand (read+write) miss cycles
2505system.cpu3.dcache.overall_miss_latency::cpu3.data 7328430 # number of overall miss cycles
2506system.cpu3.dcache.overall_miss_latency::total 7328430 # number of overall miss cycles
2507system.cpu3.dcache.ReadReq_accesses::cpu3.data 51069 # number of ReadReq accesses(hits+misses)
2508system.cpu3.dcache.ReadReq_accesses::total 51069 # number of ReadReq accesses(hits+misses)
2509system.cpu3.dcache.WriteReq_accesses::cpu3.data 41890 # number of WriteReq accesses(hits+misses)
2510system.cpu3.dcache.WriteReq_accesses::total 41890 # number of WriteReq accesses(hits+misses)
2511system.cpu3.dcache.SwapReq_accesses::cpu3.data 63 # number of SwapReq accesses(hits+misses)
2512system.cpu3.dcache.SwapReq_accesses::total 63 # number of SwapReq accesses(hits+misses)
2513system.cpu3.dcache.demand_accesses::cpu3.data 92959 # number of demand (read+write) accesses
2514system.cpu3.dcache.demand_accesses::total 92959 # number of demand (read+write) accesses
2515system.cpu3.dcache.overall_accesses::cpu3.data 92959 # number of overall (read+write) accesses
2516system.cpu3.dcache.overall_accesses::total 92959 # number of overall (read+write) accesses
2517system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.006775 # miss rate for ReadReq accesses
2518system.cpu3.dcache.ReadReq_miss_rate::total 0.006775 # miss rate for ReadReq accesses
2519system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003294 # miss rate for WriteReq accesses
2520system.cpu3.dcache.WriteReq_miss_rate::total 0.003294 # miss rate for WriteReq accesses
2521system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.809524 # miss rate for SwapReq accesses
2522system.cpu3.dcache.SwapReq_miss_rate::total 0.809524 # miss rate for SwapReq accesses
2523system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005207 # miss rate for demand accesses
2524system.cpu3.dcache.demand_miss_rate::total 0.005207 # miss rate for demand accesses
2525system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005207 # miss rate for overall accesses
2526system.cpu3.dcache.overall_miss_rate::total 0.005207 # miss rate for overall accesses
2527system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12859.592486 # average ReadReq miss latency
2528system.cpu3.dcache.ReadReq_avg_miss_latency::total 12859.592486 # average ReadReq miss latency
2529system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20862.398551 # average WriteReq miss latency
2530system.cpu3.dcache.WriteReq_avg_miss_latency::total 20862.398551 # average WriteReq miss latency
2531system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9382.529412 # average SwapReq miss latency
2532system.cpu3.dcache.SwapReq_avg_miss_latency::total 9382.529412 # average SwapReq miss latency
2533system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 15141.384298 # average overall miss latency
2534system.cpu3.dcache.demand_avg_miss_latency::total 15141.384298 # average overall miss latency
2535system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 15141.384298 # average overall miss latency
2536system.cpu3.dcache.overall_avg_miss_latency::total 15141.384298 # average overall miss latency
2537system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2538system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2539system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
2540system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
2541system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2542system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2543system.cpu3.dcache.fast_writes 0 # number of fast writes performed
2544system.cpu3.dcache.cache_copies 0 # number of cache copies performed
2545system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 195 # number of ReadReq MSHR hits
2546system.cpu3.dcache.ReadReq_mshr_hits::total 195 # number of ReadReq MSHR hits
2547system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 32 # number of WriteReq MSHR hits
2548system.cpu3.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits
2549system.cpu3.dcache.demand_mshr_hits::cpu3.data 227 # number of demand (read+write) MSHR hits
2550system.cpu3.dcache.demand_mshr_hits::total 227 # number of demand (read+write) MSHR hits
2551system.cpu3.dcache.overall_mshr_hits::cpu3.data 227 # number of overall MSHR hits
2552system.cpu3.dcache.overall_mshr_hits::total 227 # number of overall MSHR hits
2553system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 151 # number of ReadReq MSHR misses
2554system.cpu3.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses
2555system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106 # number of WriteReq MSHR misses
2556system.cpu3.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses
2557system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 51 # number of SwapReq MSHR misses
2558system.cpu3.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses
2559system.cpu3.dcache.demand_mshr_misses::cpu3.data 257 # number of demand (read+write) MSHR misses
2560system.cpu3.dcache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses
2561system.cpu3.dcache.overall_mshr_misses::cpu3.data 257 # number of overall MSHR misses
2562system.cpu3.dcache.overall_mshr_misses::total 257 # number of overall MSHR misses
2563system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1003763 # number of ReadReq MSHR miss cycles
2564system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1003763 # number of ReadReq MSHR miss cycles
2565system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1322239 # number of WriteReq MSHR miss cycles
2566system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1322239 # number of WriteReq MSHR miss cycles
2567system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 376491 # number of SwapReq MSHR miss cycles
2568system.cpu3.dcache.SwapReq_mshr_miss_latency::total 376491 # number of SwapReq MSHR miss cycles
2569system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2326002 # number of demand (read+write) MSHR miss cycles
2570system.cpu3.dcache.demand_mshr_miss_latency::total 2326002 # number of demand (read+write) MSHR miss cycles
2571system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2326002 # number of overall MSHR miss cycles
2572system.cpu3.dcache.overall_mshr_miss_latency::total 2326002 # number of overall MSHR miss cycles
2573system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.002957 # mshr miss rate for ReadReq accesses
2574system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.002957 # mshr miss rate for ReadReq accesses
2575system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002530 # mshr miss rate for WriteReq accesses
2576system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002530 # mshr miss rate for WriteReq accesses
2577system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.809524 # mshr miss rate for SwapReq accesses
2578system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.809524 # mshr miss rate for SwapReq accesses
2579system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002765 # mshr miss rate for demand accesses
2580system.cpu3.dcache.demand_mshr_miss_rate::total 0.002765 # mshr miss rate for demand accesses
2581system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002765 # mshr miss rate for overall accesses
2582system.cpu3.dcache.overall_mshr_miss_rate::total 0.002765 # mshr miss rate for overall accesses
2583system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6647.437086 # average ReadReq mshr miss latency
2584system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6647.437086 # average ReadReq mshr miss latency
2585system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12473.952830 # average WriteReq mshr miss latency
2586system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12473.952830 # average WriteReq mshr miss latency
2587system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7382.176471 # average SwapReq mshr miss latency
2588system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7382.176471 # average SwapReq mshr miss latency
2589system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency
2590system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9050.591440 # average overall mshr miss latency
2591system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency
2592system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9050.591440 # average overall mshr miss latency
2593system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2594
2595---------- End Simulation Statistics ----------