1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000111 # Number of seconds simulated
4sim_ticks 111402500 # Number of ticks simulated
5final_tick 111402500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 79928 # Simulator instruction rate (inst/s)
8host_op_rate 79928 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 8175729 # Simulator tick rate (ticks/s)
10host_mem_usage 236248 # Number of bytes of host memory used
11host_seconds 13.63 # Real time elapsed on the host
12sim_insts 1089093 # Number of instructions simulated
13sim_ops 1089093 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 43072 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 29312 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 0 # Number of bytes written to this memory
17system.physmem.num_reads 673 # Number of read requests responded to by this memory
18system.physmem.num_writes 0 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 386634052 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 263117973 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_total 386634052 # Total bandwidth to/from this memory (bytes/s)
23system.cpu0.workload.num_syscalls 89 # Number of system calls
24system.cpu0.numCycles 222806 # number of cpu cycles simulated
25system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
26system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
27system.cpu0.BPredUnit.lookups 87253 # Number of BP lookups
28system.cpu0.BPredUnit.condPredicted 84917 # Number of conditional branches predicted
29system.cpu0.BPredUnit.condIncorrect 1303 # Number of conditional branches incorrect
30system.cpu0.BPredUnit.BTBLookups 84794 # Number of BTB lookups
--- 283 unchanged lines hidden (view full) ---
314system.cpu0.icache.overall_miss_latency::total 29159500 # number of overall miss cycles
315system.cpu0.icache.ReadReq_accesses::cpu0.inst 6218 # number of ReadReq accesses(hits+misses)
316system.cpu0.icache.ReadReq_accesses::total 6218 # number of ReadReq accesses(hits+misses)
317system.cpu0.icache.demand_accesses::cpu0.inst 6218 # number of demand (read+write) accesses
318system.cpu0.icache.demand_accesses::total 6218 # number of demand (read+write) accesses
319system.cpu0.icache.overall_accesses::cpu0.inst 6218 # number of overall (read+write) accesses
320system.cpu0.icache.overall_accesses::total 6218 # number of overall (read+write) accesses
321system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.122065 # miss rate for ReadReq accesses
322system.cpu0.icache.demand_miss_rate::cpu0.inst 0.122065 # miss rate for demand accesses
323system.cpu0.icache.overall_miss_rate::cpu0.inst 0.122065 # miss rate for overall accesses
324system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38418.313570 # average ReadReq miss latency
325system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38418.313570 # average overall miss latency
326system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38418.313570 # average overall miss latency
327system.cpu0.icache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked
328system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
329system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked
330system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
331system.cpu0.icache.avg_blocked_cycles::no_mshrs 15500 # average number of cycles each access was blocked
332system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
333system.cpu0.icache.fast_writes 0 # number of fast writes performed
334system.cpu0.icache.cache_copies 0 # number of cache copies performed
--- 11 unchanged lines hidden (view full) ---
346system.cpu0.icache.overall_mshr_misses::total 594 # number of overall MSHR misses
347system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21891000 # number of ReadReq MSHR miss cycles
348system.cpu0.icache.ReadReq_mshr_miss_latency::total 21891000 # number of ReadReq MSHR miss cycles
349system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21891000 # number of demand (read+write) MSHR miss cycles
350system.cpu0.icache.demand_mshr_miss_latency::total 21891000 # number of demand (read+write) MSHR miss cycles
351system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21891000 # number of overall MSHR miss cycles
352system.cpu0.icache.overall_mshr_miss_latency::total 21891000 # number of overall MSHR miss cycles
353system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for ReadReq accesses
354system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for demand accesses
355system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for overall accesses
356system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average ReadReq mshr miss latency
357system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average overall mshr miss latency
358system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average overall mshr miss latency
359system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
360system.cpu0.dcache.replacements 8 # number of replacements
361system.cpu0.dcache.tagsinuse 141.285775 # Cycle average of tags in use
362system.cpu0.dcache.total_refs 100453 # Total number of references to valid blocks.
363system.cpu0.dcache.sampled_refs 174 # Sample count of references to valid blocks.
364system.cpu0.dcache.avg_refs 577.316092 # Average number of references to valid blocks.
365system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
366system.cpu0.dcache.occ_blocks::cpu0.data 141.285775 # Average occupied blocks per requestor
--- 35 unchanged lines hidden (view full) ---
402system.cpu0.dcache.WriteReq_accesses::total 81230 # number of WriteReq accesses(hits+misses)
403system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
404system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
405system.cpu0.dcache.demand_accesses::cpu0.data 164751 # number of demand (read+write) accesses
406system.cpu0.dcache.demand_accesses::total 164751 # number of demand (read+write) accesses
407system.cpu0.dcache.overall_accesses::cpu0.data 164751 # number of overall (read+write) accesses
408system.cpu0.dcache.overall_accesses::total 164751 # number of overall (read+write) accesses
409system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005927 # miss rate for ReadReq accesses
410system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006722 # miss rate for WriteReq accesses
411system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.476190 # miss rate for SwapReq accesses
412system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006319 # miss rate for demand accesses
413system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006319 # miss rate for overall accesses
414system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28234.343434 # average ReadReq miss latency
415system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44619.021978 # average WriteReq miss latency
416system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19025 # average SwapReq miss latency
417system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36828.036503 # average overall miss latency
418system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36828.036503 # average overall miss latency
419system.cpu0.dcache.blocked_cycles::no_mshrs 194000 # number of cycles access was blocked
420system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
421system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked
422system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
423system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10210.526316 # average number of cycles each access was blocked
424system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
425system.cpu0.dcache.fast_writes 0 # number of fast writes performed
426system.cpu0.dcache.cache_copies 0 # number of cache copies performed
--- 23 unchanged lines hidden (view full) ---
450system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6250000 # number of WriteReq MSHR miss cycles
451system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 320500 # number of SwapReq MSHR miss cycles
452system.cpu0.dcache.SwapReq_mshr_miss_latency::total 320500 # number of SwapReq MSHR miss cycles
453system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11204500 # number of demand (read+write) MSHR miss cycles
454system.cpu0.dcache.demand_mshr_miss_latency::total 11204500 # number of demand (read+write) MSHR miss cycles
455system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11204500 # number of overall MSHR miss cycles
456system.cpu0.dcache.overall_mshr_miss_latency::total 11204500 # number of overall MSHR miss cycles
457system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002179 # mshr miss rate for ReadReq accesses
458system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002167 # mshr miss rate for WriteReq accesses
459system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.476190 # mshr miss rate for SwapReq accesses
460system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002173 # mshr miss rate for demand accesses
461system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002173 # mshr miss rate for overall accesses
462system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27222.527473 # average ReadReq mshr miss latency
463system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35511.363636 # average WriteReq mshr miss latency
464system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 16025 # average SwapReq mshr miss latency
465system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31297.486034 # average overall mshr miss latency
466system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31297.486034 # average overall mshr miss latency
467system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
468system.cpu1.numCycles 187393 # number of cpu cycles simulated
469system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
470system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
471system.cpu1.BPredUnit.lookups 57495 # Number of BP lookups
472system.cpu1.BPredUnit.condPredicted 54509 # Number of conditional branches predicted
473system.cpu1.BPredUnit.condIncorrect 1432 # Number of conditional branches incorrect
474system.cpu1.BPredUnit.BTBLookups 50945 # Number of BTB lookups
--- 285 unchanged lines hidden (view full) ---
760system.cpu1.icache.overall_miss_latency::total 7500500 # number of overall miss cycles
761system.cpu1.icache.ReadReq_accesses::cpu1.inst 19809 # number of ReadReq accesses(hits+misses)
762system.cpu1.icache.ReadReq_accesses::total 19809 # number of ReadReq accesses(hits+misses)
763system.cpu1.icache.demand_accesses::cpu1.inst 19809 # number of demand (read+write) accesses
764system.cpu1.icache.demand_accesses::total 19809 # number of demand (read+write) accesses
765system.cpu1.icache.overall_accesses::cpu1.inst 19809 # number of overall (read+write) accesses
766system.cpu1.icache.overall_accesses::total 19809 # number of overall (read+write) accesses
767system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.025493 # miss rate for ReadReq accesses
768system.cpu1.icache.demand_miss_rate::cpu1.inst 0.025493 # miss rate for demand accesses
769system.cpu1.icache.overall_miss_rate::cpu1.inst 0.025493 # miss rate for overall accesses
770system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14852.475248 # average ReadReq miss latency
771system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14852.475248 # average overall miss latency
772system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14852.475248 # average overall miss latency
773system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
774system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
775system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
776system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
777system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
778system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
779system.cpu1.icache.fast_writes 0 # number of fast writes performed
780system.cpu1.icache.cache_copies 0 # number of cache copies performed
--- 11 unchanged lines hidden (view full) ---
792system.cpu1.icache.overall_mshr_misses::total 435 # number of overall MSHR misses
793system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5474500 # number of ReadReq MSHR miss cycles
794system.cpu1.icache.ReadReq_mshr_miss_latency::total 5474500 # number of ReadReq MSHR miss cycles
795system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5474500 # number of demand (read+write) MSHR miss cycles
796system.cpu1.icache.demand_mshr_miss_latency::total 5474500 # number of demand (read+write) MSHR miss cycles
797system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5474500 # number of overall MSHR miss cycles
798system.cpu1.icache.overall_mshr_miss_latency::total 5474500 # number of overall MSHR miss cycles
799system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for ReadReq accesses
800system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for demand accesses
801system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for overall accesses
802system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average ReadReq mshr miss latency
803system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average overall mshr miss latency
804system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average overall mshr miss latency
805system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
806system.cpu1.dcache.replacements 2 # number of replacements
807system.cpu1.dcache.tagsinuse 24.070551 # Cycle average of tags in use
808system.cpu1.dcache.total_refs 48111 # Total number of references to valid blocks.
809system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks.
810system.cpu1.dcache.avg_refs 1603.700000 # Average number of references to valid blocks.
811system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
812system.cpu1.dcache.occ_blocks::cpu1.data 24.070551 # Average occupied blocks per requestor
--- 35 unchanged lines hidden (view full) ---
848system.cpu1.dcache.WriteReq_accesses::total 41743 # number of WriteReq accesses(hits+misses)
849system.cpu1.dcache.SwapReq_accesses::cpu1.data 62 # number of SwapReq accesses(hits+misses)
850system.cpu1.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses)
851system.cpu1.dcache.demand_accesses::cpu1.data 93422 # number of demand (read+write) accesses
852system.cpu1.dcache.demand_accesses::total 93422 # number of demand (read+write) accesses
853system.cpu1.dcache.overall_accesses::cpu1.data 93422 # number of overall (read+write) accesses
854system.cpu1.dcache.overall_accesses::total 93422 # number of overall (read+write) accesses
855system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009191 # miss rate for ReadReq accesses
856system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003689 # miss rate for WriteReq accesses
857system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.806452 # miss rate for SwapReq accesses
858system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006733 # miss rate for demand accesses
859system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006733 # miss rate for overall accesses
860system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20285.263158 # average ReadReq miss latency
861system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19269.480519 # average WriteReq miss latency
862system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 20770 # average SwapReq miss latency
863system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20036.565978 # average overall miss latency
864system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20036.565978 # average overall miss latency
865system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
866system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
867system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
868system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
869system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
870system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
871system.cpu1.dcache.fast_writes 0 # number of fast writes performed
872system.cpu1.dcache.cache_copies 0 # number of cache copies performed
--- 23 unchanged lines hidden (view full) ---
896system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1523500 # number of WriteReq MSHR miss cycles
897system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 888500 # number of SwapReq MSHR miss cycles
898system.cpu1.dcache.SwapReq_mshr_miss_latency::total 888500 # number of SwapReq MSHR miss cycles
899system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3575500 # number of demand (read+write) MSHR miss cycles
900system.cpu1.dcache.demand_mshr_miss_latency::total 3575500 # number of demand (read+write) MSHR miss cycles
901system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3575500 # number of overall MSHR miss cycles
902system.cpu1.dcache.overall_mshr_miss_latency::total 3575500 # number of overall MSHR miss cycles
903system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003019 # mshr miss rate for ReadReq accesses
904system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002611 # mshr miss rate for WriteReq accesses
905system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.806452 # mshr miss rate for SwapReq accesses
906system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002837 # mshr miss rate for demand accesses
907system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002837 # mshr miss rate for overall accesses
908system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13153.846154 # average ReadReq mshr miss latency
909system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13977.064220 # average WriteReq mshr miss latency
910system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 17770 # average SwapReq mshr miss latency
911system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13492.452830 # average overall mshr miss latency
912system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13492.452830 # average overall mshr miss latency
913system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
914system.cpu2.numCycles 187102 # number of cpu cycles simulated
915system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
916system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
917system.cpu2.BPredUnit.lookups 52366 # Number of BP lookups
918system.cpu2.BPredUnit.condPredicted 49346 # Number of conditional branches predicted
919system.cpu2.BPredUnit.condIncorrect 1501 # Number of conditional branches incorrect
920system.cpu2.BPredUnit.BTBLookups 45884 # Number of BTB lookups
--- 285 unchanged lines hidden (view full) ---
1206system.cpu2.icache.overall_miss_latency::total 11141500 # number of overall miss cycles
1207system.cpu2.icache.ReadReq_accesses::cpu2.inst 21870 # number of ReadReq accesses(hits+misses)
1208system.cpu2.icache.ReadReq_accesses::total 21870 # number of ReadReq accesses(hits+misses)
1209system.cpu2.icache.demand_accesses::cpu2.inst 21870 # number of demand (read+write) accesses
1210system.cpu2.icache.demand_accesses::total 21870 # number of demand (read+write) accesses
1211system.cpu2.icache.overall_accesses::cpu2.inst 21870 # number of overall (read+write) accesses
1212system.cpu2.icache.overall_accesses::total 21870 # number of overall (read+write) accesses
1213system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.023411 # miss rate for ReadReq accesses
1214system.cpu2.icache.demand_miss_rate::cpu2.inst 0.023411 # miss rate for demand accesses
1215system.cpu2.icache.overall_miss_rate::cpu2.inst 0.023411 # miss rate for overall accesses
1216system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 21760.742188 # average ReadReq miss latency
1217system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 21760.742188 # average overall miss latency
1218system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 21760.742188 # average overall miss latency
1219system.cpu2.icache.blocked_cycles::no_mshrs 33000 # number of cycles access was blocked
1220system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1221system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked
1222system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
1223system.cpu2.icache.avg_blocked_cycles::no_mshrs 33000 # average number of cycles each access was blocked
1224system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1225system.cpu2.icache.fast_writes 0 # number of fast writes performed
1226system.cpu2.icache.cache_copies 0 # number of cache copies performed
--- 11 unchanged lines hidden (view full) ---
1238system.cpu2.icache.overall_mshr_misses::total 440 # number of overall MSHR misses
1239system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 8467000 # number of ReadReq MSHR miss cycles
1240system.cpu2.icache.ReadReq_mshr_miss_latency::total 8467000 # number of ReadReq MSHR miss cycles
1241system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 8467000 # number of demand (read+write) MSHR miss cycles
1242system.cpu2.icache.demand_mshr_miss_latency::total 8467000 # number of demand (read+write) MSHR miss cycles
1243system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 8467000 # number of overall MSHR miss cycles
1244system.cpu2.icache.overall_mshr_miss_latency::total 8467000 # number of overall MSHR miss cycles
1245system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for ReadReq accesses
1246system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for demand accesses
1247system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for overall accesses
1248system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average ReadReq mshr miss latency
1249system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average overall mshr miss latency
1250system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average overall mshr miss latency
1251system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1252system.cpu2.dcache.replacements 2 # number of replacements
1253system.cpu2.dcache.tagsinuse 26.720433 # Cycle average of tags in use
1254system.cpu2.dcache.total_refs 41712 # Total number of references to valid blocks.
1255system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks.
1256system.cpu2.dcache.avg_refs 1345.548387 # Average number of references to valid blocks.
1257system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1258system.cpu2.dcache.occ_blocks::cpu2.data 26.720433 # Average occupied blocks per requestor
--- 35 unchanged lines hidden (view full) ---
1294system.cpu2.dcache.WriteReq_accesses::total 35290 # number of WriteReq accesses(hits+misses)
1295system.cpu2.dcache.SwapReq_accesses::cpu2.data 76 # number of SwapReq accesses(hits+misses)
1296system.cpu2.dcache.SwapReq_accesses::total 76 # number of SwapReq accesses(hits+misses)
1297system.cpu2.dcache.demand_accesses::cpu2.data 81444 # number of demand (read+write) accesses
1298system.cpu2.dcache.demand_accesses::total 81444 # number of demand (read+write) accesses
1299system.cpu2.dcache.overall_accesses::cpu2.data 81444 # number of overall (read+write) accesses
1300system.cpu2.dcache.overall_accesses::total 81444 # number of overall (read+write) accesses
1301system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009490 # miss rate for ReadReq accesses
1302system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004137 # miss rate for WriteReq accesses
1303system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.815789 # miss rate for SwapReq accesses
1304system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007171 # miss rate for demand accesses
1305system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007171 # miss rate for overall accesses
1306system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23413.242009 # average ReadReq miss latency
1307system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20116.438356 # average WriteReq miss latency
1308system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 19048.387097 # average SwapReq miss latency
1309system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22589.041096 # average overall miss latency
1310system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22589.041096 # average overall miss latency
1311system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1312system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1313system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1314system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
1315system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1316system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1317system.cpu2.dcache.fast_writes 0 # number of fast writes performed
1318system.cpu2.dcache.cache_copies 0 # number of cache copies performed
--- 23 unchanged lines hidden (view full) ---
1342system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1516500 # number of WriteReq MSHR miss cycles
1343system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 995000 # number of SwapReq MSHR miss cycles
1344system.cpu2.dcache.SwapReq_mshr_miss_latency::total 995000 # number of SwapReq MSHR miss cycles
1345system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3996500 # number of demand (read+write) MSHR miss cycles
1346system.cpu2.dcache.demand_mshr_miss_latency::total 3996500 # number of demand (read+write) MSHR miss cycles
1347system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3996500 # number of overall MSHR miss cycles
1348system.cpu2.dcache.overall_mshr_miss_latency::total 3996500 # number of overall MSHR miss cycles
1349system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003705 # mshr miss rate for ReadReq accesses
1350system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002862 # mshr miss rate for WriteReq accesses
1351system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.815789 # mshr miss rate for SwapReq accesses
1352system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003340 # mshr miss rate for demand accesses
1353system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003340 # mshr miss rate for overall accesses
1354system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14502.923977 # average ReadReq mshr miss latency
1355system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15014.851485 # average WriteReq mshr miss latency
1356system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 16048.387097 # average SwapReq mshr miss latency
1357system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14693.014706 # average overall mshr miss latency
1358system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14693.014706 # average overall mshr miss latency
1359system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1360system.cpu3.numCycles 186832 # number of cpu cycles simulated
1361system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
1362system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
1363system.cpu3.BPredUnit.lookups 49447 # Number of BP lookups
1364system.cpu3.BPredUnit.condPredicted 46344 # Number of conditional branches predicted
1365system.cpu3.BPredUnit.condIncorrect 1525 # Number of conditional branches incorrect
1366system.cpu3.BPredUnit.BTBLookups 42752 # Number of BTB lookups
--- 285 unchanged lines hidden (view full) ---
1652system.cpu3.icache.overall_miss_latency::total 6843000 # number of overall miss cycles
1653system.cpu3.icache.ReadReq_accesses::cpu3.inst 24454 # number of ReadReq accesses(hits+misses)
1654system.cpu3.icache.ReadReq_accesses::total 24454 # number of ReadReq accesses(hits+misses)
1655system.cpu3.icache.demand_accesses::cpu3.inst 24454 # number of demand (read+write) accesses
1656system.cpu3.icache.demand_accesses::total 24454 # number of demand (read+write) accesses
1657system.cpu3.icache.overall_accesses::cpu3.inst 24454 # number of overall (read+write) accesses
1658system.cpu3.icache.overall_accesses::total 24454 # number of overall (read+write) accesses
1659system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020569 # miss rate for ReadReq accesses
1660system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020569 # miss rate for demand accesses
1661system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020569 # miss rate for overall accesses
1662system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13604.373757 # average ReadReq miss latency
1663system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13604.373757 # average overall miss latency
1664system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13604.373757 # average overall miss latency
1665system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1666system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1667system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1668system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
1669system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1670system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1671system.cpu3.icache.fast_writes 0 # number of fast writes performed
1672system.cpu3.icache.cache_copies 0 # number of cache copies performed
--- 11 unchanged lines hidden (view full) ---
1684system.cpu3.icache.overall_mshr_misses::total 432 # number of overall MSHR misses
1685system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4912000 # number of ReadReq MSHR miss cycles
1686system.cpu3.icache.ReadReq_mshr_miss_latency::total 4912000 # number of ReadReq MSHR miss cycles
1687system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4912000 # number of demand (read+write) MSHR miss cycles
1688system.cpu3.icache.demand_mshr_miss_latency::total 4912000 # number of demand (read+write) MSHR miss cycles
1689system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4912000 # number of overall MSHR miss cycles
1690system.cpu3.icache.overall_mshr_miss_latency::total 4912000 # number of overall MSHR miss cycles
1691system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for ReadReq accesses
1692system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for demand accesses
1693system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for overall accesses
1694system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average ReadReq mshr miss latency
1695system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average overall mshr miss latency
1696system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average overall mshr miss latency
1697system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1698system.cpu3.dcache.replacements 2 # number of replacements
1699system.cpu3.dcache.tagsinuse 25.290478 # Cycle average of tags in use
1700system.cpu3.dcache.total_refs 37716 # Total number of references to valid blocks.
1701system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks.
1702system.cpu3.dcache.avg_refs 1257.200000 # Average number of references to valid blocks.
1703system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1704system.cpu3.dcache.occ_blocks::cpu3.data 25.290478 # Average occupied blocks per requestor
--- 35 unchanged lines hidden (view full) ---
1740system.cpu3.dcache.WriteReq_accesses::total 31338 # number of WriteReq accesses(hits+misses)
1741system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses)
1742system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
1743system.cpu3.dcache.demand_accesses::cpu3.data 74691 # number of demand (read+write) accesses
1744system.cpu3.dcache.demand_accesses::total 74691 # number of demand (read+write) accesses
1745system.cpu3.dcache.overall_accesses::cpu3.data 74691 # number of overall (read+write) accesses
1746system.cpu3.dcache.overall_accesses::total 74691 # number of overall (read+write) accesses
1747system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009688 # miss rate for ReadReq accesses
1748system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004755 # miss rate for WriteReq accesses
1749system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses
1750system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007618 # miss rate for demand accesses
1751system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007618 # miss rate for overall accesses
1752system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 20514.285714 # average ReadReq miss latency
1753system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20184.563758 # average WriteReq miss latency
1754system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 21017.543860 # average SwapReq miss latency
1755system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 20427.943761 # average overall miss latency
1756system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 20427.943761 # average overall miss latency
1757system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1758system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1759system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1760system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
1761system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1762system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1763system.cpu3.dcache.fast_writes 0 # number of fast writes performed
1764system.cpu3.dcache.cache_copies 0 # number of cache copies performed
--- 23 unchanged lines hidden (view full) ---
1788system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1621000 # number of WriteReq MSHR miss cycles
1789system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 1027000 # number of SwapReq MSHR miss cycles
1790system.cpu3.dcache.SwapReq_mshr_miss_latency::total 1027000 # number of SwapReq MSHR miss cycles
1791system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3772000 # number of demand (read+write) MSHR miss cycles
1792system.cpu3.dcache.demand_mshr_miss_latency::total 3772000 # number of demand (read+write) MSHR miss cycles
1793system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3772000 # number of overall MSHR miss cycles
1794system.cpu3.dcache.overall_mshr_miss_latency::total 3772000 # number of overall MSHR miss cycles
1795system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003760 # mshr miss rate for ReadReq accesses
1796system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003319 # mshr miss rate for WriteReq accesses
1797system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses
1798system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003575 # mshr miss rate for demand accesses
1799system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003575 # mshr miss rate for overall accesses
1800system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13196.319018 # average ReadReq mshr miss latency
1801system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15586.538462 # average WriteReq mshr miss latency
1802system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 18017.543860 # average SwapReq mshr miss latency
1803system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14127.340824 # average overall mshr miss latency
1804system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14127.340824 # average overall mshr miss latency
1805system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1806system.l2c.replacements 0 # number of replacements
1807system.l2c.tagsinuse 441.136869 # Cycle average of tags in use
1808system.l2c.total_refs 1471 # Total number of references to valid blocks.
1809system.l2c.sampled_refs 544 # Sample count of references to valid blocks.
1810system.l2c.avg_refs 2.704044 # Average number of references to valid blocks.
1811system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1812system.l2c.occ_blocks::writebacks 4.878414 # Average occupied blocks per requestor
--- 161 unchanged lines hidden (view full) ---
1974system.l2c.ReadReq_miss_rate::cpu0.inst 0.611111 # miss rate for ReadReq accesses
1975system.l2c.ReadReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadReq accesses
1976system.l2c.ReadReq_miss_rate::cpu1.inst 0.034483 # miss rate for ReadReq accesses
1977system.l2c.ReadReq_miss_rate::cpu1.data 0.071429 # miss rate for ReadReq accesses
1978system.l2c.ReadReq_miss_rate::cpu2.inst 0.193182 # miss rate for ReadReq accesses
1979system.l2c.ReadReq_miss_rate::cpu2.data 0.500000 # miss rate for ReadReq accesses
1980system.l2c.ReadReq_miss_rate::cpu3.inst 0.004630 # miss rate for ReadReq accesses
1981system.l2c.ReadReq_miss_rate::cpu3.data 0.071429 # miss rate for ReadReq accesses
1982system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses
1983system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
1984system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
1985system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
1986system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
1987system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
1988system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
1989system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
1990system.l2c.demand_miss_rate::cpu0.inst 0.611111 # miss rate for demand accesses
1991system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses
1992system.l2c.demand_miss_rate::cpu1.inst 0.034483 # miss rate for demand accesses
1993system.l2c.demand_miss_rate::cpu1.data 0.500000 # miss rate for demand accesses
1994system.l2c.demand_miss_rate::cpu2.inst 0.193182 # miss rate for demand accesses
1995system.l2c.demand_miss_rate::cpu2.data 0.740741 # miss rate for demand accesses
1996system.l2c.demand_miss_rate::cpu3.inst 0.004630 # miss rate for demand accesses
1997system.l2c.demand_miss_rate::cpu3.data 0.500000 # miss rate for demand accesses
1998system.l2c.overall_miss_rate::cpu0.inst 0.611111 # miss rate for overall accesses
1999system.l2c.overall_miss_rate::cpu0.data 0.971264 # miss rate for overall accesses
2000system.l2c.overall_miss_rate::cpu1.inst 0.034483 # miss rate for overall accesses
2001system.l2c.overall_miss_rate::cpu1.data 0.500000 # miss rate for overall accesses
2002system.l2c.overall_miss_rate::cpu2.inst 0.193182 # miss rate for overall accesses
2003system.l2c.overall_miss_rate::cpu2.data 0.740741 # miss rate for overall accesses
2004system.l2c.overall_miss_rate::cpu3.inst 0.004630 # miss rate for overall accesses
2005system.l2c.overall_miss_rate::cpu3.data 0.500000 # miss rate for overall accesses
2006system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52119.834711 # average ReadReq miss latency
2007system.l2c.ReadReq_avg_miss_latency::cpu0.data 52393.333333 # average ReadReq miss latency
2008system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49633.333333 # average ReadReq miss latency
2009system.l2c.ReadReq_avg_miss_latency::cpu1.data 52500 # average ReadReq miss latency
2010system.l2c.ReadReq_avg_miss_latency::cpu2.inst 51482.352941 # average ReadReq miss latency
2011system.l2c.ReadReq_avg_miss_latency::cpu2.data 52285.714286 # average ReadReq miss latency
2012system.l2c.ReadReq_avg_miss_latency::cpu3.inst 49750 # average ReadReq miss latency
2013system.l2c.ReadReq_avg_miss_latency::cpu3.data 52500 # average ReadReq miss latency
2014system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2500 # average UpgradeReq miss latency
2015system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 3088.235294 # average UpgradeReq miss latency
2016system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 2625 # average UpgradeReq miss latency
2017system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52547.872340 # average ReadExReq miss latency
2018system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52291.666667 # average ReadExReq miss latency
2019system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52346.153846 # average ReadExReq miss latency
2020system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52291.666667 # average ReadExReq miss latency
2021system.l2c.demand_avg_miss_latency::cpu0.inst 52119.834711 # average overall miss latency
2022system.l2c.demand_avg_miss_latency::cpu0.data 52479.289941 # average overall miss latency
2023system.l2c.demand_avg_miss_latency::cpu1.inst 49633.333333 # average overall miss latency
2024system.l2c.demand_avg_miss_latency::cpu1.data 52307.692308 # average overall miss latency
2025system.l2c.demand_avg_miss_latency::cpu2.inst 51482.352941 # average overall miss latency
2026system.l2c.demand_avg_miss_latency::cpu2.data 52325 # average overall miss latency
2027system.l2c.demand_avg_miss_latency::cpu3.inst 49750 # average overall miss latency
2028system.l2c.demand_avg_miss_latency::cpu3.data 52307.692308 # average overall miss latency
2029system.l2c.overall_avg_miss_latency::cpu0.inst 52119.834711 # average overall miss latency
2030system.l2c.overall_avg_miss_latency::cpu0.data 52479.289941 # average overall miss latency
2031system.l2c.overall_avg_miss_latency::cpu1.inst 49633.333333 # average overall miss latency
2032system.l2c.overall_avg_miss_latency::cpu1.data 52307.692308 # average overall miss latency
2033system.l2c.overall_avg_miss_latency::cpu2.inst 51482.352941 # average overall miss latency
2034system.l2c.overall_avg_miss_latency::cpu2.data 52325 # average overall miss latency
2035system.l2c.overall_avg_miss_latency::cpu3.inst 49750 # average overall miss latency
2036system.l2c.overall_avg_miss_latency::cpu3.data 52307.692308 # average overall miss latency
2037system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2038system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2039system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
2040system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2041system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2042system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2043system.l2c.fast_writes 0 # number of fast writes performed
2044system.l2c.cache_copies 0 # number of cache copies performed
--- 86 unchanged lines hidden (view full) ---
2131system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for ReadReq accesses
2132system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadReq accesses
2133system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for ReadReq accesses
2134system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.071429 # mshr miss rate for ReadReq accesses
2135system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.181818 # mshr miss rate for ReadReq accesses
2136system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.500000 # mshr miss rate for ReadReq accesses
2137system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for ReadReq accesses
2138system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.071429 # mshr miss rate for ReadReq accesses
2139system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses
2140system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2141system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
2142system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
2143system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
2144system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
2145system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
2146system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
2147system.l2c.demand_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for demand accesses
2148system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses
2149system.l2c.demand_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for demand accesses
2150system.l2c.demand_mshr_miss_rate::cpu1.data 0.500000 # mshr miss rate for demand accesses
2151system.l2c.demand_mshr_miss_rate::cpu2.inst 0.181818 # mshr miss rate for demand accesses
2152system.l2c.demand_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for demand accesses
2153system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for demand accesses
2154system.l2c.demand_mshr_miss_rate::cpu3.data 0.500000 # mshr miss rate for demand accesses
2155system.l2c.overall_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for overall accesses
2156system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses
2157system.l2c.overall_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for overall accesses
2158system.l2c.overall_mshr_miss_rate::cpu1.data 0.500000 # mshr miss rate for overall accesses
2159system.l2c.overall_mshr_miss_rate::cpu2.inst 0.181818 # mshr miss rate for overall accesses
2160system.l2c.overall_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for overall accesses
2161system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for overall accesses
2162system.l2c.overall_mshr_miss_rate::cpu3.data 0.500000 # mshr miss rate for overall accesses
2163system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average ReadReq mshr miss latency
2164system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40220 # average ReadReq mshr miss latency
2165system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency
2166system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency
2167system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency
2168system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency
2169system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency
2170system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency
2171system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency
2172system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency
2173system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency
2174system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency
2175system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40351.063830 # average ReadExReq mshr miss latency
2176system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40125 # average ReadExReq mshr miss latency
2177system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40192.307692 # average ReadExReq mshr miss latency
2178system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40125 # average ReadExReq mshr miss latency
2179system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average overall mshr miss latency
2180system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40292.899408 # average overall mshr miss latency
2181system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency
2182system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40115.384615 # average overall mshr miss latency
2183system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
2184system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40125 # average overall mshr miss latency
2185system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
2186system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency
2187system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average overall mshr miss latency
2188system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40292.899408 # average overall mshr miss latency
2189system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency
2190system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40115.384615 # average overall mshr miss latency
2191system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
2192system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40125 # average overall mshr miss latency
2193system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
2194system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency
2195system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2196
2197---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000111 # Number of seconds simulated
4sim_ticks 111402500 # Number of ticks simulated
5final_tick 111402500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 79928 # Simulator instruction rate (inst/s)
8host_op_rate 79928 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 8175729 # Simulator tick rate (ticks/s)
10host_mem_usage 236248 # Number of bytes of host memory used
11host_seconds 13.63 # Real time elapsed on the host
12sim_insts 1089093 # Number of instructions simulated
13sim_ops 1089093 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 43072 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 29312 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 0 # Number of bytes written to this memory
17system.physmem.num_reads 673 # Number of read requests responded to by this memory
18system.physmem.num_writes 0 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 386634052 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 263117973 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_total 386634052 # Total bandwidth to/from this memory (bytes/s)
23system.cpu0.workload.num_syscalls 89 # Number of system calls
24system.cpu0.numCycles 222806 # number of cpu cycles simulated
25system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
26system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
27system.cpu0.BPredUnit.lookups 87253 # Number of BP lookups
28system.cpu0.BPredUnit.condPredicted 84917 # Number of conditional branches predicted
29system.cpu0.BPredUnit.condIncorrect 1303 # Number of conditional branches incorrect
30system.cpu0.BPredUnit.BTBLookups 84794 # Number of BTB lookups
--- 283 unchanged lines hidden (view full) ---
314system.cpu0.icache.overall_miss_latency::total 29159500 # number of overall miss cycles
315system.cpu0.icache.ReadReq_accesses::cpu0.inst 6218 # number of ReadReq accesses(hits+misses)
316system.cpu0.icache.ReadReq_accesses::total 6218 # number of ReadReq accesses(hits+misses)
317system.cpu0.icache.demand_accesses::cpu0.inst 6218 # number of demand (read+write) accesses
318system.cpu0.icache.demand_accesses::total 6218 # number of demand (read+write) accesses
319system.cpu0.icache.overall_accesses::cpu0.inst 6218 # number of overall (read+write) accesses
320system.cpu0.icache.overall_accesses::total 6218 # number of overall (read+write) accesses
321system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.122065 # miss rate for ReadReq accesses
322system.cpu0.icache.demand_miss_rate::cpu0.inst 0.122065 # miss rate for demand accesses
323system.cpu0.icache.overall_miss_rate::cpu0.inst 0.122065 # miss rate for overall accesses
324system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38418.313570 # average ReadReq miss latency
325system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38418.313570 # average overall miss latency
326system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38418.313570 # average overall miss latency
327system.cpu0.icache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked
328system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
329system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked
330system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
331system.cpu0.icache.avg_blocked_cycles::no_mshrs 15500 # average number of cycles each access was blocked
332system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
333system.cpu0.icache.fast_writes 0 # number of fast writes performed
334system.cpu0.icache.cache_copies 0 # number of cache copies performed
--- 11 unchanged lines hidden (view full) ---
346system.cpu0.icache.overall_mshr_misses::total 594 # number of overall MSHR misses
347system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21891000 # number of ReadReq MSHR miss cycles
348system.cpu0.icache.ReadReq_mshr_miss_latency::total 21891000 # number of ReadReq MSHR miss cycles
349system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21891000 # number of demand (read+write) MSHR miss cycles
350system.cpu0.icache.demand_mshr_miss_latency::total 21891000 # number of demand (read+write) MSHR miss cycles
351system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21891000 # number of overall MSHR miss cycles
352system.cpu0.icache.overall_mshr_miss_latency::total 21891000 # number of overall MSHR miss cycles
353system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for ReadReq accesses
354system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for demand accesses
355system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for overall accesses
356system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average ReadReq mshr miss latency
357system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average overall mshr miss latency
358system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average overall mshr miss latency
359system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
360system.cpu0.dcache.replacements 8 # number of replacements
361system.cpu0.dcache.tagsinuse 141.285775 # Cycle average of tags in use
362system.cpu0.dcache.total_refs 100453 # Total number of references to valid blocks.
363system.cpu0.dcache.sampled_refs 174 # Sample count of references to valid blocks.
364system.cpu0.dcache.avg_refs 577.316092 # Average number of references to valid blocks.
365system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
366system.cpu0.dcache.occ_blocks::cpu0.data 141.285775 # Average occupied blocks per requestor
--- 35 unchanged lines hidden (view full) ---
402system.cpu0.dcache.WriteReq_accesses::total 81230 # number of WriteReq accesses(hits+misses)
403system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
404system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
405system.cpu0.dcache.demand_accesses::cpu0.data 164751 # number of demand (read+write) accesses
406system.cpu0.dcache.demand_accesses::total 164751 # number of demand (read+write) accesses
407system.cpu0.dcache.overall_accesses::cpu0.data 164751 # number of overall (read+write) accesses
408system.cpu0.dcache.overall_accesses::total 164751 # number of overall (read+write) accesses
409system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005927 # miss rate for ReadReq accesses
410system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006722 # miss rate for WriteReq accesses
411system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.476190 # miss rate for SwapReq accesses
412system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006319 # miss rate for demand accesses
413system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006319 # miss rate for overall accesses
414system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28234.343434 # average ReadReq miss latency
415system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44619.021978 # average WriteReq miss latency
416system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19025 # average SwapReq miss latency
417system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36828.036503 # average overall miss latency
418system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36828.036503 # average overall miss latency
419system.cpu0.dcache.blocked_cycles::no_mshrs 194000 # number of cycles access was blocked
420system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
421system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked
422system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
423system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10210.526316 # average number of cycles each access was blocked
424system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
425system.cpu0.dcache.fast_writes 0 # number of fast writes performed
426system.cpu0.dcache.cache_copies 0 # number of cache copies performed
--- 23 unchanged lines hidden (view full) ---
450system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6250000 # number of WriteReq MSHR miss cycles
451system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 320500 # number of SwapReq MSHR miss cycles
452system.cpu0.dcache.SwapReq_mshr_miss_latency::total 320500 # number of SwapReq MSHR miss cycles
453system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11204500 # number of demand (read+write) MSHR miss cycles
454system.cpu0.dcache.demand_mshr_miss_latency::total 11204500 # number of demand (read+write) MSHR miss cycles
455system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11204500 # number of overall MSHR miss cycles
456system.cpu0.dcache.overall_mshr_miss_latency::total 11204500 # number of overall MSHR miss cycles
457system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002179 # mshr miss rate for ReadReq accesses
458system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002167 # mshr miss rate for WriteReq accesses
459system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.476190 # mshr miss rate for SwapReq accesses
460system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002173 # mshr miss rate for demand accesses
461system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002173 # mshr miss rate for overall accesses
462system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27222.527473 # average ReadReq mshr miss latency
463system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35511.363636 # average WriteReq mshr miss latency
464system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 16025 # average SwapReq mshr miss latency
465system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31297.486034 # average overall mshr miss latency
466system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31297.486034 # average overall mshr miss latency
467system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
468system.cpu1.numCycles 187393 # number of cpu cycles simulated
469system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
470system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
471system.cpu1.BPredUnit.lookups 57495 # Number of BP lookups
472system.cpu1.BPredUnit.condPredicted 54509 # Number of conditional branches predicted
473system.cpu1.BPredUnit.condIncorrect 1432 # Number of conditional branches incorrect
474system.cpu1.BPredUnit.BTBLookups 50945 # Number of BTB lookups
--- 285 unchanged lines hidden (view full) ---
760system.cpu1.icache.overall_miss_latency::total 7500500 # number of overall miss cycles
761system.cpu1.icache.ReadReq_accesses::cpu1.inst 19809 # number of ReadReq accesses(hits+misses)
762system.cpu1.icache.ReadReq_accesses::total 19809 # number of ReadReq accesses(hits+misses)
763system.cpu1.icache.demand_accesses::cpu1.inst 19809 # number of demand (read+write) accesses
764system.cpu1.icache.demand_accesses::total 19809 # number of demand (read+write) accesses
765system.cpu1.icache.overall_accesses::cpu1.inst 19809 # number of overall (read+write) accesses
766system.cpu1.icache.overall_accesses::total 19809 # number of overall (read+write) accesses
767system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.025493 # miss rate for ReadReq accesses
768system.cpu1.icache.demand_miss_rate::cpu1.inst 0.025493 # miss rate for demand accesses
769system.cpu1.icache.overall_miss_rate::cpu1.inst 0.025493 # miss rate for overall accesses
770system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14852.475248 # average ReadReq miss latency
771system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14852.475248 # average overall miss latency
772system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14852.475248 # average overall miss latency
773system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
774system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
775system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
776system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
777system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
778system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
779system.cpu1.icache.fast_writes 0 # number of fast writes performed
780system.cpu1.icache.cache_copies 0 # number of cache copies performed
--- 11 unchanged lines hidden (view full) ---
792system.cpu1.icache.overall_mshr_misses::total 435 # number of overall MSHR misses
793system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5474500 # number of ReadReq MSHR miss cycles
794system.cpu1.icache.ReadReq_mshr_miss_latency::total 5474500 # number of ReadReq MSHR miss cycles
795system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5474500 # number of demand (read+write) MSHR miss cycles
796system.cpu1.icache.demand_mshr_miss_latency::total 5474500 # number of demand (read+write) MSHR miss cycles
797system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5474500 # number of overall MSHR miss cycles
798system.cpu1.icache.overall_mshr_miss_latency::total 5474500 # number of overall MSHR miss cycles
799system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for ReadReq accesses
800system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for demand accesses
801system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for overall accesses
802system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average ReadReq mshr miss latency
803system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average overall mshr miss latency
804system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average overall mshr miss latency
805system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
806system.cpu1.dcache.replacements 2 # number of replacements
807system.cpu1.dcache.tagsinuse 24.070551 # Cycle average of tags in use
808system.cpu1.dcache.total_refs 48111 # Total number of references to valid blocks.
809system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks.
810system.cpu1.dcache.avg_refs 1603.700000 # Average number of references to valid blocks.
811system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
812system.cpu1.dcache.occ_blocks::cpu1.data 24.070551 # Average occupied blocks per requestor
--- 35 unchanged lines hidden (view full) ---
848system.cpu1.dcache.WriteReq_accesses::total 41743 # number of WriteReq accesses(hits+misses)
849system.cpu1.dcache.SwapReq_accesses::cpu1.data 62 # number of SwapReq accesses(hits+misses)
850system.cpu1.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses)
851system.cpu1.dcache.demand_accesses::cpu1.data 93422 # number of demand (read+write) accesses
852system.cpu1.dcache.demand_accesses::total 93422 # number of demand (read+write) accesses
853system.cpu1.dcache.overall_accesses::cpu1.data 93422 # number of overall (read+write) accesses
854system.cpu1.dcache.overall_accesses::total 93422 # number of overall (read+write) accesses
855system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009191 # miss rate for ReadReq accesses
856system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003689 # miss rate for WriteReq accesses
857system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.806452 # miss rate for SwapReq accesses
858system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006733 # miss rate for demand accesses
859system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006733 # miss rate for overall accesses
860system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20285.263158 # average ReadReq miss latency
861system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19269.480519 # average WriteReq miss latency
862system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 20770 # average SwapReq miss latency
863system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20036.565978 # average overall miss latency
864system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20036.565978 # average overall miss latency
865system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
866system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
867system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
868system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
869system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
870system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
871system.cpu1.dcache.fast_writes 0 # number of fast writes performed
872system.cpu1.dcache.cache_copies 0 # number of cache copies performed
--- 23 unchanged lines hidden (view full) ---
896system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1523500 # number of WriteReq MSHR miss cycles
897system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 888500 # number of SwapReq MSHR miss cycles
898system.cpu1.dcache.SwapReq_mshr_miss_latency::total 888500 # number of SwapReq MSHR miss cycles
899system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3575500 # number of demand (read+write) MSHR miss cycles
900system.cpu1.dcache.demand_mshr_miss_latency::total 3575500 # number of demand (read+write) MSHR miss cycles
901system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3575500 # number of overall MSHR miss cycles
902system.cpu1.dcache.overall_mshr_miss_latency::total 3575500 # number of overall MSHR miss cycles
903system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003019 # mshr miss rate for ReadReq accesses
904system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002611 # mshr miss rate for WriteReq accesses
905system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.806452 # mshr miss rate for SwapReq accesses
906system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002837 # mshr miss rate for demand accesses
907system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002837 # mshr miss rate for overall accesses
908system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13153.846154 # average ReadReq mshr miss latency
909system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13977.064220 # average WriteReq mshr miss latency
910system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 17770 # average SwapReq mshr miss latency
911system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13492.452830 # average overall mshr miss latency
912system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13492.452830 # average overall mshr miss latency
913system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
914system.cpu2.numCycles 187102 # number of cpu cycles simulated
915system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
916system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
917system.cpu2.BPredUnit.lookups 52366 # Number of BP lookups
918system.cpu2.BPredUnit.condPredicted 49346 # Number of conditional branches predicted
919system.cpu2.BPredUnit.condIncorrect 1501 # Number of conditional branches incorrect
920system.cpu2.BPredUnit.BTBLookups 45884 # Number of BTB lookups
--- 285 unchanged lines hidden (view full) ---
1206system.cpu2.icache.overall_miss_latency::total 11141500 # number of overall miss cycles
1207system.cpu2.icache.ReadReq_accesses::cpu2.inst 21870 # number of ReadReq accesses(hits+misses)
1208system.cpu2.icache.ReadReq_accesses::total 21870 # number of ReadReq accesses(hits+misses)
1209system.cpu2.icache.demand_accesses::cpu2.inst 21870 # number of demand (read+write) accesses
1210system.cpu2.icache.demand_accesses::total 21870 # number of demand (read+write) accesses
1211system.cpu2.icache.overall_accesses::cpu2.inst 21870 # number of overall (read+write) accesses
1212system.cpu2.icache.overall_accesses::total 21870 # number of overall (read+write) accesses
1213system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.023411 # miss rate for ReadReq accesses
1214system.cpu2.icache.demand_miss_rate::cpu2.inst 0.023411 # miss rate for demand accesses
1215system.cpu2.icache.overall_miss_rate::cpu2.inst 0.023411 # miss rate for overall accesses
1216system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 21760.742188 # average ReadReq miss latency
1217system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 21760.742188 # average overall miss latency
1218system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 21760.742188 # average overall miss latency
1219system.cpu2.icache.blocked_cycles::no_mshrs 33000 # number of cycles access was blocked
1220system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1221system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked
1222system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
1223system.cpu2.icache.avg_blocked_cycles::no_mshrs 33000 # average number of cycles each access was blocked
1224system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1225system.cpu2.icache.fast_writes 0 # number of fast writes performed
1226system.cpu2.icache.cache_copies 0 # number of cache copies performed
--- 11 unchanged lines hidden (view full) ---
1238system.cpu2.icache.overall_mshr_misses::total 440 # number of overall MSHR misses
1239system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 8467000 # number of ReadReq MSHR miss cycles
1240system.cpu2.icache.ReadReq_mshr_miss_latency::total 8467000 # number of ReadReq MSHR miss cycles
1241system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 8467000 # number of demand (read+write) MSHR miss cycles
1242system.cpu2.icache.demand_mshr_miss_latency::total 8467000 # number of demand (read+write) MSHR miss cycles
1243system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 8467000 # number of overall MSHR miss cycles
1244system.cpu2.icache.overall_mshr_miss_latency::total 8467000 # number of overall MSHR miss cycles
1245system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for ReadReq accesses
1246system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for demand accesses
1247system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for overall accesses
1248system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average ReadReq mshr miss latency
1249system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average overall mshr miss latency
1250system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average overall mshr miss latency
1251system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1252system.cpu2.dcache.replacements 2 # number of replacements
1253system.cpu2.dcache.tagsinuse 26.720433 # Cycle average of tags in use
1254system.cpu2.dcache.total_refs 41712 # Total number of references to valid blocks.
1255system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks.
1256system.cpu2.dcache.avg_refs 1345.548387 # Average number of references to valid blocks.
1257system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1258system.cpu2.dcache.occ_blocks::cpu2.data 26.720433 # Average occupied blocks per requestor
--- 35 unchanged lines hidden (view full) ---
1294system.cpu2.dcache.WriteReq_accesses::total 35290 # number of WriteReq accesses(hits+misses)
1295system.cpu2.dcache.SwapReq_accesses::cpu2.data 76 # number of SwapReq accesses(hits+misses)
1296system.cpu2.dcache.SwapReq_accesses::total 76 # number of SwapReq accesses(hits+misses)
1297system.cpu2.dcache.demand_accesses::cpu2.data 81444 # number of demand (read+write) accesses
1298system.cpu2.dcache.demand_accesses::total 81444 # number of demand (read+write) accesses
1299system.cpu2.dcache.overall_accesses::cpu2.data 81444 # number of overall (read+write) accesses
1300system.cpu2.dcache.overall_accesses::total 81444 # number of overall (read+write) accesses
1301system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009490 # miss rate for ReadReq accesses
1302system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004137 # miss rate for WriteReq accesses
1303system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.815789 # miss rate for SwapReq accesses
1304system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007171 # miss rate for demand accesses
1305system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007171 # miss rate for overall accesses
1306system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23413.242009 # average ReadReq miss latency
1307system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20116.438356 # average WriteReq miss latency
1308system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 19048.387097 # average SwapReq miss latency
1309system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22589.041096 # average overall miss latency
1310system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22589.041096 # average overall miss latency
1311system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1312system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1313system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1314system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
1315system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1316system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1317system.cpu2.dcache.fast_writes 0 # number of fast writes performed
1318system.cpu2.dcache.cache_copies 0 # number of cache copies performed
--- 23 unchanged lines hidden (view full) ---
1342system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1516500 # number of WriteReq MSHR miss cycles
1343system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 995000 # number of SwapReq MSHR miss cycles
1344system.cpu2.dcache.SwapReq_mshr_miss_latency::total 995000 # number of SwapReq MSHR miss cycles
1345system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3996500 # number of demand (read+write) MSHR miss cycles
1346system.cpu2.dcache.demand_mshr_miss_latency::total 3996500 # number of demand (read+write) MSHR miss cycles
1347system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3996500 # number of overall MSHR miss cycles
1348system.cpu2.dcache.overall_mshr_miss_latency::total 3996500 # number of overall MSHR miss cycles
1349system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003705 # mshr miss rate for ReadReq accesses
1350system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002862 # mshr miss rate for WriteReq accesses
1351system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.815789 # mshr miss rate for SwapReq accesses
1352system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003340 # mshr miss rate for demand accesses
1353system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003340 # mshr miss rate for overall accesses
1354system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14502.923977 # average ReadReq mshr miss latency
1355system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15014.851485 # average WriteReq mshr miss latency
1356system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 16048.387097 # average SwapReq mshr miss latency
1357system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14693.014706 # average overall mshr miss latency
1358system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14693.014706 # average overall mshr miss latency
1359system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1360system.cpu3.numCycles 186832 # number of cpu cycles simulated
1361system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
1362system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
1363system.cpu3.BPredUnit.lookups 49447 # Number of BP lookups
1364system.cpu3.BPredUnit.condPredicted 46344 # Number of conditional branches predicted
1365system.cpu3.BPredUnit.condIncorrect 1525 # Number of conditional branches incorrect
1366system.cpu3.BPredUnit.BTBLookups 42752 # Number of BTB lookups
--- 285 unchanged lines hidden (view full) ---
1652system.cpu3.icache.overall_miss_latency::total 6843000 # number of overall miss cycles
1653system.cpu3.icache.ReadReq_accesses::cpu3.inst 24454 # number of ReadReq accesses(hits+misses)
1654system.cpu3.icache.ReadReq_accesses::total 24454 # number of ReadReq accesses(hits+misses)
1655system.cpu3.icache.demand_accesses::cpu3.inst 24454 # number of demand (read+write) accesses
1656system.cpu3.icache.demand_accesses::total 24454 # number of demand (read+write) accesses
1657system.cpu3.icache.overall_accesses::cpu3.inst 24454 # number of overall (read+write) accesses
1658system.cpu3.icache.overall_accesses::total 24454 # number of overall (read+write) accesses
1659system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020569 # miss rate for ReadReq accesses
1660system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020569 # miss rate for demand accesses
1661system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020569 # miss rate for overall accesses
1662system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13604.373757 # average ReadReq miss latency
1663system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13604.373757 # average overall miss latency
1664system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13604.373757 # average overall miss latency
1665system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1666system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1667system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1668system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
1669system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1670system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1671system.cpu3.icache.fast_writes 0 # number of fast writes performed
1672system.cpu3.icache.cache_copies 0 # number of cache copies performed
--- 11 unchanged lines hidden (view full) ---
1684system.cpu3.icache.overall_mshr_misses::total 432 # number of overall MSHR misses
1685system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4912000 # number of ReadReq MSHR miss cycles
1686system.cpu3.icache.ReadReq_mshr_miss_latency::total 4912000 # number of ReadReq MSHR miss cycles
1687system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4912000 # number of demand (read+write) MSHR miss cycles
1688system.cpu3.icache.demand_mshr_miss_latency::total 4912000 # number of demand (read+write) MSHR miss cycles
1689system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4912000 # number of overall MSHR miss cycles
1690system.cpu3.icache.overall_mshr_miss_latency::total 4912000 # number of overall MSHR miss cycles
1691system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for ReadReq accesses
1692system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for demand accesses
1693system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for overall accesses
1694system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average ReadReq mshr miss latency
1695system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average overall mshr miss latency
1696system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average overall mshr miss latency
1697system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1698system.cpu3.dcache.replacements 2 # number of replacements
1699system.cpu3.dcache.tagsinuse 25.290478 # Cycle average of tags in use
1700system.cpu3.dcache.total_refs 37716 # Total number of references to valid blocks.
1701system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks.
1702system.cpu3.dcache.avg_refs 1257.200000 # Average number of references to valid blocks.
1703system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1704system.cpu3.dcache.occ_blocks::cpu3.data 25.290478 # Average occupied blocks per requestor
--- 35 unchanged lines hidden (view full) ---
1740system.cpu3.dcache.WriteReq_accesses::total 31338 # number of WriteReq accesses(hits+misses)
1741system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses)
1742system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
1743system.cpu3.dcache.demand_accesses::cpu3.data 74691 # number of demand (read+write) accesses
1744system.cpu3.dcache.demand_accesses::total 74691 # number of demand (read+write) accesses
1745system.cpu3.dcache.overall_accesses::cpu3.data 74691 # number of overall (read+write) accesses
1746system.cpu3.dcache.overall_accesses::total 74691 # number of overall (read+write) accesses
1747system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009688 # miss rate for ReadReq accesses
1748system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004755 # miss rate for WriteReq accesses
1749system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses
1750system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007618 # miss rate for demand accesses
1751system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007618 # miss rate for overall accesses
1752system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 20514.285714 # average ReadReq miss latency
1753system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20184.563758 # average WriteReq miss latency
1754system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 21017.543860 # average SwapReq miss latency
1755system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 20427.943761 # average overall miss latency
1756system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 20427.943761 # average overall miss latency
1757system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1758system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1759system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1760system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
1761system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1762system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1763system.cpu3.dcache.fast_writes 0 # number of fast writes performed
1764system.cpu3.dcache.cache_copies 0 # number of cache copies performed
--- 23 unchanged lines hidden (view full) ---
1788system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1621000 # number of WriteReq MSHR miss cycles
1789system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 1027000 # number of SwapReq MSHR miss cycles
1790system.cpu3.dcache.SwapReq_mshr_miss_latency::total 1027000 # number of SwapReq MSHR miss cycles
1791system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3772000 # number of demand (read+write) MSHR miss cycles
1792system.cpu3.dcache.demand_mshr_miss_latency::total 3772000 # number of demand (read+write) MSHR miss cycles
1793system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3772000 # number of overall MSHR miss cycles
1794system.cpu3.dcache.overall_mshr_miss_latency::total 3772000 # number of overall MSHR miss cycles
1795system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003760 # mshr miss rate for ReadReq accesses
1796system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003319 # mshr miss rate for WriteReq accesses
1797system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses
1798system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003575 # mshr miss rate for demand accesses
1799system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003575 # mshr miss rate for overall accesses
1800system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13196.319018 # average ReadReq mshr miss latency
1801system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15586.538462 # average WriteReq mshr miss latency
1802system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 18017.543860 # average SwapReq mshr miss latency
1803system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14127.340824 # average overall mshr miss latency
1804system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14127.340824 # average overall mshr miss latency
1805system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1806system.l2c.replacements 0 # number of replacements
1807system.l2c.tagsinuse 441.136869 # Cycle average of tags in use
1808system.l2c.total_refs 1471 # Total number of references to valid blocks.
1809system.l2c.sampled_refs 544 # Sample count of references to valid blocks.
1810system.l2c.avg_refs 2.704044 # Average number of references to valid blocks.
1811system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1812system.l2c.occ_blocks::writebacks 4.878414 # Average occupied blocks per requestor
--- 161 unchanged lines hidden (view full) ---
1974system.l2c.ReadReq_miss_rate::cpu0.inst 0.611111 # miss rate for ReadReq accesses
1975system.l2c.ReadReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadReq accesses
1976system.l2c.ReadReq_miss_rate::cpu1.inst 0.034483 # miss rate for ReadReq accesses
1977system.l2c.ReadReq_miss_rate::cpu1.data 0.071429 # miss rate for ReadReq accesses
1978system.l2c.ReadReq_miss_rate::cpu2.inst 0.193182 # miss rate for ReadReq accesses
1979system.l2c.ReadReq_miss_rate::cpu2.data 0.500000 # miss rate for ReadReq accesses
1980system.l2c.ReadReq_miss_rate::cpu3.inst 0.004630 # miss rate for ReadReq accesses
1981system.l2c.ReadReq_miss_rate::cpu3.data 0.071429 # miss rate for ReadReq accesses
1982system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses
1983system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
1984system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
1985system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
1986system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
1987system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
1988system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
1989system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
1990system.l2c.demand_miss_rate::cpu0.inst 0.611111 # miss rate for demand accesses
1991system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses
1992system.l2c.demand_miss_rate::cpu1.inst 0.034483 # miss rate for demand accesses
1993system.l2c.demand_miss_rate::cpu1.data 0.500000 # miss rate for demand accesses
1994system.l2c.demand_miss_rate::cpu2.inst 0.193182 # miss rate for demand accesses
1995system.l2c.demand_miss_rate::cpu2.data 0.740741 # miss rate for demand accesses
1996system.l2c.demand_miss_rate::cpu3.inst 0.004630 # miss rate for demand accesses
1997system.l2c.demand_miss_rate::cpu3.data 0.500000 # miss rate for demand accesses
1998system.l2c.overall_miss_rate::cpu0.inst 0.611111 # miss rate for overall accesses
1999system.l2c.overall_miss_rate::cpu0.data 0.971264 # miss rate for overall accesses
2000system.l2c.overall_miss_rate::cpu1.inst 0.034483 # miss rate for overall accesses
2001system.l2c.overall_miss_rate::cpu1.data 0.500000 # miss rate for overall accesses
2002system.l2c.overall_miss_rate::cpu2.inst 0.193182 # miss rate for overall accesses
2003system.l2c.overall_miss_rate::cpu2.data 0.740741 # miss rate for overall accesses
2004system.l2c.overall_miss_rate::cpu3.inst 0.004630 # miss rate for overall accesses
2005system.l2c.overall_miss_rate::cpu3.data 0.500000 # miss rate for overall accesses
2006system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52119.834711 # average ReadReq miss latency
2007system.l2c.ReadReq_avg_miss_latency::cpu0.data 52393.333333 # average ReadReq miss latency
2008system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49633.333333 # average ReadReq miss latency
2009system.l2c.ReadReq_avg_miss_latency::cpu1.data 52500 # average ReadReq miss latency
2010system.l2c.ReadReq_avg_miss_latency::cpu2.inst 51482.352941 # average ReadReq miss latency
2011system.l2c.ReadReq_avg_miss_latency::cpu2.data 52285.714286 # average ReadReq miss latency
2012system.l2c.ReadReq_avg_miss_latency::cpu3.inst 49750 # average ReadReq miss latency
2013system.l2c.ReadReq_avg_miss_latency::cpu3.data 52500 # average ReadReq miss latency
2014system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2500 # average UpgradeReq miss latency
2015system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 3088.235294 # average UpgradeReq miss latency
2016system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 2625 # average UpgradeReq miss latency
2017system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52547.872340 # average ReadExReq miss latency
2018system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52291.666667 # average ReadExReq miss latency
2019system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52346.153846 # average ReadExReq miss latency
2020system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52291.666667 # average ReadExReq miss latency
2021system.l2c.demand_avg_miss_latency::cpu0.inst 52119.834711 # average overall miss latency
2022system.l2c.demand_avg_miss_latency::cpu0.data 52479.289941 # average overall miss latency
2023system.l2c.demand_avg_miss_latency::cpu1.inst 49633.333333 # average overall miss latency
2024system.l2c.demand_avg_miss_latency::cpu1.data 52307.692308 # average overall miss latency
2025system.l2c.demand_avg_miss_latency::cpu2.inst 51482.352941 # average overall miss latency
2026system.l2c.demand_avg_miss_latency::cpu2.data 52325 # average overall miss latency
2027system.l2c.demand_avg_miss_latency::cpu3.inst 49750 # average overall miss latency
2028system.l2c.demand_avg_miss_latency::cpu3.data 52307.692308 # average overall miss latency
2029system.l2c.overall_avg_miss_latency::cpu0.inst 52119.834711 # average overall miss latency
2030system.l2c.overall_avg_miss_latency::cpu0.data 52479.289941 # average overall miss latency
2031system.l2c.overall_avg_miss_latency::cpu1.inst 49633.333333 # average overall miss latency
2032system.l2c.overall_avg_miss_latency::cpu1.data 52307.692308 # average overall miss latency
2033system.l2c.overall_avg_miss_latency::cpu2.inst 51482.352941 # average overall miss latency
2034system.l2c.overall_avg_miss_latency::cpu2.data 52325 # average overall miss latency
2035system.l2c.overall_avg_miss_latency::cpu3.inst 49750 # average overall miss latency
2036system.l2c.overall_avg_miss_latency::cpu3.data 52307.692308 # average overall miss latency
2037system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2038system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2039system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
2040system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2041system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2042system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2043system.l2c.fast_writes 0 # number of fast writes performed
2044system.l2c.cache_copies 0 # number of cache copies performed
--- 86 unchanged lines hidden (view full) ---
2131system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for ReadReq accesses
2132system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadReq accesses
2133system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for ReadReq accesses
2134system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.071429 # mshr miss rate for ReadReq accesses
2135system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.181818 # mshr miss rate for ReadReq accesses
2136system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.500000 # mshr miss rate for ReadReq accesses
2137system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for ReadReq accesses
2138system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.071429 # mshr miss rate for ReadReq accesses
2139system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses
2140system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2141system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
2142system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
2143system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
2144system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
2145system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
2146system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
2147system.l2c.demand_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for demand accesses
2148system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses
2149system.l2c.demand_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for demand accesses
2150system.l2c.demand_mshr_miss_rate::cpu1.data 0.500000 # mshr miss rate for demand accesses
2151system.l2c.demand_mshr_miss_rate::cpu2.inst 0.181818 # mshr miss rate for demand accesses
2152system.l2c.demand_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for demand accesses
2153system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for demand accesses
2154system.l2c.demand_mshr_miss_rate::cpu3.data 0.500000 # mshr miss rate for demand accesses
2155system.l2c.overall_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for overall accesses
2156system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses
2157system.l2c.overall_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for overall accesses
2158system.l2c.overall_mshr_miss_rate::cpu1.data 0.500000 # mshr miss rate for overall accesses
2159system.l2c.overall_mshr_miss_rate::cpu2.inst 0.181818 # mshr miss rate for overall accesses
2160system.l2c.overall_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for overall accesses
2161system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for overall accesses
2162system.l2c.overall_mshr_miss_rate::cpu3.data 0.500000 # mshr miss rate for overall accesses
2163system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average ReadReq mshr miss latency
2164system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40220 # average ReadReq mshr miss latency
2165system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency
2166system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency
2167system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency
2168system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency
2169system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency
2170system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency
2171system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency
2172system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency
2173system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency
2174system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency
2175system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40351.063830 # average ReadExReq mshr miss latency
2176system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40125 # average ReadExReq mshr miss latency
2177system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40192.307692 # average ReadExReq mshr miss latency
2178system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40125 # average ReadExReq mshr miss latency
2179system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average overall mshr miss latency
2180system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40292.899408 # average overall mshr miss latency
2181system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency
2182system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40115.384615 # average overall mshr miss latency
2183system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
2184system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40125 # average overall mshr miss latency
2185system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
2186system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency
2187system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average overall mshr miss latency
2188system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40292.899408 # average overall mshr miss latency
2189system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency
2190system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40115.384615 # average overall mshr miss latency
2191system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
2192system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40125 # average overall mshr miss latency
2193system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
2194system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency
2195system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2196
2197---------- End Simulation Statistics ----------