1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000111 # Number of seconds simulated
4sim_ticks 111025500 # Number of ticks simulated
5final_tick 111025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 119782 # Simulator instruction rate (inst/s)
8host_op_rate 119782 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 12747983 # Simulator tick rate (ticks/s)
10host_mem_usage 275656 # Number of bytes of host memory used
11host_seconds 8.71 # Real time elapsed on the host
12sim_insts 1043212 # Number of instructions simulated
13sim_ops 1043212 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory
16system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu2.inst 4672 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu3.inst 384 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory

--- 7 unchanged lines hidden (view full) ---

29system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory
32system.physmem.num_reads::cpu2.inst 73 # Number of read requests responded to by this memory
33system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu3.inst 6 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
36system.physmem.num_reads::total 659 # Number of read requests responded to by this memory
37system.physmem.bw_read::cpu0.inst 205214117 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu0.data 96842617 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu1.inst 5764442 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::cpu1.data 7493774 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::cpu2.inst 42080423 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_read::cpu2.data 11528883 # Total read bandwidth from this memory (bytes/s)
43system.physmem.bw_read::cpu3.inst 3458665 # Total read bandwidth from this memory (bytes/s)
44system.physmem.bw_read::cpu3.data 7493774 # Total read bandwidth from this memory (bytes/s)
45system.physmem.bw_read::total 379876695 # Total read bandwidth from this memory (bytes/s)
46system.physmem.bw_inst_read::cpu0.inst 205214117 # Instruction read bandwidth from this memory (bytes/s)
47system.physmem.bw_inst_read::cpu1.inst 5764442 # Instruction read bandwidth from this memory (bytes/s)
48system.physmem.bw_inst_read::cpu2.inst 42080423 # Instruction read bandwidth from this memory (bytes/s)
49system.physmem.bw_inst_read::cpu3.inst 3458665 # Instruction read bandwidth from this memory (bytes/s)
50system.physmem.bw_inst_read::total 256517647 # Instruction read bandwidth from this memory (bytes/s)
51system.physmem.bw_total::cpu0.inst 205214117 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::cpu0.data 96842617 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.bw_total::cpu1.inst 5764442 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.bw_total::cpu1.data 7493774 # Total bandwidth to/from this memory (bytes/s)
55system.physmem.bw_total::cpu2.inst 42080423 # Total bandwidth to/from this memory (bytes/s)
56system.physmem.bw_total::cpu2.data 11528883 # Total bandwidth to/from this memory (bytes/s)
57system.physmem.bw_total::cpu3.inst 3458665 # Total bandwidth to/from this memory (bytes/s)
58system.physmem.bw_total::cpu3.data 7493774 # Total bandwidth to/from this memory (bytes/s)
59system.physmem.bw_total::total 379876695 # Total bandwidth to/from this memory (bytes/s)
60system.physmem.readReqs 660 # Number of read requests accepted
61system.physmem.writeReqs 0 # Number of write requests accepted
62system.physmem.readBursts 660 # Number of DRAM read bursts, including those serviced by the write queue
63system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
64system.physmem.bytesReadDRAM 42240 # Total number of bytes read from DRAM
65system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
66system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
67system.physmem.bytesReadSys 42240 # Total read bytes from the system interface side
68system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
69system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
70system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
71system.physmem.neitherReadNorWriteReqs 76 # Number of requests that are neither read nor write
72system.physmem.perBankRdBursts::0 115 # Per bank write bursts
73system.physmem.perBankRdBursts::1 39 # Per bank write bursts
74system.physmem.perBankRdBursts::2 29 # Per bank write bursts
75system.physmem.perBankRdBursts::3 60 # Per bank write bursts
76system.physmem.perBankRdBursts::4 65 # Per bank write bursts
77system.physmem.perBankRdBursts::5 27 # Per bank write bursts
78system.physmem.perBankRdBursts::6 18 # Per bank write bursts
79system.physmem.perBankRdBursts::7 24 # Per bank write bursts
80system.physmem.perBankRdBursts::8 7 # Per bank write bursts
81system.physmem.perBankRdBursts::9 28 # Per bank write bursts
82system.physmem.perBankRdBursts::10 23 # Per bank write bursts
83system.physmem.perBankRdBursts::11 12 # Per bank write bursts
84system.physmem.perBankRdBursts::12 60 # Per bank write bursts
85system.physmem.perBankRdBursts::13 38 # Per bank write bursts
86system.physmem.perBankRdBursts::14 17 # Per bank write bursts
87system.physmem.perBankRdBursts::15 98 # Per bank write bursts
88system.physmem.perBankWrBursts::0 0 # Per bank write bursts
89system.physmem.perBankWrBursts::1 0 # Per bank write bursts
90system.physmem.perBankWrBursts::2 0 # Per bank write bursts
91system.physmem.perBankWrBursts::3 0 # Per bank write bursts
92system.physmem.perBankWrBursts::4 0 # Per bank write bursts
93system.physmem.perBankWrBursts::5 0 # Per bank write bursts
94system.physmem.perBankWrBursts::6 0 # Per bank write bursts
95system.physmem.perBankWrBursts::7 0 # Per bank write bursts
96system.physmem.perBankWrBursts::8 0 # Per bank write bursts
97system.physmem.perBankWrBursts::9 0 # Per bank write bursts
98system.physmem.perBankWrBursts::10 0 # Per bank write bursts
99system.physmem.perBankWrBursts::11 0 # Per bank write bursts
100system.physmem.perBankWrBursts::12 0 # Per bank write bursts
101system.physmem.perBankWrBursts::13 0 # Per bank write bursts
102system.physmem.perBankWrBursts::14 0 # Per bank write bursts
103system.physmem.perBankWrBursts::15 0 # Per bank write bursts
104system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
105system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
106system.physmem.totGap 110997500 # Total gap between requests
107system.physmem.readPktSize::0 0 # Read request sizes (log2)
108system.physmem.readPktSize::1 0 # Read request sizes (log2)
109system.physmem.readPktSize::2 0 # Read request sizes (log2)
110system.physmem.readPktSize::3 0 # Read request sizes (log2)
111system.physmem.readPktSize::4 0 # Read request sizes (log2)
112system.physmem.readPktSize::5 0 # Read request sizes (log2)
113system.physmem.readPktSize::6 660 # Read request sizes (log2)
114system.physmem.writePktSize::0 0 # Write request sizes (log2)
115system.physmem.writePktSize::1 0 # Write request sizes (log2)
116system.physmem.writePktSize::2 0 # Write request sizes (log2)
117system.physmem.writePktSize::3 0 # Write request sizes (log2)
118system.physmem.writePktSize::4 0 # Write request sizes (log2)
119system.physmem.writePktSize::5 0 # Write request sizes (log2)
120system.physmem.writePktSize::6 0 # Write request sizes (log2)
121system.physmem.rdQLenPdf::0 408 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::1 191 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see

--- 44 unchanged lines hidden (view full) ---

177system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
185system.physmem.bytesPerActivate::samples 151 # Bytes accessed per row activation
186system.physmem.bytesPerActivate::mean 260.662252 # Bytes accessed per row activation
187system.physmem.bytesPerActivate::gmean 168.685653 # Bytes accessed per row activation
188system.physmem.bytesPerActivate::stdev 287.368727 # Bytes accessed per row activation
189system.physmem.bytesPerActivate::64 56 37.09% 37.09% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::128 15 9.93% 47.02% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::192 26 17.22% 64.24% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::256 9 5.96% 70.20% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::320 10 6.62% 76.82% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::384 7 4.64% 81.46% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::448 4 2.65% 84.11% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::512 6 3.97% 88.08% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::576 3 1.99% 90.07% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::640 3 1.99% 92.05% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::704 2 1.32% 93.38% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::768 2 1.32% 94.70% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::832 3 1.99% 96.69% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::1024 2 1.32% 98.01% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::1152 1 0.66% 98.68% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::1536 1 0.66% 99.34% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::1984 1 0.66% 100.00% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::total 151 # Bytes accessed per row activation
207system.physmem.totQLat 4010250 # Total ticks spent queuing
208system.physmem.totMemAccLat 18159000 # Total ticks spent from burst creation until serviced by the DRAM
209system.physmem.totBusLat 3300000 # Total ticks spent in databus transfers
210system.physmem.totBankLat 10848750 # Total ticks spent accessing banks
211system.physmem.avgQLat 6076.14 # Average queueing delay per DRAM burst
212system.physmem.avgBankLat 16437.50 # Average bank access latency per DRAM burst
213system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
214system.physmem.avgMemAccLat 27513.64 # Average memory access latency per DRAM burst
215system.physmem.avgRdBW 380.45 # Average DRAM read bandwidth in MiByte/s
216system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
217system.physmem.avgRdBWSys 380.45 # Average system read bandwidth in MiByte/s
218system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
219system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
220system.physmem.busUtil 2.97 # Data bus utilization in percentage
221system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads
222system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
223system.physmem.avgRdQLen 0.16 # Average read queue length when enqueuing
224system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
225system.physmem.readRowHits 509 # Number of row buffer hits during reads
226system.physmem.writeRowHits 0 # Number of row buffer hits during writes
227system.physmem.readRowHitRate 77.12 # Row buffer hit rate for reads
228system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
229system.physmem.avgGap 168178.03 # Average gap between requests
230system.physmem.pageHitRate 77.12 # Row buffer hit rate, read and write combined
231system.physmem.prechargeAllPercent 11.34 # Percentage of time for which DRAM has all the banks in precharge state
232system.membus.throughput 379876695 # Throughput (bytes/s)
233system.membus.trans_dist::ReadReq 529 # Transaction distribution
234system.membus.trans_dist::ReadResp 528 # Transaction distribution
235system.membus.trans_dist::UpgradeReq 289 # Transaction distribution
236system.membus.trans_dist::UpgradeResp 76 # Transaction distribution
237system.membus.trans_dist::ReadExReq 164 # Transaction distribution
238system.membus.trans_dist::ReadExResp 131 # Transaction distribution
239system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1717 # Packet count per connected master and slave (bytes)
240system.membus.pkt_count::total 1717 # Packet count per connected master and slave (bytes)
241system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42176 # Cumulative packet size per connected master and slave (bytes)
242system.membus.tot_pkt_size::total 42176 # Cumulative packet size per connected master and slave (bytes)
243system.membus.data_through_bus 42176 # Total data (bytes)
244system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
245system.membus.reqLayer0.occupancy 931500 # Layer occupancy (ticks)
246system.membus.reqLayer0.utilization 0.8 # Layer utilization (%)
247system.membus.respLayer1.occupancy 6289925 # Layer occupancy (ticks)
248system.membus.respLayer1.utilization 5.7 # Layer utilization (%)
249system.l2c.tags.replacements 0 # number of replacements
250system.l2c.tags.tagsinuse 417.165472 # Cycle average of tags in use
251system.l2c.tags.total_refs 1442 # Total number of references to valid blocks.
252system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks.
253system.l2c.tags.avg_refs 2.741445 # Average number of references to valid blocks.
254system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
255system.l2c.tags.occ_blocks::writebacks 0.799798 # Average occupied blocks per requestor
256system.l2c.tags.occ_blocks::cpu0.inst 285.088059 # Average occupied blocks per requestor
257system.l2c.tags.occ_blocks::cpu0.data 58.417692 # Average occupied blocks per requestor
258system.l2c.tags.occ_blocks::cpu1.inst 7.543236 # Average occupied blocks per requestor
259system.l2c.tags.occ_blocks::cpu1.data 0.694746 # Average occupied blocks per requestor
260system.l2c.tags.occ_blocks::cpu2.inst 55.417060 # Average occupied blocks per requestor
261system.l2c.tags.occ_blocks::cpu2.data 5.409300 # Average occupied blocks per requestor
262system.l2c.tags.occ_blocks::cpu3.inst 3.063366 # Average occupied blocks per requestor
263system.l2c.tags.occ_blocks::cpu3.data 0.732215 # Average occupied blocks per requestor
264system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy
265system.l2c.tags.occ_percent::cpu0.inst 0.004350 # Average percentage of cache occupancy
266system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy
267system.l2c.tags.occ_percent::cpu1.inst 0.000115 # Average percentage of cache occupancy
268system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy
269system.l2c.tags.occ_percent::cpu2.inst 0.000846 # Average percentage of cache occupancy
270system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy
271system.l2c.tags.occ_percent::cpu3.inst 0.000047 # Average percentage of cache occupancy
272system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy
273system.l2c.tags.occ_percent::total 0.006365 # Average percentage of cache occupancy
274system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits
275system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
276system.l2c.ReadReq_hits::cpu1.inst 412 # number of ReadReq hits
277system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits
278system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits
279system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits
280system.l2c.ReadReq_hits::cpu3.inst 420 # number of ReadReq hits
281system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits
282system.l2c.ReadReq_hits::total 1442 # number of ReadReq hits
283system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
284system.l2c.Writeback_hits::total 1 # number of Writeback hits
285system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
286system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits
287system.l2c.demand_hits::cpu0.inst 229 # number of demand (read+write) hits
288system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
289system.l2c.demand_hits::cpu1.inst 412 # number of demand (read+write) hits
290system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits
291system.l2c.demand_hits::cpu2.inst 349 # number of demand (read+write) hits
292system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits
293system.l2c.demand_hits::cpu3.inst 420 # number of demand (read+write) hits
294system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits
295system.l2c.demand_hits::total 1442 # number of demand (read+write) hits
296system.l2c.overall_hits::cpu0.inst 229 # number of overall hits
297system.l2c.overall_hits::cpu0.data 5 # number of overall hits
298system.l2c.overall_hits::cpu1.inst 412 # number of overall hits
299system.l2c.overall_hits::cpu1.data 11 # number of overall hits
300system.l2c.overall_hits::cpu2.inst 349 # number of overall hits
301system.l2c.overall_hits::cpu2.data 5 # number of overall hits
302system.l2c.overall_hits::cpu3.inst 420 # number of overall hits
303system.l2c.overall_hits::cpu3.data 11 # number of overall hits
304system.l2c.overall_hits::total 1442 # number of overall hits
305system.l2c.ReadReq_misses::cpu0.inst 359 # number of ReadReq misses
306system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses
307system.l2c.ReadReq_misses::cpu1.inst 16 # number of ReadReq misses
308system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses
309system.l2c.ReadReq_misses::cpu2.inst 76 # number of ReadReq misses
310system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses
311system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses
312system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses
313system.l2c.ReadReq_misses::total 543 # number of ReadReq misses
314system.l2c.UpgradeReq_misses::cpu0.data 21 # number of UpgradeReq misses
315system.l2c.UpgradeReq_misses::cpu1.data 20 # number of UpgradeReq misses
316system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses
317system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses
318system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses
319system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses
320system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses
321system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses
322system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
323system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses
324system.l2c.demand_misses::cpu0.inst 359 # number of demand (read+write) misses
325system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses

--- 8 unchanged lines hidden (view full) ---

334system.l2c.overall_misses::cpu0.data 168 # number of overall misses
335system.l2c.overall_misses::cpu1.inst 16 # number of overall misses
336system.l2c.overall_misses::cpu1.data 13 # number of overall misses
337system.l2c.overall_misses::cpu2.inst 76 # number of overall misses
338system.l2c.overall_misses::cpu2.data 20 # number of overall misses
339system.l2c.overall_misses::cpu3.inst 9 # number of overall misses
340system.l2c.overall_misses::cpu3.data 13 # number of overall misses
341system.l2c.overall_misses::total 674 # number of overall misses
342system.l2c.ReadReq_miss_latency::cpu0.inst 24801500 # number of ReadReq miss cycles
343system.l2c.ReadReq_miss_latency::cpu0.data 5612000 # number of ReadReq miss cycles
344system.l2c.ReadReq_miss_latency::cpu1.inst 1162500 # number of ReadReq miss cycles
345system.l2c.ReadReq_miss_latency::cpu1.data 74500 # number of ReadReq miss cycles
346system.l2c.ReadReq_miss_latency::cpu2.inst 5361500 # number of ReadReq miss cycles
347system.l2c.ReadReq_miss_latency::cpu2.data 495250 # number of ReadReq miss cycles
348system.l2c.ReadReq_miss_latency::cpu3.inst 584250 # number of ReadReq miss cycles
349system.l2c.ReadReq_miss_latency::cpu3.data 74500 # number of ReadReq miss cycles
350system.l2c.ReadReq_miss_latency::total 38166000 # number of ReadReq miss cycles
351system.l2c.ReadExReq_miss_latency::cpu0.data 6725000 # number of ReadExReq miss cycles
352system.l2c.ReadExReq_miss_latency::cpu1.data 852250 # number of ReadExReq miss cycles
353system.l2c.ReadExReq_miss_latency::cpu2.data 1087000 # number of ReadExReq miss cycles
354system.l2c.ReadExReq_miss_latency::cpu3.data 958250 # number of ReadExReq miss cycles
355system.l2c.ReadExReq_miss_latency::total 9622500 # number of ReadExReq miss cycles
356system.l2c.demand_miss_latency::cpu0.inst 24801500 # number of demand (read+write) miss cycles
357system.l2c.demand_miss_latency::cpu0.data 12337000 # number of demand (read+write) miss cycles
358system.l2c.demand_miss_latency::cpu1.inst 1162500 # number of demand (read+write) miss cycles
359system.l2c.demand_miss_latency::cpu1.data 926750 # number of demand (read+write) miss cycles
360system.l2c.demand_miss_latency::cpu2.inst 5361500 # number of demand (read+write) miss cycles
361system.l2c.demand_miss_latency::cpu2.data 1582250 # number of demand (read+write) miss cycles
362system.l2c.demand_miss_latency::cpu3.inst 584250 # number of demand (read+write) miss cycles
363system.l2c.demand_miss_latency::cpu3.data 1032750 # number of demand (read+write) miss cycles
364system.l2c.demand_miss_latency::total 47788500 # number of demand (read+write) miss cycles
365system.l2c.overall_miss_latency::cpu0.inst 24801500 # number of overall miss cycles
366system.l2c.overall_miss_latency::cpu0.data 12337000 # number of overall miss cycles
367system.l2c.overall_miss_latency::cpu1.inst 1162500 # number of overall miss cycles
368system.l2c.overall_miss_latency::cpu1.data 926750 # number of overall miss cycles
369system.l2c.overall_miss_latency::cpu2.inst 5361500 # number of overall miss cycles
370system.l2c.overall_miss_latency::cpu2.data 1582250 # number of overall miss cycles
371system.l2c.overall_miss_latency::cpu3.inst 584250 # number of overall miss cycles
372system.l2c.overall_miss_latency::cpu3.data 1032750 # number of overall miss cycles
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--- 16 unchanged lines hidden (view full) ---

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--- 8 unchanged lines hidden (view full) ---

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632system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71384.615385 # average ReadExReq mshr miss latency
633system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 67312.500000 # average ReadExReq mshr miss latency
634system.l2c.ReadExReq_avg_mshr_miss_latency::total 60988.549618 # average ReadExReq mshr miss latency
635system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56689.775910 # average overall mshr miss latency
636system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61032.738095 # average overall mshr miss latency
637system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67650 # average overall mshr miss latency
638system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency
639system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 58729.452055 # average overall mshr miss latency
640system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66837.500000 # average overall mshr miss latency
641system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 61625 # average overall mshr miss latency
642system.l2c.demand_avg_mshr_miss_latency::cpu3.data 66942.307692 # average overall mshr miss latency
643system.l2c.demand_avg_mshr_miss_latency::total 58782.575758 # average overall mshr miss latency
644system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56689.775910 # average overall mshr miss latency
645system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61032.738095 # average overall mshr miss latency
646system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67650 # average overall mshr miss latency
647system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency
648system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 58729.452055 # average overall mshr miss latency
649system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66837.500000 # average overall mshr miss latency
650system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61625 # average overall mshr miss latency
651system.l2c.overall_avg_mshr_miss_latency::cpu3.data 66942.307692 # average overall mshr miss latency
652system.l2c.overall_avg_mshr_miss_latency::total 58782.575758 # average overall mshr miss latency
653system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
654system.toL2Bus.throughput 1689557804 # Throughput (bytes/s)
655system.toL2Bus.trans_dist::ReadReq 2542 # Transaction distribution
656system.toL2Bus.trans_dist::ReadResp 2541 # Transaction distribution
657system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
658system.toL2Bus.trans_dist::UpgradeReq 292 # Transaction distribution
659system.toL2Bus.trans_dist::UpgradeResp 292 # Transaction distribution
660system.toL2Bus.trans_dist::ReadExReq 389 # Transaction distribution
661system.toL2Bus.trans_dist::ReadExResp 389 # Transaction distribution
662system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1175 # Packet count per connected master and slave (bytes)
663system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 591 # Packet count per connected master and slave (bytes)
664system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 856 # Packet count per connected master and slave (bytes)
665system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 373 # Packet count per connected master and slave (bytes)
666system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 850 # Packet count per connected master and slave (bytes)
667system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes)
668system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 858 # Packet count per connected master and slave (bytes)
669system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 348 # Packet count per connected master and slave (bytes)
670system.toL2Bus.pkt_count::total 5418 # Packet count per connected master and slave (bytes)
671system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 37568 # Cumulative packet size per connected master and slave (bytes)
672system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes)
673system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 27392 # Cumulative packet size per connected master and slave (bytes)
674system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
675system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 27200 # Cumulative packet size per connected master and slave (bytes)
676system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
677system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 27456 # Cumulative packet size per connected master and slave (bytes)
678system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
679system.toL2Bus.tot_pkt_size::total 135424 # Cumulative packet size per connected master and slave (bytes)
680system.toL2Bus.data_through_bus 135424 # Total data (bytes)
681system.toL2Bus.snoop_data_through_bus 52160 # Total snoop data (bytes)
682system.toL2Bus.reqLayer0.occupancy 1628974 # Layer occupancy (ticks)
683system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%)
684system.toL2Bus.respLayer0.occupancy 2704748 # Layer occupancy (ticks)
685system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%)
686system.toL2Bus.respLayer1.occupancy 1475514 # Layer occupancy (ticks)
687system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
688system.toL2Bus.respLayer2.occupancy 1928994 # Layer occupancy (ticks)
689system.toL2Bus.respLayer2.utilization 1.7 # Layer utilization (%)
690system.toL2Bus.respLayer3.occupancy 1199245 # Layer occupancy (ticks)
691system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%)
692system.toL2Bus.respLayer4.occupancy 1926995 # Layer occupancy (ticks)
693system.toL2Bus.respLayer4.utilization 1.7 # Layer utilization (%)
694system.toL2Bus.respLayer5.occupancy 1183748 # Layer occupancy (ticks)
695system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%)
696system.toL2Bus.respLayer6.occupancy 1932245 # Layer occupancy (ticks)
697system.toL2Bus.respLayer6.utilization 1.7 # Layer utilization (%)
698system.toL2Bus.respLayer7.occupancy 1115744 # Layer occupancy (ticks)
699system.toL2Bus.respLayer7.utilization 1.0 # Layer utilization (%)
700system.cpu0.branchPred.lookups 83087 # Number of BP lookups
701system.cpu0.branchPred.condPredicted 80860 # Number of conditional branches predicted
702system.cpu0.branchPred.condIncorrect 1219 # Number of conditional branches incorrect
703system.cpu0.branchPred.BTBLookups 80377 # Number of BTB lookups
704system.cpu0.branchPred.BTBHits 78332 # Number of BTB hits
705system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
706system.cpu0.branchPred.BTBHitPct 97.455740 # BTB Hit Percentage
707system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target.
708system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions.
709system.cpu0.workload.num_syscalls 89 # Number of system calls
710system.cpu0.numCycles 222052 # number of cpu cycles simulated
711system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
712system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
713system.cpu0.fetch.icacheStallCycles 17258 # Number of cycles fetch is stalled on an Icache miss
714system.cpu0.fetch.Insts 493192 # Number of instructions fetch has processed
715system.cpu0.fetch.Branches 83087 # Number of branches that fetch encountered
716system.cpu0.fetch.predictedBranches 78844 # Number of branches that fetch has predicted taken
717system.cpu0.fetch.Cycles 161829 # Number of cycles fetch has run and was not squashing or blocked
718system.cpu0.fetch.SquashCycles 3807 # Number of cycles fetch has spent squashing
719system.cpu0.fetch.BlockedCycles 13993 # Number of cycles fetch has spent blocked
720system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
721system.cpu0.fetch.PendingTrapStallCycles 1512 # Number of stall cycles due to pending traps
722system.cpu0.fetch.CacheLines 5869 # Number of cache lines fetched
723system.cpu0.fetch.IcacheSquashes 489 # Number of outstanding Icache misses that were squashed
724system.cpu0.fetch.rateDist::samples 197037 # Number of instructions fetched each cycle (Total)
725system.cpu0.fetch.rateDist::mean 2.503043 # Number of instructions fetched each cycle (Total)
726system.cpu0.fetch.rateDist::stdev 2.216869 # Number of instructions fetched each cycle (Total)
727system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
728system.cpu0.fetch.rateDist::0 35208 17.87% 17.87% # Number of instructions fetched each cycle (Total)
729system.cpu0.fetch.rateDist::1 80150 40.68% 58.55% # Number of instructions fetched each cycle (Total)
730system.cpu0.fetch.rateDist::2 582 0.30% 58.84% # Number of instructions fetched each cycle (Total)
731system.cpu0.fetch.rateDist::3 988 0.50% 59.34% # Number of instructions fetched each cycle (Total)
732system.cpu0.fetch.rateDist::4 452 0.23% 59.57% # Number of instructions fetched each cycle (Total)
733system.cpu0.fetch.rateDist::5 76210 38.68% 98.25% # Number of instructions fetched each cycle (Total)
734system.cpu0.fetch.rateDist::6 578 0.29% 98.54% # Number of instructions fetched each cycle (Total)
735system.cpu0.fetch.rateDist::7 364 0.18% 98.73% # Number of instructions fetched each cycle (Total)
736system.cpu0.fetch.rateDist::8 2505 1.27% 100.00% # Number of instructions fetched each cycle (Total)
737system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
738system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
739system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
740system.cpu0.fetch.rateDist::total 197037 # Number of instructions fetched each cycle (Total)
741system.cpu0.fetch.branchRate 0.374178 # Number of branch fetches per cycle
742system.cpu0.fetch.rate 2.221065 # Number of inst fetches per cycle
743system.cpu0.decode.IdleCycles 17850 # Number of cycles decode is idle
744system.cpu0.decode.BlockedCycles 15597 # Number of cycles decode is blocked
745system.cpu0.decode.RunCycles 160862 # Number of cycles decode is running
746system.cpu0.decode.UnblockCycles 288 # Number of cycles decode is unblocking
747system.cpu0.decode.SquashCycles 2440 # Number of cycles decode is squashing
748system.cpu0.decode.DecodedInsts 490280 # Number of instructions handled by decode
749system.cpu0.rename.SquashCycles 2440 # Number of cycles rename is squashing
750system.cpu0.rename.IdleCycles 18506 # Number of cycles rename is idle
751system.cpu0.rename.BlockCycles 827 # Number of cycles rename is blocking
752system.cpu0.rename.serializeStallCycles 14176 # count of cycles rename stalled for serializing inst
753system.cpu0.rename.RunCycles 160527 # Number of cycles rename is running
754system.cpu0.rename.UnblockCycles 561 # Number of cycles rename is unblocking
755system.cpu0.rename.RenamedInsts 487444 # Number of instructions processed by rename
756system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
757system.cpu0.rename.LSQFullEvents 187 # Number of times rename has blocked due to LSQ full
758system.cpu0.rename.RenamedOperands 333388 # Number of destination operands rename has renamed
759system.cpu0.rename.RenameLookups 972038 # Number of register rename lookups that rename has made
760system.cpu0.rename.int_rename_lookups 734246 # Number of integer rename lookups
761system.cpu0.rename.CommittedMaps 320411 # Number of HB maps that are committed
762system.cpu0.rename.UndoneMaps 12977 # Number of HB maps that are undone due to squashing
763system.cpu0.rename.serializingInsts 872 # count of serializing insts renamed
764system.cpu0.rename.tempSerializingInsts 895 # count of temporary serializing insts renamed
765system.cpu0.rename.skidInsts 3641 # count of insts added to the skid buffer
766system.cpu0.memDep0.insertedLoads 155927 # Number of loads inserted to the mem dependence unit.
767system.cpu0.memDep0.insertedStores 78789 # Number of stores inserted to the mem dependence unit.
768system.cpu0.memDep0.conflictingLoads 76026 # Number of conflicting loads.
769system.cpu0.memDep0.conflictingStores 75860 # Number of conflicting stores.
770system.cpu0.iq.iqInstsAdded 407640 # Number of instructions added to the IQ (excludes non-spec)
771system.cpu0.iq.iqNonSpecInstsAdded 922 # Number of non-speculative instructions added to the IQ
772system.cpu0.iq.iqInstsIssued 405049 # Number of instructions issued
773system.cpu0.iq.iqSquashedInstsIssued 128 # Number of squashed instructions issued
774system.cpu0.iq.iqSquashedInstsExamined 10720 # Number of squashed instructions iterated over during squash; mainly for profiling
775system.cpu0.iq.iqSquashedOperandsExamined 9381 # Number of squashed operands that are examined and possibly removed from graph
776system.cpu0.iq.iqSquashedNonSpecRemoved 363 # Number of squashed non-spec instructions that were removed
777system.cpu0.iq.issued_per_cycle::samples 197037 # Number of insts issued each cycle
778system.cpu0.iq.issued_per_cycle::mean 2.055700 # Number of insts issued each cycle
779system.cpu0.iq.issued_per_cycle::stdev 1.097210 # Number of insts issued each cycle
780system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
781system.cpu0.iq.issued_per_cycle::0 34075 17.29% 17.29% # Number of insts issued each cycle
782system.cpu0.iq.issued_per_cycle::1 4941 2.51% 19.80% # Number of insts issued each cycle
783system.cpu0.iq.issued_per_cycle::2 78065 39.62% 59.42% # Number of insts issued each cycle
784system.cpu0.iq.issued_per_cycle::3 77366 39.26% 98.69% # Number of insts issued each cycle
785system.cpu0.iq.issued_per_cycle::4 1557 0.79% 99.48% # Number of insts issued each cycle
786system.cpu0.iq.issued_per_cycle::5 667 0.34% 99.81% # Number of insts issued each cycle
787system.cpu0.iq.issued_per_cycle::6 262 0.13% 99.95% # Number of insts issued each cycle
788system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle
789system.cpu0.iq.issued_per_cycle::8 17 0.01% 100.00% # Number of insts issued each cycle
790system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
791system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
792system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
793system.cpu0.iq.issued_per_cycle::total 197037 # Number of insts issued each cycle
794system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
795system.cpu0.iq.fu_full::IntAlu 57 27.01% 27.01% # attempts to use FU when none available
796system.cpu0.iq.fu_full::IntMult 0 0.00% 27.01% # attempts to use FU when none available
797system.cpu0.iq.fu_full::IntDiv 0 0.00% 27.01% # attempts to use FU when none available
798system.cpu0.iq.fu_full::FloatAdd 0 0.00% 27.01% # attempts to use FU when none available
799system.cpu0.iq.fu_full::FloatCmp 0 0.00% 27.01% # attempts to use FU when none available
800system.cpu0.iq.fu_full::FloatCvt 0 0.00% 27.01% # attempts to use FU when none available
801system.cpu0.iq.fu_full::FloatMult 0 0.00% 27.01% # attempts to use FU when none available
802system.cpu0.iq.fu_full::FloatDiv 0 0.00% 27.01% # attempts to use FU when none available
803system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 27.01% # attempts to use FU when none available
804system.cpu0.iq.fu_full::SimdAdd 0 0.00% 27.01% # attempts to use FU when none available
805system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 27.01% # attempts to use FU when none available
806system.cpu0.iq.fu_full::SimdAlu 0 0.00% 27.01% # attempts to use FU when none available
807system.cpu0.iq.fu_full::SimdCmp 0 0.00% 27.01% # attempts to use FU when none available
808system.cpu0.iq.fu_full::SimdCvt 0 0.00% 27.01% # attempts to use FU when none available
809system.cpu0.iq.fu_full::SimdMisc 0 0.00% 27.01% # attempts to use FU when none available
810system.cpu0.iq.fu_full::SimdMult 0 0.00% 27.01% # attempts to use FU when none available
811system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 27.01% # attempts to use FU when none available
812system.cpu0.iq.fu_full::SimdShift 0 0.00% 27.01% # attempts to use FU when none available
813system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 27.01% # attempts to use FU when none available
814system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 27.01% # attempts to use FU when none available
815system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 27.01% # attempts to use FU when none available
816system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 27.01% # attempts to use FU when none available
817system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 27.01% # attempts to use FU when none available
818system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 27.01% # attempts to use FU when none available
819system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 27.01% # attempts to use FU when none available
820system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 27.01% # attempts to use FU when none available
821system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 27.01% # attempts to use FU when none available
822system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.01% # attempts to use FU when none available
823system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 27.01% # attempts to use FU when none available
824system.cpu0.iq.fu_full::MemRead 42 19.91% 46.92% # attempts to use FU when none available
825system.cpu0.iq.fu_full::MemWrite 112 53.08% 100.00% # attempts to use FU when none available
826system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
827system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
828system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
829system.cpu0.iq.FU_type_0::IntAlu 171308 42.29% 42.29% # Type of FU issued
830system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.29% # Type of FU issued
831system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.29% # Type of FU issued
832system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.29% # Type of FU issued
833system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.29% # Type of FU issued
834system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.29% # Type of FU issued
835system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.29% # Type of FU issued
836system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.29% # Type of FU issued
837system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.29% # Type of FU issued
838system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.29% # Type of FU issued
839system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.29% # Type of FU issued
840system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.29% # Type of FU issued
841system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.29% # Type of FU issued
842system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.29% # Type of FU issued
843system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.29% # Type of FU issued
844system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.29% # Type of FU issued
845system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.29% # Type of FU issued
846system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.29% # Type of FU issued
847system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.29% # Type of FU issued
848system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.29% # Type of FU issued
849system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.29% # Type of FU issued
850system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.29% # Type of FU issued
851system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.29% # Type of FU issued
852system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.29% # Type of FU issued
853system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.29% # Type of FU issued
854system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.29% # Type of FU issued
855system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.29% # Type of FU issued
856system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.29% # Type of FU issued
857system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.29% # Type of FU issued
858system.cpu0.iq.FU_type_0::MemRead 155510 38.39% 80.69% # Type of FU issued
859system.cpu0.iq.FU_type_0::MemWrite 78231 19.31% 100.00% # Type of FU issued
860system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
861system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
862system.cpu0.iq.FU_type_0::total 405049 # Type of FU issued
863system.cpu0.iq.rate 1.824118 # Inst issue rate
864system.cpu0.iq.fu_busy_cnt 211 # FU busy when requested
865system.cpu0.iq.fu_busy_rate 0.000521 # FU busy rate (busy events/executed inst)
866system.cpu0.iq.int_inst_queue_reads 1007474 # Number of integer instruction queue reads
867system.cpu0.iq.int_inst_queue_writes 419326 # Number of integer instruction queue writes
868system.cpu0.iq.int_inst_queue_wakeup_accesses 403236 # Number of integer instruction queue wakeup accesses
869system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
870system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
871system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
872system.cpu0.iq.int_alu_accesses 405260 # Number of integer alu accesses
873system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
874system.cpu0.iew.lsq.thread0.forwLoads 75609 # Number of loads that had data forwarded from stores
875system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
876system.cpu0.iew.lsq.thread0.squashedLoads 2132 # Number of loads squashed
877system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
878system.cpu0.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations
879system.cpu0.iew.lsq.thread0.squashedStores 1385 # Number of stores squashed
880system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
881system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
882system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
883system.cpu0.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked
884system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
885system.cpu0.iew.iewSquashCycles 2440 # Number of cycles IEW is squashing
886system.cpu0.iew.iewBlockCycles 371 # Number of cycles IEW is blocking
887system.cpu0.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking
888system.cpu0.iew.iewDispatchedInsts 485139 # Number of instructions dispatched to IQ
889system.cpu0.iew.iewDispSquashedInsts 313 # Number of squashed instructions skipped by dispatch
890system.cpu0.iew.iewDispLoadInsts 155927 # Number of dispatched load instructions
891system.cpu0.iew.iewDispStoreInsts 78789 # Number of dispatched store instructions
892system.cpu0.iew.iewDispNonSpecInsts 806 # Number of dispatched non-speculative instructions
893system.cpu0.iew.iewIQFullEvents 30 # Number of times the IQ has become full, causing a stall
894system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
895system.cpu0.iew.memOrderViolationEvents 44 # Number of memory order violations
896system.cpu0.iew.predictedTakenIncorrect 328 # Number of branches that were predicted taken incorrectly
897system.cpu0.iew.predictedNotTakenIncorrect 1114 # Number of branches that were predicted not taken incorrectly
898system.cpu0.iew.branchMispredicts 1442 # Number of branch mispredicts detected at execute
899system.cpu0.iew.iewExecutedInsts 403978 # Number of executed instructions
900system.cpu0.iew.iewExecLoadInsts 155175 # Number of load instructions executed
901system.cpu0.iew.iewExecSquashedInsts 1071 # Number of squashed instructions skipped in execute
902system.cpu0.iew.exec_swp 0 # number of swp insts executed
903system.cpu0.iew.exec_nop 76577 # number of nop insts executed
904system.cpu0.iew.exec_refs 233309 # number of memory reference insts executed
905system.cpu0.iew.exec_branches 80250 # Number of branches executed
906system.cpu0.iew.exec_stores 78134 # Number of stores executed
907system.cpu0.iew.exec_rate 1.819295 # Inst execution rate
908system.cpu0.iew.wb_sent 403577 # cumulative count of insts sent to commit
909system.cpu0.iew.wb_count 403236 # cumulative count of insts written-back
910system.cpu0.iew.wb_producers 238895 # num instructions producing a value
911system.cpu0.iew.wb_consumers 241362 # num instructions consuming a value
912system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
913system.cpu0.iew.wb_rate 1.815953 # insts written-back per cycle
914system.cpu0.iew.wb_fanout 0.989779 # average fanout of values written-back
915system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
916system.cpu0.commit.commitSquashedInsts 12132 # The number of squashed insts skipped by commit
917system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
918system.cpu0.commit.branchMispredicts 1219 # The number of times a branch was mispredicted
919system.cpu0.commit.committed_per_cycle::samples 194597 # Number of insts commited each cycle
920system.cpu0.commit.committed_per_cycle::mean 2.430500 # Number of insts commited each cycle
921system.cpu0.commit.committed_per_cycle::stdev 2.136019 # Number of insts commited each cycle
922system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
923system.cpu0.commit.committed_per_cycle::0 34534 17.75% 17.75% # Number of insts commited each cycle
924system.cpu0.commit.committed_per_cycle::1 80010 41.12% 58.86% # Number of insts commited each cycle
925system.cpu0.commit.committed_per_cycle::2 2413 1.24% 60.10% # Number of insts commited each cycle
926system.cpu0.commit.committed_per_cycle::3 690 0.35% 60.46% # Number of insts commited each cycle
927system.cpu0.commit.committed_per_cycle::4 532 0.27% 60.73% # Number of insts commited each cycle
928system.cpu0.commit.committed_per_cycle::5 75417 38.76% 99.49% # Number of insts commited each cycle
929system.cpu0.commit.committed_per_cycle::6 460 0.24% 99.72% # Number of insts commited each cycle
930system.cpu0.commit.committed_per_cycle::7 239 0.12% 99.84% # Number of insts commited each cycle
931system.cpu0.commit.committed_per_cycle::8 302 0.16% 100.00% # Number of insts commited each cycle
932system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
933system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
934system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
935system.cpu0.commit.committed_per_cycle::total 194597 # Number of insts commited each cycle
936system.cpu0.commit.committedInsts 472968 # Number of instructions committed
937system.cpu0.commit.committedOps 472968 # Number of ops (including micro ops) committed
938system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
939system.cpu0.commit.refs 231199 # Number of memory references committed
940system.cpu0.commit.loads 153795 # Number of loads committed
941system.cpu0.commit.membars 84 # Number of memory barriers committed
942system.cpu0.commit.branches 79291 # Number of branches committed
943system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
944system.cpu0.commit.int_insts 318742 # Number of committed integer instructions.
945system.cpu0.commit.function_calls 223 # Number of function calls committed.
946system.cpu0.commit.bw_lim_events 302 # number cycles where commit BW limit reached
947system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
948system.cpu0.rob.rob_reads 678234 # The number of ROB reads
949system.cpu0.rob.rob_writes 972657 # The number of ROB writes
950system.cpu0.timesIdled 325 # Number of times that the entire CPU went into an idle state and unscheduled itself
951system.cpu0.idleCycles 25015 # Total number of cycles that the CPU has spent unscheduled due to idling
952system.cpu0.committedInsts 396861 # Number of Instructions Simulated
953system.cpu0.committedOps 396861 # Number of Ops (including micro ops) Simulated
954system.cpu0.committedInsts_total 396861 # Number of Instructions Simulated
955system.cpu0.cpi 0.559521 # CPI: Cycles Per Instruction
956system.cpu0.cpi_total 0.559521 # CPI: Total CPI of All Threads
957system.cpu0.ipc 1.787244 # IPC: Instructions Per Cycle
958system.cpu0.ipc_total 1.787244 # IPC: Total IPC of All Threads
959system.cpu0.int_regfile_reads 722661 # number of integer regfile reads
960system.cpu0.int_regfile_writes 325773 # number of integer regfile writes
961system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
962system.cpu0.misc_regfile_reads 235146 # number of misc regfile reads
963system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
964system.cpu0.icache.tags.replacements 297 # number of replacements
965system.cpu0.icache.tags.tagsinuse 241.313735 # Cycle average of tags in use
966system.cpu0.icache.tags.total_refs 5113 # Total number of references to valid blocks.
967system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks.
968system.cpu0.icache.tags.avg_refs 8.710392 # Average number of references to valid blocks.
969system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
970system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.313735 # Average occupied blocks per requestor
971system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471316 # Average percentage of cache occupancy
972system.cpu0.icache.tags.occ_percent::total 0.471316 # Average percentage of cache occupancy
973system.cpu0.icache.ReadReq_hits::cpu0.inst 5113 # number of ReadReq hits
974system.cpu0.icache.ReadReq_hits::total 5113 # number of ReadReq hits
975system.cpu0.icache.demand_hits::cpu0.inst 5113 # number of demand (read+write) hits
976system.cpu0.icache.demand_hits::total 5113 # number of demand (read+write) hits
977system.cpu0.icache.overall_hits::cpu0.inst 5113 # number of overall hits
978system.cpu0.icache.overall_hits::total 5113 # number of overall hits
979system.cpu0.icache.ReadReq_misses::cpu0.inst 756 # number of ReadReq misses
980system.cpu0.icache.ReadReq_misses::total 756 # number of ReadReq misses
981system.cpu0.icache.demand_misses::cpu0.inst 756 # number of demand (read+write) misses
982system.cpu0.icache.demand_misses::total 756 # number of demand (read+write) misses
983system.cpu0.icache.overall_misses::cpu0.inst 756 # number of overall misses
984system.cpu0.icache.overall_misses::total 756 # number of overall misses
985system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35940245 # number of ReadReq miss cycles
986system.cpu0.icache.ReadReq_miss_latency::total 35940245 # number of ReadReq miss cycles
987system.cpu0.icache.demand_miss_latency::cpu0.inst 35940245 # number of demand (read+write) miss cycles
988system.cpu0.icache.demand_miss_latency::total 35940245 # number of demand (read+write) miss cycles
989system.cpu0.icache.overall_miss_latency::cpu0.inst 35940245 # number of overall miss cycles
990system.cpu0.icache.overall_miss_latency::total 35940245 # number of overall miss cycles
991system.cpu0.icache.ReadReq_accesses::cpu0.inst 5869 # number of ReadReq accesses(hits+misses)
992system.cpu0.icache.ReadReq_accesses::total 5869 # number of ReadReq accesses(hits+misses)
993system.cpu0.icache.demand_accesses::cpu0.inst 5869 # number of demand (read+write) accesses
994system.cpu0.icache.demand_accesses::total 5869 # number of demand (read+write) accesses
995system.cpu0.icache.overall_accesses::cpu0.inst 5869 # number of overall (read+write) accesses
996system.cpu0.icache.overall_accesses::total 5869 # number of overall (read+write) accesses
997system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.128812 # miss rate for ReadReq accesses
998system.cpu0.icache.ReadReq_miss_rate::total 0.128812 # miss rate for ReadReq accesses
999system.cpu0.icache.demand_miss_rate::cpu0.inst 0.128812 # miss rate for demand accesses
1000system.cpu0.icache.demand_miss_rate::total 0.128812 # miss rate for demand accesses
1001system.cpu0.icache.overall_miss_rate::cpu0.inst 0.128812 # miss rate for overall accesses
1002system.cpu0.icache.overall_miss_rate::total 0.128812 # miss rate for overall accesses
1003system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47540.006614 # average ReadReq miss latency
1004system.cpu0.icache.ReadReq_avg_miss_latency::total 47540.006614 # average ReadReq miss latency
1005system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47540.006614 # average overall miss latency
1006system.cpu0.icache.demand_avg_miss_latency::total 47540.006614 # average overall miss latency
1007system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47540.006614 # average overall miss latency
1008system.cpu0.icache.overall_avg_miss_latency::total 47540.006614 # average overall miss latency
1009system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1010system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1011system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1012system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
1013system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1014system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1015system.cpu0.icache.fast_writes 0 # number of fast writes performed
1016system.cpu0.icache.cache_copies 0 # number of cache copies performed

--- 4 unchanged lines hidden (view full) ---

1021system.cpu0.icache.overall_mshr_hits::cpu0.inst 168 # number of overall MSHR hits
1022system.cpu0.icache.overall_mshr_hits::total 168 # number of overall MSHR hits
1023system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 588 # number of ReadReq MSHR misses
1024system.cpu0.icache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses
1025system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 # number of demand (read+write) MSHR misses
1026system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses
1027system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses
1028system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses
1029system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27686252 # number of ReadReq MSHR miss cycles
1030system.cpu0.icache.ReadReq_mshr_miss_latency::total 27686252 # number of ReadReq MSHR miss cycles
1031system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27686252 # number of demand (read+write) MSHR miss cycles
1032system.cpu0.icache.demand_mshr_miss_latency::total 27686252 # number of demand (read+write) MSHR miss cycles
1033system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27686252 # number of overall MSHR miss cycles
1034system.cpu0.icache.overall_mshr_miss_latency::total 27686252 # number of overall MSHR miss cycles
1035system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for ReadReq accesses
1036system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100187 # mshr miss rate for ReadReq accesses
1037system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for demand accesses
1038system.cpu0.icache.demand_mshr_miss_rate::total 0.100187 # mshr miss rate for demand accesses
1039system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for overall accesses
1040system.cpu0.icache.overall_mshr_miss_rate::total 0.100187 # mshr miss rate for overall accesses
1041system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47085.462585 # average ReadReq mshr miss latency
1042system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47085.462585 # average ReadReq mshr miss latency
1043system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47085.462585 # average overall mshr miss latency
1044system.cpu0.icache.demand_avg_mshr_miss_latency::total 47085.462585 # average overall mshr miss latency
1045system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47085.462585 # average overall mshr miss latency
1046system.cpu0.icache.overall_avg_mshr_miss_latency::total 47085.462585 # average overall mshr miss latency
1047system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1048system.cpu0.dcache.tags.replacements 2 # number of replacements
1049system.cpu0.dcache.tags.tagsinuse 142.026994 # Cycle average of tags in use
1050system.cpu0.dcache.tags.total_refs 155821 # Total number of references to valid blocks.
1051system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks.
1052system.cpu0.dcache.tags.avg_refs 916.594118 # Average number of references to valid blocks.
1053system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1054system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.026994 # Average occupied blocks per requestor
1055system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277396 # Average percentage of cache occupancy
1056system.cpu0.dcache.tags.occ_percent::total 0.277396 # Average percentage of cache occupancy
1057system.cpu0.dcache.ReadReq_hits::cpu0.data 79085 # number of ReadReq hits
1058system.cpu0.dcache.ReadReq_hits::total 79085 # number of ReadReq hits
1059system.cpu0.dcache.WriteReq_hits::cpu0.data 76817 # number of WriteReq hits
1060system.cpu0.dcache.WriteReq_hits::total 76817 # number of WriteReq hits
1061system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits
1062system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits
1063system.cpu0.dcache.demand_hits::cpu0.data 155902 # number of demand (read+write) hits
1064system.cpu0.dcache.demand_hits::total 155902 # number of demand (read+write) hits
1065system.cpu0.dcache.overall_hits::cpu0.data 155902 # number of overall hits
1066system.cpu0.dcache.overall_hits::total 155902 # number of overall hits
1067system.cpu0.dcache.ReadReq_misses::cpu0.data 420 # number of ReadReq misses
1068system.cpu0.dcache.ReadReq_misses::total 420 # number of ReadReq misses
1069system.cpu0.dcache.WriteReq_misses::cpu0.data 545 # number of WriteReq misses
1070system.cpu0.dcache.WriteReq_misses::total 545 # number of WriteReq misses
1071system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses
1072system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses
1073system.cpu0.dcache.demand_misses::cpu0.data 965 # number of demand (read+write) misses
1074system.cpu0.dcache.demand_misses::total 965 # number of demand (read+write) misses
1075system.cpu0.dcache.overall_misses::cpu0.data 965 # number of overall misses
1076system.cpu0.dcache.overall_misses::total 965 # number of overall misses
1077system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13542707 # number of ReadReq miss cycles
1078system.cpu0.dcache.ReadReq_miss_latency::total 13542707 # number of ReadReq miss cycles
1079system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32279504 # number of WriteReq miss cycles
1080system.cpu0.dcache.WriteReq_miss_latency::total 32279504 # number of WriteReq miss cycles
1081system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 404750 # number of SwapReq miss cycles
1082system.cpu0.dcache.SwapReq_miss_latency::total 404750 # number of SwapReq miss cycles
1083system.cpu0.dcache.demand_miss_latency::cpu0.data 45822211 # number of demand (read+write) miss cycles
1084system.cpu0.dcache.demand_miss_latency::total 45822211 # number of demand (read+write) miss cycles
1085system.cpu0.dcache.overall_miss_latency::cpu0.data 45822211 # number of overall miss cycles
1086system.cpu0.dcache.overall_miss_latency::total 45822211 # number of overall miss cycles
1087system.cpu0.dcache.ReadReq_accesses::cpu0.data 79505 # number of ReadReq accesses(hits+misses)
1088system.cpu0.dcache.ReadReq_accesses::total 79505 # number of ReadReq accesses(hits+misses)
1089system.cpu0.dcache.WriteReq_accesses::cpu0.data 77362 # number of WriteReq accesses(hits+misses)
1090system.cpu0.dcache.WriteReq_accesses::total 77362 # number of WriteReq accesses(hits+misses)
1091system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
1092system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
1093system.cpu0.dcache.demand_accesses::cpu0.data 156867 # number of demand (read+write) accesses
1094system.cpu0.dcache.demand_accesses::total 156867 # number of demand (read+write) accesses
1095system.cpu0.dcache.overall_accesses::cpu0.data 156867 # number of overall (read+write) accesses
1096system.cpu0.dcache.overall_accesses::total 156867 # number of overall (read+write) accesses
1097system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005283 # miss rate for ReadReq accesses
1098system.cpu0.dcache.ReadReq_miss_rate::total 0.005283 # miss rate for ReadReq accesses
1099system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007045 # miss rate for WriteReq accesses
1100system.cpu0.dcache.WriteReq_miss_rate::total 0.007045 # miss rate for WriteReq accesses
1101system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses
1102system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses
1103system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006152 # miss rate for demand accesses
1104system.cpu0.dcache.demand_miss_rate::total 0.006152 # miss rate for demand accesses
1105system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006152 # miss rate for overall accesses
1106system.cpu0.dcache.overall_miss_rate::total 0.006152 # miss rate for overall accesses
1107system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32244.540476 # average ReadReq miss latency
1108system.cpu0.dcache.ReadReq_avg_miss_latency::total 32244.540476 # average ReadReq miss latency
1109system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 59228.447706 # average WriteReq miss latency
1110system.cpu0.dcache.WriteReq_avg_miss_latency::total 59228.447706 # average WriteReq miss latency
1111system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19273.809524 # average SwapReq miss latency
1112system.cpu0.dcache.SwapReq_avg_miss_latency::total 19273.809524 # average SwapReq miss latency
1113system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47484.156477 # average overall miss latency
1114system.cpu0.dcache.demand_avg_miss_latency::total 47484.156477 # average overall miss latency
1115system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47484.156477 # average overall miss latency
1116system.cpu0.dcache.overall_avg_miss_latency::total 47484.156477 # average overall miss latency
1117system.cpu0.dcache.blocked_cycles::no_mshrs 503 # number of cycles access was blocked
1118system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1119system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked
1120system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
1121system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.952381 # average number of cycles each access was blocked
1122system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1123system.cpu0.dcache.fast_writes 0 # number of fast writes performed
1124system.cpu0.dcache.cache_copies 0 # number of cache copies performed
1125system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
1126system.cpu0.dcache.writebacks::total 1 # number of writebacks
1127system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 227 # number of ReadReq MSHR hits
1128system.cpu0.dcache.ReadReq_mshr_hits::total 227 # number of ReadReq MSHR hits
1129system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 373 # number of WriteReq MSHR hits
1130system.cpu0.dcache.WriteReq_mshr_hits::total 373 # number of WriteReq MSHR hits
1131system.cpu0.dcache.demand_mshr_hits::cpu0.data 600 # number of demand (read+write) MSHR hits
1132system.cpu0.dcache.demand_mshr_hits::total 600 # number of demand (read+write) MSHR hits
1133system.cpu0.dcache.overall_mshr_hits::cpu0.data 600 # number of overall MSHR hits
1134system.cpu0.dcache.overall_mshr_hits::total 600 # number of overall MSHR hits
1135system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 193 # number of ReadReq MSHR misses
1136system.cpu0.dcache.ReadReq_mshr_misses::total 193 # number of ReadReq MSHR misses
1137system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 172 # number of WriteReq MSHR misses
1138system.cpu0.dcache.WriteReq_mshr_misses::total 172 # number of WriteReq MSHR misses
1139system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses
1140system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses
1141system.cpu0.dcache.demand_mshr_misses::cpu0.data 365 # number of demand (read+write) MSHR misses
1142system.cpu0.dcache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses
1143system.cpu0.dcache.overall_mshr_misses::cpu0.data 365 # number of overall MSHR misses
1144system.cpu0.dcache.overall_mshr_misses::total 365 # number of overall MSHR misses
1145system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6251507 # number of ReadReq MSHR miss cycles
1146system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6251507 # number of ReadReq MSHR miss cycles
1147system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7188729 # number of WriteReq MSHR miss cycles
1148system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7188729 # number of WriteReq MSHR miss cycles
1149system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 361250 # number of SwapReq MSHR miss cycles
1150system.cpu0.dcache.SwapReq_mshr_miss_latency::total 361250 # number of SwapReq MSHR miss cycles
1151system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13440236 # number of demand (read+write) MSHR miss cycles
1152system.cpu0.dcache.demand_mshr_miss_latency::total 13440236 # number of demand (read+write) MSHR miss cycles
1153system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13440236 # number of overall MSHR miss cycles
1154system.cpu0.dcache.overall_mshr_miss_latency::total 13440236 # number of overall MSHR miss cycles
1155system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002428 # mshr miss rate for ReadReq accesses
1156system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002428 # mshr miss rate for ReadReq accesses
1157system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002223 # mshr miss rate for WriteReq accesses
1158system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002223 # mshr miss rate for WriteReq accesses
1159system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses
1160system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses
1161system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002327 # mshr miss rate for demand accesses
1162system.cpu0.dcache.demand_mshr_miss_rate::total 0.002327 # mshr miss rate for demand accesses
1163system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002327 # mshr miss rate for overall accesses
1164system.cpu0.dcache.overall_mshr_miss_rate::total 0.002327 # mshr miss rate for overall accesses
1165system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32391.227979 # average ReadReq mshr miss latency
1166system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32391.227979 # average ReadReq mshr miss latency
1167system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41794.936047 # average WriteReq mshr miss latency
1168system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41794.936047 # average WriteReq mshr miss latency
1169system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17202.380952 # average SwapReq mshr miss latency
1170system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17202.380952 # average SwapReq mshr miss latency
1171system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36822.564384 # average overall mshr miss latency
1172system.cpu0.dcache.demand_avg_mshr_miss_latency::total 36822.564384 # average overall mshr miss latency
1173system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 36822.564384 # average overall mshr miss latency
1174system.cpu0.dcache.overall_avg_mshr_miss_latency::total 36822.564384 # average overall mshr miss latency
1175system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1176system.cpu1.branchPred.lookups 47485 # Number of BP lookups
1177system.cpu1.branchPred.condPredicted 44754 # Number of conditional branches predicted
1178system.cpu1.branchPred.condIncorrect 1270 # Number of conditional branches incorrect
1179system.cpu1.branchPred.BTBLookups 41396 # Number of BTB lookups
1180system.cpu1.branchPred.BTBHits 40599 # Number of BTB hits
1181system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1182system.cpu1.branchPred.BTBHitPct 98.074693 # BTB Hit Percentage
1183system.cpu1.branchPred.usedRAS 654 # Number of times the RAS was used to get a target.
1184system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
1185system.cpu1.numCycles 177933 # number of cpu cycles simulated
1186system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1187system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1188system.cpu1.fetch.icacheStallCycles 31734 # Number of cycles fetch is stalled on an Icache miss
1189system.cpu1.fetch.Insts 260080 # Number of instructions fetch has processed
1190system.cpu1.fetch.Branches 47485 # Number of branches that fetch encountered
1191system.cpu1.fetch.predictedBranches 41253 # Number of branches that fetch has predicted taken
1192system.cpu1.fetch.Cycles 95164 # Number of cycles fetch has run and was not squashing or blocked
1193system.cpu1.fetch.SquashCycles 3727 # Number of cycles fetch has spent squashing
1194system.cpu1.fetch.BlockedCycles 37889 # Number of cycles fetch has spent blocked
1195system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1196system.cpu1.fetch.NoActiveThreadStallCycles 7775 # Number of stall cycles due to no active thread to fetch from
1197system.cpu1.fetch.PendingTrapStallCycles 775 # Number of stall cycles due to pending traps
1198system.cpu1.fetch.CacheLines 23379 # Number of cache lines fetched
1199system.cpu1.fetch.IcacheSquashes 257 # Number of outstanding Icache misses that were squashed
1200system.cpu1.fetch.rateDist::samples 175722 # Number of instructions fetched each cycle (Total)
1201system.cpu1.fetch.rateDist::mean 1.480065 # Number of instructions fetched each cycle (Total)
1202system.cpu1.fetch.rateDist::stdev 2.059330 # Number of instructions fetched each cycle (Total)
1203system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1204system.cpu1.fetch.rateDist::0 80558 45.84% 45.84% # Number of instructions fetched each cycle (Total)
1205system.cpu1.fetch.rateDist::1 49339 28.08% 73.92% # Number of instructions fetched each cycle (Total)
1206system.cpu1.fetch.rateDist::2 7969 4.54% 78.46% # Number of instructions fetched each cycle (Total)
1207system.cpu1.fetch.rateDist::3 3191 1.82% 80.27% # Number of instructions fetched each cycle (Total)
1208system.cpu1.fetch.rateDist::4 687 0.39% 80.66% # Number of instructions fetched each cycle (Total)
1209system.cpu1.fetch.rateDist::5 28723 16.35% 97.01% # Number of instructions fetched each cycle (Total)
1210system.cpu1.fetch.rateDist::6 1207 0.69% 97.70% # Number of instructions fetched each cycle (Total)
1211system.cpu1.fetch.rateDist::7 759 0.43% 98.13% # Number of instructions fetched each cycle (Total)
1212system.cpu1.fetch.rateDist::8 3289 1.87% 100.00% # Number of instructions fetched each cycle (Total)
1213system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1214system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1215system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
1216system.cpu1.fetch.rateDist::total 175722 # Number of instructions fetched each cycle (Total)
1217system.cpu1.fetch.branchRate 0.266870 # Number of branch fetches per cycle
1218system.cpu1.fetch.rate 1.461674 # Number of inst fetches per cycle
1219system.cpu1.decode.IdleCycles 38713 # Number of cycles decode is idle
1220system.cpu1.decode.BlockedCycles 32553 # Number of cycles decode is blocked
1221system.cpu1.decode.RunCycles 87468 # Number of cycles decode is running
1222system.cpu1.decode.UnblockCycles 6833 # Number of cycles decode is unblocking
1223system.cpu1.decode.SquashCycles 2380 # Number of cycles decode is squashing
1224system.cpu1.decode.DecodedInsts 256418 # Number of instructions handled by decode
1225system.cpu1.rename.SquashCycles 2380 # Number of cycles rename is squashing
1226system.cpu1.rename.IdleCycles 39395 # Number of cycles rename is idle
1227system.cpu1.rename.BlockCycles 20083 # Number of cycles rename is blocking
1228system.cpu1.rename.serializeStallCycles 11723 # count of cycles rename stalled for serializing inst
1229system.cpu1.rename.RunCycles 80903 # Number of cycles rename is running
1230system.cpu1.rename.UnblockCycles 13463 # Number of cycles rename is unblocking
1231system.cpu1.rename.RenamedInsts 254199 # Number of instructions processed by rename
1232system.cpu1.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
1233system.cpu1.rename.LSQFullEvents 22 # Number of times rename has blocked due to LSQ full
1234system.cpu1.rename.RenamedOperands 175957 # Number of destination operands rename has renamed
1235system.cpu1.rename.RenameLookups 477753 # Number of register rename lookups that rename has made
1236system.cpu1.rename.int_rename_lookups 373133 # Number of integer rename lookups
1237system.cpu1.rename.CommittedMaps 162997 # Number of HB maps that are committed
1238system.cpu1.rename.UndoneMaps 12960 # Number of HB maps that are undone due to squashing
1239system.cpu1.rename.serializingInsts 1085 # count of serializing insts renamed
1240system.cpu1.rename.tempSerializingInsts 1202 # count of temporary serializing insts renamed
1241system.cpu1.rename.skidInsts 16072 # count of insts added to the skid buffer
1242system.cpu1.memDep0.insertedLoads 69810 # Number of loads inserted to the mem dependence unit.
1243system.cpu1.memDep0.insertedStores 31966 # Number of stores inserted to the mem dependence unit.
1244system.cpu1.memDep0.conflictingLoads 34021 # Number of conflicting loads.
1245system.cpu1.memDep0.conflictingStores 26934 # Number of conflicting stores.
1246system.cpu1.iq.iqInstsAdded 208112 # Number of instructions added to the IQ (excludes non-spec)
1247system.cpu1.iq.iqNonSpecInstsAdded 8163 # Number of non-speculative instructions added to the IQ
1248system.cpu1.iq.iqInstsIssued 211924 # Number of instructions issued
1249system.cpu1.iq.iqSquashedInstsIssued 72 # Number of squashed instructions issued
1250system.cpu1.iq.iqSquashedInstsExamined 10867 # Number of squashed instructions iterated over during squash; mainly for profiling
1251system.cpu1.iq.iqSquashedOperandsExamined 10911 # Number of squashed operands that are examined and possibly removed from graph
1252system.cpu1.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed
1253system.cpu1.iq.issued_per_cycle::samples 175722 # Number of insts issued each cycle
1254system.cpu1.iq.issued_per_cycle::mean 1.206019 # Number of insts issued each cycle
1255system.cpu1.iq.issued_per_cycle::stdev 1.291588 # Number of insts issued each cycle
1256system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1257system.cpu1.iq.issued_per_cycle::0 78073 44.43% 44.43% # Number of insts issued each cycle
1258system.cpu1.iq.issued_per_cycle::1 27855 15.85% 60.28% # Number of insts issued each cycle
1259system.cpu1.iq.issued_per_cycle::2 32175 18.31% 78.59% # Number of insts issued each cycle
1260system.cpu1.iq.issued_per_cycle::3 32801 18.67% 97.26% # Number of insts issued each cycle
1261system.cpu1.iq.issued_per_cycle::4 3291 1.87% 99.13% # Number of insts issued each cycle
1262system.cpu1.iq.issued_per_cycle::5 1173 0.67% 99.80% # Number of insts issued each cycle
1263system.cpu1.iq.issued_per_cycle::6 248 0.14% 99.94% # Number of insts issued each cycle
1264system.cpu1.iq.issued_per_cycle::7 49 0.03% 99.97% # Number of insts issued each cycle
1265system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle
1266system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1267system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1268system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
1269system.cpu1.iq.issued_per_cycle::total 175722 # Number of insts issued each cycle
1270system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1271system.cpu1.iq.fu_full::IntAlu 12 4.51% 4.51% # attempts to use FU when none available
1272system.cpu1.iq.fu_full::IntMult 0 0.00% 4.51% # attempts to use FU when none available
1273system.cpu1.iq.fu_full::IntDiv 0 0.00% 4.51% # attempts to use FU when none available
1274system.cpu1.iq.fu_full::FloatAdd 0 0.00% 4.51% # attempts to use FU when none available
1275system.cpu1.iq.fu_full::FloatCmp 0 0.00% 4.51% # attempts to use FU when none available
1276system.cpu1.iq.fu_full::FloatCvt 0 0.00% 4.51% # attempts to use FU when none available
1277system.cpu1.iq.fu_full::FloatMult 0 0.00% 4.51% # attempts to use FU when none available
1278system.cpu1.iq.fu_full::FloatDiv 0 0.00% 4.51% # attempts to use FU when none available
1279system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 4.51% # attempts to use FU when none available
1280system.cpu1.iq.fu_full::SimdAdd 0 0.00% 4.51% # attempts to use FU when none available
1281system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 4.51% # attempts to use FU when none available
1282system.cpu1.iq.fu_full::SimdAlu 0 0.00% 4.51% # attempts to use FU when none available
1283system.cpu1.iq.fu_full::SimdCmp 0 0.00% 4.51% # attempts to use FU when none available
1284system.cpu1.iq.fu_full::SimdCvt 0 0.00% 4.51% # attempts to use FU when none available
1285system.cpu1.iq.fu_full::SimdMisc 0 0.00% 4.51% # attempts to use FU when none available
1286system.cpu1.iq.fu_full::SimdMult 0 0.00% 4.51% # attempts to use FU when none available
1287system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 4.51% # attempts to use FU when none available
1288system.cpu1.iq.fu_full::SimdShift 0 0.00% 4.51% # attempts to use FU when none available
1289system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 4.51% # attempts to use FU when none available
1290system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 4.51% # attempts to use FU when none available
1291system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 4.51% # attempts to use FU when none available
1292system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 4.51% # attempts to use FU when none available
1293system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 4.51% # attempts to use FU when none available
1294system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 4.51% # attempts to use FU when none available
1295system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 4.51% # attempts to use FU when none available
1296system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 4.51% # attempts to use FU when none available
1297system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 4.51% # attempts to use FU when none available
1298system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.51% # attempts to use FU when none available
1299system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 4.51% # attempts to use FU when none available
1300system.cpu1.iq.fu_full::MemRead 44 16.54% 21.05% # attempts to use FU when none available
1301system.cpu1.iq.fu_full::MemWrite 210 78.95% 100.00% # attempts to use FU when none available
1302system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1303system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1304system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
1305system.cpu1.iq.FU_type_0::IntAlu 104746 49.43% 49.43% # Type of FU issued
1306system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.43% # Type of FU issued
1307system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.43% # Type of FU issued
1308system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.43% # Type of FU issued
1309system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.43% # Type of FU issued
1310system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.43% # Type of FU issued
1311system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.43% # Type of FU issued
1312system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.43% # Type of FU issued
1313system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.43% # Type of FU issued
1314system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.43% # Type of FU issued
1315system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.43% # Type of FU issued
1316system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.43% # Type of FU issued
1317system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.43% # Type of FU issued
1318system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.43% # Type of FU issued
1319system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.43% # Type of FU issued
1320system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.43% # Type of FU issued
1321system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.43% # Type of FU issued
1322system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.43% # Type of FU issued
1323system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.43% # Type of FU issued
1324system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.43% # Type of FU issued
1325system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.43% # Type of FU issued
1326system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.43% # Type of FU issued
1327system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.43% # Type of FU issued
1328system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.43% # Type of FU issued
1329system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.43% # Type of FU issued
1330system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.43% # Type of FU issued
1331system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.43% # Type of FU issued
1332system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.43% # Type of FU issued
1333system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.43% # Type of FU issued
1334system.cpu1.iq.FU_type_0::MemRead 75900 35.81% 85.24% # Type of FU issued
1335system.cpu1.iq.FU_type_0::MemWrite 31278 14.76% 100.00% # Type of FU issued
1336system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1337system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1338system.cpu1.iq.FU_type_0::total 211924 # Type of FU issued
1339system.cpu1.iq.rate 1.191033 # Inst issue rate
1340system.cpu1.iq.fu_busy_cnt 266 # FU busy when requested
1341system.cpu1.iq.fu_busy_rate 0.001255 # FU busy rate (busy events/executed inst)
1342system.cpu1.iq.int_inst_queue_reads 599908 # Number of integer instruction queue reads
1343system.cpu1.iq.int_inst_queue_writes 227186 # Number of integer instruction queue writes
1344system.cpu1.iq.int_inst_queue_wakeup_accesses 210080 # Number of integer instruction queue wakeup accesses
1345system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
1346system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
1347system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
1348system.cpu1.iq.int_alu_accesses 212190 # Number of integer alu accesses
1349system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
1350system.cpu1.iew.lsq.thread0.forwLoads 26664 # Number of loads that had data forwarded from stores
1351system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1352system.cpu1.iew.lsq.thread0.squashedLoads 2449 # Number of loads squashed
1353system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
1354system.cpu1.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations
1355system.cpu1.iew.lsq.thread0.squashedStores 1447 # Number of stores squashed
1356system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1357system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1358system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
1359system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
1360system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1361system.cpu1.iew.iewSquashCycles 2380 # Number of cycles IEW is squashing
1362system.cpu1.iew.iewBlockCycles 699 # Number of cycles IEW is blocking
1363system.cpu1.iew.iewUnblockCycles 40 # Number of cycles IEW is unblocking
1364system.cpu1.iew.iewDispatchedInsts 251202 # Number of instructions dispatched to IQ
1365system.cpu1.iew.iewDispSquashedInsts 408 # Number of squashed instructions skipped by dispatch
1366system.cpu1.iew.iewDispLoadInsts 69810 # Number of dispatched load instructions
1367system.cpu1.iew.iewDispStoreInsts 31966 # Number of dispatched store instructions
1368system.cpu1.iew.iewDispNonSpecInsts 1044 # Number of dispatched non-speculative instructions
1369system.cpu1.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall
1370system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
1371system.cpu1.iew.memOrderViolationEvents 44 # Number of memory order violations
1372system.cpu1.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly
1373system.cpu1.iew.predictedNotTakenIncorrect 919 # Number of branches that were predicted not taken incorrectly
1374system.cpu1.iew.branchMispredicts 1389 # Number of branch mispredicts detected at execute
1375system.cpu1.iew.iewExecutedInsts 210729 # Number of executed instructions
1376system.cpu1.iew.iewExecLoadInsts 68768 # Number of load instructions executed
1377system.cpu1.iew.iewExecSquashedInsts 1195 # Number of squashed instructions skipped in execute
1378system.cpu1.iew.exec_swp 0 # number of swp insts executed
1379system.cpu1.iew.exec_nop 34927 # number of nop insts executed
1380system.cpu1.iew.exec_refs 99964 # number of memory reference insts executed
1381system.cpu1.iew.exec_branches 44131 # Number of branches executed
1382system.cpu1.iew.exec_stores 31196 # Number of stores executed
1383system.cpu1.iew.exec_rate 1.184317 # Inst execution rate
1384system.cpu1.iew.wb_sent 210404 # cumulative count of insts sent to commit
1385system.cpu1.iew.wb_count 210080 # cumulative count of insts written-back
1386system.cpu1.iew.wb_producers 116723 # num instructions producing a value
1387system.cpu1.iew.wb_consumers 121388 # num instructions consuming a value
1388system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1389system.cpu1.iew.wb_rate 1.180669 # insts written-back per cycle
1390system.cpu1.iew.wb_fanout 0.961570 # average fanout of values written-back
1391system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1392system.cpu1.commit.commitSquashedInsts 12479 # The number of squashed insts skipped by commit
1393system.cpu1.commit.commitNonSpecStalls 7561 # The number of times commit has been forced to stall to communicate backwards
1394system.cpu1.commit.branchMispredicts 1270 # The number of times a branch was mispredicted
1395system.cpu1.commit.committed_per_cycle::samples 165567 # Number of insts commited each cycle
1396system.cpu1.commit.committed_per_cycle::mean 1.441743 # Number of insts commited each cycle
1397system.cpu1.commit.committed_per_cycle::stdev 1.939965 # Number of insts commited each cycle
1398system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1399system.cpu1.commit.committed_per_cycle::0 77636 46.89% 46.89% # Number of insts commited each cycle
1400system.cpu1.commit.committed_per_cycle::1 42274 25.53% 72.42% # Number of insts commited each cycle
1401system.cpu1.commit.committed_per_cycle::2 6096 3.68% 76.11% # Number of insts commited each cycle
1402system.cpu1.commit.committed_per_cycle::3 8474 5.12% 81.22% # Number of insts commited each cycle
1403system.cpu1.commit.committed_per_cycle::4 1557 0.94% 82.16% # Number of insts commited each cycle
1404system.cpu1.commit.committed_per_cycle::5 27207 16.43% 98.60% # Number of insts commited each cycle
1405system.cpu1.commit.committed_per_cycle::6 510 0.31% 98.90% # Number of insts commited each cycle
1406system.cpu1.commit.committed_per_cycle::7 1010 0.61% 99.51% # Number of insts commited each cycle
1407system.cpu1.commit.committed_per_cycle::8 803 0.49% 100.00% # Number of insts commited each cycle
1408system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1409system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1410system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1411system.cpu1.commit.committed_per_cycle::total 165567 # Number of insts commited each cycle
1412system.cpu1.commit.committedInsts 238705 # Number of instructions committed
1413system.cpu1.commit.committedOps 238705 # Number of ops (including micro ops) committed
1414system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
1415system.cpu1.commit.refs 97880 # Number of memory references committed
1416system.cpu1.commit.loads 67361 # Number of loads committed
1417system.cpu1.commit.membars 6845 # Number of memory barriers committed
1418system.cpu1.commit.branches 43327 # Number of branches committed
1419system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
1420system.cpu1.commit.int_insts 163326 # Number of committed integer instructions.
1421system.cpu1.commit.function_calls 322 # Number of function calls committed.
1422system.cpu1.commit.bw_lim_events 803 # number cycles where commit BW limit reached
1423system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
1424system.cpu1.rob.rob_reads 415361 # The number of ROB reads
1425system.cpu1.rob.rob_writes 504754 # The number of ROB writes
1426system.cpu1.timesIdled 217 # Number of times that the entire CPU went into an idle state and unscheduled itself
1427system.cpu1.idleCycles 2211 # Total number of cycles that the CPU has spent unscheduled due to idling
1428system.cpu1.quiesceCycles 44117 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1429system.cpu1.committedInsts 197745 # Number of Instructions Simulated
1430system.cpu1.committedOps 197745 # Number of Ops (including micro ops) Simulated
1431system.cpu1.committedInsts_total 197745 # Number of Instructions Simulated
1432system.cpu1.cpi 0.899810 # CPI: Cycles Per Instruction
1433system.cpu1.cpi_total 0.899810 # CPI: Total CPI of All Threads
1434system.cpu1.ipc 1.111345 # IPC: Instructions Per Cycle
1435system.cpu1.ipc_total 1.111345 # IPC: Total IPC of All Threads
1436system.cpu1.int_regfile_reads 358439 # number of integer regfile reads
1437system.cpu1.int_regfile_writes 167816 # number of integer regfile writes
1438system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
1439system.cpu1.misc_regfile_reads 101509 # number of misc regfile reads
1440system.cpu1.misc_regfile_writes 648 # number of misc regfile writes
1441system.cpu1.icache.tags.replacements 318 # number of replacements
1442system.cpu1.icache.tags.tagsinuse 76.730522 # Cycle average of tags in use
1443system.cpu1.icache.tags.total_refs 22903 # Total number of references to valid blocks.
1444system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks.
1445system.cpu1.icache.tags.avg_refs 53.511682 # Average number of references to valid blocks.
1446system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1447system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.730522 # Average occupied blocks per requestor
1448system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149864 # Average percentage of cache occupancy
1449system.cpu1.icache.tags.occ_percent::total 0.149864 # Average percentage of cache occupancy
1450system.cpu1.icache.ReadReq_hits::cpu1.inst 22903 # number of ReadReq hits
1451system.cpu1.icache.ReadReq_hits::total 22903 # number of ReadReq hits
1452system.cpu1.icache.demand_hits::cpu1.inst 22903 # number of demand (read+write) hits
1453system.cpu1.icache.demand_hits::total 22903 # number of demand (read+write) hits
1454system.cpu1.icache.overall_hits::cpu1.inst 22903 # number of overall hits
1455system.cpu1.icache.overall_hits::total 22903 # number of overall hits
1456system.cpu1.icache.ReadReq_misses::cpu1.inst 476 # number of ReadReq misses
1457system.cpu1.icache.ReadReq_misses::total 476 # number of ReadReq misses
1458system.cpu1.icache.demand_misses::cpu1.inst 476 # number of demand (read+write) misses
1459system.cpu1.icache.demand_misses::total 476 # number of demand (read+write) misses
1460system.cpu1.icache.overall_misses::cpu1.inst 476 # number of overall misses
1461system.cpu1.icache.overall_misses::total 476 # number of overall misses
1462system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7185993 # number of ReadReq miss cycles
1463system.cpu1.icache.ReadReq_miss_latency::total 7185993 # number of ReadReq miss cycles
1464system.cpu1.icache.demand_miss_latency::cpu1.inst 7185993 # number of demand (read+write) miss cycles
1465system.cpu1.icache.demand_miss_latency::total 7185993 # number of demand (read+write) miss cycles
1466system.cpu1.icache.overall_miss_latency::cpu1.inst 7185993 # number of overall miss cycles
1467system.cpu1.icache.overall_miss_latency::total 7185993 # number of overall miss cycles
1468system.cpu1.icache.ReadReq_accesses::cpu1.inst 23379 # number of ReadReq accesses(hits+misses)
1469system.cpu1.icache.ReadReq_accesses::total 23379 # number of ReadReq accesses(hits+misses)
1470system.cpu1.icache.demand_accesses::cpu1.inst 23379 # number of demand (read+write) accesses
1471system.cpu1.icache.demand_accesses::total 23379 # number of demand (read+write) accesses
1472system.cpu1.icache.overall_accesses::cpu1.inst 23379 # number of overall (read+write) accesses
1473system.cpu1.icache.overall_accesses::total 23379 # number of overall (read+write) accesses
1474system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.020360 # miss rate for ReadReq accesses
1475system.cpu1.icache.ReadReq_miss_rate::total 0.020360 # miss rate for ReadReq accesses
1476system.cpu1.icache.demand_miss_rate::cpu1.inst 0.020360 # miss rate for demand accesses
1477system.cpu1.icache.demand_miss_rate::total 0.020360 # miss rate for demand accesses
1478system.cpu1.icache.overall_miss_rate::cpu1.inst 0.020360 # miss rate for overall accesses
1479system.cpu1.icache.overall_miss_rate::total 0.020360 # miss rate for overall accesses
1480system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15096.623950 # average ReadReq miss latency
1481system.cpu1.icache.ReadReq_avg_miss_latency::total 15096.623950 # average ReadReq miss latency
1482system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15096.623950 # average overall miss latency
1483system.cpu1.icache.demand_avg_miss_latency::total 15096.623950 # average overall miss latency
1484system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15096.623950 # average overall miss latency
1485system.cpu1.icache.overall_avg_miss_latency::total 15096.623950 # average overall miss latency
1486system.cpu1.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked
1487system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1488system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked
1489system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1490system.cpu1.icache.avg_blocked_cycles::no_mshrs 13 # average number of cycles each access was blocked
1491system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1492system.cpu1.icache.fast_writes 0 # number of fast writes performed
1493system.cpu1.icache.cache_copies 0 # number of cache copies performed
1494system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 48 # number of ReadReq MSHR hits
1495system.cpu1.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits
1496system.cpu1.icache.demand_mshr_hits::cpu1.inst 48 # number of demand (read+write) MSHR hits
1497system.cpu1.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits
1498system.cpu1.icache.overall_mshr_hits::cpu1.inst 48 # number of overall MSHR hits
1499system.cpu1.icache.overall_mshr_hits::total 48 # number of overall MSHR hits
1500system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 428 # number of ReadReq MSHR misses
1501system.cpu1.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses
1502system.cpu1.icache.demand_mshr_misses::cpu1.inst 428 # number of demand (read+write) MSHR misses
1503system.cpu1.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses
1504system.cpu1.icache.overall_mshr_misses::cpu1.inst 428 # number of overall MSHR misses
1505system.cpu1.icache.overall_mshr_misses::total 428 # number of overall MSHR misses
1506system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5726006 # number of ReadReq MSHR miss cycles
1507system.cpu1.icache.ReadReq_mshr_miss_latency::total 5726006 # number of ReadReq MSHR miss cycles
1508system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5726006 # number of demand (read+write) MSHR miss cycles
1509system.cpu1.icache.demand_mshr_miss_latency::total 5726006 # number of demand (read+write) MSHR miss cycles
1510system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5726006 # number of overall MSHR miss cycles
1511system.cpu1.icache.overall_mshr_miss_latency::total 5726006 # number of overall MSHR miss cycles
1512system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for ReadReq accesses
1513system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.018307 # mshr miss rate for ReadReq accesses
1514system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for demand accesses
1515system.cpu1.icache.demand_mshr_miss_rate::total 0.018307 # mshr miss rate for demand accesses
1516system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for overall accesses
1517system.cpu1.icache.overall_mshr_miss_rate::total 0.018307 # mshr miss rate for overall accesses
1518system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13378.518692 # average ReadReq mshr miss latency
1519system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13378.518692 # average ReadReq mshr miss latency
1520system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13378.518692 # average overall mshr miss latency
1521system.cpu1.icache.demand_avg_mshr_miss_latency::total 13378.518692 # average overall mshr miss latency
1522system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13378.518692 # average overall mshr miss latency
1523system.cpu1.icache.overall_avg_mshr_miss_latency::total 13378.518692 # average overall mshr miss latency
1524system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1525system.cpu1.dcache.tags.replacements 0 # number of replacements
1526system.cpu1.dcache.tags.tagsinuse 23.664777 # Cycle average of tags in use
1527system.cpu1.dcache.tags.total_refs 36646 # Total number of references to valid blocks.
1528system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
1529system.cpu1.dcache.tags.avg_refs 1263.655172 # Average number of references to valid blocks.
1530system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1531system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.664777 # Average occupied blocks per requestor
1532system.cpu1.dcache.tags.occ_percent::cpu1.data 0.046220 # Average percentage of cache occupancy
1533system.cpu1.dcache.tags.occ_percent::total 0.046220 # Average percentage of cache occupancy
1534system.cpu1.dcache.ReadReq_hits::cpu1.data 41736 # number of ReadReq hits
1535system.cpu1.dcache.ReadReq_hits::total 41736 # number of ReadReq hits
1536system.cpu1.dcache.WriteReq_hits::cpu1.data 30310 # number of WriteReq hits
1537system.cpu1.dcache.WriteReq_hits::total 30310 # number of WriteReq hits
1538system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits
1539system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits
1540system.cpu1.dcache.demand_hits::cpu1.data 72046 # number of demand (read+write) hits
1541system.cpu1.dcache.demand_hits::total 72046 # number of demand (read+write) hits
1542system.cpu1.dcache.overall_hits::cpu1.data 72046 # number of overall hits
1543system.cpu1.dcache.overall_hits::total 72046 # number of overall hits
1544system.cpu1.dcache.ReadReq_misses::cpu1.data 352 # number of ReadReq misses
1545system.cpu1.dcache.ReadReq_misses::total 352 # number of ReadReq misses
1546system.cpu1.dcache.WriteReq_misses::cpu1.data 139 # number of WriteReq misses
1547system.cpu1.dcache.WriteReq_misses::total 139 # number of WriteReq misses
1548system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses
1549system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses
1550system.cpu1.dcache.demand_misses::cpu1.data 491 # number of demand (read+write) misses
1551system.cpu1.dcache.demand_misses::total 491 # number of demand (read+write) misses
1552system.cpu1.dcache.overall_misses::cpu1.data 491 # number of overall misses
1553system.cpu1.dcache.overall_misses::total 491 # number of overall misses
1554system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4404095 # number of ReadReq miss cycles
1555system.cpu1.dcache.ReadReq_miss_latency::total 4404095 # number of ReadReq miss cycles
1556system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2802760 # number of WriteReq miss cycles
1557system.cpu1.dcache.WriteReq_miss_latency::total 2802760 # number of WriteReq miss cycles
1558system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 563508 # number of SwapReq miss cycles
1559system.cpu1.dcache.SwapReq_miss_latency::total 563508 # number of SwapReq miss cycles
1560system.cpu1.dcache.demand_miss_latency::cpu1.data 7206855 # number of demand (read+write) miss cycles
1561system.cpu1.dcache.demand_miss_latency::total 7206855 # number of demand (read+write) miss cycles
1562system.cpu1.dcache.overall_miss_latency::cpu1.data 7206855 # number of overall miss cycles
1563system.cpu1.dcache.overall_miss_latency::total 7206855 # number of overall miss cycles
1564system.cpu1.dcache.ReadReq_accesses::cpu1.data 42088 # number of ReadReq accesses(hits+misses)
1565system.cpu1.dcache.ReadReq_accesses::total 42088 # number of ReadReq accesses(hits+misses)
1566system.cpu1.dcache.WriteReq_accesses::cpu1.data 30449 # number of WriteReq accesses(hits+misses)
1567system.cpu1.dcache.WriteReq_accesses::total 30449 # number of WriteReq accesses(hits+misses)
1568system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses)
1569system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses)
1570system.cpu1.dcache.demand_accesses::cpu1.data 72537 # number of demand (read+write) accesses
1571system.cpu1.dcache.demand_accesses::total 72537 # number of demand (read+write) accesses
1572system.cpu1.dcache.overall_accesses::cpu1.data 72537 # number of overall (read+write) accesses
1573system.cpu1.dcache.overall_accesses::total 72537 # number of overall (read+write) accesses
1574system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008363 # miss rate for ReadReq accesses
1575system.cpu1.dcache.ReadReq_miss_rate::total 0.008363 # miss rate for ReadReq accesses
1576system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004565 # miss rate for WriteReq accesses
1577system.cpu1.dcache.WriteReq_miss_rate::total 0.004565 # miss rate for WriteReq accesses
1578system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.814286 # miss rate for SwapReq accesses
1579system.cpu1.dcache.SwapReq_miss_rate::total 0.814286 # miss rate for SwapReq accesses
1580system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006769 # miss rate for demand accesses
1581system.cpu1.dcache.demand_miss_rate::total 0.006769 # miss rate for demand accesses
1582system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006769 # miss rate for overall accesses
1583system.cpu1.dcache.overall_miss_rate::total 0.006769 # miss rate for overall accesses
1584system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12511.633523 # average ReadReq miss latency
1585system.cpu1.dcache.ReadReq_avg_miss_latency::total 12511.633523 # average ReadReq miss latency
1586system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20163.741007 # average WriteReq miss latency
1587system.cpu1.dcache.WriteReq_avg_miss_latency::total 20163.741007 # average WriteReq miss latency
1588system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9886.105263 # average SwapReq miss latency
1589system.cpu1.dcache.SwapReq_avg_miss_latency::total 9886.105263 # average SwapReq miss latency
1590system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14677.912424 # average overall miss latency
1591system.cpu1.dcache.demand_avg_miss_latency::total 14677.912424 # average overall miss latency
1592system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14677.912424 # average overall miss latency
1593system.cpu1.dcache.overall_avg_miss_latency::total 14677.912424 # average overall miss latency
1594system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1595system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1596system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1597system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1598system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1599system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1600system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1601system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1602system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 187 # number of ReadReq MSHR hits
1603system.cpu1.dcache.ReadReq_mshr_hits::total 187 # number of ReadReq MSHR hits
1604system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits
1605system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits
1606system.cpu1.dcache.demand_mshr_hits::cpu1.data 219 # number of demand (read+write) MSHR hits
1607system.cpu1.dcache.demand_mshr_hits::total 219 # number of demand (read+write) MSHR hits
1608system.cpu1.dcache.overall_mshr_hits::cpu1.data 219 # number of overall MSHR hits
1609system.cpu1.dcache.overall_mshr_hits::total 219 # number of overall MSHR hits
1610system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 165 # number of ReadReq MSHR misses
1611system.cpu1.dcache.ReadReq_mshr_misses::total 165 # number of ReadReq MSHR misses
1612system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses
1613system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses
1614system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 57 # number of SwapReq MSHR misses
1615system.cpu1.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses
1616system.cpu1.dcache.demand_mshr_misses::cpu1.data 272 # number of demand (read+write) MSHR misses
1617system.cpu1.dcache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses
1618system.cpu1.dcache.overall_mshr_misses::cpu1.data 272 # number of overall MSHR misses
1619system.cpu1.dcache.overall_mshr_misses::total 272 # number of overall MSHR misses
1620system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1130523 # number of ReadReq MSHR miss cycles
1621system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1130523 # number of ReadReq MSHR miss cycles
1622system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1329240 # number of WriteReq MSHR miss cycles
1623system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1329240 # number of WriteReq MSHR miss cycles
1624system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 449492 # number of SwapReq MSHR miss cycles
1625system.cpu1.dcache.SwapReq_mshr_miss_latency::total 449492 # number of SwapReq MSHR miss cycles
1626system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2459763 # number of demand (read+write) MSHR miss cycles
1627system.cpu1.dcache.demand_mshr_miss_latency::total 2459763 # number of demand (read+write) MSHR miss cycles
1628system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2459763 # number of overall MSHR miss cycles
1629system.cpu1.dcache.overall_mshr_miss_latency::total 2459763 # number of overall MSHR miss cycles
1630system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003920 # mshr miss rate for ReadReq accesses
1631system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003920 # mshr miss rate for ReadReq accesses
1632system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003514 # mshr miss rate for WriteReq accesses
1633system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003514 # mshr miss rate for WriteReq accesses
1634system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.814286 # mshr miss rate for SwapReq accesses
1635system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.814286 # mshr miss rate for SwapReq accesses
1636system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003750 # mshr miss rate for demand accesses
1637system.cpu1.dcache.demand_mshr_miss_rate::total 0.003750 # mshr miss rate for demand accesses
1638system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003750 # mshr miss rate for overall accesses
1639system.cpu1.dcache.overall_mshr_miss_rate::total 0.003750 # mshr miss rate for overall accesses
1640system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6851.654545 # average ReadReq mshr miss latency
1641system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6851.654545 # average ReadReq mshr miss latency
1642system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12422.803738 # average WriteReq mshr miss latency
1643system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12422.803738 # average WriteReq mshr miss latency
1644system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7885.824561 # average SwapReq mshr miss latency
1645system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7885.824561 # average SwapReq mshr miss latency
1646system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9043.246324 # average overall mshr miss latency
1647system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9043.246324 # average overall mshr miss latency
1648system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9043.246324 # average overall mshr miss latency
1649system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9043.246324 # average overall mshr miss latency
1650system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1651system.cpu2.branchPred.lookups 51290 # Number of BP lookups
1652system.cpu2.branchPred.condPredicted 48575 # Number of conditional branches predicted
1653system.cpu2.branchPred.condIncorrect 1303 # Number of conditional branches incorrect
1654system.cpu2.branchPred.BTBLookups 45092 # Number of BTB lookups
1655system.cpu2.branchPred.BTBHits 44400 # Number of BTB hits
1656system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1657system.cpu2.branchPred.BTBHitPct 98.465360 # BTB Hit Percentage
1658system.cpu2.branchPred.usedRAS 684 # Number of times the RAS was used to get a target.
1659system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
1660system.cpu2.numCycles 177568 # number of cpu cycles simulated
1661system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
1662system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
1663system.cpu2.fetch.icacheStallCycles 28807 # Number of cycles fetch is stalled on an Icache miss
1664system.cpu2.fetch.Insts 286591 # Number of instructions fetch has processed
1665system.cpu2.fetch.Branches 51290 # Number of branches that fetch encountered
1666system.cpu2.fetch.predictedBranches 45084 # Number of branches that fetch has predicted taken
1667system.cpu2.fetch.Cycles 100996 # Number of cycles fetch has run and was not squashing or blocked
1668system.cpu2.fetch.SquashCycles 3797 # Number of cycles fetch has spent squashing
1669system.cpu2.fetch.BlockedCycles 31176 # Number of cycles fetch has spent blocked
1670system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1671system.cpu2.fetch.NoActiveThreadStallCycles 7777 # Number of stall cycles due to no active thread to fetch from
1672system.cpu2.fetch.PendingTrapStallCycles 828 # Number of stall cycles due to pending traps
1673system.cpu2.fetch.CacheLines 19752 # Number of cache lines fetched
1674system.cpu2.fetch.IcacheSquashes 272 # Number of outstanding Icache misses that were squashed
1675system.cpu2.fetch.rateDist::samples 172005 # Number of instructions fetched each cycle (Total)
1676system.cpu2.fetch.rateDist::mean 1.666178 # Number of instructions fetched each cycle (Total)
1677system.cpu2.fetch.rateDist::stdev 2.140016 # Number of instructions fetched each cycle (Total)
1678system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1679system.cpu2.fetch.rateDist::0 71009 41.28% 41.28% # Number of instructions fetched each cycle (Total)
1680system.cpu2.fetch.rateDist::1 51379 29.87% 71.15% # Number of instructions fetched each cycle (Total)
1681system.cpu2.fetch.rateDist::2 6118 3.56% 74.71% # Number of instructions fetched each cycle (Total)
1682system.cpu2.fetch.rateDist::3 3176 1.85% 76.56% # Number of instructions fetched each cycle (Total)
1683system.cpu2.fetch.rateDist::4 688 0.40% 76.96% # Number of instructions fetched each cycle (Total)
1684system.cpu2.fetch.rateDist::5 34434 20.02% 96.98% # Number of instructions fetched each cycle (Total)
1685system.cpu2.fetch.rateDist::6 1153 0.67% 97.65% # Number of instructions fetched each cycle (Total)
1686system.cpu2.fetch.rateDist::7 776 0.45% 98.10% # Number of instructions fetched each cycle (Total)
1687system.cpu2.fetch.rateDist::8 3272 1.90% 100.00% # Number of instructions fetched each cycle (Total)
1688system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1689system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1690system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
1691system.cpu2.fetch.rateDist::total 172005 # Number of instructions fetched each cycle (Total)
1692system.cpu2.fetch.branchRate 0.288847 # Number of branch fetches per cycle
1693system.cpu2.fetch.rate 1.613979 # Number of inst fetches per cycle
1694system.cpu2.decode.IdleCycles 33784 # Number of cycles decode is idle
1695system.cpu2.decode.BlockedCycles 27885 # Number of cycles decode is blocked
1696system.cpu2.decode.RunCycles 95101 # Number of cycles decode is running
1697system.cpu2.decode.UnblockCycles 5041 # Number of cycles decode is unblocking
1698system.cpu2.decode.SquashCycles 2417 # Number of cycles decode is squashing
1699system.cpu2.decode.DecodedInsts 283083 # Number of instructions handled by decode
1700system.cpu2.rename.SquashCycles 2417 # Number of cycles rename is squashing
1701system.cpu2.rename.IdleCycles 34494 # Number of cycles rename is idle
1702system.cpu2.rename.BlockCycles 14868 # Number of cycles rename is blocking
1703system.cpu2.rename.serializeStallCycles 12251 # count of cycles rename stalled for serializing inst
1704system.cpu2.rename.RunCycles 90316 # Number of cycles rename is running
1705system.cpu2.rename.UnblockCycles 9882 # Number of cycles rename is unblocking
1706system.cpu2.rename.RenamedInsts 280840 # Number of instructions processed by rename
1707system.cpu2.rename.LSQFullEvents 23 # Number of times rename has blocked due to LSQ full
1708system.cpu2.rename.RenamedOperands 196811 # Number of destination operands rename has renamed
1709system.cpu2.rename.RenameLookups 538434 # Number of register rename lookups that rename has made
1710system.cpu2.rename.int_rename_lookups 418653 # Number of integer rename lookups
1711system.cpu2.rename.CommittedMaps 183802 # Number of HB maps that are committed
1712system.cpu2.rename.UndoneMaps 13009 # Number of HB maps that are undone due to squashing
1713system.cpu2.rename.serializingInsts 1113 # count of serializing insts renamed
1714system.cpu2.rename.tempSerializingInsts 1241 # count of temporary serializing insts renamed
1715system.cpu2.rename.skidInsts 12535 # count of insts added to the skid buffer
1716system.cpu2.memDep0.insertedLoads 79329 # Number of loads inserted to the mem dependence unit.
1717system.cpu2.memDep0.insertedStores 37643 # Number of stores inserted to the mem dependence unit.
1718system.cpu2.memDep0.conflictingLoads 37867 # Number of conflicting loads.
1719system.cpu2.memDep0.conflictingStores 32593 # Number of conflicting stores.
1720system.cpu2.iq.iqInstsAdded 232899 # Number of instructions added to the IQ (excludes non-spec)
1721system.cpu2.iq.iqNonSpecInstsAdded 6340 # Number of non-speculative instructions added to the IQ
1722system.cpu2.iq.iqInstsIssued 234909 # Number of instructions issued
1723system.cpu2.iq.iqSquashedInstsIssued 92 # Number of squashed instructions issued
1724system.cpu2.iq.iqSquashedInstsExamined 11011 # Number of squashed instructions iterated over during squash; mainly for profiling
1725system.cpu2.iq.iqSquashedOperandsExamined 10823 # Number of squashed operands that are examined and possibly removed from graph
1726system.cpu2.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed
1727system.cpu2.iq.issued_per_cycle::samples 172005 # Number of insts issued each cycle
1728system.cpu2.iq.issued_per_cycle::mean 1.365710 # Number of insts issued each cycle
1729system.cpu2.iq.issued_per_cycle::stdev 1.313889 # Number of insts issued each cycle
1730system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1731system.cpu2.iq.issued_per_cycle::0 68443 39.79% 39.79% # Number of insts issued each cycle
1732system.cpu2.iq.issued_per_cycle::1 22432 13.04% 52.83% # Number of insts issued each cycle
1733system.cpu2.iq.issued_per_cycle::2 37853 22.01% 74.84% # Number of insts issued each cycle
1734system.cpu2.iq.issued_per_cycle::3 38461 22.36% 97.20% # Number of insts issued each cycle
1735system.cpu2.iq.issued_per_cycle::4 3256 1.89% 99.09% # Number of insts issued each cycle
1736system.cpu2.iq.issued_per_cycle::5 1167 0.68% 99.77% # Number of insts issued each cycle
1737system.cpu2.iq.issued_per_cycle::6 279 0.16% 99.93% # Number of insts issued each cycle
1738system.cpu2.iq.issued_per_cycle::7 57 0.03% 99.97% # Number of insts issued each cycle
1739system.cpu2.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle
1740system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1741system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1742system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
1743system.cpu2.iq.issued_per_cycle::total 172005 # Number of insts issued each cycle
1744system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1745system.cpu2.iq.fu_full::IntAlu 17 6.01% 6.01% # attempts to use FU when none available
1746system.cpu2.iq.fu_full::IntMult 0 0.00% 6.01% # attempts to use FU when none available
1747system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.01% # attempts to use FU when none available
1748system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.01% # attempts to use FU when none available
1749system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.01% # attempts to use FU when none available
1750system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.01% # attempts to use FU when none available
1751system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.01% # attempts to use FU when none available
1752system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.01% # attempts to use FU when none available
1753system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.01% # attempts to use FU when none available
1754system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.01% # attempts to use FU when none available
1755system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.01% # attempts to use FU when none available
1756system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.01% # attempts to use FU when none available
1757system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.01% # attempts to use FU when none available
1758system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.01% # attempts to use FU when none available
1759system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.01% # attempts to use FU when none available
1760system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.01% # attempts to use FU when none available
1761system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.01% # attempts to use FU when none available
1762system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.01% # attempts to use FU when none available
1763system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.01% # attempts to use FU when none available
1764system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.01% # attempts to use FU when none available
1765system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.01% # attempts to use FU when none available
1766system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.01% # attempts to use FU when none available
1767system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.01% # attempts to use FU when none available
1768system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.01% # attempts to use FU when none available
1769system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.01% # attempts to use FU when none available
1770system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.01% # attempts to use FU when none available
1771system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.01% # attempts to use FU when none available
1772system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.01% # attempts to use FU when none available
1773system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.01% # attempts to use FU when none available
1774system.cpu2.iq.fu_full::MemRead 56 19.79% 25.80% # attempts to use FU when none available
1775system.cpu2.iq.fu_full::MemWrite 210 74.20% 100.00% # attempts to use FU when none available
1776system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1777system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1778system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
1779system.cpu2.iq.FU_type_0::IntAlu 114350 48.68% 48.68% # Type of FU issued
1780system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.68% # Type of FU issued
1781system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.68% # Type of FU issued
1782system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.68% # Type of FU issued
1783system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.68% # Type of FU issued
1784system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.68% # Type of FU issued
1785system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.68% # Type of FU issued
1786system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.68% # Type of FU issued
1787system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.68% # Type of FU issued
1788system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.68% # Type of FU issued
1789system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.68% # Type of FU issued
1790system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.68% # Type of FU issued
1791system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.68% # Type of FU issued
1792system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.68% # Type of FU issued
1793system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.68% # Type of FU issued
1794system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.68% # Type of FU issued
1795system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.68% # Type of FU issued
1796system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.68% # Type of FU issued
1797system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.68% # Type of FU issued
1798system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.68% # Type of FU issued
1799system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.68% # Type of FU issued
1800system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.68% # Type of FU issued
1801system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.68% # Type of FU issued
1802system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.68% # Type of FU issued
1803system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.68% # Type of FU issued
1804system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.68% # Type of FU issued
1805system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.68% # Type of FU issued
1806system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.68% # Type of FU issued
1807system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.68% # Type of FU issued
1808system.cpu2.iq.FU_type_0::MemRead 83601 35.59% 84.27% # Type of FU issued
1809system.cpu2.iq.FU_type_0::MemWrite 36958 15.73% 100.00% # Type of FU issued
1810system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1811system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1812system.cpu2.iq.FU_type_0::total 234909 # Type of FU issued
1813system.cpu2.iq.rate 1.322924 # Inst issue rate
1814system.cpu2.iq.fu_busy_cnt 283 # FU busy when requested
1815system.cpu2.iq.fu_busy_rate 0.001205 # FU busy rate (busy events/executed inst)
1816system.cpu2.iq.int_inst_queue_reads 642198 # Number of integer instruction queue reads
1817system.cpu2.iq.int_inst_queue_writes 250297 # Number of integer instruction queue writes
1818system.cpu2.iq.int_inst_queue_wakeup_accesses 233108 # Number of integer instruction queue wakeup accesses
1819system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
1820system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
1821system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
1822system.cpu2.iq.int_alu_accesses 235192 # Number of integer alu accesses
1823system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
1824system.cpu2.iew.lsq.thread0.forwLoads 32324 # Number of loads that had data forwarded from stores
1825system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1826system.cpu2.iew.lsq.thread0.squashedLoads 2477 # Number of loads squashed
1827system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
1828system.cpu2.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations
1829system.cpu2.iew.lsq.thread0.squashedStores 1468 # Number of stores squashed
1830system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1831system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1832system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
1833system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
1834system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1835system.cpu2.iew.iewSquashCycles 2417 # Number of cycles IEW is squashing
1836system.cpu2.iew.iewBlockCycles 878 # Number of cycles IEW is blocking
1837system.cpu2.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking
1838system.cpu2.iew.iewDispatchedInsts 278010 # Number of instructions dispatched to IQ
1839system.cpu2.iew.iewDispSquashedInsts 351 # Number of squashed instructions skipped by dispatch
1840system.cpu2.iew.iewDispLoadInsts 79329 # Number of dispatched load instructions
1841system.cpu2.iew.iewDispStoreInsts 37643 # Number of dispatched store instructions
1842system.cpu2.iew.iewDispNonSpecInsts 1071 # Number of dispatched non-speculative instructions
1843system.cpu2.iew.iewIQFullEvents 50 # Number of times the IQ has become full, causing a stall
1844system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
1845system.cpu2.iew.memOrderViolationEvents 47 # Number of memory order violations
1846system.cpu2.iew.predictedTakenIncorrect 457 # Number of branches that were predicted taken incorrectly
1847system.cpu2.iew.predictedNotTakenIncorrect 973 # Number of branches that were predicted not taken incorrectly
1848system.cpu2.iew.branchMispredicts 1430 # Number of branch mispredicts detected at execute
1849system.cpu2.iew.iewExecutedInsts 233765 # Number of executed instructions
1850system.cpu2.iew.iewExecLoadInsts 78300 # Number of load instructions executed
1851system.cpu2.iew.iewExecSquashedInsts 1144 # Number of squashed instructions skipped in execute
1852system.cpu2.iew.exec_swp 0 # number of swp insts executed
1853system.cpu2.iew.exec_nop 38771 # number of nop insts executed
1854system.cpu2.iew.exec_refs 115173 # number of memory reference insts executed
1855system.cpu2.iew.exec_branches 48001 # Number of branches executed
1856system.cpu2.iew.exec_stores 36873 # Number of stores executed
1857system.cpu2.iew.exec_rate 1.316482 # Inst execution rate
1858system.cpu2.iew.wb_sent 233421 # cumulative count of insts sent to commit
1859system.cpu2.iew.wb_count 233108 # cumulative count of insts written-back
1860system.cpu2.iew.wb_producers 131942 # num instructions producing a value
1861system.cpu2.iew.wb_consumers 136650 # num instructions consuming a value
1862system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1863system.cpu2.iew.wb_rate 1.312782 # insts written-back per cycle
1864system.cpu2.iew.wb_fanout 0.965547 # average fanout of values written-back
1865system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1866system.cpu2.commit.commitSquashedInsts 12656 # The number of squashed insts skipped by commit
1867system.cpu2.commit.commitNonSpecStalls 5738 # The number of times commit has been forced to stall to communicate backwards
1868system.cpu2.commit.branchMispredicts 1303 # The number of times a branch was mispredicted
1869system.cpu2.commit.committed_per_cycle::samples 161811 # Number of insts commited each cycle
1870system.cpu2.commit.committed_per_cycle::mean 1.639889 # Number of insts commited each cycle
1871system.cpu2.commit.committed_per_cycle::stdev 2.021157 # Number of insts commited each cycle
1872system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1873system.cpu2.commit.committed_per_cycle::0 66196 40.91% 40.91% # Number of insts commited each cycle
1874system.cpu2.commit.committed_per_cycle::1 46128 28.51% 69.42% # Number of insts commited each cycle
1875system.cpu2.commit.committed_per_cycle::2 6098 3.77% 73.19% # Number of insts commited each cycle
1876system.cpu2.commit.committed_per_cycle::3 6657 4.11% 77.30% # Number of insts commited each cycle
1877system.cpu2.commit.committed_per_cycle::4 1558 0.96% 78.26% # Number of insts commited each cycle
1878system.cpu2.commit.committed_per_cycle::5 32865 20.31% 98.57% # Number of insts commited each cycle
1879system.cpu2.commit.committed_per_cycle::6 486 0.30% 98.87% # Number of insts commited each cycle
1880system.cpu2.commit.committed_per_cycle::7 1000 0.62% 99.49% # Number of insts commited each cycle
1881system.cpu2.commit.committed_per_cycle::8 823 0.51% 100.00% # Number of insts commited each cycle
1882system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1883system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1884system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1885system.cpu2.commit.committed_per_cycle::total 161811 # Number of insts commited each cycle
1886system.cpu2.commit.committedInsts 265352 # Number of instructions committed
1887system.cpu2.commit.committedOps 265352 # Number of ops (including micro ops) committed
1888system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
1889system.cpu2.commit.refs 113027 # Number of memory references committed
1890system.cpu2.commit.loads 76852 # Number of loads committed
1891system.cpu2.commit.membars 5022 # Number of memory barriers committed
1892system.cpu2.commit.branches 47160 # Number of branches committed
1893system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
1894system.cpu2.commit.int_insts 182307 # Number of committed integer instructions.
1895system.cpu2.commit.function_calls 322 # Number of function calls committed.
1896system.cpu2.commit.bw_lim_events 823 # number cycles where commit BW limit reached
1897system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
1898system.cpu2.rob.rob_reads 438409 # The number of ROB reads
1899system.cpu2.rob.rob_writes 558438 # The number of ROB writes
1900system.cpu2.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself
1901system.cpu2.idleCycles 5563 # Total number of cycles that the CPU has spent unscheduled due to idling
1902system.cpu2.quiesceCycles 44482 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1903system.cpu2.committedInsts 222382 # Number of Instructions Simulated
1904system.cpu2.committedOps 222382 # Number of Ops (including micro ops) Simulated
1905system.cpu2.committedInsts_total 222382 # Number of Instructions Simulated
1906system.cpu2.cpi 0.798482 # CPI: Cycles Per Instruction
1907system.cpu2.cpi_total 0.798482 # CPI: Total CPI of All Threads
1908system.cpu2.ipc 1.252377 # IPC: Instructions Per Cycle
1909system.cpu2.ipc_total 1.252377 # IPC: Total IPC of All Threads
1910system.cpu2.int_regfile_reads 404230 # number of integer regfile reads
1911system.cpu2.int_regfile_writes 188808 # number of integer regfile writes
1912system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
1913system.cpu2.misc_regfile_reads 116736 # number of misc regfile reads
1914system.cpu2.misc_regfile_writes 648 # number of misc regfile writes
1915system.cpu2.icache.tags.replacements 317 # number of replacements
1916system.cpu2.icache.tags.tagsinuse 82.236622 # Cycle average of tags in use
1917system.cpu2.icache.tags.total_refs 19259 # Total number of references to valid blocks.
1918system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks.
1919system.cpu2.icache.tags.avg_refs 45.315294 # Average number of references to valid blocks.
1920system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1921system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.236622 # Average occupied blocks per requestor
1922system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160618 # Average percentage of cache occupancy
1923system.cpu2.icache.tags.occ_percent::total 0.160618 # Average percentage of cache occupancy
1924system.cpu2.icache.ReadReq_hits::cpu2.inst 19259 # number of ReadReq hits
1925system.cpu2.icache.ReadReq_hits::total 19259 # number of ReadReq hits
1926system.cpu2.icache.demand_hits::cpu2.inst 19259 # number of demand (read+write) hits
1927system.cpu2.icache.demand_hits::total 19259 # number of demand (read+write) hits
1928system.cpu2.icache.overall_hits::cpu2.inst 19259 # number of overall hits
1929system.cpu2.icache.overall_hits::total 19259 # number of overall hits
1930system.cpu2.icache.ReadReq_misses::cpu2.inst 493 # number of ReadReq misses
1931system.cpu2.icache.ReadReq_misses::total 493 # number of ReadReq misses
1932system.cpu2.icache.demand_misses::cpu2.inst 493 # number of demand (read+write) misses
1933system.cpu2.icache.demand_misses::total 493 # number of demand (read+write) misses
1934system.cpu2.icache.overall_misses::cpu2.inst 493 # number of overall misses
1935system.cpu2.icache.overall_misses::total 493 # number of overall misses
1936system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11620241 # number of ReadReq miss cycles
1937system.cpu2.icache.ReadReq_miss_latency::total 11620241 # number of ReadReq miss cycles
1938system.cpu2.icache.demand_miss_latency::cpu2.inst 11620241 # number of demand (read+write) miss cycles
1939system.cpu2.icache.demand_miss_latency::total 11620241 # number of demand (read+write) miss cycles
1940system.cpu2.icache.overall_miss_latency::cpu2.inst 11620241 # number of overall miss cycles
1941system.cpu2.icache.overall_miss_latency::total 11620241 # number of overall miss cycles
1942system.cpu2.icache.ReadReq_accesses::cpu2.inst 19752 # number of ReadReq accesses(hits+misses)
1943system.cpu2.icache.ReadReq_accesses::total 19752 # number of ReadReq accesses(hits+misses)
1944system.cpu2.icache.demand_accesses::cpu2.inst 19752 # number of demand (read+write) accesses
1945system.cpu2.icache.demand_accesses::total 19752 # number of demand (read+write) accesses
1946system.cpu2.icache.overall_accesses::cpu2.inst 19752 # number of overall (read+write) accesses
1947system.cpu2.icache.overall_accesses::total 19752 # number of overall (read+write) accesses
1948system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024959 # miss rate for ReadReq accesses
1949system.cpu2.icache.ReadReq_miss_rate::total 0.024959 # miss rate for ReadReq accesses
1950system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024959 # miss rate for demand accesses
1951system.cpu2.icache.demand_miss_rate::total 0.024959 # miss rate for demand accesses
1952system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024959 # miss rate for overall accesses
1953system.cpu2.icache.overall_miss_rate::total 0.024959 # miss rate for overall accesses
1954system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23570.468560 # average ReadReq miss latency
1955system.cpu2.icache.ReadReq_avg_miss_latency::total 23570.468560 # average ReadReq miss latency
1956system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23570.468560 # average overall miss latency
1957system.cpu2.icache.demand_avg_miss_latency::total 23570.468560 # average overall miss latency
1958system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23570.468560 # average overall miss latency
1959system.cpu2.icache.overall_avg_miss_latency::total 23570.468560 # average overall miss latency
1960system.cpu2.icache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked
1961system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1962system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked
1963system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
1964system.cpu2.icache.avg_blocked_cycles::no_mshrs 85 # average number of cycles each access was blocked
1965system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1966system.cpu2.icache.fast_writes 0 # number of fast writes performed
1967system.cpu2.icache.cache_copies 0 # number of cache copies performed

--- 4 unchanged lines hidden (view full) ---

1972system.cpu2.icache.overall_mshr_hits::cpu2.inst 68 # number of overall MSHR hits
1973system.cpu2.icache.overall_mshr_hits::total 68 # number of overall MSHR hits
1974system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 425 # number of ReadReq MSHR misses
1975system.cpu2.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses
1976system.cpu2.icache.demand_mshr_misses::cpu2.inst 425 # number of demand (read+write) MSHR misses
1977system.cpu2.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses
1978system.cpu2.icache.overall_mshr_misses::cpu2.inst 425 # number of overall MSHR misses
1979system.cpu2.icache.overall_mshr_misses::total 425 # number of overall MSHR misses
1980system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9299505 # number of ReadReq MSHR miss cycles
1981system.cpu2.icache.ReadReq_mshr_miss_latency::total 9299505 # number of ReadReq MSHR miss cycles
1982system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9299505 # number of demand (read+write) MSHR miss cycles
1983system.cpu2.icache.demand_mshr_miss_latency::total 9299505 # number of demand (read+write) MSHR miss cycles
1984system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9299505 # number of overall MSHR miss cycles
1985system.cpu2.icache.overall_mshr_miss_latency::total 9299505 # number of overall MSHR miss cycles
1986system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021517 # mshr miss rate for ReadReq accesses
1987system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021517 # mshr miss rate for ReadReq accesses
1988system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021517 # mshr miss rate for demand accesses
1989system.cpu2.icache.demand_mshr_miss_rate::total 0.021517 # mshr miss rate for demand accesses
1990system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021517 # mshr miss rate for overall accesses
1991system.cpu2.icache.overall_mshr_miss_rate::total 0.021517 # mshr miss rate for overall accesses
1992system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21881.188235 # average ReadReq mshr miss latency
1993system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21881.188235 # average ReadReq mshr miss latency
1994system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21881.188235 # average overall mshr miss latency
1995system.cpu2.icache.demand_avg_mshr_miss_latency::total 21881.188235 # average overall mshr miss latency
1996system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21881.188235 # average overall mshr miss latency
1997system.cpu2.icache.overall_avg_mshr_miss_latency::total 21881.188235 # average overall mshr miss latency
1998system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1999system.cpu2.dcache.tags.replacements 0 # number of replacements
2000system.cpu2.dcache.tags.tagsinuse 26.142582 # Cycle average of tags in use
2001system.cpu2.dcache.tags.total_refs 42207 # Total number of references to valid blocks.
2002system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
2003system.cpu2.dcache.tags.avg_refs 1507.392857 # Average number of references to valid blocks.
2004system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2005system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.142582 # Average occupied blocks per requestor
2006system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051060 # Average percentage of cache occupancy
2007system.cpu2.dcache.tags.occ_percent::total 0.051060 # Average percentage of cache occupancy
2008system.cpu2.dcache.ReadReq_hits::cpu2.data 45613 # number of ReadReq hits
2009system.cpu2.dcache.ReadReq_hits::total 45613 # number of ReadReq hits
2010system.cpu2.dcache.WriteReq_hits::cpu2.data 35966 # number of WriteReq hits
2011system.cpu2.dcache.WriteReq_hits::total 35966 # number of WriteReq hits
2012system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits
2013system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits
2014system.cpu2.dcache.demand_hits::cpu2.data 81579 # number of demand (read+write) hits
2015system.cpu2.dcache.demand_hits::total 81579 # number of demand (read+write) hits
2016system.cpu2.dcache.overall_hits::cpu2.data 81579 # number of overall hits
2017system.cpu2.dcache.overall_hits::total 81579 # number of overall hits
2018system.cpu2.dcache.ReadReq_misses::cpu2.data 346 # number of ReadReq misses
2019system.cpu2.dcache.ReadReq_misses::total 346 # number of ReadReq misses
2020system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses
2021system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses
2022system.cpu2.dcache.SwapReq_misses::cpu2.data 57 # number of SwapReq misses
2023system.cpu2.dcache.SwapReq_misses::total 57 # number of SwapReq misses
2024system.cpu2.dcache.demand_misses::cpu2.data 485 # number of demand (read+write) misses
2025system.cpu2.dcache.demand_misses::total 485 # number of demand (read+write) misses
2026system.cpu2.dcache.overall_misses::cpu2.data 485 # number of overall misses
2027system.cpu2.dcache.overall_misses::total 485 # number of overall misses
2028system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5531640 # number of ReadReq miss cycles
2029system.cpu2.dcache.ReadReq_miss_latency::total 5531640 # number of ReadReq miss cycles
2030system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3131011 # number of WriteReq miss cycles
2031system.cpu2.dcache.WriteReq_miss_latency::total 3131011 # number of WriteReq miss cycles
2032system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 555006 # number of SwapReq miss cycles
2033system.cpu2.dcache.SwapReq_miss_latency::total 555006 # number of SwapReq miss cycles
2034system.cpu2.dcache.demand_miss_latency::cpu2.data 8662651 # number of demand (read+write) miss cycles
2035system.cpu2.dcache.demand_miss_latency::total 8662651 # number of demand (read+write) miss cycles
2036system.cpu2.dcache.overall_miss_latency::cpu2.data 8662651 # number of overall miss cycles
2037system.cpu2.dcache.overall_miss_latency::total 8662651 # number of overall miss cycles
2038system.cpu2.dcache.ReadReq_accesses::cpu2.data 45959 # number of ReadReq accesses(hits+misses)
2039system.cpu2.dcache.ReadReq_accesses::total 45959 # number of ReadReq accesses(hits+misses)
2040system.cpu2.dcache.WriteReq_accesses::cpu2.data 36105 # number of WriteReq accesses(hits+misses)
2041system.cpu2.dcache.WriteReq_accesses::total 36105 # number of WriteReq accesses(hits+misses)
2042system.cpu2.dcache.SwapReq_accesses::cpu2.data 70 # number of SwapReq accesses(hits+misses)
2043system.cpu2.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses)
2044system.cpu2.dcache.demand_accesses::cpu2.data 82064 # number of demand (read+write) accesses
2045system.cpu2.dcache.demand_accesses::total 82064 # number of demand (read+write) accesses
2046system.cpu2.dcache.overall_accesses::cpu2.data 82064 # number of overall (read+write) accesses
2047system.cpu2.dcache.overall_accesses::total 82064 # number of overall (read+write) accesses
2048system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.007528 # miss rate for ReadReq accesses
2049system.cpu2.dcache.ReadReq_miss_rate::total 0.007528 # miss rate for ReadReq accesses
2050system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003850 # miss rate for WriteReq accesses
2051system.cpu2.dcache.WriteReq_miss_rate::total 0.003850 # miss rate for WriteReq accesses
2052system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.814286 # miss rate for SwapReq accesses
2053system.cpu2.dcache.SwapReq_miss_rate::total 0.814286 # miss rate for SwapReq accesses
2054system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005910 # miss rate for demand accesses
2055system.cpu2.dcache.demand_miss_rate::total 0.005910 # miss rate for demand accesses
2056system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005910 # miss rate for overall accesses
2057system.cpu2.dcache.overall_miss_rate::total 0.005910 # miss rate for overall accesses
2058system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15987.398844 # average ReadReq miss latency
2059system.cpu2.dcache.ReadReq_avg_miss_latency::total 15987.398844 # average ReadReq miss latency
2060system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22525.258993 # average WriteReq miss latency
2061system.cpu2.dcache.WriteReq_avg_miss_latency::total 22525.258993 # average WriteReq miss latency
2062system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9736.947368 # average SwapReq miss latency
2063system.cpu2.dcache.SwapReq_avg_miss_latency::total 9736.947368 # average SwapReq miss latency
2064system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17861.136082 # average overall miss latency
2065system.cpu2.dcache.demand_avg_miss_latency::total 17861.136082 # average overall miss latency
2066system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17861.136082 # average overall miss latency
2067system.cpu2.dcache.overall_avg_miss_latency::total 17861.136082 # average overall miss latency
2068system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2069system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2070system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
2071system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
2072system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2073system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2074system.cpu2.dcache.fast_writes 0 # number of fast writes performed
2075system.cpu2.dcache.cache_copies 0 # number of cache copies performed
2076system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 184 # number of ReadReq MSHR hits
2077system.cpu2.dcache.ReadReq_mshr_hits::total 184 # number of ReadReq MSHR hits
2078system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 33 # number of WriteReq MSHR hits
2079system.cpu2.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits
2080system.cpu2.dcache.demand_mshr_hits::cpu2.data 217 # number of demand (read+write) MSHR hits
2081system.cpu2.dcache.demand_mshr_hits::total 217 # number of demand (read+write) MSHR hits
2082system.cpu2.dcache.overall_mshr_hits::cpu2.data 217 # number of overall MSHR hits
2083system.cpu2.dcache.overall_mshr_hits::total 217 # number of overall MSHR hits
2084system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses
2085system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses
2086system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses
2087system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses
2088system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 57 # number of SwapReq MSHR misses
2089system.cpu2.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses
2090system.cpu2.dcache.demand_mshr_misses::cpu2.data 268 # number of demand (read+write) MSHR misses
2091system.cpu2.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses
2092system.cpu2.dcache.overall_mshr_misses::cpu2.data 268 # number of overall MSHR misses
2093system.cpu2.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses
2094system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1488769 # number of ReadReq MSHR miss cycles
2095system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1488769 # number of ReadReq MSHR miss cycles
2096system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1526989 # number of WriteReq MSHR miss cycles
2097system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1526989 # number of WriteReq MSHR miss cycles
2098system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 440994 # number of SwapReq MSHR miss cycles
2099system.cpu2.dcache.SwapReq_mshr_miss_latency::total 440994 # number of SwapReq MSHR miss cycles
2100system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3015758 # number of demand (read+write) MSHR miss cycles
2101system.cpu2.dcache.demand_mshr_miss_latency::total 3015758 # number of demand (read+write) MSHR miss cycles
2102system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3015758 # number of overall MSHR miss cycles
2103system.cpu2.dcache.overall_mshr_miss_latency::total 3015758 # number of overall MSHR miss cycles
2104system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003525 # mshr miss rate for ReadReq accesses
2105system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003525 # mshr miss rate for ReadReq accesses
2106system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002936 # mshr miss rate for WriteReq accesses
2107system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002936 # mshr miss rate for WriteReq accesses
2108system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.814286 # mshr miss rate for SwapReq accesses
2109system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.814286 # mshr miss rate for SwapReq accesses
2110system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003266 # mshr miss rate for demand accesses
2111system.cpu2.dcache.demand_mshr_miss_rate::total 0.003266 # mshr miss rate for demand accesses
2112system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003266 # mshr miss rate for overall accesses
2113system.cpu2.dcache.overall_mshr_miss_rate::total 0.003266 # mshr miss rate for overall accesses
2114system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9189.932099 # average ReadReq mshr miss latency
2115system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9189.932099 # average ReadReq mshr miss latency
2116system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14405.556604 # average WriteReq mshr miss latency
2117system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14405.556604 # average WriteReq mshr miss latency
2118system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7736.736842 # average SwapReq mshr miss latency
2119system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7736.736842 # average SwapReq mshr miss latency
2120system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11252.828358 # average overall mshr miss latency
2121system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11252.828358 # average overall mshr miss latency
2122system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11252.828358 # average overall mshr miss latency
2123system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11252.828358 # average overall mshr miss latency
2124system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2125system.cpu3.branchPred.lookups 52302 # Number of BP lookups
2126system.cpu3.branchPred.condPredicted 49590 # Number of conditional branches predicted
2127system.cpu3.branchPred.condIncorrect 1266 # Number of conditional branches incorrect
2128system.cpu3.branchPred.BTBLookups 46219 # Number of BTB lookups
2129system.cpu3.branchPred.BTBHits 45467 # Number of BTB hits
2130system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2131system.cpu3.branchPred.BTBHitPct 98.372963 # BTB Hit Percentage
2132system.cpu3.branchPred.usedRAS 659 # Number of times the RAS was used to get a target.
2133system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
2134system.cpu3.numCycles 177222 # number of cpu cycles simulated
2135system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
2136system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
2137system.cpu3.fetch.icacheStallCycles 28850 # Number of cycles fetch is stalled on an Icache miss
2138system.cpu3.fetch.Insts 291591 # Number of instructions fetch has processed
2139system.cpu3.fetch.Branches 52302 # Number of branches that fetch encountered
2140system.cpu3.fetch.predictedBranches 46126 # Number of branches that fetch has predicted taken
2141system.cpu3.fetch.Cycles 103443 # Number of cycles fetch has run and was not squashing or blocked
2142system.cpu3.fetch.SquashCycles 3689 # Number of cycles fetch has spent squashing
2143system.cpu3.fetch.BlockedCycles 32602 # Number of cycles fetch has spent blocked
2144system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
2145system.cpu3.fetch.NoActiveThreadStallCycles 7775 # Number of stall cycles due to no active thread to fetch from
2146system.cpu3.fetch.PendingTrapStallCycles 799 # Number of stall cycles due to pending traps
2147system.cpu3.fetch.CacheLines 20565 # Number of cache lines fetched
2148system.cpu3.fetch.IcacheSquashes 250 # Number of outstanding Icache misses that were squashed
2149system.cpu3.fetch.rateDist::samples 175820 # Number of instructions fetched each cycle (Total)
2150system.cpu3.fetch.rateDist::mean 1.658463 # Number of instructions fetched each cycle (Total)
2151system.cpu3.fetch.rateDist::stdev 2.129406 # Number of instructions fetched each cycle (Total)
2152system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2153system.cpu3.fetch.rateDist::0 72377 41.17% 41.17% # Number of instructions fetched each cycle (Total)
2154system.cpu3.fetch.rateDist::1 52818 30.04% 71.21% # Number of instructions fetched each cycle (Total)
2155system.cpu3.fetch.rateDist::2 6573 3.74% 74.94% # Number of instructions fetched each cycle (Total)
2156system.cpu3.fetch.rateDist::3 3193 1.82% 76.76% # Number of instructions fetched each cycle (Total)
2157system.cpu3.fetch.rateDist::4 659 0.37% 77.14% # Number of instructions fetched each cycle (Total)
2158system.cpu3.fetch.rateDist::5 35007 19.91% 97.05% # Number of instructions fetched each cycle (Total)
2159system.cpu3.fetch.rateDist::6 1204 0.68% 97.73% # Number of instructions fetched each cycle (Total)
2160system.cpu3.fetch.rateDist::7 759 0.43% 98.16% # Number of instructions fetched each cycle (Total)
2161system.cpu3.fetch.rateDist::8 3230 1.84% 100.00% # Number of instructions fetched each cycle (Total)
2162system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
2163system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
2164system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
2165system.cpu3.fetch.rateDist::total 175820 # Number of instructions fetched each cycle (Total)
2166system.cpu3.fetch.branchRate 0.295121 # Number of branch fetches per cycle
2167system.cpu3.fetch.rate 1.645343 # Number of inst fetches per cycle
2168system.cpu3.decode.IdleCycles 34476 # Number of cycles decode is idle
2169system.cpu3.decode.BlockedCycles 28632 # Number of cycles decode is blocked
2170system.cpu3.decode.RunCycles 97078 # Number of cycles decode is running
2171system.cpu3.decode.UnblockCycles 5513 # Number of cycles decode is unblocking
2172system.cpu3.decode.SquashCycles 2346 # Number of cycles decode is squashing
2173system.cpu3.decode.DecodedInsts 288057 # Number of instructions handled by decode
2174system.cpu3.rename.SquashCycles 2346 # Number of cycles rename is squashing
2175system.cpu3.rename.IdleCycles 35171 # Number of cycles rename is idle
2176system.cpu3.rename.BlockCycles 16067 # Number of cycles rename is blocking
2177system.cpu3.rename.serializeStallCycles 11805 # count of cycles rename stalled for serializing inst
2178system.cpu3.rename.RunCycles 91834 # Number of cycles rename is running
2179system.cpu3.rename.UnblockCycles 10822 # Number of cycles rename is unblocking
2180system.cpu3.rename.RenamedInsts 285905 # Number of instructions processed by rename
2181system.cpu3.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
2182system.cpu3.rename.LSQFullEvents 21 # Number of times rename has blocked due to LSQ full
2183system.cpu3.rename.RenamedOperands 199357 # Number of destination operands rename has renamed
2184system.cpu3.rename.RenameLookups 546724 # Number of register rename lookups that rename has made
2185system.cpu3.rename.int_rename_lookups 424837 # Number of integer rename lookups
2186system.cpu3.rename.CommittedMaps 186591 # Number of HB maps that are committed
2187system.cpu3.rename.UndoneMaps 12766 # Number of HB maps that are undone due to squashing
2188system.cpu3.rename.serializingInsts 1101 # count of serializing insts renamed
2189system.cpu3.rename.tempSerializingInsts 1226 # count of temporary serializing insts renamed
2190system.cpu3.rename.skidInsts 13474 # count of insts added to the skid buffer
2191system.cpu3.memDep0.insertedLoads 80900 # Number of loads inserted to the mem dependence unit.
2192system.cpu3.memDep0.insertedStores 38213 # Number of stores inserted to the mem dependence unit.
2193system.cpu3.memDep0.conflictingLoads 38893 # Number of conflicting loads.
2194system.cpu3.memDep0.conflictingStores 33161 # Number of conflicting stores.
2195system.cpu3.iq.iqInstsAdded 236458 # Number of instructions added to the IQ (excludes non-spec)
2196system.cpu3.iq.iqNonSpecInstsAdded 6797 # Number of non-speculative instructions added to the IQ
2197system.cpu3.iq.iqInstsIssued 239002 # Number of instructions issued
2198system.cpu3.iq.iqSquashedInstsIssued 90 # Number of squashed instructions issued
2199system.cpu3.iq.iqSquashedInstsExamined 10736 # Number of squashed instructions iterated over during squash; mainly for profiling
2200system.cpu3.iq.iqSquashedOperandsExamined 10694 # Number of squashed operands that are examined and possibly removed from graph
2201system.cpu3.iq.iqSquashedNonSpecRemoved 584 # Number of squashed non-spec instructions that were removed
2202system.cpu3.iq.issued_per_cycle::samples 175820 # Number of insts issued each cycle
2203system.cpu3.iq.issued_per_cycle::mean 1.359356 # Number of insts issued each cycle
2204system.cpu3.iq.issued_per_cycle::stdev 1.308484 # Number of insts issued each cycle
2205system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2206system.cpu3.iq.issued_per_cycle::0 69781 39.69% 39.69% # Number of insts issued each cycle
2207system.cpu3.iq.issued_per_cycle::1 23810 13.54% 53.23% # Number of insts issued each cycle
2208system.cpu3.iq.issued_per_cycle::2 38390 21.83% 75.07% # Number of insts issued each cycle
2209system.cpu3.iq.issued_per_cycle::3 39034 22.20% 97.27% # Number of insts issued each cycle
2210system.cpu3.iq.issued_per_cycle::4 3259 1.85% 99.12% # Number of insts issued each cycle
2211system.cpu3.iq.issued_per_cycle::5 1173 0.67% 99.79% # Number of insts issued each cycle
2212system.cpu3.iq.issued_per_cycle::6 261 0.15% 99.94% # Number of insts issued each cycle
2213system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle
2214system.cpu3.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle
2215system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
2216system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2217system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
2218system.cpu3.iq.issued_per_cycle::total 175820 # Number of insts issued each cycle
2219system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2220system.cpu3.iq.fu_full::IntAlu 17 6.20% 6.20% # attempts to use FU when none available
2221system.cpu3.iq.fu_full::IntMult 0 0.00% 6.20% # attempts to use FU when none available
2222system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.20% # attempts to use FU when none available
2223system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.20% # attempts to use FU when none available
2224system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.20% # attempts to use FU when none available
2225system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.20% # attempts to use FU when none available
2226system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.20% # attempts to use FU when none available
2227system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.20% # attempts to use FU when none available
2228system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.20% # attempts to use FU when none available
2229system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.20% # attempts to use FU when none available
2230system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.20% # attempts to use FU when none available
2231system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.20% # attempts to use FU when none available
2232system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.20% # attempts to use FU when none available
2233system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.20% # attempts to use FU when none available
2234system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.20% # attempts to use FU when none available
2235system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.20% # attempts to use FU when none available
2236system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.20% # attempts to use FU when none available
2237system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.20% # attempts to use FU when none available
2238system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.20% # attempts to use FU when none available
2239system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.20% # attempts to use FU when none available
2240system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.20% # attempts to use FU when none available
2241system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.20% # attempts to use FU when none available
2242system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.20% # attempts to use FU when none available
2243system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.20% # attempts to use FU when none available
2244system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.20% # attempts to use FU when none available
2245system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.20% # attempts to use FU when none available
2246system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.20% # attempts to use FU when none available
2247system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.20% # attempts to use FU when none available
2248system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.20% # attempts to use FU when none available
2249system.cpu3.iq.fu_full::MemRead 47 17.15% 23.36% # attempts to use FU when none available
2250system.cpu3.iq.fu_full::MemWrite 210 76.64% 100.00% # attempts to use FU when none available
2251system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
2252system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2253system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
2254system.cpu3.iq.FU_type_0::IntAlu 115815 48.46% 48.46% # Type of FU issued
2255system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.46% # Type of FU issued
2256system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.46% # Type of FU issued
2257system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.46% # Type of FU issued
2258system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.46% # Type of FU issued
2259system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.46% # Type of FU issued
2260system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.46% # Type of FU issued
2261system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.46% # Type of FU issued
2262system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.46% # Type of FU issued
2263system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.46% # Type of FU issued
2264system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.46% # Type of FU issued
2265system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.46% # Type of FU issued
2266system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.46% # Type of FU issued
2267system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.46% # Type of FU issued
2268system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.46% # Type of FU issued
2269system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.46% # Type of FU issued
2270system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.46% # Type of FU issued
2271system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.46% # Type of FU issued
2272system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.46% # Type of FU issued
2273system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.46% # Type of FU issued
2274system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.46% # Type of FU issued
2275system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.46% # Type of FU issued
2276system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.46% # Type of FU issued
2277system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.46% # Type of FU issued
2278system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.46% # Type of FU issued
2279system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.46% # Type of FU issued
2280system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.46% # Type of FU issued
2281system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.46% # Type of FU issued
2282system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.46% # Type of FU issued
2283system.cpu3.iq.FU_type_0::MemRead 85680 35.85% 84.31% # Type of FU issued
2284system.cpu3.iq.FU_type_0::MemWrite 37507 15.69% 100.00% # Type of FU issued
2285system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
2286system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2287system.cpu3.iq.FU_type_0::total 239002 # Type of FU issued
2288system.cpu3.iq.rate 1.348602 # Inst issue rate
2289system.cpu3.iq.fu_busy_cnt 274 # FU busy when requested
2290system.cpu3.iq.fu_busy_rate 0.001146 # FU busy rate (busy events/executed inst)
2291system.cpu3.iq.int_inst_queue_reads 654188 # Number of integer instruction queue reads
2292system.cpu3.iq.int_inst_queue_writes 254038 # Number of integer instruction queue writes
2293system.cpu3.iq.int_inst_queue_wakeup_accesses 237209 # Number of integer instruction queue wakeup accesses
2294system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
2295system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
2296system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
2297system.cpu3.iq.int_alu_accesses 239276 # Number of integer alu accesses
2298system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
2299system.cpu3.iew.lsq.thread0.forwLoads 32896 # Number of loads that had data forwarded from stores
2300system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2301system.cpu3.iew.lsq.thread0.squashedLoads 2413 # Number of loads squashed
2302system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
2303system.cpu3.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations
2304system.cpu3.iew.lsq.thread0.squashedStores 1461 # Number of stores squashed
2305system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
2306system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2307system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
2308system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
2309system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2310system.cpu3.iew.iewSquashCycles 2346 # Number of cycles IEW is squashing
2311system.cpu3.iew.iewBlockCycles 674 # Number of cycles IEW is blocking
2312system.cpu3.iew.iewUnblockCycles 43 # Number of cycles IEW is unblocking
2313system.cpu3.iew.iewDispatchedInsts 283043 # Number of instructions dispatched to IQ
2314system.cpu3.iew.iewDispSquashedInsts 388 # Number of squashed instructions skipped by dispatch
2315system.cpu3.iew.iewDispLoadInsts 80900 # Number of dispatched load instructions
2316system.cpu3.iew.iewDispStoreInsts 38213 # Number of dispatched store instructions
2317system.cpu3.iew.iewDispNonSpecInsts 1061 # Number of dispatched non-speculative instructions
2318system.cpu3.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall
2319system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
2320system.cpu3.iew.memOrderViolationEvents 47 # Number of memory order violations
2321system.cpu3.iew.predictedTakenIncorrect 456 # Number of branches that were predicted taken incorrectly
2322system.cpu3.iew.predictedNotTakenIncorrect 929 # Number of branches that were predicted not taken incorrectly
2323system.cpu3.iew.branchMispredicts 1385 # Number of branch mispredicts detected at execute
2324system.cpu3.iew.iewExecutedInsts 237848 # Number of executed instructions
2325system.cpu3.iew.iewExecLoadInsts 79902 # Number of load instructions executed
2326system.cpu3.iew.iewExecSquashedInsts 1154 # Number of squashed instructions skipped in execute
2327system.cpu3.iew.exec_swp 0 # number of swp insts executed
2328system.cpu3.iew.exec_nop 39788 # number of nop insts executed
2329system.cpu3.iew.exec_refs 117326 # number of memory reference insts executed
2330system.cpu3.iew.exec_branches 49028 # Number of branches executed
2331system.cpu3.iew.exec_stores 37424 # Number of stores executed
2332system.cpu3.iew.exec_rate 1.342091 # Inst execution rate
2333system.cpu3.iew.wb_sent 237529 # cumulative count of insts sent to commit
2334system.cpu3.iew.wb_count 237209 # cumulative count of insts written-back
2335system.cpu3.iew.wb_producers 134044 # num instructions producing a value
2336system.cpu3.iew.wb_consumers 138720 # num instructions consuming a value
2337system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
2338system.cpu3.iew.wb_rate 1.338485 # insts written-back per cycle
2339system.cpu3.iew.wb_fanout 0.966292 # average fanout of values written-back
2340system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
2341system.cpu3.commit.commitSquashedInsts 12298 # The number of squashed insts skipped by commit
2342system.cpu3.commit.commitNonSpecStalls 6213 # The number of times commit has been forced to stall to communicate backwards
2343system.cpu3.commit.branchMispredicts 1266 # The number of times a branch was mispredicted
2344system.cpu3.commit.committed_per_cycle::samples 165699 # Number of insts commited each cycle
2345system.cpu3.commit.committed_per_cycle::mean 1.633836 # Number of insts commited each cycle
2346system.cpu3.commit.committed_per_cycle::stdev 2.016583 # Number of insts commited each cycle
2347system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2348system.cpu3.commit.committed_per_cycle::0 68017 41.05% 41.05% # Number of insts commited each cycle
2349system.cpu3.commit.committed_per_cycle::1 47143 28.45% 69.50% # Number of insts commited each cycle
2350system.cpu3.commit.committed_per_cycle::2 6068 3.66% 73.16% # Number of insts commited each cycle
2351system.cpu3.commit.committed_per_cycle::3 7148 4.31% 77.48% # Number of insts commited each cycle
2352system.cpu3.commit.committed_per_cycle::4 1577 0.95% 78.43% # Number of insts commited each cycle
2353system.cpu3.commit.committed_per_cycle::5 33420 20.17% 98.60% # Number of insts commited each cycle
2354system.cpu3.commit.committed_per_cycle::6 508 0.31% 98.90% # Number of insts commited each cycle
2355system.cpu3.commit.committed_per_cycle::7 998 0.60% 99.51% # Number of insts commited each cycle
2356system.cpu3.commit.committed_per_cycle::8 820 0.49% 100.00% # Number of insts commited each cycle
2357system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
2358system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
2359system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2360system.cpu3.commit.committed_per_cycle::total 165699 # Number of insts commited each cycle
2361system.cpu3.commit.committedInsts 270725 # Number of instructions committed
2362system.cpu3.commit.committedOps 270725 # Number of ops (including micro ops) committed
2363system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
2364system.cpu3.commit.refs 115239 # Number of memory references committed
2365system.cpu3.commit.loads 78487 # Number of loads committed
2366system.cpu3.commit.membars 5499 # Number of memory barriers committed
2367system.cpu3.commit.branches 48212 # Number of branches committed
2368system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
2369system.cpu3.commit.int_insts 185574 # Number of committed integer instructions.
2370system.cpu3.commit.function_calls 322 # Number of function calls committed.
2371system.cpu3.commit.bw_lim_events 820 # number cycles where commit BW limit reached
2372system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits
2373system.cpu3.rob.rob_reads 447315 # The number of ROB reads
2374system.cpu3.rob.rob_writes 568397 # The number of ROB writes
2375system.cpu3.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself
2376system.cpu3.idleCycles 1402 # Total number of cycles that the CPU has spent unscheduled due to idling
2377system.cpu3.quiesceCycles 44828 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
2378system.cpu3.committedInsts 226224 # Number of Instructions Simulated
2379system.cpu3.committedOps 226224 # Number of Ops (including micro ops) Simulated
2380system.cpu3.committedInsts_total 226224 # Number of Instructions Simulated
2381system.cpu3.cpi 0.783392 # CPI: Cycles Per Instruction
2382system.cpu3.cpi_total 0.783392 # CPI: Total CPI of All Threads
2383system.cpu3.ipc 1.276501 # IPC: Instructions Per Cycle
2384system.cpu3.ipc_total 1.276501 # IPC: Total IPC of All Threads
2385system.cpu3.int_regfile_reads 410473 # number of integer regfile reads
2386system.cpu3.int_regfile_writes 191401 # number of integer regfile writes
2387system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
2388system.cpu3.misc_regfile_reads 118878 # number of misc regfile reads
2389system.cpu3.misc_regfile_writes 648 # number of misc regfile writes
2390system.cpu3.icache.tags.replacements 319 # number of replacements
2391system.cpu3.icache.tags.tagsinuse 79.942849 # Cycle average of tags in use
2392system.cpu3.icache.tags.total_refs 20090 # Total number of references to valid blocks.
2393system.cpu3.icache.tags.sampled_refs 429 # Sample count of references to valid blocks.
2394system.cpu3.icache.tags.avg_refs 46.829837 # Average number of references to valid blocks.
2395system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2396system.cpu3.icache.tags.occ_blocks::cpu3.inst 79.942849 # Average occupied blocks per requestor
2397system.cpu3.icache.tags.occ_percent::cpu3.inst 0.156138 # Average percentage of cache occupancy
2398system.cpu3.icache.tags.occ_percent::total 0.156138 # Average percentage of cache occupancy
2399system.cpu3.icache.ReadReq_hits::cpu3.inst 20090 # number of ReadReq hits
2400system.cpu3.icache.ReadReq_hits::total 20090 # number of ReadReq hits
2401system.cpu3.icache.demand_hits::cpu3.inst 20090 # number of demand (read+write) hits
2402system.cpu3.icache.demand_hits::total 20090 # number of demand (read+write) hits
2403system.cpu3.icache.overall_hits::cpu3.inst 20090 # number of overall hits
2404system.cpu3.icache.overall_hits::total 20090 # number of overall hits
2405system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses
2406system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses
2407system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses
2408system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses
2409system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses
2410system.cpu3.icache.overall_misses::total 475 # number of overall misses
2411system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6449245 # number of ReadReq miss cycles
2412system.cpu3.icache.ReadReq_miss_latency::total 6449245 # number of ReadReq miss cycles
2413system.cpu3.icache.demand_miss_latency::cpu3.inst 6449245 # number of demand (read+write) miss cycles
2414system.cpu3.icache.demand_miss_latency::total 6449245 # number of demand (read+write) miss cycles
2415system.cpu3.icache.overall_miss_latency::cpu3.inst 6449245 # number of overall miss cycles
2416system.cpu3.icache.overall_miss_latency::total 6449245 # number of overall miss cycles
2417system.cpu3.icache.ReadReq_accesses::cpu3.inst 20565 # number of ReadReq accesses(hits+misses)
2418system.cpu3.icache.ReadReq_accesses::total 20565 # number of ReadReq accesses(hits+misses)
2419system.cpu3.icache.demand_accesses::cpu3.inst 20565 # number of demand (read+write) accesses
2420system.cpu3.icache.demand_accesses::total 20565 # number of demand (read+write) accesses
2421system.cpu3.icache.overall_accesses::cpu3.inst 20565 # number of overall (read+write) accesses
2422system.cpu3.icache.overall_accesses::total 20565 # number of overall (read+write) accesses
2423system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023097 # miss rate for ReadReq accesses
2424system.cpu3.icache.ReadReq_miss_rate::total 0.023097 # miss rate for ReadReq accesses
2425system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023097 # miss rate for demand accesses
2426system.cpu3.icache.demand_miss_rate::total 0.023097 # miss rate for demand accesses
2427system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023097 # miss rate for overall accesses
2428system.cpu3.icache.overall_miss_rate::total 0.023097 # miss rate for overall accesses
2429system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13577.357895 # average ReadReq miss latency
2430system.cpu3.icache.ReadReq_avg_miss_latency::total 13577.357895 # average ReadReq miss latency
2431system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13577.357895 # average overall miss latency
2432system.cpu3.icache.demand_avg_miss_latency::total 13577.357895 # average overall miss latency
2433system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13577.357895 # average overall miss latency
2434system.cpu3.icache.overall_avg_miss_latency::total 13577.357895 # average overall miss latency
2435system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2436system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2437system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
2438system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
2439system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2440system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2441system.cpu3.icache.fast_writes 0 # number of fast writes performed
2442system.cpu3.icache.cache_copies 0 # number of cache copies performed
2443system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 46 # number of ReadReq MSHR hits
2444system.cpu3.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits
2445system.cpu3.icache.demand_mshr_hits::cpu3.inst 46 # number of demand (read+write) MSHR hits
2446system.cpu3.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits
2447system.cpu3.icache.overall_mshr_hits::cpu3.inst 46 # number of overall MSHR hits
2448system.cpu3.icache.overall_mshr_hits::total 46 # number of overall MSHR hits
2449system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 429 # number of ReadReq MSHR misses
2450system.cpu3.icache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses
2451system.cpu3.icache.demand_mshr_misses::cpu3.inst 429 # number of demand (read+write) MSHR misses
2452system.cpu3.icache.demand_mshr_misses::total 429 # number of demand (read+write) MSHR misses
2453system.cpu3.icache.overall_mshr_misses::cpu3.inst 429 # number of overall MSHR misses
2454system.cpu3.icache.overall_mshr_misses::total 429 # number of overall MSHR misses
2455system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5223255 # number of ReadReq MSHR miss cycles
2456system.cpu3.icache.ReadReq_mshr_miss_latency::total 5223255 # number of ReadReq MSHR miss cycles
2457system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5223255 # number of demand (read+write) MSHR miss cycles
2458system.cpu3.icache.demand_mshr_miss_latency::total 5223255 # number of demand (read+write) MSHR miss cycles
2459system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5223255 # number of overall MSHR miss cycles
2460system.cpu3.icache.overall_mshr_miss_latency::total 5223255 # number of overall MSHR miss cycles
2461system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for ReadReq accesses
2462system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020861 # mshr miss rate for ReadReq accesses
2463system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for demand accesses
2464system.cpu3.icache.demand_mshr_miss_rate::total 0.020861 # mshr miss rate for demand accesses
2465system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for overall accesses
2466system.cpu3.icache.overall_mshr_miss_rate::total 0.020861 # mshr miss rate for overall accesses
2467system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12175.419580 # average ReadReq mshr miss latency
2468system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12175.419580 # average ReadReq mshr miss latency
2469system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12175.419580 # average overall mshr miss latency
2470system.cpu3.icache.demand_avg_mshr_miss_latency::total 12175.419580 # average overall mshr miss latency
2471system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12175.419580 # average overall mshr miss latency
2472system.cpu3.icache.overall_avg_mshr_miss_latency::total 12175.419580 # average overall mshr miss latency
2473system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2474system.cpu3.dcache.tags.replacements 0 # number of replacements
2475system.cpu3.dcache.tags.tagsinuse 24.692253 # Cycle average of tags in use
2476system.cpu3.dcache.tags.total_refs 42769 # Total number of references to valid blocks.
2477system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
2478system.cpu3.dcache.tags.avg_refs 1527.464286 # Average number of references to valid blocks.
2479system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2480system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.692253 # Average occupied blocks per requestor
2481system.cpu3.dcache.tags.occ_percent::cpu3.data 0.048227 # Average percentage of cache occupancy
2482system.cpu3.dcache.tags.occ_percent::total 0.048227 # Average percentage of cache occupancy
2483system.cpu3.dcache.ReadReq_hits::cpu3.data 46656 # number of ReadReq hits
2484system.cpu3.dcache.ReadReq_hits::total 46656 # number of ReadReq hits
2485system.cpu3.dcache.WriteReq_hits::cpu3.data 36553 # number of WriteReq hits
2486system.cpu3.dcache.WriteReq_hits::total 36553 # number of WriteReq hits
2487system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits
2488system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits
2489system.cpu3.dcache.demand_hits::cpu3.data 83209 # number of demand (read+write) hits
2490system.cpu3.dcache.demand_hits::total 83209 # number of demand (read+write) hits
2491system.cpu3.dcache.overall_hits::cpu3.data 83209 # number of overall hits
2492system.cpu3.dcache.overall_hits::total 83209 # number of overall hits
2493system.cpu3.dcache.ReadReq_misses::cpu3.data 333 # number of ReadReq misses
2494system.cpu3.dcache.ReadReq_misses::total 333 # number of ReadReq misses
2495system.cpu3.dcache.WriteReq_misses::cpu3.data 131 # number of WriteReq misses
2496system.cpu3.dcache.WriteReq_misses::total 131 # number of WriteReq misses
2497system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses
2498system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses
2499system.cpu3.dcache.demand_misses::cpu3.data 464 # number of demand (read+write) misses
2500system.cpu3.dcache.demand_misses::total 464 # number of demand (read+write) misses
2501system.cpu3.dcache.overall_misses::cpu3.data 464 # number of overall misses
2502system.cpu3.dcache.overall_misses::total 464 # number of overall misses
2503system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4249100 # number of ReadReq miss cycles
2504system.cpu3.dcache.ReadReq_miss_latency::total 4249100 # number of ReadReq miss cycles
2505system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3352512 # number of WriteReq miss cycles
2506system.cpu3.dcache.WriteReq_miss_latency::total 3352512 # number of WriteReq miss cycles
2507system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 492006 # number of SwapReq miss cycles
2508system.cpu3.dcache.SwapReq_miss_latency::total 492006 # number of SwapReq miss cycles
2509system.cpu3.dcache.demand_miss_latency::cpu3.data 7601612 # number of demand (read+write) miss cycles
2510system.cpu3.dcache.demand_miss_latency::total 7601612 # number of demand (read+write) miss cycles
2511system.cpu3.dcache.overall_miss_latency::cpu3.data 7601612 # number of overall miss cycles
2512system.cpu3.dcache.overall_miss_latency::total 7601612 # number of overall miss cycles
2513system.cpu3.dcache.ReadReq_accesses::cpu3.data 46989 # number of ReadReq accesses(hits+misses)
2514system.cpu3.dcache.ReadReq_accesses::total 46989 # number of ReadReq accesses(hits+misses)
2515system.cpu3.dcache.WriteReq_accesses::cpu3.data 36684 # number of WriteReq accesses(hits+misses)
2516system.cpu3.dcache.WriteReq_accesses::total 36684 # number of WriteReq accesses(hits+misses)
2517system.cpu3.dcache.SwapReq_accesses::cpu3.data 68 # number of SwapReq accesses(hits+misses)
2518system.cpu3.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses)
2519system.cpu3.dcache.demand_accesses::cpu3.data 83673 # number of demand (read+write) accesses
2520system.cpu3.dcache.demand_accesses::total 83673 # number of demand (read+write) accesses
2521system.cpu3.dcache.overall_accesses::cpu3.data 83673 # number of overall (read+write) accesses
2522system.cpu3.dcache.overall_accesses::total 83673 # number of overall (read+write) accesses
2523system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.007087 # miss rate for ReadReq accesses
2524system.cpu3.dcache.ReadReq_miss_rate::total 0.007087 # miss rate for ReadReq accesses
2525system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003571 # miss rate for WriteReq accesses
2526system.cpu3.dcache.WriteReq_miss_rate::total 0.003571 # miss rate for WriteReq accesses
2527system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.794118 # miss rate for SwapReq accesses
2528system.cpu3.dcache.SwapReq_miss_rate::total 0.794118 # miss rate for SwapReq accesses
2529system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005545 # miss rate for demand accesses
2530system.cpu3.dcache.demand_miss_rate::total 0.005545 # miss rate for demand accesses
2531system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005545 # miss rate for overall accesses
2532system.cpu3.dcache.overall_miss_rate::total 0.005545 # miss rate for overall accesses
2533system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12760.060060 # average ReadReq miss latency
2534system.cpu3.dcache.ReadReq_avg_miss_latency::total 12760.060060 # average ReadReq miss latency
2535system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25591.694656 # average WriteReq miss latency
2536system.cpu3.dcache.WriteReq_avg_miss_latency::total 25591.694656 # average WriteReq miss latency
2537system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9111.222222 # average SwapReq miss latency
2538system.cpu3.dcache.SwapReq_avg_miss_latency::total 9111.222222 # average SwapReq miss latency
2539system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16382.784483 # average overall miss latency
2540system.cpu3.dcache.demand_avg_miss_latency::total 16382.784483 # average overall miss latency
2541system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16382.784483 # average overall miss latency
2542system.cpu3.dcache.overall_avg_miss_latency::total 16382.784483 # average overall miss latency
2543system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2544system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2545system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
2546system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
2547system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2548system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2549system.cpu3.dcache.fast_writes 0 # number of fast writes performed
2550system.cpu3.dcache.cache_copies 0 # number of cache copies performed
2551system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 181 # number of ReadReq MSHR hits
2552system.cpu3.dcache.ReadReq_mshr_hits::total 181 # number of ReadReq MSHR hits
2553system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 31 # number of WriteReq MSHR hits
2554system.cpu3.dcache.WriteReq_mshr_hits::total 31 # number of WriteReq MSHR hits
2555system.cpu3.dcache.demand_mshr_hits::cpu3.data 212 # number of demand (read+write) MSHR hits
2556system.cpu3.dcache.demand_mshr_hits::total 212 # number of demand (read+write) MSHR hits
2557system.cpu3.dcache.overall_mshr_hits::cpu3.data 212 # number of overall MSHR hits
2558system.cpu3.dcache.overall_mshr_hits::total 212 # number of overall MSHR hits
2559system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 152 # number of ReadReq MSHR misses
2560system.cpu3.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses
2561system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 100 # number of WriteReq MSHR misses
2562system.cpu3.dcache.WriteReq_mshr_misses::total 100 # number of WriteReq MSHR misses
2563system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses
2564system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses
2565system.cpu3.dcache.demand_mshr_misses::cpu3.data 252 # number of demand (read+write) MSHR misses
2566system.cpu3.dcache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses
2567system.cpu3.dcache.overall_mshr_misses::cpu3.data 252 # number of overall MSHR misses
2568system.cpu3.dcache.overall_mshr_misses::total 252 # number of overall MSHR misses
2569system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1002524 # number of ReadReq MSHR miss cycles
2570system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1002524 # number of ReadReq MSHR miss cycles
2571system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1408738 # number of WriteReq MSHR miss cycles
2572system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1408738 # number of WriteReq MSHR miss cycles
2573system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 383994 # number of SwapReq MSHR miss cycles
2574system.cpu3.dcache.SwapReq_mshr_miss_latency::total 383994 # number of SwapReq MSHR miss cycles
2575system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2411262 # number of demand (read+write) MSHR miss cycles
2576system.cpu3.dcache.demand_mshr_miss_latency::total 2411262 # number of demand (read+write) MSHR miss cycles
2577system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2411262 # number of overall MSHR miss cycles
2578system.cpu3.dcache.overall_mshr_miss_latency::total 2411262 # number of overall MSHR miss cycles
2579system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003235 # mshr miss rate for ReadReq accesses
2580system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003235 # mshr miss rate for ReadReq accesses
2581system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002726 # mshr miss rate for WriteReq accesses
2582system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002726 # mshr miss rate for WriteReq accesses
2583system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.794118 # mshr miss rate for SwapReq accesses
2584system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.794118 # mshr miss rate for SwapReq accesses
2585system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003012 # mshr miss rate for demand accesses
2586system.cpu3.dcache.demand_mshr_miss_rate::total 0.003012 # mshr miss rate for demand accesses
2587system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003012 # mshr miss rate for overall accesses
2588system.cpu3.dcache.overall_mshr_miss_rate::total 0.003012 # mshr miss rate for overall accesses
2589system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6595.552632 # average ReadReq mshr miss latency
2590system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6595.552632 # average ReadReq mshr miss latency
2591system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14087.380000 # average WriteReq mshr miss latency
2592system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14087.380000 # average WriteReq mshr miss latency
2593system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7111 # average SwapReq mshr miss latency
2594system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7111 # average SwapReq mshr miss latency
2595system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9568.500000 # average overall mshr miss latency
2596system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9568.500000 # average overall mshr miss latency
2597system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9568.500000 # average overall mshr miss latency
2598system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9568.500000 # average overall mshr miss latency
2599system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2600
2601---------- End Simulation Statistics ----------