1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000111 # Number of seconds simulated
4sim_ticks 111402500 # Number of ticks simulated
5final_tick 111402500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 133234 # Simulator instruction rate (inst/s)
8host_op_rate 133234 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 13628365 # Simulator tick rate (ticks/s)
10host_mem_usage 236536 # Number of bytes of host memory used
11host_seconds 8.17 # Real time elapsed on the host
12sim_insts 1089093 # Number of instructions simulated
13sim_ops 1089093 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu0.inst 23232 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory
16system.physmem.bytes_read::cpu1.inst 896 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu2.inst 5120 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
22system.physmem.bytes_read::total 43072 # Number of bytes read from this memory
23system.physmem.bytes_inst_read::cpu0.inst 23232 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::cpu1.inst 896 # Number of instructions bytes read from this memory
25system.physmem.bytes_inst_read::cpu2.inst 5120 # Number of instructions bytes read from this memory
26system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory
27system.physmem.bytes_inst_read::total 29312 # Number of instructions bytes read from this memory
28system.physmem.num_reads::cpu0.inst 363 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu1.inst 14 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory
32system.physmem.num_reads::cpu2.inst 80 # Number of read requests responded to by this memory
33system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
36system.physmem.num_reads::total 673 # Number of read requests responded to by this memory
37system.physmem.bw_read::cpu0.inst 208541101 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu0.data 97089383 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu1.inst 8042907 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::cpu1.data 7468414 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::cpu2.inst 45959471 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_read::cpu2.data 11489868 # Total read bandwidth from this memory (bytes/s)
43system.physmem.bw_read::cpu3.inst 574493 # Total read bandwidth from this memory (bytes/s)
44system.physmem.bw_read::cpu3.data 7468414 # Total read bandwidth from this memory (bytes/s)
45system.physmem.bw_read::total 386634052 # Total read bandwidth from this memory (bytes/s)
46system.physmem.bw_inst_read::cpu0.inst 208541101 # Instruction read bandwidth from this memory (bytes/s)
47system.physmem.bw_inst_read::cpu1.inst 8042907 # Instruction read bandwidth from this memory (bytes/s)
48system.physmem.bw_inst_read::cpu2.inst 45959471 # Instruction read bandwidth from this memory (bytes/s)
49system.physmem.bw_inst_read::cpu3.inst 574493 # Instruction read bandwidth from this memory (bytes/s)
50system.physmem.bw_inst_read::total 263117973 # Instruction read bandwidth from this memory (bytes/s)
51system.physmem.bw_total::cpu0.inst 208541101 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::cpu0.data 97089383 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.bw_total::cpu1.inst 8042907 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.bw_total::cpu1.data 7468414 # Total bandwidth to/from this memory (bytes/s)
55system.physmem.bw_total::cpu2.inst 45959471 # Total bandwidth to/from this memory (bytes/s)
56system.physmem.bw_total::cpu2.data 11489868 # Total bandwidth to/from this memory (bytes/s)
57system.physmem.bw_total::cpu3.inst 574493 # Total bandwidth to/from this memory (bytes/s)
58system.physmem.bw_total::cpu3.data 7468414 # Total bandwidth to/from this memory (bytes/s)
59system.physmem.bw_total::total 386634052 # Total bandwidth to/from this memory (bytes/s)
60system.cpu0.workload.num_syscalls 89 # Number of system calls
61system.cpu0.numCycles 222806 # number of cpu cycles simulated
62system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
63system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
64system.cpu0.BPredUnit.lookups 87253 # Number of BP lookups
65system.cpu0.BPredUnit.condPredicted 84917 # Number of conditional branches predicted
66system.cpu0.BPredUnit.condIncorrect 1303 # Number of conditional branches incorrect
67system.cpu0.BPredUnit.BTBLookups 84794 # Number of BTB lookups

--- 283 unchanged lines hidden (view full) ---

351system.cpu0.icache.overall_miss_latency::total 29159500 # number of overall miss cycles
352system.cpu0.icache.ReadReq_accesses::cpu0.inst 6218 # number of ReadReq accesses(hits+misses)
353system.cpu0.icache.ReadReq_accesses::total 6218 # number of ReadReq accesses(hits+misses)
354system.cpu0.icache.demand_accesses::cpu0.inst 6218 # number of demand (read+write) accesses
355system.cpu0.icache.demand_accesses::total 6218 # number of demand (read+write) accesses
356system.cpu0.icache.overall_accesses::cpu0.inst 6218 # number of overall (read+write) accesses
357system.cpu0.icache.overall_accesses::total 6218 # number of overall (read+write) accesses
358system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.122065 # miss rate for ReadReq accesses
359system.cpu0.icache.ReadReq_miss_rate::total 0.122065 # miss rate for ReadReq accesses
360system.cpu0.icache.demand_miss_rate::cpu0.inst 0.122065 # miss rate for demand accesses
361system.cpu0.icache.demand_miss_rate::total 0.122065 # miss rate for demand accesses
362system.cpu0.icache.overall_miss_rate::cpu0.inst 0.122065 # miss rate for overall accesses
363system.cpu0.icache.overall_miss_rate::total 0.122065 # miss rate for overall accesses
364system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38418.313570 # average ReadReq miss latency
365system.cpu0.icache.ReadReq_avg_miss_latency::total 38418.313570 # average ReadReq miss latency
366system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38418.313570 # average overall miss latency
367system.cpu0.icache.demand_avg_miss_latency::total 38418.313570 # average overall miss latency
368system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38418.313570 # average overall miss latency
369system.cpu0.icache.overall_avg_miss_latency::total 38418.313570 # average overall miss latency
370system.cpu0.icache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked
371system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
372system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked
373system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
374system.cpu0.icache.avg_blocked_cycles::no_mshrs 15500 # average number of cycles each access was blocked
375system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
376system.cpu0.icache.fast_writes 0 # number of fast writes performed
377system.cpu0.icache.cache_copies 0 # number of cache copies performed

--- 11 unchanged lines hidden (view full) ---

389system.cpu0.icache.overall_mshr_misses::total 594 # number of overall MSHR misses
390system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21891000 # number of ReadReq MSHR miss cycles
391system.cpu0.icache.ReadReq_mshr_miss_latency::total 21891000 # number of ReadReq MSHR miss cycles
392system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21891000 # number of demand (read+write) MSHR miss cycles
393system.cpu0.icache.demand_mshr_miss_latency::total 21891000 # number of demand (read+write) MSHR miss cycles
394system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21891000 # number of overall MSHR miss cycles
395system.cpu0.icache.overall_mshr_miss_latency::total 21891000 # number of overall MSHR miss cycles
396system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for ReadReq accesses
397system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.095529 # mshr miss rate for ReadReq accesses
398system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for demand accesses
399system.cpu0.icache.demand_mshr_miss_rate::total 0.095529 # mshr miss rate for demand accesses
400system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for overall accesses
401system.cpu0.icache.overall_mshr_miss_rate::total 0.095529 # mshr miss rate for overall accesses
402system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average ReadReq mshr miss latency
403system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36853.535354 # average ReadReq mshr miss latency
404system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average overall mshr miss latency
405system.cpu0.icache.demand_avg_mshr_miss_latency::total 36853.535354 # average overall mshr miss latency
406system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average overall mshr miss latency
407system.cpu0.icache.overall_avg_mshr_miss_latency::total 36853.535354 # average overall mshr miss latency
408system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
409system.cpu0.dcache.replacements 8 # number of replacements
410system.cpu0.dcache.tagsinuse 141.285775 # Cycle average of tags in use
411system.cpu0.dcache.total_refs 100453 # Total number of references to valid blocks.
412system.cpu0.dcache.sampled_refs 174 # Sample count of references to valid blocks.
413system.cpu0.dcache.avg_refs 577.316092 # Average number of references to valid blocks.
414system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
415system.cpu0.dcache.occ_blocks::cpu0.data 141.285775 # Average occupied blocks per requestor

--- 35 unchanged lines hidden (view full) ---

451system.cpu0.dcache.WriteReq_accesses::total 81230 # number of WriteReq accesses(hits+misses)
452system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
453system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
454system.cpu0.dcache.demand_accesses::cpu0.data 164751 # number of demand (read+write) accesses
455system.cpu0.dcache.demand_accesses::total 164751 # number of demand (read+write) accesses
456system.cpu0.dcache.overall_accesses::cpu0.data 164751 # number of overall (read+write) accesses
457system.cpu0.dcache.overall_accesses::total 164751 # number of overall (read+write) accesses
458system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005927 # miss rate for ReadReq accesses
459system.cpu0.dcache.ReadReq_miss_rate::total 0.005927 # miss rate for ReadReq accesses
460system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006722 # miss rate for WriteReq accesses
461system.cpu0.dcache.WriteReq_miss_rate::total 0.006722 # miss rate for WriteReq accesses
462system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.476190 # miss rate for SwapReq accesses
463system.cpu0.dcache.SwapReq_miss_rate::total 0.476190 # miss rate for SwapReq accesses
464system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006319 # miss rate for demand accesses
465system.cpu0.dcache.demand_miss_rate::total 0.006319 # miss rate for demand accesses
466system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006319 # miss rate for overall accesses
467system.cpu0.dcache.overall_miss_rate::total 0.006319 # miss rate for overall accesses
468system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28234.343434 # average ReadReq miss latency
469system.cpu0.dcache.ReadReq_avg_miss_latency::total 28234.343434 # average ReadReq miss latency
470system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44619.021978 # average WriteReq miss latency
471system.cpu0.dcache.WriteReq_avg_miss_latency::total 44619.021978 # average WriteReq miss latency
472system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19025 # average SwapReq miss latency
473system.cpu0.dcache.SwapReq_avg_miss_latency::total 19025 # average SwapReq miss latency
474system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36828.036503 # average overall miss latency
475system.cpu0.dcache.demand_avg_miss_latency::total 36828.036503 # average overall miss latency
476system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36828.036503 # average overall miss latency
477system.cpu0.dcache.overall_avg_miss_latency::total 36828.036503 # average overall miss latency
478system.cpu0.dcache.blocked_cycles::no_mshrs 194000 # number of cycles access was blocked
479system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
480system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked
481system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
482system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10210.526316 # average number of cycles each access was blocked
483system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
484system.cpu0.dcache.fast_writes 0 # number of fast writes performed
485system.cpu0.dcache.cache_copies 0 # number of cache copies performed

--- 23 unchanged lines hidden (view full) ---

509system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6250000 # number of WriteReq MSHR miss cycles
510system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 320500 # number of SwapReq MSHR miss cycles
511system.cpu0.dcache.SwapReq_mshr_miss_latency::total 320500 # number of SwapReq MSHR miss cycles
512system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11204500 # number of demand (read+write) MSHR miss cycles
513system.cpu0.dcache.demand_mshr_miss_latency::total 11204500 # number of demand (read+write) MSHR miss cycles
514system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11204500 # number of overall MSHR miss cycles
515system.cpu0.dcache.overall_mshr_miss_latency::total 11204500 # number of overall MSHR miss cycles
516system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002179 # mshr miss rate for ReadReq accesses
517system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002179 # mshr miss rate for ReadReq accesses
518system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002167 # mshr miss rate for WriteReq accesses
519system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002167 # mshr miss rate for WriteReq accesses
520system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.476190 # mshr miss rate for SwapReq accesses
521system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.476190 # mshr miss rate for SwapReq accesses
522system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002173 # mshr miss rate for demand accesses
523system.cpu0.dcache.demand_mshr_miss_rate::total 0.002173 # mshr miss rate for demand accesses
524system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002173 # mshr miss rate for overall accesses
525system.cpu0.dcache.overall_mshr_miss_rate::total 0.002173 # mshr miss rate for overall accesses
526system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27222.527473 # average ReadReq mshr miss latency
527system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27222.527473 # average ReadReq mshr miss latency
528system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35511.363636 # average WriteReq mshr miss latency
529system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35511.363636 # average WriteReq mshr miss latency
530system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 16025 # average SwapReq mshr miss latency
531system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 16025 # average SwapReq mshr miss latency
532system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31297.486034 # average overall mshr miss latency
533system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31297.486034 # average overall mshr miss latency
534system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31297.486034 # average overall mshr miss latency
535system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31297.486034 # average overall mshr miss latency
536system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
537system.cpu1.numCycles 187393 # number of cpu cycles simulated
538system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
539system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
540system.cpu1.BPredUnit.lookups 57495 # Number of BP lookups
541system.cpu1.BPredUnit.condPredicted 54509 # Number of conditional branches predicted
542system.cpu1.BPredUnit.condIncorrect 1432 # Number of conditional branches incorrect
543system.cpu1.BPredUnit.BTBLookups 50945 # Number of BTB lookups

--- 285 unchanged lines hidden (view full) ---

829system.cpu1.icache.overall_miss_latency::total 7500500 # number of overall miss cycles
830system.cpu1.icache.ReadReq_accesses::cpu1.inst 19809 # number of ReadReq accesses(hits+misses)
831system.cpu1.icache.ReadReq_accesses::total 19809 # number of ReadReq accesses(hits+misses)
832system.cpu1.icache.demand_accesses::cpu1.inst 19809 # number of demand (read+write) accesses
833system.cpu1.icache.demand_accesses::total 19809 # number of demand (read+write) accesses
834system.cpu1.icache.overall_accesses::cpu1.inst 19809 # number of overall (read+write) accesses
835system.cpu1.icache.overall_accesses::total 19809 # number of overall (read+write) accesses
836system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.025493 # miss rate for ReadReq accesses
837system.cpu1.icache.ReadReq_miss_rate::total 0.025493 # miss rate for ReadReq accesses
838system.cpu1.icache.demand_miss_rate::cpu1.inst 0.025493 # miss rate for demand accesses
839system.cpu1.icache.demand_miss_rate::total 0.025493 # miss rate for demand accesses
840system.cpu1.icache.overall_miss_rate::cpu1.inst 0.025493 # miss rate for overall accesses
841system.cpu1.icache.overall_miss_rate::total 0.025493 # miss rate for overall accesses
842system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14852.475248 # average ReadReq miss latency
843system.cpu1.icache.ReadReq_avg_miss_latency::total 14852.475248 # average ReadReq miss latency
844system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14852.475248 # average overall miss latency
845system.cpu1.icache.demand_avg_miss_latency::total 14852.475248 # average overall miss latency
846system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14852.475248 # average overall miss latency
847system.cpu1.icache.overall_avg_miss_latency::total 14852.475248 # average overall miss latency
848system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
849system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
850system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
851system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
852system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
853system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
854system.cpu1.icache.fast_writes 0 # number of fast writes performed
855system.cpu1.icache.cache_copies 0 # number of cache copies performed

--- 11 unchanged lines hidden (view full) ---

867system.cpu1.icache.overall_mshr_misses::total 435 # number of overall MSHR misses
868system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5474500 # number of ReadReq MSHR miss cycles
869system.cpu1.icache.ReadReq_mshr_miss_latency::total 5474500 # number of ReadReq MSHR miss cycles
870system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5474500 # number of demand (read+write) MSHR miss cycles
871system.cpu1.icache.demand_mshr_miss_latency::total 5474500 # number of demand (read+write) MSHR miss cycles
872system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5474500 # number of overall MSHR miss cycles
873system.cpu1.icache.overall_mshr_miss_latency::total 5474500 # number of overall MSHR miss cycles
874system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for ReadReq accesses
875system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.021960 # mshr miss rate for ReadReq accesses
876system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for demand accesses
877system.cpu1.icache.demand_mshr_miss_rate::total 0.021960 # mshr miss rate for demand accesses
878system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for overall accesses
879system.cpu1.icache.overall_mshr_miss_rate::total 0.021960 # mshr miss rate for overall accesses
880system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average ReadReq mshr miss latency
881system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12585.057471 # average ReadReq mshr miss latency
882system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average overall mshr miss latency
883system.cpu1.icache.demand_avg_mshr_miss_latency::total 12585.057471 # average overall mshr miss latency
884system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average overall mshr miss latency
885system.cpu1.icache.overall_avg_mshr_miss_latency::total 12585.057471 # average overall mshr miss latency
886system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
887system.cpu1.dcache.replacements 2 # number of replacements
888system.cpu1.dcache.tagsinuse 24.070551 # Cycle average of tags in use
889system.cpu1.dcache.total_refs 48111 # Total number of references to valid blocks.
890system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks.
891system.cpu1.dcache.avg_refs 1603.700000 # Average number of references to valid blocks.
892system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
893system.cpu1.dcache.occ_blocks::cpu1.data 24.070551 # Average occupied blocks per requestor

--- 35 unchanged lines hidden (view full) ---

929system.cpu1.dcache.WriteReq_accesses::total 41743 # number of WriteReq accesses(hits+misses)
930system.cpu1.dcache.SwapReq_accesses::cpu1.data 62 # number of SwapReq accesses(hits+misses)
931system.cpu1.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses)
932system.cpu1.dcache.demand_accesses::cpu1.data 93422 # number of demand (read+write) accesses
933system.cpu1.dcache.demand_accesses::total 93422 # number of demand (read+write) accesses
934system.cpu1.dcache.overall_accesses::cpu1.data 93422 # number of overall (read+write) accesses
935system.cpu1.dcache.overall_accesses::total 93422 # number of overall (read+write) accesses
936system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009191 # miss rate for ReadReq accesses
937system.cpu1.dcache.ReadReq_miss_rate::total 0.009191 # miss rate for ReadReq accesses
938system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003689 # miss rate for WriteReq accesses
939system.cpu1.dcache.WriteReq_miss_rate::total 0.003689 # miss rate for WriteReq accesses
940system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.806452 # miss rate for SwapReq accesses
941system.cpu1.dcache.SwapReq_miss_rate::total 0.806452 # miss rate for SwapReq accesses
942system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006733 # miss rate for demand accesses
943system.cpu1.dcache.demand_miss_rate::total 0.006733 # miss rate for demand accesses
944system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006733 # miss rate for overall accesses
945system.cpu1.dcache.overall_miss_rate::total 0.006733 # miss rate for overall accesses
946system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20285.263158 # average ReadReq miss latency
947system.cpu1.dcache.ReadReq_avg_miss_latency::total 20285.263158 # average ReadReq miss latency
948system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19269.480519 # average WriteReq miss latency
949system.cpu1.dcache.WriteReq_avg_miss_latency::total 19269.480519 # average WriteReq miss latency
950system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 20770 # average SwapReq miss latency
951system.cpu1.dcache.SwapReq_avg_miss_latency::total 20770 # average SwapReq miss latency
952system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20036.565978 # average overall miss latency
953system.cpu1.dcache.demand_avg_miss_latency::total 20036.565978 # average overall miss latency
954system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20036.565978 # average overall miss latency
955system.cpu1.dcache.overall_avg_miss_latency::total 20036.565978 # average overall miss latency
956system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
957system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
958system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
959system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
960system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
961system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
962system.cpu1.dcache.fast_writes 0 # number of fast writes performed
963system.cpu1.dcache.cache_copies 0 # number of cache copies performed

--- 23 unchanged lines hidden (view full) ---

987system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1523500 # number of WriteReq MSHR miss cycles
988system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 888500 # number of SwapReq MSHR miss cycles
989system.cpu1.dcache.SwapReq_mshr_miss_latency::total 888500 # number of SwapReq MSHR miss cycles
990system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3575500 # number of demand (read+write) MSHR miss cycles
991system.cpu1.dcache.demand_mshr_miss_latency::total 3575500 # number of demand (read+write) MSHR miss cycles
992system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3575500 # number of overall MSHR miss cycles
993system.cpu1.dcache.overall_mshr_miss_latency::total 3575500 # number of overall MSHR miss cycles
994system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003019 # mshr miss rate for ReadReq accesses
995system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003019 # mshr miss rate for ReadReq accesses
996system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002611 # mshr miss rate for WriteReq accesses
997system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002611 # mshr miss rate for WriteReq accesses
998system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.806452 # mshr miss rate for SwapReq accesses
999system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.806452 # mshr miss rate for SwapReq accesses
1000system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002837 # mshr miss rate for demand accesses
1001system.cpu1.dcache.demand_mshr_miss_rate::total 0.002837 # mshr miss rate for demand accesses
1002system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002837 # mshr miss rate for overall accesses
1003system.cpu1.dcache.overall_mshr_miss_rate::total 0.002837 # mshr miss rate for overall accesses
1004system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13153.846154 # average ReadReq mshr miss latency
1005system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13153.846154 # average ReadReq mshr miss latency
1006system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13977.064220 # average WriteReq mshr miss latency
1007system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13977.064220 # average WriteReq mshr miss latency
1008system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 17770 # average SwapReq mshr miss latency
1009system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 17770 # average SwapReq mshr miss latency
1010system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13492.452830 # average overall mshr miss latency
1011system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13492.452830 # average overall mshr miss latency
1012system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13492.452830 # average overall mshr miss latency
1013system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13492.452830 # average overall mshr miss latency
1014system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1015system.cpu2.numCycles 187102 # number of cpu cycles simulated
1016system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
1017system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
1018system.cpu2.BPredUnit.lookups 52366 # Number of BP lookups
1019system.cpu2.BPredUnit.condPredicted 49346 # Number of conditional branches predicted
1020system.cpu2.BPredUnit.condIncorrect 1501 # Number of conditional branches incorrect
1021system.cpu2.BPredUnit.BTBLookups 45884 # Number of BTB lookups

--- 285 unchanged lines hidden (view full) ---

1307system.cpu2.icache.overall_miss_latency::total 11141500 # number of overall miss cycles
1308system.cpu2.icache.ReadReq_accesses::cpu2.inst 21870 # number of ReadReq accesses(hits+misses)
1309system.cpu2.icache.ReadReq_accesses::total 21870 # number of ReadReq accesses(hits+misses)
1310system.cpu2.icache.demand_accesses::cpu2.inst 21870 # number of demand (read+write) accesses
1311system.cpu2.icache.demand_accesses::total 21870 # number of demand (read+write) accesses
1312system.cpu2.icache.overall_accesses::cpu2.inst 21870 # number of overall (read+write) accesses
1313system.cpu2.icache.overall_accesses::total 21870 # number of overall (read+write) accesses
1314system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.023411 # miss rate for ReadReq accesses
1315system.cpu2.icache.ReadReq_miss_rate::total 0.023411 # miss rate for ReadReq accesses
1316system.cpu2.icache.demand_miss_rate::cpu2.inst 0.023411 # miss rate for demand accesses
1317system.cpu2.icache.demand_miss_rate::total 0.023411 # miss rate for demand accesses
1318system.cpu2.icache.overall_miss_rate::cpu2.inst 0.023411 # miss rate for overall accesses
1319system.cpu2.icache.overall_miss_rate::total 0.023411 # miss rate for overall accesses
1320system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 21760.742188 # average ReadReq miss latency
1321system.cpu2.icache.ReadReq_avg_miss_latency::total 21760.742188 # average ReadReq miss latency
1322system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 21760.742188 # average overall miss latency
1323system.cpu2.icache.demand_avg_miss_latency::total 21760.742188 # average overall miss latency
1324system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 21760.742188 # average overall miss latency
1325system.cpu2.icache.overall_avg_miss_latency::total 21760.742188 # average overall miss latency
1326system.cpu2.icache.blocked_cycles::no_mshrs 33000 # number of cycles access was blocked
1327system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1328system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked
1329system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
1330system.cpu2.icache.avg_blocked_cycles::no_mshrs 33000 # average number of cycles each access was blocked
1331system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1332system.cpu2.icache.fast_writes 0 # number of fast writes performed
1333system.cpu2.icache.cache_copies 0 # number of cache copies performed

--- 11 unchanged lines hidden (view full) ---

1345system.cpu2.icache.overall_mshr_misses::total 440 # number of overall MSHR misses
1346system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 8467000 # number of ReadReq MSHR miss cycles
1347system.cpu2.icache.ReadReq_mshr_miss_latency::total 8467000 # number of ReadReq MSHR miss cycles
1348system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 8467000 # number of demand (read+write) MSHR miss cycles
1349system.cpu2.icache.demand_mshr_miss_latency::total 8467000 # number of demand (read+write) MSHR miss cycles
1350system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 8467000 # number of overall MSHR miss cycles
1351system.cpu2.icache.overall_mshr_miss_latency::total 8467000 # number of overall MSHR miss cycles
1352system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for ReadReq accesses
1353system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.020119 # mshr miss rate for ReadReq accesses
1354system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for demand accesses
1355system.cpu2.icache.demand_mshr_miss_rate::total 0.020119 # mshr miss rate for demand accesses
1356system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for overall accesses
1357system.cpu2.icache.overall_mshr_miss_rate::total 0.020119 # mshr miss rate for overall accesses
1358system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average ReadReq mshr miss latency
1359system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 19243.181818 # average ReadReq mshr miss latency
1360system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average overall mshr miss latency
1361system.cpu2.icache.demand_avg_mshr_miss_latency::total 19243.181818 # average overall mshr miss latency
1362system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average overall mshr miss latency
1363system.cpu2.icache.overall_avg_mshr_miss_latency::total 19243.181818 # average overall mshr miss latency
1364system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1365system.cpu2.dcache.replacements 2 # number of replacements
1366system.cpu2.dcache.tagsinuse 26.720433 # Cycle average of tags in use
1367system.cpu2.dcache.total_refs 41712 # Total number of references to valid blocks.
1368system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks.
1369system.cpu2.dcache.avg_refs 1345.548387 # Average number of references to valid blocks.
1370system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1371system.cpu2.dcache.occ_blocks::cpu2.data 26.720433 # Average occupied blocks per requestor

--- 35 unchanged lines hidden (view full) ---

1407system.cpu2.dcache.WriteReq_accesses::total 35290 # number of WriteReq accesses(hits+misses)
1408system.cpu2.dcache.SwapReq_accesses::cpu2.data 76 # number of SwapReq accesses(hits+misses)
1409system.cpu2.dcache.SwapReq_accesses::total 76 # number of SwapReq accesses(hits+misses)
1410system.cpu2.dcache.demand_accesses::cpu2.data 81444 # number of demand (read+write) accesses
1411system.cpu2.dcache.demand_accesses::total 81444 # number of demand (read+write) accesses
1412system.cpu2.dcache.overall_accesses::cpu2.data 81444 # number of overall (read+write) accesses
1413system.cpu2.dcache.overall_accesses::total 81444 # number of overall (read+write) accesses
1414system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009490 # miss rate for ReadReq accesses
1415system.cpu2.dcache.ReadReq_miss_rate::total 0.009490 # miss rate for ReadReq accesses
1416system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004137 # miss rate for WriteReq accesses
1417system.cpu2.dcache.WriteReq_miss_rate::total 0.004137 # miss rate for WriteReq accesses
1418system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.815789 # miss rate for SwapReq accesses
1419system.cpu2.dcache.SwapReq_miss_rate::total 0.815789 # miss rate for SwapReq accesses
1420system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007171 # miss rate for demand accesses
1421system.cpu2.dcache.demand_miss_rate::total 0.007171 # miss rate for demand accesses
1422system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007171 # miss rate for overall accesses
1423system.cpu2.dcache.overall_miss_rate::total 0.007171 # miss rate for overall accesses
1424system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23413.242009 # average ReadReq miss latency
1425system.cpu2.dcache.ReadReq_avg_miss_latency::total 23413.242009 # average ReadReq miss latency
1426system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20116.438356 # average WriteReq miss latency
1427system.cpu2.dcache.WriteReq_avg_miss_latency::total 20116.438356 # average WriteReq miss latency
1428system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 19048.387097 # average SwapReq miss latency
1429system.cpu2.dcache.SwapReq_avg_miss_latency::total 19048.387097 # average SwapReq miss latency
1430system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22589.041096 # average overall miss latency
1431system.cpu2.dcache.demand_avg_miss_latency::total 22589.041096 # average overall miss latency
1432system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22589.041096 # average overall miss latency
1433system.cpu2.dcache.overall_avg_miss_latency::total 22589.041096 # average overall miss latency
1434system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1435system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1436system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1437system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
1438system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1439system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1440system.cpu2.dcache.fast_writes 0 # number of fast writes performed
1441system.cpu2.dcache.cache_copies 0 # number of cache copies performed

--- 23 unchanged lines hidden (view full) ---

1465system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1516500 # number of WriteReq MSHR miss cycles
1466system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 995000 # number of SwapReq MSHR miss cycles
1467system.cpu2.dcache.SwapReq_mshr_miss_latency::total 995000 # number of SwapReq MSHR miss cycles
1468system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3996500 # number of demand (read+write) MSHR miss cycles
1469system.cpu2.dcache.demand_mshr_miss_latency::total 3996500 # number of demand (read+write) MSHR miss cycles
1470system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3996500 # number of overall MSHR miss cycles
1471system.cpu2.dcache.overall_mshr_miss_latency::total 3996500 # number of overall MSHR miss cycles
1472system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003705 # mshr miss rate for ReadReq accesses
1473system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003705 # mshr miss rate for ReadReq accesses
1474system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002862 # mshr miss rate for WriteReq accesses
1475system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002862 # mshr miss rate for WriteReq accesses
1476system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.815789 # mshr miss rate for SwapReq accesses
1477system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.815789 # mshr miss rate for SwapReq accesses
1478system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003340 # mshr miss rate for demand accesses
1479system.cpu2.dcache.demand_mshr_miss_rate::total 0.003340 # mshr miss rate for demand accesses
1480system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003340 # mshr miss rate for overall accesses
1481system.cpu2.dcache.overall_mshr_miss_rate::total 0.003340 # mshr miss rate for overall accesses
1482system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14502.923977 # average ReadReq mshr miss latency
1483system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 14502.923977 # average ReadReq mshr miss latency
1484system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15014.851485 # average WriteReq mshr miss latency
1485system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15014.851485 # average WriteReq mshr miss latency
1486system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 16048.387097 # average SwapReq mshr miss latency
1487system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 16048.387097 # average SwapReq mshr miss latency
1488system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14693.014706 # average overall mshr miss latency
1489system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14693.014706 # average overall mshr miss latency
1490system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14693.014706 # average overall mshr miss latency
1491system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14693.014706 # average overall mshr miss latency
1492system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1493system.cpu3.numCycles 186832 # number of cpu cycles simulated
1494system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
1495system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
1496system.cpu3.BPredUnit.lookups 49447 # Number of BP lookups
1497system.cpu3.BPredUnit.condPredicted 46344 # Number of conditional branches predicted
1498system.cpu3.BPredUnit.condIncorrect 1525 # Number of conditional branches incorrect
1499system.cpu3.BPredUnit.BTBLookups 42752 # Number of BTB lookups

--- 285 unchanged lines hidden (view full) ---

1785system.cpu3.icache.overall_miss_latency::total 6843000 # number of overall miss cycles
1786system.cpu3.icache.ReadReq_accesses::cpu3.inst 24454 # number of ReadReq accesses(hits+misses)
1787system.cpu3.icache.ReadReq_accesses::total 24454 # number of ReadReq accesses(hits+misses)
1788system.cpu3.icache.demand_accesses::cpu3.inst 24454 # number of demand (read+write) accesses
1789system.cpu3.icache.demand_accesses::total 24454 # number of demand (read+write) accesses
1790system.cpu3.icache.overall_accesses::cpu3.inst 24454 # number of overall (read+write) accesses
1791system.cpu3.icache.overall_accesses::total 24454 # number of overall (read+write) accesses
1792system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020569 # miss rate for ReadReq accesses
1793system.cpu3.icache.ReadReq_miss_rate::total 0.020569 # miss rate for ReadReq accesses
1794system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020569 # miss rate for demand accesses
1795system.cpu3.icache.demand_miss_rate::total 0.020569 # miss rate for demand accesses
1796system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020569 # miss rate for overall accesses
1797system.cpu3.icache.overall_miss_rate::total 0.020569 # miss rate for overall accesses
1798system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13604.373757 # average ReadReq miss latency
1799system.cpu3.icache.ReadReq_avg_miss_latency::total 13604.373757 # average ReadReq miss latency
1800system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13604.373757 # average overall miss latency
1801system.cpu3.icache.demand_avg_miss_latency::total 13604.373757 # average overall miss latency
1802system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13604.373757 # average overall miss latency
1803system.cpu3.icache.overall_avg_miss_latency::total 13604.373757 # average overall miss latency
1804system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1805system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1806system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1807system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
1808system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1809system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1810system.cpu3.icache.fast_writes 0 # number of fast writes performed
1811system.cpu3.icache.cache_copies 0 # number of cache copies performed

--- 11 unchanged lines hidden (view full) ---

1823system.cpu3.icache.overall_mshr_misses::total 432 # number of overall MSHR misses
1824system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4912000 # number of ReadReq MSHR miss cycles
1825system.cpu3.icache.ReadReq_mshr_miss_latency::total 4912000 # number of ReadReq MSHR miss cycles
1826system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4912000 # number of demand (read+write) MSHR miss cycles
1827system.cpu3.icache.demand_mshr_miss_latency::total 4912000 # number of demand (read+write) MSHR miss cycles
1828system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4912000 # number of overall MSHR miss cycles
1829system.cpu3.icache.overall_mshr_miss_latency::total 4912000 # number of overall MSHR miss cycles
1830system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for ReadReq accesses
1831system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.017666 # mshr miss rate for ReadReq accesses
1832system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for demand accesses
1833system.cpu3.icache.demand_mshr_miss_rate::total 0.017666 # mshr miss rate for demand accesses
1834system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for overall accesses
1835system.cpu3.icache.overall_mshr_miss_rate::total 0.017666 # mshr miss rate for overall accesses
1836system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average ReadReq mshr miss latency
1837system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11370.370370 # average ReadReq mshr miss latency
1838system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average overall mshr miss latency
1839system.cpu3.icache.demand_avg_mshr_miss_latency::total 11370.370370 # average overall mshr miss latency
1840system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average overall mshr miss latency
1841system.cpu3.icache.overall_avg_mshr_miss_latency::total 11370.370370 # average overall mshr miss latency
1842system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1843system.cpu3.dcache.replacements 2 # number of replacements
1844system.cpu3.dcache.tagsinuse 25.290478 # Cycle average of tags in use
1845system.cpu3.dcache.total_refs 37716 # Total number of references to valid blocks.
1846system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks.
1847system.cpu3.dcache.avg_refs 1257.200000 # Average number of references to valid blocks.
1848system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1849system.cpu3.dcache.occ_blocks::cpu3.data 25.290478 # Average occupied blocks per requestor

--- 35 unchanged lines hidden (view full) ---

1885system.cpu3.dcache.WriteReq_accesses::total 31338 # number of WriteReq accesses(hits+misses)
1886system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses)
1887system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
1888system.cpu3.dcache.demand_accesses::cpu3.data 74691 # number of demand (read+write) accesses
1889system.cpu3.dcache.demand_accesses::total 74691 # number of demand (read+write) accesses
1890system.cpu3.dcache.overall_accesses::cpu3.data 74691 # number of overall (read+write) accesses
1891system.cpu3.dcache.overall_accesses::total 74691 # number of overall (read+write) accesses
1892system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009688 # miss rate for ReadReq accesses
1893system.cpu3.dcache.ReadReq_miss_rate::total 0.009688 # miss rate for ReadReq accesses
1894system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004755 # miss rate for WriteReq accesses
1895system.cpu3.dcache.WriteReq_miss_rate::total 0.004755 # miss rate for WriteReq accesses
1896system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses
1897system.cpu3.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses
1898system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007618 # miss rate for demand accesses
1899system.cpu3.dcache.demand_miss_rate::total 0.007618 # miss rate for demand accesses
1900system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007618 # miss rate for overall accesses
1901system.cpu3.dcache.overall_miss_rate::total 0.007618 # miss rate for overall accesses
1902system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 20514.285714 # average ReadReq miss latency
1903system.cpu3.dcache.ReadReq_avg_miss_latency::total 20514.285714 # average ReadReq miss latency
1904system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20184.563758 # average WriteReq miss latency
1905system.cpu3.dcache.WriteReq_avg_miss_latency::total 20184.563758 # average WriteReq miss latency
1906system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 21017.543860 # average SwapReq miss latency
1907system.cpu3.dcache.SwapReq_avg_miss_latency::total 21017.543860 # average SwapReq miss latency
1908system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 20427.943761 # average overall miss latency
1909system.cpu3.dcache.demand_avg_miss_latency::total 20427.943761 # average overall miss latency
1910system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 20427.943761 # average overall miss latency
1911system.cpu3.dcache.overall_avg_miss_latency::total 20427.943761 # average overall miss latency
1912system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1913system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1914system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1915system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
1916system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1917system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1918system.cpu3.dcache.fast_writes 0 # number of fast writes performed
1919system.cpu3.dcache.cache_copies 0 # number of cache copies performed

--- 23 unchanged lines hidden (view full) ---

1943system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1621000 # number of WriteReq MSHR miss cycles
1944system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 1027000 # number of SwapReq MSHR miss cycles
1945system.cpu3.dcache.SwapReq_mshr_miss_latency::total 1027000 # number of SwapReq MSHR miss cycles
1946system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3772000 # number of demand (read+write) MSHR miss cycles
1947system.cpu3.dcache.demand_mshr_miss_latency::total 3772000 # number of demand (read+write) MSHR miss cycles
1948system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3772000 # number of overall MSHR miss cycles
1949system.cpu3.dcache.overall_mshr_miss_latency::total 3772000 # number of overall MSHR miss cycles
1950system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003760 # mshr miss rate for ReadReq accesses
1951system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003760 # mshr miss rate for ReadReq accesses
1952system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003319 # mshr miss rate for WriteReq accesses
1953system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003319 # mshr miss rate for WriteReq accesses
1954system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses
1955system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses
1956system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003575 # mshr miss rate for demand accesses
1957system.cpu3.dcache.demand_mshr_miss_rate::total 0.003575 # mshr miss rate for demand accesses
1958system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003575 # mshr miss rate for overall accesses
1959system.cpu3.dcache.overall_mshr_miss_rate::total 0.003575 # mshr miss rate for overall accesses
1960system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13196.319018 # average ReadReq mshr miss latency
1961system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 13196.319018 # average ReadReq mshr miss latency
1962system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15586.538462 # average WriteReq mshr miss latency
1963system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15586.538462 # average WriteReq mshr miss latency
1964system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 18017.543860 # average SwapReq mshr miss latency
1965system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 18017.543860 # average SwapReq mshr miss latency
1966system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14127.340824 # average overall mshr miss latency
1967system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14127.340824 # average overall mshr miss latency
1968system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14127.340824 # average overall mshr miss latency
1969system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14127.340824 # average overall mshr miss latency
1970system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1971system.l2c.replacements 0 # number of replacements
1972system.l2c.tagsinuse 441.136869 # Cycle average of tags in use
1973system.l2c.total_refs 1471 # Total number of references to valid blocks.
1974system.l2c.sampled_refs 544 # Sample count of references to valid blocks.
1975system.l2c.avg_refs 2.704044 # Average number of references to valid blocks.
1976system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1977system.l2c.occ_blocks::writebacks 4.878414 # Average occupied blocks per requestor

--- 161 unchanged lines hidden (view full) ---

2139system.l2c.ReadReq_miss_rate::cpu0.inst 0.611111 # miss rate for ReadReq accesses
2140system.l2c.ReadReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadReq accesses
2141system.l2c.ReadReq_miss_rate::cpu1.inst 0.034483 # miss rate for ReadReq accesses
2142system.l2c.ReadReq_miss_rate::cpu1.data 0.071429 # miss rate for ReadReq accesses
2143system.l2c.ReadReq_miss_rate::cpu2.inst 0.193182 # miss rate for ReadReq accesses
2144system.l2c.ReadReq_miss_rate::cpu2.data 0.500000 # miss rate for ReadReq accesses
2145system.l2c.ReadReq_miss_rate::cpu3.inst 0.004630 # miss rate for ReadReq accesses
2146system.l2c.ReadReq_miss_rate::cpu3.data 0.071429 # miss rate for ReadReq accesses
2147system.l2c.ReadReq_miss_rate::total 0.271379 # miss rate for ReadReq accesses
2148system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses
2149system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
2150system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
2151system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
2152system.l2c.UpgradeReq_miss_rate::total 0.963855 # miss rate for UpgradeReq accesses
2153system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
2154system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
2155system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
2156system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
2157system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
2158system.l2c.demand_miss_rate::cpu0.inst 0.611111 # miss rate for demand accesses
2159system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses
2160system.l2c.demand_miss_rate::cpu1.inst 0.034483 # miss rate for demand accesses
2161system.l2c.demand_miss_rate::cpu1.data 0.500000 # miss rate for demand accesses
2162system.l2c.demand_miss_rate::cpu2.inst 0.193182 # miss rate for demand accesses
2163system.l2c.demand_miss_rate::cpu2.data 0.740741 # miss rate for demand accesses
2164system.l2c.demand_miss_rate::cpu3.inst 0.004630 # miss rate for demand accesses
2165system.l2c.demand_miss_rate::cpu3.data 0.500000 # miss rate for demand accesses
2166system.l2c.demand_miss_rate::total 0.315692 # miss rate for demand accesses
2167system.l2c.overall_miss_rate::cpu0.inst 0.611111 # miss rate for overall accesses
2168system.l2c.overall_miss_rate::cpu0.data 0.971264 # miss rate for overall accesses
2169system.l2c.overall_miss_rate::cpu1.inst 0.034483 # miss rate for overall accesses
2170system.l2c.overall_miss_rate::cpu1.data 0.500000 # miss rate for overall accesses
2171system.l2c.overall_miss_rate::cpu2.inst 0.193182 # miss rate for overall accesses
2172system.l2c.overall_miss_rate::cpu2.data 0.740741 # miss rate for overall accesses
2173system.l2c.overall_miss_rate::cpu3.inst 0.004630 # miss rate for overall accesses
2174system.l2c.overall_miss_rate::cpu3.data 0.500000 # miss rate for overall accesses
2175system.l2c.overall_miss_rate::total 0.315692 # miss rate for overall accesses
2176system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52119.834711 # average ReadReq miss latency
2177system.l2c.ReadReq_avg_miss_latency::cpu0.data 52393.333333 # average ReadReq miss latency
2178system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49633.333333 # average ReadReq miss latency
2179system.l2c.ReadReq_avg_miss_latency::cpu1.data 52500 # average ReadReq miss latency
2180system.l2c.ReadReq_avg_miss_latency::cpu2.inst 51482.352941 # average ReadReq miss latency
2181system.l2c.ReadReq_avg_miss_latency::cpu2.data 52285.714286 # average ReadReq miss latency
2182system.l2c.ReadReq_avg_miss_latency::cpu3.inst 49750 # average ReadReq miss latency
2183system.l2c.ReadReq_avg_miss_latency::cpu3.data 52500 # average ReadReq miss latency
2184system.l2c.ReadReq_avg_miss_latency::total 51985.428051 # average ReadReq miss latency
2185system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2500 # average UpgradeReq miss latency
2186system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 3088.235294 # average UpgradeReq miss latency
2187system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 2625 # average UpgradeReq miss latency
2188system.l2c.UpgradeReq_avg_miss_latency::total 1968.750000 # average UpgradeReq miss latency
2189system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52547.872340 # average ReadExReq miss latency
2190system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52291.666667 # average ReadExReq miss latency
2191system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52346.153846 # average ReadExReq miss latency
2192system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52291.666667 # average ReadExReq miss latency
2193system.l2c.ReadExReq_avg_miss_latency::total 52480.916031 # average ReadExReq miss latency
2194system.l2c.demand_avg_miss_latency::cpu0.inst 52119.834711 # average overall miss latency
2195system.l2c.demand_avg_miss_latency::cpu0.data 52479.289941 # average overall miss latency
2196system.l2c.demand_avg_miss_latency::cpu1.inst 49633.333333 # average overall miss latency
2197system.l2c.demand_avg_miss_latency::cpu1.data 52307.692308 # average overall miss latency
2198system.l2c.demand_avg_miss_latency::cpu2.inst 51482.352941 # average overall miss latency
2199system.l2c.demand_avg_miss_latency::cpu2.data 52325 # average overall miss latency
2200system.l2c.demand_avg_miss_latency::cpu3.inst 49750 # average overall miss latency
2201system.l2c.demand_avg_miss_latency::cpu3.data 52307.692308 # average overall miss latency
2202system.l2c.demand_avg_miss_latency::total 52080.882353 # average overall miss latency
2203system.l2c.overall_avg_miss_latency::cpu0.inst 52119.834711 # average overall miss latency
2204system.l2c.overall_avg_miss_latency::cpu0.data 52479.289941 # average overall miss latency
2205system.l2c.overall_avg_miss_latency::cpu1.inst 49633.333333 # average overall miss latency
2206system.l2c.overall_avg_miss_latency::cpu1.data 52307.692308 # average overall miss latency
2207system.l2c.overall_avg_miss_latency::cpu2.inst 51482.352941 # average overall miss latency
2208system.l2c.overall_avg_miss_latency::cpu2.data 52325 # average overall miss latency
2209system.l2c.overall_avg_miss_latency::cpu3.inst 49750 # average overall miss latency
2210system.l2c.overall_avg_miss_latency::cpu3.data 52307.692308 # average overall miss latency
2211system.l2c.overall_avg_miss_latency::total 52080.882353 # average overall miss latency
2212system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2213system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2214system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
2215system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2216system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2217system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2218system.l2c.fast_writes 0 # number of fast writes performed
2219system.l2c.cache_copies 0 # number of cache copies performed

--- 86 unchanged lines hidden (view full) ---

2306system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for ReadReq accesses
2307system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadReq accesses
2308system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for ReadReq accesses
2309system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.071429 # mshr miss rate for ReadReq accesses
2310system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.181818 # mshr miss rate for ReadReq accesses
2311system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.500000 # mshr miss rate for ReadReq accesses
2312system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for ReadReq accesses
2313system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.071429 # mshr miss rate for ReadReq accesses
2314system.l2c.ReadReq_mshr_miss_rate::total 0.267919 # mshr miss rate for ReadReq accesses
2315system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses
2316system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2317system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
2318system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
2319system.l2c.UpgradeReq_mshr_miss_rate::total 0.963855 # mshr miss rate for UpgradeReq accesses
2320system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
2321system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
2322system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
2323system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
2324system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
2325system.l2c.demand_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for demand accesses
2326system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses
2327system.l2c.demand_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for demand accesses
2328system.l2c.demand_mshr_miss_rate::cpu1.data 0.500000 # mshr miss rate for demand accesses
2329system.l2c.demand_mshr_miss_rate::cpu2.inst 0.181818 # mshr miss rate for demand accesses
2330system.l2c.demand_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for demand accesses
2331system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for demand accesses
2332system.l2c.demand_mshr_miss_rate::cpu3.data 0.500000 # mshr miss rate for demand accesses
2333system.l2c.demand_mshr_miss_rate::total 0.312442 # mshr miss rate for demand accesses
2334system.l2c.overall_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for overall accesses
2335system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses
2336system.l2c.overall_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for overall accesses
2337system.l2c.overall_mshr_miss_rate::cpu1.data 0.500000 # mshr miss rate for overall accesses
2338system.l2c.overall_mshr_miss_rate::cpu2.inst 0.181818 # mshr miss rate for overall accesses
2339system.l2c.overall_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for overall accesses
2340system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for overall accesses
2341system.l2c.overall_mshr_miss_rate::cpu3.data 0.500000 # mshr miss rate for overall accesses
2342system.l2c.overall_mshr_miss_rate::total 0.312442 # mshr miss rate for overall accesses
2343system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average ReadReq mshr miss latency
2344system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40220 # average ReadReq mshr miss latency
2345system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency
2346system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency
2347system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency
2348system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency
2349system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency
2350system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency
2351system.l2c.ReadReq_avg_mshr_miss_latency::total 39979.704797 # average ReadReq mshr miss latency
2352system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency
2353system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency
2354system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency
2355system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency
2356system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40000 # average UpgradeReq mshr miss latency
2357system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40351.063830 # average ReadExReq mshr miss latency
2358system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40125 # average ReadExReq mshr miss latency
2359system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40192.307692 # average ReadExReq mshr miss latency
2360system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40125 # average ReadExReq mshr miss latency
2361system.l2c.ReadExReq_avg_mshr_miss_latency::total 40293.893130 # average ReadExReq mshr miss latency
2362system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average overall mshr miss latency
2363system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40292.899408 # average overall mshr miss latency
2364system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency
2365system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40115.384615 # average overall mshr miss latency
2366system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
2367system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40125 # average overall mshr miss latency
2368system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
2369system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency
2370system.l2c.demand_avg_mshr_miss_latency::total 40040.861813 # average overall mshr miss latency
2371system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average overall mshr miss latency
2372system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40292.899408 # average overall mshr miss latency
2373system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency
2374system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40115.384615 # average overall mshr miss latency
2375system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
2376system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40125 # average overall mshr miss latency
2377system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
2378system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency
2379system.l2c.overall_avg_mshr_miss_latency::total 40040.861813 # average overall mshr miss latency
2380system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2381
2382---------- End Simulation Statistics ----------