| config.ini (9924:31ef410b6843) | config.ini (9988:0b2e590c85be) |
|---|---|
| 1[root] 2type=Root 3children=system | 1[root] 2type=Root 3children=system |
| 4eventq_index=0 |
|
| 4full_system=false | 5full_system=false |
| 6sim_quantum=0 |
|
| 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bus voltage_domain 12boot_osflags=a 13cache_line_size=64 14clk_domain=system.clk_domain | 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bus voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain |
| 17eventq_index=0 |
|
| 15init_param=0 16kernel= 17load_addr_mask=1099511627775 18mem_mode=timing 19mem_ranges= 20memories=system.physmem 21num_work_ids=16 22readfile= --- 5 unchanged lines hidden (view full) --- 28work_end_ckpt_count=0 29work_end_exit_count=0 30work_item_id=-1 31system_port=system.membus.slave[0] 32 33[system.clk_domain] 34type=SrcClockDomain 35clock=1000 | 18init_param=0 19kernel= 20load_addr_mask=1099511627775 21mem_mode=timing 22mem_ranges= 23memories=system.physmem 24num_work_ids=16 25readfile= --- 5 unchanged lines hidden (view full) --- 31work_end_ckpt_count=0 32work_end_exit_count=0 33work_item_id=-1 34system_port=system.membus.slave[0] 35 36[system.clk_domain] 37type=SrcClockDomain 38clock=1000 |
| 39eventq_index=0 |
|
| 36voltage_domain=system.voltage_domain 37 38[system.cpu0] 39type=DerivO3CPU 40children=branchPred dcache dtb fuPool icache interrupts isa itb tracer workload 41LFSTSize=1024 42LQEntries=32 43LSQCheckLoads=true --- 15 unchanged lines hidden (view full) --- 59decodeToFetchDelay=1 60decodeToRenameDelay=1 61decodeWidth=8 62dispatchWidth=8 63do_checkpoint_insts=true 64do_quiesce=true 65do_statistics_insts=true 66dtb=system.cpu0.dtb | 40voltage_domain=system.voltage_domain 41 42[system.cpu0] 43type=DerivO3CPU 44children=branchPred dcache dtb fuPool icache interrupts isa itb tracer workload 45LFSTSize=1024 46LQEntries=32 47LSQCheckLoads=true --- 15 unchanged lines hidden (view full) --- 63decodeToFetchDelay=1 64decodeToRenameDelay=1 65decodeWidth=8 66dispatchWidth=8 67do_checkpoint_insts=true 68do_quiesce=true 69do_statistics_insts=true 70dtb=system.cpu0.dtb |
| 71eventq_index=0 72fetchBufferSize=64 |
|
| 67fetchToDecodeDelay=1 68fetchTrapLatency=1 69fetchWidth=8 70forwardComSize=5 71fuPool=system.cpu0.fuPool 72function_trace=false 73function_trace_start=0 74iewToCommitDelay=1 --- 48 unchanged lines hidden (view full) --- 123 124[system.cpu0.branchPred] 125type=BranchPredictor 126BTBEntries=4096 127BTBTagSize=16 128RASSize=16 129choiceCtrBits=2 130choicePredictorSize=8192 | 73fetchToDecodeDelay=1 74fetchTrapLatency=1 75fetchWidth=8 76forwardComSize=5 77fuPool=system.cpu0.fuPool 78function_trace=false 79function_trace_start=0 80iewToCommitDelay=1 --- 48 unchanged lines hidden (view full) --- 129 130[system.cpu0.branchPred] 131type=BranchPredictor 132BTBEntries=4096 133BTBTagSize=16 134RASSize=16 135choiceCtrBits=2 136choicePredictorSize=8192 |
| 137eventq_index=0 |
|
| 131globalCtrBits=2 132globalPredictorSize=8192 133instShiftAmt=2 134localCtrBits=2 135localHistoryTableSize=2048 136localPredictorSize=2048 137numThreads=1 138predType=tournament 139 140[system.cpu0.dcache] 141type=BaseCache 142children=tags 143addr_ranges=0:18446744073709551615 144assoc=4 145clk_domain=system.cpu_clk_domain | 138globalCtrBits=2 139globalPredictorSize=8192 140instShiftAmt=2 141localCtrBits=2 142localHistoryTableSize=2048 143localPredictorSize=2048 144numThreads=1 145predType=tournament 146 147[system.cpu0.dcache] 148type=BaseCache 149children=tags 150addr_ranges=0:18446744073709551615 151assoc=4 152clk_domain=system.cpu_clk_domain |
| 153eventq_index=0 |
|
| 146forward_snoops=true 147hit_latency=2 148is_top_level=true 149max_miss_count=0 150mshrs=4 151prefetch_on_access=false 152prefetcher=Null 153response_latency=2 --- 6 unchanged lines hidden (view full) --- 160cpu_side=system.cpu0.dcache_port 161mem_side=system.toL2Bus.slave[1] 162 163[system.cpu0.dcache.tags] 164type=LRU 165assoc=4 166block_size=64 167clk_domain=system.cpu_clk_domain | 154forward_snoops=true 155hit_latency=2 156is_top_level=true 157max_miss_count=0 158mshrs=4 159prefetch_on_access=false 160prefetcher=Null 161response_latency=2 --- 6 unchanged lines hidden (view full) --- 168cpu_side=system.cpu0.dcache_port 169mem_side=system.toL2Bus.slave[1] 170 171[system.cpu0.dcache.tags] 172type=LRU 173assoc=4 174block_size=64 175clk_domain=system.cpu_clk_domain |
| 176eventq_index=0 |
|
| 168hit_latency=2 169size=32768 170 171[system.cpu0.dtb] 172type=SparcTLB | 177hit_latency=2 178size=32768 179 180[system.cpu0.dtb] 181type=SparcTLB |
| 182eventq_index=0 |
|
| 173size=64 174 175[system.cpu0.fuPool] 176type=FUPool 177children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 178FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 | 183size=64 184 185[system.cpu0.fuPool] 186type=FUPool 187children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 188FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 |
| 189eventq_index=0 |
|
| 179 180[system.cpu0.fuPool.FUList0] 181type=FUDesc 182children=opList 183count=6 | 190 191[system.cpu0.fuPool.FUList0] 192type=FUDesc 193children=opList 194count=6 |
| 195eventq_index=0 |
|
| 184opList=system.cpu0.fuPool.FUList0.opList 185 186[system.cpu0.fuPool.FUList0.opList] 187type=OpDesc | 196opList=system.cpu0.fuPool.FUList0.opList 197 198[system.cpu0.fuPool.FUList0.opList] 199type=OpDesc |
| 200eventq_index=0 |
|
| 188issueLat=1 189opClass=IntAlu 190opLat=1 191 192[system.cpu0.fuPool.FUList1] 193type=FUDesc 194children=opList0 opList1 195count=2 | 201issueLat=1 202opClass=IntAlu 203opLat=1 204 205[system.cpu0.fuPool.FUList1] 206type=FUDesc 207children=opList0 opList1 208count=2 |
| 209eventq_index=0 |
|
| 196opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 197 198[system.cpu0.fuPool.FUList1.opList0] 199type=OpDesc | 210opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 211 212[system.cpu0.fuPool.FUList1.opList0] 213type=OpDesc |
| 214eventq_index=0 |
|
| 200issueLat=1 201opClass=IntMult 202opLat=3 203 204[system.cpu0.fuPool.FUList1.opList1] 205type=OpDesc | 215issueLat=1 216opClass=IntMult 217opLat=3 218 219[system.cpu0.fuPool.FUList1.opList1] 220type=OpDesc |
| 221eventq_index=0 |
|
| 206issueLat=19 207opClass=IntDiv 208opLat=20 209 210[system.cpu0.fuPool.FUList2] 211type=FUDesc 212children=opList0 opList1 opList2 213count=4 | 222issueLat=19 223opClass=IntDiv 224opLat=20 225 226[system.cpu0.fuPool.FUList2] 227type=FUDesc 228children=opList0 opList1 opList2 229count=4 |
| 230eventq_index=0 |
|
| 214opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 215 216[system.cpu0.fuPool.FUList2.opList0] 217type=OpDesc | 231opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 232 233[system.cpu0.fuPool.FUList2.opList0] 234type=OpDesc |
| 235eventq_index=0 |
|
| 218issueLat=1 219opClass=FloatAdd 220opLat=2 221 222[system.cpu0.fuPool.FUList2.opList1] 223type=OpDesc | 236issueLat=1 237opClass=FloatAdd 238opLat=2 239 240[system.cpu0.fuPool.FUList2.opList1] 241type=OpDesc |
| 242eventq_index=0 |
|
| 224issueLat=1 225opClass=FloatCmp 226opLat=2 227 228[system.cpu0.fuPool.FUList2.opList2] 229type=OpDesc | 243issueLat=1 244opClass=FloatCmp 245opLat=2 246 247[system.cpu0.fuPool.FUList2.opList2] 248type=OpDesc |
| 249eventq_index=0 |
|
| 230issueLat=1 231opClass=FloatCvt 232opLat=2 233 234[system.cpu0.fuPool.FUList3] 235type=FUDesc 236children=opList0 opList1 opList2 237count=2 | 250issueLat=1 251opClass=FloatCvt 252opLat=2 253 254[system.cpu0.fuPool.FUList3] 255type=FUDesc 256children=opList0 opList1 opList2 257count=2 |
| 258eventq_index=0 |
|
| 238opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 239 240[system.cpu0.fuPool.FUList3.opList0] 241type=OpDesc | 259opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 260 261[system.cpu0.fuPool.FUList3.opList0] 262type=OpDesc |
| 263eventq_index=0 |
|
| 242issueLat=1 243opClass=FloatMult 244opLat=4 245 246[system.cpu0.fuPool.FUList3.opList1] 247type=OpDesc | 264issueLat=1 265opClass=FloatMult 266opLat=4 267 268[system.cpu0.fuPool.FUList3.opList1] 269type=OpDesc |
| 270eventq_index=0 |
|
| 248issueLat=12 249opClass=FloatDiv 250opLat=12 251 252[system.cpu0.fuPool.FUList3.opList2] 253type=OpDesc | 271issueLat=12 272opClass=FloatDiv 273opLat=12 274 275[system.cpu0.fuPool.FUList3.opList2] 276type=OpDesc |
| 277eventq_index=0 |
|
| 254issueLat=24 255opClass=FloatSqrt 256opLat=24 257 258[system.cpu0.fuPool.FUList4] 259type=FUDesc 260children=opList 261count=0 | 278issueLat=24 279opClass=FloatSqrt 280opLat=24 281 282[system.cpu0.fuPool.FUList4] 283type=FUDesc 284children=opList 285count=0 |
| 286eventq_index=0 |
|
| 262opList=system.cpu0.fuPool.FUList4.opList 263 264[system.cpu0.fuPool.FUList4.opList] 265type=OpDesc | 287opList=system.cpu0.fuPool.FUList4.opList 288 289[system.cpu0.fuPool.FUList4.opList] 290type=OpDesc |
| 291eventq_index=0 |
|
| 266issueLat=1 267opClass=MemRead 268opLat=1 269 270[system.cpu0.fuPool.FUList5] 271type=FUDesc 272children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 273count=4 | 292issueLat=1 293opClass=MemRead 294opLat=1 295 296[system.cpu0.fuPool.FUList5] 297type=FUDesc 298children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 299count=4 |
| 300eventq_index=0 |
|
| 274opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 275 276[system.cpu0.fuPool.FUList5.opList00] 277type=OpDesc | 301opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 302 303[system.cpu0.fuPool.FUList5.opList00] 304type=OpDesc |
| 305eventq_index=0 |
|
| 278issueLat=1 279opClass=SimdAdd 280opLat=1 281 282[system.cpu0.fuPool.FUList5.opList01] 283type=OpDesc | 306issueLat=1 307opClass=SimdAdd 308opLat=1 309 310[system.cpu0.fuPool.FUList5.opList01] 311type=OpDesc |
| 312eventq_index=0 |
|
| 284issueLat=1 285opClass=SimdAddAcc 286opLat=1 287 288[system.cpu0.fuPool.FUList5.opList02] 289type=OpDesc | 313issueLat=1 314opClass=SimdAddAcc 315opLat=1 316 317[system.cpu0.fuPool.FUList5.opList02] 318type=OpDesc |
| 319eventq_index=0 |
|
| 290issueLat=1 291opClass=SimdAlu 292opLat=1 293 294[system.cpu0.fuPool.FUList5.opList03] 295type=OpDesc | 320issueLat=1 321opClass=SimdAlu 322opLat=1 323 324[system.cpu0.fuPool.FUList5.opList03] 325type=OpDesc |
| 326eventq_index=0 |
|
| 296issueLat=1 297opClass=SimdCmp 298opLat=1 299 300[system.cpu0.fuPool.FUList5.opList04] 301type=OpDesc | 327issueLat=1 328opClass=SimdCmp 329opLat=1 330 331[system.cpu0.fuPool.FUList5.opList04] 332type=OpDesc |
| 333eventq_index=0 |
|
| 302issueLat=1 303opClass=SimdCvt 304opLat=1 305 306[system.cpu0.fuPool.FUList5.opList05] 307type=OpDesc | 334issueLat=1 335opClass=SimdCvt 336opLat=1 337 338[system.cpu0.fuPool.FUList5.opList05] 339type=OpDesc |
| 340eventq_index=0 |
|
| 308issueLat=1 309opClass=SimdMisc 310opLat=1 311 312[system.cpu0.fuPool.FUList5.opList06] 313type=OpDesc | 341issueLat=1 342opClass=SimdMisc 343opLat=1 344 345[system.cpu0.fuPool.FUList5.opList06] 346type=OpDesc |
| 347eventq_index=0 |
|
| 314issueLat=1 315opClass=SimdMult 316opLat=1 317 318[system.cpu0.fuPool.FUList5.opList07] 319type=OpDesc | 348issueLat=1 349opClass=SimdMult 350opLat=1 351 352[system.cpu0.fuPool.FUList5.opList07] 353type=OpDesc |
| 354eventq_index=0 |
|
| 320issueLat=1 321opClass=SimdMultAcc 322opLat=1 323 324[system.cpu0.fuPool.FUList5.opList08] 325type=OpDesc | 355issueLat=1 356opClass=SimdMultAcc 357opLat=1 358 359[system.cpu0.fuPool.FUList5.opList08] 360type=OpDesc |
| 361eventq_index=0 |
|
| 326issueLat=1 327opClass=SimdShift 328opLat=1 329 330[system.cpu0.fuPool.FUList5.opList09] 331type=OpDesc | 362issueLat=1 363opClass=SimdShift 364opLat=1 365 366[system.cpu0.fuPool.FUList5.opList09] 367type=OpDesc |
| 368eventq_index=0 |
|
| 332issueLat=1 333opClass=SimdShiftAcc 334opLat=1 335 336[system.cpu0.fuPool.FUList5.opList10] 337type=OpDesc | 369issueLat=1 370opClass=SimdShiftAcc 371opLat=1 372 373[system.cpu0.fuPool.FUList5.opList10] 374type=OpDesc |
| 375eventq_index=0 |
|
| 338issueLat=1 339opClass=SimdSqrt 340opLat=1 341 342[system.cpu0.fuPool.FUList5.opList11] 343type=OpDesc | 376issueLat=1 377opClass=SimdSqrt 378opLat=1 379 380[system.cpu0.fuPool.FUList5.opList11] 381type=OpDesc |
| 382eventq_index=0 |
|
| 344issueLat=1 345opClass=SimdFloatAdd 346opLat=1 347 348[system.cpu0.fuPool.FUList5.opList12] 349type=OpDesc | 383issueLat=1 384opClass=SimdFloatAdd 385opLat=1 386 387[system.cpu0.fuPool.FUList5.opList12] 388type=OpDesc |
| 389eventq_index=0 |
|
| 350issueLat=1 351opClass=SimdFloatAlu 352opLat=1 353 354[system.cpu0.fuPool.FUList5.opList13] 355type=OpDesc | 390issueLat=1 391opClass=SimdFloatAlu 392opLat=1 393 394[system.cpu0.fuPool.FUList5.opList13] 395type=OpDesc |
| 396eventq_index=0 |
|
| 356issueLat=1 357opClass=SimdFloatCmp 358opLat=1 359 360[system.cpu0.fuPool.FUList5.opList14] 361type=OpDesc | 397issueLat=1 398opClass=SimdFloatCmp 399opLat=1 400 401[system.cpu0.fuPool.FUList5.opList14] 402type=OpDesc |
| 403eventq_index=0 |
|
| 362issueLat=1 363opClass=SimdFloatCvt 364opLat=1 365 366[system.cpu0.fuPool.FUList5.opList15] 367type=OpDesc | 404issueLat=1 405opClass=SimdFloatCvt 406opLat=1 407 408[system.cpu0.fuPool.FUList5.opList15] 409type=OpDesc |
| 410eventq_index=0 |
|
| 368issueLat=1 369opClass=SimdFloatDiv 370opLat=1 371 372[system.cpu0.fuPool.FUList5.opList16] 373type=OpDesc | 411issueLat=1 412opClass=SimdFloatDiv 413opLat=1 414 415[system.cpu0.fuPool.FUList5.opList16] 416type=OpDesc |
| 417eventq_index=0 |
|
| 374issueLat=1 375opClass=SimdFloatMisc 376opLat=1 377 378[system.cpu0.fuPool.FUList5.opList17] 379type=OpDesc | 418issueLat=1 419opClass=SimdFloatMisc 420opLat=1 421 422[system.cpu0.fuPool.FUList5.opList17] 423type=OpDesc |
| 424eventq_index=0 |
|
| 380issueLat=1 381opClass=SimdFloatMult 382opLat=1 383 384[system.cpu0.fuPool.FUList5.opList18] 385type=OpDesc | 425issueLat=1 426opClass=SimdFloatMult 427opLat=1 428 429[system.cpu0.fuPool.FUList5.opList18] 430type=OpDesc |
| 431eventq_index=0 |
|
| 386issueLat=1 387opClass=SimdFloatMultAcc 388opLat=1 389 390[system.cpu0.fuPool.FUList5.opList19] 391type=OpDesc | 432issueLat=1 433opClass=SimdFloatMultAcc 434opLat=1 435 436[system.cpu0.fuPool.FUList5.opList19] 437type=OpDesc |
| 438eventq_index=0 |
|
| 392issueLat=1 393opClass=SimdFloatSqrt 394opLat=1 395 396[system.cpu0.fuPool.FUList6] 397type=FUDesc 398children=opList 399count=0 | 439issueLat=1 440opClass=SimdFloatSqrt 441opLat=1 442 443[system.cpu0.fuPool.FUList6] 444type=FUDesc 445children=opList 446count=0 |
| 447eventq_index=0 |
|
| 400opList=system.cpu0.fuPool.FUList6.opList 401 402[system.cpu0.fuPool.FUList6.opList] 403type=OpDesc | 448opList=system.cpu0.fuPool.FUList6.opList 449 450[system.cpu0.fuPool.FUList6.opList] 451type=OpDesc |
| 452eventq_index=0 |
|
| 404issueLat=1 405opClass=MemWrite 406opLat=1 407 408[system.cpu0.fuPool.FUList7] 409type=FUDesc 410children=opList0 opList1 411count=4 | 453issueLat=1 454opClass=MemWrite 455opLat=1 456 457[system.cpu0.fuPool.FUList7] 458type=FUDesc 459children=opList0 opList1 460count=4 |
| 461eventq_index=0 |
|
| 412opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 413 414[system.cpu0.fuPool.FUList7.opList0] 415type=OpDesc | 462opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 463 464[system.cpu0.fuPool.FUList7.opList0] 465type=OpDesc |
| 466eventq_index=0 |
|
| 416issueLat=1 417opClass=MemRead 418opLat=1 419 420[system.cpu0.fuPool.FUList7.opList1] 421type=OpDesc | 467issueLat=1 468opClass=MemRead 469opLat=1 470 471[system.cpu0.fuPool.FUList7.opList1] 472type=OpDesc |
| 473eventq_index=0 |
|
| 422issueLat=1 423opClass=MemWrite 424opLat=1 425 426[system.cpu0.fuPool.FUList8] 427type=FUDesc 428children=opList 429count=1 | 474issueLat=1 475opClass=MemWrite 476opLat=1 477 478[system.cpu0.fuPool.FUList8] 479type=FUDesc 480children=opList 481count=1 |
| 482eventq_index=0 |
|
| 430opList=system.cpu0.fuPool.FUList8.opList 431 432[system.cpu0.fuPool.FUList8.opList] 433type=OpDesc | 483opList=system.cpu0.fuPool.FUList8.opList 484 485[system.cpu0.fuPool.FUList8.opList] 486type=OpDesc |
| 487eventq_index=0 |
|
| 434issueLat=3 435opClass=IprAccess 436opLat=3 437 438[system.cpu0.icache] 439type=BaseCache 440children=tags 441addr_ranges=0:18446744073709551615 442assoc=1 443clk_domain=system.cpu_clk_domain | 488issueLat=3 489opClass=IprAccess 490opLat=3 491 492[system.cpu0.icache] 493type=BaseCache 494children=tags 495addr_ranges=0:18446744073709551615 496assoc=1 497clk_domain=system.cpu_clk_domain |
| 498eventq_index=0 |
|
| 444forward_snoops=true 445hit_latency=2 446is_top_level=true 447max_miss_count=0 448mshrs=4 449prefetch_on_access=false 450prefetcher=Null 451response_latency=2 --- 6 unchanged lines hidden (view full) --- 458cpu_side=system.cpu0.icache_port 459mem_side=system.toL2Bus.slave[0] 460 461[system.cpu0.icache.tags] 462type=LRU 463assoc=1 464block_size=64 465clk_domain=system.cpu_clk_domain | 499forward_snoops=true 500hit_latency=2 501is_top_level=true 502max_miss_count=0 503mshrs=4 504prefetch_on_access=false 505prefetcher=Null 506response_latency=2 --- 6 unchanged lines hidden (view full) --- 513cpu_side=system.cpu0.icache_port 514mem_side=system.toL2Bus.slave[0] 515 516[system.cpu0.icache.tags] 517type=LRU 518assoc=1 519block_size=64 520clk_domain=system.cpu_clk_domain |
| 521eventq_index=0 |
|
| 466hit_latency=2 467size=32768 468 469[system.cpu0.interrupts] 470type=SparcInterrupts | 522hit_latency=2 523size=32768 524 525[system.cpu0.interrupts] 526type=SparcInterrupts |
| 527eventq_index=0 |
|
| 471 472[system.cpu0.isa] 473type=SparcISA | 528 529[system.cpu0.isa] 530type=SparcISA |
| 531eventq_index=0 |
|
| 474 475[system.cpu0.itb] 476type=SparcTLB | 532 533[system.cpu0.itb] 534type=SparcTLB |
| 535eventq_index=0 |
|
| 477size=64 478 479[system.cpu0.tracer] 480type=ExeTracer | 536size=64 537 538[system.cpu0.tracer] 539type=ExeTracer |
| 540eventq_index=0 |
|
| 481 482[system.cpu0.workload] 483type=LiveProcess 484cmd=test_atomic 4 485cwd= 486egid=100 487env= 488errout=cerr 489euid=100 | 541 542[system.cpu0.workload] 543type=LiveProcess 544cmd=test_atomic 4 545cwd= 546egid=100 547env= 548errout=cerr 549euid=100 |
| 490executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic | 550eventq_index=0 551executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic |
| 491gid=100 492input=cin 493max_stack_size=67108864 494output=cout 495pid=100 496ppid=99 497simpoint=0 498system=system --- 23 unchanged lines hidden (view full) --- 522decodeToFetchDelay=1 523decodeToRenameDelay=1 524decodeWidth=8 525dispatchWidth=8 526do_checkpoint_insts=true 527do_quiesce=true 528do_statistics_insts=true 529dtb=system.cpu1.dtb | 552gid=100 553input=cin 554max_stack_size=67108864 555output=cout 556pid=100 557ppid=99 558simpoint=0 559system=system --- 23 unchanged lines hidden (view full) --- 583decodeToFetchDelay=1 584decodeToRenameDelay=1 585decodeWidth=8 586dispatchWidth=8 587do_checkpoint_insts=true 588do_quiesce=true 589do_statistics_insts=true 590dtb=system.cpu1.dtb |
| 591eventq_index=0 592fetchBufferSize=64 |
|
| 530fetchToDecodeDelay=1 531fetchTrapLatency=1 532fetchWidth=8 533forwardComSize=5 534fuPool=system.cpu1.fuPool 535function_trace=false 536function_trace_start=0 537iewToCommitDelay=1 --- 48 unchanged lines hidden (view full) --- 586 587[system.cpu1.branchPred] 588type=BranchPredictor 589BTBEntries=4096 590BTBTagSize=16 591RASSize=16 592choiceCtrBits=2 593choicePredictorSize=8192 | 593fetchToDecodeDelay=1 594fetchTrapLatency=1 595fetchWidth=8 596forwardComSize=5 597fuPool=system.cpu1.fuPool 598function_trace=false 599function_trace_start=0 600iewToCommitDelay=1 --- 48 unchanged lines hidden (view full) --- 649 650[system.cpu1.branchPred] 651type=BranchPredictor 652BTBEntries=4096 653BTBTagSize=16 654RASSize=16 655choiceCtrBits=2 656choicePredictorSize=8192 |
| 657eventq_index=0 |
|
| 594globalCtrBits=2 595globalPredictorSize=8192 596instShiftAmt=2 597localCtrBits=2 598localHistoryTableSize=2048 599localPredictorSize=2048 600numThreads=1 601predType=tournament 602 603[system.cpu1.dcache] 604type=BaseCache 605children=tags 606addr_ranges=0:18446744073709551615 607assoc=4 608clk_domain=system.cpu_clk_domain | 658globalCtrBits=2 659globalPredictorSize=8192 660instShiftAmt=2 661localCtrBits=2 662localHistoryTableSize=2048 663localPredictorSize=2048 664numThreads=1 665predType=tournament 666 667[system.cpu1.dcache] 668type=BaseCache 669children=tags 670addr_ranges=0:18446744073709551615 671assoc=4 672clk_domain=system.cpu_clk_domain |
| 673eventq_index=0 |
|
| 609forward_snoops=true 610hit_latency=2 611is_top_level=true 612max_miss_count=0 613mshrs=4 614prefetch_on_access=false 615prefetcher=Null 616response_latency=2 --- 6 unchanged lines hidden (view full) --- 623cpu_side=system.cpu1.dcache_port 624mem_side=system.toL2Bus.slave[3] 625 626[system.cpu1.dcache.tags] 627type=LRU 628assoc=4 629block_size=64 630clk_domain=system.cpu_clk_domain | 674forward_snoops=true 675hit_latency=2 676is_top_level=true 677max_miss_count=0 678mshrs=4 679prefetch_on_access=false 680prefetcher=Null 681response_latency=2 --- 6 unchanged lines hidden (view full) --- 688cpu_side=system.cpu1.dcache_port 689mem_side=system.toL2Bus.slave[3] 690 691[system.cpu1.dcache.tags] 692type=LRU 693assoc=4 694block_size=64 695clk_domain=system.cpu_clk_domain |
| 696eventq_index=0 |
|
| 631hit_latency=2 632size=32768 633 634[system.cpu1.dtb] 635type=SparcTLB | 697hit_latency=2 698size=32768 699 700[system.cpu1.dtb] 701type=SparcTLB |
| 702eventq_index=0 |
|
| 636size=64 637 638[system.cpu1.fuPool] 639type=FUPool 640children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 641FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 | 703size=64 704 705[system.cpu1.fuPool] 706type=FUPool 707children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 708FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 |
| 709eventq_index=0 |
|
| 642 643[system.cpu1.fuPool.FUList0] 644type=FUDesc 645children=opList 646count=6 | 710 711[system.cpu1.fuPool.FUList0] 712type=FUDesc 713children=opList 714count=6 |
| 715eventq_index=0 |
|
| 647opList=system.cpu1.fuPool.FUList0.opList 648 649[system.cpu1.fuPool.FUList0.opList] 650type=OpDesc | 716opList=system.cpu1.fuPool.FUList0.opList 717 718[system.cpu1.fuPool.FUList0.opList] 719type=OpDesc |
| 720eventq_index=0 |
|
| 651issueLat=1 652opClass=IntAlu 653opLat=1 654 655[system.cpu1.fuPool.FUList1] 656type=FUDesc 657children=opList0 opList1 658count=2 | 721issueLat=1 722opClass=IntAlu 723opLat=1 724 725[system.cpu1.fuPool.FUList1] 726type=FUDesc 727children=opList0 opList1 728count=2 |
| 729eventq_index=0 |
|
| 659opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 660 661[system.cpu1.fuPool.FUList1.opList0] 662type=OpDesc | 730opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 731 732[system.cpu1.fuPool.FUList1.opList0] 733type=OpDesc |
| 734eventq_index=0 |
|
| 663issueLat=1 664opClass=IntMult 665opLat=3 666 667[system.cpu1.fuPool.FUList1.opList1] 668type=OpDesc | 735issueLat=1 736opClass=IntMult 737opLat=3 738 739[system.cpu1.fuPool.FUList1.opList1] 740type=OpDesc |
| 741eventq_index=0 |
|
| 669issueLat=19 670opClass=IntDiv 671opLat=20 672 673[system.cpu1.fuPool.FUList2] 674type=FUDesc 675children=opList0 opList1 opList2 676count=4 | 742issueLat=19 743opClass=IntDiv 744opLat=20 745 746[system.cpu1.fuPool.FUList2] 747type=FUDesc 748children=opList0 opList1 opList2 749count=4 |
| 750eventq_index=0 |
|
| 677opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 678 679[system.cpu1.fuPool.FUList2.opList0] 680type=OpDesc | 751opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 752 753[system.cpu1.fuPool.FUList2.opList0] 754type=OpDesc |
| 755eventq_index=0 |
|
| 681issueLat=1 682opClass=FloatAdd 683opLat=2 684 685[system.cpu1.fuPool.FUList2.opList1] 686type=OpDesc | 756issueLat=1 757opClass=FloatAdd 758opLat=2 759 760[system.cpu1.fuPool.FUList2.opList1] 761type=OpDesc |
| 762eventq_index=0 |
|
| 687issueLat=1 688opClass=FloatCmp 689opLat=2 690 691[system.cpu1.fuPool.FUList2.opList2] 692type=OpDesc | 763issueLat=1 764opClass=FloatCmp 765opLat=2 766 767[system.cpu1.fuPool.FUList2.opList2] 768type=OpDesc |
| 769eventq_index=0 |
|
| 693issueLat=1 694opClass=FloatCvt 695opLat=2 696 697[system.cpu1.fuPool.FUList3] 698type=FUDesc 699children=opList0 opList1 opList2 700count=2 | 770issueLat=1 771opClass=FloatCvt 772opLat=2 773 774[system.cpu1.fuPool.FUList3] 775type=FUDesc 776children=opList0 opList1 opList2 777count=2 |
| 778eventq_index=0 |
|
| 701opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 702 703[system.cpu1.fuPool.FUList3.opList0] 704type=OpDesc | 779opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 780 781[system.cpu1.fuPool.FUList3.opList0] 782type=OpDesc |
| 783eventq_index=0 |
|
| 705issueLat=1 706opClass=FloatMult 707opLat=4 708 709[system.cpu1.fuPool.FUList3.opList1] 710type=OpDesc | 784issueLat=1 785opClass=FloatMult 786opLat=4 787 788[system.cpu1.fuPool.FUList3.opList1] 789type=OpDesc |
| 790eventq_index=0 |
|
| 711issueLat=12 712opClass=FloatDiv 713opLat=12 714 715[system.cpu1.fuPool.FUList3.opList2] 716type=OpDesc | 791issueLat=12 792opClass=FloatDiv 793opLat=12 794 795[system.cpu1.fuPool.FUList3.opList2] 796type=OpDesc |
| 797eventq_index=0 |
|
| 717issueLat=24 718opClass=FloatSqrt 719opLat=24 720 721[system.cpu1.fuPool.FUList4] 722type=FUDesc 723children=opList 724count=0 | 798issueLat=24 799opClass=FloatSqrt 800opLat=24 801 802[system.cpu1.fuPool.FUList4] 803type=FUDesc 804children=opList 805count=0 |
| 806eventq_index=0 |
|
| 725opList=system.cpu1.fuPool.FUList4.opList 726 727[system.cpu1.fuPool.FUList4.opList] 728type=OpDesc | 807opList=system.cpu1.fuPool.FUList4.opList 808 809[system.cpu1.fuPool.FUList4.opList] 810type=OpDesc |
| 811eventq_index=0 |
|
| 729issueLat=1 730opClass=MemRead 731opLat=1 732 733[system.cpu1.fuPool.FUList5] 734type=FUDesc 735children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 736count=4 | 812issueLat=1 813opClass=MemRead 814opLat=1 815 816[system.cpu1.fuPool.FUList5] 817type=FUDesc 818children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 819count=4 |
| 820eventq_index=0 |
|
| 737opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 738 739[system.cpu1.fuPool.FUList5.opList00] 740type=OpDesc | 821opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 822 823[system.cpu1.fuPool.FUList5.opList00] 824type=OpDesc |
| 825eventq_index=0 |
|
| 741issueLat=1 742opClass=SimdAdd 743opLat=1 744 745[system.cpu1.fuPool.FUList5.opList01] 746type=OpDesc | 826issueLat=1 827opClass=SimdAdd 828opLat=1 829 830[system.cpu1.fuPool.FUList5.opList01] 831type=OpDesc |
| 832eventq_index=0 |
|
| 747issueLat=1 748opClass=SimdAddAcc 749opLat=1 750 751[system.cpu1.fuPool.FUList5.opList02] 752type=OpDesc | 833issueLat=1 834opClass=SimdAddAcc 835opLat=1 836 837[system.cpu1.fuPool.FUList5.opList02] 838type=OpDesc |
| 839eventq_index=0 |
|
| 753issueLat=1 754opClass=SimdAlu 755opLat=1 756 757[system.cpu1.fuPool.FUList5.opList03] 758type=OpDesc | 840issueLat=1 841opClass=SimdAlu 842opLat=1 843 844[system.cpu1.fuPool.FUList5.opList03] 845type=OpDesc |
| 846eventq_index=0 |
|
| 759issueLat=1 760opClass=SimdCmp 761opLat=1 762 763[system.cpu1.fuPool.FUList5.opList04] 764type=OpDesc | 847issueLat=1 848opClass=SimdCmp 849opLat=1 850 851[system.cpu1.fuPool.FUList5.opList04] 852type=OpDesc |
| 853eventq_index=0 |
|
| 765issueLat=1 766opClass=SimdCvt 767opLat=1 768 769[system.cpu1.fuPool.FUList5.opList05] 770type=OpDesc | 854issueLat=1 855opClass=SimdCvt 856opLat=1 857 858[system.cpu1.fuPool.FUList5.opList05] 859type=OpDesc |
| 860eventq_index=0 |
|
| 771issueLat=1 772opClass=SimdMisc 773opLat=1 774 775[system.cpu1.fuPool.FUList5.opList06] 776type=OpDesc | 861issueLat=1 862opClass=SimdMisc 863opLat=1 864 865[system.cpu1.fuPool.FUList5.opList06] 866type=OpDesc |
| 867eventq_index=0 |
|
| 777issueLat=1 778opClass=SimdMult 779opLat=1 780 781[system.cpu1.fuPool.FUList5.opList07] 782type=OpDesc | 868issueLat=1 869opClass=SimdMult 870opLat=1 871 872[system.cpu1.fuPool.FUList5.opList07] 873type=OpDesc |
| 874eventq_index=0 |
|
| 783issueLat=1 784opClass=SimdMultAcc 785opLat=1 786 787[system.cpu1.fuPool.FUList5.opList08] 788type=OpDesc | 875issueLat=1 876opClass=SimdMultAcc 877opLat=1 878 879[system.cpu1.fuPool.FUList5.opList08] 880type=OpDesc |
| 881eventq_index=0 |
|
| 789issueLat=1 790opClass=SimdShift 791opLat=1 792 793[system.cpu1.fuPool.FUList5.opList09] 794type=OpDesc | 882issueLat=1 883opClass=SimdShift 884opLat=1 885 886[system.cpu1.fuPool.FUList5.opList09] 887type=OpDesc |
| 888eventq_index=0 |
|
| 795issueLat=1 796opClass=SimdShiftAcc 797opLat=1 798 799[system.cpu1.fuPool.FUList5.opList10] 800type=OpDesc | 889issueLat=1 890opClass=SimdShiftAcc 891opLat=1 892 893[system.cpu1.fuPool.FUList5.opList10] 894type=OpDesc |
| 895eventq_index=0 |
|
| 801issueLat=1 802opClass=SimdSqrt 803opLat=1 804 805[system.cpu1.fuPool.FUList5.opList11] 806type=OpDesc | 896issueLat=1 897opClass=SimdSqrt 898opLat=1 899 900[system.cpu1.fuPool.FUList5.opList11] 901type=OpDesc |
| 902eventq_index=0 |
|
| 807issueLat=1 808opClass=SimdFloatAdd 809opLat=1 810 811[system.cpu1.fuPool.FUList5.opList12] 812type=OpDesc | 903issueLat=1 904opClass=SimdFloatAdd 905opLat=1 906 907[system.cpu1.fuPool.FUList5.opList12] 908type=OpDesc |
| 909eventq_index=0 |
|
| 813issueLat=1 814opClass=SimdFloatAlu 815opLat=1 816 817[system.cpu1.fuPool.FUList5.opList13] 818type=OpDesc | 910issueLat=1 911opClass=SimdFloatAlu 912opLat=1 913 914[system.cpu1.fuPool.FUList5.opList13] 915type=OpDesc |
| 916eventq_index=0 |
|
| 819issueLat=1 820opClass=SimdFloatCmp 821opLat=1 822 823[system.cpu1.fuPool.FUList5.opList14] 824type=OpDesc | 917issueLat=1 918opClass=SimdFloatCmp 919opLat=1 920 921[system.cpu1.fuPool.FUList5.opList14] 922type=OpDesc |
| 923eventq_index=0 |
|
| 825issueLat=1 826opClass=SimdFloatCvt 827opLat=1 828 829[system.cpu1.fuPool.FUList5.opList15] 830type=OpDesc | 924issueLat=1 925opClass=SimdFloatCvt 926opLat=1 927 928[system.cpu1.fuPool.FUList5.opList15] 929type=OpDesc |
| 930eventq_index=0 |
|
| 831issueLat=1 832opClass=SimdFloatDiv 833opLat=1 834 835[system.cpu1.fuPool.FUList5.opList16] 836type=OpDesc | 931issueLat=1 932opClass=SimdFloatDiv 933opLat=1 934 935[system.cpu1.fuPool.FUList5.opList16] 936type=OpDesc |
| 937eventq_index=0 |
|
| 837issueLat=1 838opClass=SimdFloatMisc 839opLat=1 840 841[system.cpu1.fuPool.FUList5.opList17] 842type=OpDesc | 938issueLat=1 939opClass=SimdFloatMisc 940opLat=1 941 942[system.cpu1.fuPool.FUList5.opList17] 943type=OpDesc |
| 944eventq_index=0 |
|
| 843issueLat=1 844opClass=SimdFloatMult 845opLat=1 846 847[system.cpu1.fuPool.FUList5.opList18] 848type=OpDesc | 945issueLat=1 946opClass=SimdFloatMult 947opLat=1 948 949[system.cpu1.fuPool.FUList5.opList18] 950type=OpDesc |
| 951eventq_index=0 |
|
| 849issueLat=1 850opClass=SimdFloatMultAcc 851opLat=1 852 853[system.cpu1.fuPool.FUList5.opList19] 854type=OpDesc | 952issueLat=1 953opClass=SimdFloatMultAcc 954opLat=1 955 956[system.cpu1.fuPool.FUList5.opList19] 957type=OpDesc |
| 958eventq_index=0 |
|
| 855issueLat=1 856opClass=SimdFloatSqrt 857opLat=1 858 859[system.cpu1.fuPool.FUList6] 860type=FUDesc 861children=opList 862count=0 | 959issueLat=1 960opClass=SimdFloatSqrt 961opLat=1 962 963[system.cpu1.fuPool.FUList6] 964type=FUDesc 965children=opList 966count=0 |
| 967eventq_index=0 |
|
| 863opList=system.cpu1.fuPool.FUList6.opList 864 865[system.cpu1.fuPool.FUList6.opList] 866type=OpDesc | 968opList=system.cpu1.fuPool.FUList6.opList 969 970[system.cpu1.fuPool.FUList6.opList] 971type=OpDesc |
| 972eventq_index=0 |
|
| 867issueLat=1 868opClass=MemWrite 869opLat=1 870 871[system.cpu1.fuPool.FUList7] 872type=FUDesc 873children=opList0 opList1 874count=4 | 973issueLat=1 974opClass=MemWrite 975opLat=1 976 977[system.cpu1.fuPool.FUList7] 978type=FUDesc 979children=opList0 opList1 980count=4 |
| 981eventq_index=0 |
|
| 875opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 876 877[system.cpu1.fuPool.FUList7.opList0] 878type=OpDesc | 982opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 983 984[system.cpu1.fuPool.FUList7.opList0] 985type=OpDesc |
| 986eventq_index=0 |
|
| 879issueLat=1 880opClass=MemRead 881opLat=1 882 883[system.cpu1.fuPool.FUList7.opList1] 884type=OpDesc | 987issueLat=1 988opClass=MemRead 989opLat=1 990 991[system.cpu1.fuPool.FUList7.opList1] 992type=OpDesc |
| 993eventq_index=0 |
|
| 885issueLat=1 886opClass=MemWrite 887opLat=1 888 889[system.cpu1.fuPool.FUList8] 890type=FUDesc 891children=opList 892count=1 | 994issueLat=1 995opClass=MemWrite 996opLat=1 997 998[system.cpu1.fuPool.FUList8] 999type=FUDesc 1000children=opList 1001count=1 |
| 1002eventq_index=0 |
|
| 893opList=system.cpu1.fuPool.FUList8.opList 894 895[system.cpu1.fuPool.FUList8.opList] 896type=OpDesc | 1003opList=system.cpu1.fuPool.FUList8.opList 1004 1005[system.cpu1.fuPool.FUList8.opList] 1006type=OpDesc |
| 1007eventq_index=0 |
|
| 897issueLat=3 898opClass=IprAccess 899opLat=3 900 901[system.cpu1.icache] 902type=BaseCache 903children=tags 904addr_ranges=0:18446744073709551615 905assoc=1 906clk_domain=system.cpu_clk_domain | 1008issueLat=3 1009opClass=IprAccess 1010opLat=3 1011 1012[system.cpu1.icache] 1013type=BaseCache 1014children=tags 1015addr_ranges=0:18446744073709551615 1016assoc=1 1017clk_domain=system.cpu_clk_domain |
| 1018eventq_index=0 |
|
| 907forward_snoops=true 908hit_latency=2 909is_top_level=true 910max_miss_count=0 911mshrs=4 912prefetch_on_access=false 913prefetcher=Null 914response_latency=2 --- 6 unchanged lines hidden (view full) --- 921cpu_side=system.cpu1.icache_port 922mem_side=system.toL2Bus.slave[2] 923 924[system.cpu1.icache.tags] 925type=LRU 926assoc=1 927block_size=64 928clk_domain=system.cpu_clk_domain | 1019forward_snoops=true 1020hit_latency=2 1021is_top_level=true 1022max_miss_count=0 1023mshrs=4 1024prefetch_on_access=false 1025prefetcher=Null 1026response_latency=2 --- 6 unchanged lines hidden (view full) --- 1033cpu_side=system.cpu1.icache_port 1034mem_side=system.toL2Bus.slave[2] 1035 1036[system.cpu1.icache.tags] 1037type=LRU 1038assoc=1 1039block_size=64 1040clk_domain=system.cpu_clk_domain |
| 1041eventq_index=0 |
|
| 929hit_latency=2 930size=32768 931 932[system.cpu1.interrupts] 933type=SparcInterrupts | 1042hit_latency=2 1043size=32768 1044 1045[system.cpu1.interrupts] 1046type=SparcInterrupts |
| 1047eventq_index=0 |
|
| 934 935[system.cpu1.isa] 936type=SparcISA | 1048 1049[system.cpu1.isa] 1050type=SparcISA |
| 1051eventq_index=0 |
|
| 937 938[system.cpu1.itb] 939type=SparcTLB | 1052 1053[system.cpu1.itb] 1054type=SparcTLB |
| 1055eventq_index=0 |
|
| 940size=64 941 942[system.cpu1.tracer] 943type=ExeTracer | 1056size=64 1057 1058[system.cpu1.tracer] 1059type=ExeTracer |
| 1060eventq_index=0 |
|
| 944 945[system.cpu2] 946type=DerivO3CPU 947children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 948LFSTSize=1024 949LQEntries=32 950LSQCheckLoads=true 951LSQDepCheckShift=4 --- 14 unchanged lines hidden (view full) --- 966decodeToFetchDelay=1 967decodeToRenameDelay=1 968decodeWidth=8 969dispatchWidth=8 970do_checkpoint_insts=true 971do_quiesce=true 972do_statistics_insts=true 973dtb=system.cpu2.dtb | 1061 1062[system.cpu2] 1063type=DerivO3CPU 1064children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1065LFSTSize=1024 1066LQEntries=32 1067LSQCheckLoads=true 1068LSQDepCheckShift=4 --- 14 unchanged lines hidden (view full) --- 1083decodeToFetchDelay=1 1084decodeToRenameDelay=1 1085decodeWidth=8 1086dispatchWidth=8 1087do_checkpoint_insts=true 1088do_quiesce=true 1089do_statistics_insts=true 1090dtb=system.cpu2.dtb |
| 1091eventq_index=0 1092fetchBufferSize=64 |
|
| 974fetchToDecodeDelay=1 975fetchTrapLatency=1 976fetchWidth=8 977forwardComSize=5 978fuPool=system.cpu2.fuPool 979function_trace=false 980function_trace_start=0 981iewToCommitDelay=1 --- 48 unchanged lines hidden (view full) --- 1030 1031[system.cpu2.branchPred] 1032type=BranchPredictor 1033BTBEntries=4096 1034BTBTagSize=16 1035RASSize=16 1036choiceCtrBits=2 1037choicePredictorSize=8192 | 1093fetchToDecodeDelay=1 1094fetchTrapLatency=1 1095fetchWidth=8 1096forwardComSize=5 1097fuPool=system.cpu2.fuPool 1098function_trace=false 1099function_trace_start=0 1100iewToCommitDelay=1 --- 48 unchanged lines hidden (view full) --- 1149 1150[system.cpu2.branchPred] 1151type=BranchPredictor 1152BTBEntries=4096 1153BTBTagSize=16 1154RASSize=16 1155choiceCtrBits=2 1156choicePredictorSize=8192 |
| 1157eventq_index=0 |
|
| 1038globalCtrBits=2 1039globalPredictorSize=8192 1040instShiftAmt=2 1041localCtrBits=2 1042localHistoryTableSize=2048 1043localPredictorSize=2048 1044numThreads=1 1045predType=tournament 1046 1047[system.cpu2.dcache] 1048type=BaseCache 1049children=tags 1050addr_ranges=0:18446744073709551615 1051assoc=4 1052clk_domain=system.cpu_clk_domain | 1158globalCtrBits=2 1159globalPredictorSize=8192 1160instShiftAmt=2 1161localCtrBits=2 1162localHistoryTableSize=2048 1163localPredictorSize=2048 1164numThreads=1 1165predType=tournament 1166 1167[system.cpu2.dcache] 1168type=BaseCache 1169children=tags 1170addr_ranges=0:18446744073709551615 1171assoc=4 1172clk_domain=system.cpu_clk_domain |
| 1173eventq_index=0 |
|
| 1053forward_snoops=true 1054hit_latency=2 1055is_top_level=true 1056max_miss_count=0 1057mshrs=4 1058prefetch_on_access=false 1059prefetcher=Null 1060response_latency=2 --- 6 unchanged lines hidden (view full) --- 1067cpu_side=system.cpu2.dcache_port 1068mem_side=system.toL2Bus.slave[5] 1069 1070[system.cpu2.dcache.tags] 1071type=LRU 1072assoc=4 1073block_size=64 1074clk_domain=system.cpu_clk_domain | 1174forward_snoops=true 1175hit_latency=2 1176is_top_level=true 1177max_miss_count=0 1178mshrs=4 1179prefetch_on_access=false 1180prefetcher=Null 1181response_latency=2 --- 6 unchanged lines hidden (view full) --- 1188cpu_side=system.cpu2.dcache_port 1189mem_side=system.toL2Bus.slave[5] 1190 1191[system.cpu2.dcache.tags] 1192type=LRU 1193assoc=4 1194block_size=64 1195clk_domain=system.cpu_clk_domain |
| 1196eventq_index=0 |
|
| 1075hit_latency=2 1076size=32768 1077 1078[system.cpu2.dtb] 1079type=SparcTLB | 1197hit_latency=2 1198size=32768 1199 1200[system.cpu2.dtb] 1201type=SparcTLB |
| 1202eventq_index=0 |
|
| 1080size=64 1081 1082[system.cpu2.fuPool] 1083type=FUPool 1084children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1085FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 | 1203size=64 1204 1205[system.cpu2.fuPool] 1206type=FUPool 1207children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1208FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 |
| 1209eventq_index=0 |
|
| 1086 1087[system.cpu2.fuPool.FUList0] 1088type=FUDesc 1089children=opList 1090count=6 | 1210 1211[system.cpu2.fuPool.FUList0] 1212type=FUDesc 1213children=opList 1214count=6 |
| 1215eventq_index=0 |
|
| 1091opList=system.cpu2.fuPool.FUList0.opList 1092 1093[system.cpu2.fuPool.FUList0.opList] 1094type=OpDesc | 1216opList=system.cpu2.fuPool.FUList0.opList 1217 1218[system.cpu2.fuPool.FUList0.opList] 1219type=OpDesc |
| 1220eventq_index=0 |
|
| 1095issueLat=1 1096opClass=IntAlu 1097opLat=1 1098 1099[system.cpu2.fuPool.FUList1] 1100type=FUDesc 1101children=opList0 opList1 1102count=2 | 1221issueLat=1 1222opClass=IntAlu 1223opLat=1 1224 1225[system.cpu2.fuPool.FUList1] 1226type=FUDesc 1227children=opList0 opList1 1228count=2 |
| 1229eventq_index=0 |
|
| 1103opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 1104 1105[system.cpu2.fuPool.FUList1.opList0] 1106type=OpDesc | 1230opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 1231 1232[system.cpu2.fuPool.FUList1.opList0] 1233type=OpDesc |
| 1234eventq_index=0 |
|
| 1107issueLat=1 1108opClass=IntMult 1109opLat=3 1110 1111[system.cpu2.fuPool.FUList1.opList1] 1112type=OpDesc | 1235issueLat=1 1236opClass=IntMult 1237opLat=3 1238 1239[system.cpu2.fuPool.FUList1.opList1] 1240type=OpDesc |
| 1241eventq_index=0 |
|
| 1113issueLat=19 1114opClass=IntDiv 1115opLat=20 1116 1117[system.cpu2.fuPool.FUList2] 1118type=FUDesc 1119children=opList0 opList1 opList2 1120count=4 | 1242issueLat=19 1243opClass=IntDiv 1244opLat=20 1245 1246[system.cpu2.fuPool.FUList2] 1247type=FUDesc 1248children=opList0 opList1 opList2 1249count=4 |
| 1250eventq_index=0 |
|
| 1121opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 1122 1123[system.cpu2.fuPool.FUList2.opList0] 1124type=OpDesc | 1251opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 1252 1253[system.cpu2.fuPool.FUList2.opList0] 1254type=OpDesc |
| 1255eventq_index=0 |
|
| 1125issueLat=1 1126opClass=FloatAdd 1127opLat=2 1128 1129[system.cpu2.fuPool.FUList2.opList1] 1130type=OpDesc | 1256issueLat=1 1257opClass=FloatAdd 1258opLat=2 1259 1260[system.cpu2.fuPool.FUList2.opList1] 1261type=OpDesc |
| 1262eventq_index=0 |
|
| 1131issueLat=1 1132opClass=FloatCmp 1133opLat=2 1134 1135[system.cpu2.fuPool.FUList2.opList2] 1136type=OpDesc | 1263issueLat=1 1264opClass=FloatCmp 1265opLat=2 1266 1267[system.cpu2.fuPool.FUList2.opList2] 1268type=OpDesc |
| 1269eventq_index=0 |
|
| 1137issueLat=1 1138opClass=FloatCvt 1139opLat=2 1140 1141[system.cpu2.fuPool.FUList3] 1142type=FUDesc 1143children=opList0 opList1 opList2 1144count=2 | 1270issueLat=1 1271opClass=FloatCvt 1272opLat=2 1273 1274[system.cpu2.fuPool.FUList3] 1275type=FUDesc 1276children=opList0 opList1 opList2 1277count=2 |
| 1278eventq_index=0 |
|
| 1145opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 1146 1147[system.cpu2.fuPool.FUList3.opList0] 1148type=OpDesc | 1279opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 1280 1281[system.cpu2.fuPool.FUList3.opList0] 1282type=OpDesc |
| 1283eventq_index=0 |
|
| 1149issueLat=1 1150opClass=FloatMult 1151opLat=4 1152 1153[system.cpu2.fuPool.FUList3.opList1] 1154type=OpDesc | 1284issueLat=1 1285opClass=FloatMult 1286opLat=4 1287 1288[system.cpu2.fuPool.FUList3.opList1] 1289type=OpDesc |
| 1290eventq_index=0 |
|
| 1155issueLat=12 1156opClass=FloatDiv 1157opLat=12 1158 1159[system.cpu2.fuPool.FUList3.opList2] 1160type=OpDesc | 1291issueLat=12 1292opClass=FloatDiv 1293opLat=12 1294 1295[system.cpu2.fuPool.FUList3.opList2] 1296type=OpDesc |
| 1297eventq_index=0 |
|
| 1161issueLat=24 1162opClass=FloatSqrt 1163opLat=24 1164 1165[system.cpu2.fuPool.FUList4] 1166type=FUDesc 1167children=opList 1168count=0 | 1298issueLat=24 1299opClass=FloatSqrt 1300opLat=24 1301 1302[system.cpu2.fuPool.FUList4] 1303type=FUDesc 1304children=opList 1305count=0 |
| 1306eventq_index=0 |
|
| 1169opList=system.cpu2.fuPool.FUList4.opList 1170 1171[system.cpu2.fuPool.FUList4.opList] 1172type=OpDesc | 1307opList=system.cpu2.fuPool.FUList4.opList 1308 1309[system.cpu2.fuPool.FUList4.opList] 1310type=OpDesc |
| 1311eventq_index=0 |
|
| 1173issueLat=1 1174opClass=MemRead 1175opLat=1 1176 1177[system.cpu2.fuPool.FUList5] 1178type=FUDesc 1179children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1180count=4 | 1312issueLat=1 1313opClass=MemRead 1314opLat=1 1315 1316[system.cpu2.fuPool.FUList5] 1317type=FUDesc 1318children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1319count=4 |
| 1320eventq_index=0 |
|
| 1181opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 1182 1183[system.cpu2.fuPool.FUList5.opList00] 1184type=OpDesc | 1321opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 1322 1323[system.cpu2.fuPool.FUList5.opList00] 1324type=OpDesc |
| 1325eventq_index=0 |
|
| 1185issueLat=1 1186opClass=SimdAdd 1187opLat=1 1188 1189[system.cpu2.fuPool.FUList5.opList01] 1190type=OpDesc | 1326issueLat=1 1327opClass=SimdAdd 1328opLat=1 1329 1330[system.cpu2.fuPool.FUList5.opList01] 1331type=OpDesc |
| 1332eventq_index=0 |
|
| 1191issueLat=1 1192opClass=SimdAddAcc 1193opLat=1 1194 1195[system.cpu2.fuPool.FUList5.opList02] 1196type=OpDesc | 1333issueLat=1 1334opClass=SimdAddAcc 1335opLat=1 1336 1337[system.cpu2.fuPool.FUList5.opList02] 1338type=OpDesc |
| 1339eventq_index=0 |
|
| 1197issueLat=1 1198opClass=SimdAlu 1199opLat=1 1200 1201[system.cpu2.fuPool.FUList5.opList03] 1202type=OpDesc | 1340issueLat=1 1341opClass=SimdAlu 1342opLat=1 1343 1344[system.cpu2.fuPool.FUList5.opList03] 1345type=OpDesc |
| 1346eventq_index=0 |
|
| 1203issueLat=1 1204opClass=SimdCmp 1205opLat=1 1206 1207[system.cpu2.fuPool.FUList5.opList04] 1208type=OpDesc | 1347issueLat=1 1348opClass=SimdCmp 1349opLat=1 1350 1351[system.cpu2.fuPool.FUList5.opList04] 1352type=OpDesc |
| 1353eventq_index=0 |
|
| 1209issueLat=1 1210opClass=SimdCvt 1211opLat=1 1212 1213[system.cpu2.fuPool.FUList5.opList05] 1214type=OpDesc | 1354issueLat=1 1355opClass=SimdCvt 1356opLat=1 1357 1358[system.cpu2.fuPool.FUList5.opList05] 1359type=OpDesc |
| 1360eventq_index=0 |
|
| 1215issueLat=1 1216opClass=SimdMisc 1217opLat=1 1218 1219[system.cpu2.fuPool.FUList5.opList06] 1220type=OpDesc | 1361issueLat=1 1362opClass=SimdMisc 1363opLat=1 1364 1365[system.cpu2.fuPool.FUList5.opList06] 1366type=OpDesc |
| 1367eventq_index=0 |
|
| 1221issueLat=1 1222opClass=SimdMult 1223opLat=1 1224 1225[system.cpu2.fuPool.FUList5.opList07] 1226type=OpDesc | 1368issueLat=1 1369opClass=SimdMult 1370opLat=1 1371 1372[system.cpu2.fuPool.FUList5.opList07] 1373type=OpDesc |
| 1374eventq_index=0 |
|
| 1227issueLat=1 1228opClass=SimdMultAcc 1229opLat=1 1230 1231[system.cpu2.fuPool.FUList5.opList08] 1232type=OpDesc | 1375issueLat=1 1376opClass=SimdMultAcc 1377opLat=1 1378 1379[system.cpu2.fuPool.FUList5.opList08] 1380type=OpDesc |
| 1381eventq_index=0 |
|
| 1233issueLat=1 1234opClass=SimdShift 1235opLat=1 1236 1237[system.cpu2.fuPool.FUList5.opList09] 1238type=OpDesc | 1382issueLat=1 1383opClass=SimdShift 1384opLat=1 1385 1386[system.cpu2.fuPool.FUList5.opList09] 1387type=OpDesc |
| 1388eventq_index=0 |
|
| 1239issueLat=1 1240opClass=SimdShiftAcc 1241opLat=1 1242 1243[system.cpu2.fuPool.FUList5.opList10] 1244type=OpDesc | 1389issueLat=1 1390opClass=SimdShiftAcc 1391opLat=1 1392 1393[system.cpu2.fuPool.FUList5.opList10] 1394type=OpDesc |
| 1395eventq_index=0 |
|
| 1245issueLat=1 1246opClass=SimdSqrt 1247opLat=1 1248 1249[system.cpu2.fuPool.FUList5.opList11] 1250type=OpDesc | 1396issueLat=1 1397opClass=SimdSqrt 1398opLat=1 1399 1400[system.cpu2.fuPool.FUList5.opList11] 1401type=OpDesc |
| 1402eventq_index=0 |
|
| 1251issueLat=1 1252opClass=SimdFloatAdd 1253opLat=1 1254 1255[system.cpu2.fuPool.FUList5.opList12] 1256type=OpDesc | 1403issueLat=1 1404opClass=SimdFloatAdd 1405opLat=1 1406 1407[system.cpu2.fuPool.FUList5.opList12] 1408type=OpDesc |
| 1409eventq_index=0 |
|
| 1257issueLat=1 1258opClass=SimdFloatAlu 1259opLat=1 1260 1261[system.cpu2.fuPool.FUList5.opList13] 1262type=OpDesc | 1410issueLat=1 1411opClass=SimdFloatAlu 1412opLat=1 1413 1414[system.cpu2.fuPool.FUList5.opList13] 1415type=OpDesc |
| 1416eventq_index=0 |
|
| 1263issueLat=1 1264opClass=SimdFloatCmp 1265opLat=1 1266 1267[system.cpu2.fuPool.FUList5.opList14] 1268type=OpDesc | 1417issueLat=1 1418opClass=SimdFloatCmp 1419opLat=1 1420 1421[system.cpu2.fuPool.FUList5.opList14] 1422type=OpDesc |
| 1423eventq_index=0 |
|
| 1269issueLat=1 1270opClass=SimdFloatCvt 1271opLat=1 1272 1273[system.cpu2.fuPool.FUList5.opList15] 1274type=OpDesc | 1424issueLat=1 1425opClass=SimdFloatCvt 1426opLat=1 1427 1428[system.cpu2.fuPool.FUList5.opList15] 1429type=OpDesc |
| 1430eventq_index=0 |
|
| 1275issueLat=1 1276opClass=SimdFloatDiv 1277opLat=1 1278 1279[system.cpu2.fuPool.FUList5.opList16] 1280type=OpDesc | 1431issueLat=1 1432opClass=SimdFloatDiv 1433opLat=1 1434 1435[system.cpu2.fuPool.FUList5.opList16] 1436type=OpDesc |
| 1437eventq_index=0 |
|
| 1281issueLat=1 1282opClass=SimdFloatMisc 1283opLat=1 1284 1285[system.cpu2.fuPool.FUList5.opList17] 1286type=OpDesc | 1438issueLat=1 1439opClass=SimdFloatMisc 1440opLat=1 1441 1442[system.cpu2.fuPool.FUList5.opList17] 1443type=OpDesc |
| 1444eventq_index=0 |
|
| 1287issueLat=1 1288opClass=SimdFloatMult 1289opLat=1 1290 1291[system.cpu2.fuPool.FUList5.opList18] 1292type=OpDesc | 1445issueLat=1 1446opClass=SimdFloatMult 1447opLat=1 1448 1449[system.cpu2.fuPool.FUList5.opList18] 1450type=OpDesc |
| 1451eventq_index=0 |
|
| 1293issueLat=1 1294opClass=SimdFloatMultAcc 1295opLat=1 1296 1297[system.cpu2.fuPool.FUList5.opList19] 1298type=OpDesc | 1452issueLat=1 1453opClass=SimdFloatMultAcc 1454opLat=1 1455 1456[system.cpu2.fuPool.FUList5.opList19] 1457type=OpDesc |
| 1458eventq_index=0 |
|
| 1299issueLat=1 1300opClass=SimdFloatSqrt 1301opLat=1 1302 1303[system.cpu2.fuPool.FUList6] 1304type=FUDesc 1305children=opList 1306count=0 | 1459issueLat=1 1460opClass=SimdFloatSqrt 1461opLat=1 1462 1463[system.cpu2.fuPool.FUList6] 1464type=FUDesc 1465children=opList 1466count=0 |
| 1467eventq_index=0 |
|
| 1307opList=system.cpu2.fuPool.FUList6.opList 1308 1309[system.cpu2.fuPool.FUList6.opList] 1310type=OpDesc | 1468opList=system.cpu2.fuPool.FUList6.opList 1469 1470[system.cpu2.fuPool.FUList6.opList] 1471type=OpDesc |
| 1472eventq_index=0 |
|
| 1311issueLat=1 1312opClass=MemWrite 1313opLat=1 1314 1315[system.cpu2.fuPool.FUList7] 1316type=FUDesc 1317children=opList0 opList1 1318count=4 | 1473issueLat=1 1474opClass=MemWrite 1475opLat=1 1476 1477[system.cpu2.fuPool.FUList7] 1478type=FUDesc 1479children=opList0 opList1 1480count=4 |
| 1481eventq_index=0 |
|
| 1319opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 1320 1321[system.cpu2.fuPool.FUList7.opList0] 1322type=OpDesc | 1482opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 1483 1484[system.cpu2.fuPool.FUList7.opList0] 1485type=OpDesc |
| 1486eventq_index=0 |
|
| 1323issueLat=1 1324opClass=MemRead 1325opLat=1 1326 1327[system.cpu2.fuPool.FUList7.opList1] 1328type=OpDesc | 1487issueLat=1 1488opClass=MemRead 1489opLat=1 1490 1491[system.cpu2.fuPool.FUList7.opList1] 1492type=OpDesc |
| 1493eventq_index=0 |
|
| 1329issueLat=1 1330opClass=MemWrite 1331opLat=1 1332 1333[system.cpu2.fuPool.FUList8] 1334type=FUDesc 1335children=opList 1336count=1 | 1494issueLat=1 1495opClass=MemWrite 1496opLat=1 1497 1498[system.cpu2.fuPool.FUList8] 1499type=FUDesc 1500children=opList 1501count=1 |
| 1502eventq_index=0 |
|
| 1337opList=system.cpu2.fuPool.FUList8.opList 1338 1339[system.cpu2.fuPool.FUList8.opList] 1340type=OpDesc | 1503opList=system.cpu2.fuPool.FUList8.opList 1504 1505[system.cpu2.fuPool.FUList8.opList] 1506type=OpDesc |
| 1507eventq_index=0 |
|
| 1341issueLat=3 1342opClass=IprAccess 1343opLat=3 1344 1345[system.cpu2.icache] 1346type=BaseCache 1347children=tags 1348addr_ranges=0:18446744073709551615 1349assoc=1 1350clk_domain=system.cpu_clk_domain | 1508issueLat=3 1509opClass=IprAccess 1510opLat=3 1511 1512[system.cpu2.icache] 1513type=BaseCache 1514children=tags 1515addr_ranges=0:18446744073709551615 1516assoc=1 1517clk_domain=system.cpu_clk_domain |
| 1518eventq_index=0 |
|
| 1351forward_snoops=true 1352hit_latency=2 1353is_top_level=true 1354max_miss_count=0 1355mshrs=4 1356prefetch_on_access=false 1357prefetcher=Null 1358response_latency=2 --- 6 unchanged lines hidden (view full) --- 1365cpu_side=system.cpu2.icache_port 1366mem_side=system.toL2Bus.slave[4] 1367 1368[system.cpu2.icache.tags] 1369type=LRU 1370assoc=1 1371block_size=64 1372clk_domain=system.cpu_clk_domain | 1519forward_snoops=true 1520hit_latency=2 1521is_top_level=true 1522max_miss_count=0 1523mshrs=4 1524prefetch_on_access=false 1525prefetcher=Null 1526response_latency=2 --- 6 unchanged lines hidden (view full) --- 1533cpu_side=system.cpu2.icache_port 1534mem_side=system.toL2Bus.slave[4] 1535 1536[system.cpu2.icache.tags] 1537type=LRU 1538assoc=1 1539block_size=64 1540clk_domain=system.cpu_clk_domain |
| 1541eventq_index=0 |
|
| 1373hit_latency=2 1374size=32768 1375 1376[system.cpu2.interrupts] 1377type=SparcInterrupts | 1542hit_latency=2 1543size=32768 1544 1545[system.cpu2.interrupts] 1546type=SparcInterrupts |
| 1547eventq_index=0 |
|
| 1378 1379[system.cpu2.isa] 1380type=SparcISA | 1548 1549[system.cpu2.isa] 1550type=SparcISA |
| 1551eventq_index=0 |
|
| 1381 1382[system.cpu2.itb] 1383type=SparcTLB | 1552 1553[system.cpu2.itb] 1554type=SparcTLB |
| 1555eventq_index=0 |
|
| 1384size=64 1385 1386[system.cpu2.tracer] 1387type=ExeTracer | 1556size=64 1557 1558[system.cpu2.tracer] 1559type=ExeTracer |
| 1560eventq_index=0 |
|
| 1388 1389[system.cpu3] 1390type=DerivO3CPU 1391children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1392LFSTSize=1024 1393LQEntries=32 1394LSQCheckLoads=true 1395LSQDepCheckShift=4 --- 14 unchanged lines hidden (view full) --- 1410decodeToFetchDelay=1 1411decodeToRenameDelay=1 1412decodeWidth=8 1413dispatchWidth=8 1414do_checkpoint_insts=true 1415do_quiesce=true 1416do_statistics_insts=true 1417dtb=system.cpu3.dtb | 1561 1562[system.cpu3] 1563type=DerivO3CPU 1564children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1565LFSTSize=1024 1566LQEntries=32 1567LSQCheckLoads=true 1568LSQDepCheckShift=4 --- 14 unchanged lines hidden (view full) --- 1583decodeToFetchDelay=1 1584decodeToRenameDelay=1 1585decodeWidth=8 1586dispatchWidth=8 1587do_checkpoint_insts=true 1588do_quiesce=true 1589do_statistics_insts=true 1590dtb=system.cpu3.dtb |
| 1591eventq_index=0 1592fetchBufferSize=64 |
|
| 1418fetchToDecodeDelay=1 1419fetchTrapLatency=1 1420fetchWidth=8 1421forwardComSize=5 1422fuPool=system.cpu3.fuPool 1423function_trace=false 1424function_trace_start=0 1425iewToCommitDelay=1 --- 48 unchanged lines hidden (view full) --- 1474 1475[system.cpu3.branchPred] 1476type=BranchPredictor 1477BTBEntries=4096 1478BTBTagSize=16 1479RASSize=16 1480choiceCtrBits=2 1481choicePredictorSize=8192 | 1593fetchToDecodeDelay=1 1594fetchTrapLatency=1 1595fetchWidth=8 1596forwardComSize=5 1597fuPool=system.cpu3.fuPool 1598function_trace=false 1599function_trace_start=0 1600iewToCommitDelay=1 --- 48 unchanged lines hidden (view full) --- 1649 1650[system.cpu3.branchPred] 1651type=BranchPredictor 1652BTBEntries=4096 1653BTBTagSize=16 1654RASSize=16 1655choiceCtrBits=2 1656choicePredictorSize=8192 |
| 1657eventq_index=0 |
|
| 1482globalCtrBits=2 1483globalPredictorSize=8192 1484instShiftAmt=2 1485localCtrBits=2 1486localHistoryTableSize=2048 1487localPredictorSize=2048 1488numThreads=1 1489predType=tournament 1490 1491[system.cpu3.dcache] 1492type=BaseCache 1493children=tags 1494addr_ranges=0:18446744073709551615 1495assoc=4 1496clk_domain=system.cpu_clk_domain | 1658globalCtrBits=2 1659globalPredictorSize=8192 1660instShiftAmt=2 1661localCtrBits=2 1662localHistoryTableSize=2048 1663localPredictorSize=2048 1664numThreads=1 1665predType=tournament 1666 1667[system.cpu3.dcache] 1668type=BaseCache 1669children=tags 1670addr_ranges=0:18446744073709551615 1671assoc=4 1672clk_domain=system.cpu_clk_domain |
| 1673eventq_index=0 |
|
| 1497forward_snoops=true 1498hit_latency=2 1499is_top_level=true 1500max_miss_count=0 1501mshrs=4 1502prefetch_on_access=false 1503prefetcher=Null 1504response_latency=2 --- 6 unchanged lines hidden (view full) --- 1511cpu_side=system.cpu3.dcache_port 1512mem_side=system.toL2Bus.slave[7] 1513 1514[system.cpu3.dcache.tags] 1515type=LRU 1516assoc=4 1517block_size=64 1518clk_domain=system.cpu_clk_domain | 1674forward_snoops=true 1675hit_latency=2 1676is_top_level=true 1677max_miss_count=0 1678mshrs=4 1679prefetch_on_access=false 1680prefetcher=Null 1681response_latency=2 --- 6 unchanged lines hidden (view full) --- 1688cpu_side=system.cpu3.dcache_port 1689mem_side=system.toL2Bus.slave[7] 1690 1691[system.cpu3.dcache.tags] 1692type=LRU 1693assoc=4 1694block_size=64 1695clk_domain=system.cpu_clk_domain |
| 1696eventq_index=0 |
|
| 1519hit_latency=2 1520size=32768 1521 1522[system.cpu3.dtb] 1523type=SparcTLB | 1697hit_latency=2 1698size=32768 1699 1700[system.cpu3.dtb] 1701type=SparcTLB |
| 1702eventq_index=0 |
|
| 1524size=64 1525 1526[system.cpu3.fuPool] 1527type=FUPool 1528children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1529FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 | 1703size=64 1704 1705[system.cpu3.fuPool] 1706type=FUPool 1707children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1708FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 |
| 1709eventq_index=0 |
|
| 1530 1531[system.cpu3.fuPool.FUList0] 1532type=FUDesc 1533children=opList 1534count=6 | 1710 1711[system.cpu3.fuPool.FUList0] 1712type=FUDesc 1713children=opList 1714count=6 |
| 1715eventq_index=0 |
|
| 1535opList=system.cpu3.fuPool.FUList0.opList 1536 1537[system.cpu3.fuPool.FUList0.opList] 1538type=OpDesc | 1716opList=system.cpu3.fuPool.FUList0.opList 1717 1718[system.cpu3.fuPool.FUList0.opList] 1719type=OpDesc |
| 1720eventq_index=0 |
|
| 1539issueLat=1 1540opClass=IntAlu 1541opLat=1 1542 1543[system.cpu3.fuPool.FUList1] 1544type=FUDesc 1545children=opList0 opList1 1546count=2 | 1721issueLat=1 1722opClass=IntAlu 1723opLat=1 1724 1725[system.cpu3.fuPool.FUList1] 1726type=FUDesc 1727children=opList0 opList1 1728count=2 |
| 1729eventq_index=0 |
|
| 1547opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 1548 1549[system.cpu3.fuPool.FUList1.opList0] 1550type=OpDesc | 1730opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 1731 1732[system.cpu3.fuPool.FUList1.opList0] 1733type=OpDesc |
| 1734eventq_index=0 |
|
| 1551issueLat=1 1552opClass=IntMult 1553opLat=3 1554 1555[system.cpu3.fuPool.FUList1.opList1] 1556type=OpDesc | 1735issueLat=1 1736opClass=IntMult 1737opLat=3 1738 1739[system.cpu3.fuPool.FUList1.opList1] 1740type=OpDesc |
| 1741eventq_index=0 |
|
| 1557issueLat=19 1558opClass=IntDiv 1559opLat=20 1560 1561[system.cpu3.fuPool.FUList2] 1562type=FUDesc 1563children=opList0 opList1 opList2 1564count=4 | 1742issueLat=19 1743opClass=IntDiv 1744opLat=20 1745 1746[system.cpu3.fuPool.FUList2] 1747type=FUDesc 1748children=opList0 opList1 opList2 1749count=4 |
| 1750eventq_index=0 |
|
| 1565opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 1566 1567[system.cpu3.fuPool.FUList2.opList0] 1568type=OpDesc | 1751opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 1752 1753[system.cpu3.fuPool.FUList2.opList0] 1754type=OpDesc |
| 1755eventq_index=0 |
|
| 1569issueLat=1 1570opClass=FloatAdd 1571opLat=2 1572 1573[system.cpu3.fuPool.FUList2.opList1] 1574type=OpDesc | 1756issueLat=1 1757opClass=FloatAdd 1758opLat=2 1759 1760[system.cpu3.fuPool.FUList2.opList1] 1761type=OpDesc |
| 1762eventq_index=0 |
|
| 1575issueLat=1 1576opClass=FloatCmp 1577opLat=2 1578 1579[system.cpu3.fuPool.FUList2.opList2] 1580type=OpDesc | 1763issueLat=1 1764opClass=FloatCmp 1765opLat=2 1766 1767[system.cpu3.fuPool.FUList2.opList2] 1768type=OpDesc |
| 1769eventq_index=0 |
|
| 1581issueLat=1 1582opClass=FloatCvt 1583opLat=2 1584 1585[system.cpu3.fuPool.FUList3] 1586type=FUDesc 1587children=opList0 opList1 opList2 1588count=2 | 1770issueLat=1 1771opClass=FloatCvt 1772opLat=2 1773 1774[system.cpu3.fuPool.FUList3] 1775type=FUDesc 1776children=opList0 opList1 opList2 1777count=2 |
| 1778eventq_index=0 |
|
| 1589opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 1590 1591[system.cpu3.fuPool.FUList3.opList0] 1592type=OpDesc | 1779opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 1780 1781[system.cpu3.fuPool.FUList3.opList0] 1782type=OpDesc |
| 1783eventq_index=0 |
|
| 1593issueLat=1 1594opClass=FloatMult 1595opLat=4 1596 1597[system.cpu3.fuPool.FUList3.opList1] 1598type=OpDesc | 1784issueLat=1 1785opClass=FloatMult 1786opLat=4 1787 1788[system.cpu3.fuPool.FUList3.opList1] 1789type=OpDesc |
| 1790eventq_index=0 |
|
| 1599issueLat=12 1600opClass=FloatDiv 1601opLat=12 1602 1603[system.cpu3.fuPool.FUList3.opList2] 1604type=OpDesc | 1791issueLat=12 1792opClass=FloatDiv 1793opLat=12 1794 1795[system.cpu3.fuPool.FUList3.opList2] 1796type=OpDesc |
| 1797eventq_index=0 |
|
| 1605issueLat=24 1606opClass=FloatSqrt 1607opLat=24 1608 1609[system.cpu3.fuPool.FUList4] 1610type=FUDesc 1611children=opList 1612count=0 | 1798issueLat=24 1799opClass=FloatSqrt 1800opLat=24 1801 1802[system.cpu3.fuPool.FUList4] 1803type=FUDesc 1804children=opList 1805count=0 |
| 1806eventq_index=0 |
|
| 1613opList=system.cpu3.fuPool.FUList4.opList 1614 1615[system.cpu3.fuPool.FUList4.opList] 1616type=OpDesc | 1807opList=system.cpu3.fuPool.FUList4.opList 1808 1809[system.cpu3.fuPool.FUList4.opList] 1810type=OpDesc |
| 1811eventq_index=0 |
|
| 1617issueLat=1 1618opClass=MemRead 1619opLat=1 1620 1621[system.cpu3.fuPool.FUList5] 1622type=FUDesc 1623children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1624count=4 | 1812issueLat=1 1813opClass=MemRead 1814opLat=1 1815 1816[system.cpu3.fuPool.FUList5] 1817type=FUDesc 1818children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1819count=4 |
| 1820eventq_index=0 |
|
| 1625opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 1626 1627[system.cpu3.fuPool.FUList5.opList00] 1628type=OpDesc | 1821opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 1822 1823[system.cpu3.fuPool.FUList5.opList00] 1824type=OpDesc |
| 1825eventq_index=0 |
|
| 1629issueLat=1 1630opClass=SimdAdd 1631opLat=1 1632 1633[system.cpu3.fuPool.FUList5.opList01] 1634type=OpDesc | 1826issueLat=1 1827opClass=SimdAdd 1828opLat=1 1829 1830[system.cpu3.fuPool.FUList5.opList01] 1831type=OpDesc |
| 1832eventq_index=0 |
|
| 1635issueLat=1 1636opClass=SimdAddAcc 1637opLat=1 1638 1639[system.cpu3.fuPool.FUList5.opList02] 1640type=OpDesc | 1833issueLat=1 1834opClass=SimdAddAcc 1835opLat=1 1836 1837[system.cpu3.fuPool.FUList5.opList02] 1838type=OpDesc |
| 1839eventq_index=0 |
|
| 1641issueLat=1 1642opClass=SimdAlu 1643opLat=1 1644 1645[system.cpu3.fuPool.FUList5.opList03] 1646type=OpDesc | 1840issueLat=1 1841opClass=SimdAlu 1842opLat=1 1843 1844[system.cpu3.fuPool.FUList5.opList03] 1845type=OpDesc |
| 1846eventq_index=0 |
|
| 1647issueLat=1 1648opClass=SimdCmp 1649opLat=1 1650 1651[system.cpu3.fuPool.FUList5.opList04] 1652type=OpDesc | 1847issueLat=1 1848opClass=SimdCmp 1849opLat=1 1850 1851[system.cpu3.fuPool.FUList5.opList04] 1852type=OpDesc |
| 1853eventq_index=0 |
|
| 1653issueLat=1 1654opClass=SimdCvt 1655opLat=1 1656 1657[system.cpu3.fuPool.FUList5.opList05] 1658type=OpDesc | 1854issueLat=1 1855opClass=SimdCvt 1856opLat=1 1857 1858[system.cpu3.fuPool.FUList5.opList05] 1859type=OpDesc |
| 1860eventq_index=0 |
|
| 1659issueLat=1 1660opClass=SimdMisc 1661opLat=1 1662 1663[system.cpu3.fuPool.FUList5.opList06] 1664type=OpDesc | 1861issueLat=1 1862opClass=SimdMisc 1863opLat=1 1864 1865[system.cpu3.fuPool.FUList5.opList06] 1866type=OpDesc |
| 1867eventq_index=0 |
|
| 1665issueLat=1 1666opClass=SimdMult 1667opLat=1 1668 1669[system.cpu3.fuPool.FUList5.opList07] 1670type=OpDesc | 1868issueLat=1 1869opClass=SimdMult 1870opLat=1 1871 1872[system.cpu3.fuPool.FUList5.opList07] 1873type=OpDesc |
| 1874eventq_index=0 |
|
| 1671issueLat=1 1672opClass=SimdMultAcc 1673opLat=1 1674 1675[system.cpu3.fuPool.FUList5.opList08] 1676type=OpDesc | 1875issueLat=1 1876opClass=SimdMultAcc 1877opLat=1 1878 1879[system.cpu3.fuPool.FUList5.opList08] 1880type=OpDesc |
| 1881eventq_index=0 |
|
| 1677issueLat=1 1678opClass=SimdShift 1679opLat=1 1680 1681[system.cpu3.fuPool.FUList5.opList09] 1682type=OpDesc | 1882issueLat=1 1883opClass=SimdShift 1884opLat=1 1885 1886[system.cpu3.fuPool.FUList5.opList09] 1887type=OpDesc |
| 1888eventq_index=0 |
|
| 1683issueLat=1 1684opClass=SimdShiftAcc 1685opLat=1 1686 1687[system.cpu3.fuPool.FUList5.opList10] 1688type=OpDesc | 1889issueLat=1 1890opClass=SimdShiftAcc 1891opLat=1 1892 1893[system.cpu3.fuPool.FUList5.opList10] 1894type=OpDesc |
| 1895eventq_index=0 |
|
| 1689issueLat=1 1690opClass=SimdSqrt 1691opLat=1 1692 1693[system.cpu3.fuPool.FUList5.opList11] 1694type=OpDesc | 1896issueLat=1 1897opClass=SimdSqrt 1898opLat=1 1899 1900[system.cpu3.fuPool.FUList5.opList11] 1901type=OpDesc |
| 1902eventq_index=0 |
|
| 1695issueLat=1 1696opClass=SimdFloatAdd 1697opLat=1 1698 1699[system.cpu3.fuPool.FUList5.opList12] 1700type=OpDesc | 1903issueLat=1 1904opClass=SimdFloatAdd 1905opLat=1 1906 1907[system.cpu3.fuPool.FUList5.opList12] 1908type=OpDesc |
| 1909eventq_index=0 |
|
| 1701issueLat=1 1702opClass=SimdFloatAlu 1703opLat=1 1704 1705[system.cpu3.fuPool.FUList5.opList13] 1706type=OpDesc | 1910issueLat=1 1911opClass=SimdFloatAlu 1912opLat=1 1913 1914[system.cpu3.fuPool.FUList5.opList13] 1915type=OpDesc |
| 1916eventq_index=0 |
|
| 1707issueLat=1 1708opClass=SimdFloatCmp 1709opLat=1 1710 1711[system.cpu3.fuPool.FUList5.opList14] 1712type=OpDesc | 1917issueLat=1 1918opClass=SimdFloatCmp 1919opLat=1 1920 1921[system.cpu3.fuPool.FUList5.opList14] 1922type=OpDesc |
| 1923eventq_index=0 |
|
| 1713issueLat=1 1714opClass=SimdFloatCvt 1715opLat=1 1716 1717[system.cpu3.fuPool.FUList5.opList15] 1718type=OpDesc | 1924issueLat=1 1925opClass=SimdFloatCvt 1926opLat=1 1927 1928[system.cpu3.fuPool.FUList5.opList15] 1929type=OpDesc |
| 1930eventq_index=0 |
|
| 1719issueLat=1 1720opClass=SimdFloatDiv 1721opLat=1 1722 1723[system.cpu3.fuPool.FUList5.opList16] 1724type=OpDesc | 1931issueLat=1 1932opClass=SimdFloatDiv 1933opLat=1 1934 1935[system.cpu3.fuPool.FUList5.opList16] 1936type=OpDesc |
| 1937eventq_index=0 |
|
| 1725issueLat=1 1726opClass=SimdFloatMisc 1727opLat=1 1728 1729[system.cpu3.fuPool.FUList5.opList17] 1730type=OpDesc | 1938issueLat=1 1939opClass=SimdFloatMisc 1940opLat=1 1941 1942[system.cpu3.fuPool.FUList5.opList17] 1943type=OpDesc |
| 1944eventq_index=0 |
|
| 1731issueLat=1 1732opClass=SimdFloatMult 1733opLat=1 1734 1735[system.cpu3.fuPool.FUList5.opList18] 1736type=OpDesc | 1945issueLat=1 1946opClass=SimdFloatMult 1947opLat=1 1948 1949[system.cpu3.fuPool.FUList5.opList18] 1950type=OpDesc |
| 1951eventq_index=0 |
|
| 1737issueLat=1 1738opClass=SimdFloatMultAcc 1739opLat=1 1740 1741[system.cpu3.fuPool.FUList5.opList19] 1742type=OpDesc | 1952issueLat=1 1953opClass=SimdFloatMultAcc 1954opLat=1 1955 1956[system.cpu3.fuPool.FUList5.opList19] 1957type=OpDesc |
| 1958eventq_index=0 |
|
| 1743issueLat=1 1744opClass=SimdFloatSqrt 1745opLat=1 1746 1747[system.cpu3.fuPool.FUList6] 1748type=FUDesc 1749children=opList 1750count=0 | 1959issueLat=1 1960opClass=SimdFloatSqrt 1961opLat=1 1962 1963[system.cpu3.fuPool.FUList6] 1964type=FUDesc 1965children=opList 1966count=0 |
| 1967eventq_index=0 |
|
| 1751opList=system.cpu3.fuPool.FUList6.opList 1752 1753[system.cpu3.fuPool.FUList6.opList] 1754type=OpDesc | 1968opList=system.cpu3.fuPool.FUList6.opList 1969 1970[system.cpu3.fuPool.FUList6.opList] 1971type=OpDesc |
| 1972eventq_index=0 |
|
| 1755issueLat=1 1756opClass=MemWrite 1757opLat=1 1758 1759[system.cpu3.fuPool.FUList7] 1760type=FUDesc 1761children=opList0 opList1 1762count=4 | 1973issueLat=1 1974opClass=MemWrite 1975opLat=1 1976 1977[system.cpu3.fuPool.FUList7] 1978type=FUDesc 1979children=opList0 opList1 1980count=4 |
| 1981eventq_index=0 |
|
| 1763opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 1764 1765[system.cpu3.fuPool.FUList7.opList0] 1766type=OpDesc | 1982opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 1983 1984[system.cpu3.fuPool.FUList7.opList0] 1985type=OpDesc |
| 1986eventq_index=0 |
|
| 1767issueLat=1 1768opClass=MemRead 1769opLat=1 1770 1771[system.cpu3.fuPool.FUList7.opList1] 1772type=OpDesc | 1987issueLat=1 1988opClass=MemRead 1989opLat=1 1990 1991[system.cpu3.fuPool.FUList7.opList1] 1992type=OpDesc |
| 1993eventq_index=0 |
|
| 1773issueLat=1 1774opClass=MemWrite 1775opLat=1 1776 1777[system.cpu3.fuPool.FUList8] 1778type=FUDesc 1779children=opList 1780count=1 | 1994issueLat=1 1995opClass=MemWrite 1996opLat=1 1997 1998[system.cpu3.fuPool.FUList8] 1999type=FUDesc 2000children=opList 2001count=1 |
| 2002eventq_index=0 |
|
| 1781opList=system.cpu3.fuPool.FUList8.opList 1782 1783[system.cpu3.fuPool.FUList8.opList] 1784type=OpDesc | 2003opList=system.cpu3.fuPool.FUList8.opList 2004 2005[system.cpu3.fuPool.FUList8.opList] 2006type=OpDesc |
| 2007eventq_index=0 |
|
| 1785issueLat=3 1786opClass=IprAccess 1787opLat=3 1788 1789[system.cpu3.icache] 1790type=BaseCache 1791children=tags 1792addr_ranges=0:18446744073709551615 1793assoc=1 1794clk_domain=system.cpu_clk_domain | 2008issueLat=3 2009opClass=IprAccess 2010opLat=3 2011 2012[system.cpu3.icache] 2013type=BaseCache 2014children=tags 2015addr_ranges=0:18446744073709551615 2016assoc=1 2017clk_domain=system.cpu_clk_domain |
| 2018eventq_index=0 |
|
| 1795forward_snoops=true 1796hit_latency=2 1797is_top_level=true 1798max_miss_count=0 1799mshrs=4 1800prefetch_on_access=false 1801prefetcher=Null 1802response_latency=2 --- 6 unchanged lines hidden (view full) --- 1809cpu_side=system.cpu3.icache_port 1810mem_side=system.toL2Bus.slave[6] 1811 1812[system.cpu3.icache.tags] 1813type=LRU 1814assoc=1 1815block_size=64 1816clk_domain=system.cpu_clk_domain | 2019forward_snoops=true 2020hit_latency=2 2021is_top_level=true 2022max_miss_count=0 2023mshrs=4 2024prefetch_on_access=false 2025prefetcher=Null 2026response_latency=2 --- 6 unchanged lines hidden (view full) --- 2033cpu_side=system.cpu3.icache_port 2034mem_side=system.toL2Bus.slave[6] 2035 2036[system.cpu3.icache.tags] 2037type=LRU 2038assoc=1 2039block_size=64 2040clk_domain=system.cpu_clk_domain |
| 2041eventq_index=0 |
|
| 1817hit_latency=2 1818size=32768 1819 1820[system.cpu3.interrupts] 1821type=SparcInterrupts | 2042hit_latency=2 2043size=32768 2044 2045[system.cpu3.interrupts] 2046type=SparcInterrupts |
| 2047eventq_index=0 |
|
| 1822 1823[system.cpu3.isa] 1824type=SparcISA | 2048 2049[system.cpu3.isa] 2050type=SparcISA |
| 2051eventq_index=0 |
|
| 1825 1826[system.cpu3.itb] 1827type=SparcTLB | 2052 2053[system.cpu3.itb] 2054type=SparcTLB |
| 2055eventq_index=0 |
|
| 1828size=64 1829 1830[system.cpu3.tracer] 1831type=ExeTracer | 2056size=64 2057 2058[system.cpu3.tracer] 2059type=ExeTracer |
| 2060eventq_index=0 |
|
| 1832 1833[system.cpu_clk_domain] 1834type=SrcClockDomain 1835clock=500 | 2061 2062[system.cpu_clk_domain] 2063type=SrcClockDomain 2064clock=500 |
| 2065eventq_index=0 |
|
| 1836voltage_domain=system.voltage_domain 1837 1838[system.l2c] 1839type=BaseCache 1840children=tags 1841addr_ranges=0:18446744073709551615 1842assoc=8 1843clk_domain=system.cpu_clk_domain | 2066voltage_domain=system.voltage_domain 2067 2068[system.l2c] 2069type=BaseCache 2070children=tags 2071addr_ranges=0:18446744073709551615 2072assoc=8 2073clk_domain=system.cpu_clk_domain |
| 2074eventq_index=0 |
|
| 1844forward_snoops=true 1845hit_latency=20 1846is_top_level=false 1847max_miss_count=0 1848mshrs=20 1849prefetch_on_access=false 1850prefetcher=Null 1851response_latency=20 --- 6 unchanged lines hidden (view full) --- 1858cpu_side=system.toL2Bus.master[0] 1859mem_side=system.membus.slave[1] 1860 1861[system.l2c.tags] 1862type=LRU 1863assoc=8 1864block_size=64 1865clk_domain=system.cpu_clk_domain | 2075forward_snoops=true 2076hit_latency=20 2077is_top_level=false 2078max_miss_count=0 2079mshrs=20 2080prefetch_on_access=false 2081prefetcher=Null 2082response_latency=20 --- 6 unchanged lines hidden (view full) --- 2089cpu_side=system.toL2Bus.master[0] 2090mem_side=system.membus.slave[1] 2091 2092[system.l2c.tags] 2093type=LRU 2094assoc=8 2095block_size=64 2096clk_domain=system.cpu_clk_domain |
| 2097eventq_index=0 |
|
| 1866hit_latency=20 1867size=4194304 1868 1869[system.membus] 1870type=CoherentBus 1871clk_domain=system.clk_domain | 2098hit_latency=20 2099size=4194304 2100 2101[system.membus] 2102type=CoherentBus 2103clk_domain=system.clk_domain |
| 2104eventq_index=0 |
|
| 1872header_cycles=1 1873system=system 1874use_default_range=false 1875width=8 1876master=system.physmem.port 1877slave=system.system_port system.l2c.mem_side 1878 1879[system.physmem] 1880type=SimpleDRAM 1881activation_limit=4 1882addr_mapping=RaBaChCo 1883banks_per_rank=8 1884burst_length=8 1885channels=1 1886clk_domain=system.clk_domain 1887conf_table_reported=true 1888device_bus_width=8 1889device_rowbuffer_size=1024 1890devices_per_rank=8 | 2105header_cycles=1 2106system=system 2107use_default_range=false 2108width=8 2109master=system.physmem.port 2110slave=system.system_port system.l2c.mem_side 2111 2112[system.physmem] 2113type=SimpleDRAM 2114activation_limit=4 2115addr_mapping=RaBaChCo 2116banks_per_rank=8 2117burst_length=8 2118channels=1 2119clk_domain=system.clk_domain 2120conf_table_reported=true 2121device_bus_width=8 2122device_rowbuffer_size=1024 2123devices_per_rank=8 |
| 2124eventq_index=0 |
|
| 1891in_addr_map=true 1892mem_sched_policy=frfcfs 1893null=false 1894page_policy=open 1895range=0:134217727 1896ranks_per_channel=2 1897read_buffer_size=32 1898static_backend_latency=10000 1899static_frontend_latency=10000 1900tBURST=5000 1901tCL=13750 | 2125in_addr_map=true 2126mem_sched_policy=frfcfs 2127null=false 2128page_policy=open 2129range=0:134217727 2130ranks_per_channel=2 2131read_buffer_size=32 2132static_backend_latency=10000 2133static_frontend_latency=10000 2134tBURST=5000 2135tCL=13750 |
| 2136tRAS=35000 |
|
| 1902tRCD=13750 1903tREFI=7800000 1904tRFC=300000 1905tRP=13750 | 2137tRCD=13750 2138tREFI=7800000 2139tRFC=300000 2140tRP=13750 |
| 2141tRRD=6250 |
|
| 1906tWTR=7500 1907tXAW=40000 1908write_buffer_size=32 | 2142tWTR=7500 2143tXAW=40000 2144write_buffer_size=32 |
| 1909write_thresh_perc=70 | 2145write_high_thresh_perc=70 2146write_low_thresh_perc=0 |
| 1910port=system.membus.master[0] 1911 1912[system.toL2Bus] 1913type=CoherentBus 1914clk_domain=system.cpu_clk_domain | 2147port=system.membus.master[0] 2148 2149[system.toL2Bus] 2150type=CoherentBus 2151clk_domain=system.cpu_clk_domain |
| 2152eventq_index=0 |
|
| 1915header_cycles=1 1916system=system 1917use_default_range=false 1918width=8 1919master=system.l2c.cpu_side 1920slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 1921 1922[system.voltage_domain] 1923type=VoltageDomain | 2153header_cycles=1 2154system=system 2155use_default_range=false 2156width=8 2157master=system.l2c.cpu_side 2158slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 2159 2160[system.voltage_domain] 2161type=VoltageDomain |
| 2162eventq_index=0 |
|
| 1924voltage=1.000000 1925 | 2163voltage=1.000000 2164 |