| config.ini (8983:8800b05e1cb3) | config.ini (9055:38f1926fb599) |
|---|---|
| 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 1754 unchanged lines hidden (view full) --- 1763tgts_per_mshr=16 1764trace_addr=0 1765two_queue=false 1766write_buffers=8 1767cpu_side=system.toL2Bus.master[0] 1768mem_side=system.membus.slave[0] 1769 1770[system.membus] | 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 1754 unchanged lines hidden (view full) --- 1763tgts_per_mshr=16 1764trace_addr=0 1765two_queue=false 1766write_buffers=8 1767cpu_side=system.toL2Bus.master[0] 1768mem_side=system.membus.slave[0] 1769 1770[system.membus] |
| 1771type=Bus | 1771type=CoherentBus |
| 1772block_size=64 | 1772block_size=64 |
| 1773bus_id=0 | |
| 1774clock=1000 1775header_cycles=1 1776use_default_range=false 1777width=64 1778master=system.physmem.port[0] 1779slave=system.l2c.mem_side system.system_port 1780 1781[system.physmem] --- 4 unchanged lines hidden (view full) --- 1786latency=30000 1787latency_var=0 1788null=false 1789range=0:134217727 1790zero=false 1791port=system.membus.master[0] 1792 1793[system.toL2Bus] | 1773clock=1000 1774header_cycles=1 1775use_default_range=false 1776width=64 1777master=system.physmem.port[0] 1778slave=system.l2c.mem_side system.system_port 1779 1780[system.physmem] --- 4 unchanged lines hidden (view full) --- 1785latency=30000 1786latency_var=0 1787null=false 1788range=0:134217727 1789zero=false 1790port=system.membus.master[0] 1791 1792[system.toL2Bus] |
| 1794type=Bus | 1793type=CoherentBus |
| 1795block_size=64 | 1794block_size=64 |
| 1796bus_id=0 | |
| 1797clock=1000 1798header_cycles=1 1799use_default_range=false 1800width=64 1801master=system.l2c.cpu_side 1802slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 1803 | 1795clock=1000 1796header_cycles=1 1797use_default_range=false 1798width=64 1799master=system.l2c.cpu_side 1800slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 1801 |