| config.ini (8835:7c68f84d7c4e) | config.ini (8983:8800b05e1cb3) |
|---|---|
| 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus 12boot_osflags=a 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=timing 17memories=system.physmem 18num_work_ids=16 | 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus 12boot_osflags=a 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=timing 17memories=system.physmem 18num_work_ids=16 |
| 19physmem=system.physmem | |
| 20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 | 19readfile= 20symbolfile= 21work_begin_ckpt_count=0 22work_begin_cpu_id_exit=-1 23work_begin_exit_count=0 24work_cpus_ckpt_count=0 25work_end_ckpt_count=0 26work_end_exit_count=0 27work_item_id=-1 |
| 29system_port=system.membus.port[2] | 28system_port=system.membus.slave[1] |
| 30 31[system.cpu0] 32type=DerivO3CPU 33children=dcache dtb fuPool icache interrupts itb tracer workload 34BTBEntries=4096 35BTBTagSize=16 36LFSTSize=1024 37LQEntries=32 --- 84 unchanged lines hidden (view full) --- 122wbDepth=1 123wbWidth=8 124workload=system.cpu0.workload 125dcache_port=system.cpu0.dcache.cpu_side 126icache_port=system.cpu0.icache.cpu_side 127 128[system.cpu0.dcache] 129type=BaseCache | 29 30[system.cpu0] 31type=DerivO3CPU 32children=dcache dtb fuPool icache interrupts itb tracer workload 33BTBEntries=4096 34BTBTagSize=16 35LFSTSize=1024 36LQEntries=32 --- 84 unchanged lines hidden (view full) --- 121wbDepth=1 122wbWidth=8 123workload=system.cpu0.workload 124dcache_port=system.cpu0.dcache.cpu_side 125icache_port=system.cpu0.icache.cpu_side 126 127[system.cpu0.dcache] 128type=BaseCache |
| 130addr_range=0:18446744073709551615 | 129addr_ranges=0:18446744073709551615 |
| 131assoc=4 132block_size=64 133forward_snoops=true 134hash_delay=1 135is_top_level=true 136latency=1000 137max_miss_count=0 138mshrs=4 --- 4 unchanged lines hidden (view full) --- 143size=32768 144subblock_size=0 145system=system 146tgts_per_mshr=20 147trace_addr=0 148two_queue=false 149write_buffers=8 150cpu_side=system.cpu0.dcache_port | 130assoc=4 131block_size=64 132forward_snoops=true 133hash_delay=1 134is_top_level=true 135latency=1000 136max_miss_count=0 137mshrs=4 --- 4 unchanged lines hidden (view full) --- 142size=32768 143subblock_size=0 144system=system 145tgts_per_mshr=20 146trace_addr=0 147two_queue=false 148write_buffers=8 149cpu_side=system.cpu0.dcache_port |
| 151mem_side=system.toL2Bus.port[2] | 150mem_side=system.toL2Bus.slave[1] |
| 152 153[system.cpu0.dtb] 154type=SparcTLB 155size=64 156 157[system.cpu0.fuPool] 158type=FUPool 159children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 --- 254 unchanged lines hidden (view full) --- 414[system.cpu0.fuPool.FUList8.opList] 415type=OpDesc 416issueLat=3 417opClass=IprAccess 418opLat=3 419 420[system.cpu0.icache] 421type=BaseCache | 151 152[system.cpu0.dtb] 153type=SparcTLB 154size=64 155 156[system.cpu0.fuPool] 157type=FUPool 158children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 --- 254 unchanged lines hidden (view full) --- 413[system.cpu0.fuPool.FUList8.opList] 414type=OpDesc 415issueLat=3 416opClass=IprAccess 417opLat=3 418 419[system.cpu0.icache] 420type=BaseCache |
| 422addr_range=0:18446744073709551615 | 421addr_ranges=0:18446744073709551615 |
| 423assoc=1 424block_size=64 425forward_snoops=true 426hash_delay=1 427is_top_level=true 428latency=1000 429max_miss_count=0 430mshrs=4 --- 4 unchanged lines hidden (view full) --- 435size=32768 436subblock_size=0 437system=system 438tgts_per_mshr=20 439trace_addr=0 440two_queue=false 441write_buffers=8 442cpu_side=system.cpu0.icache_port | 422assoc=1 423block_size=64 424forward_snoops=true 425hash_delay=1 426is_top_level=true 427latency=1000 428max_miss_count=0 429mshrs=4 --- 4 unchanged lines hidden (view full) --- 434size=32768 435subblock_size=0 436system=system 437tgts_per_mshr=20 438trace_addr=0 439two_queue=false 440write_buffers=8 441cpu_side=system.cpu0.icache_port |
| 443mem_side=system.toL2Bus.port[1] | 442mem_side=system.toL2Bus.slave[0] |
| 444 445[system.cpu0.interrupts] 446type=SparcInterrupts 447 448[system.cpu0.itb] 449type=SparcTLB 450size=64 451 --- 113 unchanged lines hidden (view full) --- 565wbDepth=1 566wbWidth=8 567workload=system.cpu0.workload 568dcache_port=system.cpu1.dcache.cpu_side 569icache_port=system.cpu1.icache.cpu_side 570 571[system.cpu1.dcache] 572type=BaseCache | 443 444[system.cpu0.interrupts] 445type=SparcInterrupts 446 447[system.cpu0.itb] 448type=SparcTLB 449size=64 450 --- 113 unchanged lines hidden (view full) --- 564wbDepth=1 565wbWidth=8 566workload=system.cpu0.workload 567dcache_port=system.cpu1.dcache.cpu_side 568icache_port=system.cpu1.icache.cpu_side 569 570[system.cpu1.dcache] 571type=BaseCache |
| 573addr_range=0:18446744073709551615 | 572addr_ranges=0:18446744073709551615 |
| 574assoc=4 575block_size=64 576forward_snoops=true 577hash_delay=1 578is_top_level=true 579latency=1000 580max_miss_count=0 581mshrs=4 --- 4 unchanged lines hidden (view full) --- 586size=32768 587subblock_size=0 588system=system 589tgts_per_mshr=20 590trace_addr=0 591two_queue=false 592write_buffers=8 593cpu_side=system.cpu1.dcache_port | 573assoc=4 574block_size=64 575forward_snoops=true 576hash_delay=1 577is_top_level=true 578latency=1000 579max_miss_count=0 580mshrs=4 --- 4 unchanged lines hidden (view full) --- 585size=32768 586subblock_size=0 587system=system 588tgts_per_mshr=20 589trace_addr=0 590two_queue=false 591write_buffers=8 592cpu_side=system.cpu1.dcache_port |
| 594mem_side=system.toL2Bus.port[4] | 593mem_side=system.toL2Bus.slave[3] |
| 595 596[system.cpu1.dtb] 597type=SparcTLB 598size=64 599 600[system.cpu1.fuPool] 601type=FUPool 602children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 --- 254 unchanged lines hidden (view full) --- 857[system.cpu1.fuPool.FUList8.opList] 858type=OpDesc 859issueLat=3 860opClass=IprAccess 861opLat=3 862 863[system.cpu1.icache] 864type=BaseCache | 594 595[system.cpu1.dtb] 596type=SparcTLB 597size=64 598 599[system.cpu1.fuPool] 600type=FUPool 601children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 --- 254 unchanged lines hidden (view full) --- 856[system.cpu1.fuPool.FUList8.opList] 857type=OpDesc 858issueLat=3 859opClass=IprAccess 860opLat=3 861 862[system.cpu1.icache] 863type=BaseCache |
| 865addr_range=0:18446744073709551615 | 864addr_ranges=0:18446744073709551615 |
| 866assoc=1 867block_size=64 868forward_snoops=true 869hash_delay=1 870is_top_level=true 871latency=1000 872max_miss_count=0 873mshrs=4 --- 4 unchanged lines hidden (view full) --- 878size=32768 879subblock_size=0 880system=system 881tgts_per_mshr=20 882trace_addr=0 883two_queue=false 884write_buffers=8 885cpu_side=system.cpu1.icache_port | 865assoc=1 866block_size=64 867forward_snoops=true 868hash_delay=1 869is_top_level=true 870latency=1000 871max_miss_count=0 872mshrs=4 --- 4 unchanged lines hidden (view full) --- 877size=32768 878subblock_size=0 879system=system 880tgts_per_mshr=20 881trace_addr=0 882two_queue=false 883write_buffers=8 884cpu_side=system.cpu1.icache_port |
| 886mem_side=system.toL2Bus.port[3] | 885mem_side=system.toL2Bus.slave[2] |
| 887 888[system.cpu1.interrupts] 889type=SparcInterrupts 890 891[system.cpu1.itb] 892type=SparcTLB 893size=64 894 --- 94 unchanged lines hidden (view full) --- 989wbDepth=1 990wbWidth=8 991workload=system.cpu0.workload 992dcache_port=system.cpu2.dcache.cpu_side 993icache_port=system.cpu2.icache.cpu_side 994 995[system.cpu2.dcache] 996type=BaseCache | 886 887[system.cpu1.interrupts] 888type=SparcInterrupts 889 890[system.cpu1.itb] 891type=SparcTLB 892size=64 893 --- 94 unchanged lines hidden (view full) --- 988wbDepth=1 989wbWidth=8 990workload=system.cpu0.workload 991dcache_port=system.cpu2.dcache.cpu_side 992icache_port=system.cpu2.icache.cpu_side 993 994[system.cpu2.dcache] 995type=BaseCache |
| 997addr_range=0:18446744073709551615 | 996addr_ranges=0:18446744073709551615 |
| 998assoc=4 999block_size=64 1000forward_snoops=true 1001hash_delay=1 1002is_top_level=true 1003latency=1000 1004max_miss_count=0 1005mshrs=4 --- 4 unchanged lines hidden (view full) --- 1010size=32768 1011subblock_size=0 1012system=system 1013tgts_per_mshr=20 1014trace_addr=0 1015two_queue=false 1016write_buffers=8 1017cpu_side=system.cpu2.dcache_port | 997assoc=4 998block_size=64 999forward_snoops=true 1000hash_delay=1 1001is_top_level=true 1002latency=1000 1003max_miss_count=0 1004mshrs=4 --- 4 unchanged lines hidden (view full) --- 1009size=32768 1010subblock_size=0 1011system=system 1012tgts_per_mshr=20 1013trace_addr=0 1014two_queue=false 1015write_buffers=8 1016cpu_side=system.cpu2.dcache_port |
| 1018mem_side=system.toL2Bus.port[6] | 1017mem_side=system.toL2Bus.slave[5] |
| 1019 1020[system.cpu2.dtb] 1021type=SparcTLB 1022size=64 1023 1024[system.cpu2.fuPool] 1025type=FUPool 1026children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 --- 254 unchanged lines hidden (view full) --- 1281[system.cpu2.fuPool.FUList8.opList] 1282type=OpDesc 1283issueLat=3 1284opClass=IprAccess 1285opLat=3 1286 1287[system.cpu2.icache] 1288type=BaseCache | 1018 1019[system.cpu2.dtb] 1020type=SparcTLB 1021size=64 1022 1023[system.cpu2.fuPool] 1024type=FUPool 1025children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 --- 254 unchanged lines hidden (view full) --- 1280[system.cpu2.fuPool.FUList8.opList] 1281type=OpDesc 1282issueLat=3 1283opClass=IprAccess 1284opLat=3 1285 1286[system.cpu2.icache] 1287type=BaseCache |
| 1289addr_range=0:18446744073709551615 | 1288addr_ranges=0:18446744073709551615 |
| 1290assoc=1 1291block_size=64 1292forward_snoops=true 1293hash_delay=1 1294is_top_level=true 1295latency=1000 1296max_miss_count=0 1297mshrs=4 --- 4 unchanged lines hidden (view full) --- 1302size=32768 1303subblock_size=0 1304system=system 1305tgts_per_mshr=20 1306trace_addr=0 1307two_queue=false 1308write_buffers=8 1309cpu_side=system.cpu2.icache_port | 1289assoc=1 1290block_size=64 1291forward_snoops=true 1292hash_delay=1 1293is_top_level=true 1294latency=1000 1295max_miss_count=0 1296mshrs=4 --- 4 unchanged lines hidden (view full) --- 1301size=32768 1302subblock_size=0 1303system=system 1304tgts_per_mshr=20 1305trace_addr=0 1306two_queue=false 1307write_buffers=8 1308cpu_side=system.cpu2.icache_port |
| 1310mem_side=system.toL2Bus.port[5] | 1309mem_side=system.toL2Bus.slave[4] |
| 1311 1312[system.cpu2.interrupts] 1313type=SparcInterrupts 1314 1315[system.cpu2.itb] 1316type=SparcTLB 1317size=64 1318 --- 94 unchanged lines hidden (view full) --- 1413wbDepth=1 1414wbWidth=8 1415workload=system.cpu0.workload 1416dcache_port=system.cpu3.dcache.cpu_side 1417icache_port=system.cpu3.icache.cpu_side 1418 1419[system.cpu3.dcache] 1420type=BaseCache | 1310 1311[system.cpu2.interrupts] 1312type=SparcInterrupts 1313 1314[system.cpu2.itb] 1315type=SparcTLB 1316size=64 1317 --- 94 unchanged lines hidden (view full) --- 1412wbDepth=1 1413wbWidth=8 1414workload=system.cpu0.workload 1415dcache_port=system.cpu3.dcache.cpu_side 1416icache_port=system.cpu3.icache.cpu_side 1417 1418[system.cpu3.dcache] 1419type=BaseCache |
| 1421addr_range=0:18446744073709551615 | 1420addr_ranges=0:18446744073709551615 |
| 1422assoc=4 1423block_size=64 1424forward_snoops=true 1425hash_delay=1 1426is_top_level=true 1427latency=1000 1428max_miss_count=0 1429mshrs=4 --- 4 unchanged lines hidden (view full) --- 1434size=32768 1435subblock_size=0 1436system=system 1437tgts_per_mshr=20 1438trace_addr=0 1439two_queue=false 1440write_buffers=8 1441cpu_side=system.cpu3.dcache_port | 1421assoc=4 1422block_size=64 1423forward_snoops=true 1424hash_delay=1 1425is_top_level=true 1426latency=1000 1427max_miss_count=0 1428mshrs=4 --- 4 unchanged lines hidden (view full) --- 1433size=32768 1434subblock_size=0 1435system=system 1436tgts_per_mshr=20 1437trace_addr=0 1438two_queue=false 1439write_buffers=8 1440cpu_side=system.cpu3.dcache_port |
| 1442mem_side=system.toL2Bus.port[8] | 1441mem_side=system.toL2Bus.slave[7] |
| 1443 1444[system.cpu3.dtb] 1445type=SparcTLB 1446size=64 1447 1448[system.cpu3.fuPool] 1449type=FUPool 1450children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 --- 254 unchanged lines hidden (view full) --- 1705[system.cpu3.fuPool.FUList8.opList] 1706type=OpDesc 1707issueLat=3 1708opClass=IprAccess 1709opLat=3 1710 1711[system.cpu3.icache] 1712type=BaseCache | 1442 1443[system.cpu3.dtb] 1444type=SparcTLB 1445size=64 1446 1447[system.cpu3.fuPool] 1448type=FUPool 1449children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 --- 254 unchanged lines hidden (view full) --- 1704[system.cpu3.fuPool.FUList8.opList] 1705type=OpDesc 1706issueLat=3 1707opClass=IprAccess 1708opLat=3 1709 1710[system.cpu3.icache] 1711type=BaseCache |
| 1713addr_range=0:18446744073709551615 | 1712addr_ranges=0:18446744073709551615 |
| 1714assoc=1 1715block_size=64 1716forward_snoops=true 1717hash_delay=1 1718is_top_level=true 1719latency=1000 1720max_miss_count=0 1721mshrs=4 --- 4 unchanged lines hidden (view full) --- 1726size=32768 1727subblock_size=0 1728system=system 1729tgts_per_mshr=20 1730trace_addr=0 1731two_queue=false 1732write_buffers=8 1733cpu_side=system.cpu3.icache_port | 1713assoc=1 1714block_size=64 1715forward_snoops=true 1716hash_delay=1 1717is_top_level=true 1718latency=1000 1719max_miss_count=0 1720mshrs=4 --- 4 unchanged lines hidden (view full) --- 1725size=32768 1726subblock_size=0 1727system=system 1728tgts_per_mshr=20 1729trace_addr=0 1730two_queue=false 1731write_buffers=8 1732cpu_side=system.cpu3.icache_port |
| 1734mem_side=system.toL2Bus.port[7] | 1733mem_side=system.toL2Bus.slave[6] |
| 1735 1736[system.cpu3.interrupts] 1737type=SparcInterrupts 1738 1739[system.cpu3.itb] 1740type=SparcTLB 1741size=64 1742 1743[system.cpu3.tracer] 1744type=ExeTracer 1745 1746[system.l2c] 1747type=BaseCache | 1734 1735[system.cpu3.interrupts] 1736type=SparcInterrupts 1737 1738[system.cpu3.itb] 1739type=SparcTLB 1740size=64 1741 1742[system.cpu3.tracer] 1743type=ExeTracer 1744 1745[system.l2c] 1746type=BaseCache |
| 1748addr_range=0:18446744073709551615 | 1747addr_ranges=0:18446744073709551615 |
| 1749assoc=8 1750block_size=64 1751forward_snoops=true 1752hash_delay=1 1753is_top_level=false 1754latency=10000 1755max_miss_count=0 1756mshrs=92 1757prefetch_on_access=false 1758prefetcher=Null 1759prioritizeRequests=false 1760repl=Null 1761size=4194304 1762subblock_size=0 1763system=system 1764tgts_per_mshr=16 1765trace_addr=0 1766two_queue=false 1767write_buffers=8 | 1748assoc=8 1749block_size=64 1750forward_snoops=true 1751hash_delay=1 1752is_top_level=false 1753latency=10000 1754max_miss_count=0 1755mshrs=92 1756prefetch_on_access=false 1757prefetcher=Null 1758prioritizeRequests=false 1759repl=Null 1760size=4194304 1761subblock_size=0 1762system=system 1763tgts_per_mshr=16 1764trace_addr=0 1765two_queue=false 1766write_buffers=8 |
| 1768cpu_side=system.toL2Bus.port[0] 1769mem_side=system.membus.port[0] | 1767cpu_side=system.toL2Bus.master[0] 1768mem_side=system.membus.slave[0] |
| 1770 1771[system.membus] 1772type=Bus 1773block_size=64 1774bus_id=0 1775clock=1000 1776header_cycles=1 1777use_default_range=false 1778width=64 | 1769 1770[system.membus] 1771type=Bus 1772block_size=64 1773bus_id=0 1774clock=1000 1775header_cycles=1 1776use_default_range=false 1777width=64 |
| 1779port=system.l2c.mem_side system.physmem.port[0] system.system_port | 1778master=system.physmem.port[0] 1779slave=system.l2c.mem_side system.system_port |
| 1780 1781[system.physmem] | 1780 1781[system.physmem] |
| 1782type=PhysicalMemory | 1782type=SimpleMemory 1783conf_table_reported=false |
| 1783file= | 1784file= |
| 1785in_addr_map=true |
|
| 1784latency=30000 1785latency_var=0 1786null=false 1787range=0:134217727 1788zero=false | 1786latency=30000 1787latency_var=0 1788null=false 1789range=0:134217727 1790zero=false |
| 1789port=system.membus.port[1] | 1791port=system.membus.master[0] |
| 1790 1791[system.toL2Bus] 1792type=Bus 1793block_size=64 1794bus_id=0 1795clock=1000 1796header_cycles=1 1797use_default_range=false 1798width=64 | 1792 1793[system.toL2Bus] 1794type=Bus 1795block_size=64 1796bus_id=0 1797clock=1000 1798header_cycles=1 1799use_default_range=false 1800width=64 |
| 1799port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side | 1801master=system.l2c.cpu_side 1802slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side |
| 1800 | 1803 |