| config.ini (11680:b4d943429dc6) | config.ini (11731:c473ca7cc650) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 163 unchanged lines hidden (view full) --- 172 173[system.cpu0.dcache] 174type=Cache 175children=tags 176addr_ranges=0:18446744073709551615:0:0:0:0 177assoc=4 178clk_domain=system.cpu_clk_domain 179clusivity=mostly_incl | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 163 unchanged lines hidden (view full) --- 172 173[system.cpu0.dcache] 174type=Cache 175children=tags 176addr_ranges=0:18446744073709551615:0:0:0:0 177assoc=4 178clk_domain=system.cpu_clk_domain 179clusivity=mostly_incl |
| 180data_latency=2 |
|
| 180default_p_state=UNDEFINED 181demand_mshr_reserve=1 182eventq_index=0 | 181default_p_state=UNDEFINED 182demand_mshr_reserve=1 183eventq_index=0 |
| 183hit_latency=2 | |
| 184is_read_only=false 185max_miss_count=0 186mshrs=4 187p_state_clk_gate_bins=20 188p_state_clk_gate_max=1000000000000 189p_state_clk_gate_min=1000 190power_model=Null 191prefetch_on_access=false 192prefetcher=Null 193response_latency=2 194sequential_access=false 195size=32768 196system=system | 184is_read_only=false 185max_miss_count=0 186mshrs=4 187p_state_clk_gate_bins=20 188p_state_clk_gate_max=1000000000000 189p_state_clk_gate_min=1000 190power_model=Null 191prefetch_on_access=false 192prefetcher=Null 193response_latency=2 194sequential_access=false 195size=32768 196system=system |
| 197tag_latency=2 |
|
| 197tags=system.cpu0.dcache.tags 198tgts_per_mshr=20 199write_buffers=8 200writeback_clean=false 201cpu_side=system.cpu0.dcache_port 202mem_side=system.toL2Bus.slave[1] 203 204[system.cpu0.dcache.tags] 205type=LRU 206assoc=4 207block_size=64 208clk_domain=system.cpu_clk_domain | 198tags=system.cpu0.dcache.tags 199tgts_per_mshr=20 200write_buffers=8 201writeback_clean=false 202cpu_side=system.cpu0.dcache_port 203mem_side=system.toL2Bus.slave[1] 204 205[system.cpu0.dcache.tags] 206type=LRU 207assoc=4 208block_size=64 209clk_domain=system.cpu_clk_domain |
| 210data_latency=2 |
|
| 209default_p_state=UNDEFINED 210eventq_index=0 | 211default_p_state=UNDEFINED 212eventq_index=0 |
| 211hit_latency=2 | |
| 212p_state_clk_gate_bins=20 213p_state_clk_gate_max=1000000000000 214p_state_clk_gate_min=1000 215power_model=Null 216sequential_access=false 217size=32768 | 213p_state_clk_gate_bins=20 214p_state_clk_gate_max=1000000000000 215p_state_clk_gate_min=1000 216power_model=Null 217sequential_access=false 218size=32768 |
| 219tag_latency=2 |
|
| 218 219[system.cpu0.dtb] 220type=SparcTLB 221eventq_index=0 222size=64 223 224[system.cpu0.fuPool] 225type=FUPool --- 61 unchanged lines hidden (view full) --- 287type=OpDesc 288eventq_index=0 289opClass=FloatCvt 290opLat=2 291pipelined=true 292 293[system.cpu0.fuPool.FUList3] 294type=FUDesc | 220 221[system.cpu0.dtb] 222type=SparcTLB 223eventq_index=0 224size=64 225 226[system.cpu0.fuPool] 227type=FUPool --- 61 unchanged lines hidden (view full) --- 289type=OpDesc 290eventq_index=0 291opClass=FloatCvt 292opLat=2 293pipelined=true 294 295[system.cpu0.fuPool.FUList3] 296type=FUDesc |
| 295children=opList0 opList1 opList2 | 297children=opList0 opList1 opList2 opList3 opList4 |
| 296count=2 297eventq_index=0 | 298count=2 299eventq_index=0 |
| 298opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 | 300opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 system.cpu0.fuPool.FUList3.opList3 system.cpu0.fuPool.FUList3.opList4 |
| 299 300[system.cpu0.fuPool.FUList3.opList0] 301type=OpDesc 302eventq_index=0 303opClass=FloatMult 304opLat=4 305pipelined=true 306 307[system.cpu0.fuPool.FUList3.opList1] 308type=OpDesc 309eventq_index=0 | 301 302[system.cpu0.fuPool.FUList3.opList0] 303type=OpDesc 304eventq_index=0 305opClass=FloatMult 306opLat=4 307pipelined=true 308 309[system.cpu0.fuPool.FUList3.opList1] 310type=OpDesc 311eventq_index=0 |
| 312opClass=FloatMultAcc 313opLat=5 314pipelined=true 315 316[system.cpu0.fuPool.FUList3.opList2] 317type=OpDesc 318eventq_index=0 319opClass=FloatMisc 320opLat=3 321pipelined=true 322 323[system.cpu0.fuPool.FUList3.opList3] 324type=OpDesc 325eventq_index=0 |
|
| 310opClass=FloatDiv 311opLat=12 312pipelined=false 313 | 326opClass=FloatDiv 327opLat=12 328pipelined=false 329 |
| 314[system.cpu0.fuPool.FUList3.opList2] | 330[system.cpu0.fuPool.FUList3.opList4] |
| 315type=OpDesc 316eventq_index=0 317opClass=FloatSqrt 318opLat=24 319pipelined=false 320 321[system.cpu0.fuPool.FUList4] 322type=FUDesc | 331type=OpDesc 332eventq_index=0 333opClass=FloatSqrt 334opLat=24 335pipelined=false 336 337[system.cpu0.fuPool.FUList4] 338type=FUDesc |
| 323children=opList | 339children=opList0 opList1 |
| 324count=0 325eventq_index=0 | 340count=0 341eventq_index=0 |
| 326opList=system.cpu0.fuPool.FUList4.opList | 342opList=system.cpu0.fuPool.FUList4.opList0 system.cpu0.fuPool.FUList4.opList1 |
| 327 | 343 |
| 328[system.cpu0.fuPool.FUList4.opList] | 344[system.cpu0.fuPool.FUList4.opList0] |
| 329type=OpDesc 330eventq_index=0 331opClass=MemRead 332opLat=1 333pipelined=true 334 | 345type=OpDesc 346eventq_index=0 347opClass=MemRead 348opLat=1 349pipelined=true 350 |
| 351[system.cpu0.fuPool.FUList4.opList1] 352type=OpDesc 353eventq_index=0 354opClass=FloatMemRead 355opLat=1 356pipelined=true 357 |
|
| 335[system.cpu0.fuPool.FUList5] 336type=FUDesc 337children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 338count=4 339eventq_index=0 340opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 341 342[system.cpu0.fuPool.FUList5.opList00] --- 133 unchanged lines hidden (view full) --- 476type=OpDesc 477eventq_index=0 478opClass=SimdFloatSqrt 479opLat=1 480pipelined=true 481 482[system.cpu0.fuPool.FUList6] 483type=FUDesc | 358[system.cpu0.fuPool.FUList5] 359type=FUDesc 360children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 361count=4 362eventq_index=0 363opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 364 365[system.cpu0.fuPool.FUList5.opList00] --- 133 unchanged lines hidden (view full) --- 499type=OpDesc 500eventq_index=0 501opClass=SimdFloatSqrt 502opLat=1 503pipelined=true 504 505[system.cpu0.fuPool.FUList6] 506type=FUDesc |
| 484children=opList | 507children=opList0 opList1 |
| 485count=0 486eventq_index=0 | 508count=0 509eventq_index=0 |
| 487opList=system.cpu0.fuPool.FUList6.opList | 510opList=system.cpu0.fuPool.FUList6.opList0 system.cpu0.fuPool.FUList6.opList1 |
| 488 | 511 |
| 489[system.cpu0.fuPool.FUList6.opList] | 512[system.cpu0.fuPool.FUList6.opList0] |
| 490type=OpDesc 491eventq_index=0 492opClass=MemWrite 493opLat=1 494pipelined=true 495 | 513type=OpDesc 514eventq_index=0 515opClass=MemWrite 516opLat=1 517pipelined=true 518 |
| 519[system.cpu0.fuPool.FUList6.opList1] 520type=OpDesc 521eventq_index=0 522opClass=FloatMemWrite 523opLat=1 524pipelined=true 525 |
|
| 496[system.cpu0.fuPool.FUList7] 497type=FUDesc | 526[system.cpu0.fuPool.FUList7] 527type=FUDesc |
| 498children=opList0 opList1 | 528children=opList0 opList1 opList2 opList3 |
| 499count=4 500eventq_index=0 | 529count=4 530eventq_index=0 |
| 501opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 | 531opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 system.cpu0.fuPool.FUList7.opList2 system.cpu0.fuPool.FUList7.opList3 |
| 502 503[system.cpu0.fuPool.FUList7.opList0] 504type=OpDesc 505eventq_index=0 506opClass=MemRead 507opLat=1 508pipelined=true 509 510[system.cpu0.fuPool.FUList7.opList1] 511type=OpDesc 512eventq_index=0 513opClass=MemWrite 514opLat=1 515pipelined=true 516 | 532 533[system.cpu0.fuPool.FUList7.opList0] 534type=OpDesc 535eventq_index=0 536opClass=MemRead 537opLat=1 538pipelined=true 539 540[system.cpu0.fuPool.FUList7.opList1] 541type=OpDesc 542eventq_index=0 543opClass=MemWrite 544opLat=1 545pipelined=true 546 |
| 547[system.cpu0.fuPool.FUList7.opList2] 548type=OpDesc 549eventq_index=0 550opClass=FloatMemRead 551opLat=1 552pipelined=true 553 554[system.cpu0.fuPool.FUList7.opList3] 555type=OpDesc 556eventq_index=0 557opClass=FloatMemWrite 558opLat=1 559pipelined=true 560 |
|
| 517[system.cpu0.fuPool.FUList8] 518type=FUDesc 519children=opList 520count=1 521eventq_index=0 522opList=system.cpu0.fuPool.FUList8.opList 523 524[system.cpu0.fuPool.FUList8.opList] --- 5 unchanged lines hidden (view full) --- 530 531[system.cpu0.icache] 532type=Cache 533children=tags 534addr_ranges=0:18446744073709551615:0:0:0:0 535assoc=1 536clk_domain=system.cpu_clk_domain 537clusivity=mostly_incl | 561[system.cpu0.fuPool.FUList8] 562type=FUDesc 563children=opList 564count=1 565eventq_index=0 566opList=system.cpu0.fuPool.FUList8.opList 567 568[system.cpu0.fuPool.FUList8.opList] --- 5 unchanged lines hidden (view full) --- 574 575[system.cpu0.icache] 576type=Cache 577children=tags 578addr_ranges=0:18446744073709551615:0:0:0:0 579assoc=1 580clk_domain=system.cpu_clk_domain 581clusivity=mostly_incl |
| 582data_latency=2 |
|
| 538default_p_state=UNDEFINED 539demand_mshr_reserve=1 540eventq_index=0 | 583default_p_state=UNDEFINED 584demand_mshr_reserve=1 585eventq_index=0 |
| 541hit_latency=2 | |
| 542is_read_only=true 543max_miss_count=0 544mshrs=4 545p_state_clk_gate_bins=20 546p_state_clk_gate_max=1000000000000 547p_state_clk_gate_min=1000 548power_model=Null 549prefetch_on_access=false 550prefetcher=Null 551response_latency=2 552sequential_access=false 553size=32768 554system=system | 586is_read_only=true 587max_miss_count=0 588mshrs=4 589p_state_clk_gate_bins=20 590p_state_clk_gate_max=1000000000000 591p_state_clk_gate_min=1000 592power_model=Null 593prefetch_on_access=false 594prefetcher=Null 595response_latency=2 596sequential_access=false 597size=32768 598system=system |
| 599tag_latency=2 |
|
| 555tags=system.cpu0.icache.tags 556tgts_per_mshr=20 557write_buffers=8 558writeback_clean=true 559cpu_side=system.cpu0.icache_port 560mem_side=system.toL2Bus.slave[0] 561 562[system.cpu0.icache.tags] 563type=LRU 564assoc=1 565block_size=64 566clk_domain=system.cpu_clk_domain | 600tags=system.cpu0.icache.tags 601tgts_per_mshr=20 602write_buffers=8 603writeback_clean=true 604cpu_side=system.cpu0.icache_port 605mem_side=system.toL2Bus.slave[0] 606 607[system.cpu0.icache.tags] 608type=LRU 609assoc=1 610block_size=64 611clk_domain=system.cpu_clk_domain |
| 612data_latency=2 |
|
| 567default_p_state=UNDEFINED 568eventq_index=0 | 613default_p_state=UNDEFINED 614eventq_index=0 |
| 569hit_latency=2 | |
| 570p_state_clk_gate_bins=20 571p_state_clk_gate_max=1000000000000 572p_state_clk_gate_min=1000 573power_model=Null 574sequential_access=false 575size=32768 | 615p_state_clk_gate_bins=20 616p_state_clk_gate_max=1000000000000 617p_state_clk_gate_min=1000 618power_model=Null 619sequential_access=false 620size=32768 |
| 621tag_latency=2 |
|
| 576 577[system.cpu0.interrupts] 578type=SparcInterrupts 579eventq_index=0 580 581[system.cpu0.isa] 582type=SparcISA 583eventq_index=0 --- 12 unchanged lines hidden (view full) --- 596cmd=test_atomic 4 597cwd= 598drivers= 599egid=100 600env= 601errout=cerr 602euid=100 603eventq_index=0 | 622 623[system.cpu0.interrupts] 624type=SparcInterrupts 625eventq_index=0 626 627[system.cpu0.isa] 628type=SparcISA 629eventq_index=0 --- 12 unchanged lines hidden (view full) --- 642cmd=test_atomic 4 643cwd= 644drivers= 645egid=100 646env= 647errout=cerr 648euid=100 649eventq_index=0 |
| 604executable=/arm/projectscratch/randd/systems/dist/test-progs/m5threads/bin/sparc/linux/test_atomic | 650executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic |
| 605gid=100 606input=cin 607kvmInSE=false 608max_stack_size=67108864 609output=cout 610pid=100 611ppid=99 612simpoint=0 --- 120 unchanged lines hidden (view full) --- 733 734[system.cpu1.dcache] 735type=Cache 736children=tags 737addr_ranges=0:18446744073709551615:0:0:0:0 738assoc=4 739clk_domain=system.cpu_clk_domain 740clusivity=mostly_incl | 651gid=100 652input=cin 653kvmInSE=false 654max_stack_size=67108864 655output=cout 656pid=100 657ppid=99 658simpoint=0 --- 120 unchanged lines hidden (view full) --- 779 780[system.cpu1.dcache] 781type=Cache 782children=tags 783addr_ranges=0:18446744073709551615:0:0:0:0 784assoc=4 785clk_domain=system.cpu_clk_domain 786clusivity=mostly_incl |
| 787data_latency=2 |
|
| 741default_p_state=UNDEFINED 742demand_mshr_reserve=1 743eventq_index=0 | 788default_p_state=UNDEFINED 789demand_mshr_reserve=1 790eventq_index=0 |
| 744hit_latency=2 | |
| 745is_read_only=false 746max_miss_count=0 747mshrs=4 748p_state_clk_gate_bins=20 749p_state_clk_gate_max=1000000000000 750p_state_clk_gate_min=1000 751power_model=Null 752prefetch_on_access=false 753prefetcher=Null 754response_latency=2 755sequential_access=false 756size=32768 757system=system | 791is_read_only=false 792max_miss_count=0 793mshrs=4 794p_state_clk_gate_bins=20 795p_state_clk_gate_max=1000000000000 796p_state_clk_gate_min=1000 797power_model=Null 798prefetch_on_access=false 799prefetcher=Null 800response_latency=2 801sequential_access=false 802size=32768 803system=system |
| 804tag_latency=2 |
|
| 758tags=system.cpu1.dcache.tags 759tgts_per_mshr=20 760write_buffers=8 761writeback_clean=false 762cpu_side=system.cpu1.dcache_port 763mem_side=system.toL2Bus.slave[3] 764 765[system.cpu1.dcache.tags] 766type=LRU 767assoc=4 768block_size=64 769clk_domain=system.cpu_clk_domain | 805tags=system.cpu1.dcache.tags 806tgts_per_mshr=20 807write_buffers=8 808writeback_clean=false 809cpu_side=system.cpu1.dcache_port 810mem_side=system.toL2Bus.slave[3] 811 812[system.cpu1.dcache.tags] 813type=LRU 814assoc=4 815block_size=64 816clk_domain=system.cpu_clk_domain |
| 817data_latency=2 |
|
| 770default_p_state=UNDEFINED 771eventq_index=0 | 818default_p_state=UNDEFINED 819eventq_index=0 |
| 772hit_latency=2 | |
| 773p_state_clk_gate_bins=20 774p_state_clk_gate_max=1000000000000 775p_state_clk_gate_min=1000 776power_model=Null 777sequential_access=false 778size=32768 | 820p_state_clk_gate_bins=20 821p_state_clk_gate_max=1000000000000 822p_state_clk_gate_min=1000 823power_model=Null 824sequential_access=false 825size=32768 |
| 826tag_latency=2 |
|
| 779 780[system.cpu1.dtb] 781type=SparcTLB 782eventq_index=0 783size=64 784 785[system.cpu1.fuPool] 786type=FUPool --- 61 unchanged lines hidden (view full) --- 848type=OpDesc 849eventq_index=0 850opClass=FloatCvt 851opLat=2 852pipelined=true 853 854[system.cpu1.fuPool.FUList3] 855type=FUDesc | 827 828[system.cpu1.dtb] 829type=SparcTLB 830eventq_index=0 831size=64 832 833[system.cpu1.fuPool] 834type=FUPool --- 61 unchanged lines hidden (view full) --- 896type=OpDesc 897eventq_index=0 898opClass=FloatCvt 899opLat=2 900pipelined=true 901 902[system.cpu1.fuPool.FUList3] 903type=FUDesc |
| 856children=opList0 opList1 opList2 | 904children=opList0 opList1 opList2 opList3 opList4 |
| 857count=2 858eventq_index=0 | 905count=2 906eventq_index=0 |
| 859opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 | 907opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 system.cpu1.fuPool.FUList3.opList3 system.cpu1.fuPool.FUList3.opList4 |
| 860 861[system.cpu1.fuPool.FUList3.opList0] 862type=OpDesc 863eventq_index=0 864opClass=FloatMult 865opLat=4 866pipelined=true 867 868[system.cpu1.fuPool.FUList3.opList1] 869type=OpDesc 870eventq_index=0 | 908 909[system.cpu1.fuPool.FUList3.opList0] 910type=OpDesc 911eventq_index=0 912opClass=FloatMult 913opLat=4 914pipelined=true 915 916[system.cpu1.fuPool.FUList3.opList1] 917type=OpDesc 918eventq_index=0 |
| 919opClass=FloatMultAcc 920opLat=5 921pipelined=true 922 923[system.cpu1.fuPool.FUList3.opList2] 924type=OpDesc 925eventq_index=0 926opClass=FloatMisc 927opLat=3 928pipelined=true 929 930[system.cpu1.fuPool.FUList3.opList3] 931type=OpDesc 932eventq_index=0 |
|
| 871opClass=FloatDiv 872opLat=12 873pipelined=false 874 | 933opClass=FloatDiv 934opLat=12 935pipelined=false 936 |
| 875[system.cpu1.fuPool.FUList3.opList2] | 937[system.cpu1.fuPool.FUList3.opList4] |
| 876type=OpDesc 877eventq_index=0 878opClass=FloatSqrt 879opLat=24 880pipelined=false 881 882[system.cpu1.fuPool.FUList4] 883type=FUDesc | 938type=OpDesc 939eventq_index=0 940opClass=FloatSqrt 941opLat=24 942pipelined=false 943 944[system.cpu1.fuPool.FUList4] 945type=FUDesc |
| 884children=opList | 946children=opList0 opList1 |
| 885count=0 886eventq_index=0 | 947count=0 948eventq_index=0 |
| 887opList=system.cpu1.fuPool.FUList4.opList | 949opList=system.cpu1.fuPool.FUList4.opList0 system.cpu1.fuPool.FUList4.opList1 |
| 888 | 950 |
| 889[system.cpu1.fuPool.FUList4.opList] | 951[system.cpu1.fuPool.FUList4.opList0] |
| 890type=OpDesc 891eventq_index=0 892opClass=MemRead 893opLat=1 894pipelined=true 895 | 952type=OpDesc 953eventq_index=0 954opClass=MemRead 955opLat=1 956pipelined=true 957 |
| 958[system.cpu1.fuPool.FUList4.opList1] 959type=OpDesc 960eventq_index=0 961opClass=FloatMemRead 962opLat=1 963pipelined=true 964 |
|
| 896[system.cpu1.fuPool.FUList5] 897type=FUDesc 898children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 899count=4 900eventq_index=0 901opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 902 903[system.cpu1.fuPool.FUList5.opList00] --- 133 unchanged lines hidden (view full) --- 1037type=OpDesc 1038eventq_index=0 1039opClass=SimdFloatSqrt 1040opLat=1 1041pipelined=true 1042 1043[system.cpu1.fuPool.FUList6] 1044type=FUDesc | 965[system.cpu1.fuPool.FUList5] 966type=FUDesc 967children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 968count=4 969eventq_index=0 970opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 971 972[system.cpu1.fuPool.FUList5.opList00] --- 133 unchanged lines hidden (view full) --- 1106type=OpDesc 1107eventq_index=0 1108opClass=SimdFloatSqrt 1109opLat=1 1110pipelined=true 1111 1112[system.cpu1.fuPool.FUList6] 1113type=FUDesc |
| 1045children=opList | 1114children=opList0 opList1 |
| 1046count=0 1047eventq_index=0 | 1115count=0 1116eventq_index=0 |
| 1048opList=system.cpu1.fuPool.FUList6.opList | 1117opList=system.cpu1.fuPool.FUList6.opList0 system.cpu1.fuPool.FUList6.opList1 |
| 1049 | 1118 |
| 1050[system.cpu1.fuPool.FUList6.opList] | 1119[system.cpu1.fuPool.FUList6.opList0] |
| 1051type=OpDesc 1052eventq_index=0 1053opClass=MemWrite 1054opLat=1 1055pipelined=true 1056 | 1120type=OpDesc 1121eventq_index=0 1122opClass=MemWrite 1123opLat=1 1124pipelined=true 1125 |
| 1126[system.cpu1.fuPool.FUList6.opList1] 1127type=OpDesc 1128eventq_index=0 1129opClass=FloatMemWrite 1130opLat=1 1131pipelined=true 1132 |
|
| 1057[system.cpu1.fuPool.FUList7] 1058type=FUDesc | 1133[system.cpu1.fuPool.FUList7] 1134type=FUDesc |
| 1059children=opList0 opList1 | 1135children=opList0 opList1 opList2 opList3 |
| 1060count=4 1061eventq_index=0 | 1136count=4 1137eventq_index=0 |
| 1062opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 | 1138opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 system.cpu1.fuPool.FUList7.opList2 system.cpu1.fuPool.FUList7.opList3 |
| 1063 1064[system.cpu1.fuPool.FUList7.opList0] 1065type=OpDesc 1066eventq_index=0 1067opClass=MemRead 1068opLat=1 1069pipelined=true 1070 1071[system.cpu1.fuPool.FUList7.opList1] 1072type=OpDesc 1073eventq_index=0 1074opClass=MemWrite 1075opLat=1 1076pipelined=true 1077 | 1139 1140[system.cpu1.fuPool.FUList7.opList0] 1141type=OpDesc 1142eventq_index=0 1143opClass=MemRead 1144opLat=1 1145pipelined=true 1146 1147[system.cpu1.fuPool.FUList7.opList1] 1148type=OpDesc 1149eventq_index=0 1150opClass=MemWrite 1151opLat=1 1152pipelined=true 1153 |
| 1154[system.cpu1.fuPool.FUList7.opList2] 1155type=OpDesc 1156eventq_index=0 1157opClass=FloatMemRead 1158opLat=1 1159pipelined=true 1160 1161[system.cpu1.fuPool.FUList7.opList3] 1162type=OpDesc 1163eventq_index=0 1164opClass=FloatMemWrite 1165opLat=1 1166pipelined=true 1167 |
|
| 1078[system.cpu1.fuPool.FUList8] 1079type=FUDesc 1080children=opList 1081count=1 1082eventq_index=0 1083opList=system.cpu1.fuPool.FUList8.opList 1084 1085[system.cpu1.fuPool.FUList8.opList] --- 5 unchanged lines hidden (view full) --- 1091 1092[system.cpu1.icache] 1093type=Cache 1094children=tags 1095addr_ranges=0:18446744073709551615:0:0:0:0 1096assoc=1 1097clk_domain=system.cpu_clk_domain 1098clusivity=mostly_incl | 1168[system.cpu1.fuPool.FUList8] 1169type=FUDesc 1170children=opList 1171count=1 1172eventq_index=0 1173opList=system.cpu1.fuPool.FUList8.opList 1174 1175[system.cpu1.fuPool.FUList8.opList] --- 5 unchanged lines hidden (view full) --- 1181 1182[system.cpu1.icache] 1183type=Cache 1184children=tags 1185addr_ranges=0:18446744073709551615:0:0:0:0 1186assoc=1 1187clk_domain=system.cpu_clk_domain 1188clusivity=mostly_incl |
| 1189data_latency=2 |
|
| 1099default_p_state=UNDEFINED 1100demand_mshr_reserve=1 1101eventq_index=0 | 1190default_p_state=UNDEFINED 1191demand_mshr_reserve=1 1192eventq_index=0 |
| 1102hit_latency=2 | |
| 1103is_read_only=true 1104max_miss_count=0 1105mshrs=4 1106p_state_clk_gate_bins=20 1107p_state_clk_gate_max=1000000000000 1108p_state_clk_gate_min=1000 1109power_model=Null 1110prefetch_on_access=false 1111prefetcher=Null 1112response_latency=2 1113sequential_access=false 1114size=32768 1115system=system | 1193is_read_only=true 1194max_miss_count=0 1195mshrs=4 1196p_state_clk_gate_bins=20 1197p_state_clk_gate_max=1000000000000 1198p_state_clk_gate_min=1000 1199power_model=Null 1200prefetch_on_access=false 1201prefetcher=Null 1202response_latency=2 1203sequential_access=false 1204size=32768 1205system=system |
| 1206tag_latency=2 |
|
| 1116tags=system.cpu1.icache.tags 1117tgts_per_mshr=20 1118write_buffers=8 1119writeback_clean=true 1120cpu_side=system.cpu1.icache_port 1121mem_side=system.toL2Bus.slave[2] 1122 1123[system.cpu1.icache.tags] 1124type=LRU 1125assoc=1 1126block_size=64 1127clk_domain=system.cpu_clk_domain | 1207tags=system.cpu1.icache.tags 1208tgts_per_mshr=20 1209write_buffers=8 1210writeback_clean=true 1211cpu_side=system.cpu1.icache_port 1212mem_side=system.toL2Bus.slave[2] 1213 1214[system.cpu1.icache.tags] 1215type=LRU 1216assoc=1 1217block_size=64 1218clk_domain=system.cpu_clk_domain |
| 1219data_latency=2 |
|
| 1128default_p_state=UNDEFINED 1129eventq_index=0 | 1220default_p_state=UNDEFINED 1221eventq_index=0 |
| 1130hit_latency=2 | |
| 1131p_state_clk_gate_bins=20 1132p_state_clk_gate_max=1000000000000 1133p_state_clk_gate_min=1000 1134power_model=Null 1135sequential_access=false 1136size=32768 | 1222p_state_clk_gate_bins=20 1223p_state_clk_gate_max=1000000000000 1224p_state_clk_gate_min=1000 1225power_model=Null 1226sequential_access=false 1227size=32768 |
| 1228tag_latency=2 |
|
| 1137 1138[system.cpu1.interrupts] 1139type=SparcInterrupts 1140eventq_index=0 1141 1142[system.cpu1.isa] 1143type=SparcISA 1144eventq_index=0 --- 126 unchanged lines hidden (view full) --- 1271 1272[system.cpu2.dcache] 1273type=Cache 1274children=tags 1275addr_ranges=0:18446744073709551615:0:0:0:0 1276assoc=4 1277clk_domain=system.cpu_clk_domain 1278clusivity=mostly_incl | 1229 1230[system.cpu1.interrupts] 1231type=SparcInterrupts 1232eventq_index=0 1233 1234[system.cpu1.isa] 1235type=SparcISA 1236eventq_index=0 --- 126 unchanged lines hidden (view full) --- 1363 1364[system.cpu2.dcache] 1365type=Cache 1366children=tags 1367addr_ranges=0:18446744073709551615:0:0:0:0 1368assoc=4 1369clk_domain=system.cpu_clk_domain 1370clusivity=mostly_incl |
| 1371data_latency=2 |
|
| 1279default_p_state=UNDEFINED 1280demand_mshr_reserve=1 1281eventq_index=0 | 1372default_p_state=UNDEFINED 1373demand_mshr_reserve=1 1374eventq_index=0 |
| 1282hit_latency=2 | |
| 1283is_read_only=false 1284max_miss_count=0 1285mshrs=4 1286p_state_clk_gate_bins=20 1287p_state_clk_gate_max=1000000000000 1288p_state_clk_gate_min=1000 1289power_model=Null 1290prefetch_on_access=false 1291prefetcher=Null 1292response_latency=2 1293sequential_access=false 1294size=32768 1295system=system | 1375is_read_only=false 1376max_miss_count=0 1377mshrs=4 1378p_state_clk_gate_bins=20 1379p_state_clk_gate_max=1000000000000 1380p_state_clk_gate_min=1000 1381power_model=Null 1382prefetch_on_access=false 1383prefetcher=Null 1384response_latency=2 1385sequential_access=false 1386size=32768 1387system=system |
| 1388tag_latency=2 |
|
| 1296tags=system.cpu2.dcache.tags 1297tgts_per_mshr=20 1298write_buffers=8 1299writeback_clean=false 1300cpu_side=system.cpu2.dcache_port 1301mem_side=system.toL2Bus.slave[5] 1302 1303[system.cpu2.dcache.tags] 1304type=LRU 1305assoc=4 1306block_size=64 1307clk_domain=system.cpu_clk_domain | 1389tags=system.cpu2.dcache.tags 1390tgts_per_mshr=20 1391write_buffers=8 1392writeback_clean=false 1393cpu_side=system.cpu2.dcache_port 1394mem_side=system.toL2Bus.slave[5] 1395 1396[system.cpu2.dcache.tags] 1397type=LRU 1398assoc=4 1399block_size=64 1400clk_domain=system.cpu_clk_domain |
| 1401data_latency=2 |
|
| 1308default_p_state=UNDEFINED 1309eventq_index=0 | 1402default_p_state=UNDEFINED 1403eventq_index=0 |
| 1310hit_latency=2 | |
| 1311p_state_clk_gate_bins=20 1312p_state_clk_gate_max=1000000000000 1313p_state_clk_gate_min=1000 1314power_model=Null 1315sequential_access=false 1316size=32768 | 1404p_state_clk_gate_bins=20 1405p_state_clk_gate_max=1000000000000 1406p_state_clk_gate_min=1000 1407power_model=Null 1408sequential_access=false 1409size=32768 |
| 1410tag_latency=2 |
|
| 1317 1318[system.cpu2.dtb] 1319type=SparcTLB 1320eventq_index=0 1321size=64 1322 1323[system.cpu2.fuPool] 1324type=FUPool --- 61 unchanged lines hidden (view full) --- 1386type=OpDesc 1387eventq_index=0 1388opClass=FloatCvt 1389opLat=2 1390pipelined=true 1391 1392[system.cpu2.fuPool.FUList3] 1393type=FUDesc | 1411 1412[system.cpu2.dtb] 1413type=SparcTLB 1414eventq_index=0 1415size=64 1416 1417[system.cpu2.fuPool] 1418type=FUPool --- 61 unchanged lines hidden (view full) --- 1480type=OpDesc 1481eventq_index=0 1482opClass=FloatCvt 1483opLat=2 1484pipelined=true 1485 1486[system.cpu2.fuPool.FUList3] 1487type=FUDesc |
| 1394children=opList0 opList1 opList2 | 1488children=opList0 opList1 opList2 opList3 opList4 |
| 1395count=2 1396eventq_index=0 | 1489count=2 1490eventq_index=0 |
| 1397opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 | 1491opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 system.cpu2.fuPool.FUList3.opList3 system.cpu2.fuPool.FUList3.opList4 |
| 1398 1399[system.cpu2.fuPool.FUList3.opList0] 1400type=OpDesc 1401eventq_index=0 1402opClass=FloatMult 1403opLat=4 1404pipelined=true 1405 1406[system.cpu2.fuPool.FUList3.opList1] 1407type=OpDesc 1408eventq_index=0 | 1492 1493[system.cpu2.fuPool.FUList3.opList0] 1494type=OpDesc 1495eventq_index=0 1496opClass=FloatMult 1497opLat=4 1498pipelined=true 1499 1500[system.cpu2.fuPool.FUList3.opList1] 1501type=OpDesc 1502eventq_index=0 |
| 1503opClass=FloatMultAcc 1504opLat=5 1505pipelined=true 1506 1507[system.cpu2.fuPool.FUList3.opList2] 1508type=OpDesc 1509eventq_index=0 1510opClass=FloatMisc 1511opLat=3 1512pipelined=true 1513 1514[system.cpu2.fuPool.FUList3.opList3] 1515type=OpDesc 1516eventq_index=0 |
|
| 1409opClass=FloatDiv 1410opLat=12 1411pipelined=false 1412 | 1517opClass=FloatDiv 1518opLat=12 1519pipelined=false 1520 |
| 1413[system.cpu2.fuPool.FUList3.opList2] | 1521[system.cpu2.fuPool.FUList3.opList4] |
| 1414type=OpDesc 1415eventq_index=0 1416opClass=FloatSqrt 1417opLat=24 1418pipelined=false 1419 1420[system.cpu2.fuPool.FUList4] 1421type=FUDesc | 1522type=OpDesc 1523eventq_index=0 1524opClass=FloatSqrt 1525opLat=24 1526pipelined=false 1527 1528[system.cpu2.fuPool.FUList4] 1529type=FUDesc |
| 1422children=opList | 1530children=opList0 opList1 |
| 1423count=0 1424eventq_index=0 | 1531count=0 1532eventq_index=0 |
| 1425opList=system.cpu2.fuPool.FUList4.opList | 1533opList=system.cpu2.fuPool.FUList4.opList0 system.cpu2.fuPool.FUList4.opList1 |
| 1426 | 1534 |
| 1427[system.cpu2.fuPool.FUList4.opList] | 1535[system.cpu2.fuPool.FUList4.opList0] |
| 1428type=OpDesc 1429eventq_index=0 1430opClass=MemRead 1431opLat=1 1432pipelined=true 1433 | 1536type=OpDesc 1537eventq_index=0 1538opClass=MemRead 1539opLat=1 1540pipelined=true 1541 |
| 1542[system.cpu2.fuPool.FUList4.opList1] 1543type=OpDesc 1544eventq_index=0 1545opClass=FloatMemRead 1546opLat=1 1547pipelined=true 1548 |
|
| 1434[system.cpu2.fuPool.FUList5] 1435type=FUDesc 1436children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1437count=4 1438eventq_index=0 1439opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 1440 1441[system.cpu2.fuPool.FUList5.opList00] --- 133 unchanged lines hidden (view full) --- 1575type=OpDesc 1576eventq_index=0 1577opClass=SimdFloatSqrt 1578opLat=1 1579pipelined=true 1580 1581[system.cpu2.fuPool.FUList6] 1582type=FUDesc | 1549[system.cpu2.fuPool.FUList5] 1550type=FUDesc 1551children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1552count=4 1553eventq_index=0 1554opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 1555 1556[system.cpu2.fuPool.FUList5.opList00] --- 133 unchanged lines hidden (view full) --- 1690type=OpDesc 1691eventq_index=0 1692opClass=SimdFloatSqrt 1693opLat=1 1694pipelined=true 1695 1696[system.cpu2.fuPool.FUList6] 1697type=FUDesc |
| 1583children=opList | 1698children=opList0 opList1 |
| 1584count=0 1585eventq_index=0 | 1699count=0 1700eventq_index=0 |
| 1586opList=system.cpu2.fuPool.FUList6.opList | 1701opList=system.cpu2.fuPool.FUList6.opList0 system.cpu2.fuPool.FUList6.opList1 |
| 1587 | 1702 |
| 1588[system.cpu2.fuPool.FUList6.opList] | 1703[system.cpu2.fuPool.FUList6.opList0] |
| 1589type=OpDesc 1590eventq_index=0 1591opClass=MemWrite 1592opLat=1 1593pipelined=true 1594 | 1704type=OpDesc 1705eventq_index=0 1706opClass=MemWrite 1707opLat=1 1708pipelined=true 1709 |
| 1710[system.cpu2.fuPool.FUList6.opList1] 1711type=OpDesc 1712eventq_index=0 1713opClass=FloatMemWrite 1714opLat=1 1715pipelined=true 1716 |
|
| 1595[system.cpu2.fuPool.FUList7] 1596type=FUDesc | 1717[system.cpu2.fuPool.FUList7] 1718type=FUDesc |
| 1597children=opList0 opList1 | 1719children=opList0 opList1 opList2 opList3 |
| 1598count=4 1599eventq_index=0 | 1720count=4 1721eventq_index=0 |
| 1600opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 | 1722opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 system.cpu2.fuPool.FUList7.opList2 system.cpu2.fuPool.FUList7.opList3 |
| 1601 1602[system.cpu2.fuPool.FUList7.opList0] 1603type=OpDesc 1604eventq_index=0 1605opClass=MemRead 1606opLat=1 1607pipelined=true 1608 1609[system.cpu2.fuPool.FUList7.opList1] 1610type=OpDesc 1611eventq_index=0 1612opClass=MemWrite 1613opLat=1 1614pipelined=true 1615 | 1723 1724[system.cpu2.fuPool.FUList7.opList0] 1725type=OpDesc 1726eventq_index=0 1727opClass=MemRead 1728opLat=1 1729pipelined=true 1730 1731[system.cpu2.fuPool.FUList7.opList1] 1732type=OpDesc 1733eventq_index=0 1734opClass=MemWrite 1735opLat=1 1736pipelined=true 1737 |
| 1738[system.cpu2.fuPool.FUList7.opList2] 1739type=OpDesc 1740eventq_index=0 1741opClass=FloatMemRead 1742opLat=1 1743pipelined=true 1744 1745[system.cpu2.fuPool.FUList7.opList3] 1746type=OpDesc 1747eventq_index=0 1748opClass=FloatMemWrite 1749opLat=1 1750pipelined=true 1751 |
|
| 1616[system.cpu2.fuPool.FUList8] 1617type=FUDesc 1618children=opList 1619count=1 1620eventq_index=0 1621opList=system.cpu2.fuPool.FUList8.opList 1622 1623[system.cpu2.fuPool.FUList8.opList] --- 5 unchanged lines hidden (view full) --- 1629 1630[system.cpu2.icache] 1631type=Cache 1632children=tags 1633addr_ranges=0:18446744073709551615:0:0:0:0 1634assoc=1 1635clk_domain=system.cpu_clk_domain 1636clusivity=mostly_incl | 1752[system.cpu2.fuPool.FUList8] 1753type=FUDesc 1754children=opList 1755count=1 1756eventq_index=0 1757opList=system.cpu2.fuPool.FUList8.opList 1758 1759[system.cpu2.fuPool.FUList8.opList] --- 5 unchanged lines hidden (view full) --- 1765 1766[system.cpu2.icache] 1767type=Cache 1768children=tags 1769addr_ranges=0:18446744073709551615:0:0:0:0 1770assoc=1 1771clk_domain=system.cpu_clk_domain 1772clusivity=mostly_incl |
| 1773data_latency=2 |
|
| 1637default_p_state=UNDEFINED 1638demand_mshr_reserve=1 1639eventq_index=0 | 1774default_p_state=UNDEFINED 1775demand_mshr_reserve=1 1776eventq_index=0 |
| 1640hit_latency=2 | |
| 1641is_read_only=true 1642max_miss_count=0 1643mshrs=4 1644p_state_clk_gate_bins=20 1645p_state_clk_gate_max=1000000000000 1646p_state_clk_gate_min=1000 1647power_model=Null 1648prefetch_on_access=false 1649prefetcher=Null 1650response_latency=2 1651sequential_access=false 1652size=32768 1653system=system | 1777is_read_only=true 1778max_miss_count=0 1779mshrs=4 1780p_state_clk_gate_bins=20 1781p_state_clk_gate_max=1000000000000 1782p_state_clk_gate_min=1000 1783power_model=Null 1784prefetch_on_access=false 1785prefetcher=Null 1786response_latency=2 1787sequential_access=false 1788size=32768 1789system=system |
| 1790tag_latency=2 |
|
| 1654tags=system.cpu2.icache.tags 1655tgts_per_mshr=20 1656write_buffers=8 1657writeback_clean=true 1658cpu_side=system.cpu2.icache_port 1659mem_side=system.toL2Bus.slave[4] 1660 1661[system.cpu2.icache.tags] 1662type=LRU 1663assoc=1 1664block_size=64 1665clk_domain=system.cpu_clk_domain | 1791tags=system.cpu2.icache.tags 1792tgts_per_mshr=20 1793write_buffers=8 1794writeback_clean=true 1795cpu_side=system.cpu2.icache_port 1796mem_side=system.toL2Bus.slave[4] 1797 1798[system.cpu2.icache.tags] 1799type=LRU 1800assoc=1 1801block_size=64 1802clk_domain=system.cpu_clk_domain |
| 1803data_latency=2 |
|
| 1666default_p_state=UNDEFINED 1667eventq_index=0 | 1804default_p_state=UNDEFINED 1805eventq_index=0 |
| 1668hit_latency=2 | |
| 1669p_state_clk_gate_bins=20 1670p_state_clk_gate_max=1000000000000 1671p_state_clk_gate_min=1000 1672power_model=Null 1673sequential_access=false 1674size=32768 | 1806p_state_clk_gate_bins=20 1807p_state_clk_gate_max=1000000000000 1808p_state_clk_gate_min=1000 1809power_model=Null 1810sequential_access=false 1811size=32768 |
| 1812tag_latency=2 |
|
| 1675 1676[system.cpu2.interrupts] 1677type=SparcInterrupts 1678eventq_index=0 1679 1680[system.cpu2.isa] 1681type=SparcISA 1682eventq_index=0 --- 126 unchanged lines hidden (view full) --- 1809 1810[system.cpu3.dcache] 1811type=Cache 1812children=tags 1813addr_ranges=0:18446744073709551615:0:0:0:0 1814assoc=4 1815clk_domain=system.cpu_clk_domain 1816clusivity=mostly_incl | 1813 1814[system.cpu2.interrupts] 1815type=SparcInterrupts 1816eventq_index=0 1817 1818[system.cpu2.isa] 1819type=SparcISA 1820eventq_index=0 --- 126 unchanged lines hidden (view full) --- 1947 1948[system.cpu3.dcache] 1949type=Cache 1950children=tags 1951addr_ranges=0:18446744073709551615:0:0:0:0 1952assoc=4 1953clk_domain=system.cpu_clk_domain 1954clusivity=mostly_incl |
| 1955data_latency=2 |
|
| 1817default_p_state=UNDEFINED 1818demand_mshr_reserve=1 1819eventq_index=0 | 1956default_p_state=UNDEFINED 1957demand_mshr_reserve=1 1958eventq_index=0 |
| 1820hit_latency=2 | |
| 1821is_read_only=false 1822max_miss_count=0 1823mshrs=4 1824p_state_clk_gate_bins=20 1825p_state_clk_gate_max=1000000000000 1826p_state_clk_gate_min=1000 1827power_model=Null 1828prefetch_on_access=false 1829prefetcher=Null 1830response_latency=2 1831sequential_access=false 1832size=32768 1833system=system | 1959is_read_only=false 1960max_miss_count=0 1961mshrs=4 1962p_state_clk_gate_bins=20 1963p_state_clk_gate_max=1000000000000 1964p_state_clk_gate_min=1000 1965power_model=Null 1966prefetch_on_access=false 1967prefetcher=Null 1968response_latency=2 1969sequential_access=false 1970size=32768 1971system=system |
| 1972tag_latency=2 |
|
| 1834tags=system.cpu3.dcache.tags 1835tgts_per_mshr=20 1836write_buffers=8 1837writeback_clean=false 1838cpu_side=system.cpu3.dcache_port 1839mem_side=system.toL2Bus.slave[7] 1840 1841[system.cpu3.dcache.tags] 1842type=LRU 1843assoc=4 1844block_size=64 1845clk_domain=system.cpu_clk_domain | 1973tags=system.cpu3.dcache.tags 1974tgts_per_mshr=20 1975write_buffers=8 1976writeback_clean=false 1977cpu_side=system.cpu3.dcache_port 1978mem_side=system.toL2Bus.slave[7] 1979 1980[system.cpu3.dcache.tags] 1981type=LRU 1982assoc=4 1983block_size=64 1984clk_domain=system.cpu_clk_domain |
| 1985data_latency=2 |
|
| 1846default_p_state=UNDEFINED 1847eventq_index=0 | 1986default_p_state=UNDEFINED 1987eventq_index=0 |
| 1848hit_latency=2 | |
| 1849p_state_clk_gate_bins=20 1850p_state_clk_gate_max=1000000000000 1851p_state_clk_gate_min=1000 1852power_model=Null 1853sequential_access=false 1854size=32768 | 1988p_state_clk_gate_bins=20 1989p_state_clk_gate_max=1000000000000 1990p_state_clk_gate_min=1000 1991power_model=Null 1992sequential_access=false 1993size=32768 |
| 1994tag_latency=2 |
|
| 1855 1856[system.cpu3.dtb] 1857type=SparcTLB 1858eventq_index=0 1859size=64 1860 1861[system.cpu3.fuPool] 1862type=FUPool --- 61 unchanged lines hidden (view full) --- 1924type=OpDesc 1925eventq_index=0 1926opClass=FloatCvt 1927opLat=2 1928pipelined=true 1929 1930[system.cpu3.fuPool.FUList3] 1931type=FUDesc | 1995 1996[system.cpu3.dtb] 1997type=SparcTLB 1998eventq_index=0 1999size=64 2000 2001[system.cpu3.fuPool] 2002type=FUPool --- 61 unchanged lines hidden (view full) --- 2064type=OpDesc 2065eventq_index=0 2066opClass=FloatCvt 2067opLat=2 2068pipelined=true 2069 2070[system.cpu3.fuPool.FUList3] 2071type=FUDesc |
| 1932children=opList0 opList1 opList2 | 2072children=opList0 opList1 opList2 opList3 opList4 |
| 1933count=2 1934eventq_index=0 | 2073count=2 2074eventq_index=0 |
| 1935opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 | 2075opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 system.cpu3.fuPool.FUList3.opList3 system.cpu3.fuPool.FUList3.opList4 |
| 1936 1937[system.cpu3.fuPool.FUList3.opList0] 1938type=OpDesc 1939eventq_index=0 1940opClass=FloatMult 1941opLat=4 1942pipelined=true 1943 1944[system.cpu3.fuPool.FUList3.opList1] 1945type=OpDesc 1946eventq_index=0 | 2076 2077[system.cpu3.fuPool.FUList3.opList0] 2078type=OpDesc 2079eventq_index=0 2080opClass=FloatMult 2081opLat=4 2082pipelined=true 2083 2084[system.cpu3.fuPool.FUList3.opList1] 2085type=OpDesc 2086eventq_index=0 |
| 2087opClass=FloatMultAcc 2088opLat=5 2089pipelined=true 2090 2091[system.cpu3.fuPool.FUList3.opList2] 2092type=OpDesc 2093eventq_index=0 2094opClass=FloatMisc 2095opLat=3 2096pipelined=true 2097 2098[system.cpu3.fuPool.FUList3.opList3] 2099type=OpDesc 2100eventq_index=0 |
|
| 1947opClass=FloatDiv 1948opLat=12 1949pipelined=false 1950 | 2101opClass=FloatDiv 2102opLat=12 2103pipelined=false 2104 |
| 1951[system.cpu3.fuPool.FUList3.opList2] | 2105[system.cpu3.fuPool.FUList3.opList4] |
| 1952type=OpDesc 1953eventq_index=0 1954opClass=FloatSqrt 1955opLat=24 1956pipelined=false 1957 1958[system.cpu3.fuPool.FUList4] 1959type=FUDesc | 2106type=OpDesc 2107eventq_index=0 2108opClass=FloatSqrt 2109opLat=24 2110pipelined=false 2111 2112[system.cpu3.fuPool.FUList4] 2113type=FUDesc |
| 1960children=opList | 2114children=opList0 opList1 |
| 1961count=0 1962eventq_index=0 | 2115count=0 2116eventq_index=0 |
| 1963opList=system.cpu3.fuPool.FUList4.opList | 2117opList=system.cpu3.fuPool.FUList4.opList0 system.cpu3.fuPool.FUList4.opList1 |
| 1964 | 2118 |
| 1965[system.cpu3.fuPool.FUList4.opList] | 2119[system.cpu3.fuPool.FUList4.opList0] |
| 1966type=OpDesc 1967eventq_index=0 1968opClass=MemRead 1969opLat=1 1970pipelined=true 1971 | 2120type=OpDesc 2121eventq_index=0 2122opClass=MemRead 2123opLat=1 2124pipelined=true 2125 |
| 2126[system.cpu3.fuPool.FUList4.opList1] 2127type=OpDesc 2128eventq_index=0 2129opClass=FloatMemRead 2130opLat=1 2131pipelined=true 2132 |
|
| 1972[system.cpu3.fuPool.FUList5] 1973type=FUDesc 1974children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1975count=4 1976eventq_index=0 1977opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 1978 1979[system.cpu3.fuPool.FUList5.opList00] --- 133 unchanged lines hidden (view full) --- 2113type=OpDesc 2114eventq_index=0 2115opClass=SimdFloatSqrt 2116opLat=1 2117pipelined=true 2118 2119[system.cpu3.fuPool.FUList6] 2120type=FUDesc | 2133[system.cpu3.fuPool.FUList5] 2134type=FUDesc 2135children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 2136count=4 2137eventq_index=0 2138opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 2139 2140[system.cpu3.fuPool.FUList5.opList00] --- 133 unchanged lines hidden (view full) --- 2274type=OpDesc 2275eventq_index=0 2276opClass=SimdFloatSqrt 2277opLat=1 2278pipelined=true 2279 2280[system.cpu3.fuPool.FUList6] 2281type=FUDesc |
| 2121children=opList | 2282children=opList0 opList1 |
| 2122count=0 2123eventq_index=0 | 2283count=0 2284eventq_index=0 |
| 2124opList=system.cpu3.fuPool.FUList6.opList | 2285opList=system.cpu3.fuPool.FUList6.opList0 system.cpu3.fuPool.FUList6.opList1 |
| 2125 | 2286 |
| 2126[system.cpu3.fuPool.FUList6.opList] | 2287[system.cpu3.fuPool.FUList6.opList0] |
| 2127type=OpDesc 2128eventq_index=0 2129opClass=MemWrite 2130opLat=1 2131pipelined=true 2132 | 2288type=OpDesc 2289eventq_index=0 2290opClass=MemWrite 2291opLat=1 2292pipelined=true 2293 |
| 2294[system.cpu3.fuPool.FUList6.opList1] 2295type=OpDesc 2296eventq_index=0 2297opClass=FloatMemWrite 2298opLat=1 2299pipelined=true 2300 |
|
| 2133[system.cpu3.fuPool.FUList7] 2134type=FUDesc | 2301[system.cpu3.fuPool.FUList7] 2302type=FUDesc |
| 2135children=opList0 opList1 | 2303children=opList0 opList1 opList2 opList3 |
| 2136count=4 2137eventq_index=0 | 2304count=4 2305eventq_index=0 |
| 2138opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 | 2306opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 system.cpu3.fuPool.FUList7.opList2 system.cpu3.fuPool.FUList7.opList3 |
| 2139 2140[system.cpu3.fuPool.FUList7.opList0] 2141type=OpDesc 2142eventq_index=0 2143opClass=MemRead 2144opLat=1 2145pipelined=true 2146 2147[system.cpu3.fuPool.FUList7.opList1] 2148type=OpDesc 2149eventq_index=0 2150opClass=MemWrite 2151opLat=1 2152pipelined=true 2153 | 2307 2308[system.cpu3.fuPool.FUList7.opList0] 2309type=OpDesc 2310eventq_index=0 2311opClass=MemRead 2312opLat=1 2313pipelined=true 2314 2315[system.cpu3.fuPool.FUList7.opList1] 2316type=OpDesc 2317eventq_index=0 2318opClass=MemWrite 2319opLat=1 2320pipelined=true 2321 |
| 2322[system.cpu3.fuPool.FUList7.opList2] 2323type=OpDesc 2324eventq_index=0 2325opClass=FloatMemRead 2326opLat=1 2327pipelined=true 2328 2329[system.cpu3.fuPool.FUList7.opList3] 2330type=OpDesc 2331eventq_index=0 2332opClass=FloatMemWrite 2333opLat=1 2334pipelined=true 2335 |
|
| 2154[system.cpu3.fuPool.FUList8] 2155type=FUDesc 2156children=opList 2157count=1 2158eventq_index=0 2159opList=system.cpu3.fuPool.FUList8.opList 2160 2161[system.cpu3.fuPool.FUList8.opList] --- 5 unchanged lines hidden (view full) --- 2167 2168[system.cpu3.icache] 2169type=Cache 2170children=tags 2171addr_ranges=0:18446744073709551615:0:0:0:0 2172assoc=1 2173clk_domain=system.cpu_clk_domain 2174clusivity=mostly_incl | 2336[system.cpu3.fuPool.FUList8] 2337type=FUDesc 2338children=opList 2339count=1 2340eventq_index=0 2341opList=system.cpu3.fuPool.FUList8.opList 2342 2343[system.cpu3.fuPool.FUList8.opList] --- 5 unchanged lines hidden (view full) --- 2349 2350[system.cpu3.icache] 2351type=Cache 2352children=tags 2353addr_ranges=0:18446744073709551615:0:0:0:0 2354assoc=1 2355clk_domain=system.cpu_clk_domain 2356clusivity=mostly_incl |
| 2357data_latency=2 |
|
| 2175default_p_state=UNDEFINED 2176demand_mshr_reserve=1 2177eventq_index=0 | 2358default_p_state=UNDEFINED 2359demand_mshr_reserve=1 2360eventq_index=0 |
| 2178hit_latency=2 | |
| 2179is_read_only=true 2180max_miss_count=0 2181mshrs=4 2182p_state_clk_gate_bins=20 2183p_state_clk_gate_max=1000000000000 2184p_state_clk_gate_min=1000 2185power_model=Null 2186prefetch_on_access=false 2187prefetcher=Null 2188response_latency=2 2189sequential_access=false 2190size=32768 2191system=system | 2361is_read_only=true 2362max_miss_count=0 2363mshrs=4 2364p_state_clk_gate_bins=20 2365p_state_clk_gate_max=1000000000000 2366p_state_clk_gate_min=1000 2367power_model=Null 2368prefetch_on_access=false 2369prefetcher=Null 2370response_latency=2 2371sequential_access=false 2372size=32768 2373system=system |
| 2374tag_latency=2 |
|
| 2192tags=system.cpu3.icache.tags 2193tgts_per_mshr=20 2194write_buffers=8 2195writeback_clean=true 2196cpu_side=system.cpu3.icache_port 2197mem_side=system.toL2Bus.slave[6] 2198 2199[system.cpu3.icache.tags] 2200type=LRU 2201assoc=1 2202block_size=64 2203clk_domain=system.cpu_clk_domain | 2375tags=system.cpu3.icache.tags 2376tgts_per_mshr=20 2377write_buffers=8 2378writeback_clean=true 2379cpu_side=system.cpu3.icache_port 2380mem_side=system.toL2Bus.slave[6] 2381 2382[system.cpu3.icache.tags] 2383type=LRU 2384assoc=1 2385block_size=64 2386clk_domain=system.cpu_clk_domain |
| 2387data_latency=2 |
|
| 2204default_p_state=UNDEFINED 2205eventq_index=0 | 2388default_p_state=UNDEFINED 2389eventq_index=0 |
| 2206hit_latency=2 | |
| 2207p_state_clk_gate_bins=20 2208p_state_clk_gate_max=1000000000000 2209p_state_clk_gate_min=1000 2210power_model=Null 2211sequential_access=false 2212size=32768 | 2390p_state_clk_gate_bins=20 2391p_state_clk_gate_max=1000000000000 2392p_state_clk_gate_min=1000 2393power_model=Null 2394sequential_access=false 2395size=32768 |
| 2396tag_latency=2 |
|
| 2213 2214[system.cpu3.interrupts] 2215type=SparcInterrupts 2216eventq_index=0 2217 2218[system.cpu3.isa] 2219type=SparcISA 2220eventq_index=0 --- 25 unchanged lines hidden (view full) --- 2246 2247[system.l2c] 2248type=Cache 2249children=tags 2250addr_ranges=0:18446744073709551615:0:0:0:0 2251assoc=8 2252clk_domain=system.cpu_clk_domain 2253clusivity=mostly_incl | 2397 2398[system.cpu3.interrupts] 2399type=SparcInterrupts 2400eventq_index=0 2401 2402[system.cpu3.isa] 2403type=SparcISA 2404eventq_index=0 --- 25 unchanged lines hidden (view full) --- 2430 2431[system.l2c] 2432type=Cache 2433children=tags 2434addr_ranges=0:18446744073709551615:0:0:0:0 2435assoc=8 2436clk_domain=system.cpu_clk_domain 2437clusivity=mostly_incl |
| 2438data_latency=20 |
|
| 2254default_p_state=UNDEFINED 2255demand_mshr_reserve=1 2256eventq_index=0 | 2439default_p_state=UNDEFINED 2440demand_mshr_reserve=1 2441eventq_index=0 |
| 2257hit_latency=20 | |
| 2258is_read_only=false 2259max_miss_count=0 2260mshrs=20 2261p_state_clk_gate_bins=20 2262p_state_clk_gate_max=1000000000000 2263p_state_clk_gate_min=1000 2264power_model=Null 2265prefetch_on_access=false 2266prefetcher=Null 2267response_latency=20 2268sequential_access=false 2269size=4194304 2270system=system | 2442is_read_only=false 2443max_miss_count=0 2444mshrs=20 2445p_state_clk_gate_bins=20 2446p_state_clk_gate_max=1000000000000 2447p_state_clk_gate_min=1000 2448power_model=Null 2449prefetch_on_access=false 2450prefetcher=Null 2451response_latency=20 2452sequential_access=false 2453size=4194304 2454system=system |
| 2455tag_latency=20 |
|
| 2271tags=system.l2c.tags 2272tgts_per_mshr=12 2273write_buffers=8 2274writeback_clean=false 2275cpu_side=system.toL2Bus.master[0] 2276mem_side=system.membus.slave[1] 2277 2278[system.l2c.tags] 2279type=LRU 2280assoc=8 2281block_size=64 2282clk_domain=system.cpu_clk_domain | 2456tags=system.l2c.tags 2457tgts_per_mshr=12 2458write_buffers=8 2459writeback_clean=false 2460cpu_side=system.toL2Bus.master[0] 2461mem_side=system.membus.slave[1] 2462 2463[system.l2c.tags] 2464type=LRU 2465assoc=8 2466block_size=64 2467clk_domain=system.cpu_clk_domain |
| 2468data_latency=20 |
|
| 2283default_p_state=UNDEFINED 2284eventq_index=0 | 2469default_p_state=UNDEFINED 2470eventq_index=0 |
| 2285hit_latency=20 | |
| 2286p_state_clk_gate_bins=20 2287p_state_clk_gate_max=1000000000000 2288p_state_clk_gate_min=1000 2289power_model=Null 2290sequential_access=false 2291size=4194304 | 2471p_state_clk_gate_bins=20 2472p_state_clk_gate_max=1000000000000 2473p_state_clk_gate_min=1000 2474power_model=Null 2475sequential_access=false 2476size=4194304 |
| 2477tag_latency=20 |
|
| 2292 2293[system.membus] 2294type=CoherentXBar 2295children=snoop_filter 2296clk_domain=system.clk_domain 2297default_p_state=UNDEFINED 2298eventq_index=0 2299forward_latency=4 --- 139 unchanged lines hidden --- | 2478 2479[system.membus] 2480type=CoherentXBar 2481children=snoop_filter 2482clk_domain=system.clk_domain 2483default_p_state=UNDEFINED 2484eventq_index=0 2485forward_latency=4 --- 139 unchanged lines hidden --- |