1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 163 unchanged lines hidden (view full) --- 172 173[system.cpu0.dcache] 174type=Cache 175children=tags 176addr_ranges=0:18446744073709551615:0:0:0:0 177assoc=4 178clk_domain=system.cpu_clk_domain 179clusivity=mostly_incl |
180data_latency=2 |
181default_p_state=UNDEFINED 182demand_mshr_reserve=1 183eventq_index=0 |
184is_read_only=false 185max_miss_count=0 186mshrs=4 187p_state_clk_gate_bins=20 188p_state_clk_gate_max=1000000000000 189p_state_clk_gate_min=1000 190power_model=Null 191prefetch_on_access=false 192prefetcher=Null 193response_latency=2 194sequential_access=false 195size=32768 196system=system |
197tag_latency=2 |
198tags=system.cpu0.dcache.tags 199tgts_per_mshr=20 200write_buffers=8 201writeback_clean=false 202cpu_side=system.cpu0.dcache_port 203mem_side=system.toL2Bus.slave[1] 204 205[system.cpu0.dcache.tags] 206type=LRU 207assoc=4 208block_size=64 209clk_domain=system.cpu_clk_domain |
210data_latency=2 |
211default_p_state=UNDEFINED 212eventq_index=0 |
213p_state_clk_gate_bins=20 214p_state_clk_gate_max=1000000000000 215p_state_clk_gate_min=1000 216power_model=Null 217sequential_access=false 218size=32768 |
219tag_latency=2 |
220 221[system.cpu0.dtb] 222type=SparcTLB 223eventq_index=0 224size=64 225 226[system.cpu0.fuPool] 227type=FUPool --- 61 unchanged lines hidden (view full) --- 289type=OpDesc 290eventq_index=0 291opClass=FloatCvt 292opLat=2 293pipelined=true 294 295[system.cpu0.fuPool.FUList3] 296type=FUDesc |
297children=opList0 opList1 opList2 opList3 opList4 |
298count=2 299eventq_index=0 |
300opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 system.cpu0.fuPool.FUList3.opList3 system.cpu0.fuPool.FUList3.opList4 |
301 302[system.cpu0.fuPool.FUList3.opList0] 303type=OpDesc 304eventq_index=0 305opClass=FloatMult 306opLat=4 307pipelined=true 308 309[system.cpu0.fuPool.FUList3.opList1] 310type=OpDesc 311eventq_index=0 |
312opClass=FloatMultAcc 313opLat=5 314pipelined=true 315 316[system.cpu0.fuPool.FUList3.opList2] 317type=OpDesc 318eventq_index=0 319opClass=FloatMisc 320opLat=3 321pipelined=true 322 323[system.cpu0.fuPool.FUList3.opList3] 324type=OpDesc 325eventq_index=0 |
326opClass=FloatDiv 327opLat=12 328pipelined=false 329 |
330[system.cpu0.fuPool.FUList3.opList4] |
331type=OpDesc 332eventq_index=0 333opClass=FloatSqrt 334opLat=24 335pipelined=false 336 337[system.cpu0.fuPool.FUList4] 338type=FUDesc |
339children=opList0 opList1 |
340count=0 341eventq_index=0 |
342opList=system.cpu0.fuPool.FUList4.opList0 system.cpu0.fuPool.FUList4.opList1 |
343 |
344[system.cpu0.fuPool.FUList4.opList0] |
345type=OpDesc 346eventq_index=0 347opClass=MemRead 348opLat=1 349pipelined=true 350 |
351[system.cpu0.fuPool.FUList4.opList1] 352type=OpDesc 353eventq_index=0 354opClass=FloatMemRead 355opLat=1 356pipelined=true 357 |
358[system.cpu0.fuPool.FUList5] 359type=FUDesc 360children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 361count=4 362eventq_index=0 363opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 364 365[system.cpu0.fuPool.FUList5.opList00] --- 133 unchanged lines hidden (view full) --- 499type=OpDesc 500eventq_index=0 501opClass=SimdFloatSqrt 502opLat=1 503pipelined=true 504 505[system.cpu0.fuPool.FUList6] 506type=FUDesc |
507children=opList0 opList1 |
508count=0 509eventq_index=0 |
510opList=system.cpu0.fuPool.FUList6.opList0 system.cpu0.fuPool.FUList6.opList1 |
511 |
512[system.cpu0.fuPool.FUList6.opList0] |
513type=OpDesc 514eventq_index=0 515opClass=MemWrite 516opLat=1 517pipelined=true 518 |
519[system.cpu0.fuPool.FUList6.opList1] 520type=OpDesc 521eventq_index=0 522opClass=FloatMemWrite 523opLat=1 524pipelined=true 525 |
526[system.cpu0.fuPool.FUList7] 527type=FUDesc |
528children=opList0 opList1 opList2 opList3 |
529count=4 530eventq_index=0 |
531opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 system.cpu0.fuPool.FUList7.opList2 system.cpu0.fuPool.FUList7.opList3 |
532 533[system.cpu0.fuPool.FUList7.opList0] 534type=OpDesc 535eventq_index=0 536opClass=MemRead 537opLat=1 538pipelined=true 539 540[system.cpu0.fuPool.FUList7.opList1] 541type=OpDesc 542eventq_index=0 543opClass=MemWrite 544opLat=1 545pipelined=true 546 |
547[system.cpu0.fuPool.FUList7.opList2] 548type=OpDesc 549eventq_index=0 550opClass=FloatMemRead 551opLat=1 552pipelined=true 553 554[system.cpu0.fuPool.FUList7.opList3] 555type=OpDesc 556eventq_index=0 557opClass=FloatMemWrite 558opLat=1 559pipelined=true 560 |
561[system.cpu0.fuPool.FUList8] 562type=FUDesc 563children=opList 564count=1 565eventq_index=0 566opList=system.cpu0.fuPool.FUList8.opList 567 568[system.cpu0.fuPool.FUList8.opList] --- 5 unchanged lines hidden (view full) --- 574 575[system.cpu0.icache] 576type=Cache 577children=tags 578addr_ranges=0:18446744073709551615:0:0:0:0 579assoc=1 580clk_domain=system.cpu_clk_domain 581clusivity=mostly_incl |
582data_latency=2 |
583default_p_state=UNDEFINED 584demand_mshr_reserve=1 585eventq_index=0 |
586is_read_only=true 587max_miss_count=0 588mshrs=4 589p_state_clk_gate_bins=20 590p_state_clk_gate_max=1000000000000 591p_state_clk_gate_min=1000 592power_model=Null 593prefetch_on_access=false 594prefetcher=Null 595response_latency=2 596sequential_access=false 597size=32768 598system=system |
599tag_latency=2 |
600tags=system.cpu0.icache.tags 601tgts_per_mshr=20 602write_buffers=8 603writeback_clean=true 604cpu_side=system.cpu0.icache_port 605mem_side=system.toL2Bus.slave[0] 606 607[system.cpu0.icache.tags] 608type=LRU 609assoc=1 610block_size=64 611clk_domain=system.cpu_clk_domain |
612data_latency=2 |
613default_p_state=UNDEFINED 614eventq_index=0 |
615p_state_clk_gate_bins=20 616p_state_clk_gate_max=1000000000000 617p_state_clk_gate_min=1000 618power_model=Null 619sequential_access=false 620size=32768 |
621tag_latency=2 |
622 623[system.cpu0.interrupts] 624type=SparcInterrupts 625eventq_index=0 626 627[system.cpu0.isa] 628type=SparcISA 629eventq_index=0 --- 12 unchanged lines hidden (view full) --- 642cmd=test_atomic 4 643cwd= 644drivers= 645egid=100 646env= 647errout=cerr 648euid=100 649eventq_index=0 |
650executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic |
651gid=100 652input=cin 653kvmInSE=false 654max_stack_size=67108864 655output=cout 656pid=100 657ppid=99 658simpoint=0 --- 120 unchanged lines hidden (view full) --- 779 780[system.cpu1.dcache] 781type=Cache 782children=tags 783addr_ranges=0:18446744073709551615:0:0:0:0 784assoc=4 785clk_domain=system.cpu_clk_domain 786clusivity=mostly_incl |
787data_latency=2 |
788default_p_state=UNDEFINED 789demand_mshr_reserve=1 790eventq_index=0 |
791is_read_only=false 792max_miss_count=0 793mshrs=4 794p_state_clk_gate_bins=20 795p_state_clk_gate_max=1000000000000 796p_state_clk_gate_min=1000 797power_model=Null 798prefetch_on_access=false 799prefetcher=Null 800response_latency=2 801sequential_access=false 802size=32768 803system=system |
804tag_latency=2 |
805tags=system.cpu1.dcache.tags 806tgts_per_mshr=20 807write_buffers=8 808writeback_clean=false 809cpu_side=system.cpu1.dcache_port 810mem_side=system.toL2Bus.slave[3] 811 812[system.cpu1.dcache.tags] 813type=LRU 814assoc=4 815block_size=64 816clk_domain=system.cpu_clk_domain |
817data_latency=2 |
818default_p_state=UNDEFINED 819eventq_index=0 |
820p_state_clk_gate_bins=20 821p_state_clk_gate_max=1000000000000 822p_state_clk_gate_min=1000 823power_model=Null 824sequential_access=false 825size=32768 |
826tag_latency=2 |
827 828[system.cpu1.dtb] 829type=SparcTLB 830eventq_index=0 831size=64 832 833[system.cpu1.fuPool] 834type=FUPool --- 61 unchanged lines hidden (view full) --- 896type=OpDesc 897eventq_index=0 898opClass=FloatCvt 899opLat=2 900pipelined=true 901 902[system.cpu1.fuPool.FUList3] 903type=FUDesc |
904children=opList0 opList1 opList2 opList3 opList4 |
905count=2 906eventq_index=0 |
907opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 system.cpu1.fuPool.FUList3.opList3 system.cpu1.fuPool.FUList3.opList4 |
908 909[system.cpu1.fuPool.FUList3.opList0] 910type=OpDesc 911eventq_index=0 912opClass=FloatMult 913opLat=4 914pipelined=true 915 916[system.cpu1.fuPool.FUList3.opList1] 917type=OpDesc 918eventq_index=0 |
919opClass=FloatMultAcc 920opLat=5 921pipelined=true 922 923[system.cpu1.fuPool.FUList3.opList2] 924type=OpDesc 925eventq_index=0 926opClass=FloatMisc 927opLat=3 928pipelined=true 929 930[system.cpu1.fuPool.FUList3.opList3] 931type=OpDesc 932eventq_index=0 |
933opClass=FloatDiv 934opLat=12 935pipelined=false 936 |
937[system.cpu1.fuPool.FUList3.opList4] |
938type=OpDesc 939eventq_index=0 940opClass=FloatSqrt 941opLat=24 942pipelined=false 943 944[system.cpu1.fuPool.FUList4] 945type=FUDesc |
946children=opList0 opList1 |
947count=0 948eventq_index=0 |
949opList=system.cpu1.fuPool.FUList4.opList0 system.cpu1.fuPool.FUList4.opList1 |
950 |
951[system.cpu1.fuPool.FUList4.opList0] |
952type=OpDesc 953eventq_index=0 954opClass=MemRead 955opLat=1 956pipelined=true 957 |
958[system.cpu1.fuPool.FUList4.opList1] 959type=OpDesc 960eventq_index=0 961opClass=FloatMemRead 962opLat=1 963pipelined=true 964 |
965[system.cpu1.fuPool.FUList5] 966type=FUDesc 967children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 968count=4 969eventq_index=0 970opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 971 972[system.cpu1.fuPool.FUList5.opList00] --- 133 unchanged lines hidden (view full) --- 1106type=OpDesc 1107eventq_index=0 1108opClass=SimdFloatSqrt 1109opLat=1 1110pipelined=true 1111 1112[system.cpu1.fuPool.FUList6] 1113type=FUDesc |
1114children=opList0 opList1 |
1115count=0 1116eventq_index=0 |
1117opList=system.cpu1.fuPool.FUList6.opList0 system.cpu1.fuPool.FUList6.opList1 |
1118 |
1119[system.cpu1.fuPool.FUList6.opList0] |
1120type=OpDesc 1121eventq_index=0 1122opClass=MemWrite 1123opLat=1 1124pipelined=true 1125 |
1126[system.cpu1.fuPool.FUList6.opList1] 1127type=OpDesc 1128eventq_index=0 1129opClass=FloatMemWrite 1130opLat=1 1131pipelined=true 1132 |
1133[system.cpu1.fuPool.FUList7] 1134type=FUDesc |
1135children=opList0 opList1 opList2 opList3 |
1136count=4 1137eventq_index=0 |
1138opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 system.cpu1.fuPool.FUList7.opList2 system.cpu1.fuPool.FUList7.opList3 |
1139 1140[system.cpu1.fuPool.FUList7.opList0] 1141type=OpDesc 1142eventq_index=0 1143opClass=MemRead 1144opLat=1 1145pipelined=true 1146 1147[system.cpu1.fuPool.FUList7.opList1] 1148type=OpDesc 1149eventq_index=0 1150opClass=MemWrite 1151opLat=1 1152pipelined=true 1153 |
1154[system.cpu1.fuPool.FUList7.opList2] 1155type=OpDesc 1156eventq_index=0 1157opClass=FloatMemRead 1158opLat=1 1159pipelined=true 1160 1161[system.cpu1.fuPool.FUList7.opList3] 1162type=OpDesc 1163eventq_index=0 1164opClass=FloatMemWrite 1165opLat=1 1166pipelined=true 1167 |
1168[system.cpu1.fuPool.FUList8] 1169type=FUDesc 1170children=opList 1171count=1 1172eventq_index=0 1173opList=system.cpu1.fuPool.FUList8.opList 1174 1175[system.cpu1.fuPool.FUList8.opList] --- 5 unchanged lines hidden (view full) --- 1181 1182[system.cpu1.icache] 1183type=Cache 1184children=tags 1185addr_ranges=0:18446744073709551615:0:0:0:0 1186assoc=1 1187clk_domain=system.cpu_clk_domain 1188clusivity=mostly_incl |
1189data_latency=2 |
1190default_p_state=UNDEFINED 1191demand_mshr_reserve=1 1192eventq_index=0 |
1193is_read_only=true 1194max_miss_count=0 1195mshrs=4 1196p_state_clk_gate_bins=20 1197p_state_clk_gate_max=1000000000000 1198p_state_clk_gate_min=1000 1199power_model=Null 1200prefetch_on_access=false 1201prefetcher=Null 1202response_latency=2 1203sequential_access=false 1204size=32768 1205system=system |
1206tag_latency=2 |
1207tags=system.cpu1.icache.tags 1208tgts_per_mshr=20 1209write_buffers=8 1210writeback_clean=true 1211cpu_side=system.cpu1.icache_port 1212mem_side=system.toL2Bus.slave[2] 1213 1214[system.cpu1.icache.tags] 1215type=LRU 1216assoc=1 1217block_size=64 1218clk_domain=system.cpu_clk_domain |
1219data_latency=2 |
1220default_p_state=UNDEFINED 1221eventq_index=0 |
1222p_state_clk_gate_bins=20 1223p_state_clk_gate_max=1000000000000 1224p_state_clk_gate_min=1000 1225power_model=Null 1226sequential_access=false 1227size=32768 |
1228tag_latency=2 |
1229 1230[system.cpu1.interrupts] 1231type=SparcInterrupts 1232eventq_index=0 1233 1234[system.cpu1.isa] 1235type=SparcISA 1236eventq_index=0 --- 126 unchanged lines hidden (view full) --- 1363 1364[system.cpu2.dcache] 1365type=Cache 1366children=tags 1367addr_ranges=0:18446744073709551615:0:0:0:0 1368assoc=4 1369clk_domain=system.cpu_clk_domain 1370clusivity=mostly_incl |
1371data_latency=2 |
1372default_p_state=UNDEFINED 1373demand_mshr_reserve=1 1374eventq_index=0 |
1375is_read_only=false 1376max_miss_count=0 1377mshrs=4 1378p_state_clk_gate_bins=20 1379p_state_clk_gate_max=1000000000000 1380p_state_clk_gate_min=1000 1381power_model=Null 1382prefetch_on_access=false 1383prefetcher=Null 1384response_latency=2 1385sequential_access=false 1386size=32768 1387system=system |
1388tag_latency=2 |
1389tags=system.cpu2.dcache.tags 1390tgts_per_mshr=20 1391write_buffers=8 1392writeback_clean=false 1393cpu_side=system.cpu2.dcache_port 1394mem_side=system.toL2Bus.slave[5] 1395 1396[system.cpu2.dcache.tags] 1397type=LRU 1398assoc=4 1399block_size=64 1400clk_domain=system.cpu_clk_domain |
1401data_latency=2 |
1402default_p_state=UNDEFINED 1403eventq_index=0 |
1404p_state_clk_gate_bins=20 1405p_state_clk_gate_max=1000000000000 1406p_state_clk_gate_min=1000 1407power_model=Null 1408sequential_access=false 1409size=32768 |
1410tag_latency=2 |
1411 1412[system.cpu2.dtb] 1413type=SparcTLB 1414eventq_index=0 1415size=64 1416 1417[system.cpu2.fuPool] 1418type=FUPool --- 61 unchanged lines hidden (view full) --- 1480type=OpDesc 1481eventq_index=0 1482opClass=FloatCvt 1483opLat=2 1484pipelined=true 1485 1486[system.cpu2.fuPool.FUList3] 1487type=FUDesc |
1488children=opList0 opList1 opList2 opList3 opList4 |
1489count=2 1490eventq_index=0 |
1491opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 system.cpu2.fuPool.FUList3.opList3 system.cpu2.fuPool.FUList3.opList4 |
1492 1493[system.cpu2.fuPool.FUList3.opList0] 1494type=OpDesc 1495eventq_index=0 1496opClass=FloatMult 1497opLat=4 1498pipelined=true 1499 1500[system.cpu2.fuPool.FUList3.opList1] 1501type=OpDesc 1502eventq_index=0 |
1503opClass=FloatMultAcc 1504opLat=5 1505pipelined=true 1506 1507[system.cpu2.fuPool.FUList3.opList2] 1508type=OpDesc 1509eventq_index=0 1510opClass=FloatMisc 1511opLat=3 1512pipelined=true 1513 1514[system.cpu2.fuPool.FUList3.opList3] 1515type=OpDesc 1516eventq_index=0 |
1517opClass=FloatDiv 1518opLat=12 1519pipelined=false 1520 |
1521[system.cpu2.fuPool.FUList3.opList4] |
1522type=OpDesc 1523eventq_index=0 1524opClass=FloatSqrt 1525opLat=24 1526pipelined=false 1527 1528[system.cpu2.fuPool.FUList4] 1529type=FUDesc |
1530children=opList0 opList1 |
1531count=0 1532eventq_index=0 |
1533opList=system.cpu2.fuPool.FUList4.opList0 system.cpu2.fuPool.FUList4.opList1 |
1534 |
1535[system.cpu2.fuPool.FUList4.opList0] |
1536type=OpDesc 1537eventq_index=0 1538opClass=MemRead 1539opLat=1 1540pipelined=true 1541 |
1542[system.cpu2.fuPool.FUList4.opList1] 1543type=OpDesc 1544eventq_index=0 1545opClass=FloatMemRead 1546opLat=1 1547pipelined=true 1548 |
1549[system.cpu2.fuPool.FUList5] 1550type=FUDesc 1551children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1552count=4 1553eventq_index=0 1554opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 1555 1556[system.cpu2.fuPool.FUList5.opList00] --- 133 unchanged lines hidden (view full) --- 1690type=OpDesc 1691eventq_index=0 1692opClass=SimdFloatSqrt 1693opLat=1 1694pipelined=true 1695 1696[system.cpu2.fuPool.FUList6] 1697type=FUDesc |
1698children=opList0 opList1 |
1699count=0 1700eventq_index=0 |
1701opList=system.cpu2.fuPool.FUList6.opList0 system.cpu2.fuPool.FUList6.opList1 |
1702 |
1703[system.cpu2.fuPool.FUList6.opList0] |
1704type=OpDesc 1705eventq_index=0 1706opClass=MemWrite 1707opLat=1 1708pipelined=true 1709 |
1710[system.cpu2.fuPool.FUList6.opList1] 1711type=OpDesc 1712eventq_index=0 1713opClass=FloatMemWrite 1714opLat=1 1715pipelined=true 1716 |
1717[system.cpu2.fuPool.FUList7] 1718type=FUDesc |
1719children=opList0 opList1 opList2 opList3 |
1720count=4 1721eventq_index=0 |
1722opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 system.cpu2.fuPool.FUList7.opList2 system.cpu2.fuPool.FUList7.opList3 |
1723 1724[system.cpu2.fuPool.FUList7.opList0] 1725type=OpDesc 1726eventq_index=0 1727opClass=MemRead 1728opLat=1 1729pipelined=true 1730 1731[system.cpu2.fuPool.FUList7.opList1] 1732type=OpDesc 1733eventq_index=0 1734opClass=MemWrite 1735opLat=1 1736pipelined=true 1737 |
1738[system.cpu2.fuPool.FUList7.opList2] 1739type=OpDesc 1740eventq_index=0 1741opClass=FloatMemRead 1742opLat=1 1743pipelined=true 1744 1745[system.cpu2.fuPool.FUList7.opList3] 1746type=OpDesc 1747eventq_index=0 1748opClass=FloatMemWrite 1749opLat=1 1750pipelined=true 1751 |
1752[system.cpu2.fuPool.FUList8] 1753type=FUDesc 1754children=opList 1755count=1 1756eventq_index=0 1757opList=system.cpu2.fuPool.FUList8.opList 1758 1759[system.cpu2.fuPool.FUList8.opList] --- 5 unchanged lines hidden (view full) --- 1765 1766[system.cpu2.icache] 1767type=Cache 1768children=tags 1769addr_ranges=0:18446744073709551615:0:0:0:0 1770assoc=1 1771clk_domain=system.cpu_clk_domain 1772clusivity=mostly_incl |
1773data_latency=2 |
1774default_p_state=UNDEFINED 1775demand_mshr_reserve=1 1776eventq_index=0 |
1777is_read_only=true 1778max_miss_count=0 1779mshrs=4 1780p_state_clk_gate_bins=20 1781p_state_clk_gate_max=1000000000000 1782p_state_clk_gate_min=1000 1783power_model=Null 1784prefetch_on_access=false 1785prefetcher=Null 1786response_latency=2 1787sequential_access=false 1788size=32768 1789system=system |
1790tag_latency=2 |
1791tags=system.cpu2.icache.tags 1792tgts_per_mshr=20 1793write_buffers=8 1794writeback_clean=true 1795cpu_side=system.cpu2.icache_port 1796mem_side=system.toL2Bus.slave[4] 1797 1798[system.cpu2.icache.tags] 1799type=LRU 1800assoc=1 1801block_size=64 1802clk_domain=system.cpu_clk_domain |
1803data_latency=2 |
1804default_p_state=UNDEFINED 1805eventq_index=0 |
1806p_state_clk_gate_bins=20 1807p_state_clk_gate_max=1000000000000 1808p_state_clk_gate_min=1000 1809power_model=Null 1810sequential_access=false 1811size=32768 |
1812tag_latency=2 |
1813 1814[system.cpu2.interrupts] 1815type=SparcInterrupts 1816eventq_index=0 1817 1818[system.cpu2.isa] 1819type=SparcISA 1820eventq_index=0 --- 126 unchanged lines hidden (view full) --- 1947 1948[system.cpu3.dcache] 1949type=Cache 1950children=tags 1951addr_ranges=0:18446744073709551615:0:0:0:0 1952assoc=4 1953clk_domain=system.cpu_clk_domain 1954clusivity=mostly_incl |
1955data_latency=2 |
1956default_p_state=UNDEFINED 1957demand_mshr_reserve=1 1958eventq_index=0 |
1959is_read_only=false 1960max_miss_count=0 1961mshrs=4 1962p_state_clk_gate_bins=20 1963p_state_clk_gate_max=1000000000000 1964p_state_clk_gate_min=1000 1965power_model=Null 1966prefetch_on_access=false 1967prefetcher=Null 1968response_latency=2 1969sequential_access=false 1970size=32768 1971system=system |
1972tag_latency=2 |
1973tags=system.cpu3.dcache.tags 1974tgts_per_mshr=20 1975write_buffers=8 1976writeback_clean=false 1977cpu_side=system.cpu3.dcache_port 1978mem_side=system.toL2Bus.slave[7] 1979 1980[system.cpu3.dcache.tags] 1981type=LRU 1982assoc=4 1983block_size=64 1984clk_domain=system.cpu_clk_domain |
1985data_latency=2 |
1986default_p_state=UNDEFINED 1987eventq_index=0 |
1988p_state_clk_gate_bins=20 1989p_state_clk_gate_max=1000000000000 1990p_state_clk_gate_min=1000 1991power_model=Null 1992sequential_access=false 1993size=32768 |
1994tag_latency=2 |
1995 1996[system.cpu3.dtb] 1997type=SparcTLB 1998eventq_index=0 1999size=64 2000 2001[system.cpu3.fuPool] 2002type=FUPool --- 61 unchanged lines hidden (view full) --- 2064type=OpDesc 2065eventq_index=0 2066opClass=FloatCvt 2067opLat=2 2068pipelined=true 2069 2070[system.cpu3.fuPool.FUList3] 2071type=FUDesc |
2072children=opList0 opList1 opList2 opList3 opList4 |
2073count=2 2074eventq_index=0 |
2075opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 system.cpu3.fuPool.FUList3.opList3 system.cpu3.fuPool.FUList3.opList4 |
2076 2077[system.cpu3.fuPool.FUList3.opList0] 2078type=OpDesc 2079eventq_index=0 2080opClass=FloatMult 2081opLat=4 2082pipelined=true 2083 2084[system.cpu3.fuPool.FUList3.opList1] 2085type=OpDesc 2086eventq_index=0 |
2087opClass=FloatMultAcc 2088opLat=5 2089pipelined=true 2090 2091[system.cpu3.fuPool.FUList3.opList2] 2092type=OpDesc 2093eventq_index=0 2094opClass=FloatMisc 2095opLat=3 2096pipelined=true 2097 2098[system.cpu3.fuPool.FUList3.opList3] 2099type=OpDesc 2100eventq_index=0 |
2101opClass=FloatDiv 2102opLat=12 2103pipelined=false 2104 |
2105[system.cpu3.fuPool.FUList3.opList4] |
2106type=OpDesc 2107eventq_index=0 2108opClass=FloatSqrt 2109opLat=24 2110pipelined=false 2111 2112[system.cpu3.fuPool.FUList4] 2113type=FUDesc |
2114children=opList0 opList1 |
2115count=0 2116eventq_index=0 |
2117opList=system.cpu3.fuPool.FUList4.opList0 system.cpu3.fuPool.FUList4.opList1 |
2118 |
2119[system.cpu3.fuPool.FUList4.opList0] |
2120type=OpDesc 2121eventq_index=0 2122opClass=MemRead 2123opLat=1 2124pipelined=true 2125 |
2126[system.cpu3.fuPool.FUList4.opList1] 2127type=OpDesc 2128eventq_index=0 2129opClass=FloatMemRead 2130opLat=1 2131pipelined=true 2132 |
2133[system.cpu3.fuPool.FUList5] 2134type=FUDesc 2135children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 2136count=4 2137eventq_index=0 2138opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 2139 2140[system.cpu3.fuPool.FUList5.opList00] --- 133 unchanged lines hidden (view full) --- 2274type=OpDesc 2275eventq_index=0 2276opClass=SimdFloatSqrt 2277opLat=1 2278pipelined=true 2279 2280[system.cpu3.fuPool.FUList6] 2281type=FUDesc |
2282children=opList0 opList1 |
2283count=0 2284eventq_index=0 |
2285opList=system.cpu3.fuPool.FUList6.opList0 system.cpu3.fuPool.FUList6.opList1 |
2286 |
2287[system.cpu3.fuPool.FUList6.opList0] |
2288type=OpDesc 2289eventq_index=0 2290opClass=MemWrite 2291opLat=1 2292pipelined=true 2293 |
2294[system.cpu3.fuPool.FUList6.opList1] 2295type=OpDesc 2296eventq_index=0 2297opClass=FloatMemWrite 2298opLat=1 2299pipelined=true 2300 |
2301[system.cpu3.fuPool.FUList7] 2302type=FUDesc |
2303children=opList0 opList1 opList2 opList3 |
2304count=4 2305eventq_index=0 |
2306opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 system.cpu3.fuPool.FUList7.opList2 system.cpu3.fuPool.FUList7.opList3 |
2307 2308[system.cpu3.fuPool.FUList7.opList0] 2309type=OpDesc 2310eventq_index=0 2311opClass=MemRead 2312opLat=1 2313pipelined=true 2314 2315[system.cpu3.fuPool.FUList7.opList1] 2316type=OpDesc 2317eventq_index=0 2318opClass=MemWrite 2319opLat=1 2320pipelined=true 2321 |
2322[system.cpu3.fuPool.FUList7.opList2] 2323type=OpDesc 2324eventq_index=0 2325opClass=FloatMemRead 2326opLat=1 2327pipelined=true 2328 2329[system.cpu3.fuPool.FUList7.opList3] 2330type=OpDesc 2331eventq_index=0 2332opClass=FloatMemWrite 2333opLat=1 2334pipelined=true 2335 |
2336[system.cpu3.fuPool.FUList8] 2337type=FUDesc 2338children=opList 2339count=1 2340eventq_index=0 2341opList=system.cpu3.fuPool.FUList8.opList 2342 2343[system.cpu3.fuPool.FUList8.opList] --- 5 unchanged lines hidden (view full) --- 2349 2350[system.cpu3.icache] 2351type=Cache 2352children=tags 2353addr_ranges=0:18446744073709551615:0:0:0:0 2354assoc=1 2355clk_domain=system.cpu_clk_domain 2356clusivity=mostly_incl |
2357data_latency=2 |
2358default_p_state=UNDEFINED 2359demand_mshr_reserve=1 2360eventq_index=0 |
2361is_read_only=true 2362max_miss_count=0 2363mshrs=4 2364p_state_clk_gate_bins=20 2365p_state_clk_gate_max=1000000000000 2366p_state_clk_gate_min=1000 2367power_model=Null 2368prefetch_on_access=false 2369prefetcher=Null 2370response_latency=2 2371sequential_access=false 2372size=32768 2373system=system |
2374tag_latency=2 |
2375tags=system.cpu3.icache.tags 2376tgts_per_mshr=20 2377write_buffers=8 2378writeback_clean=true 2379cpu_side=system.cpu3.icache_port 2380mem_side=system.toL2Bus.slave[6] 2381 2382[system.cpu3.icache.tags] 2383type=LRU 2384assoc=1 2385block_size=64 2386clk_domain=system.cpu_clk_domain |
2387data_latency=2 |
2388default_p_state=UNDEFINED 2389eventq_index=0 |
2390p_state_clk_gate_bins=20 2391p_state_clk_gate_max=1000000000000 2392p_state_clk_gate_min=1000 2393power_model=Null 2394sequential_access=false 2395size=32768 |
2396tag_latency=2 |
2397 2398[system.cpu3.interrupts] 2399type=SparcInterrupts 2400eventq_index=0 2401 2402[system.cpu3.isa] 2403type=SparcISA 2404eventq_index=0 --- 25 unchanged lines hidden (view full) --- 2430 2431[system.l2c] 2432type=Cache 2433children=tags 2434addr_ranges=0:18446744073709551615:0:0:0:0 2435assoc=8 2436clk_domain=system.cpu_clk_domain 2437clusivity=mostly_incl |
2438data_latency=20 |
2439default_p_state=UNDEFINED 2440demand_mshr_reserve=1 2441eventq_index=0 |
2442is_read_only=false 2443max_miss_count=0 2444mshrs=20 2445p_state_clk_gate_bins=20 2446p_state_clk_gate_max=1000000000000 2447p_state_clk_gate_min=1000 2448power_model=Null 2449prefetch_on_access=false 2450prefetcher=Null 2451response_latency=20 2452sequential_access=false 2453size=4194304 2454system=system |
2455tag_latency=20 |
2456tags=system.l2c.tags 2457tgts_per_mshr=12 2458write_buffers=8 2459writeback_clean=false 2460cpu_side=system.toL2Bus.master[0] 2461mem_side=system.membus.slave[1] 2462 2463[system.l2c.tags] 2464type=LRU 2465assoc=8 2466block_size=64 2467clk_domain=system.cpu_clk_domain |
2468data_latency=20 |
2469default_p_state=UNDEFINED 2470eventq_index=0 |
2471p_state_clk_gate_bins=20 2472p_state_clk_gate_max=1000000000000 2473p_state_clk_gate_min=1000 2474power_model=Null 2475sequential_access=false 2476size=4194304 |
2477tag_latency=20 |
2478 2479[system.membus] 2480type=CoherentXBar 2481children=snoop_filter 2482clk_domain=system.clk_domain 2483default_p_state=UNDEFINED 2484eventq_index=0 2485forward_latency=4 --- 139 unchanged lines hidden --- |