19d18
< physmem=system.physmem
29c28
< system_port=system.membus.port[2]
---
> system_port=system.membus.slave[1]
130c129
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
151c150
< mem_side=system.toL2Bus.port[2]
---
> mem_side=system.toL2Bus.slave[1]
422c421
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
443c442
< mem_side=system.toL2Bus.port[1]
---
> mem_side=system.toL2Bus.slave[0]
573c572
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
594c593
< mem_side=system.toL2Bus.port[4]
---
> mem_side=system.toL2Bus.slave[3]
865c864
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
886c885
< mem_side=system.toL2Bus.port[3]
---
> mem_side=system.toL2Bus.slave[2]
997c996
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
1018c1017
< mem_side=system.toL2Bus.port[6]
---
> mem_side=system.toL2Bus.slave[5]
1289c1288
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
1310c1309
< mem_side=system.toL2Bus.port[5]
---
> mem_side=system.toL2Bus.slave[4]
1421c1420
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
1442c1441
< mem_side=system.toL2Bus.port[8]
---
> mem_side=system.toL2Bus.slave[7]
1713c1712
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
1734c1733
< mem_side=system.toL2Bus.port[7]
---
> mem_side=system.toL2Bus.slave[6]
1748c1747
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
1768,1769c1767,1768
< cpu_side=system.toL2Bus.port[0]
< mem_side=system.membus.port[0]
---
> cpu_side=system.toL2Bus.master[0]
> mem_side=system.membus.slave[0]
1779c1778,1779
< port=system.l2c.mem_side system.physmem.port[0] system.system_port
---
> master=system.physmem.port[0]
> slave=system.l2c.mem_side system.system_port
1782c1782,1783
< type=PhysicalMemory
---
> type=SimpleMemory
> conf_table_reported=false
1783a1785
> in_addr_map=true
1789c1791
< port=system.membus.port[1]
---
> port=system.membus.master[0]
1799c1801,1802
< port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
---
> master=system.l2c.cpu_side
> slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side