179a180
> data_latency=2
183d183
< hit_latency=2
196a197
> tag_latency=2
208a210
> data_latency=2
211d212
< hit_latency=2
217a219
> tag_latency=2
295c297
< children=opList0 opList1 opList2
---
> children=opList0 opList1 opList2 opList3 opList4
298c300
< opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
---
> opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 system.cpu0.fuPool.FUList3.opList3 system.cpu0.fuPool.FUList3.opList4
309a312,325
> opClass=FloatMultAcc
> opLat=5
> pipelined=true
>
> [system.cpu0.fuPool.FUList3.opList2]
> type=OpDesc
> eventq_index=0
> opClass=FloatMisc
> opLat=3
> pipelined=true
>
> [system.cpu0.fuPool.FUList3.opList3]
> type=OpDesc
> eventq_index=0
314c330
< [system.cpu0.fuPool.FUList3.opList2]
---
> [system.cpu0.fuPool.FUList3.opList4]
323c339
< children=opList
---
> children=opList0 opList1
326c342
< opList=system.cpu0.fuPool.FUList4.opList
---
> opList=system.cpu0.fuPool.FUList4.opList0 system.cpu0.fuPool.FUList4.opList1
328c344
< [system.cpu0.fuPool.FUList4.opList]
---
> [system.cpu0.fuPool.FUList4.opList0]
334a351,357
> [system.cpu0.fuPool.FUList4.opList1]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemRead
> opLat=1
> pipelined=true
>
484c507
< children=opList
---
> children=opList0 opList1
487c510
< opList=system.cpu0.fuPool.FUList6.opList
---
> opList=system.cpu0.fuPool.FUList6.opList0 system.cpu0.fuPool.FUList6.opList1
489c512
< [system.cpu0.fuPool.FUList6.opList]
---
> [system.cpu0.fuPool.FUList6.opList0]
495a519,525
> [system.cpu0.fuPool.FUList6.opList1]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemWrite
> opLat=1
> pipelined=true
>
498c528
< children=opList0 opList1
---
> children=opList0 opList1 opList2 opList3
501c531
< opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
---
> opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 system.cpu0.fuPool.FUList7.opList2 system.cpu0.fuPool.FUList7.opList3
516a547,560
> [system.cpu0.fuPool.FUList7.opList2]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemRead
> opLat=1
> pipelined=true
>
> [system.cpu0.fuPool.FUList7.opList3]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemWrite
> opLat=1
> pipelined=true
>
537a582
> data_latency=2
541d585
< hit_latency=2
554a599
> tag_latency=2
566a612
> data_latency=2
569d614
< hit_latency=2
575a621
> tag_latency=2
604c650
< executable=/arm/projectscratch/randd/systems/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
---
> executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
740a787
> data_latency=2
744d790
< hit_latency=2
757a804
> tag_latency=2
769a817
> data_latency=2
772d819
< hit_latency=2
778a826
> tag_latency=2
856c904
< children=opList0 opList1 opList2
---
> children=opList0 opList1 opList2 opList3 opList4
859c907
< opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2
---
> opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 system.cpu1.fuPool.FUList3.opList3 system.cpu1.fuPool.FUList3.opList4
870a919,932
> opClass=FloatMultAcc
> opLat=5
> pipelined=true
>
> [system.cpu1.fuPool.FUList3.opList2]
> type=OpDesc
> eventq_index=0
> opClass=FloatMisc
> opLat=3
> pipelined=true
>
> [system.cpu1.fuPool.FUList3.opList3]
> type=OpDesc
> eventq_index=0
875c937
< [system.cpu1.fuPool.FUList3.opList2]
---
> [system.cpu1.fuPool.FUList3.opList4]
884c946
< children=opList
---
> children=opList0 opList1
887c949
< opList=system.cpu1.fuPool.FUList4.opList
---
> opList=system.cpu1.fuPool.FUList4.opList0 system.cpu1.fuPool.FUList4.opList1
889c951
< [system.cpu1.fuPool.FUList4.opList]
---
> [system.cpu1.fuPool.FUList4.opList0]
895a958,964
> [system.cpu1.fuPool.FUList4.opList1]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemRead
> opLat=1
> pipelined=true
>
1045c1114
< children=opList
---
> children=opList0 opList1
1048c1117
< opList=system.cpu1.fuPool.FUList6.opList
---
> opList=system.cpu1.fuPool.FUList6.opList0 system.cpu1.fuPool.FUList6.opList1
1050c1119
< [system.cpu1.fuPool.FUList6.opList]
---
> [system.cpu1.fuPool.FUList6.opList0]
1056a1126,1132
> [system.cpu1.fuPool.FUList6.opList1]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemWrite
> opLat=1
> pipelined=true
>
1059c1135
< children=opList0 opList1
---
> children=opList0 opList1 opList2 opList3
1062c1138
< opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
---
> opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 system.cpu1.fuPool.FUList7.opList2 system.cpu1.fuPool.FUList7.opList3
1077a1154,1167
> [system.cpu1.fuPool.FUList7.opList2]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemRead
> opLat=1
> pipelined=true
>
> [system.cpu1.fuPool.FUList7.opList3]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemWrite
> opLat=1
> pipelined=true
>
1098a1189
> data_latency=2
1102d1192
< hit_latency=2
1115a1206
> tag_latency=2
1127a1219
> data_latency=2
1130d1221
< hit_latency=2
1136a1228
> tag_latency=2
1278a1371
> data_latency=2
1282d1374
< hit_latency=2
1295a1388
> tag_latency=2
1307a1401
> data_latency=2
1310d1403
< hit_latency=2
1316a1410
> tag_latency=2
1394c1488
< children=opList0 opList1 opList2
---
> children=opList0 opList1 opList2 opList3 opList4
1397c1491
< opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2
---
> opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 system.cpu2.fuPool.FUList3.opList3 system.cpu2.fuPool.FUList3.opList4
1408a1503,1516
> opClass=FloatMultAcc
> opLat=5
> pipelined=true
>
> [system.cpu2.fuPool.FUList3.opList2]
> type=OpDesc
> eventq_index=0
> opClass=FloatMisc
> opLat=3
> pipelined=true
>
> [system.cpu2.fuPool.FUList3.opList3]
> type=OpDesc
> eventq_index=0
1413c1521
< [system.cpu2.fuPool.FUList3.opList2]
---
> [system.cpu2.fuPool.FUList3.opList4]
1422c1530
< children=opList
---
> children=opList0 opList1
1425c1533
< opList=system.cpu2.fuPool.FUList4.opList
---
> opList=system.cpu2.fuPool.FUList4.opList0 system.cpu2.fuPool.FUList4.opList1
1427c1535
< [system.cpu2.fuPool.FUList4.opList]
---
> [system.cpu2.fuPool.FUList4.opList0]
1433a1542,1548
> [system.cpu2.fuPool.FUList4.opList1]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemRead
> opLat=1
> pipelined=true
>
1583c1698
< children=opList
---
> children=opList0 opList1
1586c1701
< opList=system.cpu2.fuPool.FUList6.opList
---
> opList=system.cpu2.fuPool.FUList6.opList0 system.cpu2.fuPool.FUList6.opList1
1588c1703
< [system.cpu2.fuPool.FUList6.opList]
---
> [system.cpu2.fuPool.FUList6.opList0]
1594a1710,1716
> [system.cpu2.fuPool.FUList6.opList1]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemWrite
> opLat=1
> pipelined=true
>
1597c1719
< children=opList0 opList1
---
> children=opList0 opList1 opList2 opList3
1600c1722
< opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
---
> opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 system.cpu2.fuPool.FUList7.opList2 system.cpu2.fuPool.FUList7.opList3
1615a1738,1751
> [system.cpu2.fuPool.FUList7.opList2]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemRead
> opLat=1
> pipelined=true
>
> [system.cpu2.fuPool.FUList7.opList3]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemWrite
> opLat=1
> pipelined=true
>
1636a1773
> data_latency=2
1640d1776
< hit_latency=2
1653a1790
> tag_latency=2
1665a1803
> data_latency=2
1668d1805
< hit_latency=2
1674a1812
> tag_latency=2
1816a1955
> data_latency=2
1820d1958
< hit_latency=2
1833a1972
> tag_latency=2
1845a1985
> data_latency=2
1848d1987
< hit_latency=2
1854a1994
> tag_latency=2
1932c2072
< children=opList0 opList1 opList2
---
> children=opList0 opList1 opList2 opList3 opList4
1935c2075
< opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2
---
> opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 system.cpu3.fuPool.FUList3.opList3 system.cpu3.fuPool.FUList3.opList4
1946a2087,2100
> opClass=FloatMultAcc
> opLat=5
> pipelined=true
>
> [system.cpu3.fuPool.FUList3.opList2]
> type=OpDesc
> eventq_index=0
> opClass=FloatMisc
> opLat=3
> pipelined=true
>
> [system.cpu3.fuPool.FUList3.opList3]
> type=OpDesc
> eventq_index=0
1951c2105
< [system.cpu3.fuPool.FUList3.opList2]
---
> [system.cpu3.fuPool.FUList3.opList4]
1960c2114
< children=opList
---
> children=opList0 opList1
1963c2117
< opList=system.cpu3.fuPool.FUList4.opList
---
> opList=system.cpu3.fuPool.FUList4.opList0 system.cpu3.fuPool.FUList4.opList1
1965c2119
< [system.cpu3.fuPool.FUList4.opList]
---
> [system.cpu3.fuPool.FUList4.opList0]
1971a2126,2132
> [system.cpu3.fuPool.FUList4.opList1]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemRead
> opLat=1
> pipelined=true
>
2121c2282
< children=opList
---
> children=opList0 opList1
2124c2285
< opList=system.cpu3.fuPool.FUList6.opList
---
> opList=system.cpu3.fuPool.FUList6.opList0 system.cpu3.fuPool.FUList6.opList1
2126c2287
< [system.cpu3.fuPool.FUList6.opList]
---
> [system.cpu3.fuPool.FUList6.opList0]
2132a2294,2300
> [system.cpu3.fuPool.FUList6.opList1]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemWrite
> opLat=1
> pipelined=true
>
2135c2303
< children=opList0 opList1
---
> children=opList0 opList1 opList2 opList3
2138c2306
< opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1
---
> opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 system.cpu3.fuPool.FUList7.opList2 system.cpu3.fuPool.FUList7.opList3
2153a2322,2335
> [system.cpu3.fuPool.FUList7.opList2]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemRead
> opLat=1
> pipelined=true
>
> [system.cpu3.fuPool.FUList7.opList3]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemWrite
> opLat=1
> pipelined=true
>
2174a2357
> data_latency=2
2178d2360
< hit_latency=2
2191a2374
> tag_latency=2
2203a2387
> data_latency=2
2206d2389
< hit_latency=2
2212a2396
> tag_latency=2
2253a2438
> data_latency=20
2257d2441
< hit_latency=20
2270a2455
> tag_latency=20
2282a2468
> data_latency=20
2285d2470
< hit_latency=20
2291a2477
> tag_latency=20
> data_latency=2
183d183
< hit_latency=2
196a197
> tag_latency=2
208a210
> data_latency=2
211d212
< hit_latency=2
217a219
> tag_latency=2
295c297
< children=opList0 opList1 opList2
---
> children=opList0 opList1 opList2 opList3 opList4
298c300
< opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
---
> opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 system.cpu0.fuPool.FUList3.opList3 system.cpu0.fuPool.FUList3.opList4
309a312,325
> opClass=FloatMultAcc
> opLat=5
> pipelined=true
>
> [system.cpu0.fuPool.FUList3.opList2]
> type=OpDesc
> eventq_index=0
> opClass=FloatMisc
> opLat=3
> pipelined=true
>
> [system.cpu0.fuPool.FUList3.opList3]
> type=OpDesc
> eventq_index=0
314c330
< [system.cpu0.fuPool.FUList3.opList2]
---
> [system.cpu0.fuPool.FUList3.opList4]
323c339
< children=opList
---
> children=opList0 opList1
326c342
< opList=system.cpu0.fuPool.FUList4.opList
---
> opList=system.cpu0.fuPool.FUList4.opList0 system.cpu0.fuPool.FUList4.opList1
328c344
< [system.cpu0.fuPool.FUList4.opList]
---
> [system.cpu0.fuPool.FUList4.opList0]
334a351,357
> [system.cpu0.fuPool.FUList4.opList1]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemRead
> opLat=1
> pipelined=true
>
484c507
< children=opList
---
> children=opList0 opList1
487c510
< opList=system.cpu0.fuPool.FUList6.opList
---
> opList=system.cpu0.fuPool.FUList6.opList0 system.cpu0.fuPool.FUList6.opList1
489c512
< [system.cpu0.fuPool.FUList6.opList]
---
> [system.cpu0.fuPool.FUList6.opList0]
495a519,525
> [system.cpu0.fuPool.FUList6.opList1]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemWrite
> opLat=1
> pipelined=true
>
498c528
< children=opList0 opList1
---
> children=opList0 opList1 opList2 opList3
501c531
< opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
---
> opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 system.cpu0.fuPool.FUList7.opList2 system.cpu0.fuPool.FUList7.opList3
516a547,560
> [system.cpu0.fuPool.FUList7.opList2]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemRead
> opLat=1
> pipelined=true
>
> [system.cpu0.fuPool.FUList7.opList3]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemWrite
> opLat=1
> pipelined=true
>
537a582
> data_latency=2
541d585
< hit_latency=2
554a599
> tag_latency=2
566a612
> data_latency=2
569d614
< hit_latency=2
575a621
> tag_latency=2
604c650
< executable=/arm/projectscratch/randd/systems/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
---
> executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
740a787
> data_latency=2
744d790
< hit_latency=2
757a804
> tag_latency=2
769a817
> data_latency=2
772d819
< hit_latency=2
778a826
> tag_latency=2
856c904
< children=opList0 opList1 opList2
---
> children=opList0 opList1 opList2 opList3 opList4
859c907
< opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2
---
> opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 system.cpu1.fuPool.FUList3.opList3 system.cpu1.fuPool.FUList3.opList4
870a919,932
> opClass=FloatMultAcc
> opLat=5
> pipelined=true
>
> [system.cpu1.fuPool.FUList3.opList2]
> type=OpDesc
> eventq_index=0
> opClass=FloatMisc
> opLat=3
> pipelined=true
>
> [system.cpu1.fuPool.FUList3.opList3]
> type=OpDesc
> eventq_index=0
875c937
< [system.cpu1.fuPool.FUList3.opList2]
---
> [system.cpu1.fuPool.FUList3.opList4]
884c946
< children=opList
---
> children=opList0 opList1
887c949
< opList=system.cpu1.fuPool.FUList4.opList
---
> opList=system.cpu1.fuPool.FUList4.opList0 system.cpu1.fuPool.FUList4.opList1
889c951
< [system.cpu1.fuPool.FUList4.opList]
---
> [system.cpu1.fuPool.FUList4.opList0]
895a958,964
> [system.cpu1.fuPool.FUList4.opList1]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemRead
> opLat=1
> pipelined=true
>
1045c1114
< children=opList
---
> children=opList0 opList1
1048c1117
< opList=system.cpu1.fuPool.FUList6.opList
---
> opList=system.cpu1.fuPool.FUList6.opList0 system.cpu1.fuPool.FUList6.opList1
1050c1119
< [system.cpu1.fuPool.FUList6.opList]
---
> [system.cpu1.fuPool.FUList6.opList0]
1056a1126,1132
> [system.cpu1.fuPool.FUList6.opList1]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemWrite
> opLat=1
> pipelined=true
>
1059c1135
< children=opList0 opList1
---
> children=opList0 opList1 opList2 opList3
1062c1138
< opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
---
> opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 system.cpu1.fuPool.FUList7.opList2 system.cpu1.fuPool.FUList7.opList3
1077a1154,1167
> [system.cpu1.fuPool.FUList7.opList2]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemRead
> opLat=1
> pipelined=true
>
> [system.cpu1.fuPool.FUList7.opList3]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemWrite
> opLat=1
> pipelined=true
>
1098a1189
> data_latency=2
1102d1192
< hit_latency=2
1115a1206
> tag_latency=2
1127a1219
> data_latency=2
1130d1221
< hit_latency=2
1136a1228
> tag_latency=2
1278a1371
> data_latency=2
1282d1374
< hit_latency=2
1295a1388
> tag_latency=2
1307a1401
> data_latency=2
1310d1403
< hit_latency=2
1316a1410
> tag_latency=2
1394c1488
< children=opList0 opList1 opList2
---
> children=opList0 opList1 opList2 opList3 opList4
1397c1491
< opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2
---
> opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 system.cpu2.fuPool.FUList3.opList3 system.cpu2.fuPool.FUList3.opList4
1408a1503,1516
> opClass=FloatMultAcc
> opLat=5
> pipelined=true
>
> [system.cpu2.fuPool.FUList3.opList2]
> type=OpDesc
> eventq_index=0
> opClass=FloatMisc
> opLat=3
> pipelined=true
>
> [system.cpu2.fuPool.FUList3.opList3]
> type=OpDesc
> eventq_index=0
1413c1521
< [system.cpu2.fuPool.FUList3.opList2]
---
> [system.cpu2.fuPool.FUList3.opList4]
1422c1530
< children=opList
---
> children=opList0 opList1
1425c1533
< opList=system.cpu2.fuPool.FUList4.opList
---
> opList=system.cpu2.fuPool.FUList4.opList0 system.cpu2.fuPool.FUList4.opList1
1427c1535
< [system.cpu2.fuPool.FUList4.opList]
---
> [system.cpu2.fuPool.FUList4.opList0]
1433a1542,1548
> [system.cpu2.fuPool.FUList4.opList1]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemRead
> opLat=1
> pipelined=true
>
1583c1698
< children=opList
---
> children=opList0 opList1
1586c1701
< opList=system.cpu2.fuPool.FUList6.opList
---
> opList=system.cpu2.fuPool.FUList6.opList0 system.cpu2.fuPool.FUList6.opList1
1588c1703
< [system.cpu2.fuPool.FUList6.opList]
---
> [system.cpu2.fuPool.FUList6.opList0]
1594a1710,1716
> [system.cpu2.fuPool.FUList6.opList1]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemWrite
> opLat=1
> pipelined=true
>
1597c1719
< children=opList0 opList1
---
> children=opList0 opList1 opList2 opList3
1600c1722
< opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
---
> opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 system.cpu2.fuPool.FUList7.opList2 system.cpu2.fuPool.FUList7.opList3
1615a1738,1751
> [system.cpu2.fuPool.FUList7.opList2]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemRead
> opLat=1
> pipelined=true
>
> [system.cpu2.fuPool.FUList7.opList3]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemWrite
> opLat=1
> pipelined=true
>
1636a1773
> data_latency=2
1640d1776
< hit_latency=2
1653a1790
> tag_latency=2
1665a1803
> data_latency=2
1668d1805
< hit_latency=2
1674a1812
> tag_latency=2
1816a1955
> data_latency=2
1820d1958
< hit_latency=2
1833a1972
> tag_latency=2
1845a1985
> data_latency=2
1848d1987
< hit_latency=2
1854a1994
> tag_latency=2
1932c2072
< children=opList0 opList1 opList2
---
> children=opList0 opList1 opList2 opList3 opList4
1935c2075
< opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2
---
> opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 system.cpu3.fuPool.FUList3.opList3 system.cpu3.fuPool.FUList3.opList4
1946a2087,2100
> opClass=FloatMultAcc
> opLat=5
> pipelined=true
>
> [system.cpu3.fuPool.FUList3.opList2]
> type=OpDesc
> eventq_index=0
> opClass=FloatMisc
> opLat=3
> pipelined=true
>
> [system.cpu3.fuPool.FUList3.opList3]
> type=OpDesc
> eventq_index=0
1951c2105
< [system.cpu3.fuPool.FUList3.opList2]
---
> [system.cpu3.fuPool.FUList3.opList4]
1960c2114
< children=opList
---
> children=opList0 opList1
1963c2117
< opList=system.cpu3.fuPool.FUList4.opList
---
> opList=system.cpu3.fuPool.FUList4.opList0 system.cpu3.fuPool.FUList4.opList1
1965c2119
< [system.cpu3.fuPool.FUList4.opList]
---
> [system.cpu3.fuPool.FUList4.opList0]
1971a2126,2132
> [system.cpu3.fuPool.FUList4.opList1]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemRead
> opLat=1
> pipelined=true
>
2121c2282
< children=opList
---
> children=opList0 opList1
2124c2285
< opList=system.cpu3.fuPool.FUList6.opList
---
> opList=system.cpu3.fuPool.FUList6.opList0 system.cpu3.fuPool.FUList6.opList1
2126c2287
< [system.cpu3.fuPool.FUList6.opList]
---
> [system.cpu3.fuPool.FUList6.opList0]
2132a2294,2300
> [system.cpu3.fuPool.FUList6.opList1]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemWrite
> opLat=1
> pipelined=true
>
2135c2303
< children=opList0 opList1
---
> children=opList0 opList1 opList2 opList3
2138c2306
< opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1
---
> opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 system.cpu3.fuPool.FUList7.opList2 system.cpu3.fuPool.FUList7.opList3
2153a2322,2335
> [system.cpu3.fuPool.FUList7.opList2]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemRead
> opLat=1
> pipelined=true
>
> [system.cpu3.fuPool.FUList7.opList3]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemWrite
> opLat=1
> pipelined=true
>
2174a2357
> data_latency=2
2178d2360
< hit_latency=2
2191a2374
> tag_latency=2
2203a2387
> data_latency=2
2206d2389
< hit_latency=2
2212a2396
> tag_latency=2
2253a2438
> data_latency=20
2257d2441
< hit_latency=20
2270a2455
> tag_latency=20
2282a2468
> data_latency=20
2285d2470
< hit_latency=20
2291a2477
> tag_latency=20