1[root]
2type=Root
3children=system
4full_system=false
5time_sync_enable=false
6time_sync_period=100000000000
7time_sync_spin_threshold=100000000
8
9[system]
10type=System
11children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
12boot_osflags=a
13clock=1000
14init_param=0
15kernel=
16load_addr_mask=1099511627775
17mem_mode=timing
| 1[root]
2type=Root
3children=system
4full_system=false
5time_sync_enable=false
6time_sync_period=100000000000
7time_sync_spin_threshold=100000000
8
9[system]
10type=System
11children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
12boot_osflags=a
13clock=1000
14init_param=0
15kernel=
16load_addr_mask=1099511627775
17mem_mode=timing
|
| 18mem_ranges=
|
18memories=system.physmem
19num_work_ids=16
20readfile=
21symbolfile=
22work_begin_ckpt_count=0
23work_begin_cpu_id_exit=-1
24work_begin_exit_count=0
25work_cpus_ckpt_count=0
26work_end_ckpt_count=0
27work_end_exit_count=0
28work_item_id=-1
29system_port=system.membus.slave[1]
30
31[system.cpu0]
32type=DerivO3CPU
| 19memories=system.physmem
20num_work_ids=16
21readfile=
22symbolfile=
23work_begin_ckpt_count=0
24work_begin_cpu_id_exit=-1
25work_begin_exit_count=0
26work_cpus_ckpt_count=0
27work_end_ckpt_count=0
28work_end_exit_count=0
29work_item_id=-1
30system_port=system.membus.slave[1]
31
32[system.cpu0]
33type=DerivO3CPU
|
33children=dcache dtb fuPool icache interrupts itb tracer workload
| 34children=dcache dtb fuPool icache interrupts isa itb tracer workload
|
34BTBEntries=4096
35BTBTagSize=16
36LFSTSize=1024
37LQEntries=32
38LSQCheckLoads=true
39LSQDepCheckShift=4
40RASSize=16
41SQEntries=32
42SSITSize=1024
43activity=0
44backComSize=5
45cachePorts=200
46checker=Null
47choiceCtrBits=2
48choicePredictorSize=8192
49clock=500
50commitToDecodeDelay=1
51commitToFetchDelay=1
52commitToIEWDelay=1
53commitToRenameDelay=1
54commitWidth=8
55cpu_id=0
56decodeToFetchDelay=1
57decodeToRenameDelay=1
58decodeWidth=8
| 35BTBEntries=4096
36BTBTagSize=16
37LFSTSize=1024
38LQEntries=32
39LSQCheckLoads=true
40LSQDepCheckShift=4
41RASSize=16
42SQEntries=32
43SSITSize=1024
44activity=0
45backComSize=5
46cachePorts=200
47checker=Null
48choiceCtrBits=2
49choicePredictorSize=8192
50clock=500
51commitToDecodeDelay=1
52commitToFetchDelay=1
53commitToIEWDelay=1
54commitToRenameDelay=1
55commitWidth=8
56cpu_id=0
57decodeToFetchDelay=1
58decodeToRenameDelay=1
59decodeWidth=8
|
59defer_registration=false
| |
60dispatchWidth=8
61do_checkpoint_insts=true
62do_quiesce=true
63do_statistics_insts=true
64dtb=system.cpu0.dtb
65fetchToDecodeDelay=1
66fetchTrapLatency=1
67fetchWidth=8
68forwardComSize=5
69fuPool=system.cpu0.fuPool
70function_trace=false
71function_trace_start=0
72globalCtrBits=2
73globalHistoryBits=13
74globalPredictorSize=8192
75iewToCommitDelay=1
76iewToDecodeDelay=1
77iewToFetchDelay=1
78iewToRenameDelay=1
79instShiftAmt=2
80interrupts=system.cpu0.interrupts
| 60dispatchWidth=8
61do_checkpoint_insts=true
62do_quiesce=true
63do_statistics_insts=true
64dtb=system.cpu0.dtb
65fetchToDecodeDelay=1
66fetchTrapLatency=1
67fetchWidth=8
68forwardComSize=5
69fuPool=system.cpu0.fuPool
70function_trace=false
71function_trace_start=0
72globalCtrBits=2
73globalHistoryBits=13
74globalPredictorSize=8192
75iewToCommitDelay=1
76iewToDecodeDelay=1
77iewToFetchDelay=1
78iewToRenameDelay=1
79instShiftAmt=2
80interrupts=system.cpu0.interrupts
|
| 81isa=system.cpu0.isa
|
81issueToExecuteDelay=1
82issueWidth=8
83itb=system.cpu0.itb
84localCtrBits=2
85localHistoryBits=11
86localHistoryTableSize=2048
87localPredictorSize=2048
88max_insts_all_threads=0
89max_insts_any_thread=0
90max_loads_all_threads=0
91max_loads_any_thread=0
92needsTSO=false
93numIQEntries=64
94numPhysFloatRegs=256
95numPhysIntRegs=256
96numROBEntries=192
97numRobs=1
98numThreads=1
99predType=tournament
100profile=0
101progress_interval=0
102renameToDecodeDelay=1
103renameToFetchDelay=1
104renameToIEWDelay=2
105renameToROBDelay=1
106renameWidth=8
107smtCommitPolicy=RoundRobin
108smtFetchPolicy=SingleThread
109smtIQPolicy=Partitioned
110smtIQThreshold=100
111smtLSQPolicy=Partitioned
112smtLSQThreshold=100
113smtNumFetchingThreads=1
114smtROBPolicy=Partitioned
115smtROBThreshold=100
116squashWidth=8
117store_set_clear_period=250000
| 82issueToExecuteDelay=1
83issueWidth=8
84itb=system.cpu0.itb
85localCtrBits=2
86localHistoryBits=11
87localHistoryTableSize=2048
88localPredictorSize=2048
89max_insts_all_threads=0
90max_insts_any_thread=0
91max_loads_all_threads=0
92max_loads_any_thread=0
93needsTSO=false
94numIQEntries=64
95numPhysFloatRegs=256
96numPhysIntRegs=256
97numROBEntries=192
98numRobs=1
99numThreads=1
100predType=tournament
101profile=0
102progress_interval=0
103renameToDecodeDelay=1
104renameToFetchDelay=1
105renameToIEWDelay=2
106renameToROBDelay=1
107renameWidth=8
108smtCommitPolicy=RoundRobin
109smtFetchPolicy=SingleThread
110smtIQPolicy=Partitioned
111smtIQThreshold=100
112smtLSQPolicy=Partitioned
113smtLSQThreshold=100
114smtNumFetchingThreads=1
115smtROBPolicy=Partitioned
116smtROBThreshold=100
117squashWidth=8
118store_set_clear_period=250000
|
| 119switched_out=false
|
118system=system
119tracer=system.cpu0.tracer
120trapLatency=13
121wbDepth=1
122wbWidth=8
123workload=system.cpu0.workload
124dcache_port=system.cpu0.dcache.cpu_side
125icache_port=system.cpu0.icache.cpu_side
126
127[system.cpu0.dcache]
128type=BaseCache
129addr_ranges=0:18446744073709551615
130assoc=4
131block_size=64
132clock=500
133forward_snoops=true
| 120system=system
121tracer=system.cpu0.tracer
122trapLatency=13
123wbDepth=1
124wbWidth=8
125workload=system.cpu0.workload
126dcache_port=system.cpu0.dcache.cpu_side
127icache_port=system.cpu0.icache.cpu_side
128
129[system.cpu0.dcache]
130type=BaseCache
131addr_ranges=0:18446744073709551615
132assoc=4
133block_size=64
134clock=500
135forward_snoops=true
|
134hash_delay=1
| |
135hit_latency=2
136is_top_level=true
137max_miss_count=0
138mshrs=4
139prefetch_on_access=false
140prefetcher=Null
| 136hit_latency=2
137is_top_level=true
138max_miss_count=0
139mshrs=4
140prefetch_on_access=false
141prefetcher=Null
|
141prioritizeRequests=false
142repl=Null
| |
143response_latency=2
144size=32768
| 142response_latency=2
143size=32768
|
145subblock_size=0
| |
146system=system
147tgts_per_mshr=20
| 144system=system
145tgts_per_mshr=20
|
148trace_addr=0
| |
149two_queue=false
150write_buffers=8
151cpu_side=system.cpu0.dcache_port
152mem_side=system.toL2Bus.slave[1]
153
154[system.cpu0.dtb]
155type=SparcTLB
156size=64
157
158[system.cpu0.fuPool]
159type=FUPool
160children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
161FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
162
163[system.cpu0.fuPool.FUList0]
164type=FUDesc
165children=opList
166count=6
167opList=system.cpu0.fuPool.FUList0.opList
168
169[system.cpu0.fuPool.FUList0.opList]
170type=OpDesc
171issueLat=1
172opClass=IntAlu
173opLat=1
174
175[system.cpu0.fuPool.FUList1]
176type=FUDesc
177children=opList0 opList1
178count=2
179opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
180
181[system.cpu0.fuPool.FUList1.opList0]
182type=OpDesc
183issueLat=1
184opClass=IntMult
185opLat=3
186
187[system.cpu0.fuPool.FUList1.opList1]
188type=OpDesc
189issueLat=19
190opClass=IntDiv
191opLat=20
192
193[system.cpu0.fuPool.FUList2]
194type=FUDesc
195children=opList0 opList1 opList2
196count=4
197opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
198
199[system.cpu0.fuPool.FUList2.opList0]
200type=OpDesc
201issueLat=1
202opClass=FloatAdd
203opLat=2
204
205[system.cpu0.fuPool.FUList2.opList1]
206type=OpDesc
207issueLat=1
208opClass=FloatCmp
209opLat=2
210
211[system.cpu0.fuPool.FUList2.opList2]
212type=OpDesc
213issueLat=1
214opClass=FloatCvt
215opLat=2
216
217[system.cpu0.fuPool.FUList3]
218type=FUDesc
219children=opList0 opList1 opList2
220count=2
221opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
222
223[system.cpu0.fuPool.FUList3.opList0]
224type=OpDesc
225issueLat=1
226opClass=FloatMult
227opLat=4
228
229[system.cpu0.fuPool.FUList3.opList1]
230type=OpDesc
231issueLat=12
232opClass=FloatDiv
233opLat=12
234
235[system.cpu0.fuPool.FUList3.opList2]
236type=OpDesc
237issueLat=24
238opClass=FloatSqrt
239opLat=24
240
241[system.cpu0.fuPool.FUList4]
242type=FUDesc
243children=opList
244count=0
245opList=system.cpu0.fuPool.FUList4.opList
246
247[system.cpu0.fuPool.FUList4.opList]
248type=OpDesc
249issueLat=1
250opClass=MemRead
251opLat=1
252
253[system.cpu0.fuPool.FUList5]
254type=FUDesc
255children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
256count=4
257opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19
258
259[system.cpu0.fuPool.FUList5.opList00]
260type=OpDesc
261issueLat=1
262opClass=SimdAdd
263opLat=1
264
265[system.cpu0.fuPool.FUList5.opList01]
266type=OpDesc
267issueLat=1
268opClass=SimdAddAcc
269opLat=1
270
271[system.cpu0.fuPool.FUList5.opList02]
272type=OpDesc
273issueLat=1
274opClass=SimdAlu
275opLat=1
276
277[system.cpu0.fuPool.FUList5.opList03]
278type=OpDesc
279issueLat=1
280opClass=SimdCmp
281opLat=1
282
283[system.cpu0.fuPool.FUList5.opList04]
284type=OpDesc
285issueLat=1
286opClass=SimdCvt
287opLat=1
288
289[system.cpu0.fuPool.FUList5.opList05]
290type=OpDesc
291issueLat=1
292opClass=SimdMisc
293opLat=1
294
295[system.cpu0.fuPool.FUList5.opList06]
296type=OpDesc
297issueLat=1
298opClass=SimdMult
299opLat=1
300
301[system.cpu0.fuPool.FUList5.opList07]
302type=OpDesc
303issueLat=1
304opClass=SimdMultAcc
305opLat=1
306
307[system.cpu0.fuPool.FUList5.opList08]
308type=OpDesc
309issueLat=1
310opClass=SimdShift
311opLat=1
312
313[system.cpu0.fuPool.FUList5.opList09]
314type=OpDesc
315issueLat=1
316opClass=SimdShiftAcc
317opLat=1
318
319[system.cpu0.fuPool.FUList5.opList10]
320type=OpDesc
321issueLat=1
322opClass=SimdSqrt
323opLat=1
324
325[system.cpu0.fuPool.FUList5.opList11]
326type=OpDesc
327issueLat=1
328opClass=SimdFloatAdd
329opLat=1
330
331[system.cpu0.fuPool.FUList5.opList12]
332type=OpDesc
333issueLat=1
334opClass=SimdFloatAlu
335opLat=1
336
337[system.cpu0.fuPool.FUList5.opList13]
338type=OpDesc
339issueLat=1
340opClass=SimdFloatCmp
341opLat=1
342
343[system.cpu0.fuPool.FUList5.opList14]
344type=OpDesc
345issueLat=1
346opClass=SimdFloatCvt
347opLat=1
348
349[system.cpu0.fuPool.FUList5.opList15]
350type=OpDesc
351issueLat=1
352opClass=SimdFloatDiv
353opLat=1
354
355[system.cpu0.fuPool.FUList5.opList16]
356type=OpDesc
357issueLat=1
358opClass=SimdFloatMisc
359opLat=1
360
361[system.cpu0.fuPool.FUList5.opList17]
362type=OpDesc
363issueLat=1
364opClass=SimdFloatMult
365opLat=1
366
367[system.cpu0.fuPool.FUList5.opList18]
368type=OpDesc
369issueLat=1
370opClass=SimdFloatMultAcc
371opLat=1
372
373[system.cpu0.fuPool.FUList5.opList19]
374type=OpDesc
375issueLat=1
376opClass=SimdFloatSqrt
377opLat=1
378
379[system.cpu0.fuPool.FUList6]
380type=FUDesc
381children=opList
382count=0
383opList=system.cpu0.fuPool.FUList6.opList
384
385[system.cpu0.fuPool.FUList6.opList]
386type=OpDesc
387issueLat=1
388opClass=MemWrite
389opLat=1
390
391[system.cpu0.fuPool.FUList7]
392type=FUDesc
393children=opList0 opList1
394count=4
395opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
396
397[system.cpu0.fuPool.FUList7.opList0]
398type=OpDesc
399issueLat=1
400opClass=MemRead
401opLat=1
402
403[system.cpu0.fuPool.FUList7.opList1]
404type=OpDesc
405issueLat=1
406opClass=MemWrite
407opLat=1
408
409[system.cpu0.fuPool.FUList8]
410type=FUDesc
411children=opList
412count=1
413opList=system.cpu0.fuPool.FUList8.opList
414
415[system.cpu0.fuPool.FUList8.opList]
416type=OpDesc
417issueLat=3
418opClass=IprAccess
419opLat=3
420
421[system.cpu0.icache]
422type=BaseCache
423addr_ranges=0:18446744073709551615
424assoc=1
425block_size=64
426clock=500
427forward_snoops=true
| 146two_queue=false
147write_buffers=8
148cpu_side=system.cpu0.dcache_port
149mem_side=system.toL2Bus.slave[1]
150
151[system.cpu0.dtb]
152type=SparcTLB
153size=64
154
155[system.cpu0.fuPool]
156type=FUPool
157children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
158FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
159
160[system.cpu0.fuPool.FUList0]
161type=FUDesc
162children=opList
163count=6
164opList=system.cpu0.fuPool.FUList0.opList
165
166[system.cpu0.fuPool.FUList0.opList]
167type=OpDesc
168issueLat=1
169opClass=IntAlu
170opLat=1
171
172[system.cpu0.fuPool.FUList1]
173type=FUDesc
174children=opList0 opList1
175count=2
176opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
177
178[system.cpu0.fuPool.FUList1.opList0]
179type=OpDesc
180issueLat=1
181opClass=IntMult
182opLat=3
183
184[system.cpu0.fuPool.FUList1.opList1]
185type=OpDesc
186issueLat=19
187opClass=IntDiv
188opLat=20
189
190[system.cpu0.fuPool.FUList2]
191type=FUDesc
192children=opList0 opList1 opList2
193count=4
194opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
195
196[system.cpu0.fuPool.FUList2.opList0]
197type=OpDesc
198issueLat=1
199opClass=FloatAdd
200opLat=2
201
202[system.cpu0.fuPool.FUList2.opList1]
203type=OpDesc
204issueLat=1
205opClass=FloatCmp
206opLat=2
207
208[system.cpu0.fuPool.FUList2.opList2]
209type=OpDesc
210issueLat=1
211opClass=FloatCvt
212opLat=2
213
214[system.cpu0.fuPool.FUList3]
215type=FUDesc
216children=opList0 opList1 opList2
217count=2
218opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
219
220[system.cpu0.fuPool.FUList3.opList0]
221type=OpDesc
222issueLat=1
223opClass=FloatMult
224opLat=4
225
226[system.cpu0.fuPool.FUList3.opList1]
227type=OpDesc
228issueLat=12
229opClass=FloatDiv
230opLat=12
231
232[system.cpu0.fuPool.FUList3.opList2]
233type=OpDesc
234issueLat=24
235opClass=FloatSqrt
236opLat=24
237
238[system.cpu0.fuPool.FUList4]
239type=FUDesc
240children=opList
241count=0
242opList=system.cpu0.fuPool.FUList4.opList
243
244[system.cpu0.fuPool.FUList4.opList]
245type=OpDesc
246issueLat=1
247opClass=MemRead
248opLat=1
249
250[system.cpu0.fuPool.FUList5]
251type=FUDesc
252children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
253count=4
254opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19
255
256[system.cpu0.fuPool.FUList5.opList00]
257type=OpDesc
258issueLat=1
259opClass=SimdAdd
260opLat=1
261
262[system.cpu0.fuPool.FUList5.opList01]
263type=OpDesc
264issueLat=1
265opClass=SimdAddAcc
266opLat=1
267
268[system.cpu0.fuPool.FUList5.opList02]
269type=OpDesc
270issueLat=1
271opClass=SimdAlu
272opLat=1
273
274[system.cpu0.fuPool.FUList5.opList03]
275type=OpDesc
276issueLat=1
277opClass=SimdCmp
278opLat=1
279
280[system.cpu0.fuPool.FUList5.opList04]
281type=OpDesc
282issueLat=1
283opClass=SimdCvt
284opLat=1
285
286[system.cpu0.fuPool.FUList5.opList05]
287type=OpDesc
288issueLat=1
289opClass=SimdMisc
290opLat=1
291
292[system.cpu0.fuPool.FUList5.opList06]
293type=OpDesc
294issueLat=1
295opClass=SimdMult
296opLat=1
297
298[system.cpu0.fuPool.FUList5.opList07]
299type=OpDesc
300issueLat=1
301opClass=SimdMultAcc
302opLat=1
303
304[system.cpu0.fuPool.FUList5.opList08]
305type=OpDesc
306issueLat=1
307opClass=SimdShift
308opLat=1
309
310[system.cpu0.fuPool.FUList5.opList09]
311type=OpDesc
312issueLat=1
313opClass=SimdShiftAcc
314opLat=1
315
316[system.cpu0.fuPool.FUList5.opList10]
317type=OpDesc
318issueLat=1
319opClass=SimdSqrt
320opLat=1
321
322[system.cpu0.fuPool.FUList5.opList11]
323type=OpDesc
324issueLat=1
325opClass=SimdFloatAdd
326opLat=1
327
328[system.cpu0.fuPool.FUList5.opList12]
329type=OpDesc
330issueLat=1
331opClass=SimdFloatAlu
332opLat=1
333
334[system.cpu0.fuPool.FUList5.opList13]
335type=OpDesc
336issueLat=1
337opClass=SimdFloatCmp
338opLat=1
339
340[system.cpu0.fuPool.FUList5.opList14]
341type=OpDesc
342issueLat=1
343opClass=SimdFloatCvt
344opLat=1
345
346[system.cpu0.fuPool.FUList5.opList15]
347type=OpDesc
348issueLat=1
349opClass=SimdFloatDiv
350opLat=1
351
352[system.cpu0.fuPool.FUList5.opList16]
353type=OpDesc
354issueLat=1
355opClass=SimdFloatMisc
356opLat=1
357
358[system.cpu0.fuPool.FUList5.opList17]
359type=OpDesc
360issueLat=1
361opClass=SimdFloatMult
362opLat=1
363
364[system.cpu0.fuPool.FUList5.opList18]
365type=OpDesc
366issueLat=1
367opClass=SimdFloatMultAcc
368opLat=1
369
370[system.cpu0.fuPool.FUList5.opList19]
371type=OpDesc
372issueLat=1
373opClass=SimdFloatSqrt
374opLat=1
375
376[system.cpu0.fuPool.FUList6]
377type=FUDesc
378children=opList
379count=0
380opList=system.cpu0.fuPool.FUList6.opList
381
382[system.cpu0.fuPool.FUList6.opList]
383type=OpDesc
384issueLat=1
385opClass=MemWrite
386opLat=1
387
388[system.cpu0.fuPool.FUList7]
389type=FUDesc
390children=opList0 opList1
391count=4
392opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
393
394[system.cpu0.fuPool.FUList7.opList0]
395type=OpDesc
396issueLat=1
397opClass=MemRead
398opLat=1
399
400[system.cpu0.fuPool.FUList7.opList1]
401type=OpDesc
402issueLat=1
403opClass=MemWrite
404opLat=1
405
406[system.cpu0.fuPool.FUList8]
407type=FUDesc
408children=opList
409count=1
410opList=system.cpu0.fuPool.FUList8.opList
411
412[system.cpu0.fuPool.FUList8.opList]
413type=OpDesc
414issueLat=3
415opClass=IprAccess
416opLat=3
417
418[system.cpu0.icache]
419type=BaseCache
420addr_ranges=0:18446744073709551615
421assoc=1
422block_size=64
423clock=500
424forward_snoops=true
|
428hash_delay=1
| |
429hit_latency=2
430is_top_level=true
431max_miss_count=0
432mshrs=4
433prefetch_on_access=false
434prefetcher=Null
| 425hit_latency=2
426is_top_level=true
427max_miss_count=0
428mshrs=4
429prefetch_on_access=false
430prefetcher=Null
|
435prioritizeRequests=false
436repl=Null
| |
437response_latency=2
438size=32768
| 431response_latency=2
432size=32768
|
439subblock_size=0
| |
440system=system
441tgts_per_mshr=20
| 433system=system
434tgts_per_mshr=20
|
442trace_addr=0
| |
443two_queue=false
444write_buffers=8
445cpu_side=system.cpu0.icache_port
446mem_side=system.toL2Bus.slave[0]
447
448[system.cpu0.interrupts]
449type=SparcInterrupts
450
| 435two_queue=false
436write_buffers=8
437cpu_side=system.cpu0.icache_port
438mem_side=system.toL2Bus.slave[0]
439
440[system.cpu0.interrupts]
441type=SparcInterrupts
442
|
| 443[system.cpu0.isa]
444type=SparcISA
445
|
451[system.cpu0.itb]
452type=SparcTLB
453size=64
454
455[system.cpu0.tracer]
456type=ExeTracer
457
458[system.cpu0.workload]
459type=LiveProcess
460cmd=test_atomic 4
461cwd=
462egid=100
463env=
464errout=cerr
465euid=100
| 446[system.cpu0.itb]
447type=SparcTLB
448size=64
449
450[system.cpu0.tracer]
451type=ExeTracer
452
453[system.cpu0.workload]
454type=LiveProcess
455cmd=test_atomic 4
456cwd=
457egid=100
458env=
459errout=cerr
460euid=100
|
466executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic
| 461executable=/gem5/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
|
467gid=100
468input=cin
469max_stack_size=67108864
470output=cout
471pid=100
472ppid=99
473simpoint=0
474system=system
475uid=100
476
477[system.cpu1]
478type=DerivO3CPU
| 462gid=100
463input=cin
464max_stack_size=67108864
465output=cout
466pid=100
467ppid=99
468simpoint=0
469system=system
470uid=100
471
472[system.cpu1]
473type=DerivO3CPU
|
479children=dcache dtb fuPool icache interrupts itb tracer
| 474children=dcache dtb fuPool icache interrupts isa itb tracer
|
480BTBEntries=4096
481BTBTagSize=16
482LFSTSize=1024
483LQEntries=32
484LSQCheckLoads=true
485LSQDepCheckShift=4
486RASSize=16
487SQEntries=32
488SSITSize=1024
489activity=0
490backComSize=5
491cachePorts=200
492checker=Null
493choiceCtrBits=2
494choicePredictorSize=8192
495clock=500
496commitToDecodeDelay=1
497commitToFetchDelay=1
498commitToIEWDelay=1
499commitToRenameDelay=1
500commitWidth=8
501cpu_id=1
502decodeToFetchDelay=1
503decodeToRenameDelay=1
504decodeWidth=8
| 475BTBEntries=4096
476BTBTagSize=16
477LFSTSize=1024
478LQEntries=32
479LSQCheckLoads=true
480LSQDepCheckShift=4
481RASSize=16
482SQEntries=32
483SSITSize=1024
484activity=0
485backComSize=5
486cachePorts=200
487checker=Null
488choiceCtrBits=2
489choicePredictorSize=8192
490clock=500
491commitToDecodeDelay=1
492commitToFetchDelay=1
493commitToIEWDelay=1
494commitToRenameDelay=1
495commitWidth=8
496cpu_id=1
497decodeToFetchDelay=1
498decodeToRenameDelay=1
499decodeWidth=8
|
505defer_registration=false
| |
506dispatchWidth=8
507do_checkpoint_insts=true
508do_quiesce=true
509do_statistics_insts=true
510dtb=system.cpu1.dtb
511fetchToDecodeDelay=1
512fetchTrapLatency=1
513fetchWidth=8
514forwardComSize=5
515fuPool=system.cpu1.fuPool
516function_trace=false
517function_trace_start=0
518globalCtrBits=2
519globalHistoryBits=13
520globalPredictorSize=8192
521iewToCommitDelay=1
522iewToDecodeDelay=1
523iewToFetchDelay=1
524iewToRenameDelay=1
525instShiftAmt=2
526interrupts=system.cpu1.interrupts
| 500dispatchWidth=8
501do_checkpoint_insts=true
502do_quiesce=true
503do_statistics_insts=true
504dtb=system.cpu1.dtb
505fetchToDecodeDelay=1
506fetchTrapLatency=1
507fetchWidth=8
508forwardComSize=5
509fuPool=system.cpu1.fuPool
510function_trace=false
511function_trace_start=0
512globalCtrBits=2
513globalHistoryBits=13
514globalPredictorSize=8192
515iewToCommitDelay=1
516iewToDecodeDelay=1
517iewToFetchDelay=1
518iewToRenameDelay=1
519instShiftAmt=2
520interrupts=system.cpu1.interrupts
|
| 521isa=system.cpu1.isa
|
527issueToExecuteDelay=1
528issueWidth=8
529itb=system.cpu1.itb
530localCtrBits=2
531localHistoryBits=11
532localHistoryTableSize=2048
533localPredictorSize=2048
534max_insts_all_threads=0
535max_insts_any_thread=0
536max_loads_all_threads=0
537max_loads_any_thread=0
538needsTSO=false
539numIQEntries=64
540numPhysFloatRegs=256
541numPhysIntRegs=256
542numROBEntries=192
543numRobs=1
544numThreads=1
545predType=tournament
546profile=0
547progress_interval=0
548renameToDecodeDelay=1
549renameToFetchDelay=1
550renameToIEWDelay=2
551renameToROBDelay=1
552renameWidth=8
553smtCommitPolicy=RoundRobin
554smtFetchPolicy=SingleThread
555smtIQPolicy=Partitioned
556smtIQThreshold=100
557smtLSQPolicy=Partitioned
558smtLSQThreshold=100
559smtNumFetchingThreads=1
560smtROBPolicy=Partitioned
561smtROBThreshold=100
562squashWidth=8
563store_set_clear_period=250000
| 522issueToExecuteDelay=1
523issueWidth=8
524itb=system.cpu1.itb
525localCtrBits=2
526localHistoryBits=11
527localHistoryTableSize=2048
528localPredictorSize=2048
529max_insts_all_threads=0
530max_insts_any_thread=0
531max_loads_all_threads=0
532max_loads_any_thread=0
533needsTSO=false
534numIQEntries=64
535numPhysFloatRegs=256
536numPhysIntRegs=256
537numROBEntries=192
538numRobs=1
539numThreads=1
540predType=tournament
541profile=0
542progress_interval=0
543renameToDecodeDelay=1
544renameToFetchDelay=1
545renameToIEWDelay=2
546renameToROBDelay=1
547renameWidth=8
548smtCommitPolicy=RoundRobin
549smtFetchPolicy=SingleThread
550smtIQPolicy=Partitioned
551smtIQThreshold=100
552smtLSQPolicy=Partitioned
553smtLSQThreshold=100
554smtNumFetchingThreads=1
555smtROBPolicy=Partitioned
556smtROBThreshold=100
557squashWidth=8
558store_set_clear_period=250000
|
| 559switched_out=false
|
564system=system
565tracer=system.cpu1.tracer
566trapLatency=13
567wbDepth=1
568wbWidth=8
569workload=system.cpu0.workload
570dcache_port=system.cpu1.dcache.cpu_side
571icache_port=system.cpu1.icache.cpu_side
572
573[system.cpu1.dcache]
574type=BaseCache
575addr_ranges=0:18446744073709551615
576assoc=4
577block_size=64
578clock=500
579forward_snoops=true
| 560system=system
561tracer=system.cpu1.tracer
562trapLatency=13
563wbDepth=1
564wbWidth=8
565workload=system.cpu0.workload
566dcache_port=system.cpu1.dcache.cpu_side
567icache_port=system.cpu1.icache.cpu_side
568
569[system.cpu1.dcache]
570type=BaseCache
571addr_ranges=0:18446744073709551615
572assoc=4
573block_size=64
574clock=500
575forward_snoops=true
|
580hash_delay=1
| |
581hit_latency=2
582is_top_level=true
583max_miss_count=0
584mshrs=4
585prefetch_on_access=false
586prefetcher=Null
| 576hit_latency=2
577is_top_level=true
578max_miss_count=0
579mshrs=4
580prefetch_on_access=false
581prefetcher=Null
|
587prioritizeRequests=false
588repl=Null
| |
589response_latency=2
590size=32768
| 582response_latency=2
583size=32768
|
591subblock_size=0
| |
592system=system
593tgts_per_mshr=20
| 584system=system
585tgts_per_mshr=20
|
594trace_addr=0
| |
595two_queue=false
596write_buffers=8
597cpu_side=system.cpu1.dcache_port
598mem_side=system.toL2Bus.slave[3]
599
600[system.cpu1.dtb]
601type=SparcTLB
602size=64
603
604[system.cpu1.fuPool]
605type=FUPool
606children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
607FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8
608
609[system.cpu1.fuPool.FUList0]
610type=FUDesc
611children=opList
612count=6
613opList=system.cpu1.fuPool.FUList0.opList
614
615[system.cpu1.fuPool.FUList0.opList]
616type=OpDesc
617issueLat=1
618opClass=IntAlu
619opLat=1
620
621[system.cpu1.fuPool.FUList1]
622type=FUDesc
623children=opList0 opList1
624count=2
625opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1
626
627[system.cpu1.fuPool.FUList1.opList0]
628type=OpDesc
629issueLat=1
630opClass=IntMult
631opLat=3
632
633[system.cpu1.fuPool.FUList1.opList1]
634type=OpDesc
635issueLat=19
636opClass=IntDiv
637opLat=20
638
639[system.cpu1.fuPool.FUList2]
640type=FUDesc
641children=opList0 opList1 opList2
642count=4
643opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2
644
645[system.cpu1.fuPool.FUList2.opList0]
646type=OpDesc
647issueLat=1
648opClass=FloatAdd
649opLat=2
650
651[system.cpu1.fuPool.FUList2.opList1]
652type=OpDesc
653issueLat=1
654opClass=FloatCmp
655opLat=2
656
657[system.cpu1.fuPool.FUList2.opList2]
658type=OpDesc
659issueLat=1
660opClass=FloatCvt
661opLat=2
662
663[system.cpu1.fuPool.FUList3]
664type=FUDesc
665children=opList0 opList1 opList2
666count=2
667opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2
668
669[system.cpu1.fuPool.FUList3.opList0]
670type=OpDesc
671issueLat=1
672opClass=FloatMult
673opLat=4
674
675[system.cpu1.fuPool.FUList3.opList1]
676type=OpDesc
677issueLat=12
678opClass=FloatDiv
679opLat=12
680
681[system.cpu1.fuPool.FUList3.opList2]
682type=OpDesc
683issueLat=24
684opClass=FloatSqrt
685opLat=24
686
687[system.cpu1.fuPool.FUList4]
688type=FUDesc
689children=opList
690count=0
691opList=system.cpu1.fuPool.FUList4.opList
692
693[system.cpu1.fuPool.FUList4.opList]
694type=OpDesc
695issueLat=1
696opClass=MemRead
697opLat=1
698
699[system.cpu1.fuPool.FUList5]
700type=FUDesc
701children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
702count=4
703opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19
704
705[system.cpu1.fuPool.FUList5.opList00]
706type=OpDesc
707issueLat=1
708opClass=SimdAdd
709opLat=1
710
711[system.cpu1.fuPool.FUList5.opList01]
712type=OpDesc
713issueLat=1
714opClass=SimdAddAcc
715opLat=1
716
717[system.cpu1.fuPool.FUList5.opList02]
718type=OpDesc
719issueLat=1
720opClass=SimdAlu
721opLat=1
722
723[system.cpu1.fuPool.FUList5.opList03]
724type=OpDesc
725issueLat=1
726opClass=SimdCmp
727opLat=1
728
729[system.cpu1.fuPool.FUList5.opList04]
730type=OpDesc
731issueLat=1
732opClass=SimdCvt
733opLat=1
734
735[system.cpu1.fuPool.FUList5.opList05]
736type=OpDesc
737issueLat=1
738opClass=SimdMisc
739opLat=1
740
741[system.cpu1.fuPool.FUList5.opList06]
742type=OpDesc
743issueLat=1
744opClass=SimdMult
745opLat=1
746
747[system.cpu1.fuPool.FUList5.opList07]
748type=OpDesc
749issueLat=1
750opClass=SimdMultAcc
751opLat=1
752
753[system.cpu1.fuPool.FUList5.opList08]
754type=OpDesc
755issueLat=1
756opClass=SimdShift
757opLat=1
758
759[system.cpu1.fuPool.FUList5.opList09]
760type=OpDesc
761issueLat=1
762opClass=SimdShiftAcc
763opLat=1
764
765[system.cpu1.fuPool.FUList5.opList10]
766type=OpDesc
767issueLat=1
768opClass=SimdSqrt
769opLat=1
770
771[system.cpu1.fuPool.FUList5.opList11]
772type=OpDesc
773issueLat=1
774opClass=SimdFloatAdd
775opLat=1
776
777[system.cpu1.fuPool.FUList5.opList12]
778type=OpDesc
779issueLat=1
780opClass=SimdFloatAlu
781opLat=1
782
783[system.cpu1.fuPool.FUList5.opList13]
784type=OpDesc
785issueLat=1
786opClass=SimdFloatCmp
787opLat=1
788
789[system.cpu1.fuPool.FUList5.opList14]
790type=OpDesc
791issueLat=1
792opClass=SimdFloatCvt
793opLat=1
794
795[system.cpu1.fuPool.FUList5.opList15]
796type=OpDesc
797issueLat=1
798opClass=SimdFloatDiv
799opLat=1
800
801[system.cpu1.fuPool.FUList5.opList16]
802type=OpDesc
803issueLat=1
804opClass=SimdFloatMisc
805opLat=1
806
807[system.cpu1.fuPool.FUList5.opList17]
808type=OpDesc
809issueLat=1
810opClass=SimdFloatMult
811opLat=1
812
813[system.cpu1.fuPool.FUList5.opList18]
814type=OpDesc
815issueLat=1
816opClass=SimdFloatMultAcc
817opLat=1
818
819[system.cpu1.fuPool.FUList5.opList19]
820type=OpDesc
821issueLat=1
822opClass=SimdFloatSqrt
823opLat=1
824
825[system.cpu1.fuPool.FUList6]
826type=FUDesc
827children=opList
828count=0
829opList=system.cpu1.fuPool.FUList6.opList
830
831[system.cpu1.fuPool.FUList6.opList]
832type=OpDesc
833issueLat=1
834opClass=MemWrite
835opLat=1
836
837[system.cpu1.fuPool.FUList7]
838type=FUDesc
839children=opList0 opList1
840count=4
841opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
842
843[system.cpu1.fuPool.FUList7.opList0]
844type=OpDesc
845issueLat=1
846opClass=MemRead
847opLat=1
848
849[system.cpu1.fuPool.FUList7.opList1]
850type=OpDesc
851issueLat=1
852opClass=MemWrite
853opLat=1
854
855[system.cpu1.fuPool.FUList8]
856type=FUDesc
857children=opList
858count=1
859opList=system.cpu1.fuPool.FUList8.opList
860
861[system.cpu1.fuPool.FUList8.opList]
862type=OpDesc
863issueLat=3
864opClass=IprAccess
865opLat=3
866
867[system.cpu1.icache]
868type=BaseCache
869addr_ranges=0:18446744073709551615
870assoc=1
871block_size=64
872clock=500
873forward_snoops=true
| 586two_queue=false
587write_buffers=8
588cpu_side=system.cpu1.dcache_port
589mem_side=system.toL2Bus.slave[3]
590
591[system.cpu1.dtb]
592type=SparcTLB
593size=64
594
595[system.cpu1.fuPool]
596type=FUPool
597children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
598FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8
599
600[system.cpu1.fuPool.FUList0]
601type=FUDesc
602children=opList
603count=6
604opList=system.cpu1.fuPool.FUList0.opList
605
606[system.cpu1.fuPool.FUList0.opList]
607type=OpDesc
608issueLat=1
609opClass=IntAlu
610opLat=1
611
612[system.cpu1.fuPool.FUList1]
613type=FUDesc
614children=opList0 opList1
615count=2
616opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1
617
618[system.cpu1.fuPool.FUList1.opList0]
619type=OpDesc
620issueLat=1
621opClass=IntMult
622opLat=3
623
624[system.cpu1.fuPool.FUList1.opList1]
625type=OpDesc
626issueLat=19
627opClass=IntDiv
628opLat=20
629
630[system.cpu1.fuPool.FUList2]
631type=FUDesc
632children=opList0 opList1 opList2
633count=4
634opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2
635
636[system.cpu1.fuPool.FUList2.opList0]
637type=OpDesc
638issueLat=1
639opClass=FloatAdd
640opLat=2
641
642[system.cpu1.fuPool.FUList2.opList1]
643type=OpDesc
644issueLat=1
645opClass=FloatCmp
646opLat=2
647
648[system.cpu1.fuPool.FUList2.opList2]
649type=OpDesc
650issueLat=1
651opClass=FloatCvt
652opLat=2
653
654[system.cpu1.fuPool.FUList3]
655type=FUDesc
656children=opList0 opList1 opList2
657count=2
658opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2
659
660[system.cpu1.fuPool.FUList3.opList0]
661type=OpDesc
662issueLat=1
663opClass=FloatMult
664opLat=4
665
666[system.cpu1.fuPool.FUList3.opList1]
667type=OpDesc
668issueLat=12
669opClass=FloatDiv
670opLat=12
671
672[system.cpu1.fuPool.FUList3.opList2]
673type=OpDesc
674issueLat=24
675opClass=FloatSqrt
676opLat=24
677
678[system.cpu1.fuPool.FUList4]
679type=FUDesc
680children=opList
681count=0
682opList=system.cpu1.fuPool.FUList4.opList
683
684[system.cpu1.fuPool.FUList4.opList]
685type=OpDesc
686issueLat=1
687opClass=MemRead
688opLat=1
689
690[system.cpu1.fuPool.FUList5]
691type=FUDesc
692children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
693count=4
694opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19
695
696[system.cpu1.fuPool.FUList5.opList00]
697type=OpDesc
698issueLat=1
699opClass=SimdAdd
700opLat=1
701
702[system.cpu1.fuPool.FUList5.opList01]
703type=OpDesc
704issueLat=1
705opClass=SimdAddAcc
706opLat=1
707
708[system.cpu1.fuPool.FUList5.opList02]
709type=OpDesc
710issueLat=1
711opClass=SimdAlu
712opLat=1
713
714[system.cpu1.fuPool.FUList5.opList03]
715type=OpDesc
716issueLat=1
717opClass=SimdCmp
718opLat=1
719
720[system.cpu1.fuPool.FUList5.opList04]
721type=OpDesc
722issueLat=1
723opClass=SimdCvt
724opLat=1
725
726[system.cpu1.fuPool.FUList5.opList05]
727type=OpDesc
728issueLat=1
729opClass=SimdMisc
730opLat=1
731
732[system.cpu1.fuPool.FUList5.opList06]
733type=OpDesc
734issueLat=1
735opClass=SimdMult
736opLat=1
737
738[system.cpu1.fuPool.FUList5.opList07]
739type=OpDesc
740issueLat=1
741opClass=SimdMultAcc
742opLat=1
743
744[system.cpu1.fuPool.FUList5.opList08]
745type=OpDesc
746issueLat=1
747opClass=SimdShift
748opLat=1
749
750[system.cpu1.fuPool.FUList5.opList09]
751type=OpDesc
752issueLat=1
753opClass=SimdShiftAcc
754opLat=1
755
756[system.cpu1.fuPool.FUList5.opList10]
757type=OpDesc
758issueLat=1
759opClass=SimdSqrt
760opLat=1
761
762[system.cpu1.fuPool.FUList5.opList11]
763type=OpDesc
764issueLat=1
765opClass=SimdFloatAdd
766opLat=1
767
768[system.cpu1.fuPool.FUList5.opList12]
769type=OpDesc
770issueLat=1
771opClass=SimdFloatAlu
772opLat=1
773
774[system.cpu1.fuPool.FUList5.opList13]
775type=OpDesc
776issueLat=1
777opClass=SimdFloatCmp
778opLat=1
779
780[system.cpu1.fuPool.FUList5.opList14]
781type=OpDesc
782issueLat=1
783opClass=SimdFloatCvt
784opLat=1
785
786[system.cpu1.fuPool.FUList5.opList15]
787type=OpDesc
788issueLat=1
789opClass=SimdFloatDiv
790opLat=1
791
792[system.cpu1.fuPool.FUList5.opList16]
793type=OpDesc
794issueLat=1
795opClass=SimdFloatMisc
796opLat=1
797
798[system.cpu1.fuPool.FUList5.opList17]
799type=OpDesc
800issueLat=1
801opClass=SimdFloatMult
802opLat=1
803
804[system.cpu1.fuPool.FUList5.opList18]
805type=OpDesc
806issueLat=1
807opClass=SimdFloatMultAcc
808opLat=1
809
810[system.cpu1.fuPool.FUList5.opList19]
811type=OpDesc
812issueLat=1
813opClass=SimdFloatSqrt
814opLat=1
815
816[system.cpu1.fuPool.FUList6]
817type=FUDesc
818children=opList
819count=0
820opList=system.cpu1.fuPool.FUList6.opList
821
822[system.cpu1.fuPool.FUList6.opList]
823type=OpDesc
824issueLat=1
825opClass=MemWrite
826opLat=1
827
828[system.cpu1.fuPool.FUList7]
829type=FUDesc
830children=opList0 opList1
831count=4
832opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
833
834[system.cpu1.fuPool.FUList7.opList0]
835type=OpDesc
836issueLat=1
837opClass=MemRead
838opLat=1
839
840[system.cpu1.fuPool.FUList7.opList1]
841type=OpDesc
842issueLat=1
843opClass=MemWrite
844opLat=1
845
846[system.cpu1.fuPool.FUList8]
847type=FUDesc
848children=opList
849count=1
850opList=system.cpu1.fuPool.FUList8.opList
851
852[system.cpu1.fuPool.FUList8.opList]
853type=OpDesc
854issueLat=3
855opClass=IprAccess
856opLat=3
857
858[system.cpu1.icache]
859type=BaseCache
860addr_ranges=0:18446744073709551615
861assoc=1
862block_size=64
863clock=500
864forward_snoops=true
|
874hash_delay=1
| |
875hit_latency=2
876is_top_level=true
877max_miss_count=0
878mshrs=4
879prefetch_on_access=false
880prefetcher=Null
| 865hit_latency=2
866is_top_level=true
867max_miss_count=0
868mshrs=4
869prefetch_on_access=false
870prefetcher=Null
|
881prioritizeRequests=false
882repl=Null
| |
883response_latency=2
884size=32768
| 871response_latency=2
872size=32768
|
885subblock_size=0
| |
886system=system
887tgts_per_mshr=20
| 873system=system
874tgts_per_mshr=20
|
888trace_addr=0
| |
889two_queue=false
890write_buffers=8
891cpu_side=system.cpu1.icache_port
892mem_side=system.toL2Bus.slave[2]
893
894[system.cpu1.interrupts]
895type=SparcInterrupts
896
| 875two_queue=false
876write_buffers=8
877cpu_side=system.cpu1.icache_port
878mem_side=system.toL2Bus.slave[2]
879
880[system.cpu1.interrupts]
881type=SparcInterrupts
882
|
| 883[system.cpu1.isa]
884type=SparcISA
885
|
897[system.cpu1.itb]
898type=SparcTLB
899size=64
900
901[system.cpu1.tracer]
902type=ExeTracer
903
904[system.cpu2]
905type=DerivO3CPU
| 886[system.cpu1.itb]
887type=SparcTLB
888size=64
889
890[system.cpu1.tracer]
891type=ExeTracer
892
893[system.cpu2]
894type=DerivO3CPU
|
906children=dcache dtb fuPool icache interrupts itb tracer
| 895children=dcache dtb fuPool icache interrupts isa itb tracer
|
907BTBEntries=4096
908BTBTagSize=16
909LFSTSize=1024
910LQEntries=32
911LSQCheckLoads=true
912LSQDepCheckShift=4
913RASSize=16
914SQEntries=32
915SSITSize=1024
916activity=0
917backComSize=5
918cachePorts=200
919checker=Null
920choiceCtrBits=2
921choicePredictorSize=8192
922clock=500
923commitToDecodeDelay=1
924commitToFetchDelay=1
925commitToIEWDelay=1
926commitToRenameDelay=1
927commitWidth=8
928cpu_id=2
929decodeToFetchDelay=1
930decodeToRenameDelay=1
931decodeWidth=8
| 896BTBEntries=4096
897BTBTagSize=16
898LFSTSize=1024
899LQEntries=32
900LSQCheckLoads=true
901LSQDepCheckShift=4
902RASSize=16
903SQEntries=32
904SSITSize=1024
905activity=0
906backComSize=5
907cachePorts=200
908checker=Null
909choiceCtrBits=2
910choicePredictorSize=8192
911clock=500
912commitToDecodeDelay=1
913commitToFetchDelay=1
914commitToIEWDelay=1
915commitToRenameDelay=1
916commitWidth=8
917cpu_id=2
918decodeToFetchDelay=1
919decodeToRenameDelay=1
920decodeWidth=8
|
932defer_registration=false
| |
933dispatchWidth=8
934do_checkpoint_insts=true
935do_quiesce=true
936do_statistics_insts=true
937dtb=system.cpu2.dtb
938fetchToDecodeDelay=1
939fetchTrapLatency=1
940fetchWidth=8
941forwardComSize=5
942fuPool=system.cpu2.fuPool
943function_trace=false
944function_trace_start=0
945globalCtrBits=2
946globalHistoryBits=13
947globalPredictorSize=8192
948iewToCommitDelay=1
949iewToDecodeDelay=1
950iewToFetchDelay=1
951iewToRenameDelay=1
952instShiftAmt=2
953interrupts=system.cpu2.interrupts
| 921dispatchWidth=8
922do_checkpoint_insts=true
923do_quiesce=true
924do_statistics_insts=true
925dtb=system.cpu2.dtb
926fetchToDecodeDelay=1
927fetchTrapLatency=1
928fetchWidth=8
929forwardComSize=5
930fuPool=system.cpu2.fuPool
931function_trace=false
932function_trace_start=0
933globalCtrBits=2
934globalHistoryBits=13
935globalPredictorSize=8192
936iewToCommitDelay=1
937iewToDecodeDelay=1
938iewToFetchDelay=1
939iewToRenameDelay=1
940instShiftAmt=2
941interrupts=system.cpu2.interrupts
|
| 942isa=system.cpu2.isa
|
954issueToExecuteDelay=1
955issueWidth=8
956itb=system.cpu2.itb
957localCtrBits=2
958localHistoryBits=11
959localHistoryTableSize=2048
960localPredictorSize=2048
961max_insts_all_threads=0
962max_insts_any_thread=0
963max_loads_all_threads=0
964max_loads_any_thread=0
965needsTSO=false
966numIQEntries=64
967numPhysFloatRegs=256
968numPhysIntRegs=256
969numROBEntries=192
970numRobs=1
971numThreads=1
972predType=tournament
973profile=0
974progress_interval=0
975renameToDecodeDelay=1
976renameToFetchDelay=1
977renameToIEWDelay=2
978renameToROBDelay=1
979renameWidth=8
980smtCommitPolicy=RoundRobin
981smtFetchPolicy=SingleThread
982smtIQPolicy=Partitioned
983smtIQThreshold=100
984smtLSQPolicy=Partitioned
985smtLSQThreshold=100
986smtNumFetchingThreads=1
987smtROBPolicy=Partitioned
988smtROBThreshold=100
989squashWidth=8
990store_set_clear_period=250000
| 943issueToExecuteDelay=1
944issueWidth=8
945itb=system.cpu2.itb
946localCtrBits=2
947localHistoryBits=11
948localHistoryTableSize=2048
949localPredictorSize=2048
950max_insts_all_threads=0
951max_insts_any_thread=0
952max_loads_all_threads=0
953max_loads_any_thread=0
954needsTSO=false
955numIQEntries=64
956numPhysFloatRegs=256
957numPhysIntRegs=256
958numROBEntries=192
959numRobs=1
960numThreads=1
961predType=tournament
962profile=0
963progress_interval=0
964renameToDecodeDelay=1
965renameToFetchDelay=1
966renameToIEWDelay=2
967renameToROBDelay=1
968renameWidth=8
969smtCommitPolicy=RoundRobin
970smtFetchPolicy=SingleThread
971smtIQPolicy=Partitioned
972smtIQThreshold=100
973smtLSQPolicy=Partitioned
974smtLSQThreshold=100
975smtNumFetchingThreads=1
976smtROBPolicy=Partitioned
977smtROBThreshold=100
978squashWidth=8
979store_set_clear_period=250000
|
| 980switched_out=false
|
991system=system
992tracer=system.cpu2.tracer
993trapLatency=13
994wbDepth=1
995wbWidth=8
996workload=system.cpu0.workload
997dcache_port=system.cpu2.dcache.cpu_side
998icache_port=system.cpu2.icache.cpu_side
999
1000[system.cpu2.dcache]
1001type=BaseCache
1002addr_ranges=0:18446744073709551615
1003assoc=4
1004block_size=64
1005clock=500
1006forward_snoops=true
| 981system=system
982tracer=system.cpu2.tracer
983trapLatency=13
984wbDepth=1
985wbWidth=8
986workload=system.cpu0.workload
987dcache_port=system.cpu2.dcache.cpu_side
988icache_port=system.cpu2.icache.cpu_side
989
990[system.cpu2.dcache]
991type=BaseCache
992addr_ranges=0:18446744073709551615
993assoc=4
994block_size=64
995clock=500
996forward_snoops=true
|
1007hash_delay=1
| |
1008hit_latency=2
1009is_top_level=true
1010max_miss_count=0
1011mshrs=4
1012prefetch_on_access=false
1013prefetcher=Null
| 997hit_latency=2
998is_top_level=true
999max_miss_count=0
1000mshrs=4
1001prefetch_on_access=false
1002prefetcher=Null
|
1014prioritizeRequests=false
1015repl=Null
| |
1016response_latency=2
1017size=32768
| 1003response_latency=2
1004size=32768
|
1018subblock_size=0
| |
1019system=system
1020tgts_per_mshr=20
| 1005system=system
1006tgts_per_mshr=20
|
1021trace_addr=0
| |
1022two_queue=false
1023write_buffers=8
1024cpu_side=system.cpu2.dcache_port
1025mem_side=system.toL2Bus.slave[5]
1026
1027[system.cpu2.dtb]
1028type=SparcTLB
1029size=64
1030
1031[system.cpu2.fuPool]
1032type=FUPool
1033children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
1034FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8
1035
1036[system.cpu2.fuPool.FUList0]
1037type=FUDesc
1038children=opList
1039count=6
1040opList=system.cpu2.fuPool.FUList0.opList
1041
1042[system.cpu2.fuPool.FUList0.opList]
1043type=OpDesc
1044issueLat=1
1045opClass=IntAlu
1046opLat=1
1047
1048[system.cpu2.fuPool.FUList1]
1049type=FUDesc
1050children=opList0 opList1
1051count=2
1052opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
1053
1054[system.cpu2.fuPool.FUList1.opList0]
1055type=OpDesc
1056issueLat=1
1057opClass=IntMult
1058opLat=3
1059
1060[system.cpu2.fuPool.FUList1.opList1]
1061type=OpDesc
1062issueLat=19
1063opClass=IntDiv
1064opLat=20
1065
1066[system.cpu2.fuPool.FUList2]
1067type=FUDesc
1068children=opList0 opList1 opList2
1069count=4
1070opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2
1071
1072[system.cpu2.fuPool.FUList2.opList0]
1073type=OpDesc
1074issueLat=1
1075opClass=FloatAdd
1076opLat=2
1077
1078[system.cpu2.fuPool.FUList2.opList1]
1079type=OpDesc
1080issueLat=1
1081opClass=FloatCmp
1082opLat=2
1083
1084[system.cpu2.fuPool.FUList2.opList2]
1085type=OpDesc
1086issueLat=1
1087opClass=FloatCvt
1088opLat=2
1089
1090[system.cpu2.fuPool.FUList3]
1091type=FUDesc
1092children=opList0 opList1 opList2
1093count=2
1094opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2
1095
1096[system.cpu2.fuPool.FUList3.opList0]
1097type=OpDesc
1098issueLat=1
1099opClass=FloatMult
1100opLat=4
1101
1102[system.cpu2.fuPool.FUList3.opList1]
1103type=OpDesc
1104issueLat=12
1105opClass=FloatDiv
1106opLat=12
1107
1108[system.cpu2.fuPool.FUList3.opList2]
1109type=OpDesc
1110issueLat=24
1111opClass=FloatSqrt
1112opLat=24
1113
1114[system.cpu2.fuPool.FUList4]
1115type=FUDesc
1116children=opList
1117count=0
1118opList=system.cpu2.fuPool.FUList4.opList
1119
1120[system.cpu2.fuPool.FUList4.opList]
1121type=OpDesc
1122issueLat=1
1123opClass=MemRead
1124opLat=1
1125
1126[system.cpu2.fuPool.FUList5]
1127type=FUDesc
1128children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
1129count=4
1130opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19
1131
1132[system.cpu2.fuPool.FUList5.opList00]
1133type=OpDesc
1134issueLat=1
1135opClass=SimdAdd
1136opLat=1
1137
1138[system.cpu2.fuPool.FUList5.opList01]
1139type=OpDesc
1140issueLat=1
1141opClass=SimdAddAcc
1142opLat=1
1143
1144[system.cpu2.fuPool.FUList5.opList02]
1145type=OpDesc
1146issueLat=1
1147opClass=SimdAlu
1148opLat=1
1149
1150[system.cpu2.fuPool.FUList5.opList03]
1151type=OpDesc
1152issueLat=1
1153opClass=SimdCmp
1154opLat=1
1155
1156[system.cpu2.fuPool.FUList5.opList04]
1157type=OpDesc
1158issueLat=1
1159opClass=SimdCvt
1160opLat=1
1161
1162[system.cpu2.fuPool.FUList5.opList05]
1163type=OpDesc
1164issueLat=1
1165opClass=SimdMisc
1166opLat=1
1167
1168[system.cpu2.fuPool.FUList5.opList06]
1169type=OpDesc
1170issueLat=1
1171opClass=SimdMult
1172opLat=1
1173
1174[system.cpu2.fuPool.FUList5.opList07]
1175type=OpDesc
1176issueLat=1
1177opClass=SimdMultAcc
1178opLat=1
1179
1180[system.cpu2.fuPool.FUList5.opList08]
1181type=OpDesc
1182issueLat=1
1183opClass=SimdShift
1184opLat=1
1185
1186[system.cpu2.fuPool.FUList5.opList09]
1187type=OpDesc
1188issueLat=1
1189opClass=SimdShiftAcc
1190opLat=1
1191
1192[system.cpu2.fuPool.FUList5.opList10]
1193type=OpDesc
1194issueLat=1
1195opClass=SimdSqrt
1196opLat=1
1197
1198[system.cpu2.fuPool.FUList5.opList11]
1199type=OpDesc
1200issueLat=1
1201opClass=SimdFloatAdd
1202opLat=1
1203
1204[system.cpu2.fuPool.FUList5.opList12]
1205type=OpDesc
1206issueLat=1
1207opClass=SimdFloatAlu
1208opLat=1
1209
1210[system.cpu2.fuPool.FUList5.opList13]
1211type=OpDesc
1212issueLat=1
1213opClass=SimdFloatCmp
1214opLat=1
1215
1216[system.cpu2.fuPool.FUList5.opList14]
1217type=OpDesc
1218issueLat=1
1219opClass=SimdFloatCvt
1220opLat=1
1221
1222[system.cpu2.fuPool.FUList5.opList15]
1223type=OpDesc
1224issueLat=1
1225opClass=SimdFloatDiv
1226opLat=1
1227
1228[system.cpu2.fuPool.FUList5.opList16]
1229type=OpDesc
1230issueLat=1
1231opClass=SimdFloatMisc
1232opLat=1
1233
1234[system.cpu2.fuPool.FUList5.opList17]
1235type=OpDesc
1236issueLat=1
1237opClass=SimdFloatMult
1238opLat=1
1239
1240[system.cpu2.fuPool.FUList5.opList18]
1241type=OpDesc
1242issueLat=1
1243opClass=SimdFloatMultAcc
1244opLat=1
1245
1246[system.cpu2.fuPool.FUList5.opList19]
1247type=OpDesc
1248issueLat=1
1249opClass=SimdFloatSqrt
1250opLat=1
1251
1252[system.cpu2.fuPool.FUList6]
1253type=FUDesc
1254children=opList
1255count=0
1256opList=system.cpu2.fuPool.FUList6.opList
1257
1258[system.cpu2.fuPool.FUList6.opList]
1259type=OpDesc
1260issueLat=1
1261opClass=MemWrite
1262opLat=1
1263
1264[system.cpu2.fuPool.FUList7]
1265type=FUDesc
1266children=opList0 opList1
1267count=4
1268opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
1269
1270[system.cpu2.fuPool.FUList7.opList0]
1271type=OpDesc
1272issueLat=1
1273opClass=MemRead
1274opLat=1
1275
1276[system.cpu2.fuPool.FUList7.opList1]
1277type=OpDesc
1278issueLat=1
1279opClass=MemWrite
1280opLat=1
1281
1282[system.cpu2.fuPool.FUList8]
1283type=FUDesc
1284children=opList
1285count=1
1286opList=system.cpu2.fuPool.FUList8.opList
1287
1288[system.cpu2.fuPool.FUList8.opList]
1289type=OpDesc
1290issueLat=3
1291opClass=IprAccess
1292opLat=3
1293
1294[system.cpu2.icache]
1295type=BaseCache
1296addr_ranges=0:18446744073709551615
1297assoc=1
1298block_size=64
1299clock=500
1300forward_snoops=true
| 1007two_queue=false
1008write_buffers=8
1009cpu_side=system.cpu2.dcache_port
1010mem_side=system.toL2Bus.slave[5]
1011
1012[system.cpu2.dtb]
1013type=SparcTLB
1014size=64
1015
1016[system.cpu2.fuPool]
1017type=FUPool
1018children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
1019FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8
1020
1021[system.cpu2.fuPool.FUList0]
1022type=FUDesc
1023children=opList
1024count=6
1025opList=system.cpu2.fuPool.FUList0.opList
1026
1027[system.cpu2.fuPool.FUList0.opList]
1028type=OpDesc
1029issueLat=1
1030opClass=IntAlu
1031opLat=1
1032
1033[system.cpu2.fuPool.FUList1]
1034type=FUDesc
1035children=opList0 opList1
1036count=2
1037opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
1038
1039[system.cpu2.fuPool.FUList1.opList0]
1040type=OpDesc
1041issueLat=1
1042opClass=IntMult
1043opLat=3
1044
1045[system.cpu2.fuPool.FUList1.opList1]
1046type=OpDesc
1047issueLat=19
1048opClass=IntDiv
1049opLat=20
1050
1051[system.cpu2.fuPool.FUList2]
1052type=FUDesc
1053children=opList0 opList1 opList2
1054count=4
1055opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2
1056
1057[system.cpu2.fuPool.FUList2.opList0]
1058type=OpDesc
1059issueLat=1
1060opClass=FloatAdd
1061opLat=2
1062
1063[system.cpu2.fuPool.FUList2.opList1]
1064type=OpDesc
1065issueLat=1
1066opClass=FloatCmp
1067opLat=2
1068
1069[system.cpu2.fuPool.FUList2.opList2]
1070type=OpDesc
1071issueLat=1
1072opClass=FloatCvt
1073opLat=2
1074
1075[system.cpu2.fuPool.FUList3]
1076type=FUDesc
1077children=opList0 opList1 opList2
1078count=2
1079opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2
1080
1081[system.cpu2.fuPool.FUList3.opList0]
1082type=OpDesc
1083issueLat=1
1084opClass=FloatMult
1085opLat=4
1086
1087[system.cpu2.fuPool.FUList3.opList1]
1088type=OpDesc
1089issueLat=12
1090opClass=FloatDiv
1091opLat=12
1092
1093[system.cpu2.fuPool.FUList3.opList2]
1094type=OpDesc
1095issueLat=24
1096opClass=FloatSqrt
1097opLat=24
1098
1099[system.cpu2.fuPool.FUList4]
1100type=FUDesc
1101children=opList
1102count=0
1103opList=system.cpu2.fuPool.FUList4.opList
1104
1105[system.cpu2.fuPool.FUList4.opList]
1106type=OpDesc
1107issueLat=1
1108opClass=MemRead
1109opLat=1
1110
1111[system.cpu2.fuPool.FUList5]
1112type=FUDesc
1113children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
1114count=4
1115opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19
1116
1117[system.cpu2.fuPool.FUList5.opList00]
1118type=OpDesc
1119issueLat=1
1120opClass=SimdAdd
1121opLat=1
1122
1123[system.cpu2.fuPool.FUList5.opList01]
1124type=OpDesc
1125issueLat=1
1126opClass=SimdAddAcc
1127opLat=1
1128
1129[system.cpu2.fuPool.FUList5.opList02]
1130type=OpDesc
1131issueLat=1
1132opClass=SimdAlu
1133opLat=1
1134
1135[system.cpu2.fuPool.FUList5.opList03]
1136type=OpDesc
1137issueLat=1
1138opClass=SimdCmp
1139opLat=1
1140
1141[system.cpu2.fuPool.FUList5.opList04]
1142type=OpDesc
1143issueLat=1
1144opClass=SimdCvt
1145opLat=1
1146
1147[system.cpu2.fuPool.FUList5.opList05]
1148type=OpDesc
1149issueLat=1
1150opClass=SimdMisc
1151opLat=1
1152
1153[system.cpu2.fuPool.FUList5.opList06]
1154type=OpDesc
1155issueLat=1
1156opClass=SimdMult
1157opLat=1
1158
1159[system.cpu2.fuPool.FUList5.opList07]
1160type=OpDesc
1161issueLat=1
1162opClass=SimdMultAcc
1163opLat=1
1164
1165[system.cpu2.fuPool.FUList5.opList08]
1166type=OpDesc
1167issueLat=1
1168opClass=SimdShift
1169opLat=1
1170
1171[system.cpu2.fuPool.FUList5.opList09]
1172type=OpDesc
1173issueLat=1
1174opClass=SimdShiftAcc
1175opLat=1
1176
1177[system.cpu2.fuPool.FUList5.opList10]
1178type=OpDesc
1179issueLat=1
1180opClass=SimdSqrt
1181opLat=1
1182
1183[system.cpu2.fuPool.FUList5.opList11]
1184type=OpDesc
1185issueLat=1
1186opClass=SimdFloatAdd
1187opLat=1
1188
1189[system.cpu2.fuPool.FUList5.opList12]
1190type=OpDesc
1191issueLat=1
1192opClass=SimdFloatAlu
1193opLat=1
1194
1195[system.cpu2.fuPool.FUList5.opList13]
1196type=OpDesc
1197issueLat=1
1198opClass=SimdFloatCmp
1199opLat=1
1200
1201[system.cpu2.fuPool.FUList5.opList14]
1202type=OpDesc
1203issueLat=1
1204opClass=SimdFloatCvt
1205opLat=1
1206
1207[system.cpu2.fuPool.FUList5.opList15]
1208type=OpDesc
1209issueLat=1
1210opClass=SimdFloatDiv
1211opLat=1
1212
1213[system.cpu2.fuPool.FUList5.opList16]
1214type=OpDesc
1215issueLat=1
1216opClass=SimdFloatMisc
1217opLat=1
1218
1219[system.cpu2.fuPool.FUList5.opList17]
1220type=OpDesc
1221issueLat=1
1222opClass=SimdFloatMult
1223opLat=1
1224
1225[system.cpu2.fuPool.FUList5.opList18]
1226type=OpDesc
1227issueLat=1
1228opClass=SimdFloatMultAcc
1229opLat=1
1230
1231[system.cpu2.fuPool.FUList5.opList19]
1232type=OpDesc
1233issueLat=1
1234opClass=SimdFloatSqrt
1235opLat=1
1236
1237[system.cpu2.fuPool.FUList6]
1238type=FUDesc
1239children=opList
1240count=0
1241opList=system.cpu2.fuPool.FUList6.opList
1242
1243[system.cpu2.fuPool.FUList6.opList]
1244type=OpDesc
1245issueLat=1
1246opClass=MemWrite
1247opLat=1
1248
1249[system.cpu2.fuPool.FUList7]
1250type=FUDesc
1251children=opList0 opList1
1252count=4
1253opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
1254
1255[system.cpu2.fuPool.FUList7.opList0]
1256type=OpDesc
1257issueLat=1
1258opClass=MemRead
1259opLat=1
1260
1261[system.cpu2.fuPool.FUList7.opList1]
1262type=OpDesc
1263issueLat=1
1264opClass=MemWrite
1265opLat=1
1266
1267[system.cpu2.fuPool.FUList8]
1268type=FUDesc
1269children=opList
1270count=1
1271opList=system.cpu2.fuPool.FUList8.opList
1272
1273[system.cpu2.fuPool.FUList8.opList]
1274type=OpDesc
1275issueLat=3
1276opClass=IprAccess
1277opLat=3
1278
1279[system.cpu2.icache]
1280type=BaseCache
1281addr_ranges=0:18446744073709551615
1282assoc=1
1283block_size=64
1284clock=500
1285forward_snoops=true
|
1301hash_delay=1
| |
1302hit_latency=2
1303is_top_level=true
1304max_miss_count=0
1305mshrs=4
1306prefetch_on_access=false
1307prefetcher=Null
| 1286hit_latency=2
1287is_top_level=true
1288max_miss_count=0
1289mshrs=4
1290prefetch_on_access=false
1291prefetcher=Null
|
1308prioritizeRequests=false
1309repl=Null
| |
1310response_latency=2
1311size=32768
| 1292response_latency=2
1293size=32768
|
1312subblock_size=0
| |
1313system=system
1314tgts_per_mshr=20
| 1294system=system
1295tgts_per_mshr=20
|
1315trace_addr=0
| |
1316two_queue=false
1317write_buffers=8
1318cpu_side=system.cpu2.icache_port
1319mem_side=system.toL2Bus.slave[4]
1320
1321[system.cpu2.interrupts]
1322type=SparcInterrupts
1323
| 1296two_queue=false
1297write_buffers=8
1298cpu_side=system.cpu2.icache_port
1299mem_side=system.toL2Bus.slave[4]
1300
1301[system.cpu2.interrupts]
1302type=SparcInterrupts
1303
|
| 1304[system.cpu2.isa]
1305type=SparcISA
1306
|
1324[system.cpu2.itb]
1325type=SparcTLB
1326size=64
1327
1328[system.cpu2.tracer]
1329type=ExeTracer
1330
1331[system.cpu3]
1332type=DerivO3CPU
| 1307[system.cpu2.itb]
1308type=SparcTLB
1309size=64
1310
1311[system.cpu2.tracer]
1312type=ExeTracer
1313
1314[system.cpu3]
1315type=DerivO3CPU
|
1333children=dcache dtb fuPool icache interrupts itb tracer
| 1316children=dcache dtb fuPool icache interrupts isa itb tracer
|
1334BTBEntries=4096
1335BTBTagSize=16
1336LFSTSize=1024
1337LQEntries=32
1338LSQCheckLoads=true
1339LSQDepCheckShift=4
1340RASSize=16
1341SQEntries=32
1342SSITSize=1024
1343activity=0
1344backComSize=5
1345cachePorts=200
1346checker=Null
1347choiceCtrBits=2
1348choicePredictorSize=8192
1349clock=500
1350commitToDecodeDelay=1
1351commitToFetchDelay=1
1352commitToIEWDelay=1
1353commitToRenameDelay=1
1354commitWidth=8
1355cpu_id=3
1356decodeToFetchDelay=1
1357decodeToRenameDelay=1
1358decodeWidth=8
| 1317BTBEntries=4096
1318BTBTagSize=16
1319LFSTSize=1024
1320LQEntries=32
1321LSQCheckLoads=true
1322LSQDepCheckShift=4
1323RASSize=16
1324SQEntries=32
1325SSITSize=1024
1326activity=0
1327backComSize=5
1328cachePorts=200
1329checker=Null
1330choiceCtrBits=2
1331choicePredictorSize=8192
1332clock=500
1333commitToDecodeDelay=1
1334commitToFetchDelay=1
1335commitToIEWDelay=1
1336commitToRenameDelay=1
1337commitWidth=8
1338cpu_id=3
1339decodeToFetchDelay=1
1340decodeToRenameDelay=1
1341decodeWidth=8
|
1359defer_registration=false
| |
1360dispatchWidth=8
1361do_checkpoint_insts=true
1362do_quiesce=true
1363do_statistics_insts=true
1364dtb=system.cpu3.dtb
1365fetchToDecodeDelay=1
1366fetchTrapLatency=1
1367fetchWidth=8
1368forwardComSize=5
1369fuPool=system.cpu3.fuPool
1370function_trace=false
1371function_trace_start=0
1372globalCtrBits=2
1373globalHistoryBits=13
1374globalPredictorSize=8192
1375iewToCommitDelay=1
1376iewToDecodeDelay=1
1377iewToFetchDelay=1
1378iewToRenameDelay=1
1379instShiftAmt=2
1380interrupts=system.cpu3.interrupts
| 1342dispatchWidth=8
1343do_checkpoint_insts=true
1344do_quiesce=true
1345do_statistics_insts=true
1346dtb=system.cpu3.dtb
1347fetchToDecodeDelay=1
1348fetchTrapLatency=1
1349fetchWidth=8
1350forwardComSize=5
1351fuPool=system.cpu3.fuPool
1352function_trace=false
1353function_trace_start=0
1354globalCtrBits=2
1355globalHistoryBits=13
1356globalPredictorSize=8192
1357iewToCommitDelay=1
1358iewToDecodeDelay=1
1359iewToFetchDelay=1
1360iewToRenameDelay=1
1361instShiftAmt=2
1362interrupts=system.cpu3.interrupts
|
| 1363isa=system.cpu3.isa
|
1381issueToExecuteDelay=1
1382issueWidth=8
1383itb=system.cpu3.itb
1384localCtrBits=2
1385localHistoryBits=11
1386localHistoryTableSize=2048
1387localPredictorSize=2048
1388max_insts_all_threads=0
1389max_insts_any_thread=0
1390max_loads_all_threads=0
1391max_loads_any_thread=0
1392needsTSO=false
1393numIQEntries=64
1394numPhysFloatRegs=256
1395numPhysIntRegs=256
1396numROBEntries=192
1397numRobs=1
1398numThreads=1
1399predType=tournament
1400profile=0
1401progress_interval=0
1402renameToDecodeDelay=1
1403renameToFetchDelay=1
1404renameToIEWDelay=2
1405renameToROBDelay=1
1406renameWidth=8
1407smtCommitPolicy=RoundRobin
1408smtFetchPolicy=SingleThread
1409smtIQPolicy=Partitioned
1410smtIQThreshold=100
1411smtLSQPolicy=Partitioned
1412smtLSQThreshold=100
1413smtNumFetchingThreads=1
1414smtROBPolicy=Partitioned
1415smtROBThreshold=100
1416squashWidth=8
1417store_set_clear_period=250000
| 1364issueToExecuteDelay=1
1365issueWidth=8
1366itb=system.cpu3.itb
1367localCtrBits=2
1368localHistoryBits=11
1369localHistoryTableSize=2048
1370localPredictorSize=2048
1371max_insts_all_threads=0
1372max_insts_any_thread=0
1373max_loads_all_threads=0
1374max_loads_any_thread=0
1375needsTSO=false
1376numIQEntries=64
1377numPhysFloatRegs=256
1378numPhysIntRegs=256
1379numROBEntries=192
1380numRobs=1
1381numThreads=1
1382predType=tournament
1383profile=0
1384progress_interval=0
1385renameToDecodeDelay=1
1386renameToFetchDelay=1
1387renameToIEWDelay=2
1388renameToROBDelay=1
1389renameWidth=8
1390smtCommitPolicy=RoundRobin
1391smtFetchPolicy=SingleThread
1392smtIQPolicy=Partitioned
1393smtIQThreshold=100
1394smtLSQPolicy=Partitioned
1395smtLSQThreshold=100
1396smtNumFetchingThreads=1
1397smtROBPolicy=Partitioned
1398smtROBThreshold=100
1399squashWidth=8
1400store_set_clear_period=250000
|
| 1401switched_out=false
|
1418system=system
1419tracer=system.cpu3.tracer
1420trapLatency=13
1421wbDepth=1
1422wbWidth=8
1423workload=system.cpu0.workload
1424dcache_port=system.cpu3.dcache.cpu_side
1425icache_port=system.cpu3.icache.cpu_side
1426
1427[system.cpu3.dcache]
1428type=BaseCache
1429addr_ranges=0:18446744073709551615
1430assoc=4
1431block_size=64
1432clock=500
1433forward_snoops=true
| 1402system=system
1403tracer=system.cpu3.tracer
1404trapLatency=13
1405wbDepth=1
1406wbWidth=8
1407workload=system.cpu0.workload
1408dcache_port=system.cpu3.dcache.cpu_side
1409icache_port=system.cpu3.icache.cpu_side
1410
1411[system.cpu3.dcache]
1412type=BaseCache
1413addr_ranges=0:18446744073709551615
1414assoc=4
1415block_size=64
1416clock=500
1417forward_snoops=true
|
1434hash_delay=1
| |
1435hit_latency=2
1436is_top_level=true
1437max_miss_count=0
1438mshrs=4
1439prefetch_on_access=false
1440prefetcher=Null
| 1418hit_latency=2
1419is_top_level=true
1420max_miss_count=0
1421mshrs=4
1422prefetch_on_access=false
1423prefetcher=Null
|
1441prioritizeRequests=false
1442repl=Null
| |
1443response_latency=2
1444size=32768
| 1424response_latency=2
1425size=32768
|
1445subblock_size=0
| |
1446system=system
1447tgts_per_mshr=20
| 1426system=system
1427tgts_per_mshr=20
|
1448trace_addr=0
| |
1449two_queue=false
1450write_buffers=8
1451cpu_side=system.cpu3.dcache_port
1452mem_side=system.toL2Bus.slave[7]
1453
1454[system.cpu3.dtb]
1455type=SparcTLB
1456size=64
1457
1458[system.cpu3.fuPool]
1459type=FUPool
1460children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
1461FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8
1462
1463[system.cpu3.fuPool.FUList0]
1464type=FUDesc
1465children=opList
1466count=6
1467opList=system.cpu3.fuPool.FUList0.opList
1468
1469[system.cpu3.fuPool.FUList0.opList]
1470type=OpDesc
1471issueLat=1
1472opClass=IntAlu
1473opLat=1
1474
1475[system.cpu3.fuPool.FUList1]
1476type=FUDesc
1477children=opList0 opList1
1478count=2
1479opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1
1480
1481[system.cpu3.fuPool.FUList1.opList0]
1482type=OpDesc
1483issueLat=1
1484opClass=IntMult
1485opLat=3
1486
1487[system.cpu3.fuPool.FUList1.opList1]
1488type=OpDesc
1489issueLat=19
1490opClass=IntDiv
1491opLat=20
1492
1493[system.cpu3.fuPool.FUList2]
1494type=FUDesc
1495children=opList0 opList1 opList2
1496count=4
1497opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2
1498
1499[system.cpu3.fuPool.FUList2.opList0]
1500type=OpDesc
1501issueLat=1
1502opClass=FloatAdd
1503opLat=2
1504
1505[system.cpu3.fuPool.FUList2.opList1]
1506type=OpDesc
1507issueLat=1
1508opClass=FloatCmp
1509opLat=2
1510
1511[system.cpu3.fuPool.FUList2.opList2]
1512type=OpDesc
1513issueLat=1
1514opClass=FloatCvt
1515opLat=2
1516
1517[system.cpu3.fuPool.FUList3]
1518type=FUDesc
1519children=opList0 opList1 opList2
1520count=2
1521opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2
1522
1523[system.cpu3.fuPool.FUList3.opList0]
1524type=OpDesc
1525issueLat=1
1526opClass=FloatMult
1527opLat=4
1528
1529[system.cpu3.fuPool.FUList3.opList1]
1530type=OpDesc
1531issueLat=12
1532opClass=FloatDiv
1533opLat=12
1534
1535[system.cpu3.fuPool.FUList3.opList2]
1536type=OpDesc
1537issueLat=24
1538opClass=FloatSqrt
1539opLat=24
1540
1541[system.cpu3.fuPool.FUList4]
1542type=FUDesc
1543children=opList
1544count=0
1545opList=system.cpu3.fuPool.FUList4.opList
1546
1547[system.cpu3.fuPool.FUList4.opList]
1548type=OpDesc
1549issueLat=1
1550opClass=MemRead
1551opLat=1
1552
1553[system.cpu3.fuPool.FUList5]
1554type=FUDesc
1555children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
1556count=4
1557opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19
1558
1559[system.cpu3.fuPool.FUList5.opList00]
1560type=OpDesc
1561issueLat=1
1562opClass=SimdAdd
1563opLat=1
1564
1565[system.cpu3.fuPool.FUList5.opList01]
1566type=OpDesc
1567issueLat=1
1568opClass=SimdAddAcc
1569opLat=1
1570
1571[system.cpu3.fuPool.FUList5.opList02]
1572type=OpDesc
1573issueLat=1
1574opClass=SimdAlu
1575opLat=1
1576
1577[system.cpu3.fuPool.FUList5.opList03]
1578type=OpDesc
1579issueLat=1
1580opClass=SimdCmp
1581opLat=1
1582
1583[system.cpu3.fuPool.FUList5.opList04]
1584type=OpDesc
1585issueLat=1
1586opClass=SimdCvt
1587opLat=1
1588
1589[system.cpu3.fuPool.FUList5.opList05]
1590type=OpDesc
1591issueLat=1
1592opClass=SimdMisc
1593opLat=1
1594
1595[system.cpu3.fuPool.FUList5.opList06]
1596type=OpDesc
1597issueLat=1
1598opClass=SimdMult
1599opLat=1
1600
1601[system.cpu3.fuPool.FUList5.opList07]
1602type=OpDesc
1603issueLat=1
1604opClass=SimdMultAcc
1605opLat=1
1606
1607[system.cpu3.fuPool.FUList5.opList08]
1608type=OpDesc
1609issueLat=1
1610opClass=SimdShift
1611opLat=1
1612
1613[system.cpu3.fuPool.FUList5.opList09]
1614type=OpDesc
1615issueLat=1
1616opClass=SimdShiftAcc
1617opLat=1
1618
1619[system.cpu3.fuPool.FUList5.opList10]
1620type=OpDesc
1621issueLat=1
1622opClass=SimdSqrt
1623opLat=1
1624
1625[system.cpu3.fuPool.FUList5.opList11]
1626type=OpDesc
1627issueLat=1
1628opClass=SimdFloatAdd
1629opLat=1
1630
1631[system.cpu3.fuPool.FUList5.opList12]
1632type=OpDesc
1633issueLat=1
1634opClass=SimdFloatAlu
1635opLat=1
1636
1637[system.cpu3.fuPool.FUList5.opList13]
1638type=OpDesc
1639issueLat=1
1640opClass=SimdFloatCmp
1641opLat=1
1642
1643[system.cpu3.fuPool.FUList5.opList14]
1644type=OpDesc
1645issueLat=1
1646opClass=SimdFloatCvt
1647opLat=1
1648
1649[system.cpu3.fuPool.FUList5.opList15]
1650type=OpDesc
1651issueLat=1
1652opClass=SimdFloatDiv
1653opLat=1
1654
1655[system.cpu3.fuPool.FUList5.opList16]
1656type=OpDesc
1657issueLat=1
1658opClass=SimdFloatMisc
1659opLat=1
1660
1661[system.cpu3.fuPool.FUList5.opList17]
1662type=OpDesc
1663issueLat=1
1664opClass=SimdFloatMult
1665opLat=1
1666
1667[system.cpu3.fuPool.FUList5.opList18]
1668type=OpDesc
1669issueLat=1
1670opClass=SimdFloatMultAcc
1671opLat=1
1672
1673[system.cpu3.fuPool.FUList5.opList19]
1674type=OpDesc
1675issueLat=1
1676opClass=SimdFloatSqrt
1677opLat=1
1678
1679[system.cpu3.fuPool.FUList6]
1680type=FUDesc
1681children=opList
1682count=0
1683opList=system.cpu3.fuPool.FUList6.opList
1684
1685[system.cpu3.fuPool.FUList6.opList]
1686type=OpDesc
1687issueLat=1
1688opClass=MemWrite
1689opLat=1
1690
1691[system.cpu3.fuPool.FUList7]
1692type=FUDesc
1693children=opList0 opList1
1694count=4
1695opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1
1696
1697[system.cpu3.fuPool.FUList7.opList0]
1698type=OpDesc
1699issueLat=1
1700opClass=MemRead
1701opLat=1
1702
1703[system.cpu3.fuPool.FUList7.opList1]
1704type=OpDesc
1705issueLat=1
1706opClass=MemWrite
1707opLat=1
1708
1709[system.cpu3.fuPool.FUList8]
1710type=FUDesc
1711children=opList
1712count=1
1713opList=system.cpu3.fuPool.FUList8.opList
1714
1715[system.cpu3.fuPool.FUList8.opList]
1716type=OpDesc
1717issueLat=3
1718opClass=IprAccess
1719opLat=3
1720
1721[system.cpu3.icache]
1722type=BaseCache
1723addr_ranges=0:18446744073709551615
1724assoc=1
1725block_size=64
1726clock=500
1727forward_snoops=true
| 1428two_queue=false
1429write_buffers=8
1430cpu_side=system.cpu3.dcache_port
1431mem_side=system.toL2Bus.slave[7]
1432
1433[system.cpu3.dtb]
1434type=SparcTLB
1435size=64
1436
1437[system.cpu3.fuPool]
1438type=FUPool
1439children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
1440FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8
1441
1442[system.cpu3.fuPool.FUList0]
1443type=FUDesc
1444children=opList
1445count=6
1446opList=system.cpu3.fuPool.FUList0.opList
1447
1448[system.cpu3.fuPool.FUList0.opList]
1449type=OpDesc
1450issueLat=1
1451opClass=IntAlu
1452opLat=1
1453
1454[system.cpu3.fuPool.FUList1]
1455type=FUDesc
1456children=opList0 opList1
1457count=2
1458opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1
1459
1460[system.cpu3.fuPool.FUList1.opList0]
1461type=OpDesc
1462issueLat=1
1463opClass=IntMult
1464opLat=3
1465
1466[system.cpu3.fuPool.FUList1.opList1]
1467type=OpDesc
1468issueLat=19
1469opClass=IntDiv
1470opLat=20
1471
1472[system.cpu3.fuPool.FUList2]
1473type=FUDesc
1474children=opList0 opList1 opList2
1475count=4
1476opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2
1477
1478[system.cpu3.fuPool.FUList2.opList0]
1479type=OpDesc
1480issueLat=1
1481opClass=FloatAdd
1482opLat=2
1483
1484[system.cpu3.fuPool.FUList2.opList1]
1485type=OpDesc
1486issueLat=1
1487opClass=FloatCmp
1488opLat=2
1489
1490[system.cpu3.fuPool.FUList2.opList2]
1491type=OpDesc
1492issueLat=1
1493opClass=FloatCvt
1494opLat=2
1495
1496[system.cpu3.fuPool.FUList3]
1497type=FUDesc
1498children=opList0 opList1 opList2
1499count=2
1500opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2
1501
1502[system.cpu3.fuPool.FUList3.opList0]
1503type=OpDesc
1504issueLat=1
1505opClass=FloatMult
1506opLat=4
1507
1508[system.cpu3.fuPool.FUList3.opList1]
1509type=OpDesc
1510issueLat=12
1511opClass=FloatDiv
1512opLat=12
1513
1514[system.cpu3.fuPool.FUList3.opList2]
1515type=OpDesc
1516issueLat=24
1517opClass=FloatSqrt
1518opLat=24
1519
1520[system.cpu3.fuPool.FUList4]
1521type=FUDesc
1522children=opList
1523count=0
1524opList=system.cpu3.fuPool.FUList4.opList
1525
1526[system.cpu3.fuPool.FUList4.opList]
1527type=OpDesc
1528issueLat=1
1529opClass=MemRead
1530opLat=1
1531
1532[system.cpu3.fuPool.FUList5]
1533type=FUDesc
1534children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
1535count=4
1536opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19
1537
1538[system.cpu3.fuPool.FUList5.opList00]
1539type=OpDesc
1540issueLat=1
1541opClass=SimdAdd
1542opLat=1
1543
1544[system.cpu3.fuPool.FUList5.opList01]
1545type=OpDesc
1546issueLat=1
1547opClass=SimdAddAcc
1548opLat=1
1549
1550[system.cpu3.fuPool.FUList5.opList02]
1551type=OpDesc
1552issueLat=1
1553opClass=SimdAlu
1554opLat=1
1555
1556[system.cpu3.fuPool.FUList5.opList03]
1557type=OpDesc
1558issueLat=1
1559opClass=SimdCmp
1560opLat=1
1561
1562[system.cpu3.fuPool.FUList5.opList04]
1563type=OpDesc
1564issueLat=1
1565opClass=SimdCvt
1566opLat=1
1567
1568[system.cpu3.fuPool.FUList5.opList05]
1569type=OpDesc
1570issueLat=1
1571opClass=SimdMisc
1572opLat=1
1573
1574[system.cpu3.fuPool.FUList5.opList06]
1575type=OpDesc
1576issueLat=1
1577opClass=SimdMult
1578opLat=1
1579
1580[system.cpu3.fuPool.FUList5.opList07]
1581type=OpDesc
1582issueLat=1
1583opClass=SimdMultAcc
1584opLat=1
1585
1586[system.cpu3.fuPool.FUList5.opList08]
1587type=OpDesc
1588issueLat=1
1589opClass=SimdShift
1590opLat=1
1591
1592[system.cpu3.fuPool.FUList5.opList09]
1593type=OpDesc
1594issueLat=1
1595opClass=SimdShiftAcc
1596opLat=1
1597
1598[system.cpu3.fuPool.FUList5.opList10]
1599type=OpDesc
1600issueLat=1
1601opClass=SimdSqrt
1602opLat=1
1603
1604[system.cpu3.fuPool.FUList5.opList11]
1605type=OpDesc
1606issueLat=1
1607opClass=SimdFloatAdd
1608opLat=1
1609
1610[system.cpu3.fuPool.FUList5.opList12]
1611type=OpDesc
1612issueLat=1
1613opClass=SimdFloatAlu
1614opLat=1
1615
1616[system.cpu3.fuPool.FUList5.opList13]
1617type=OpDesc
1618issueLat=1
1619opClass=SimdFloatCmp
1620opLat=1
1621
1622[system.cpu3.fuPool.FUList5.opList14]
1623type=OpDesc
1624issueLat=1
1625opClass=SimdFloatCvt
1626opLat=1
1627
1628[system.cpu3.fuPool.FUList5.opList15]
1629type=OpDesc
1630issueLat=1
1631opClass=SimdFloatDiv
1632opLat=1
1633
1634[system.cpu3.fuPool.FUList5.opList16]
1635type=OpDesc
1636issueLat=1
1637opClass=SimdFloatMisc
1638opLat=1
1639
1640[system.cpu3.fuPool.FUList5.opList17]
1641type=OpDesc
1642issueLat=1
1643opClass=SimdFloatMult
1644opLat=1
1645
1646[system.cpu3.fuPool.FUList5.opList18]
1647type=OpDesc
1648issueLat=1
1649opClass=SimdFloatMultAcc
1650opLat=1
1651
1652[system.cpu3.fuPool.FUList5.opList19]
1653type=OpDesc
1654issueLat=1
1655opClass=SimdFloatSqrt
1656opLat=1
1657
1658[system.cpu3.fuPool.FUList6]
1659type=FUDesc
1660children=opList
1661count=0
1662opList=system.cpu3.fuPool.FUList6.opList
1663
1664[system.cpu3.fuPool.FUList6.opList]
1665type=OpDesc
1666issueLat=1
1667opClass=MemWrite
1668opLat=1
1669
1670[system.cpu3.fuPool.FUList7]
1671type=FUDesc
1672children=opList0 opList1
1673count=4
1674opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1
1675
1676[system.cpu3.fuPool.FUList7.opList0]
1677type=OpDesc
1678issueLat=1
1679opClass=MemRead
1680opLat=1
1681
1682[system.cpu3.fuPool.FUList7.opList1]
1683type=OpDesc
1684issueLat=1
1685opClass=MemWrite
1686opLat=1
1687
1688[system.cpu3.fuPool.FUList8]
1689type=FUDesc
1690children=opList
1691count=1
1692opList=system.cpu3.fuPool.FUList8.opList
1693
1694[system.cpu3.fuPool.FUList8.opList]
1695type=OpDesc
1696issueLat=3
1697opClass=IprAccess
1698opLat=3
1699
1700[system.cpu3.icache]
1701type=BaseCache
1702addr_ranges=0:18446744073709551615
1703assoc=1
1704block_size=64
1705clock=500
1706forward_snoops=true
|
1728hash_delay=1
| |
1729hit_latency=2
1730is_top_level=true
1731max_miss_count=0
1732mshrs=4
1733prefetch_on_access=false
1734prefetcher=Null
| 1707hit_latency=2
1708is_top_level=true
1709max_miss_count=0
1710mshrs=4
1711prefetch_on_access=false
1712prefetcher=Null
|
1735prioritizeRequests=false
1736repl=Null
| |
1737response_latency=2
1738size=32768
| 1713response_latency=2
1714size=32768
|
1739subblock_size=0
| |
1740system=system
1741tgts_per_mshr=20
| 1715system=system
1716tgts_per_mshr=20
|
1742trace_addr=0
| |
1743two_queue=false
1744write_buffers=8
1745cpu_side=system.cpu3.icache_port
1746mem_side=system.toL2Bus.slave[6]
1747
1748[system.cpu3.interrupts]
1749type=SparcInterrupts
1750
| 1717two_queue=false
1718write_buffers=8
1719cpu_side=system.cpu3.icache_port
1720mem_side=system.toL2Bus.slave[6]
1721
1722[system.cpu3.interrupts]
1723type=SparcInterrupts
1724
|
| 1725[system.cpu3.isa]
1726type=SparcISA
1727
|
1751[system.cpu3.itb]
1752type=SparcTLB
1753size=64
1754
1755[system.cpu3.tracer]
1756type=ExeTracer
1757
1758[system.l2c]
1759type=BaseCache
1760addr_ranges=0:18446744073709551615
1761assoc=8
1762block_size=64
1763clock=500
1764forward_snoops=true
| 1728[system.cpu3.itb]
1729type=SparcTLB
1730size=64
1731
1732[system.cpu3.tracer]
1733type=ExeTracer
1734
1735[system.l2c]
1736type=BaseCache
1737addr_ranges=0:18446744073709551615
1738assoc=8
1739block_size=64
1740clock=500
1741forward_snoops=true
|
1765hash_delay=1
| |
1766hit_latency=20
1767is_top_level=false
1768max_miss_count=0
1769mshrs=20
1770prefetch_on_access=false
1771prefetcher=Null
| 1742hit_latency=20
1743is_top_level=false
1744max_miss_count=0
1745mshrs=20
1746prefetch_on_access=false
1747prefetcher=Null
|
1772prioritizeRequests=false
1773repl=Null
| |
1774response_latency=20
1775size=4194304
| 1748response_latency=20
1749size=4194304
|
1776subblock_size=0
| |
1777system=system
1778tgts_per_mshr=12
| 1750system=system
1751tgts_per_mshr=12
|
1779trace_addr=0
| |
1780two_queue=false
1781write_buffers=8
1782cpu_side=system.toL2Bus.master[0]
1783mem_side=system.membus.slave[0]
1784
1785[system.membus]
1786type=CoherentBus
1787block_size=64
1788clock=1000
1789header_cycles=1
1790use_default_range=false
1791width=8
1792master=system.physmem.port
1793slave=system.l2c.mem_side system.system_port
1794
1795[system.physmem]
1796type=SimpleDRAM
1797addr_mapping=openmap
1798banks_per_rank=8
1799clock=1000
1800conf_table_reported=false
1801in_addr_map=true
1802lines_per_rowbuffer=64
1803mem_sched_policy=fcfs
1804null=false
1805page_policy=open
1806range=0:134217727
1807ranks_per_channel=2
1808read_buffer_size=32
1809tBURST=4000
1810tCL=14000
1811tRCD=14000
1812tREFI=7800000
1813tRFC=300000
1814tRP=14000
1815tWTR=1000
1816write_buffer_size=32
1817write_thresh_perc=70
1818zero=false
1819port=system.membus.master[0]
1820
1821[system.toL2Bus]
1822type=CoherentBus
1823block_size=64
1824clock=500
1825header_cycles=1
1826use_default_range=false
1827width=8
1828master=system.l2c.cpu_side
1829slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
1830
| 1752two_queue=false
1753write_buffers=8
1754cpu_side=system.toL2Bus.master[0]
1755mem_side=system.membus.slave[0]
1756
1757[system.membus]
1758type=CoherentBus
1759block_size=64
1760clock=1000
1761header_cycles=1
1762use_default_range=false
1763width=8
1764master=system.physmem.port
1765slave=system.l2c.mem_side system.system_port
1766
1767[system.physmem]
1768type=SimpleDRAM
1769addr_mapping=openmap
1770banks_per_rank=8
1771clock=1000
1772conf_table_reported=false
1773in_addr_map=true
1774lines_per_rowbuffer=64
1775mem_sched_policy=fcfs
1776null=false
1777page_policy=open
1778range=0:134217727
1779ranks_per_channel=2
1780read_buffer_size=32
1781tBURST=4000
1782tCL=14000
1783tRCD=14000
1784tREFI=7800000
1785tRFC=300000
1786tRP=14000
1787tWTR=1000
1788write_buffer_size=32
1789write_thresh_perc=70
1790zero=false
1791port=system.membus.master[0]
1792
1793[system.toL2Bus]
1794type=CoherentBus
1795block_size=64
1796clock=500
1797header_cycles=1
1798use_default_range=false
1799width=8
1800master=system.l2c.cpu_side
1801slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
1802
|