config.ini (8835:7c68f84d7c4e) config.ini (8983:8800b05e1cb3)
1[root]
2type=Root
3children=system
4full_system=false
5time_sync_enable=false
6time_sync_period=100000000000
7time_sync_spin_threshold=100000000
8
9[system]
10type=System
11children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
12boot_osflags=a
13init_param=0
14kernel=
15load_addr_mask=1099511627775
16mem_mode=timing
17memories=system.physmem
18num_work_ids=16
1[root]
2type=Root
3children=system
4full_system=false
5time_sync_enable=false
6time_sync_period=100000000000
7time_sync_spin_threshold=100000000
8
9[system]
10type=System
11children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
12boot_osflags=a
13init_param=0
14kernel=
15load_addr_mask=1099511627775
16mem_mode=timing
17memories=system.physmem
18num_work_ids=16
19physmem=system.physmem
20readfile=
21symbolfile=
22work_begin_ckpt_count=0
23work_begin_cpu_id_exit=-1
24work_begin_exit_count=0
25work_cpus_ckpt_count=0
26work_end_ckpt_count=0
27work_end_exit_count=0
28work_item_id=-1
19readfile=
20symbolfile=
21work_begin_ckpt_count=0
22work_begin_cpu_id_exit=-1
23work_begin_exit_count=0
24work_cpus_ckpt_count=0
25work_end_ckpt_count=0
26work_end_exit_count=0
27work_item_id=-1
29system_port=system.membus.port[2]
28system_port=system.membus.slave[1]
30
31[system.cpu0]
32type=DerivO3CPU
33children=dcache dtb fuPool icache interrupts itb tracer workload
34BTBEntries=4096
35BTBTagSize=16
36LFSTSize=1024
37LQEntries=32
38LSQCheckLoads=true
39LSQDepCheckShift=4
40RASSize=16
41SQEntries=32
42SSITSize=1024
43activity=0
44backComSize=5
45cachePorts=200
46checker=Null
47choiceCtrBits=2
48choicePredictorSize=8192
49clock=500
50commitToDecodeDelay=1
51commitToFetchDelay=1
52commitToIEWDelay=1
53commitToRenameDelay=1
54commitWidth=8
55cpu_id=0
56decodeToFetchDelay=1
57decodeToRenameDelay=1
58decodeWidth=8
59defer_registration=false
60dispatchWidth=8
61do_checkpoint_insts=true
62do_quiesce=true
63do_statistics_insts=true
64dtb=system.cpu0.dtb
65fetchToDecodeDelay=1
66fetchTrapLatency=1
67fetchWidth=8
68forwardComSize=5
69fuPool=system.cpu0.fuPool
70function_trace=false
71function_trace_start=0
72globalCtrBits=2
73globalHistoryBits=13
74globalPredictorSize=8192
75iewToCommitDelay=1
76iewToDecodeDelay=1
77iewToFetchDelay=1
78iewToRenameDelay=1
79instShiftAmt=2
80interrupts=system.cpu0.interrupts
81issueToExecuteDelay=1
82issueWidth=8
83itb=system.cpu0.itb
84localCtrBits=2
85localHistoryBits=11
86localHistoryTableSize=2048
87localPredictorSize=2048
88max_insts_all_threads=0
89max_insts_any_thread=0
90max_loads_all_threads=0
91max_loads_any_thread=0
92needsTSO=false
93numIQEntries=64
94numPhysFloatRegs=256
95numPhysIntRegs=256
96numROBEntries=192
97numRobs=1
98numThreads=1
99phase=0
100predType=tournament
101profile=0
102progress_interval=0
103renameToDecodeDelay=1
104renameToFetchDelay=1
105renameToIEWDelay=2
106renameToROBDelay=1
107renameWidth=8
108smtCommitPolicy=RoundRobin
109smtFetchPolicy=SingleThread
110smtIQPolicy=Partitioned
111smtIQThreshold=100
112smtLSQPolicy=Partitioned
113smtLSQThreshold=100
114smtNumFetchingThreads=1
115smtROBPolicy=Partitioned
116smtROBThreshold=100
117squashWidth=8
118store_set_clear_period=250000
119system=system
120tracer=system.cpu0.tracer
121trapLatency=13
122wbDepth=1
123wbWidth=8
124workload=system.cpu0.workload
125dcache_port=system.cpu0.dcache.cpu_side
126icache_port=system.cpu0.icache.cpu_side
127
128[system.cpu0.dcache]
129type=BaseCache
29
30[system.cpu0]
31type=DerivO3CPU
32children=dcache dtb fuPool icache interrupts itb tracer workload
33BTBEntries=4096
34BTBTagSize=16
35LFSTSize=1024
36LQEntries=32
37LSQCheckLoads=true
38LSQDepCheckShift=4
39RASSize=16
40SQEntries=32
41SSITSize=1024
42activity=0
43backComSize=5
44cachePorts=200
45checker=Null
46choiceCtrBits=2
47choicePredictorSize=8192
48clock=500
49commitToDecodeDelay=1
50commitToFetchDelay=1
51commitToIEWDelay=1
52commitToRenameDelay=1
53commitWidth=8
54cpu_id=0
55decodeToFetchDelay=1
56decodeToRenameDelay=1
57decodeWidth=8
58defer_registration=false
59dispatchWidth=8
60do_checkpoint_insts=true
61do_quiesce=true
62do_statistics_insts=true
63dtb=system.cpu0.dtb
64fetchToDecodeDelay=1
65fetchTrapLatency=1
66fetchWidth=8
67forwardComSize=5
68fuPool=system.cpu0.fuPool
69function_trace=false
70function_trace_start=0
71globalCtrBits=2
72globalHistoryBits=13
73globalPredictorSize=8192
74iewToCommitDelay=1
75iewToDecodeDelay=1
76iewToFetchDelay=1
77iewToRenameDelay=1
78instShiftAmt=2
79interrupts=system.cpu0.interrupts
80issueToExecuteDelay=1
81issueWidth=8
82itb=system.cpu0.itb
83localCtrBits=2
84localHistoryBits=11
85localHistoryTableSize=2048
86localPredictorSize=2048
87max_insts_all_threads=0
88max_insts_any_thread=0
89max_loads_all_threads=0
90max_loads_any_thread=0
91needsTSO=false
92numIQEntries=64
93numPhysFloatRegs=256
94numPhysIntRegs=256
95numROBEntries=192
96numRobs=1
97numThreads=1
98phase=0
99predType=tournament
100profile=0
101progress_interval=0
102renameToDecodeDelay=1
103renameToFetchDelay=1
104renameToIEWDelay=2
105renameToROBDelay=1
106renameWidth=8
107smtCommitPolicy=RoundRobin
108smtFetchPolicy=SingleThread
109smtIQPolicy=Partitioned
110smtIQThreshold=100
111smtLSQPolicy=Partitioned
112smtLSQThreshold=100
113smtNumFetchingThreads=1
114smtROBPolicy=Partitioned
115smtROBThreshold=100
116squashWidth=8
117store_set_clear_period=250000
118system=system
119tracer=system.cpu0.tracer
120trapLatency=13
121wbDepth=1
122wbWidth=8
123workload=system.cpu0.workload
124dcache_port=system.cpu0.dcache.cpu_side
125icache_port=system.cpu0.icache.cpu_side
126
127[system.cpu0.dcache]
128type=BaseCache
130addr_range=0:18446744073709551615
129addr_ranges=0:18446744073709551615
131assoc=4
132block_size=64
133forward_snoops=true
134hash_delay=1
135is_top_level=true
136latency=1000
137max_miss_count=0
138mshrs=4
139prefetch_on_access=false
140prefetcher=Null
141prioritizeRequests=false
142repl=Null
143size=32768
144subblock_size=0
145system=system
146tgts_per_mshr=20
147trace_addr=0
148two_queue=false
149write_buffers=8
150cpu_side=system.cpu0.dcache_port
130assoc=4
131block_size=64
132forward_snoops=true
133hash_delay=1
134is_top_level=true
135latency=1000
136max_miss_count=0
137mshrs=4
138prefetch_on_access=false
139prefetcher=Null
140prioritizeRequests=false
141repl=Null
142size=32768
143subblock_size=0
144system=system
145tgts_per_mshr=20
146trace_addr=0
147two_queue=false
148write_buffers=8
149cpu_side=system.cpu0.dcache_port
151mem_side=system.toL2Bus.port[2]
150mem_side=system.toL2Bus.slave[1]
152
153[system.cpu0.dtb]
154type=SparcTLB
155size=64
156
157[system.cpu0.fuPool]
158type=FUPool
159children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
160FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
161
162[system.cpu0.fuPool.FUList0]
163type=FUDesc
164children=opList
165count=6
166opList=system.cpu0.fuPool.FUList0.opList
167
168[system.cpu0.fuPool.FUList0.opList]
169type=OpDesc
170issueLat=1
171opClass=IntAlu
172opLat=1
173
174[system.cpu0.fuPool.FUList1]
175type=FUDesc
176children=opList0 opList1
177count=2
178opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
179
180[system.cpu0.fuPool.FUList1.opList0]
181type=OpDesc
182issueLat=1
183opClass=IntMult
184opLat=3
185
186[system.cpu0.fuPool.FUList1.opList1]
187type=OpDesc
188issueLat=19
189opClass=IntDiv
190opLat=20
191
192[system.cpu0.fuPool.FUList2]
193type=FUDesc
194children=opList0 opList1 opList2
195count=4
196opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
197
198[system.cpu0.fuPool.FUList2.opList0]
199type=OpDesc
200issueLat=1
201opClass=FloatAdd
202opLat=2
203
204[system.cpu0.fuPool.FUList2.opList1]
205type=OpDesc
206issueLat=1
207opClass=FloatCmp
208opLat=2
209
210[system.cpu0.fuPool.FUList2.opList2]
211type=OpDesc
212issueLat=1
213opClass=FloatCvt
214opLat=2
215
216[system.cpu0.fuPool.FUList3]
217type=FUDesc
218children=opList0 opList1 opList2
219count=2
220opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
221
222[system.cpu0.fuPool.FUList3.opList0]
223type=OpDesc
224issueLat=1
225opClass=FloatMult
226opLat=4
227
228[system.cpu0.fuPool.FUList3.opList1]
229type=OpDesc
230issueLat=12
231opClass=FloatDiv
232opLat=12
233
234[system.cpu0.fuPool.FUList3.opList2]
235type=OpDesc
236issueLat=24
237opClass=FloatSqrt
238opLat=24
239
240[system.cpu0.fuPool.FUList4]
241type=FUDesc
242children=opList
243count=0
244opList=system.cpu0.fuPool.FUList4.opList
245
246[system.cpu0.fuPool.FUList4.opList]
247type=OpDesc
248issueLat=1
249opClass=MemRead
250opLat=1
251
252[system.cpu0.fuPool.FUList5]
253type=FUDesc
254children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
255count=4
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257
258[system.cpu0.fuPool.FUList5.opList00]
259type=OpDesc
260issueLat=1
261opClass=SimdAdd
262opLat=1
263
264[system.cpu0.fuPool.FUList5.opList01]
265type=OpDesc
266issueLat=1
267opClass=SimdAddAcc
268opLat=1
269
270[system.cpu0.fuPool.FUList5.opList02]
271type=OpDesc
272issueLat=1
273opClass=SimdAlu
274opLat=1
275
276[system.cpu0.fuPool.FUList5.opList03]
277type=OpDesc
278issueLat=1
279opClass=SimdCmp
280opLat=1
281
282[system.cpu0.fuPool.FUList5.opList04]
283type=OpDesc
284issueLat=1
285opClass=SimdCvt
286opLat=1
287
288[system.cpu0.fuPool.FUList5.opList05]
289type=OpDesc
290issueLat=1
291opClass=SimdMisc
292opLat=1
293
294[system.cpu0.fuPool.FUList5.opList06]
295type=OpDesc
296issueLat=1
297opClass=SimdMult
298opLat=1
299
300[system.cpu0.fuPool.FUList5.opList07]
301type=OpDesc
302issueLat=1
303opClass=SimdMultAcc
304opLat=1
305
306[system.cpu0.fuPool.FUList5.opList08]
307type=OpDesc
308issueLat=1
309opClass=SimdShift
310opLat=1
311
312[system.cpu0.fuPool.FUList5.opList09]
313type=OpDesc
314issueLat=1
315opClass=SimdShiftAcc
316opLat=1
317
318[system.cpu0.fuPool.FUList5.opList10]
319type=OpDesc
320issueLat=1
321opClass=SimdSqrt
322opLat=1
323
324[system.cpu0.fuPool.FUList5.opList11]
325type=OpDesc
326issueLat=1
327opClass=SimdFloatAdd
328opLat=1
329
330[system.cpu0.fuPool.FUList5.opList12]
331type=OpDesc
332issueLat=1
333opClass=SimdFloatAlu
334opLat=1
335
336[system.cpu0.fuPool.FUList5.opList13]
337type=OpDesc
338issueLat=1
339opClass=SimdFloatCmp
340opLat=1
341
342[system.cpu0.fuPool.FUList5.opList14]
343type=OpDesc
344issueLat=1
345opClass=SimdFloatCvt
346opLat=1
347
348[system.cpu0.fuPool.FUList5.opList15]
349type=OpDesc
350issueLat=1
351opClass=SimdFloatDiv
352opLat=1
353
354[system.cpu0.fuPool.FUList5.opList16]
355type=OpDesc
356issueLat=1
357opClass=SimdFloatMisc
358opLat=1
359
360[system.cpu0.fuPool.FUList5.opList17]
361type=OpDesc
362issueLat=1
363opClass=SimdFloatMult
364opLat=1
365
366[system.cpu0.fuPool.FUList5.opList18]
367type=OpDesc
368issueLat=1
369opClass=SimdFloatMultAcc
370opLat=1
371
372[system.cpu0.fuPool.FUList5.opList19]
373type=OpDesc
374issueLat=1
375opClass=SimdFloatSqrt
376opLat=1
377
378[system.cpu0.fuPool.FUList6]
379type=FUDesc
380children=opList
381count=0
382opList=system.cpu0.fuPool.FUList6.opList
383
384[system.cpu0.fuPool.FUList6.opList]
385type=OpDesc
386issueLat=1
387opClass=MemWrite
388opLat=1
389
390[system.cpu0.fuPool.FUList7]
391type=FUDesc
392children=opList0 opList1
393count=4
394opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
395
396[system.cpu0.fuPool.FUList7.opList0]
397type=OpDesc
398issueLat=1
399opClass=MemRead
400opLat=1
401
402[system.cpu0.fuPool.FUList7.opList1]
403type=OpDesc
404issueLat=1
405opClass=MemWrite
406opLat=1
407
408[system.cpu0.fuPool.FUList8]
409type=FUDesc
410children=opList
411count=1
412opList=system.cpu0.fuPool.FUList8.opList
413
414[system.cpu0.fuPool.FUList8.opList]
415type=OpDesc
416issueLat=3
417opClass=IprAccess
418opLat=3
419
420[system.cpu0.icache]
421type=BaseCache
151
152[system.cpu0.dtb]
153type=SparcTLB
154size=64
155
156[system.cpu0.fuPool]
157type=FUPool
158children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
159FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
160
161[system.cpu0.fuPool.FUList0]
162type=FUDesc
163children=opList
164count=6
165opList=system.cpu0.fuPool.FUList0.opList
166
167[system.cpu0.fuPool.FUList0.opList]
168type=OpDesc
169issueLat=1
170opClass=IntAlu
171opLat=1
172
173[system.cpu0.fuPool.FUList1]
174type=FUDesc
175children=opList0 opList1
176count=2
177opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
178
179[system.cpu0.fuPool.FUList1.opList0]
180type=OpDesc
181issueLat=1
182opClass=IntMult
183opLat=3
184
185[system.cpu0.fuPool.FUList1.opList1]
186type=OpDesc
187issueLat=19
188opClass=IntDiv
189opLat=20
190
191[system.cpu0.fuPool.FUList2]
192type=FUDesc
193children=opList0 opList1 opList2
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196
197[system.cpu0.fuPool.FUList2.opList0]
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200opClass=FloatAdd
201opLat=2
202
203[system.cpu0.fuPool.FUList2.opList1]
204type=OpDesc
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208
209[system.cpu0.fuPool.FUList2.opList2]
210type=OpDesc
211issueLat=1
212opClass=FloatCvt
213opLat=2
214
215[system.cpu0.fuPool.FUList3]
216type=FUDesc
217children=opList0 opList1 opList2
218count=2
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220
221[system.cpu0.fuPool.FUList3.opList0]
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226
227[system.cpu0.fuPool.FUList3.opList1]
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232
233[system.cpu0.fuPool.FUList3.opList2]
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238
239[system.cpu0.fuPool.FUList4]
240type=FUDesc
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244
245[system.cpu0.fuPool.FUList4.opList]
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250
251[system.cpu0.fuPool.FUList5]
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253children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
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256
257[system.cpu0.fuPool.FUList5.opList00]
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263[system.cpu0.fuPool.FUList5.opList01]
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269[system.cpu0.fuPool.FUList5.opList02]
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281[system.cpu0.fuPool.FUList5.opList04]
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287[system.cpu0.fuPool.FUList5.opList05]
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293[system.cpu0.fuPool.FUList5.opList06]
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299[system.cpu0.fuPool.FUList5.opList07]
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305[system.cpu0.fuPool.FUList5.opList08]
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311[system.cpu0.fuPool.FUList5.opList09]
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317[system.cpu0.fuPool.FUList5.opList10]
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323[system.cpu0.fuPool.FUList5.opList11]
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329[system.cpu0.fuPool.FUList5.opList12]
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383[system.cpu0.fuPool.FUList6.opList]
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605[system.cpu1.fuPool.FUList0]
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665[system.cpu1.fuPool.FUList3.opList0]
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701[system.cpu1.fuPool.FUList5.opList00]
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725[system.cpu1.fuPool.FUList5.opList04]
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737[system.cpu1.fuPool.FUList5.opList06]
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767[system.cpu1.fuPool.FUList5.opList11]
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851[system.cpu1.fuPool.FUList8]
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857[system.cpu1.fuPool.FUList8.opList]
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863[system.cpu1.icache]
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595[system.cpu1.dtb]
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599[system.cpu1.fuPool]
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604[system.cpu1.fuPool.FUList0]
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610[system.cpu1.fuPool.FUList0.opList]
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616[system.cpu1.fuPool.FUList1]
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622[system.cpu1.fuPool.FUList1.opList0]
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628[system.cpu1.fuPool.FUList1.opList1]
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634[system.cpu1.fuPool.FUList2]
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640[system.cpu1.fuPool.FUList2.opList0]
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646[system.cpu1.fuPool.FUList2.opList1]
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652[system.cpu1.fuPool.FUList2.opList2]
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658[system.cpu1.fuPool.FUList3]
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663
664[system.cpu1.fuPool.FUList3.opList0]
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670[system.cpu1.fuPool.FUList3.opList1]
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676[system.cpu1.fuPool.FUList3.opList2]
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1263[system.cpu2.fuPool.FUList7.opList0]
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1265issueLat=1
1266opClass=MemRead
1267opLat=1
1268
1269[system.cpu2.fuPool.FUList7.opList1]
1270type=OpDesc
1271issueLat=1
1272opClass=MemWrite
1273opLat=1
1274
1275[system.cpu2.fuPool.FUList8]
1276type=FUDesc
1277children=opList
1278count=1
1279opList=system.cpu2.fuPool.FUList8.opList
1280
1281[system.cpu2.fuPool.FUList8.opList]
1282type=OpDesc
1283issueLat=3
1284opClass=IprAccess
1285opLat=3
1286
1287[system.cpu2.icache]
1288type=BaseCache
1018
1019[system.cpu2.dtb]
1020type=SparcTLB
1021size=64
1022
1023[system.cpu2.fuPool]
1024type=FUPool
1025children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
1026FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8
1027
1028[system.cpu2.fuPool.FUList0]
1029type=FUDesc
1030children=opList
1031count=6
1032opList=system.cpu2.fuPool.FUList0.opList
1033
1034[system.cpu2.fuPool.FUList0.opList]
1035type=OpDesc
1036issueLat=1
1037opClass=IntAlu
1038opLat=1
1039
1040[system.cpu2.fuPool.FUList1]
1041type=FUDesc
1042children=opList0 opList1
1043count=2
1044opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
1045
1046[system.cpu2.fuPool.FUList1.opList0]
1047type=OpDesc
1048issueLat=1
1049opClass=IntMult
1050opLat=3
1051
1052[system.cpu2.fuPool.FUList1.opList1]
1053type=OpDesc
1054issueLat=19
1055opClass=IntDiv
1056opLat=20
1057
1058[system.cpu2.fuPool.FUList2]
1059type=FUDesc
1060children=opList0 opList1 opList2
1061count=4
1062opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2
1063
1064[system.cpu2.fuPool.FUList2.opList0]
1065type=OpDesc
1066issueLat=1
1067opClass=FloatAdd
1068opLat=2
1069
1070[system.cpu2.fuPool.FUList2.opList1]
1071type=OpDesc
1072issueLat=1
1073opClass=FloatCmp
1074opLat=2
1075
1076[system.cpu2.fuPool.FUList2.opList2]
1077type=OpDesc
1078issueLat=1
1079opClass=FloatCvt
1080opLat=2
1081
1082[system.cpu2.fuPool.FUList3]
1083type=FUDesc
1084children=opList0 opList1 opList2
1085count=2
1086opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2
1087
1088[system.cpu2.fuPool.FUList3.opList0]
1089type=OpDesc
1090issueLat=1
1091opClass=FloatMult
1092opLat=4
1093
1094[system.cpu2.fuPool.FUList3.opList1]
1095type=OpDesc
1096issueLat=12
1097opClass=FloatDiv
1098opLat=12
1099
1100[system.cpu2.fuPool.FUList3.opList2]
1101type=OpDesc
1102issueLat=24
1103opClass=FloatSqrt
1104opLat=24
1105
1106[system.cpu2.fuPool.FUList4]
1107type=FUDesc
1108children=opList
1109count=0
1110opList=system.cpu2.fuPool.FUList4.opList
1111
1112[system.cpu2.fuPool.FUList4.opList]
1113type=OpDesc
1114issueLat=1
1115opClass=MemRead
1116opLat=1
1117
1118[system.cpu2.fuPool.FUList5]
1119type=FUDesc
1120children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
1121count=4
1122opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19
1123
1124[system.cpu2.fuPool.FUList5.opList00]
1125type=OpDesc
1126issueLat=1
1127opClass=SimdAdd
1128opLat=1
1129
1130[system.cpu2.fuPool.FUList5.opList01]
1131type=OpDesc
1132issueLat=1
1133opClass=SimdAddAcc
1134opLat=1
1135
1136[system.cpu2.fuPool.FUList5.opList02]
1137type=OpDesc
1138issueLat=1
1139opClass=SimdAlu
1140opLat=1
1141
1142[system.cpu2.fuPool.FUList5.opList03]
1143type=OpDesc
1144issueLat=1
1145opClass=SimdCmp
1146opLat=1
1147
1148[system.cpu2.fuPool.FUList5.opList04]
1149type=OpDesc
1150issueLat=1
1151opClass=SimdCvt
1152opLat=1
1153
1154[system.cpu2.fuPool.FUList5.opList05]
1155type=OpDesc
1156issueLat=1
1157opClass=SimdMisc
1158opLat=1
1159
1160[system.cpu2.fuPool.FUList5.opList06]
1161type=OpDesc
1162issueLat=1
1163opClass=SimdMult
1164opLat=1
1165
1166[system.cpu2.fuPool.FUList5.opList07]
1167type=OpDesc
1168issueLat=1
1169opClass=SimdMultAcc
1170opLat=1
1171
1172[system.cpu2.fuPool.FUList5.opList08]
1173type=OpDesc
1174issueLat=1
1175opClass=SimdShift
1176opLat=1
1177
1178[system.cpu2.fuPool.FUList5.opList09]
1179type=OpDesc
1180issueLat=1
1181opClass=SimdShiftAcc
1182opLat=1
1183
1184[system.cpu2.fuPool.FUList5.opList10]
1185type=OpDesc
1186issueLat=1
1187opClass=SimdSqrt
1188opLat=1
1189
1190[system.cpu2.fuPool.FUList5.opList11]
1191type=OpDesc
1192issueLat=1
1193opClass=SimdFloatAdd
1194opLat=1
1195
1196[system.cpu2.fuPool.FUList5.opList12]
1197type=OpDesc
1198issueLat=1
1199opClass=SimdFloatAlu
1200opLat=1
1201
1202[system.cpu2.fuPool.FUList5.opList13]
1203type=OpDesc
1204issueLat=1
1205opClass=SimdFloatCmp
1206opLat=1
1207
1208[system.cpu2.fuPool.FUList5.opList14]
1209type=OpDesc
1210issueLat=1
1211opClass=SimdFloatCvt
1212opLat=1
1213
1214[system.cpu2.fuPool.FUList5.opList15]
1215type=OpDesc
1216issueLat=1
1217opClass=SimdFloatDiv
1218opLat=1
1219
1220[system.cpu2.fuPool.FUList5.opList16]
1221type=OpDesc
1222issueLat=1
1223opClass=SimdFloatMisc
1224opLat=1
1225
1226[system.cpu2.fuPool.FUList5.opList17]
1227type=OpDesc
1228issueLat=1
1229opClass=SimdFloatMult
1230opLat=1
1231
1232[system.cpu2.fuPool.FUList5.opList18]
1233type=OpDesc
1234issueLat=1
1235opClass=SimdFloatMultAcc
1236opLat=1
1237
1238[system.cpu2.fuPool.FUList5.opList19]
1239type=OpDesc
1240issueLat=1
1241opClass=SimdFloatSqrt
1242opLat=1
1243
1244[system.cpu2.fuPool.FUList6]
1245type=FUDesc
1246children=opList
1247count=0
1248opList=system.cpu2.fuPool.FUList6.opList
1249
1250[system.cpu2.fuPool.FUList6.opList]
1251type=OpDesc
1252issueLat=1
1253opClass=MemWrite
1254opLat=1
1255
1256[system.cpu2.fuPool.FUList7]
1257type=FUDesc
1258children=opList0 opList1
1259count=4
1260opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
1261
1262[system.cpu2.fuPool.FUList7.opList0]
1263type=OpDesc
1264issueLat=1
1265opClass=MemRead
1266opLat=1
1267
1268[system.cpu2.fuPool.FUList7.opList1]
1269type=OpDesc
1270issueLat=1
1271opClass=MemWrite
1272opLat=1
1273
1274[system.cpu2.fuPool.FUList8]
1275type=FUDesc
1276children=opList
1277count=1
1278opList=system.cpu2.fuPool.FUList8.opList
1279
1280[system.cpu2.fuPool.FUList8.opList]
1281type=OpDesc
1282issueLat=3
1283opClass=IprAccess
1284opLat=3
1285
1286[system.cpu2.icache]
1287type=BaseCache
1289addr_range=0:18446744073709551615
1288addr_ranges=0:18446744073709551615
1290assoc=1
1291block_size=64
1292forward_snoops=true
1293hash_delay=1
1294is_top_level=true
1295latency=1000
1296max_miss_count=0
1297mshrs=4
1298prefetch_on_access=false
1299prefetcher=Null
1300prioritizeRequests=false
1301repl=Null
1302size=32768
1303subblock_size=0
1304system=system
1305tgts_per_mshr=20
1306trace_addr=0
1307two_queue=false
1308write_buffers=8
1309cpu_side=system.cpu2.icache_port
1289assoc=1
1290block_size=64
1291forward_snoops=true
1292hash_delay=1
1293is_top_level=true
1294latency=1000
1295max_miss_count=0
1296mshrs=4
1297prefetch_on_access=false
1298prefetcher=Null
1299prioritizeRequests=false
1300repl=Null
1301size=32768
1302subblock_size=0
1303system=system
1304tgts_per_mshr=20
1305trace_addr=0
1306two_queue=false
1307write_buffers=8
1308cpu_side=system.cpu2.icache_port
1310mem_side=system.toL2Bus.port[5]
1309mem_side=system.toL2Bus.slave[4]
1311
1312[system.cpu2.interrupts]
1313type=SparcInterrupts
1314
1315[system.cpu2.itb]
1316type=SparcTLB
1317size=64
1318
1319[system.cpu2.tracer]
1320type=ExeTracer
1321
1322[system.cpu3]
1323type=DerivO3CPU
1324children=dcache dtb fuPool icache interrupts itb tracer
1325BTBEntries=4096
1326BTBTagSize=16
1327LFSTSize=1024
1328LQEntries=32
1329LSQCheckLoads=true
1330LSQDepCheckShift=4
1331RASSize=16
1332SQEntries=32
1333SSITSize=1024
1334activity=0
1335backComSize=5
1336cachePorts=200
1337checker=Null
1338choiceCtrBits=2
1339choicePredictorSize=8192
1340clock=500
1341commitToDecodeDelay=1
1342commitToFetchDelay=1
1343commitToIEWDelay=1
1344commitToRenameDelay=1
1345commitWidth=8
1346cpu_id=3
1347decodeToFetchDelay=1
1348decodeToRenameDelay=1
1349decodeWidth=8
1350defer_registration=false
1351dispatchWidth=8
1352do_checkpoint_insts=true
1353do_quiesce=true
1354do_statistics_insts=true
1355dtb=system.cpu3.dtb
1356fetchToDecodeDelay=1
1357fetchTrapLatency=1
1358fetchWidth=8
1359forwardComSize=5
1360fuPool=system.cpu3.fuPool
1361function_trace=false
1362function_trace_start=0
1363globalCtrBits=2
1364globalHistoryBits=13
1365globalPredictorSize=8192
1366iewToCommitDelay=1
1367iewToDecodeDelay=1
1368iewToFetchDelay=1
1369iewToRenameDelay=1
1370instShiftAmt=2
1371interrupts=system.cpu3.interrupts
1372issueToExecuteDelay=1
1373issueWidth=8
1374itb=system.cpu3.itb
1375localCtrBits=2
1376localHistoryBits=11
1377localHistoryTableSize=2048
1378localPredictorSize=2048
1379max_insts_all_threads=0
1380max_insts_any_thread=0
1381max_loads_all_threads=0
1382max_loads_any_thread=0
1383needsTSO=false
1384numIQEntries=64
1385numPhysFloatRegs=256
1386numPhysIntRegs=256
1387numROBEntries=192
1388numRobs=1
1389numThreads=1
1390phase=0
1391predType=tournament
1392profile=0
1393progress_interval=0
1394renameToDecodeDelay=1
1395renameToFetchDelay=1
1396renameToIEWDelay=2
1397renameToROBDelay=1
1398renameWidth=8
1399smtCommitPolicy=RoundRobin
1400smtFetchPolicy=SingleThread
1401smtIQPolicy=Partitioned
1402smtIQThreshold=100
1403smtLSQPolicy=Partitioned
1404smtLSQThreshold=100
1405smtNumFetchingThreads=1
1406smtROBPolicy=Partitioned
1407smtROBThreshold=100
1408squashWidth=8
1409store_set_clear_period=250000
1410system=system
1411tracer=system.cpu3.tracer
1412trapLatency=13
1413wbDepth=1
1414wbWidth=8
1415workload=system.cpu0.workload
1416dcache_port=system.cpu3.dcache.cpu_side
1417icache_port=system.cpu3.icache.cpu_side
1418
1419[system.cpu3.dcache]
1420type=BaseCache
1310
1311[system.cpu2.interrupts]
1312type=SparcInterrupts
1313
1314[system.cpu2.itb]
1315type=SparcTLB
1316size=64
1317
1318[system.cpu2.tracer]
1319type=ExeTracer
1320
1321[system.cpu3]
1322type=DerivO3CPU
1323children=dcache dtb fuPool icache interrupts itb tracer
1324BTBEntries=4096
1325BTBTagSize=16
1326LFSTSize=1024
1327LQEntries=32
1328LSQCheckLoads=true
1329LSQDepCheckShift=4
1330RASSize=16
1331SQEntries=32
1332SSITSize=1024
1333activity=0
1334backComSize=5
1335cachePorts=200
1336checker=Null
1337choiceCtrBits=2
1338choicePredictorSize=8192
1339clock=500
1340commitToDecodeDelay=1
1341commitToFetchDelay=1
1342commitToIEWDelay=1
1343commitToRenameDelay=1
1344commitWidth=8
1345cpu_id=3
1346decodeToFetchDelay=1
1347decodeToRenameDelay=1
1348decodeWidth=8
1349defer_registration=false
1350dispatchWidth=8
1351do_checkpoint_insts=true
1352do_quiesce=true
1353do_statistics_insts=true
1354dtb=system.cpu3.dtb
1355fetchToDecodeDelay=1
1356fetchTrapLatency=1
1357fetchWidth=8
1358forwardComSize=5
1359fuPool=system.cpu3.fuPool
1360function_trace=false
1361function_trace_start=0
1362globalCtrBits=2
1363globalHistoryBits=13
1364globalPredictorSize=8192
1365iewToCommitDelay=1
1366iewToDecodeDelay=1
1367iewToFetchDelay=1
1368iewToRenameDelay=1
1369instShiftAmt=2
1370interrupts=system.cpu3.interrupts
1371issueToExecuteDelay=1
1372issueWidth=8
1373itb=system.cpu3.itb
1374localCtrBits=2
1375localHistoryBits=11
1376localHistoryTableSize=2048
1377localPredictorSize=2048
1378max_insts_all_threads=0
1379max_insts_any_thread=0
1380max_loads_all_threads=0
1381max_loads_any_thread=0
1382needsTSO=false
1383numIQEntries=64
1384numPhysFloatRegs=256
1385numPhysIntRegs=256
1386numROBEntries=192
1387numRobs=1
1388numThreads=1
1389phase=0
1390predType=tournament
1391profile=0
1392progress_interval=0
1393renameToDecodeDelay=1
1394renameToFetchDelay=1
1395renameToIEWDelay=2
1396renameToROBDelay=1
1397renameWidth=8
1398smtCommitPolicy=RoundRobin
1399smtFetchPolicy=SingleThread
1400smtIQPolicy=Partitioned
1401smtIQThreshold=100
1402smtLSQPolicy=Partitioned
1403smtLSQThreshold=100
1404smtNumFetchingThreads=1
1405smtROBPolicy=Partitioned
1406smtROBThreshold=100
1407squashWidth=8
1408store_set_clear_period=250000
1409system=system
1410tracer=system.cpu3.tracer
1411trapLatency=13
1412wbDepth=1
1413wbWidth=8
1414workload=system.cpu0.workload
1415dcache_port=system.cpu3.dcache.cpu_side
1416icache_port=system.cpu3.icache.cpu_side
1417
1418[system.cpu3.dcache]
1419type=BaseCache
1421addr_range=0:18446744073709551615
1420addr_ranges=0:18446744073709551615
1422assoc=4
1423block_size=64
1424forward_snoops=true
1425hash_delay=1
1426is_top_level=true
1427latency=1000
1428max_miss_count=0
1429mshrs=4
1430prefetch_on_access=false
1431prefetcher=Null
1432prioritizeRequests=false
1433repl=Null
1434size=32768
1435subblock_size=0
1436system=system
1437tgts_per_mshr=20
1438trace_addr=0
1439two_queue=false
1440write_buffers=8
1441cpu_side=system.cpu3.dcache_port
1421assoc=4
1422block_size=64
1423forward_snoops=true
1424hash_delay=1
1425is_top_level=true
1426latency=1000
1427max_miss_count=0
1428mshrs=4
1429prefetch_on_access=false
1430prefetcher=Null
1431prioritizeRequests=false
1432repl=Null
1433size=32768
1434subblock_size=0
1435system=system
1436tgts_per_mshr=20
1437trace_addr=0
1438two_queue=false
1439write_buffers=8
1440cpu_side=system.cpu3.dcache_port
1442mem_side=system.toL2Bus.port[8]
1441mem_side=system.toL2Bus.slave[7]
1443
1444[system.cpu3.dtb]
1445type=SparcTLB
1446size=64
1447
1448[system.cpu3.fuPool]
1449type=FUPool
1450children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
1451FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8
1452
1453[system.cpu3.fuPool.FUList0]
1454type=FUDesc
1455children=opList
1456count=6
1457opList=system.cpu3.fuPool.FUList0.opList
1458
1459[system.cpu3.fuPool.FUList0.opList]
1460type=OpDesc
1461issueLat=1
1462opClass=IntAlu
1463opLat=1
1464
1465[system.cpu3.fuPool.FUList1]
1466type=FUDesc
1467children=opList0 opList1
1468count=2
1469opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1
1470
1471[system.cpu3.fuPool.FUList1.opList0]
1472type=OpDesc
1473issueLat=1
1474opClass=IntMult
1475opLat=3
1476
1477[system.cpu3.fuPool.FUList1.opList1]
1478type=OpDesc
1479issueLat=19
1480opClass=IntDiv
1481opLat=20
1482
1483[system.cpu3.fuPool.FUList2]
1484type=FUDesc
1485children=opList0 opList1 opList2
1486count=4
1487opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2
1488
1489[system.cpu3.fuPool.FUList2.opList0]
1490type=OpDesc
1491issueLat=1
1492opClass=FloatAdd
1493opLat=2
1494
1495[system.cpu3.fuPool.FUList2.opList1]
1496type=OpDesc
1497issueLat=1
1498opClass=FloatCmp
1499opLat=2
1500
1501[system.cpu3.fuPool.FUList2.opList2]
1502type=OpDesc
1503issueLat=1
1504opClass=FloatCvt
1505opLat=2
1506
1507[system.cpu3.fuPool.FUList3]
1508type=FUDesc
1509children=opList0 opList1 opList2
1510count=2
1511opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2
1512
1513[system.cpu3.fuPool.FUList3.opList0]
1514type=OpDesc
1515issueLat=1
1516opClass=FloatMult
1517opLat=4
1518
1519[system.cpu3.fuPool.FUList3.opList1]
1520type=OpDesc
1521issueLat=12
1522opClass=FloatDiv
1523opLat=12
1524
1525[system.cpu3.fuPool.FUList3.opList2]
1526type=OpDesc
1527issueLat=24
1528opClass=FloatSqrt
1529opLat=24
1530
1531[system.cpu3.fuPool.FUList4]
1532type=FUDesc
1533children=opList
1534count=0
1535opList=system.cpu3.fuPool.FUList4.opList
1536
1537[system.cpu3.fuPool.FUList4.opList]
1538type=OpDesc
1539issueLat=1
1540opClass=MemRead
1541opLat=1
1542
1543[system.cpu3.fuPool.FUList5]
1544type=FUDesc
1545children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
1546count=4
1547opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19
1548
1549[system.cpu3.fuPool.FUList5.opList00]
1550type=OpDesc
1551issueLat=1
1552opClass=SimdAdd
1553opLat=1
1554
1555[system.cpu3.fuPool.FUList5.opList01]
1556type=OpDesc
1557issueLat=1
1558opClass=SimdAddAcc
1559opLat=1
1560
1561[system.cpu3.fuPool.FUList5.opList02]
1562type=OpDesc
1563issueLat=1
1564opClass=SimdAlu
1565opLat=1
1566
1567[system.cpu3.fuPool.FUList5.opList03]
1568type=OpDesc
1569issueLat=1
1570opClass=SimdCmp
1571opLat=1
1572
1573[system.cpu3.fuPool.FUList5.opList04]
1574type=OpDesc
1575issueLat=1
1576opClass=SimdCvt
1577opLat=1
1578
1579[system.cpu3.fuPool.FUList5.opList05]
1580type=OpDesc
1581issueLat=1
1582opClass=SimdMisc
1583opLat=1
1584
1585[system.cpu3.fuPool.FUList5.opList06]
1586type=OpDesc
1587issueLat=1
1588opClass=SimdMult
1589opLat=1
1590
1591[system.cpu3.fuPool.FUList5.opList07]
1592type=OpDesc
1593issueLat=1
1594opClass=SimdMultAcc
1595opLat=1
1596
1597[system.cpu3.fuPool.FUList5.opList08]
1598type=OpDesc
1599issueLat=1
1600opClass=SimdShift
1601opLat=1
1602
1603[system.cpu3.fuPool.FUList5.opList09]
1604type=OpDesc
1605issueLat=1
1606opClass=SimdShiftAcc
1607opLat=1
1608
1609[system.cpu3.fuPool.FUList5.opList10]
1610type=OpDesc
1611issueLat=1
1612opClass=SimdSqrt
1613opLat=1
1614
1615[system.cpu3.fuPool.FUList5.opList11]
1616type=OpDesc
1617issueLat=1
1618opClass=SimdFloatAdd
1619opLat=1
1620
1621[system.cpu3.fuPool.FUList5.opList12]
1622type=OpDesc
1623issueLat=1
1624opClass=SimdFloatAlu
1625opLat=1
1626
1627[system.cpu3.fuPool.FUList5.opList13]
1628type=OpDesc
1629issueLat=1
1630opClass=SimdFloatCmp
1631opLat=1
1632
1633[system.cpu3.fuPool.FUList5.opList14]
1634type=OpDesc
1635issueLat=1
1636opClass=SimdFloatCvt
1637opLat=1
1638
1639[system.cpu3.fuPool.FUList5.opList15]
1640type=OpDesc
1641issueLat=1
1642opClass=SimdFloatDiv
1643opLat=1
1644
1645[system.cpu3.fuPool.FUList5.opList16]
1646type=OpDesc
1647issueLat=1
1648opClass=SimdFloatMisc
1649opLat=1
1650
1651[system.cpu3.fuPool.FUList5.opList17]
1652type=OpDesc
1653issueLat=1
1654opClass=SimdFloatMult
1655opLat=1
1656
1657[system.cpu3.fuPool.FUList5.opList18]
1658type=OpDesc
1659issueLat=1
1660opClass=SimdFloatMultAcc
1661opLat=1
1662
1663[system.cpu3.fuPool.FUList5.opList19]
1664type=OpDesc
1665issueLat=1
1666opClass=SimdFloatSqrt
1667opLat=1
1668
1669[system.cpu3.fuPool.FUList6]
1670type=FUDesc
1671children=opList
1672count=0
1673opList=system.cpu3.fuPool.FUList6.opList
1674
1675[system.cpu3.fuPool.FUList6.opList]
1676type=OpDesc
1677issueLat=1
1678opClass=MemWrite
1679opLat=1
1680
1681[system.cpu3.fuPool.FUList7]
1682type=FUDesc
1683children=opList0 opList1
1684count=4
1685opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1
1686
1687[system.cpu3.fuPool.FUList7.opList0]
1688type=OpDesc
1689issueLat=1
1690opClass=MemRead
1691opLat=1
1692
1693[system.cpu3.fuPool.FUList7.opList1]
1694type=OpDesc
1695issueLat=1
1696opClass=MemWrite
1697opLat=1
1698
1699[system.cpu3.fuPool.FUList8]
1700type=FUDesc
1701children=opList
1702count=1
1703opList=system.cpu3.fuPool.FUList8.opList
1704
1705[system.cpu3.fuPool.FUList8.opList]
1706type=OpDesc
1707issueLat=3
1708opClass=IprAccess
1709opLat=3
1710
1711[system.cpu3.icache]
1712type=BaseCache
1442
1443[system.cpu3.dtb]
1444type=SparcTLB
1445size=64
1446
1447[system.cpu3.fuPool]
1448type=FUPool
1449children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
1450FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8
1451
1452[system.cpu3.fuPool.FUList0]
1453type=FUDesc
1454children=opList
1455count=6
1456opList=system.cpu3.fuPool.FUList0.opList
1457
1458[system.cpu3.fuPool.FUList0.opList]
1459type=OpDesc
1460issueLat=1
1461opClass=IntAlu
1462opLat=1
1463
1464[system.cpu3.fuPool.FUList1]
1465type=FUDesc
1466children=opList0 opList1
1467count=2
1468opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1
1469
1470[system.cpu3.fuPool.FUList1.opList0]
1471type=OpDesc
1472issueLat=1
1473opClass=IntMult
1474opLat=3
1475
1476[system.cpu3.fuPool.FUList1.opList1]
1477type=OpDesc
1478issueLat=19
1479opClass=IntDiv
1480opLat=20
1481
1482[system.cpu3.fuPool.FUList2]
1483type=FUDesc
1484children=opList0 opList1 opList2
1485count=4
1486opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2
1487
1488[system.cpu3.fuPool.FUList2.opList0]
1489type=OpDesc
1490issueLat=1
1491opClass=FloatAdd
1492opLat=2
1493
1494[system.cpu3.fuPool.FUList2.opList1]
1495type=OpDesc
1496issueLat=1
1497opClass=FloatCmp
1498opLat=2
1499
1500[system.cpu3.fuPool.FUList2.opList2]
1501type=OpDesc
1502issueLat=1
1503opClass=FloatCvt
1504opLat=2
1505
1506[system.cpu3.fuPool.FUList3]
1507type=FUDesc
1508children=opList0 opList1 opList2
1509count=2
1510opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2
1511
1512[system.cpu3.fuPool.FUList3.opList0]
1513type=OpDesc
1514issueLat=1
1515opClass=FloatMult
1516opLat=4
1517
1518[system.cpu3.fuPool.FUList3.opList1]
1519type=OpDesc
1520issueLat=12
1521opClass=FloatDiv
1522opLat=12
1523
1524[system.cpu3.fuPool.FUList3.opList2]
1525type=OpDesc
1526issueLat=24
1527opClass=FloatSqrt
1528opLat=24
1529
1530[system.cpu3.fuPool.FUList4]
1531type=FUDesc
1532children=opList
1533count=0
1534opList=system.cpu3.fuPool.FUList4.opList
1535
1536[system.cpu3.fuPool.FUList4.opList]
1537type=OpDesc
1538issueLat=1
1539opClass=MemRead
1540opLat=1
1541
1542[system.cpu3.fuPool.FUList5]
1543type=FUDesc
1544children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
1545count=4
1546opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19
1547
1548[system.cpu3.fuPool.FUList5.opList00]
1549type=OpDesc
1550issueLat=1
1551opClass=SimdAdd
1552opLat=1
1553
1554[system.cpu3.fuPool.FUList5.opList01]
1555type=OpDesc
1556issueLat=1
1557opClass=SimdAddAcc
1558opLat=1
1559
1560[system.cpu3.fuPool.FUList5.opList02]
1561type=OpDesc
1562issueLat=1
1563opClass=SimdAlu
1564opLat=1
1565
1566[system.cpu3.fuPool.FUList5.opList03]
1567type=OpDesc
1568issueLat=1
1569opClass=SimdCmp
1570opLat=1
1571
1572[system.cpu3.fuPool.FUList5.opList04]
1573type=OpDesc
1574issueLat=1
1575opClass=SimdCvt
1576opLat=1
1577
1578[system.cpu3.fuPool.FUList5.opList05]
1579type=OpDesc
1580issueLat=1
1581opClass=SimdMisc
1582opLat=1
1583
1584[system.cpu3.fuPool.FUList5.opList06]
1585type=OpDesc
1586issueLat=1
1587opClass=SimdMult
1588opLat=1
1589
1590[system.cpu3.fuPool.FUList5.opList07]
1591type=OpDesc
1592issueLat=1
1593opClass=SimdMultAcc
1594opLat=1
1595
1596[system.cpu3.fuPool.FUList5.opList08]
1597type=OpDesc
1598issueLat=1
1599opClass=SimdShift
1600opLat=1
1601
1602[system.cpu3.fuPool.FUList5.opList09]
1603type=OpDesc
1604issueLat=1
1605opClass=SimdShiftAcc
1606opLat=1
1607
1608[system.cpu3.fuPool.FUList5.opList10]
1609type=OpDesc
1610issueLat=1
1611opClass=SimdSqrt
1612opLat=1
1613
1614[system.cpu3.fuPool.FUList5.opList11]
1615type=OpDesc
1616issueLat=1
1617opClass=SimdFloatAdd
1618opLat=1
1619
1620[system.cpu3.fuPool.FUList5.opList12]
1621type=OpDesc
1622issueLat=1
1623opClass=SimdFloatAlu
1624opLat=1
1625
1626[system.cpu3.fuPool.FUList5.opList13]
1627type=OpDesc
1628issueLat=1
1629opClass=SimdFloatCmp
1630opLat=1
1631
1632[system.cpu3.fuPool.FUList5.opList14]
1633type=OpDesc
1634issueLat=1
1635opClass=SimdFloatCvt
1636opLat=1
1637
1638[system.cpu3.fuPool.FUList5.opList15]
1639type=OpDesc
1640issueLat=1
1641opClass=SimdFloatDiv
1642opLat=1
1643
1644[system.cpu3.fuPool.FUList5.opList16]
1645type=OpDesc
1646issueLat=1
1647opClass=SimdFloatMisc
1648opLat=1
1649
1650[system.cpu3.fuPool.FUList5.opList17]
1651type=OpDesc
1652issueLat=1
1653opClass=SimdFloatMult
1654opLat=1
1655
1656[system.cpu3.fuPool.FUList5.opList18]
1657type=OpDesc
1658issueLat=1
1659opClass=SimdFloatMultAcc
1660opLat=1
1661
1662[system.cpu3.fuPool.FUList5.opList19]
1663type=OpDesc
1664issueLat=1
1665opClass=SimdFloatSqrt
1666opLat=1
1667
1668[system.cpu3.fuPool.FUList6]
1669type=FUDesc
1670children=opList
1671count=0
1672opList=system.cpu3.fuPool.FUList6.opList
1673
1674[system.cpu3.fuPool.FUList6.opList]
1675type=OpDesc
1676issueLat=1
1677opClass=MemWrite
1678opLat=1
1679
1680[system.cpu3.fuPool.FUList7]
1681type=FUDesc
1682children=opList0 opList1
1683count=4
1684opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1
1685
1686[system.cpu3.fuPool.FUList7.opList0]
1687type=OpDesc
1688issueLat=1
1689opClass=MemRead
1690opLat=1
1691
1692[system.cpu3.fuPool.FUList7.opList1]
1693type=OpDesc
1694issueLat=1
1695opClass=MemWrite
1696opLat=1
1697
1698[system.cpu3.fuPool.FUList8]
1699type=FUDesc
1700children=opList
1701count=1
1702opList=system.cpu3.fuPool.FUList8.opList
1703
1704[system.cpu3.fuPool.FUList8.opList]
1705type=OpDesc
1706issueLat=3
1707opClass=IprAccess
1708opLat=3
1709
1710[system.cpu3.icache]
1711type=BaseCache
1713addr_range=0:18446744073709551615
1712addr_ranges=0:18446744073709551615
1714assoc=1
1715block_size=64
1716forward_snoops=true
1717hash_delay=1
1718is_top_level=true
1719latency=1000
1720max_miss_count=0
1721mshrs=4
1722prefetch_on_access=false
1723prefetcher=Null
1724prioritizeRequests=false
1725repl=Null
1726size=32768
1727subblock_size=0
1728system=system
1729tgts_per_mshr=20
1730trace_addr=0
1731two_queue=false
1732write_buffers=8
1733cpu_side=system.cpu3.icache_port
1713assoc=1
1714block_size=64
1715forward_snoops=true
1716hash_delay=1
1717is_top_level=true
1718latency=1000
1719max_miss_count=0
1720mshrs=4
1721prefetch_on_access=false
1722prefetcher=Null
1723prioritizeRequests=false
1724repl=Null
1725size=32768
1726subblock_size=0
1727system=system
1728tgts_per_mshr=20
1729trace_addr=0
1730two_queue=false
1731write_buffers=8
1732cpu_side=system.cpu3.icache_port
1734mem_side=system.toL2Bus.port[7]
1733mem_side=system.toL2Bus.slave[6]
1735
1736[system.cpu3.interrupts]
1737type=SparcInterrupts
1738
1739[system.cpu3.itb]
1740type=SparcTLB
1741size=64
1742
1743[system.cpu3.tracer]
1744type=ExeTracer
1745
1746[system.l2c]
1747type=BaseCache
1734
1735[system.cpu3.interrupts]
1736type=SparcInterrupts
1737
1738[system.cpu3.itb]
1739type=SparcTLB
1740size=64
1741
1742[system.cpu3.tracer]
1743type=ExeTracer
1744
1745[system.l2c]
1746type=BaseCache
1748addr_range=0:18446744073709551615
1747addr_ranges=0:18446744073709551615
1749assoc=8
1750block_size=64
1751forward_snoops=true
1752hash_delay=1
1753is_top_level=false
1754latency=10000
1755max_miss_count=0
1756mshrs=92
1757prefetch_on_access=false
1758prefetcher=Null
1759prioritizeRequests=false
1760repl=Null
1761size=4194304
1762subblock_size=0
1763system=system
1764tgts_per_mshr=16
1765trace_addr=0
1766two_queue=false
1767write_buffers=8
1748assoc=8
1749block_size=64
1750forward_snoops=true
1751hash_delay=1
1752is_top_level=false
1753latency=10000
1754max_miss_count=0
1755mshrs=92
1756prefetch_on_access=false
1757prefetcher=Null
1758prioritizeRequests=false
1759repl=Null
1760size=4194304
1761subblock_size=0
1762system=system
1763tgts_per_mshr=16
1764trace_addr=0
1765two_queue=false
1766write_buffers=8
1768cpu_side=system.toL2Bus.port[0]
1769mem_side=system.membus.port[0]
1767cpu_side=system.toL2Bus.master[0]
1768mem_side=system.membus.slave[0]
1770
1771[system.membus]
1772type=Bus
1773block_size=64
1774bus_id=0
1775clock=1000
1776header_cycles=1
1777use_default_range=false
1778width=64
1769
1770[system.membus]
1771type=Bus
1772block_size=64
1773bus_id=0
1774clock=1000
1775header_cycles=1
1776use_default_range=false
1777width=64
1779port=system.l2c.mem_side system.physmem.port[0] system.system_port
1778master=system.physmem.port[0]
1779slave=system.l2c.mem_side system.system_port
1780
1781[system.physmem]
1780
1781[system.physmem]
1782type=PhysicalMemory
1782type=SimpleMemory
1783conf_table_reported=false
1783file=
1784file=
1785in_addr_map=true
1784latency=30000
1785latency_var=0
1786null=false
1787range=0:134217727
1788zero=false
1786latency=30000
1787latency_var=0
1788null=false
1789range=0:134217727
1790zero=false
1789port=system.membus.port[1]
1791port=system.membus.master[0]
1790
1791[system.toL2Bus]
1792type=Bus
1793block_size=64
1794bus_id=0
1795clock=1000
1796header_cycles=1
1797use_default_range=false
1798width=64
1792
1793[system.toL2Bus]
1794type=Bus
1795block_size=64
1796bus_id=0
1797clock=1000
1798header_cycles=1
1799use_default_range=false
1800width=64
1799port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
1801master=system.l2c.cpu_side
1802slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
1800
1803