Cross Reference: /gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini

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config.ini (11731:c473ca7cc650)	config.ini (11956:9366df873131)
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51domain_id=-1 52eventq_index=0 53init_perf_level=0 54voltage_domain=system.voltage_domain 55 56[system.cpu0] 57type=DerivO3CPU 58children=branchPred dcache dtb fuPool icache interrupts isa itb tracer workload 59LFSTSize=1024 60LQEntries=32 61LSQCheckLoads=true 62LSQDepCheckShift=4 63SQEntries=32 64SSITSize=1024 65activity=0 66backComSize=5 67branchPred=system.cpu0.branchPred	1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51domain_id=-1 52eventq_index=0 53init_perf_level=0 54voltage_domain=system.voltage_domain 55 56[system.cpu0] 57type=DerivO3CPU 58children=branchPred dcache dtb fuPool icache interrupts isa itb tracer workload 59LFSTSize=1024 60LQEntries=32 61LSQCheckLoads=true 62LSQDepCheckShift=4 63SQEntries=32 64SSITSize=1024 65activity=0 66backComSize=5 67branchPred=system.cpu0.branchPred
68cachePorts=200	68cacheStorePorts=200
69checker=Null 70clk_domain=system.cpu_clk_domain 71commitToDecodeDelay=1 72commitToFetchDelay=1 73commitToIEWDelay=1 74commitToRenameDelay=1 75commitWidth=8 76cpu_id=0 77decodeToFetchDelay=1 78decodeToRenameDelay=1 79decodeWidth=8 80default_p_state=UNDEFINED 81dispatchWidth=8 82do_checkpoint_insts=true 83do_quiesce=true 84do_statistics_insts=true 85dtb=system.cpu0.dtb 86eventq_index=0 87fetchBufferSize=64 88fetchQueueSize=32 89fetchToDecodeDelay=1 90fetchTrapLatency=1 91fetchWidth=8 92forwardComSize=5 93fuPool=system.cpu0.fuPool 94function_trace=false 95function_trace_start=0 96iewToCommitDelay=1 97iewToDecodeDelay=1 98iewToFetchDelay=1 99iewToRenameDelay=1 100interrupts=system.cpu0.interrupts 101isa=system.cpu0.isa 102issueToExecuteDelay=1 103issueWidth=8 104itb=system.cpu0.itb 105max_insts_all_threads=0 106max_insts_any_thread=0 107max_loads_all_threads=0 108max_loads_any_thread=0 109needsTSO=false 110numIQEntries=64 111numPhysCCRegs=0 112numPhysFloatRegs=256 113numPhysIntRegs=256 114numROBEntries=192 115numRobs=1 116numThreads=1 117p_state_clk_gate_bins=20 118p_state_clk_gate_max=1000000000000 119p_state_clk_gate_min=1000 120power_model=Null 121profile=0 122progress_interval=0 123renameToDecodeDelay=1 124renameToFetchDelay=1 125renameToIEWDelay=2 126renameToROBDelay=1 127renameWidth=8 128simpoint_start_insts= 129smtCommitPolicy=RoundRobin 130smtFetchPolicy=SingleThread 131smtIQPolicy=Partitioned 132smtIQThreshold=100 133smtLSQPolicy=Partitioned 134smtLSQThreshold=100 135smtNumFetchingThreads=1 136smtROBPolicy=Partitioned 137smtROBThreshold=100 138socket_id=0 139squashWidth=8 140store_set_clear_period=250000 141switched_out=false	69checker=Null 70clk_domain=system.cpu_clk_domain 71commitToDecodeDelay=1 72commitToFetchDelay=1 73commitToIEWDelay=1 74commitToRenameDelay=1 75commitWidth=8 76cpu_id=0 77decodeToFetchDelay=1 78decodeToRenameDelay=1 79decodeWidth=8 80default_p_state=UNDEFINED 81dispatchWidth=8 82do_checkpoint_insts=true 83do_quiesce=true 84do_statistics_insts=true 85dtb=system.cpu0.dtb 86eventq_index=0 87fetchBufferSize=64 88fetchQueueSize=32 89fetchToDecodeDelay=1 90fetchTrapLatency=1 91fetchWidth=8 92forwardComSize=5 93fuPool=system.cpu0.fuPool 94function_trace=false 95function_trace_start=0 96iewToCommitDelay=1 97iewToDecodeDelay=1 98iewToFetchDelay=1 99iewToRenameDelay=1 100interrupts=system.cpu0.interrupts 101isa=system.cpu0.isa 102issueToExecuteDelay=1 103issueWidth=8 104itb=system.cpu0.itb 105max_insts_all_threads=0 106max_insts_any_thread=0 107max_loads_all_threads=0 108max_loads_any_thread=0 109needsTSO=false 110numIQEntries=64 111numPhysCCRegs=0 112numPhysFloatRegs=256 113numPhysIntRegs=256 114numROBEntries=192 115numRobs=1 116numThreads=1 117p_state_clk_gate_bins=20 118p_state_clk_gate_max=1000000000000 119p_state_clk_gate_min=1000 120power_model=Null 121profile=0 122progress_interval=0 123renameToDecodeDelay=1 124renameToFetchDelay=1 125renameToIEWDelay=2 126renameToROBDelay=1 127renameWidth=8 128simpoint_start_insts= 129smtCommitPolicy=RoundRobin 130smtFetchPolicy=SingleThread 131smtIQPolicy=Partitioned 132smtIQThreshold=100 133smtLSQPolicy=Partitioned 134smtLSQThreshold=100 135smtNumFetchingThreads=1 136smtROBPolicy=Partitioned 137smtROBThreshold=100 138socket_id=0 139squashWidth=8 140store_set_clear_period=250000 141switched_out=false
	142syscallRetryLatency=10000
142system=system 143tracer=system.cpu0.tracer 144trapLatency=13 145wbWidth=8 146workload=system.cpu0.workload 147dcache_port=system.cpu0.dcache.cpu_side 148icache_port=system.cpu0.icache.cpu_side 149 150[system.cpu0.branchPred] 151type=TournamentBP 152BTBEntries=4096 153BTBTagSize=16 154RASSize=16 155choiceCtrBits=2 156choicePredictorSize=8192 157eventq_index=0 158globalCtrBits=2 159globalPredictorSize=8192 160indirectHashGHR=true 161indirectHashTargets=true 162indirectPathLength=3 163indirectSets=256 164indirectTagSize=16 165indirectWays=2 166instShiftAmt=2 167localCtrBits=2 168localHistoryTableSize=2048 169localPredictorSize=2048 170numThreads=1 171useIndirect=true 172 173[system.cpu0.dcache] 174type=Cache 175children=tags 176addr_ranges=0:18446744073709551615:0:0:0:0 177assoc=4 178clk_domain=system.cpu_clk_domain 179clusivity=mostly_incl 180data_latency=2 181default_p_state=UNDEFINED 182demand_mshr_reserve=1 183eventq_index=0 184is_read_only=false 185max_miss_count=0 186mshrs=4 187p_state_clk_gate_bins=20 188p_state_clk_gate_max=1000000000000 189p_state_clk_gate_min=1000 190power_model=Null 191prefetch_on_access=false 192prefetcher=Null 193response_latency=2 194sequential_access=false 195size=32768 196system=system 197tag_latency=2 198tags=system.cpu0.dcache.tags 199tgts_per_mshr=20 200write_buffers=8 201writeback_clean=false 202cpu_side=system.cpu0.dcache_port 203mem_side=system.toL2Bus.slave[1] 204 205[system.cpu0.dcache.tags] 206type=LRU 207assoc=4 208block_size=64 209clk_domain=system.cpu_clk_domain 210data_latency=2 211default_p_state=UNDEFINED 212eventq_index=0 213p_state_clk_gate_bins=20 214p_state_clk_gate_max=1000000000000 215p_state_clk_gate_min=1000 216power_model=Null 217sequential_access=false 218size=32768 219tag_latency=2 220 221[system.cpu0.dtb] 222type=SparcTLB 223eventq_index=0 224size=64 225 226[system.cpu0.fuPool] 227type=FUPool 228children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 229FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 230eventq_index=0 231 232[system.cpu0.fuPool.FUList0] 233type=FUDesc 234children=opList 235count=6 236eventq_index=0 237opList=system.cpu0.fuPool.FUList0.opList 238 239[system.cpu0.fuPool.FUList0.opList] 240type=OpDesc 241eventq_index=0 242opClass=IntAlu 243opLat=1 244pipelined=true 245 246[system.cpu0.fuPool.FUList1] 247type=FUDesc 248children=opList0 opList1 249count=2 250eventq_index=0 251opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 252 253[system.cpu0.fuPool.FUList1.opList0] 254type=OpDesc 255eventq_index=0 256opClass=IntMult 257opLat=3 258pipelined=true 259 260[system.cpu0.fuPool.FUList1.opList1] 261type=OpDesc 262eventq_index=0 263opClass=IntDiv 264opLat=20 265pipelined=false 266 267[system.cpu0.fuPool.FUList2] 268type=FUDesc 269children=opList0 opList1 opList2 270count=4 271eventq_index=0 272opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 273 274[system.cpu0.fuPool.FUList2.opList0] 275type=OpDesc 276eventq_index=0 277opClass=FloatAdd 278opLat=2 279pipelined=true 280 281[system.cpu0.fuPool.FUList2.opList1] 282type=OpDesc 283eventq_index=0 284opClass=FloatCmp 285opLat=2 286pipelined=true 287 288[system.cpu0.fuPool.FUList2.opList2] 289type=OpDesc 290eventq_index=0 291opClass=FloatCvt 292opLat=2 293pipelined=true 294 295[system.cpu0.fuPool.FUList3] 296type=FUDesc 297children=opList0 opList1 opList2 opList3 opList4 298count=2 299eventq_index=0 300opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 system.cpu0.fuPool.FUList3.opList3 system.cpu0.fuPool.FUList3.opList4 301 302[system.cpu0.fuPool.FUList3.opList0] 303type=OpDesc 304eventq_index=0 305opClass=FloatMult 306opLat=4 307pipelined=true 308 309[system.cpu0.fuPool.FUList3.opList1] 310type=OpDesc 311eventq_index=0 312opClass=FloatMultAcc 313opLat=5 314pipelined=true 315 316[system.cpu0.fuPool.FUList3.opList2] 317type=OpDesc 318eventq_index=0 319opClass=FloatMisc 320opLat=3 321pipelined=true 322 323[system.cpu0.fuPool.FUList3.opList3] 324type=OpDesc 325eventq_index=0 326opClass=FloatDiv 327opLat=12 328pipelined=false 329 330[system.cpu0.fuPool.FUList3.opList4] 331type=OpDesc 332eventq_index=0 333opClass=FloatSqrt 334opLat=24 335pipelined=false 336 337[system.cpu0.fuPool.FUList4] 338type=FUDesc 339children=opList0 opList1 340count=0 341eventq_index=0 342opList=system.cpu0.fuPool.FUList4.opList0 system.cpu0.fuPool.FUList4.opList1 343 344[system.cpu0.fuPool.FUList4.opList0] 345type=OpDesc 346eventq_index=0 347opClass=MemRead 348opLat=1 349pipelined=true 350 351[system.cpu0.fuPool.FUList4.opList1] 352type=OpDesc 353eventq_index=0 354opClass=FloatMemRead 355opLat=1 356pipelined=true 357 358[system.cpu0.fuPool.FUList5] 359type=FUDesc 360children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 361count=4 362eventq_index=0 363opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 364 365[system.cpu0.fuPool.FUList5.opList00] 366type=OpDesc 367eventq_index=0 368opClass=SimdAdd 369opLat=1 370pipelined=true 371 372[system.cpu0.fuPool.FUList5.opList01] 373type=OpDesc 374eventq_index=0 375opClass=SimdAddAcc 376opLat=1 377pipelined=true 378 379[system.cpu0.fuPool.FUList5.opList02] 380type=OpDesc 381eventq_index=0 382opClass=SimdAlu 383opLat=1 384pipelined=true 385 386[system.cpu0.fuPool.FUList5.opList03] 387type=OpDesc 388eventq_index=0 389opClass=SimdCmp 390opLat=1 391pipelined=true 392 393[system.cpu0.fuPool.FUList5.opList04] 394type=OpDesc 395eventq_index=0 396opClass=SimdCvt 397opLat=1 398pipelined=true 399 400[system.cpu0.fuPool.FUList5.opList05] 401type=OpDesc 402eventq_index=0 403opClass=SimdMisc 404opLat=1 405pipelined=true 406 407[system.cpu0.fuPool.FUList5.opList06] 408type=OpDesc 409eventq_index=0 410opClass=SimdMult 411opLat=1 412pipelined=true 413 414[system.cpu0.fuPool.FUList5.opList07] 415type=OpDesc 416eventq_index=0 417opClass=SimdMultAcc 418opLat=1 419pipelined=true 420 421[system.cpu0.fuPool.FUList5.opList08] 422type=OpDesc 423eventq_index=0 424opClass=SimdShift 425opLat=1 426pipelined=true 427 428[system.cpu0.fuPool.FUList5.opList09] 429type=OpDesc 430eventq_index=0 431opClass=SimdShiftAcc 432opLat=1 433pipelined=true 434 435[system.cpu0.fuPool.FUList5.opList10] 436type=OpDesc 437eventq_index=0 438opClass=SimdSqrt 439opLat=1 440pipelined=true 441 442[system.cpu0.fuPool.FUList5.opList11] 443type=OpDesc 444eventq_index=0 445opClass=SimdFloatAdd 446opLat=1 447pipelined=true 448 449[system.cpu0.fuPool.FUList5.opList12] 450type=OpDesc 451eventq_index=0 452opClass=SimdFloatAlu 453opLat=1 454pipelined=true 455 456[system.cpu0.fuPool.FUList5.opList13] 457type=OpDesc 458eventq_index=0 459opClass=SimdFloatCmp 460opLat=1 461pipelined=true 462 463[system.cpu0.fuPool.FUList5.opList14] 464type=OpDesc 465eventq_index=0 466opClass=SimdFloatCvt 467opLat=1 468pipelined=true 469 470[system.cpu0.fuPool.FUList5.opList15] 471type=OpDesc 472eventq_index=0 473opClass=SimdFloatDiv 474opLat=1 475pipelined=true 476 477[system.cpu0.fuPool.FUList5.opList16] 478type=OpDesc 479eventq_index=0 480opClass=SimdFloatMisc 481opLat=1 482pipelined=true 483 484[system.cpu0.fuPool.FUList5.opList17] 485type=OpDesc 486eventq_index=0 487opClass=SimdFloatMult 488opLat=1 489pipelined=true 490 491[system.cpu0.fuPool.FUList5.opList18] 492type=OpDesc 493eventq_index=0 494opClass=SimdFloatMultAcc 495opLat=1 496pipelined=true 497 498[system.cpu0.fuPool.FUList5.opList19] 499type=OpDesc 500eventq_index=0 501opClass=SimdFloatSqrt 502opLat=1 503pipelined=true 504 505[system.cpu0.fuPool.FUList6] 506type=FUDesc 507children=opList0 opList1 508count=0 509eventq_index=0 510opList=system.cpu0.fuPool.FUList6.opList0 system.cpu0.fuPool.FUList6.opList1 511 512[system.cpu0.fuPool.FUList6.opList0] 513type=OpDesc 514eventq_index=0 515opClass=MemWrite 516opLat=1 517pipelined=true 518 519[system.cpu0.fuPool.FUList6.opList1] 520type=OpDesc 521eventq_index=0 522opClass=FloatMemWrite 523opLat=1 524pipelined=true 525 526[system.cpu0.fuPool.FUList7] 527type=FUDesc 528children=opList0 opList1 opList2 opList3 529count=4 530eventq_index=0 531opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 system.cpu0.fuPool.FUList7.opList2 system.cpu0.fuPool.FUList7.opList3 532 533[system.cpu0.fuPool.FUList7.opList0] 534type=OpDesc 535eventq_index=0 536opClass=MemRead 537opLat=1 538pipelined=true 539 540[system.cpu0.fuPool.FUList7.opList1] 541type=OpDesc 542eventq_index=0 543opClass=MemWrite 544opLat=1 545pipelined=true 546 547[system.cpu0.fuPool.FUList7.opList2] 548type=OpDesc 549eventq_index=0 550opClass=FloatMemRead 551opLat=1 552pipelined=true 553 554[system.cpu0.fuPool.FUList7.opList3] 555type=OpDesc 556eventq_index=0 557opClass=FloatMemWrite 558opLat=1 559pipelined=true 560 561[system.cpu0.fuPool.FUList8] 562type=FUDesc 563children=opList 564count=1 565eventq_index=0 566opList=system.cpu0.fuPool.FUList8.opList 567 568[system.cpu0.fuPool.FUList8.opList] 569type=OpDesc 570eventq_index=0 571opClass=IprAccess 572opLat=3 573pipelined=false 574 575[system.cpu0.icache] 576type=Cache 577children=tags 578addr_ranges=0:18446744073709551615:0:0:0:0 579assoc=1 580clk_domain=system.cpu_clk_domain 581clusivity=mostly_incl 582data_latency=2 583default_p_state=UNDEFINED 584demand_mshr_reserve=1 585eventq_index=0 586is_read_only=true 587max_miss_count=0 588mshrs=4 589p_state_clk_gate_bins=20 590p_state_clk_gate_max=1000000000000 591p_state_clk_gate_min=1000 592power_model=Null 593prefetch_on_access=false 594prefetcher=Null 595response_latency=2 596sequential_access=false 597size=32768 598system=system 599tag_latency=2 600tags=system.cpu0.icache.tags 601tgts_per_mshr=20 602write_buffers=8 603writeback_clean=true 604cpu_side=system.cpu0.icache_port 605mem_side=system.toL2Bus.slave[0] 606 607[system.cpu0.icache.tags] 608type=LRU 609assoc=1 610block_size=64 611clk_domain=system.cpu_clk_domain 612data_latency=2 613default_p_state=UNDEFINED 614eventq_index=0 615p_state_clk_gate_bins=20 616p_state_clk_gate_max=1000000000000 617p_state_clk_gate_min=1000 618power_model=Null 619sequential_access=false 620size=32768 621tag_latency=2 622 623[system.cpu0.interrupts] 624type=SparcInterrupts 625eventq_index=0 626 627[system.cpu0.isa] 628type=SparcISA 629eventq_index=0 630 631[system.cpu0.itb] 632type=SparcTLB 633eventq_index=0 634size=64 635 636[system.cpu0.tracer] 637type=ExeTracer 638eventq_index=0 639 640[system.cpu0.workload]	143system=system 144tracer=system.cpu0.tracer 145trapLatency=13 146wbWidth=8 147workload=system.cpu0.workload 148dcache_port=system.cpu0.dcache.cpu_side 149icache_port=system.cpu0.icache.cpu_side 150 151[system.cpu0.branchPred] 152type=TournamentBP 153BTBEntries=4096 154BTBTagSize=16 155RASSize=16 156choiceCtrBits=2 157choicePredictorSize=8192 158eventq_index=0 159globalCtrBits=2 160globalPredictorSize=8192 161indirectHashGHR=true 162indirectHashTargets=true 163indirectPathLength=3 164indirectSets=256 165indirectTagSize=16 166indirectWays=2 167instShiftAmt=2 168localCtrBits=2 169localHistoryTableSize=2048 170localPredictorSize=2048 171numThreads=1 172useIndirect=true 173 174[system.cpu0.dcache] 175type=Cache 176children=tags 177addr_ranges=0:18446744073709551615:0:0:0:0 178assoc=4 179clk_domain=system.cpu_clk_domain 180clusivity=mostly_incl 181data_latency=2 182default_p_state=UNDEFINED 183demand_mshr_reserve=1 184eventq_index=0 185is_read_only=false 186max_miss_count=0 187mshrs=4 188p_state_clk_gate_bins=20 189p_state_clk_gate_max=1000000000000 190p_state_clk_gate_min=1000 191power_model=Null 192prefetch_on_access=false 193prefetcher=Null 194response_latency=2 195sequential_access=false 196size=32768 197system=system 198tag_latency=2 199tags=system.cpu0.dcache.tags 200tgts_per_mshr=20 201write_buffers=8 202writeback_clean=false 203cpu_side=system.cpu0.dcache_port 204mem_side=system.toL2Bus.slave[1] 205 206[system.cpu0.dcache.tags] 207type=LRU 208assoc=4 209block_size=64 210clk_domain=system.cpu_clk_domain 211data_latency=2 212default_p_state=UNDEFINED 213eventq_index=0 214p_state_clk_gate_bins=20 215p_state_clk_gate_max=1000000000000 216p_state_clk_gate_min=1000 217power_model=Null 218sequential_access=false 219size=32768 220tag_latency=2 221 222[system.cpu0.dtb] 223type=SparcTLB 224eventq_index=0 225size=64 226 227[system.cpu0.fuPool] 228type=FUPool 229children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 230FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 231eventq_index=0 232 233[system.cpu0.fuPool.FUList0] 234type=FUDesc 235children=opList 236count=6 237eventq_index=0 238opList=system.cpu0.fuPool.FUList0.opList 239 240[system.cpu0.fuPool.FUList0.opList] 241type=OpDesc 242eventq_index=0 243opClass=IntAlu 244opLat=1 245pipelined=true 246 247[system.cpu0.fuPool.FUList1] 248type=FUDesc 249children=opList0 opList1 250count=2 251eventq_index=0 252opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 253 254[system.cpu0.fuPool.FUList1.opList0] 255type=OpDesc 256eventq_index=0 257opClass=IntMult 258opLat=3 259pipelined=true 260 261[system.cpu0.fuPool.FUList1.opList1] 262type=OpDesc 263eventq_index=0 264opClass=IntDiv 265opLat=20 266pipelined=false 267 268[system.cpu0.fuPool.FUList2] 269type=FUDesc 270children=opList0 opList1 opList2 271count=4 272eventq_index=0 273opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 274 275[system.cpu0.fuPool.FUList2.opList0] 276type=OpDesc 277eventq_index=0 278opClass=FloatAdd 279opLat=2 280pipelined=true 281 282[system.cpu0.fuPool.FUList2.opList1] 283type=OpDesc 284eventq_index=0 285opClass=FloatCmp 286opLat=2 287pipelined=true 288 289[system.cpu0.fuPool.FUList2.opList2] 290type=OpDesc 291eventq_index=0 292opClass=FloatCvt 293opLat=2 294pipelined=true 295 296[system.cpu0.fuPool.FUList3] 297type=FUDesc 298children=opList0 opList1 opList2 opList3 opList4 299count=2 300eventq_index=0 301opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 system.cpu0.fuPool.FUList3.opList3 system.cpu0.fuPool.FUList3.opList4 302 303[system.cpu0.fuPool.FUList3.opList0] 304type=OpDesc 305eventq_index=0 306opClass=FloatMult 307opLat=4 308pipelined=true 309 310[system.cpu0.fuPool.FUList3.opList1] 311type=OpDesc 312eventq_index=0 313opClass=FloatMultAcc 314opLat=5 315pipelined=true 316 317[system.cpu0.fuPool.FUList3.opList2] 318type=OpDesc 319eventq_index=0 320opClass=FloatMisc 321opLat=3 322pipelined=true 323 324[system.cpu0.fuPool.FUList3.opList3] 325type=OpDesc 326eventq_index=0 327opClass=FloatDiv 328opLat=12 329pipelined=false 330 331[system.cpu0.fuPool.FUList3.opList4] 332type=OpDesc 333eventq_index=0 334opClass=FloatSqrt 335opLat=24 336pipelined=false 337 338[system.cpu0.fuPool.FUList4] 339type=FUDesc 340children=opList0 opList1 341count=0 342eventq_index=0 343opList=system.cpu0.fuPool.FUList4.opList0 system.cpu0.fuPool.FUList4.opList1 344 345[system.cpu0.fuPool.FUList4.opList0] 346type=OpDesc 347eventq_index=0 348opClass=MemRead 349opLat=1 350pipelined=true 351 352[system.cpu0.fuPool.FUList4.opList1] 353type=OpDesc 354eventq_index=0 355opClass=FloatMemRead 356opLat=1 357pipelined=true 358 359[system.cpu0.fuPool.FUList5] 360type=FUDesc 361children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 362count=4 363eventq_index=0 364opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 365 366[system.cpu0.fuPool.FUList5.opList00] 367type=OpDesc 368eventq_index=0 369opClass=SimdAdd 370opLat=1 371pipelined=true 372 373[system.cpu0.fuPool.FUList5.opList01] 374type=OpDesc 375eventq_index=0 376opClass=SimdAddAcc 377opLat=1 378pipelined=true 379 380[system.cpu0.fuPool.FUList5.opList02] 381type=OpDesc 382eventq_index=0 383opClass=SimdAlu 384opLat=1 385pipelined=true 386 387[system.cpu0.fuPool.FUList5.opList03] 388type=OpDesc 389eventq_index=0 390opClass=SimdCmp 391opLat=1 392pipelined=true 393 394[system.cpu0.fuPool.FUList5.opList04] 395type=OpDesc 396eventq_index=0 397opClass=SimdCvt 398opLat=1 399pipelined=true 400 401[system.cpu0.fuPool.FUList5.opList05] 402type=OpDesc 403eventq_index=0 404opClass=SimdMisc 405opLat=1 406pipelined=true 407 408[system.cpu0.fuPool.FUList5.opList06] 409type=OpDesc 410eventq_index=0 411opClass=SimdMult 412opLat=1 413pipelined=true 414 415[system.cpu0.fuPool.FUList5.opList07] 416type=OpDesc 417eventq_index=0 418opClass=SimdMultAcc 419opLat=1 420pipelined=true 421 422[system.cpu0.fuPool.FUList5.opList08] 423type=OpDesc 424eventq_index=0 425opClass=SimdShift 426opLat=1 427pipelined=true 428 429[system.cpu0.fuPool.FUList5.opList09] 430type=OpDesc 431eventq_index=0 432opClass=SimdShiftAcc 433opLat=1 434pipelined=true 435 436[system.cpu0.fuPool.FUList5.opList10] 437type=OpDesc 438eventq_index=0 439opClass=SimdSqrt 440opLat=1 441pipelined=true 442 443[system.cpu0.fuPool.FUList5.opList11] 444type=OpDesc 445eventq_index=0 446opClass=SimdFloatAdd 447opLat=1 448pipelined=true 449 450[system.cpu0.fuPool.FUList5.opList12] 451type=OpDesc 452eventq_index=0 453opClass=SimdFloatAlu 454opLat=1 455pipelined=true 456 457[system.cpu0.fuPool.FUList5.opList13] 458type=OpDesc 459eventq_index=0 460opClass=SimdFloatCmp 461opLat=1 462pipelined=true 463 464[system.cpu0.fuPool.FUList5.opList14] 465type=OpDesc 466eventq_index=0 467opClass=SimdFloatCvt 468opLat=1 469pipelined=true 470 471[system.cpu0.fuPool.FUList5.opList15] 472type=OpDesc 473eventq_index=0 474opClass=SimdFloatDiv 475opLat=1 476pipelined=true 477 478[system.cpu0.fuPool.FUList5.opList16] 479type=OpDesc 480eventq_index=0 481opClass=SimdFloatMisc 482opLat=1 483pipelined=true 484 485[system.cpu0.fuPool.FUList5.opList17] 486type=OpDesc 487eventq_index=0 488opClass=SimdFloatMult 489opLat=1 490pipelined=true 491 492[system.cpu0.fuPool.FUList5.opList18] 493type=OpDesc 494eventq_index=0 495opClass=SimdFloatMultAcc 496opLat=1 497pipelined=true 498 499[system.cpu0.fuPool.FUList5.opList19] 500type=OpDesc 501eventq_index=0 502opClass=SimdFloatSqrt 503opLat=1 504pipelined=true 505 506[system.cpu0.fuPool.FUList6] 507type=FUDesc 508children=opList0 opList1 509count=0 510eventq_index=0 511opList=system.cpu0.fuPool.FUList6.opList0 system.cpu0.fuPool.FUList6.opList1 512 513[system.cpu0.fuPool.FUList6.opList0] 514type=OpDesc 515eventq_index=0 516opClass=MemWrite 517opLat=1 518pipelined=true 519 520[system.cpu0.fuPool.FUList6.opList1] 521type=OpDesc 522eventq_index=0 523opClass=FloatMemWrite 524opLat=1 525pipelined=true 526 527[system.cpu0.fuPool.FUList7] 528type=FUDesc 529children=opList0 opList1 opList2 opList3 530count=4 531eventq_index=0 532opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 system.cpu0.fuPool.FUList7.opList2 system.cpu0.fuPool.FUList7.opList3 533 534[system.cpu0.fuPool.FUList7.opList0] 535type=OpDesc 536eventq_index=0 537opClass=MemRead 538opLat=1 539pipelined=true 540 541[system.cpu0.fuPool.FUList7.opList1] 542type=OpDesc 543eventq_index=0 544opClass=MemWrite 545opLat=1 546pipelined=true 547 548[system.cpu0.fuPool.FUList7.opList2] 549type=OpDesc 550eventq_index=0 551opClass=FloatMemRead 552opLat=1 553pipelined=true 554 555[system.cpu0.fuPool.FUList7.opList3] 556type=OpDesc 557eventq_index=0 558opClass=FloatMemWrite 559opLat=1 560pipelined=true 561 562[system.cpu0.fuPool.FUList8] 563type=FUDesc 564children=opList 565count=1 566eventq_index=0 567opList=system.cpu0.fuPool.FUList8.opList 568 569[system.cpu0.fuPool.FUList8.opList] 570type=OpDesc 571eventq_index=0 572opClass=IprAccess 573opLat=3 574pipelined=false 575 576[system.cpu0.icache] 577type=Cache 578children=tags 579addr_ranges=0:18446744073709551615:0:0:0:0 580assoc=1 581clk_domain=system.cpu_clk_domain 582clusivity=mostly_incl 583data_latency=2 584default_p_state=UNDEFINED 585demand_mshr_reserve=1 586eventq_index=0 587is_read_only=true 588max_miss_count=0 589mshrs=4 590p_state_clk_gate_bins=20 591p_state_clk_gate_max=1000000000000 592p_state_clk_gate_min=1000 593power_model=Null 594prefetch_on_access=false 595prefetcher=Null 596response_latency=2 597sequential_access=false 598size=32768 599system=system 600tag_latency=2 601tags=system.cpu0.icache.tags 602tgts_per_mshr=20 603write_buffers=8 604writeback_clean=true 605cpu_side=system.cpu0.icache_port 606mem_side=system.toL2Bus.slave[0] 607 608[system.cpu0.icache.tags] 609type=LRU 610assoc=1 611block_size=64 612clk_domain=system.cpu_clk_domain 613data_latency=2 614default_p_state=UNDEFINED 615eventq_index=0 616p_state_clk_gate_bins=20 617p_state_clk_gate_max=1000000000000 618p_state_clk_gate_min=1000 619power_model=Null 620sequential_access=false 621size=32768 622tag_latency=2 623 624[system.cpu0.interrupts] 625type=SparcInterrupts 626eventq_index=0 627 628[system.cpu0.isa] 629type=SparcISA 630eventq_index=0 631 632[system.cpu0.itb] 633type=SparcTLB 634eventq_index=0 635size=64 636 637[system.cpu0.tracer] 638type=ExeTracer 639eventq_index=0 640 641[system.cpu0.workload]
641type=LiveProcess	642type=Process
642cmd=test_atomic 4 643cwd= 644drivers= 645egid=100 646env= 647errout=cerr 648euid=100 649eventq_index=0	643cmd=test_atomic 4 644cwd= 645drivers= 646egid=100 647env= 648errout=cerr 649euid=100 650eventq_index=0
650executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic	651executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
651gid=100 652input=cin 653kvmInSE=false	652gid=100 653input=cin 654kvmInSE=false
654max_stack_size=67108864	655maxStackSize=67108864
655output=cout	656output=cout
	657pgid=100
656pid=100	658pid=100
657ppid=99	659ppid=0
658simpoint=0 659system=system 660uid=100 661useArchPT=false 662 663[system.cpu1] 664type=DerivO3CPU 665children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 666LFSTSize=1024 667LQEntries=32 668LSQCheckLoads=true 669LSQDepCheckShift=4 670SQEntries=32 671SSITSize=1024 672activity=0 673backComSize=5 674branchPred=system.cpu1.branchPred	660simpoint=0 661system=system 662uid=100 663useArchPT=false 664 665[system.cpu1] 666type=DerivO3CPU 667children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 668LFSTSize=1024 669LQEntries=32 670LSQCheckLoads=true 671LSQDepCheckShift=4 672SQEntries=32 673SSITSize=1024 674activity=0 675backComSize=5 676branchPred=system.cpu1.branchPred
675cachePorts=200	677cacheStorePorts=200
676checker=Null 677clk_domain=system.cpu_clk_domain 678commitToDecodeDelay=1 679commitToFetchDelay=1 680commitToIEWDelay=1 681commitToRenameDelay=1 682commitWidth=8 683cpu_id=1 684decodeToFetchDelay=1 685decodeToRenameDelay=1 686decodeWidth=8 687default_p_state=UNDEFINED 688dispatchWidth=8 689do_checkpoint_insts=true 690do_quiesce=true 691do_statistics_insts=true 692dtb=system.cpu1.dtb 693eventq_index=0 694fetchBufferSize=64 695fetchQueueSize=32 696fetchToDecodeDelay=1 697fetchTrapLatency=1 698fetchWidth=8 699forwardComSize=5 700fuPool=system.cpu1.fuPool 701function_trace=false 702function_trace_start=0 703iewToCommitDelay=1 704iewToDecodeDelay=1 705iewToFetchDelay=1 706iewToRenameDelay=1 707interrupts=system.cpu1.interrupts 708isa=system.cpu1.isa 709issueToExecuteDelay=1 710issueWidth=8 711itb=system.cpu1.itb 712max_insts_all_threads=0 713max_insts_any_thread=0 714max_loads_all_threads=0 715max_loads_any_thread=0 716needsTSO=false 717numIQEntries=64 718numPhysCCRegs=0 719numPhysFloatRegs=256 720numPhysIntRegs=256 721numROBEntries=192 722numRobs=1 723numThreads=1 724p_state_clk_gate_bins=20 725p_state_clk_gate_max=1000000000000 726p_state_clk_gate_min=1000 727power_model=Null 728profile=0 729progress_interval=0 730renameToDecodeDelay=1 731renameToFetchDelay=1 732renameToIEWDelay=2 733renameToROBDelay=1 734renameWidth=8 735simpoint_start_insts= 736smtCommitPolicy=RoundRobin 737smtFetchPolicy=SingleThread 738smtIQPolicy=Partitioned 739smtIQThreshold=100 740smtLSQPolicy=Partitioned 741smtLSQThreshold=100 742smtNumFetchingThreads=1 743smtROBPolicy=Partitioned 744smtROBThreshold=100 745socket_id=0 746squashWidth=8 747store_set_clear_period=250000 748switched_out=false	678checker=Null 679clk_domain=system.cpu_clk_domain 680commitToDecodeDelay=1 681commitToFetchDelay=1 682commitToIEWDelay=1 683commitToRenameDelay=1 684commitWidth=8 685cpu_id=1 686decodeToFetchDelay=1 687decodeToRenameDelay=1 688decodeWidth=8 689default_p_state=UNDEFINED 690dispatchWidth=8 691do_checkpoint_insts=true 692do_quiesce=true 693do_statistics_insts=true 694dtb=system.cpu1.dtb 695eventq_index=0 696fetchBufferSize=64 697fetchQueueSize=32 698fetchToDecodeDelay=1 699fetchTrapLatency=1 700fetchWidth=8 701forwardComSize=5 702fuPool=system.cpu1.fuPool 703function_trace=false 704function_trace_start=0 705iewToCommitDelay=1 706iewToDecodeDelay=1 707iewToFetchDelay=1 708iewToRenameDelay=1 709interrupts=system.cpu1.interrupts 710isa=system.cpu1.isa 711issueToExecuteDelay=1 712issueWidth=8 713itb=system.cpu1.itb 714max_insts_all_threads=0 715max_insts_any_thread=0 716max_loads_all_threads=0 717max_loads_any_thread=0 718needsTSO=false 719numIQEntries=64 720numPhysCCRegs=0 721numPhysFloatRegs=256 722numPhysIntRegs=256 723numROBEntries=192 724numRobs=1 725numThreads=1 726p_state_clk_gate_bins=20 727p_state_clk_gate_max=1000000000000 728p_state_clk_gate_min=1000 729power_model=Null 730profile=0 731progress_interval=0 732renameToDecodeDelay=1 733renameToFetchDelay=1 734renameToIEWDelay=2 735renameToROBDelay=1 736renameWidth=8 737simpoint_start_insts= 738smtCommitPolicy=RoundRobin 739smtFetchPolicy=SingleThread 740smtIQPolicy=Partitioned 741smtIQThreshold=100 742smtLSQPolicy=Partitioned 743smtLSQThreshold=100 744smtNumFetchingThreads=1 745smtROBPolicy=Partitioned 746smtROBThreshold=100 747socket_id=0 748squashWidth=8 749store_set_clear_period=250000 750switched_out=false
	751syscallRetryLatency=10000
749system=system 750tracer=system.cpu1.tracer 751trapLatency=13 752wbWidth=8 753workload=system.cpu0.workload 754dcache_port=system.cpu1.dcache.cpu_side 755icache_port=system.cpu1.icache.cpu_side 756 757[system.cpu1.branchPred] 758type=TournamentBP 759BTBEntries=4096 760BTBTagSize=16 761RASSize=16 762choiceCtrBits=2 763choicePredictorSize=8192 764eventq_index=0 765globalCtrBits=2 766globalPredictorSize=8192 767indirectHashGHR=true 768indirectHashTargets=true 769indirectPathLength=3 770indirectSets=256 771indirectTagSize=16 772indirectWays=2 773instShiftAmt=2 774localCtrBits=2 775localHistoryTableSize=2048 776localPredictorSize=2048 777numThreads=1 778useIndirect=true 779 780[system.cpu1.dcache] 781type=Cache 782children=tags 783addr_ranges=0:18446744073709551615:0:0:0:0 784assoc=4 785clk_domain=system.cpu_clk_domain 786clusivity=mostly_incl 787data_latency=2 788default_p_state=UNDEFINED 789demand_mshr_reserve=1 790eventq_index=0 791is_read_only=false 792max_miss_count=0 793mshrs=4 794p_state_clk_gate_bins=20 795p_state_clk_gate_max=1000000000000 796p_state_clk_gate_min=1000 797power_model=Null 798prefetch_on_access=false 799prefetcher=Null 800response_latency=2 801sequential_access=false 802size=32768 803system=system 804tag_latency=2 805tags=system.cpu1.dcache.tags 806tgts_per_mshr=20 807write_buffers=8 808writeback_clean=false 809cpu_side=system.cpu1.dcache_port 810mem_side=system.toL2Bus.slave[3] 811 812[system.cpu1.dcache.tags] 813type=LRU 814assoc=4 815block_size=64 816clk_domain=system.cpu_clk_domain 817data_latency=2 818default_p_state=UNDEFINED 819eventq_index=0 820p_state_clk_gate_bins=20 821p_state_clk_gate_max=1000000000000 822p_state_clk_gate_min=1000 823power_model=Null 824sequential_access=false 825size=32768 826tag_latency=2 827 828[system.cpu1.dtb] 829type=SparcTLB 830eventq_index=0 831size=64 832 833[system.cpu1.fuPool] 834type=FUPool 835children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 836FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 837eventq_index=0 838 839[system.cpu1.fuPool.FUList0] 840type=FUDesc 841children=opList 842count=6 843eventq_index=0 844opList=system.cpu1.fuPool.FUList0.opList 845 846[system.cpu1.fuPool.FUList0.opList] 847type=OpDesc 848eventq_index=0 849opClass=IntAlu 850opLat=1 851pipelined=true 852 853[system.cpu1.fuPool.FUList1] 854type=FUDesc 855children=opList0 opList1 856count=2 857eventq_index=0 858opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 859 860[system.cpu1.fuPool.FUList1.opList0] 861type=OpDesc 862eventq_index=0 863opClass=IntMult 864opLat=3 865pipelined=true 866 867[system.cpu1.fuPool.FUList1.opList1] 868type=OpDesc 869eventq_index=0 870opClass=IntDiv 871opLat=20 872pipelined=false 873 874[system.cpu1.fuPool.FUList2] 875type=FUDesc 876children=opList0 opList1 opList2 877count=4 878eventq_index=0 879opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 880 881[system.cpu1.fuPool.FUList2.opList0] 882type=OpDesc 883eventq_index=0 884opClass=FloatAdd 885opLat=2 886pipelined=true 887 888[system.cpu1.fuPool.FUList2.opList1] 889type=OpDesc 890eventq_index=0 891opClass=FloatCmp 892opLat=2 893pipelined=true 894 895[system.cpu1.fuPool.FUList2.opList2] 896type=OpDesc 897eventq_index=0 898opClass=FloatCvt 899opLat=2 900pipelined=true 901 902[system.cpu1.fuPool.FUList3] 903type=FUDesc 904children=opList0 opList1 opList2 opList3 opList4 905count=2 906eventq_index=0 907opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 system.cpu1.fuPool.FUList3.opList3 system.cpu1.fuPool.FUList3.opList4 908 909[system.cpu1.fuPool.FUList3.opList0] 910type=OpDesc 911eventq_index=0 912opClass=FloatMult 913opLat=4 914pipelined=true 915 916[system.cpu1.fuPool.FUList3.opList1] 917type=OpDesc 918eventq_index=0 919opClass=FloatMultAcc 920opLat=5 921pipelined=true 922 923[system.cpu1.fuPool.FUList3.opList2] 924type=OpDesc 925eventq_index=0 926opClass=FloatMisc 927opLat=3 928pipelined=true 929 930[system.cpu1.fuPool.FUList3.opList3] 931type=OpDesc 932eventq_index=0 933opClass=FloatDiv 934opLat=12 935pipelined=false 936 937[system.cpu1.fuPool.FUList3.opList4] 938type=OpDesc 939eventq_index=0 940opClass=FloatSqrt 941opLat=24 942pipelined=false 943 944[system.cpu1.fuPool.FUList4] 945type=FUDesc 946children=opList0 opList1 947count=0 948eventq_index=0 949opList=system.cpu1.fuPool.FUList4.opList0 system.cpu1.fuPool.FUList4.opList1 950 951[system.cpu1.fuPool.FUList4.opList0] 952type=OpDesc 953eventq_index=0 954opClass=MemRead 955opLat=1 956pipelined=true 957 958[system.cpu1.fuPool.FUList4.opList1] 959type=OpDesc 960eventq_index=0 961opClass=FloatMemRead 962opLat=1 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1209write_buffers=8 1210writeback_clean=true 1211cpu_side=system.cpu1.icache_port 1212mem_side=system.toL2Bus.slave[2] 1213 1214[system.cpu1.icache.tags] 1215type=LRU 1216assoc=1 1217block_size=64 1218clk_domain=system.cpu_clk_domain 1219data_latency=2 1220default_p_state=UNDEFINED 1221eventq_index=0 1222p_state_clk_gate_bins=20 1223p_state_clk_gate_max=1000000000000 1224p_state_clk_gate_min=1000 1225power_model=Null 1226sequential_access=false 1227size=32768 1228tag_latency=2 1229 1230[system.cpu1.interrupts] 1231type=SparcInterrupts 1232eventq_index=0 1233 1234[system.cpu1.isa] 1235type=SparcISA 1236eventq_index=0 1237 1238[system.cpu1.itb] 1239type=SparcTLB 1240eventq_index=0 1241size=64 1242 1243[system.cpu1.tracer] 1244type=ExeTracer 1245eventq_index=0 1246 1247[system.cpu2] 1248type=DerivO3CPU 1249children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1250LFSTSize=1024 1251LQEntries=32 1252LSQCheckLoads=true 1253LSQDepCheckShift=4 1254SQEntries=32 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962type=OpDesc 963eventq_index=0 964opClass=FloatMemRead 965opLat=1 966pipelined=true 967 968[system.cpu1.fuPool.FUList5] 969type=FUDesc 970children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 971count=4 972eventq_index=0 973opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 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1073[system.cpu1.fuPool.FUList5.opList14] 1074type=OpDesc 1075eventq_index=0 1076opClass=SimdFloatCvt 1077opLat=1 1078pipelined=true 1079 1080[system.cpu1.fuPool.FUList5.opList15] 1081type=OpDesc 1082eventq_index=0 1083opClass=SimdFloatDiv 1084opLat=1 1085pipelined=true 1086 1087[system.cpu1.fuPool.FUList5.opList16] 1088type=OpDesc 1089eventq_index=0 1090opClass=SimdFloatMisc 1091opLat=1 1092pipelined=true 1093 1094[system.cpu1.fuPool.FUList5.opList17] 1095type=OpDesc 1096eventq_index=0 1097opClass=SimdFloatMult 1098opLat=1 1099pipelined=true 1100 1101[system.cpu1.fuPool.FUList5.opList18] 1102type=OpDesc 1103eventq_index=0 1104opClass=SimdFloatMultAcc 1105opLat=1 1106pipelined=true 1107 1108[system.cpu1.fuPool.FUList5.opList19] 1109type=OpDesc 1110eventq_index=0 1111opClass=SimdFloatSqrt 1112opLat=1 1113pipelined=true 1114 1115[system.cpu1.fuPool.FUList6] 1116type=FUDesc 1117children=opList0 opList1 1118count=0 1119eventq_index=0 1120opList=system.cpu1.fuPool.FUList6.opList0 system.cpu1.fuPool.FUList6.opList1 1121 1122[system.cpu1.fuPool.FUList6.opList0] 1123type=OpDesc 1124eventq_index=0 1125opClass=MemWrite 1126opLat=1 1127pipelined=true 1128 1129[system.cpu1.fuPool.FUList6.opList1] 1130type=OpDesc 1131eventq_index=0 1132opClass=FloatMemWrite 1133opLat=1 1134pipelined=true 1135 1136[system.cpu1.fuPool.FUList7] 1137type=FUDesc 1138children=opList0 opList1 opList2 opList3 1139count=4 1140eventq_index=0 1141opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 system.cpu1.fuPool.FUList7.opList2 system.cpu1.fuPool.FUList7.opList3 1142 1143[system.cpu1.fuPool.FUList7.opList0] 1144type=OpDesc 1145eventq_index=0 1146opClass=MemRead 1147opLat=1 1148pipelined=true 1149 1150[system.cpu1.fuPool.FUList7.opList1] 1151type=OpDesc 1152eventq_index=0 1153opClass=MemWrite 1154opLat=1 1155pipelined=true 1156 1157[system.cpu1.fuPool.FUList7.opList2] 1158type=OpDesc 1159eventq_index=0 1160opClass=FloatMemRead 1161opLat=1 1162pipelined=true 1163 1164[system.cpu1.fuPool.FUList7.opList3] 1165type=OpDesc 1166eventq_index=0 1167opClass=FloatMemWrite 1168opLat=1 1169pipelined=true 1170 1171[system.cpu1.fuPool.FUList8] 1172type=FUDesc 1173children=opList 1174count=1 1175eventq_index=0 1176opList=system.cpu1.fuPool.FUList8.opList 1177 1178[system.cpu1.fuPool.FUList8.opList] 1179type=OpDesc 1180eventq_index=0 1181opClass=IprAccess 1182opLat=3 1183pipelined=false 1184 1185[system.cpu1.icache] 1186type=Cache 1187children=tags 1188addr_ranges=0:18446744073709551615:0:0:0:0 1189assoc=1 1190clk_domain=system.cpu_clk_domain 1191clusivity=mostly_incl 1192data_latency=2 1193default_p_state=UNDEFINED 1194demand_mshr_reserve=1 1195eventq_index=0 1196is_read_only=true 1197max_miss_count=0 1198mshrs=4 1199p_state_clk_gate_bins=20 1200p_state_clk_gate_max=1000000000000 1201p_state_clk_gate_min=1000 1202power_model=Null 1203prefetch_on_access=false 1204prefetcher=Null 1205response_latency=2 1206sequential_access=false 1207size=32768 1208system=system 1209tag_latency=2 1210tags=system.cpu1.icache.tags 1211tgts_per_mshr=20 1212write_buffers=8 1213writeback_clean=true 1214cpu_side=system.cpu1.icache_port 1215mem_side=system.toL2Bus.slave[2] 1216 1217[system.cpu1.icache.tags] 1218type=LRU 1219assoc=1 1220block_size=64 1221clk_domain=system.cpu_clk_domain 1222data_latency=2 1223default_p_state=UNDEFINED 1224eventq_index=0 1225p_state_clk_gate_bins=20 1226p_state_clk_gate_max=1000000000000 1227p_state_clk_gate_min=1000 1228power_model=Null 1229sequential_access=false 1230size=32768 1231tag_latency=2 1232 1233[system.cpu1.interrupts] 1234type=SparcInterrupts 1235eventq_index=0 1236 1237[system.cpu1.isa] 1238type=SparcISA 1239eventq_index=0 1240 1241[system.cpu1.itb] 1242type=SparcTLB 1243eventq_index=0 1244size=64 1245 1246[system.cpu1.tracer] 1247type=ExeTracer 1248eventq_index=0 1249 1250[system.cpu2] 1251type=DerivO3CPU 1252children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1253LFSTSize=1024 1254LQEntries=32 1255LSQCheckLoads=true 1256LSQDepCheckShift=4 1257SQEntries=32 1258SSITSize=1024 1259activity=0 1260backComSize=5 1261branchPred=system.cpu2.branchPred
1259cachePorts=200	1262cacheStorePorts=200
1260checker=Null 1261clk_domain=system.cpu_clk_domain 1262commitToDecodeDelay=1 1263commitToFetchDelay=1 1264commitToIEWDelay=1 1265commitToRenameDelay=1 1266commitWidth=8 1267cpu_id=2 1268decodeToFetchDelay=1 1269decodeToRenameDelay=1 1270decodeWidth=8 1271default_p_state=UNDEFINED 1272dispatchWidth=8 1273do_checkpoint_insts=true 1274do_quiesce=true 1275do_statistics_insts=true 1276dtb=system.cpu2.dtb 1277eventq_index=0 1278fetchBufferSize=64 1279fetchQueueSize=32 1280fetchToDecodeDelay=1 1281fetchTrapLatency=1 1282fetchWidth=8 1283forwardComSize=5 1284fuPool=system.cpu2.fuPool 1285function_trace=false 1286function_trace_start=0 1287iewToCommitDelay=1 1288iewToDecodeDelay=1 1289iewToFetchDelay=1 1290iewToRenameDelay=1 1291interrupts=system.cpu2.interrupts 1292isa=system.cpu2.isa 1293issueToExecuteDelay=1 1294issueWidth=8 1295itb=system.cpu2.itb 1296max_insts_all_threads=0 1297max_insts_any_thread=0 1298max_loads_all_threads=0 1299max_loads_any_thread=0 1300needsTSO=false 1301numIQEntries=64 1302numPhysCCRegs=0 1303numPhysFloatRegs=256 1304numPhysIntRegs=256 1305numROBEntries=192 1306numRobs=1 1307numThreads=1 1308p_state_clk_gate_bins=20 1309p_state_clk_gate_max=1000000000000 1310p_state_clk_gate_min=1000 1311power_model=Null 1312profile=0 1313progress_interval=0 1314renameToDecodeDelay=1 1315renameToFetchDelay=1 1316renameToIEWDelay=2 1317renameToROBDelay=1 1318renameWidth=8 1319simpoint_start_insts= 1320smtCommitPolicy=RoundRobin 1321smtFetchPolicy=SingleThread 1322smtIQPolicy=Partitioned 1323smtIQThreshold=100 1324smtLSQPolicy=Partitioned 1325smtLSQThreshold=100 1326smtNumFetchingThreads=1 1327smtROBPolicy=Partitioned 1328smtROBThreshold=100 1329socket_id=0 1330squashWidth=8 1331store_set_clear_period=250000 1332switched_out=false	1263checker=Null 1264clk_domain=system.cpu_clk_domain 1265commitToDecodeDelay=1 1266commitToFetchDelay=1 1267commitToIEWDelay=1 1268commitToRenameDelay=1 1269commitWidth=8 1270cpu_id=2 1271decodeToFetchDelay=1 1272decodeToRenameDelay=1 1273decodeWidth=8 1274default_p_state=UNDEFINED 1275dispatchWidth=8 1276do_checkpoint_insts=true 1277do_quiesce=true 1278do_statistics_insts=true 1279dtb=system.cpu2.dtb 1280eventq_index=0 1281fetchBufferSize=64 1282fetchQueueSize=32 1283fetchToDecodeDelay=1 1284fetchTrapLatency=1 1285fetchWidth=8 1286forwardComSize=5 1287fuPool=system.cpu2.fuPool 1288function_trace=false 1289function_trace_start=0 1290iewToCommitDelay=1 1291iewToDecodeDelay=1 1292iewToFetchDelay=1 1293iewToRenameDelay=1 1294interrupts=system.cpu2.interrupts 1295isa=system.cpu2.isa 1296issueToExecuteDelay=1 1297issueWidth=8 1298itb=system.cpu2.itb 1299max_insts_all_threads=0 1300max_insts_any_thread=0 1301max_loads_all_threads=0 1302max_loads_any_thread=0 1303needsTSO=false 1304numIQEntries=64 1305numPhysCCRegs=0 1306numPhysFloatRegs=256 1307numPhysIntRegs=256 1308numROBEntries=192 1309numRobs=1 1310numThreads=1 1311p_state_clk_gate_bins=20 1312p_state_clk_gate_max=1000000000000 1313p_state_clk_gate_min=1000 1314power_model=Null 1315profile=0 1316progress_interval=0 1317renameToDecodeDelay=1 1318renameToFetchDelay=1 1319renameToIEWDelay=2 1320renameToROBDelay=1 1321renameWidth=8 1322simpoint_start_insts= 1323smtCommitPolicy=RoundRobin 1324smtFetchPolicy=SingleThread 1325smtIQPolicy=Partitioned 1326smtIQThreshold=100 1327smtLSQPolicy=Partitioned 1328smtLSQThreshold=100 1329smtNumFetchingThreads=1 1330smtROBPolicy=Partitioned 1331smtROBThreshold=100 1332socket_id=0 1333squashWidth=8 1334store_set_clear_period=250000 1335switched_out=false
	1336syscallRetryLatency=10000
1333system=system 1334tracer=system.cpu2.tracer 1335trapLatency=13 1336wbWidth=8 1337workload=system.cpu0.workload 1338dcache_port=system.cpu2.dcache.cpu_side 1339icache_port=system.cpu2.icache.cpu_side 1340 1341[system.cpu2.branchPred] 1342type=TournamentBP 1343BTBEntries=4096 1344BTBTagSize=16 1345RASSize=16 1346choiceCtrBits=2 1347choicePredictorSize=8192 1348eventq_index=0 1349globalCtrBits=2 1350globalPredictorSize=8192 1351indirectHashGHR=true 1352indirectHashTargets=true 1353indirectPathLength=3 1354indirectSets=256 1355indirectTagSize=16 1356indirectWays=2 1357instShiftAmt=2 1358localCtrBits=2 1359localHistoryTableSize=2048 1360localPredictorSize=2048 1361numThreads=1 1362useIndirect=true 1363 1364[system.cpu2.dcache] 1365type=Cache 1366children=tags 1367addr_ranges=0:18446744073709551615:0:0:0:0 1368assoc=4 1369clk_domain=system.cpu_clk_domain 1370clusivity=mostly_incl 1371data_latency=2 1372default_p_state=UNDEFINED 1373demand_mshr_reserve=1 1374eventq_index=0 1375is_read_only=false 1376max_miss_count=0 1377mshrs=4 1378p_state_clk_gate_bins=20 1379p_state_clk_gate_max=1000000000000 1380p_state_clk_gate_min=1000 1381power_model=Null 1382prefetch_on_access=false 1383prefetcher=Null 1384response_latency=2 1385sequential_access=false 1386size=32768 1387system=system 1388tag_latency=2 1389tags=system.cpu2.dcache.tags 1390tgts_per_mshr=20 1391write_buffers=8 1392writeback_clean=false 1393cpu_side=system.cpu2.dcache_port 1394mem_side=system.toL2Bus.slave[5] 1395 1396[system.cpu2.dcache.tags] 1397type=LRU 1398assoc=4 1399block_size=64 1400clk_domain=system.cpu_clk_domain 1401data_latency=2 1402default_p_state=UNDEFINED 1403eventq_index=0 1404p_state_clk_gate_bins=20 1405p_state_clk_gate_max=1000000000000 1406p_state_clk_gate_min=1000 1407power_model=Null 1408sequential_access=false 1409size=32768 1410tag_latency=2 1411 1412[system.cpu2.dtb] 1413type=SparcTLB 1414eventq_index=0 1415size=64 1416 1417[system.cpu2.fuPool] 1418type=FUPool 1419children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1420FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 1421eventq_index=0 1422 1423[system.cpu2.fuPool.FUList0] 1424type=FUDesc 1425children=opList 1426count=6 1427eventq_index=0 1428opList=system.cpu2.fuPool.FUList0.opList 1429 1430[system.cpu2.fuPool.FUList0.opList] 1431type=OpDesc 1432eventq_index=0 1433opClass=IntAlu 1434opLat=1 1435pipelined=true 1436 1437[system.cpu2.fuPool.FUList1] 1438type=FUDesc 1439children=opList0 opList1 1440count=2 1441eventq_index=0 1442opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 1443 1444[system.cpu2.fuPool.FUList1.opList0] 1445type=OpDesc 1446eventq_index=0 1447opClass=IntMult 1448opLat=3 1449pipelined=true 1450 1451[system.cpu2.fuPool.FUList1.opList1] 1452type=OpDesc 1453eventq_index=0 1454opClass=IntDiv 1455opLat=20 1456pipelined=false 1457 1458[system.cpu2.fuPool.FUList2] 1459type=FUDesc 1460children=opList0 opList1 opList2 1461count=4 1462eventq_index=0 1463opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 1464 1465[system.cpu2.fuPool.FUList2.opList0] 1466type=OpDesc 1467eventq_index=0 1468opClass=FloatAdd 1469opLat=2 1470pipelined=true 1471 1472[system.cpu2.fuPool.FUList2.opList1] 1473type=OpDesc 1474eventq_index=0 1475opClass=FloatCmp 1476opLat=2 1477pipelined=true 1478 1479[system.cpu2.fuPool.FUList2.opList2] 1480type=OpDesc 1481eventq_index=0 1482opClass=FloatCvt 1483opLat=2 1484pipelined=true 1485 1486[system.cpu2.fuPool.FUList3] 1487type=FUDesc 1488children=opList0 opList1 opList2 opList3 opList4 1489count=2 1490eventq_index=0 1491opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 system.cpu2.fuPool.FUList3.opList3 system.cpu2.fuPool.FUList3.opList4 1492 1493[system.cpu2.fuPool.FUList3.opList0] 1494type=OpDesc 1495eventq_index=0 1496opClass=FloatMult 1497opLat=4 1498pipelined=true 1499 1500[system.cpu2.fuPool.FUList3.opList1] 1501type=OpDesc 1502eventq_index=0 1503opClass=FloatMultAcc 1504opLat=5 1505pipelined=true 1506 1507[system.cpu2.fuPool.FUList3.opList2] 1508type=OpDesc 1509eventq_index=0 1510opClass=FloatMisc 1511opLat=3 1512pipelined=true 1513 1514[system.cpu2.fuPool.FUList3.opList3] 1515type=OpDesc 1516eventq_index=0 1517opClass=FloatDiv 1518opLat=12 1519pipelined=false 1520 1521[system.cpu2.fuPool.FUList3.opList4] 1522type=OpDesc 1523eventq_index=0 1524opClass=FloatSqrt 1525opLat=24 1526pipelined=false 1527 1528[system.cpu2.fuPool.FUList4] 1529type=FUDesc 1530children=opList0 opList1 1531count=0 1532eventq_index=0 1533opList=system.cpu2.fuPool.FUList4.opList0 system.cpu2.fuPool.FUList4.opList1 1534 1535[system.cpu2.fuPool.FUList4.opList0] 1536type=OpDesc 1537eventq_index=0 1538opClass=MemRead 1539opLat=1 1540pipelined=true 1541 1542[system.cpu2.fuPool.FUList4.opList1] 1543type=OpDesc 1544eventq_index=0 1545opClass=FloatMemRead 1546opLat=1 1547pipelined=true 1548 1549[system.cpu2.fuPool.FUList5] 1550type=FUDesc 1551children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1552count=4 1553eventq_index=0 1554opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 1555 1556[system.cpu2.fuPool.FUList5.opList00] 1557type=OpDesc 1558eventq_index=0 1559opClass=SimdAdd 1560opLat=1 1561pipelined=true 1562 1563[system.cpu2.fuPool.FUList5.opList01] 1564type=OpDesc 1565eventq_index=0 1566opClass=SimdAddAcc 1567opLat=1 1568pipelined=true 1569 1570[system.cpu2.fuPool.FUList5.opList02] 1571type=OpDesc 1572eventq_index=0 1573opClass=SimdAlu 1574opLat=1 1575pipelined=true 1576 1577[system.cpu2.fuPool.FUList5.opList03] 1578type=OpDesc 1579eventq_index=0 1580opClass=SimdCmp 1581opLat=1 1582pipelined=true 1583 1584[system.cpu2.fuPool.FUList5.opList04] 1585type=OpDesc 1586eventq_index=0 1587opClass=SimdCvt 1588opLat=1 1589pipelined=true 1590 1591[system.cpu2.fuPool.FUList5.opList05] 1592type=OpDesc 1593eventq_index=0 1594opClass=SimdMisc 1595opLat=1 1596pipelined=true 1597 1598[system.cpu2.fuPool.FUList5.opList06] 1599type=OpDesc 1600eventq_index=0 1601opClass=SimdMult 1602opLat=1 1603pipelined=true 1604 1605[system.cpu2.fuPool.FUList5.opList07] 1606type=OpDesc 1607eventq_index=0 1608opClass=SimdMultAcc 1609opLat=1 1610pipelined=true 1611 1612[system.cpu2.fuPool.FUList5.opList08] 1613type=OpDesc 1614eventq_index=0 1615opClass=SimdShift 1616opLat=1 1617pipelined=true 1618 1619[system.cpu2.fuPool.FUList5.opList09] 1620type=OpDesc 1621eventq_index=0 1622opClass=SimdShiftAcc 1623opLat=1 1624pipelined=true 1625 1626[system.cpu2.fuPool.FUList5.opList10] 1627type=OpDesc 1628eventq_index=0 1629opClass=SimdSqrt 1630opLat=1 1631pipelined=true 1632 1633[system.cpu2.fuPool.FUList5.opList11] 1634type=OpDesc 1635eventq_index=0 1636opClass=SimdFloatAdd 1637opLat=1 1638pipelined=true 1639 1640[system.cpu2.fuPool.FUList5.opList12] 1641type=OpDesc 1642eventq_index=0 1643opClass=SimdFloatAlu 1644opLat=1 1645pipelined=true 1646 1647[system.cpu2.fuPool.FUList5.opList13] 1648type=OpDesc 1649eventq_index=0 1650opClass=SimdFloatCmp 1651opLat=1 1652pipelined=true 1653 1654[system.cpu2.fuPool.FUList5.opList14] 1655type=OpDesc 1656eventq_index=0 1657opClass=SimdFloatCvt 1658opLat=1 1659pipelined=true 1660 1661[system.cpu2.fuPool.FUList5.opList15] 1662type=OpDesc 1663eventq_index=0 1664opClass=SimdFloatDiv 1665opLat=1 1666pipelined=true 1667 1668[system.cpu2.fuPool.FUList5.opList16] 1669type=OpDesc 1670eventq_index=0 1671opClass=SimdFloatMisc 1672opLat=1 1673pipelined=true 1674 1675[system.cpu2.fuPool.FUList5.opList17] 1676type=OpDesc 1677eventq_index=0 1678opClass=SimdFloatMult 1679opLat=1 1680pipelined=true 1681 1682[system.cpu2.fuPool.FUList5.opList18] 1683type=OpDesc 1684eventq_index=0 1685opClass=SimdFloatMultAcc 1686opLat=1 1687pipelined=true 1688 1689[system.cpu2.fuPool.FUList5.opList19] 1690type=OpDesc 1691eventq_index=0 1692opClass=SimdFloatSqrt 1693opLat=1 1694pipelined=true 1695 1696[system.cpu2.fuPool.FUList6] 1697type=FUDesc 1698children=opList0 opList1 1699count=0 1700eventq_index=0 1701opList=system.cpu2.fuPool.FUList6.opList0 system.cpu2.fuPool.FUList6.opList1 1702 1703[system.cpu2.fuPool.FUList6.opList0] 1704type=OpDesc 1705eventq_index=0 1706opClass=MemWrite 1707opLat=1 1708pipelined=true 1709 1710[system.cpu2.fuPool.FUList6.opList1] 1711type=OpDesc 1712eventq_index=0 1713opClass=FloatMemWrite 1714opLat=1 1715pipelined=true 1716 1717[system.cpu2.fuPool.FUList7] 1718type=FUDesc 1719children=opList0 opList1 opList2 opList3 1720count=4 1721eventq_index=0 1722opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 system.cpu2.fuPool.FUList7.opList2 system.cpu2.fuPool.FUList7.opList3 1723 1724[system.cpu2.fuPool.FUList7.opList0] 1725type=OpDesc 1726eventq_index=0 1727opClass=MemRead 1728opLat=1 1729pipelined=true 1730 1731[system.cpu2.fuPool.FUList7.opList1] 1732type=OpDesc 1733eventq_index=0 1734opClass=MemWrite 1735opLat=1 1736pipelined=true 1737 1738[system.cpu2.fuPool.FUList7.opList2] 1739type=OpDesc 1740eventq_index=0 1741opClass=FloatMemRead 1742opLat=1 1743pipelined=true 1744 1745[system.cpu2.fuPool.FUList7.opList3] 1746type=OpDesc 1747eventq_index=0 1748opClass=FloatMemWrite 1749opLat=1 1750pipelined=true 1751 1752[system.cpu2.fuPool.FUList8] 1753type=FUDesc 1754children=opList 1755count=1 1756eventq_index=0 1757opList=system.cpu2.fuPool.FUList8.opList 1758 1759[system.cpu2.fuPool.FUList8.opList] 1760type=OpDesc 1761eventq_index=0 1762opClass=IprAccess 1763opLat=3 1764pipelined=false 1765 1766[system.cpu2.icache] 1767type=Cache 1768children=tags 1769addr_ranges=0:18446744073709551615:0:0:0:0 1770assoc=1 1771clk_domain=system.cpu_clk_domain 1772clusivity=mostly_incl 1773data_latency=2 1774default_p_state=UNDEFINED 1775demand_mshr_reserve=1 1776eventq_index=0 1777is_read_only=true 1778max_miss_count=0 1779mshrs=4 1780p_state_clk_gate_bins=20 1781p_state_clk_gate_max=1000000000000 1782p_state_clk_gate_min=1000 1783power_model=Null 1784prefetch_on_access=false 1785prefetcher=Null 1786response_latency=2 1787sequential_access=false 1788size=32768 1789system=system 1790tag_latency=2 1791tags=system.cpu2.icache.tags 1792tgts_per_mshr=20 1793write_buffers=8 1794writeback_clean=true 1795cpu_side=system.cpu2.icache_port 1796mem_side=system.toL2Bus.slave[4] 1797 1798[system.cpu2.icache.tags] 1799type=LRU 1800assoc=1 1801block_size=64 1802clk_domain=system.cpu_clk_domain 1803data_latency=2 1804default_p_state=UNDEFINED 1805eventq_index=0 1806p_state_clk_gate_bins=20 1807p_state_clk_gate_max=1000000000000 1808p_state_clk_gate_min=1000 1809power_model=Null 1810sequential_access=false 1811size=32768 1812tag_latency=2 1813 1814[system.cpu2.interrupts] 1815type=SparcInterrupts 1816eventq_index=0 1817 1818[system.cpu2.isa] 1819type=SparcISA 1820eventq_index=0 1821 1822[system.cpu2.itb] 1823type=SparcTLB 1824eventq_index=0 1825size=64 1826 1827[system.cpu2.tracer] 1828type=ExeTracer 1829eventq_index=0 1830 1831[system.cpu3] 1832type=DerivO3CPU 1833children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1834LFSTSize=1024 1835LQEntries=32 1836LSQCheckLoads=true 1837LSQDepCheckShift=4 1838SQEntries=32 1839SSITSize=1024 1840activity=0 1841backComSize=5 1842branchPred=system.cpu3.branchPred	1337system=system 1338tracer=system.cpu2.tracer 1339trapLatency=13 1340wbWidth=8 1341workload=system.cpu0.workload 1342dcache_port=system.cpu2.dcache.cpu_side 1343icache_port=system.cpu2.icache.cpu_side 1344 1345[system.cpu2.branchPred] 1346type=TournamentBP 1347BTBEntries=4096 1348BTBTagSize=16 1349RASSize=16 1350choiceCtrBits=2 1351choicePredictorSize=8192 1352eventq_index=0 1353globalCtrBits=2 1354globalPredictorSize=8192 1355indirectHashGHR=true 1356indirectHashTargets=true 1357indirectPathLength=3 1358indirectSets=256 1359indirectTagSize=16 1360indirectWays=2 1361instShiftAmt=2 1362localCtrBits=2 1363localHistoryTableSize=2048 1364localPredictorSize=2048 1365numThreads=1 1366useIndirect=true 1367 1368[system.cpu2.dcache] 1369type=Cache 1370children=tags 1371addr_ranges=0:18446744073709551615:0:0:0:0 1372assoc=4 1373clk_domain=system.cpu_clk_domain 1374clusivity=mostly_incl 1375data_latency=2 1376default_p_state=UNDEFINED 1377demand_mshr_reserve=1 1378eventq_index=0 1379is_read_only=false 1380max_miss_count=0 1381mshrs=4 1382p_state_clk_gate_bins=20 1383p_state_clk_gate_max=1000000000000 1384p_state_clk_gate_min=1000 1385power_model=Null 1386prefetch_on_access=false 1387prefetcher=Null 1388response_latency=2 1389sequential_access=false 1390size=32768 1391system=system 1392tag_latency=2 1393tags=system.cpu2.dcache.tags 1394tgts_per_mshr=20 1395write_buffers=8 1396writeback_clean=false 1397cpu_side=system.cpu2.dcache_port 1398mem_side=system.toL2Bus.slave[5] 1399 1400[system.cpu2.dcache.tags] 1401type=LRU 1402assoc=4 1403block_size=64 1404clk_domain=system.cpu_clk_domain 1405data_latency=2 1406default_p_state=UNDEFINED 1407eventq_index=0 1408p_state_clk_gate_bins=20 1409p_state_clk_gate_max=1000000000000 1410p_state_clk_gate_min=1000 1411power_model=Null 1412sequential_access=false 1413size=32768 1414tag_latency=2 1415 1416[system.cpu2.dtb] 1417type=SparcTLB 1418eventq_index=0 1419size=64 1420 1421[system.cpu2.fuPool] 1422type=FUPool 1423children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1424FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 1425eventq_index=0 1426 1427[system.cpu2.fuPool.FUList0] 1428type=FUDesc 1429children=opList 1430count=6 1431eventq_index=0 1432opList=system.cpu2.fuPool.FUList0.opList 1433 1434[system.cpu2.fuPool.FUList0.opList] 1435type=OpDesc 1436eventq_index=0 1437opClass=IntAlu 1438opLat=1 1439pipelined=true 1440 1441[system.cpu2.fuPool.FUList1] 1442type=FUDesc 1443children=opList0 opList1 1444count=2 1445eventq_index=0 1446opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 1447 1448[system.cpu2.fuPool.FUList1.opList0] 1449type=OpDesc 1450eventq_index=0 1451opClass=IntMult 1452opLat=3 1453pipelined=true 1454 1455[system.cpu2.fuPool.FUList1.opList1] 1456type=OpDesc 1457eventq_index=0 1458opClass=IntDiv 1459opLat=20 1460pipelined=false 1461 1462[system.cpu2.fuPool.FUList2] 1463type=FUDesc 1464children=opList0 opList1 opList2 1465count=4 1466eventq_index=0 1467opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 1468 1469[system.cpu2.fuPool.FUList2.opList0] 1470type=OpDesc 1471eventq_index=0 1472opClass=FloatAdd 1473opLat=2 1474pipelined=true 1475 1476[system.cpu2.fuPool.FUList2.opList1] 1477type=OpDesc 1478eventq_index=0 1479opClass=FloatCmp 1480opLat=2 1481pipelined=true 1482 1483[system.cpu2.fuPool.FUList2.opList2] 1484type=OpDesc 1485eventq_index=0 1486opClass=FloatCvt 1487opLat=2 1488pipelined=true 1489 1490[system.cpu2.fuPool.FUList3] 1491type=FUDesc 1492children=opList0 opList1 opList2 opList3 opList4 1493count=2 1494eventq_index=0 1495opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 system.cpu2.fuPool.FUList3.opList3 system.cpu2.fuPool.FUList3.opList4 1496 1497[system.cpu2.fuPool.FUList3.opList0] 1498type=OpDesc 1499eventq_index=0 1500opClass=FloatMult 1501opLat=4 1502pipelined=true 1503 1504[system.cpu2.fuPool.FUList3.opList1] 1505type=OpDesc 1506eventq_index=0 1507opClass=FloatMultAcc 1508opLat=5 1509pipelined=true 1510 1511[system.cpu2.fuPool.FUList3.opList2] 1512type=OpDesc 1513eventq_index=0 1514opClass=FloatMisc 1515opLat=3 1516pipelined=true 1517 1518[system.cpu2.fuPool.FUList3.opList3] 1519type=OpDesc 1520eventq_index=0 1521opClass=FloatDiv 1522opLat=12 1523pipelined=false 1524 1525[system.cpu2.fuPool.FUList3.opList4] 1526type=OpDesc 1527eventq_index=0 1528opClass=FloatSqrt 1529opLat=24 1530pipelined=false 1531 1532[system.cpu2.fuPool.FUList4] 1533type=FUDesc 1534children=opList0 opList1 1535count=0 1536eventq_index=0 1537opList=system.cpu2.fuPool.FUList4.opList0 system.cpu2.fuPool.FUList4.opList1 1538 1539[system.cpu2.fuPool.FUList4.opList0] 1540type=OpDesc 1541eventq_index=0 1542opClass=MemRead 1543opLat=1 1544pipelined=true 1545 1546[system.cpu2.fuPool.FUList4.opList1] 1547type=OpDesc 1548eventq_index=0 1549opClass=FloatMemRead 1550opLat=1 1551pipelined=true 1552 1553[system.cpu2.fuPool.FUList5] 1554type=FUDesc 1555children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1556count=4 1557eventq_index=0 1558opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 1559 1560[system.cpu2.fuPool.FUList5.opList00] 1561type=OpDesc 1562eventq_index=0 1563opClass=SimdAdd 1564opLat=1 1565pipelined=true 1566 1567[system.cpu2.fuPool.FUList5.opList01] 1568type=OpDesc 1569eventq_index=0 1570opClass=SimdAddAcc 1571opLat=1 1572pipelined=true 1573 1574[system.cpu2.fuPool.FUList5.opList02] 1575type=OpDesc 1576eventq_index=0 1577opClass=SimdAlu 1578opLat=1 1579pipelined=true 1580 1581[system.cpu2.fuPool.FUList5.opList03] 1582type=OpDesc 1583eventq_index=0 1584opClass=SimdCmp 1585opLat=1 1586pipelined=true 1587 1588[system.cpu2.fuPool.FUList5.opList04] 1589type=OpDesc 1590eventq_index=0 1591opClass=SimdCvt 1592opLat=1 1593pipelined=true 1594 1595[system.cpu2.fuPool.FUList5.opList05] 1596type=OpDesc 1597eventq_index=0 1598opClass=SimdMisc 1599opLat=1 1600pipelined=true 1601 1602[system.cpu2.fuPool.FUList5.opList06] 1603type=OpDesc 1604eventq_index=0 1605opClass=SimdMult 1606opLat=1 1607pipelined=true 1608 1609[system.cpu2.fuPool.FUList5.opList07] 1610type=OpDesc 1611eventq_index=0 1612opClass=SimdMultAcc 1613opLat=1 1614pipelined=true 1615 1616[system.cpu2.fuPool.FUList5.opList08] 1617type=OpDesc 1618eventq_index=0 1619opClass=SimdShift 1620opLat=1 1621pipelined=true 1622 1623[system.cpu2.fuPool.FUList5.opList09] 1624type=OpDesc 1625eventq_index=0 1626opClass=SimdShiftAcc 1627opLat=1 1628pipelined=true 1629 1630[system.cpu2.fuPool.FUList5.opList10] 1631type=OpDesc 1632eventq_index=0 1633opClass=SimdSqrt 1634opLat=1 1635pipelined=true 1636 1637[system.cpu2.fuPool.FUList5.opList11] 1638type=OpDesc 1639eventq_index=0 1640opClass=SimdFloatAdd 1641opLat=1 1642pipelined=true 1643 1644[system.cpu2.fuPool.FUList5.opList12] 1645type=OpDesc 1646eventq_index=0 1647opClass=SimdFloatAlu 1648opLat=1 1649pipelined=true 1650 1651[system.cpu2.fuPool.FUList5.opList13] 1652type=OpDesc 1653eventq_index=0 1654opClass=SimdFloatCmp 1655opLat=1 1656pipelined=true 1657 1658[system.cpu2.fuPool.FUList5.opList14] 1659type=OpDesc 1660eventq_index=0 1661opClass=SimdFloatCvt 1662opLat=1 1663pipelined=true 1664 1665[system.cpu2.fuPool.FUList5.opList15] 1666type=OpDesc 1667eventq_index=0 1668opClass=SimdFloatDiv 1669opLat=1 1670pipelined=true 1671 1672[system.cpu2.fuPool.FUList5.opList16] 1673type=OpDesc 1674eventq_index=0 1675opClass=SimdFloatMisc 1676opLat=1 1677pipelined=true 1678 1679[system.cpu2.fuPool.FUList5.opList17] 1680type=OpDesc 1681eventq_index=0 1682opClass=SimdFloatMult 1683opLat=1 1684pipelined=true 1685 1686[system.cpu2.fuPool.FUList5.opList18] 1687type=OpDesc 1688eventq_index=0 1689opClass=SimdFloatMultAcc 1690opLat=1 1691pipelined=true 1692 1693[system.cpu2.fuPool.FUList5.opList19] 1694type=OpDesc 1695eventq_index=0 1696opClass=SimdFloatSqrt 1697opLat=1 1698pipelined=true 1699 1700[system.cpu2.fuPool.FUList6] 1701type=FUDesc 1702children=opList0 opList1 1703count=0 1704eventq_index=0 1705opList=system.cpu2.fuPool.FUList6.opList0 system.cpu2.fuPool.FUList6.opList1 1706 1707[system.cpu2.fuPool.FUList6.opList0] 1708type=OpDesc 1709eventq_index=0 1710opClass=MemWrite 1711opLat=1 1712pipelined=true 1713 1714[system.cpu2.fuPool.FUList6.opList1] 1715type=OpDesc 1716eventq_index=0 1717opClass=FloatMemWrite 1718opLat=1 1719pipelined=true 1720 1721[system.cpu2.fuPool.FUList7] 1722type=FUDesc 1723children=opList0 opList1 opList2 opList3 1724count=4 1725eventq_index=0 1726opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 system.cpu2.fuPool.FUList7.opList2 system.cpu2.fuPool.FUList7.opList3 1727 1728[system.cpu2.fuPool.FUList7.opList0] 1729type=OpDesc 1730eventq_index=0 1731opClass=MemRead 1732opLat=1 1733pipelined=true 1734 1735[system.cpu2.fuPool.FUList7.opList1] 1736type=OpDesc 1737eventq_index=0 1738opClass=MemWrite 1739opLat=1 1740pipelined=true 1741 1742[system.cpu2.fuPool.FUList7.opList2] 1743type=OpDesc 1744eventq_index=0 1745opClass=FloatMemRead 1746opLat=1 1747pipelined=true 1748 1749[system.cpu2.fuPool.FUList7.opList3] 1750type=OpDesc 1751eventq_index=0 1752opClass=FloatMemWrite 1753opLat=1 1754pipelined=true 1755 1756[system.cpu2.fuPool.FUList8] 1757type=FUDesc 1758children=opList 1759count=1 1760eventq_index=0 1761opList=system.cpu2.fuPool.FUList8.opList 1762 1763[system.cpu2.fuPool.FUList8.opList] 1764type=OpDesc 1765eventq_index=0 1766opClass=IprAccess 1767opLat=3 1768pipelined=false 1769 1770[system.cpu2.icache] 1771type=Cache 1772children=tags 1773addr_ranges=0:18446744073709551615:0:0:0:0 1774assoc=1 1775clk_domain=system.cpu_clk_domain 1776clusivity=mostly_incl 1777data_latency=2 1778default_p_state=UNDEFINED 1779demand_mshr_reserve=1 1780eventq_index=0 1781is_read_only=true 1782max_miss_count=0 1783mshrs=4 1784p_state_clk_gate_bins=20 1785p_state_clk_gate_max=1000000000000 1786p_state_clk_gate_min=1000 1787power_model=Null 1788prefetch_on_access=false 1789prefetcher=Null 1790response_latency=2 1791sequential_access=false 1792size=32768 1793system=system 1794tag_latency=2 1795tags=system.cpu2.icache.tags 1796tgts_per_mshr=20 1797write_buffers=8 1798writeback_clean=true 1799cpu_side=system.cpu2.icache_port 1800mem_side=system.toL2Bus.slave[4] 1801 1802[system.cpu2.icache.tags] 1803type=LRU 1804assoc=1 1805block_size=64 1806clk_domain=system.cpu_clk_domain 1807data_latency=2 1808default_p_state=UNDEFINED 1809eventq_index=0 1810p_state_clk_gate_bins=20 1811p_state_clk_gate_max=1000000000000 1812p_state_clk_gate_min=1000 1813power_model=Null 1814sequential_access=false 1815size=32768 1816tag_latency=2 1817 1818[system.cpu2.interrupts] 1819type=SparcInterrupts 1820eventq_index=0 1821 1822[system.cpu2.isa] 1823type=SparcISA 1824eventq_index=0 1825 1826[system.cpu2.itb] 1827type=SparcTLB 1828eventq_index=0 1829size=64 1830 1831[system.cpu2.tracer] 1832type=ExeTracer 1833eventq_index=0 1834 1835[system.cpu3] 1836type=DerivO3CPU 1837children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1838LFSTSize=1024 1839LQEntries=32 1840LSQCheckLoads=true 1841LSQDepCheckShift=4 1842SQEntries=32 1843SSITSize=1024 1844activity=0 1845backComSize=5 1846branchPred=system.cpu3.branchPred
1843cachePorts=200	1847cacheStorePorts=200
1844checker=Null 1845clk_domain=system.cpu_clk_domain 1846commitToDecodeDelay=1 1847commitToFetchDelay=1 1848commitToIEWDelay=1 1849commitToRenameDelay=1 1850commitWidth=8 1851cpu_id=3 1852decodeToFetchDelay=1 1853decodeToRenameDelay=1 1854decodeWidth=8 1855default_p_state=UNDEFINED 1856dispatchWidth=8 1857do_checkpoint_insts=true 1858do_quiesce=true 1859do_statistics_insts=true 1860dtb=system.cpu3.dtb 1861eventq_index=0 1862fetchBufferSize=64 1863fetchQueueSize=32 1864fetchToDecodeDelay=1 1865fetchTrapLatency=1 1866fetchWidth=8 1867forwardComSize=5 1868fuPool=system.cpu3.fuPool 1869function_trace=false 1870function_trace_start=0 1871iewToCommitDelay=1 1872iewToDecodeDelay=1 1873iewToFetchDelay=1 1874iewToRenameDelay=1 1875interrupts=system.cpu3.interrupts 1876isa=system.cpu3.isa 1877issueToExecuteDelay=1 1878issueWidth=8 1879itb=system.cpu3.itb 1880max_insts_all_threads=0 1881max_insts_any_thread=0 1882max_loads_all_threads=0 1883max_loads_any_thread=0 1884needsTSO=false 1885numIQEntries=64 1886numPhysCCRegs=0 1887numPhysFloatRegs=256 1888numPhysIntRegs=256 1889numROBEntries=192 1890numRobs=1 1891numThreads=1 1892p_state_clk_gate_bins=20 1893p_state_clk_gate_max=1000000000000 1894p_state_clk_gate_min=1000 1895power_model=Null 1896profile=0 1897progress_interval=0 1898renameToDecodeDelay=1 1899renameToFetchDelay=1 1900renameToIEWDelay=2 1901renameToROBDelay=1 1902renameWidth=8 1903simpoint_start_insts= 1904smtCommitPolicy=RoundRobin 1905smtFetchPolicy=SingleThread 1906smtIQPolicy=Partitioned 1907smtIQThreshold=100 1908smtLSQPolicy=Partitioned 1909smtLSQThreshold=100 1910smtNumFetchingThreads=1 1911smtROBPolicy=Partitioned 1912smtROBThreshold=100 1913socket_id=0 1914squashWidth=8 1915store_set_clear_period=250000 1916switched_out=false	1848checker=Null 1849clk_domain=system.cpu_clk_domain 1850commitToDecodeDelay=1 1851commitToFetchDelay=1 1852commitToIEWDelay=1 1853commitToRenameDelay=1 1854commitWidth=8 1855cpu_id=3 1856decodeToFetchDelay=1 1857decodeToRenameDelay=1 1858decodeWidth=8 1859default_p_state=UNDEFINED 1860dispatchWidth=8 1861do_checkpoint_insts=true 1862do_quiesce=true 1863do_statistics_insts=true 1864dtb=system.cpu3.dtb 1865eventq_index=0 1866fetchBufferSize=64 1867fetchQueueSize=32 1868fetchToDecodeDelay=1 1869fetchTrapLatency=1 1870fetchWidth=8 1871forwardComSize=5 1872fuPool=system.cpu3.fuPool 1873function_trace=false 1874function_trace_start=0 1875iewToCommitDelay=1 1876iewToDecodeDelay=1 1877iewToFetchDelay=1 1878iewToRenameDelay=1 1879interrupts=system.cpu3.interrupts 1880isa=system.cpu3.isa 1881issueToExecuteDelay=1 1882issueWidth=8 1883itb=system.cpu3.itb 1884max_insts_all_threads=0 1885max_insts_any_thread=0 1886max_loads_all_threads=0 1887max_loads_any_thread=0 1888needsTSO=false 1889numIQEntries=64 1890numPhysCCRegs=0 1891numPhysFloatRegs=256 1892numPhysIntRegs=256 1893numROBEntries=192 1894numRobs=1 1895numThreads=1 1896p_state_clk_gate_bins=20 1897p_state_clk_gate_max=1000000000000 1898p_state_clk_gate_min=1000 1899power_model=Null 1900profile=0 1901progress_interval=0 1902renameToDecodeDelay=1 1903renameToFetchDelay=1 1904renameToIEWDelay=2 1905renameToROBDelay=1 1906renameWidth=8 1907simpoint_start_insts= 1908smtCommitPolicy=RoundRobin 1909smtFetchPolicy=SingleThread 1910smtIQPolicy=Partitioned 1911smtIQThreshold=100 1912smtLSQPolicy=Partitioned 1913smtLSQThreshold=100 1914smtNumFetchingThreads=1 1915smtROBPolicy=Partitioned 1916smtROBThreshold=100 1917socket_id=0 1918squashWidth=8 1919store_set_clear_period=250000 1920switched_out=false
	1921syscallRetryLatency=10000
1917system=system 1918tracer=system.cpu3.tracer 1919trapLatency=13 1920wbWidth=8 1921workload=system.cpu0.workload 1922dcache_port=system.cpu3.dcache.cpu_side 1923icache_port=system.cpu3.icache.cpu_side 1924 1925[system.cpu3.branchPred] 1926type=TournamentBP 1927BTBEntries=4096 1928BTBTagSize=16 1929RASSize=16 1930choiceCtrBits=2 1931choicePredictorSize=8192 1932eventq_index=0 1933globalCtrBits=2 1934globalPredictorSize=8192 1935indirectHashGHR=true 1936indirectHashTargets=true 1937indirectPathLength=3 1938indirectSets=256 1939indirectTagSize=16 1940indirectWays=2 1941instShiftAmt=2 1942localCtrBits=2 1943localHistoryTableSize=2048 1944localPredictorSize=2048 1945numThreads=1 1946useIndirect=true 1947 1948[system.cpu3.dcache] 1949type=Cache 1950children=tags 1951addr_ranges=0:18446744073709551615:0:0:0:0 1952assoc=4 1953clk_domain=system.cpu_clk_domain 1954clusivity=mostly_incl 1955data_latency=2 1956default_p_state=UNDEFINED 1957demand_mshr_reserve=1 1958eventq_index=0 1959is_read_only=false 1960max_miss_count=0 1961mshrs=4 1962p_state_clk_gate_bins=20 1963p_state_clk_gate_max=1000000000000 1964p_state_clk_gate_min=1000 1965power_model=Null 1966prefetch_on_access=false 1967prefetcher=Null 1968response_latency=2 1969sequential_access=false 1970size=32768 1971system=system 1972tag_latency=2 1973tags=system.cpu3.dcache.tags 1974tgts_per_mshr=20 1975write_buffers=8 1976writeback_clean=false 1977cpu_side=system.cpu3.dcache_port 1978mem_side=system.toL2Bus.slave[7] 1979 1980[system.cpu3.dcache.tags] 1981type=LRU 1982assoc=4 1983block_size=64 1984clk_domain=system.cpu_clk_domain 1985data_latency=2 1986default_p_state=UNDEFINED 1987eventq_index=0 1988p_state_clk_gate_bins=20 1989p_state_clk_gate_max=1000000000000 1990p_state_clk_gate_min=1000 1991power_model=Null 1992sequential_access=false 1993size=32768 1994tag_latency=2 1995 1996[system.cpu3.dtb] 1997type=SparcTLB 1998eventq_index=0 1999size=64 2000 2001[system.cpu3.fuPool] 2002type=FUPool 2003children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 2004FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 2005eventq_index=0 2006 2007[system.cpu3.fuPool.FUList0] 2008type=FUDesc 2009children=opList 2010count=6 2011eventq_index=0 2012opList=system.cpu3.fuPool.FUList0.opList 2013 2014[system.cpu3.fuPool.FUList0.opList] 2015type=OpDesc 2016eventq_index=0 2017opClass=IntAlu 2018opLat=1 2019pipelined=true 2020 2021[system.cpu3.fuPool.FUList1] 2022type=FUDesc 2023children=opList0 opList1 2024count=2 2025eventq_index=0 2026opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 2027 2028[system.cpu3.fuPool.FUList1.opList0] 2029type=OpDesc 2030eventq_index=0 2031opClass=IntMult 2032opLat=3 2033pipelined=true 2034 2035[system.cpu3.fuPool.FUList1.opList1] 2036type=OpDesc 2037eventq_index=0 2038opClass=IntDiv 2039opLat=20 2040pipelined=false 2041 2042[system.cpu3.fuPool.FUList2] 2043type=FUDesc 2044children=opList0 opList1 opList2 2045count=4 2046eventq_index=0 2047opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 2048 2049[system.cpu3.fuPool.FUList2.opList0] 2050type=OpDesc 2051eventq_index=0 2052opClass=FloatAdd 2053opLat=2 2054pipelined=true 2055 2056[system.cpu3.fuPool.FUList2.opList1] 2057type=OpDesc 2058eventq_index=0 2059opClass=FloatCmp 2060opLat=2 2061pipelined=true 2062 2063[system.cpu3.fuPool.FUList2.opList2] 2064type=OpDesc 2065eventq_index=0 2066opClass=FloatCvt 2067opLat=2 2068pipelined=true 2069 2070[system.cpu3.fuPool.FUList3] 2071type=FUDesc 2072children=opList0 opList1 opList2 opList3 opList4 2073count=2 2074eventq_index=0 2075opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 system.cpu3.fuPool.FUList3.opList3 system.cpu3.fuPool.FUList3.opList4 2076 2077[system.cpu3.fuPool.FUList3.opList0] 2078type=OpDesc 2079eventq_index=0 2080opClass=FloatMult 2081opLat=4 2082pipelined=true 2083 2084[system.cpu3.fuPool.FUList3.opList1] 2085type=OpDesc 2086eventq_index=0 2087opClass=FloatMultAcc 2088opLat=5 2089pipelined=true 2090 2091[system.cpu3.fuPool.FUList3.opList2] 2092type=OpDesc 2093eventq_index=0 2094opClass=FloatMisc 2095opLat=3 2096pipelined=true 2097 2098[system.cpu3.fuPool.FUList3.opList3] 2099type=OpDesc 2100eventq_index=0 2101opClass=FloatDiv 2102opLat=12 2103pipelined=false 2104 2105[system.cpu3.fuPool.FUList3.opList4] 2106type=OpDesc 2107eventq_index=0 2108opClass=FloatSqrt 2109opLat=24 2110pipelined=false 2111 2112[system.cpu3.fuPool.FUList4] 2113type=FUDesc 2114children=opList0 opList1 2115count=0 2116eventq_index=0 2117opList=system.cpu3.fuPool.FUList4.opList0 system.cpu3.fuPool.FUList4.opList1 2118 2119[system.cpu3.fuPool.FUList4.opList0] 2120type=OpDesc 2121eventq_index=0 2122opClass=MemRead 2123opLat=1 2124pipelined=true 2125 2126[system.cpu3.fuPool.FUList4.opList1] 2127type=OpDesc 2128eventq_index=0 2129opClass=FloatMemRead 2130opLat=1 2131pipelined=true 2132 2133[system.cpu3.fuPool.FUList5] 2134type=FUDesc 2135children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 2136count=4 2137eventq_index=0 2138opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 2139 2140[system.cpu3.fuPool.FUList5.opList00] 2141type=OpDesc 2142eventq_index=0 2143opClass=SimdAdd 2144opLat=1 2145pipelined=true 2146 2147[system.cpu3.fuPool.FUList5.opList01] 2148type=OpDesc 2149eventq_index=0 2150opClass=SimdAddAcc 2151opLat=1 2152pipelined=true 2153 2154[system.cpu3.fuPool.FUList5.opList02] 2155type=OpDesc 2156eventq_index=0 2157opClass=SimdAlu 2158opLat=1 2159pipelined=true 2160 2161[system.cpu3.fuPool.FUList5.opList03] 2162type=OpDesc 2163eventq_index=0 2164opClass=SimdCmp 2165opLat=1 2166pipelined=true 2167 2168[system.cpu3.fuPool.FUList5.opList04] 2169type=OpDesc 2170eventq_index=0 2171opClass=SimdCvt 2172opLat=1 2173pipelined=true 2174 2175[system.cpu3.fuPool.FUList5.opList05] 2176type=OpDesc 2177eventq_index=0 2178opClass=SimdMisc 2179opLat=1 2180pipelined=true 2181 2182[system.cpu3.fuPool.FUList5.opList06] 2183type=OpDesc 2184eventq_index=0 2185opClass=SimdMult 2186opLat=1 2187pipelined=true 2188 2189[system.cpu3.fuPool.FUList5.opList07] 2190type=OpDesc 2191eventq_index=0 2192opClass=SimdMultAcc 2193opLat=1 2194pipelined=true 2195 2196[system.cpu3.fuPool.FUList5.opList08] 2197type=OpDesc 2198eventq_index=0 2199opClass=SimdShift 2200opLat=1 2201pipelined=true 2202 2203[system.cpu3.fuPool.FUList5.opList09] 2204type=OpDesc 2205eventq_index=0 2206opClass=SimdShiftAcc 2207opLat=1 2208pipelined=true 2209 2210[system.cpu3.fuPool.FUList5.opList10] 2211type=OpDesc 2212eventq_index=0 2213opClass=SimdSqrt 2214opLat=1 2215pipelined=true 2216 2217[system.cpu3.fuPool.FUList5.opList11] 2218type=OpDesc 2219eventq_index=0 2220opClass=SimdFloatAdd 2221opLat=1 2222pipelined=true 2223 2224[system.cpu3.fuPool.FUList5.opList12] 2225type=OpDesc 2226eventq_index=0 2227opClass=SimdFloatAlu 2228opLat=1 2229pipelined=true 2230 2231[system.cpu3.fuPool.FUList5.opList13] 2232type=OpDesc 2233eventq_index=0 2234opClass=SimdFloatCmp 2235opLat=1 2236pipelined=true 2237 2238[system.cpu3.fuPool.FUList5.opList14] 2239type=OpDesc 2240eventq_index=0 2241opClass=SimdFloatCvt 2242opLat=1 2243pipelined=true 2244 2245[system.cpu3.fuPool.FUList5.opList15] 2246type=OpDesc 2247eventq_index=0 2248opClass=SimdFloatDiv 2249opLat=1 2250pipelined=true 2251 2252[system.cpu3.fuPool.FUList5.opList16] 2253type=OpDesc 2254eventq_index=0 2255opClass=SimdFloatMisc 2256opLat=1 2257pipelined=true 2258 2259[system.cpu3.fuPool.FUList5.opList17] 2260type=OpDesc 2261eventq_index=0 2262opClass=SimdFloatMult 2263opLat=1 2264pipelined=true 2265 2266[system.cpu3.fuPool.FUList5.opList18] 2267type=OpDesc 2268eventq_index=0 2269opClass=SimdFloatMultAcc 2270opLat=1 2271pipelined=true 2272 2273[system.cpu3.fuPool.FUList5.opList19] 2274type=OpDesc 2275eventq_index=0 2276opClass=SimdFloatSqrt 2277opLat=1 2278pipelined=true 2279 2280[system.cpu3.fuPool.FUList6] 2281type=FUDesc 2282children=opList0 opList1 2283count=0 2284eventq_index=0 2285opList=system.cpu3.fuPool.FUList6.opList0 system.cpu3.fuPool.FUList6.opList1 2286 2287[system.cpu3.fuPool.FUList6.opList0] 2288type=OpDesc 2289eventq_index=0 2290opClass=MemWrite 2291opLat=1 2292pipelined=true 2293 2294[system.cpu3.fuPool.FUList6.opList1] 2295type=OpDesc 2296eventq_index=0 2297opClass=FloatMemWrite 2298opLat=1 2299pipelined=true 2300 2301[system.cpu3.fuPool.FUList7] 2302type=FUDesc 2303children=opList0 opList1 opList2 opList3 2304count=4 2305eventq_index=0 2306opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 system.cpu3.fuPool.FUList7.opList2 system.cpu3.fuPool.FUList7.opList3 2307 2308[system.cpu3.fuPool.FUList7.opList0] 2309type=OpDesc 2310eventq_index=0 2311opClass=MemRead 2312opLat=1 2313pipelined=true 2314 2315[system.cpu3.fuPool.FUList7.opList1] 2316type=OpDesc 2317eventq_index=0 2318opClass=MemWrite 2319opLat=1 2320pipelined=true 2321 2322[system.cpu3.fuPool.FUList7.opList2] 2323type=OpDesc 2324eventq_index=0 2325opClass=FloatMemRead 2326opLat=1 2327pipelined=true 2328 2329[system.cpu3.fuPool.FUList7.opList3] 2330type=OpDesc 2331eventq_index=0 2332opClass=FloatMemWrite 2333opLat=1 2334pipelined=true 2335 2336[system.cpu3.fuPool.FUList8] 2337type=FUDesc 2338children=opList 2339count=1 2340eventq_index=0 2341opList=system.cpu3.fuPool.FUList8.opList 2342 2343[system.cpu3.fuPool.FUList8.opList] 2344type=OpDesc 2345eventq_index=0 2346opClass=IprAccess 2347opLat=3 2348pipelined=false 2349 2350[system.cpu3.icache] 2351type=Cache 2352children=tags 2353addr_ranges=0:18446744073709551615:0:0:0:0 2354assoc=1 2355clk_domain=system.cpu_clk_domain 2356clusivity=mostly_incl 2357data_latency=2 2358default_p_state=UNDEFINED 2359demand_mshr_reserve=1 2360eventq_index=0 2361is_read_only=true 2362max_miss_count=0 2363mshrs=4 2364p_state_clk_gate_bins=20 2365p_state_clk_gate_max=1000000000000 2366p_state_clk_gate_min=1000 2367power_model=Null 2368prefetch_on_access=false 2369prefetcher=Null 2370response_latency=2 2371sequential_access=false 2372size=32768 2373system=system 2374tag_latency=2 2375tags=system.cpu3.icache.tags 2376tgts_per_mshr=20 2377write_buffers=8 2378writeback_clean=true 2379cpu_side=system.cpu3.icache_port 2380mem_side=system.toL2Bus.slave[6] 2381 2382[system.cpu3.icache.tags] 2383type=LRU 2384assoc=1 2385block_size=64 2386clk_domain=system.cpu_clk_domain 2387data_latency=2 2388default_p_state=UNDEFINED 2389eventq_index=0 2390p_state_clk_gate_bins=20 2391p_state_clk_gate_max=1000000000000 2392p_state_clk_gate_min=1000 2393power_model=Null 2394sequential_access=false 2395size=32768 2396tag_latency=2 2397 2398[system.cpu3.interrupts] 2399type=SparcInterrupts 2400eventq_index=0 2401 2402[system.cpu3.isa] 2403type=SparcISA 2404eventq_index=0 2405 2406[system.cpu3.itb] 2407type=SparcTLB 2408eventq_index=0 2409size=64 2410 2411[system.cpu3.tracer] 2412type=ExeTracer 2413eventq_index=0 2414 2415[system.cpu_clk_domain] 2416type=SrcClockDomain 2417clock=500 2418domain_id=-1 2419eventq_index=0 2420init_perf_level=0 2421voltage_domain=system.voltage_domain 2422 2423[system.dvfs_handler] 2424type=DVFSHandler 2425domains= 2426enable=false 2427eventq_index=0 2428sys_clk_domain=system.clk_domain 2429transition_latency=100000000 2430 2431[system.l2c] 2432type=Cache 2433children=tags 2434addr_ranges=0:18446744073709551615:0:0:0:0 2435assoc=8 2436clk_domain=system.cpu_clk_domain 2437clusivity=mostly_incl 2438data_latency=20 2439default_p_state=UNDEFINED 2440demand_mshr_reserve=1 2441eventq_index=0 2442is_read_only=false 2443max_miss_count=0 2444mshrs=20 2445p_state_clk_gate_bins=20 2446p_state_clk_gate_max=1000000000000 2447p_state_clk_gate_min=1000 2448power_model=Null 2449prefetch_on_access=false 2450prefetcher=Null 2451response_latency=20 2452sequential_access=false 2453size=4194304 2454system=system 2455tag_latency=20 2456tags=system.l2c.tags 2457tgts_per_mshr=12 2458write_buffers=8 2459writeback_clean=false 2460cpu_side=system.toL2Bus.master[0] 2461mem_side=system.membus.slave[1] 2462 2463[system.l2c.tags] 2464type=LRU 2465assoc=8 2466block_size=64 2467clk_domain=system.cpu_clk_domain 2468data_latency=20 2469default_p_state=UNDEFINED 2470eventq_index=0 2471p_state_clk_gate_bins=20 2472p_state_clk_gate_max=1000000000000 2473p_state_clk_gate_min=1000 2474power_model=Null 2475sequential_access=false 2476size=4194304 2477tag_latency=20 2478 2479[system.membus] 2480type=CoherentXBar 2481children=snoop_filter 2482clk_domain=system.clk_domain 2483default_p_state=UNDEFINED 2484eventq_index=0 2485forward_latency=4 2486frontend_latency=3 2487p_state_clk_gate_bins=20 2488p_state_clk_gate_max=1000000000000 2489p_state_clk_gate_min=1000 2490point_of_coherency=true 2491power_model=Null 2492response_latency=2 2493snoop_filter=system.membus.snoop_filter 2494snoop_response_latency=4 2495system=system 2496use_default_range=false 2497width=16 2498master=system.physmem.port 2499slave=system.system_port system.l2c.mem_side 2500 2501[system.membus.snoop_filter] 2502type=SnoopFilter 2503eventq_index=0 2504lookup_latency=1 2505max_capacity=8388608 2506system=system 2507 2508[system.physmem] 2509type=DRAMCtrl 2510IDD0=0.055000 2511IDD02=0.000000 2512IDD2N=0.032000 2513IDD2N2=0.000000 2514IDD2P0=0.000000 2515IDD2P02=0.000000 2516IDD2P1=0.032000 2517IDD2P12=0.000000 2518IDD3N=0.038000 2519IDD3N2=0.000000 2520IDD3P0=0.000000 2521IDD3P02=0.000000 2522IDD3P1=0.038000 2523IDD3P12=0.000000 2524IDD4R=0.157000 2525IDD4R2=0.000000 2526IDD4W=0.125000 2527IDD4W2=0.000000 2528IDD5=0.235000 2529IDD52=0.000000 2530IDD6=0.020000 2531IDD62=0.000000 2532VDD=1.500000 2533VDD2=0.000000 2534activation_limit=4 2535addr_mapping=RoRaBaCoCh 2536bank_groups_per_rank=0 2537banks_per_rank=8 2538burst_length=8 2539channels=1 2540clk_domain=system.clk_domain 2541conf_table_reported=true 2542default_p_state=UNDEFINED 2543device_bus_width=8 2544device_rowbuffer_size=1024 2545device_size=536870912 2546devices_per_rank=8 2547dll=true 2548eventq_index=0 2549in_addr_map=true 2550kvm_map=true 2551max_accesses_per_row=16 2552mem_sched_policy=frfcfs 2553min_writes_per_switch=16 2554null=false 2555p_state_clk_gate_bins=20 2556p_state_clk_gate_max=1000000000000 2557p_state_clk_gate_min=1000 2558page_policy=open_adaptive 2559power_model=Null 2560range=0:134217727:0:0:0:0 2561ranks_per_channel=2 2562read_buffer_size=32 2563static_backend_latency=10000 2564static_frontend_latency=10000 2565tBURST=5000 2566tCCD_L=0 2567tCK=1250 2568tCL=13750 2569tCS=2500 2570tRAS=35000 2571tRCD=13750 2572tREFI=7800000 2573tRFC=260000 2574tRP=13750 2575tRRD=6000 2576tRRD_L=0 2577tRTP=7500 2578tRTW=2500 2579tWR=15000 2580tWTR=7500 2581tXAW=30000 2582tXP=6000 2583tXPDLL=0 2584tXS=270000 2585tXSDLL=0 2586write_buffer_size=64 2587write_high_thresh_perc=85 2588write_low_thresh_perc=50 2589port=system.membus.master[0] 2590 2591[system.toL2Bus] 2592type=CoherentXBar 2593children=snoop_filter 2594clk_domain=system.cpu_clk_domain 2595default_p_state=UNDEFINED 2596eventq_index=0 2597forward_latency=0 2598frontend_latency=1 2599p_state_clk_gate_bins=20 2600p_state_clk_gate_max=1000000000000 2601p_state_clk_gate_min=1000 2602point_of_coherency=false 2603power_model=Null 2604response_latency=1 2605snoop_filter=system.toL2Bus.snoop_filter 2606snoop_response_latency=1 2607system=system 2608use_default_range=false 2609width=32 2610master=system.l2c.cpu_side 2611slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 2612 2613[system.toL2Bus.snoop_filter] 2614type=SnoopFilter 2615eventq_index=0 2616lookup_latency=0 2617max_capacity=8388608 2618system=system 2619 2620[system.voltage_domain] 2621type=VoltageDomain 2622eventq_index=0 2623voltage=1.000000 2624	1922system=system 1923tracer=system.cpu3.tracer 1924trapLatency=13 1925wbWidth=8 1926workload=system.cpu0.workload 1927dcache_port=system.cpu3.dcache.cpu_side 1928icache_port=system.cpu3.icache.cpu_side 1929 1930[system.cpu3.branchPred] 1931type=TournamentBP 1932BTBEntries=4096 1933BTBTagSize=16 1934RASSize=16 1935choiceCtrBits=2 1936choicePredictorSize=8192 1937eventq_index=0 1938globalCtrBits=2 1939globalPredictorSize=8192 1940indirectHashGHR=true 1941indirectHashTargets=true 1942indirectPathLength=3 1943indirectSets=256 1944indirectTagSize=16 1945indirectWays=2 1946instShiftAmt=2 1947localCtrBits=2 1948localHistoryTableSize=2048 1949localPredictorSize=2048 1950numThreads=1 1951useIndirect=true 1952 1953[system.cpu3.dcache] 1954type=Cache 1955children=tags 1956addr_ranges=0:18446744073709551615:0:0:0:0 1957assoc=4 1958clk_domain=system.cpu_clk_domain 1959clusivity=mostly_incl 1960data_latency=2 1961default_p_state=UNDEFINED 1962demand_mshr_reserve=1 1963eventq_index=0 1964is_read_only=false 1965max_miss_count=0 1966mshrs=4 1967p_state_clk_gate_bins=20 1968p_state_clk_gate_max=1000000000000 1969p_state_clk_gate_min=1000 1970power_model=Null 1971prefetch_on_access=false 1972prefetcher=Null 1973response_latency=2 1974sequential_access=false 1975size=32768 1976system=system 1977tag_latency=2 1978tags=system.cpu3.dcache.tags 1979tgts_per_mshr=20 1980write_buffers=8 1981writeback_clean=false 1982cpu_side=system.cpu3.dcache_port 1983mem_side=system.toL2Bus.slave[7] 1984 1985[system.cpu3.dcache.tags] 1986type=LRU 1987assoc=4 1988block_size=64 1989clk_domain=system.cpu_clk_domain 1990data_latency=2 1991default_p_state=UNDEFINED 1992eventq_index=0 1993p_state_clk_gate_bins=20 1994p_state_clk_gate_max=1000000000000 1995p_state_clk_gate_min=1000 1996power_model=Null 1997sequential_access=false 1998size=32768 1999tag_latency=2 2000 2001[system.cpu3.dtb] 2002type=SparcTLB 2003eventq_index=0 2004size=64 2005 2006[system.cpu3.fuPool] 2007type=FUPool 2008children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 2009FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 2010eventq_index=0 2011 2012[system.cpu3.fuPool.FUList0] 2013type=FUDesc 2014children=opList 2015count=6 2016eventq_index=0 2017opList=system.cpu3.fuPool.FUList0.opList 2018 2019[system.cpu3.fuPool.FUList0.opList] 2020type=OpDesc 2021eventq_index=0 2022opClass=IntAlu 2023opLat=1 2024pipelined=true 2025 2026[system.cpu3.fuPool.FUList1] 2027type=FUDesc 2028children=opList0 opList1 2029count=2 2030eventq_index=0 2031opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 2032 2033[system.cpu3.fuPool.FUList1.opList0] 2034type=OpDesc 2035eventq_index=0 2036opClass=IntMult 2037opLat=3 2038pipelined=true 2039 2040[system.cpu3.fuPool.FUList1.opList1] 2041type=OpDesc 2042eventq_index=0 2043opClass=IntDiv 2044opLat=20 2045pipelined=false 2046 2047[system.cpu3.fuPool.FUList2] 2048type=FUDesc 2049children=opList0 opList1 opList2 2050count=4 2051eventq_index=0 2052opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 2053 2054[system.cpu3.fuPool.FUList2.opList0] 2055type=OpDesc 2056eventq_index=0 2057opClass=FloatAdd 2058opLat=2 2059pipelined=true 2060 2061[system.cpu3.fuPool.FUList2.opList1] 2062type=OpDesc 2063eventq_index=0 2064opClass=FloatCmp 2065opLat=2 2066pipelined=true 2067 2068[system.cpu3.fuPool.FUList2.opList2] 2069type=OpDesc 2070eventq_index=0 2071opClass=FloatCvt 2072opLat=2 2073pipelined=true 2074 2075[system.cpu3.fuPool.FUList3] 2076type=FUDesc 2077children=opList0 opList1 opList2 opList3 opList4 2078count=2 2079eventq_index=0 2080opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 system.cpu3.fuPool.FUList3.opList3 system.cpu3.fuPool.FUList3.opList4 2081 2082[system.cpu3.fuPool.FUList3.opList0] 2083type=OpDesc 2084eventq_index=0 2085opClass=FloatMult 2086opLat=4 2087pipelined=true 2088 2089[system.cpu3.fuPool.FUList3.opList1] 2090type=OpDesc 2091eventq_index=0 2092opClass=FloatMultAcc 2093opLat=5 2094pipelined=true 2095 2096[system.cpu3.fuPool.FUList3.opList2] 2097type=OpDesc 2098eventq_index=0 2099opClass=FloatMisc 2100opLat=3 2101pipelined=true 2102 2103[system.cpu3.fuPool.FUList3.opList3] 2104type=OpDesc 2105eventq_index=0 2106opClass=FloatDiv 2107opLat=12 2108pipelined=false 2109 2110[system.cpu3.fuPool.FUList3.opList4] 2111type=OpDesc 2112eventq_index=0 2113opClass=FloatSqrt 2114opLat=24 2115pipelined=false 2116 2117[system.cpu3.fuPool.FUList4] 2118type=FUDesc 2119children=opList0 opList1 2120count=0 2121eventq_index=0 2122opList=system.cpu3.fuPool.FUList4.opList0 system.cpu3.fuPool.FUList4.opList1 2123 2124[system.cpu3.fuPool.FUList4.opList0] 2125type=OpDesc 2126eventq_index=0 2127opClass=MemRead 2128opLat=1 2129pipelined=true 2130 2131[system.cpu3.fuPool.FUList4.opList1] 2132type=OpDesc 2133eventq_index=0 2134opClass=FloatMemRead 2135opLat=1 2136pipelined=true 2137 2138[system.cpu3.fuPool.FUList5] 2139type=FUDesc 2140children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 2141count=4 2142eventq_index=0 2143opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 2144 2145[system.cpu3.fuPool.FUList5.opList00] 2146type=OpDesc 2147eventq_index=0 2148opClass=SimdAdd 2149opLat=1 2150pipelined=true 2151 2152[system.cpu3.fuPool.FUList5.opList01] 2153type=OpDesc 2154eventq_index=0 2155opClass=SimdAddAcc 2156opLat=1 2157pipelined=true 2158 2159[system.cpu3.fuPool.FUList5.opList02] 2160type=OpDesc 2161eventq_index=0 2162opClass=SimdAlu 2163opLat=1 2164pipelined=true 2165 2166[system.cpu3.fuPool.FUList5.opList03] 2167type=OpDesc 2168eventq_index=0 2169opClass=SimdCmp 2170opLat=1 2171pipelined=true 2172 2173[system.cpu3.fuPool.FUList5.opList04] 2174type=OpDesc 2175eventq_index=0 2176opClass=SimdCvt 2177opLat=1 2178pipelined=true 2179 2180[system.cpu3.fuPool.FUList5.opList05] 2181type=OpDesc 2182eventq_index=0 2183opClass=SimdMisc 2184opLat=1 2185pipelined=true 2186 2187[system.cpu3.fuPool.FUList5.opList06] 2188type=OpDesc 2189eventq_index=0 2190opClass=SimdMult 2191opLat=1 2192pipelined=true 2193 2194[system.cpu3.fuPool.FUList5.opList07] 2195type=OpDesc 2196eventq_index=0 2197opClass=SimdMultAcc 2198opLat=1 2199pipelined=true 2200 2201[system.cpu3.fuPool.FUList5.opList08] 2202type=OpDesc 2203eventq_index=0 2204opClass=SimdShift 2205opLat=1 2206pipelined=true 2207 2208[system.cpu3.fuPool.FUList5.opList09] 2209type=OpDesc 2210eventq_index=0 2211opClass=SimdShiftAcc 2212opLat=1 2213pipelined=true 2214 2215[system.cpu3.fuPool.FUList5.opList10] 2216type=OpDesc 2217eventq_index=0 2218opClass=SimdSqrt 2219opLat=1 2220pipelined=true 2221 2222[system.cpu3.fuPool.FUList5.opList11] 2223type=OpDesc 2224eventq_index=0 2225opClass=SimdFloatAdd 2226opLat=1 2227pipelined=true 2228 2229[system.cpu3.fuPool.FUList5.opList12] 2230type=OpDesc 2231eventq_index=0 2232opClass=SimdFloatAlu 2233opLat=1 2234pipelined=true 2235 2236[system.cpu3.fuPool.FUList5.opList13] 2237type=OpDesc 2238eventq_index=0 2239opClass=SimdFloatCmp 2240opLat=1 2241pipelined=true 2242 2243[system.cpu3.fuPool.FUList5.opList14] 2244type=OpDesc 2245eventq_index=0 2246opClass=SimdFloatCvt 2247opLat=1 2248pipelined=true 2249 2250[system.cpu3.fuPool.FUList5.opList15] 2251type=OpDesc 2252eventq_index=0 2253opClass=SimdFloatDiv 2254opLat=1 2255pipelined=true 2256 2257[system.cpu3.fuPool.FUList5.opList16] 2258type=OpDesc 2259eventq_index=0 2260opClass=SimdFloatMisc 2261opLat=1 2262pipelined=true 2263 2264[system.cpu3.fuPool.FUList5.opList17] 2265type=OpDesc 2266eventq_index=0 2267opClass=SimdFloatMult 2268opLat=1 2269pipelined=true 2270 2271[system.cpu3.fuPool.FUList5.opList18] 2272type=OpDesc 2273eventq_index=0 2274opClass=SimdFloatMultAcc 2275opLat=1 2276pipelined=true 2277 2278[system.cpu3.fuPool.FUList5.opList19] 2279type=OpDesc 2280eventq_index=0 2281opClass=SimdFloatSqrt 2282opLat=1 2283pipelined=true 2284 2285[system.cpu3.fuPool.FUList6] 2286type=FUDesc 2287children=opList0 opList1 2288count=0 2289eventq_index=0 2290opList=system.cpu3.fuPool.FUList6.opList0 system.cpu3.fuPool.FUList6.opList1 2291 2292[system.cpu3.fuPool.FUList6.opList0] 2293type=OpDesc 2294eventq_index=0 2295opClass=MemWrite 2296opLat=1 2297pipelined=true 2298 2299[system.cpu3.fuPool.FUList6.opList1] 2300type=OpDesc 2301eventq_index=0 2302opClass=FloatMemWrite 2303opLat=1 2304pipelined=true 2305 2306[system.cpu3.fuPool.FUList7] 2307type=FUDesc 2308children=opList0 opList1 opList2 opList3 2309count=4 2310eventq_index=0 2311opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 system.cpu3.fuPool.FUList7.opList2 system.cpu3.fuPool.FUList7.opList3 2312 2313[system.cpu3.fuPool.FUList7.opList0] 2314type=OpDesc 2315eventq_index=0 2316opClass=MemRead 2317opLat=1 2318pipelined=true 2319 2320[system.cpu3.fuPool.FUList7.opList1] 2321type=OpDesc 2322eventq_index=0 2323opClass=MemWrite 2324opLat=1 2325pipelined=true 2326 2327[system.cpu3.fuPool.FUList7.opList2] 2328type=OpDesc 2329eventq_index=0 2330opClass=FloatMemRead 2331opLat=1 2332pipelined=true 2333 2334[system.cpu3.fuPool.FUList7.opList3] 2335type=OpDesc 2336eventq_index=0 2337opClass=FloatMemWrite 2338opLat=1 2339pipelined=true 2340 2341[system.cpu3.fuPool.FUList8] 2342type=FUDesc 2343children=opList 2344count=1 2345eventq_index=0 2346opList=system.cpu3.fuPool.FUList8.opList 2347 2348[system.cpu3.fuPool.FUList8.opList] 2349type=OpDesc 2350eventq_index=0 2351opClass=IprAccess 2352opLat=3 2353pipelined=false 2354 2355[system.cpu3.icache] 2356type=Cache 2357children=tags 2358addr_ranges=0:18446744073709551615:0:0:0:0 2359assoc=1 2360clk_domain=system.cpu_clk_domain 2361clusivity=mostly_incl 2362data_latency=2 2363default_p_state=UNDEFINED 2364demand_mshr_reserve=1 2365eventq_index=0 2366is_read_only=true 2367max_miss_count=0 2368mshrs=4 2369p_state_clk_gate_bins=20 2370p_state_clk_gate_max=1000000000000 2371p_state_clk_gate_min=1000 2372power_model=Null 2373prefetch_on_access=false 2374prefetcher=Null 2375response_latency=2 2376sequential_access=false 2377size=32768 2378system=system 2379tag_latency=2 2380tags=system.cpu3.icache.tags 2381tgts_per_mshr=20 2382write_buffers=8 2383writeback_clean=true 2384cpu_side=system.cpu3.icache_port 2385mem_side=system.toL2Bus.slave[6] 2386 2387[system.cpu3.icache.tags] 2388type=LRU 2389assoc=1 2390block_size=64 2391clk_domain=system.cpu_clk_domain 2392data_latency=2 2393default_p_state=UNDEFINED 2394eventq_index=0 2395p_state_clk_gate_bins=20 2396p_state_clk_gate_max=1000000000000 2397p_state_clk_gate_min=1000 2398power_model=Null 2399sequential_access=false 2400size=32768 2401tag_latency=2 2402 2403[system.cpu3.interrupts] 2404type=SparcInterrupts 2405eventq_index=0 2406 2407[system.cpu3.isa] 2408type=SparcISA 2409eventq_index=0 2410 2411[system.cpu3.itb] 2412type=SparcTLB 2413eventq_index=0 2414size=64 2415 2416[system.cpu3.tracer] 2417type=ExeTracer 2418eventq_index=0 2419 2420[system.cpu_clk_domain] 2421type=SrcClockDomain 2422clock=500 2423domain_id=-1 2424eventq_index=0 2425init_perf_level=0 2426voltage_domain=system.voltage_domain 2427 2428[system.dvfs_handler] 2429type=DVFSHandler 2430domains= 2431enable=false 2432eventq_index=0 2433sys_clk_domain=system.clk_domain 2434transition_latency=100000000 2435 2436[system.l2c] 2437type=Cache 2438children=tags 2439addr_ranges=0:18446744073709551615:0:0:0:0 2440assoc=8 2441clk_domain=system.cpu_clk_domain 2442clusivity=mostly_incl 2443data_latency=20 2444default_p_state=UNDEFINED 2445demand_mshr_reserve=1 2446eventq_index=0 2447is_read_only=false 2448max_miss_count=0 2449mshrs=20 2450p_state_clk_gate_bins=20 2451p_state_clk_gate_max=1000000000000 2452p_state_clk_gate_min=1000 2453power_model=Null 2454prefetch_on_access=false 2455prefetcher=Null 2456response_latency=20 2457sequential_access=false 2458size=4194304 2459system=system 2460tag_latency=20 2461tags=system.l2c.tags 2462tgts_per_mshr=12 2463write_buffers=8 2464writeback_clean=false 2465cpu_side=system.toL2Bus.master[0] 2466mem_side=system.membus.slave[1] 2467 2468[system.l2c.tags] 2469type=LRU 2470assoc=8 2471block_size=64 2472clk_domain=system.cpu_clk_domain 2473data_latency=20 2474default_p_state=UNDEFINED 2475eventq_index=0 2476p_state_clk_gate_bins=20 2477p_state_clk_gate_max=1000000000000 2478p_state_clk_gate_min=1000 2479power_model=Null 2480sequential_access=false 2481size=4194304 2482tag_latency=20 2483 2484[system.membus] 2485type=CoherentXBar 2486children=snoop_filter 2487clk_domain=system.clk_domain 2488default_p_state=UNDEFINED 2489eventq_index=0 2490forward_latency=4 2491frontend_latency=3 2492p_state_clk_gate_bins=20 2493p_state_clk_gate_max=1000000000000 2494p_state_clk_gate_min=1000 2495point_of_coherency=true 2496power_model=Null 2497response_latency=2 2498snoop_filter=system.membus.snoop_filter 2499snoop_response_latency=4 2500system=system 2501use_default_range=false 2502width=16 2503master=system.physmem.port 2504slave=system.system_port system.l2c.mem_side 2505 2506[system.membus.snoop_filter] 2507type=SnoopFilter 2508eventq_index=0 2509lookup_latency=1 2510max_capacity=8388608 2511system=system 2512 2513[system.physmem] 2514type=DRAMCtrl 2515IDD0=0.055000 2516IDD02=0.000000 2517IDD2N=0.032000 2518IDD2N2=0.000000 2519IDD2P0=0.000000 2520IDD2P02=0.000000 2521IDD2P1=0.032000 2522IDD2P12=0.000000 2523IDD3N=0.038000 2524IDD3N2=0.000000 2525IDD3P0=0.000000 2526IDD3P02=0.000000 2527IDD3P1=0.038000 2528IDD3P12=0.000000 2529IDD4R=0.157000 2530IDD4R2=0.000000 2531IDD4W=0.125000 2532IDD4W2=0.000000 2533IDD5=0.235000 2534IDD52=0.000000 2535IDD6=0.020000 2536IDD62=0.000000 2537VDD=1.500000 2538VDD2=0.000000 2539activation_limit=4 2540addr_mapping=RoRaBaCoCh 2541bank_groups_per_rank=0 2542banks_per_rank=8 2543burst_length=8 2544channels=1 2545clk_domain=system.clk_domain 2546conf_table_reported=true 2547default_p_state=UNDEFINED 2548device_bus_width=8 2549device_rowbuffer_size=1024 2550device_size=536870912 2551devices_per_rank=8 2552dll=true 2553eventq_index=0 2554in_addr_map=true 2555kvm_map=true 2556max_accesses_per_row=16 2557mem_sched_policy=frfcfs 2558min_writes_per_switch=16 2559null=false 2560p_state_clk_gate_bins=20 2561p_state_clk_gate_max=1000000000000 2562p_state_clk_gate_min=1000 2563page_policy=open_adaptive 2564power_model=Null 2565range=0:134217727:0:0:0:0 2566ranks_per_channel=2 2567read_buffer_size=32 2568static_backend_latency=10000 2569static_frontend_latency=10000 2570tBURST=5000 2571tCCD_L=0 2572tCK=1250 2573tCL=13750 2574tCS=2500 2575tRAS=35000 2576tRCD=13750 2577tREFI=7800000 2578tRFC=260000 2579tRP=13750 2580tRRD=6000 2581tRRD_L=0 2582tRTP=7500 2583tRTW=2500 2584tWR=15000 2585tWTR=7500 2586tXAW=30000 2587tXP=6000 2588tXPDLL=0 2589tXS=270000 2590tXSDLL=0 2591write_buffer_size=64 2592write_high_thresh_perc=85 2593write_low_thresh_perc=50 2594port=system.membus.master[0] 2595 2596[system.toL2Bus] 2597type=CoherentXBar 2598children=snoop_filter 2599clk_domain=system.cpu_clk_domain 2600default_p_state=UNDEFINED 2601eventq_index=0 2602forward_latency=0 2603frontend_latency=1 2604p_state_clk_gate_bins=20 2605p_state_clk_gate_max=1000000000000 2606p_state_clk_gate_min=1000 2607point_of_coherency=false 2608power_model=Null 2609response_latency=1 2610snoop_filter=system.toL2Bus.snoop_filter 2611snoop_response_latency=1 2612system=system 2613use_default_range=false 2614width=32 2615master=system.l2c.cpu_side 2616slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 2617 2618[system.toL2Bus.snoop_filter] 2619type=SnoopFilter 2620eventq_index=0 2621lookup_latency=0 2622max_capacity=8388608 2623system=system 2624 2625[system.voltage_domain] 2626type=VoltageDomain 2627eventq_index=0 2628voltage=1.000000 2629