Cross Reference: /gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini

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config.ini (11680:b4d943429dc6)	config.ini (11731:c473ca7cc650)
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51domain_id=-1 52eventq_index=0 53init_perf_level=0 54voltage_domain=system.voltage_domain 55 56[system.cpu0] 57type=DerivO3CPU 58children=branchPred dcache dtb fuPool icache interrupts isa itb tracer workload 59LFSTSize=1024 60LQEntries=32 61LSQCheckLoads=true 62LSQDepCheckShift=4 63SQEntries=32 64SSITSize=1024 65activity=0 66backComSize=5 67branchPred=system.cpu0.branchPred 68cachePorts=200 69checker=Null 70clk_domain=system.cpu_clk_domain 71commitToDecodeDelay=1 72commitToFetchDelay=1 73commitToIEWDelay=1 74commitToRenameDelay=1 75commitWidth=8 76cpu_id=0 77decodeToFetchDelay=1 78decodeToRenameDelay=1 79decodeWidth=8 80default_p_state=UNDEFINED 81dispatchWidth=8 82do_checkpoint_insts=true 83do_quiesce=true 84do_statistics_insts=true 85dtb=system.cpu0.dtb 86eventq_index=0 87fetchBufferSize=64 88fetchQueueSize=32 89fetchToDecodeDelay=1 90fetchTrapLatency=1 91fetchWidth=8 92forwardComSize=5 93fuPool=system.cpu0.fuPool 94function_trace=false 95function_trace_start=0 96iewToCommitDelay=1 97iewToDecodeDelay=1 98iewToFetchDelay=1 99iewToRenameDelay=1 100interrupts=system.cpu0.interrupts 101isa=system.cpu0.isa 102issueToExecuteDelay=1 103issueWidth=8 104itb=system.cpu0.itb 105max_insts_all_threads=0 106max_insts_any_thread=0 107max_loads_all_threads=0 108max_loads_any_thread=0 109needsTSO=false 110numIQEntries=64 111numPhysCCRegs=0 112numPhysFloatRegs=256 113numPhysIntRegs=256 114numROBEntries=192 115numRobs=1 116numThreads=1 117p_state_clk_gate_bins=20 118p_state_clk_gate_max=1000000000000 119p_state_clk_gate_min=1000 120power_model=Null 121profile=0 122progress_interval=0 123renameToDecodeDelay=1 124renameToFetchDelay=1 125renameToIEWDelay=2 126renameToROBDelay=1 127renameWidth=8 128simpoint_start_insts= 129smtCommitPolicy=RoundRobin 130smtFetchPolicy=SingleThread 131smtIQPolicy=Partitioned 132smtIQThreshold=100 133smtLSQPolicy=Partitioned 134smtLSQThreshold=100 135smtNumFetchingThreads=1 136smtROBPolicy=Partitioned 137smtROBThreshold=100 138socket_id=0 139squashWidth=8 140store_set_clear_period=250000 141switched_out=false 142system=system 143tracer=system.cpu0.tracer 144trapLatency=13 145wbWidth=8 146workload=system.cpu0.workload 147dcache_port=system.cpu0.dcache.cpu_side 148icache_port=system.cpu0.icache.cpu_side 149 150[system.cpu0.branchPred] 151type=TournamentBP 152BTBEntries=4096 153BTBTagSize=16 154RASSize=16 155choiceCtrBits=2 156choicePredictorSize=8192 157eventq_index=0 158globalCtrBits=2 159globalPredictorSize=8192 160indirectHashGHR=true 161indirectHashTargets=true 162indirectPathLength=3 163indirectSets=256 164indirectTagSize=16 165indirectWays=2 166instShiftAmt=2 167localCtrBits=2 168localHistoryTableSize=2048 169localPredictorSize=2048 170numThreads=1 171useIndirect=true 172 173[system.cpu0.dcache] 174type=Cache 175children=tags 176addr_ranges=0:18446744073709551615:0:0:0:0 177assoc=4 178clk_domain=system.cpu_clk_domain 179clusivity=mostly_incl	1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51domain_id=-1 52eventq_index=0 53init_perf_level=0 54voltage_domain=system.voltage_domain 55 56[system.cpu0] 57type=DerivO3CPU 58children=branchPred dcache dtb fuPool icache interrupts isa itb tracer workload 59LFSTSize=1024 60LQEntries=32 61LSQCheckLoads=true 62LSQDepCheckShift=4 63SQEntries=32 64SSITSize=1024 65activity=0 66backComSize=5 67branchPred=system.cpu0.branchPred 68cachePorts=200 69checker=Null 70clk_domain=system.cpu_clk_domain 71commitToDecodeDelay=1 72commitToFetchDelay=1 73commitToIEWDelay=1 74commitToRenameDelay=1 75commitWidth=8 76cpu_id=0 77decodeToFetchDelay=1 78decodeToRenameDelay=1 79decodeWidth=8 80default_p_state=UNDEFINED 81dispatchWidth=8 82do_checkpoint_insts=true 83do_quiesce=true 84do_statistics_insts=true 85dtb=system.cpu0.dtb 86eventq_index=0 87fetchBufferSize=64 88fetchQueueSize=32 89fetchToDecodeDelay=1 90fetchTrapLatency=1 91fetchWidth=8 92forwardComSize=5 93fuPool=system.cpu0.fuPool 94function_trace=false 95function_trace_start=0 96iewToCommitDelay=1 97iewToDecodeDelay=1 98iewToFetchDelay=1 99iewToRenameDelay=1 100interrupts=system.cpu0.interrupts 101isa=system.cpu0.isa 102issueToExecuteDelay=1 103issueWidth=8 104itb=system.cpu0.itb 105max_insts_all_threads=0 106max_insts_any_thread=0 107max_loads_all_threads=0 108max_loads_any_thread=0 109needsTSO=false 110numIQEntries=64 111numPhysCCRegs=0 112numPhysFloatRegs=256 113numPhysIntRegs=256 114numROBEntries=192 115numRobs=1 116numThreads=1 117p_state_clk_gate_bins=20 118p_state_clk_gate_max=1000000000000 119p_state_clk_gate_min=1000 120power_model=Null 121profile=0 122progress_interval=0 123renameToDecodeDelay=1 124renameToFetchDelay=1 125renameToIEWDelay=2 126renameToROBDelay=1 127renameWidth=8 128simpoint_start_insts= 129smtCommitPolicy=RoundRobin 130smtFetchPolicy=SingleThread 131smtIQPolicy=Partitioned 132smtIQThreshold=100 133smtLSQPolicy=Partitioned 134smtLSQThreshold=100 135smtNumFetchingThreads=1 136smtROBPolicy=Partitioned 137smtROBThreshold=100 138socket_id=0 139squashWidth=8 140store_set_clear_period=250000 141switched_out=false 142system=system 143tracer=system.cpu0.tracer 144trapLatency=13 145wbWidth=8 146workload=system.cpu0.workload 147dcache_port=system.cpu0.dcache.cpu_side 148icache_port=system.cpu0.icache.cpu_side 149 150[system.cpu0.branchPred] 151type=TournamentBP 152BTBEntries=4096 153BTBTagSize=16 154RASSize=16 155choiceCtrBits=2 156choicePredictorSize=8192 157eventq_index=0 158globalCtrBits=2 159globalPredictorSize=8192 160indirectHashGHR=true 161indirectHashTargets=true 162indirectPathLength=3 163indirectSets=256 164indirectTagSize=16 165indirectWays=2 166instShiftAmt=2 167localCtrBits=2 168localHistoryTableSize=2048 169localPredictorSize=2048 170numThreads=1 171useIndirect=true 172 173[system.cpu0.dcache] 174type=Cache 175children=tags 176addr_ranges=0:18446744073709551615:0:0:0:0 177assoc=4 178clk_domain=system.cpu_clk_domain 179clusivity=mostly_incl
	180data_latency=2
180default_p_state=UNDEFINED 181demand_mshr_reserve=1 182eventq_index=0	181default_p_state=UNDEFINED 182demand_mshr_reserve=1 183eventq_index=0
183hit_latency=2
184is_read_only=false 185max_miss_count=0 186mshrs=4 187p_state_clk_gate_bins=20 188p_state_clk_gate_max=1000000000000 189p_state_clk_gate_min=1000 190power_model=Null 191prefetch_on_access=false 192prefetcher=Null 193response_latency=2 194sequential_access=false 195size=32768 196system=system	184is_read_only=false 185max_miss_count=0 186mshrs=4 187p_state_clk_gate_bins=20 188p_state_clk_gate_max=1000000000000 189p_state_clk_gate_min=1000 190power_model=Null 191prefetch_on_access=false 192prefetcher=Null 193response_latency=2 194sequential_access=false 195size=32768 196system=system
	197tag_latency=2
197tags=system.cpu0.dcache.tags 198tgts_per_mshr=20 199write_buffers=8 200writeback_clean=false 201cpu_side=system.cpu0.dcache_port 202mem_side=system.toL2Bus.slave[1] 203 204[system.cpu0.dcache.tags] 205type=LRU 206assoc=4 207block_size=64 208clk_domain=system.cpu_clk_domain	198tags=system.cpu0.dcache.tags 199tgts_per_mshr=20 200write_buffers=8 201writeback_clean=false 202cpu_side=system.cpu0.dcache_port 203mem_side=system.toL2Bus.slave[1] 204 205[system.cpu0.dcache.tags] 206type=LRU 207assoc=4 208block_size=64 209clk_domain=system.cpu_clk_domain
	210data_latency=2
209default_p_state=UNDEFINED 210eventq_index=0	211default_p_state=UNDEFINED 212eventq_index=0
211hit_latency=2
212p_state_clk_gate_bins=20 213p_state_clk_gate_max=1000000000000 214p_state_clk_gate_min=1000 215power_model=Null 216sequential_access=false 217size=32768	213p_state_clk_gate_bins=20 214p_state_clk_gate_max=1000000000000 215p_state_clk_gate_min=1000 216power_model=Null 217sequential_access=false 218size=32768
	219tag_latency=2
218 219[system.cpu0.dtb] 220type=SparcTLB 221eventq_index=0 222size=64 223 224[system.cpu0.fuPool] 225type=FUPool 226children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 227FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 228eventq_index=0 229 230[system.cpu0.fuPool.FUList0] 231type=FUDesc 232children=opList 233count=6 234eventq_index=0 235opList=system.cpu0.fuPool.FUList0.opList 236 237[system.cpu0.fuPool.FUList0.opList] 238type=OpDesc 239eventq_index=0 240opClass=IntAlu 241opLat=1 242pipelined=true 243 244[system.cpu0.fuPool.FUList1] 245type=FUDesc 246children=opList0 opList1 247count=2 248eventq_index=0 249opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 250 251[system.cpu0.fuPool.FUList1.opList0] 252type=OpDesc 253eventq_index=0 254opClass=IntMult 255opLat=3 256pipelined=true 257 258[system.cpu0.fuPool.FUList1.opList1] 259type=OpDesc 260eventq_index=0 261opClass=IntDiv 262opLat=20 263pipelined=false 264 265[system.cpu0.fuPool.FUList2] 266type=FUDesc 267children=opList0 opList1 opList2 268count=4 269eventq_index=0 270opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 271 272[system.cpu0.fuPool.FUList2.opList0] 273type=OpDesc 274eventq_index=0 275opClass=FloatAdd 276opLat=2 277pipelined=true 278 279[system.cpu0.fuPool.FUList2.opList1] 280type=OpDesc 281eventq_index=0 282opClass=FloatCmp 283opLat=2 284pipelined=true 285 286[system.cpu0.fuPool.FUList2.opList2] 287type=OpDesc 288eventq_index=0 289opClass=FloatCvt 290opLat=2 291pipelined=true 292 293[system.cpu0.fuPool.FUList3] 294type=FUDesc	220 221[system.cpu0.dtb] 222type=SparcTLB 223eventq_index=0 224size=64 225 226[system.cpu0.fuPool] 227type=FUPool 228children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 229FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 230eventq_index=0 231 232[system.cpu0.fuPool.FUList0] 233type=FUDesc 234children=opList 235count=6 236eventq_index=0 237opList=system.cpu0.fuPool.FUList0.opList 238 239[system.cpu0.fuPool.FUList0.opList] 240type=OpDesc 241eventq_index=0 242opClass=IntAlu 243opLat=1 244pipelined=true 245 246[system.cpu0.fuPool.FUList1] 247type=FUDesc 248children=opList0 opList1 249count=2 250eventq_index=0 251opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 252 253[system.cpu0.fuPool.FUList1.opList0] 254type=OpDesc 255eventq_index=0 256opClass=IntMult 257opLat=3 258pipelined=true 259 260[system.cpu0.fuPool.FUList1.opList1] 261type=OpDesc 262eventq_index=0 263opClass=IntDiv 264opLat=20 265pipelined=false 266 267[system.cpu0.fuPool.FUList2] 268type=FUDesc 269children=opList0 opList1 opList2 270count=4 271eventq_index=0 272opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 273 274[system.cpu0.fuPool.FUList2.opList0] 275type=OpDesc 276eventq_index=0 277opClass=FloatAdd 278opLat=2 279pipelined=true 280 281[system.cpu0.fuPool.FUList2.opList1] 282type=OpDesc 283eventq_index=0 284opClass=FloatCmp 285opLat=2 286pipelined=true 287 288[system.cpu0.fuPool.FUList2.opList2] 289type=OpDesc 290eventq_index=0 291opClass=FloatCvt 292opLat=2 293pipelined=true 294 295[system.cpu0.fuPool.FUList3] 296type=FUDesc
295children=opList0 opList1 opList2	297children=opList0 opList1 opList2 opList3 opList4
296count=2 297eventq_index=0	298count=2 299eventq_index=0
298opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2	300opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 system.cpu0.fuPool.FUList3.opList3 system.cpu0.fuPool.FUList3.opList4
299 300[system.cpu0.fuPool.FUList3.opList0] 301type=OpDesc 302eventq_index=0 303opClass=FloatMult 304opLat=4 305pipelined=true 306 307[system.cpu0.fuPool.FUList3.opList1] 308type=OpDesc 309eventq_index=0	301 302[system.cpu0.fuPool.FUList3.opList0] 303type=OpDesc 304eventq_index=0 305opClass=FloatMult 306opLat=4 307pipelined=true 308 309[system.cpu0.fuPool.FUList3.opList1] 310type=OpDesc 311eventq_index=0
	312opClass=FloatMultAcc 313opLat=5 314pipelined=true 315 316[system.cpu0.fuPool.FUList3.opList2] 317type=OpDesc 318eventq_index=0 319opClass=FloatMisc 320opLat=3 321pipelined=true 322 323[system.cpu0.fuPool.FUList3.opList3] 324type=OpDesc 325eventq_index=0
310opClass=FloatDiv 311opLat=12 312pipelined=false 313	326opClass=FloatDiv 327opLat=12 328pipelined=false 329
314[system.cpu0.fuPool.FUList3.opList2]	330[system.cpu0.fuPool.FUList3.opList4]
315type=OpDesc 316eventq_index=0 317opClass=FloatSqrt 318opLat=24 319pipelined=false 320 321[system.cpu0.fuPool.FUList4] 322type=FUDesc	331type=OpDesc 332eventq_index=0 333opClass=FloatSqrt 334opLat=24 335pipelined=false 336 337[system.cpu0.fuPool.FUList4] 338type=FUDesc
323children=opList	339children=opList0 opList1
324count=0 325eventq_index=0	340count=0 341eventq_index=0
326opList=system.cpu0.fuPool.FUList4.opList	342opList=system.cpu0.fuPool.FUList4.opList0 system.cpu0.fuPool.FUList4.opList1
327	343
328[system.cpu0.fuPool.FUList4.opList]	344[system.cpu0.fuPool.FUList4.opList0]
329type=OpDesc 330eventq_index=0 331opClass=MemRead 332opLat=1 333pipelined=true 334	345type=OpDesc 346eventq_index=0 347opClass=MemRead 348opLat=1 349pipelined=true 350
	351[system.cpu0.fuPool.FUList4.opList1] 352type=OpDesc 353eventq_index=0 354opClass=FloatMemRead 355opLat=1 356pipelined=true 357
335[system.cpu0.fuPool.FUList5] 336type=FUDesc 337children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 338count=4 339eventq_index=0 340opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 341 342[system.cpu0.fuPool.FUList5.opList00] 343type=OpDesc 344eventq_index=0 345opClass=SimdAdd 346opLat=1 347pipelined=true 348 349[system.cpu0.fuPool.FUList5.opList01] 350type=OpDesc 351eventq_index=0 352opClass=SimdAddAcc 353opLat=1 354pipelined=true 355 356[system.cpu0.fuPool.FUList5.opList02] 357type=OpDesc 358eventq_index=0 359opClass=SimdAlu 360opLat=1 361pipelined=true 362 363[system.cpu0.fuPool.FUList5.opList03] 364type=OpDesc 365eventq_index=0 366opClass=SimdCmp 367opLat=1 368pipelined=true 369 370[system.cpu0.fuPool.FUList5.opList04] 371type=OpDesc 372eventq_index=0 373opClass=SimdCvt 374opLat=1 375pipelined=true 376 377[system.cpu0.fuPool.FUList5.opList05] 378type=OpDesc 379eventq_index=0 380opClass=SimdMisc 381opLat=1 382pipelined=true 383 384[system.cpu0.fuPool.FUList5.opList06] 385type=OpDesc 386eventq_index=0 387opClass=SimdMult 388opLat=1 389pipelined=true 390 391[system.cpu0.fuPool.FUList5.opList07] 392type=OpDesc 393eventq_index=0 394opClass=SimdMultAcc 395opLat=1 396pipelined=true 397 398[system.cpu0.fuPool.FUList5.opList08] 399type=OpDesc 400eventq_index=0 401opClass=SimdShift 402opLat=1 403pipelined=true 404 405[system.cpu0.fuPool.FUList5.opList09] 406type=OpDesc 407eventq_index=0 408opClass=SimdShiftAcc 409opLat=1 410pipelined=true 411 412[system.cpu0.fuPool.FUList5.opList10] 413type=OpDesc 414eventq_index=0 415opClass=SimdSqrt 416opLat=1 417pipelined=true 418 419[system.cpu0.fuPool.FUList5.opList11] 420type=OpDesc 421eventq_index=0 422opClass=SimdFloatAdd 423opLat=1 424pipelined=true 425 426[system.cpu0.fuPool.FUList5.opList12] 427type=OpDesc 428eventq_index=0 429opClass=SimdFloatAlu 430opLat=1 431pipelined=true 432 433[system.cpu0.fuPool.FUList5.opList13] 434type=OpDesc 435eventq_index=0 436opClass=SimdFloatCmp 437opLat=1 438pipelined=true 439 440[system.cpu0.fuPool.FUList5.opList14] 441type=OpDesc 442eventq_index=0 443opClass=SimdFloatCvt 444opLat=1 445pipelined=true 446 447[system.cpu0.fuPool.FUList5.opList15] 448type=OpDesc 449eventq_index=0 450opClass=SimdFloatDiv 451opLat=1 452pipelined=true 453 454[system.cpu0.fuPool.FUList5.opList16] 455type=OpDesc 456eventq_index=0 457opClass=SimdFloatMisc 458opLat=1 459pipelined=true 460 461[system.cpu0.fuPool.FUList5.opList17] 462type=OpDesc 463eventq_index=0 464opClass=SimdFloatMult 465opLat=1 466pipelined=true 467 468[system.cpu0.fuPool.FUList5.opList18] 469type=OpDesc 470eventq_index=0 471opClass=SimdFloatMultAcc 472opLat=1 473pipelined=true 474 475[system.cpu0.fuPool.FUList5.opList19] 476type=OpDesc 477eventq_index=0 478opClass=SimdFloatSqrt 479opLat=1 480pipelined=true 481 482[system.cpu0.fuPool.FUList6] 483type=FUDesc	358[system.cpu0.fuPool.FUList5] 359type=FUDesc 360children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 361count=4 362eventq_index=0 363opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 364 365[system.cpu0.fuPool.FUList5.opList00] 366type=OpDesc 367eventq_index=0 368opClass=SimdAdd 369opLat=1 370pipelined=true 371 372[system.cpu0.fuPool.FUList5.opList01] 373type=OpDesc 374eventq_index=0 375opClass=SimdAddAcc 376opLat=1 377pipelined=true 378 379[system.cpu0.fuPool.FUList5.opList02] 380type=OpDesc 381eventq_index=0 382opClass=SimdAlu 383opLat=1 384pipelined=true 385 386[system.cpu0.fuPool.FUList5.opList03] 387type=OpDesc 388eventq_index=0 389opClass=SimdCmp 390opLat=1 391pipelined=true 392 393[system.cpu0.fuPool.FUList5.opList04] 394type=OpDesc 395eventq_index=0 396opClass=SimdCvt 397opLat=1 398pipelined=true 399 400[system.cpu0.fuPool.FUList5.opList05] 401type=OpDesc 402eventq_index=0 403opClass=SimdMisc 404opLat=1 405pipelined=true 406 407[system.cpu0.fuPool.FUList5.opList06] 408type=OpDesc 409eventq_index=0 410opClass=SimdMult 411opLat=1 412pipelined=true 413 414[system.cpu0.fuPool.FUList5.opList07] 415type=OpDesc 416eventq_index=0 417opClass=SimdMultAcc 418opLat=1 419pipelined=true 420 421[system.cpu0.fuPool.FUList5.opList08] 422type=OpDesc 423eventq_index=0 424opClass=SimdShift 425opLat=1 426pipelined=true 427 428[system.cpu0.fuPool.FUList5.opList09] 429type=OpDesc 430eventq_index=0 431opClass=SimdShiftAcc 432opLat=1 433pipelined=true 434 435[system.cpu0.fuPool.FUList5.opList10] 436type=OpDesc 437eventq_index=0 438opClass=SimdSqrt 439opLat=1 440pipelined=true 441 442[system.cpu0.fuPool.FUList5.opList11] 443type=OpDesc 444eventq_index=0 445opClass=SimdFloatAdd 446opLat=1 447pipelined=true 448 449[system.cpu0.fuPool.FUList5.opList12] 450type=OpDesc 451eventq_index=0 452opClass=SimdFloatAlu 453opLat=1 454pipelined=true 455 456[system.cpu0.fuPool.FUList5.opList13] 457type=OpDesc 458eventq_index=0 459opClass=SimdFloatCmp 460opLat=1 461pipelined=true 462 463[system.cpu0.fuPool.FUList5.opList14] 464type=OpDesc 465eventq_index=0 466opClass=SimdFloatCvt 467opLat=1 468pipelined=true 469 470[system.cpu0.fuPool.FUList5.opList15] 471type=OpDesc 472eventq_index=0 473opClass=SimdFloatDiv 474opLat=1 475pipelined=true 476 477[system.cpu0.fuPool.FUList5.opList16] 478type=OpDesc 479eventq_index=0 480opClass=SimdFloatMisc 481opLat=1 482pipelined=true 483 484[system.cpu0.fuPool.FUList5.opList17] 485type=OpDesc 486eventq_index=0 487opClass=SimdFloatMult 488opLat=1 489pipelined=true 490 491[system.cpu0.fuPool.FUList5.opList18] 492type=OpDesc 493eventq_index=0 494opClass=SimdFloatMultAcc 495opLat=1 496pipelined=true 497 498[system.cpu0.fuPool.FUList5.opList19] 499type=OpDesc 500eventq_index=0 501opClass=SimdFloatSqrt 502opLat=1 503pipelined=true 504 505[system.cpu0.fuPool.FUList6] 506type=FUDesc
484children=opList	507children=opList0 opList1
485count=0 486eventq_index=0	508count=0 509eventq_index=0
487opList=system.cpu0.fuPool.FUList6.opList	510opList=system.cpu0.fuPool.FUList6.opList0 system.cpu0.fuPool.FUList6.opList1
488	511
489[system.cpu0.fuPool.FUList6.opList]	512[system.cpu0.fuPool.FUList6.opList0]
490type=OpDesc 491eventq_index=0 492opClass=MemWrite 493opLat=1 494pipelined=true 495	513type=OpDesc 514eventq_index=0 515opClass=MemWrite 516opLat=1 517pipelined=true 518
	519[system.cpu0.fuPool.FUList6.opList1] 520type=OpDesc 521eventq_index=0 522opClass=FloatMemWrite 523opLat=1 524pipelined=true 525
496[system.cpu0.fuPool.FUList7] 497type=FUDesc	526[system.cpu0.fuPool.FUList7] 527type=FUDesc
498children=opList0 opList1	528children=opList0 opList1 opList2 opList3
499count=4 500eventq_index=0	529count=4 530eventq_index=0
501opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1	531opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 system.cpu0.fuPool.FUList7.opList2 system.cpu0.fuPool.FUList7.opList3
502 503[system.cpu0.fuPool.FUList7.opList0] 504type=OpDesc 505eventq_index=0 506opClass=MemRead 507opLat=1 508pipelined=true 509 510[system.cpu0.fuPool.FUList7.opList1] 511type=OpDesc 512eventq_index=0 513opClass=MemWrite 514opLat=1 515pipelined=true 516	532 533[system.cpu0.fuPool.FUList7.opList0] 534type=OpDesc 535eventq_index=0 536opClass=MemRead 537opLat=1 538pipelined=true 539 540[system.cpu0.fuPool.FUList7.opList1] 541type=OpDesc 542eventq_index=0 543opClass=MemWrite 544opLat=1 545pipelined=true 546
	547[system.cpu0.fuPool.FUList7.opList2] 548type=OpDesc 549eventq_index=0 550opClass=FloatMemRead 551opLat=1 552pipelined=true 553 554[system.cpu0.fuPool.FUList7.opList3] 555type=OpDesc 556eventq_index=0 557opClass=FloatMemWrite 558opLat=1 559pipelined=true 560
517[system.cpu0.fuPool.FUList8] 518type=FUDesc 519children=opList 520count=1 521eventq_index=0 522opList=system.cpu0.fuPool.FUList8.opList 523 524[system.cpu0.fuPool.FUList8.opList] 525type=OpDesc 526eventq_index=0 527opClass=IprAccess 528opLat=3 529pipelined=false 530 531[system.cpu0.icache] 532type=Cache 533children=tags 534addr_ranges=0:18446744073709551615:0:0:0:0 535assoc=1 536clk_domain=system.cpu_clk_domain 537clusivity=mostly_incl	561[system.cpu0.fuPool.FUList8] 562type=FUDesc 563children=opList 564count=1 565eventq_index=0 566opList=system.cpu0.fuPool.FUList8.opList 567 568[system.cpu0.fuPool.FUList8.opList] 569type=OpDesc 570eventq_index=0 571opClass=IprAccess 572opLat=3 573pipelined=false 574 575[system.cpu0.icache] 576type=Cache 577children=tags 578addr_ranges=0:18446744073709551615:0:0:0:0 579assoc=1 580clk_domain=system.cpu_clk_domain 581clusivity=mostly_incl
	582data_latency=2
538default_p_state=UNDEFINED 539demand_mshr_reserve=1 540eventq_index=0	583default_p_state=UNDEFINED 584demand_mshr_reserve=1 585eventq_index=0
541hit_latency=2
542is_read_only=true 543max_miss_count=0 544mshrs=4 545p_state_clk_gate_bins=20 546p_state_clk_gate_max=1000000000000 547p_state_clk_gate_min=1000 548power_model=Null 549prefetch_on_access=false 550prefetcher=Null 551response_latency=2 552sequential_access=false 553size=32768 554system=system	586is_read_only=true 587max_miss_count=0 588mshrs=4 589p_state_clk_gate_bins=20 590p_state_clk_gate_max=1000000000000 591p_state_clk_gate_min=1000 592power_model=Null 593prefetch_on_access=false 594prefetcher=Null 595response_latency=2 596sequential_access=false 597size=32768 598system=system
	599tag_latency=2
555tags=system.cpu0.icache.tags 556tgts_per_mshr=20 557write_buffers=8 558writeback_clean=true 559cpu_side=system.cpu0.icache_port 560mem_side=system.toL2Bus.slave[0] 561 562[system.cpu0.icache.tags] 563type=LRU 564assoc=1 565block_size=64 566clk_domain=system.cpu_clk_domain	600tags=system.cpu0.icache.tags 601tgts_per_mshr=20 602write_buffers=8 603writeback_clean=true 604cpu_side=system.cpu0.icache_port 605mem_side=system.toL2Bus.slave[0] 606 607[system.cpu0.icache.tags] 608type=LRU 609assoc=1 610block_size=64 611clk_domain=system.cpu_clk_domain
	612data_latency=2
567default_p_state=UNDEFINED 568eventq_index=0	613default_p_state=UNDEFINED 614eventq_index=0
569hit_latency=2
570p_state_clk_gate_bins=20 571p_state_clk_gate_max=1000000000000 572p_state_clk_gate_min=1000 573power_model=Null 574sequential_access=false 575size=32768	615p_state_clk_gate_bins=20 616p_state_clk_gate_max=1000000000000 617p_state_clk_gate_min=1000 618power_model=Null 619sequential_access=false 620size=32768
	621tag_latency=2
576 577[system.cpu0.interrupts] 578type=SparcInterrupts 579eventq_index=0 580 581[system.cpu0.isa] 582type=SparcISA 583eventq_index=0 584 585[system.cpu0.itb] 586type=SparcTLB 587eventq_index=0 588size=64 589 590[system.cpu0.tracer] 591type=ExeTracer 592eventq_index=0 593 594[system.cpu0.workload] 595type=LiveProcess 596cmd=test_atomic 4 597cwd= 598drivers= 599egid=100 600env= 601errout=cerr 602euid=100 603eventq_index=0	622 623[system.cpu0.interrupts] 624type=SparcInterrupts 625eventq_index=0 626 627[system.cpu0.isa] 628type=SparcISA 629eventq_index=0 630 631[system.cpu0.itb] 632type=SparcTLB 633eventq_index=0 634size=64 635 636[system.cpu0.tracer] 637type=ExeTracer 638eventq_index=0 639 640[system.cpu0.workload] 641type=LiveProcess 642cmd=test_atomic 4 643cwd= 644drivers= 645egid=100 646env= 647errout=cerr 648euid=100 649eventq_index=0
604executable=/arm/projectscratch/randd/systems/dist/test-progs/m5threads/bin/sparc/linux/test_atomic	650executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
605gid=100 606input=cin 607kvmInSE=false 608max_stack_size=67108864 609output=cout 610pid=100 611ppid=99 612simpoint=0 613system=system 614uid=100 615useArchPT=false 616 617[system.cpu1] 618type=DerivO3CPU 619children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 620LFSTSize=1024 621LQEntries=32 622LSQCheckLoads=true 623LSQDepCheckShift=4 624SQEntries=32 625SSITSize=1024 626activity=0 627backComSize=5 628branchPred=system.cpu1.branchPred 629cachePorts=200 630checker=Null 631clk_domain=system.cpu_clk_domain 632commitToDecodeDelay=1 633commitToFetchDelay=1 634commitToIEWDelay=1 635commitToRenameDelay=1 636commitWidth=8 637cpu_id=1 638decodeToFetchDelay=1 639decodeToRenameDelay=1 640decodeWidth=8 641default_p_state=UNDEFINED 642dispatchWidth=8 643do_checkpoint_insts=true 644do_quiesce=true 645do_statistics_insts=true 646dtb=system.cpu1.dtb 647eventq_index=0 648fetchBufferSize=64 649fetchQueueSize=32 650fetchToDecodeDelay=1 651fetchTrapLatency=1 652fetchWidth=8 653forwardComSize=5 654fuPool=system.cpu1.fuPool 655function_trace=false 656function_trace_start=0 657iewToCommitDelay=1 658iewToDecodeDelay=1 659iewToFetchDelay=1 660iewToRenameDelay=1 661interrupts=system.cpu1.interrupts 662isa=system.cpu1.isa 663issueToExecuteDelay=1 664issueWidth=8 665itb=system.cpu1.itb 666max_insts_all_threads=0 667max_insts_any_thread=0 668max_loads_all_threads=0 669max_loads_any_thread=0 670needsTSO=false 671numIQEntries=64 672numPhysCCRegs=0 673numPhysFloatRegs=256 674numPhysIntRegs=256 675numROBEntries=192 676numRobs=1 677numThreads=1 678p_state_clk_gate_bins=20 679p_state_clk_gate_max=1000000000000 680p_state_clk_gate_min=1000 681power_model=Null 682profile=0 683progress_interval=0 684renameToDecodeDelay=1 685renameToFetchDelay=1 686renameToIEWDelay=2 687renameToROBDelay=1 688renameWidth=8 689simpoint_start_insts= 690smtCommitPolicy=RoundRobin 691smtFetchPolicy=SingleThread 692smtIQPolicy=Partitioned 693smtIQThreshold=100 694smtLSQPolicy=Partitioned 695smtLSQThreshold=100 696smtNumFetchingThreads=1 697smtROBPolicy=Partitioned 698smtROBThreshold=100 699socket_id=0 700squashWidth=8 701store_set_clear_period=250000 702switched_out=false 703system=system 704tracer=system.cpu1.tracer 705trapLatency=13 706wbWidth=8 707workload=system.cpu0.workload 708dcache_port=system.cpu1.dcache.cpu_side 709icache_port=system.cpu1.icache.cpu_side 710 711[system.cpu1.branchPred] 712type=TournamentBP 713BTBEntries=4096 714BTBTagSize=16 715RASSize=16 716choiceCtrBits=2 717choicePredictorSize=8192 718eventq_index=0 719globalCtrBits=2 720globalPredictorSize=8192 721indirectHashGHR=true 722indirectHashTargets=true 723indirectPathLength=3 724indirectSets=256 725indirectTagSize=16 726indirectWays=2 727instShiftAmt=2 728localCtrBits=2 729localHistoryTableSize=2048 730localPredictorSize=2048 731numThreads=1 732useIndirect=true 733 734[system.cpu1.dcache] 735type=Cache 736children=tags 737addr_ranges=0:18446744073709551615:0:0:0:0 738assoc=4 739clk_domain=system.cpu_clk_domain 740clusivity=mostly_incl	651gid=100 652input=cin 653kvmInSE=false 654max_stack_size=67108864 655output=cout 656pid=100 657ppid=99 658simpoint=0 659system=system 660uid=100 661useArchPT=false 662 663[system.cpu1] 664type=DerivO3CPU 665children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 666LFSTSize=1024 667LQEntries=32 668LSQCheckLoads=true 669LSQDepCheckShift=4 670SQEntries=32 671SSITSize=1024 672activity=0 673backComSize=5 674branchPred=system.cpu1.branchPred 675cachePorts=200 676checker=Null 677clk_domain=system.cpu_clk_domain 678commitToDecodeDelay=1 679commitToFetchDelay=1 680commitToIEWDelay=1 681commitToRenameDelay=1 682commitWidth=8 683cpu_id=1 684decodeToFetchDelay=1 685decodeToRenameDelay=1 686decodeWidth=8 687default_p_state=UNDEFINED 688dispatchWidth=8 689do_checkpoint_insts=true 690do_quiesce=true 691do_statistics_insts=true 692dtb=system.cpu1.dtb 693eventq_index=0 694fetchBufferSize=64 695fetchQueueSize=32 696fetchToDecodeDelay=1 697fetchTrapLatency=1 698fetchWidth=8 699forwardComSize=5 700fuPool=system.cpu1.fuPool 701function_trace=false 702function_trace_start=0 703iewToCommitDelay=1 704iewToDecodeDelay=1 705iewToFetchDelay=1 706iewToRenameDelay=1 707interrupts=system.cpu1.interrupts 708isa=system.cpu1.isa 709issueToExecuteDelay=1 710issueWidth=8 711itb=system.cpu1.itb 712max_insts_all_threads=0 713max_insts_any_thread=0 714max_loads_all_threads=0 715max_loads_any_thread=0 716needsTSO=false 717numIQEntries=64 718numPhysCCRegs=0 719numPhysFloatRegs=256 720numPhysIntRegs=256 721numROBEntries=192 722numRobs=1 723numThreads=1 724p_state_clk_gate_bins=20 725p_state_clk_gate_max=1000000000000 726p_state_clk_gate_min=1000 727power_model=Null 728profile=0 729progress_interval=0 730renameToDecodeDelay=1 731renameToFetchDelay=1 732renameToIEWDelay=2 733renameToROBDelay=1 734renameWidth=8 735simpoint_start_insts= 736smtCommitPolicy=RoundRobin 737smtFetchPolicy=SingleThread 738smtIQPolicy=Partitioned 739smtIQThreshold=100 740smtLSQPolicy=Partitioned 741smtLSQThreshold=100 742smtNumFetchingThreads=1 743smtROBPolicy=Partitioned 744smtROBThreshold=100 745socket_id=0 746squashWidth=8 747store_set_clear_period=250000 748switched_out=false 749system=system 750tracer=system.cpu1.tracer 751trapLatency=13 752wbWidth=8 753workload=system.cpu0.workload 754dcache_port=system.cpu1.dcache.cpu_side 755icache_port=system.cpu1.icache.cpu_side 756 757[system.cpu1.branchPred] 758type=TournamentBP 759BTBEntries=4096 760BTBTagSize=16 761RASSize=16 762choiceCtrBits=2 763choicePredictorSize=8192 764eventq_index=0 765globalCtrBits=2 766globalPredictorSize=8192 767indirectHashGHR=true 768indirectHashTargets=true 769indirectPathLength=3 770indirectSets=256 771indirectTagSize=16 772indirectWays=2 773instShiftAmt=2 774localCtrBits=2 775localHistoryTableSize=2048 776localPredictorSize=2048 777numThreads=1 778useIndirect=true 779 780[system.cpu1.dcache] 781type=Cache 782children=tags 783addr_ranges=0:18446744073709551615:0:0:0:0 784assoc=4 785clk_domain=system.cpu_clk_domain 786clusivity=mostly_incl
	787data_latency=2
741default_p_state=UNDEFINED 742demand_mshr_reserve=1 743eventq_index=0	788default_p_state=UNDEFINED 789demand_mshr_reserve=1 790eventq_index=0
744hit_latency=2
745is_read_only=false 746max_miss_count=0 747mshrs=4 748p_state_clk_gate_bins=20 749p_state_clk_gate_max=1000000000000 750p_state_clk_gate_min=1000 751power_model=Null 752prefetch_on_access=false 753prefetcher=Null 754response_latency=2 755sequential_access=false 756size=32768 757system=system	791is_read_only=false 792max_miss_count=0 793mshrs=4 794p_state_clk_gate_bins=20 795p_state_clk_gate_max=1000000000000 796p_state_clk_gate_min=1000 797power_model=Null 798prefetch_on_access=false 799prefetcher=Null 800response_latency=2 801sequential_access=false 802size=32768 803system=system
	804tag_latency=2
758tags=system.cpu1.dcache.tags 759tgts_per_mshr=20 760write_buffers=8 761writeback_clean=false 762cpu_side=system.cpu1.dcache_port 763mem_side=system.toL2Bus.slave[3] 764 765[system.cpu1.dcache.tags] 766type=LRU 767assoc=4 768block_size=64 769clk_domain=system.cpu_clk_domain	805tags=system.cpu1.dcache.tags 806tgts_per_mshr=20 807write_buffers=8 808writeback_clean=false 809cpu_side=system.cpu1.dcache_port 810mem_side=system.toL2Bus.slave[3] 811 812[system.cpu1.dcache.tags] 813type=LRU 814assoc=4 815block_size=64 816clk_domain=system.cpu_clk_domain
	817data_latency=2
770default_p_state=UNDEFINED 771eventq_index=0	818default_p_state=UNDEFINED 819eventq_index=0
772hit_latency=2
773p_state_clk_gate_bins=20 774p_state_clk_gate_max=1000000000000 775p_state_clk_gate_min=1000 776power_model=Null 777sequential_access=false 778size=32768	820p_state_clk_gate_bins=20 821p_state_clk_gate_max=1000000000000 822p_state_clk_gate_min=1000 823power_model=Null 824sequential_access=false 825size=32768
	826tag_latency=2
779 780[system.cpu1.dtb] 781type=SparcTLB 782eventq_index=0 783size=64 784 785[system.cpu1.fuPool] 786type=FUPool 787children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 788FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 789eventq_index=0 790 791[system.cpu1.fuPool.FUList0] 792type=FUDesc 793children=opList 794count=6 795eventq_index=0 796opList=system.cpu1.fuPool.FUList0.opList 797 798[system.cpu1.fuPool.FUList0.opList] 799type=OpDesc 800eventq_index=0 801opClass=IntAlu 802opLat=1 803pipelined=true 804 805[system.cpu1.fuPool.FUList1] 806type=FUDesc 807children=opList0 opList1 808count=2 809eventq_index=0 810opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 811 812[system.cpu1.fuPool.FUList1.opList0] 813type=OpDesc 814eventq_index=0 815opClass=IntMult 816opLat=3 817pipelined=true 818 819[system.cpu1.fuPool.FUList1.opList1] 820type=OpDesc 821eventq_index=0 822opClass=IntDiv 823opLat=20 824pipelined=false 825 826[system.cpu1.fuPool.FUList2] 827type=FUDesc 828children=opList0 opList1 opList2 829count=4 830eventq_index=0 831opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 832 833[system.cpu1.fuPool.FUList2.opList0] 834type=OpDesc 835eventq_index=0 836opClass=FloatAdd 837opLat=2 838pipelined=true 839 840[system.cpu1.fuPool.FUList2.opList1] 841type=OpDesc 842eventq_index=0 843opClass=FloatCmp 844opLat=2 845pipelined=true 846 847[system.cpu1.fuPool.FUList2.opList2] 848type=OpDesc 849eventq_index=0 850opClass=FloatCvt 851opLat=2 852pipelined=true 853 854[system.cpu1.fuPool.FUList3] 855type=FUDesc	827 828[system.cpu1.dtb] 829type=SparcTLB 830eventq_index=0 831size=64 832 833[system.cpu1.fuPool] 834type=FUPool 835children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 836FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 837eventq_index=0 838 839[system.cpu1.fuPool.FUList0] 840type=FUDesc 841children=opList 842count=6 843eventq_index=0 844opList=system.cpu1.fuPool.FUList0.opList 845 846[system.cpu1.fuPool.FUList0.opList] 847type=OpDesc 848eventq_index=0 849opClass=IntAlu 850opLat=1 851pipelined=true 852 853[system.cpu1.fuPool.FUList1] 854type=FUDesc 855children=opList0 opList1 856count=2 857eventq_index=0 858opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 859 860[system.cpu1.fuPool.FUList1.opList0] 861type=OpDesc 862eventq_index=0 863opClass=IntMult 864opLat=3 865pipelined=true 866 867[system.cpu1.fuPool.FUList1.opList1] 868type=OpDesc 869eventq_index=0 870opClass=IntDiv 871opLat=20 872pipelined=false 873 874[system.cpu1.fuPool.FUList2] 875type=FUDesc 876children=opList0 opList1 opList2 877count=4 878eventq_index=0 879opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 880 881[system.cpu1.fuPool.FUList2.opList0] 882type=OpDesc 883eventq_index=0 884opClass=FloatAdd 885opLat=2 886pipelined=true 887 888[system.cpu1.fuPool.FUList2.opList1] 889type=OpDesc 890eventq_index=0 891opClass=FloatCmp 892opLat=2 893pipelined=true 894 895[system.cpu1.fuPool.FUList2.opList2] 896type=OpDesc 897eventq_index=0 898opClass=FloatCvt 899opLat=2 900pipelined=true 901 902[system.cpu1.fuPool.FUList3] 903type=FUDesc
856children=opList0 opList1 opList2	904children=opList0 opList1 opList2 opList3 opList4
857count=2 858eventq_index=0	905count=2 906eventq_index=0
859opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2	907opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 system.cpu1.fuPool.FUList3.opList3 system.cpu1.fuPool.FUList3.opList4
860 861[system.cpu1.fuPool.FUList3.opList0] 862type=OpDesc 863eventq_index=0 864opClass=FloatMult 865opLat=4 866pipelined=true 867 868[system.cpu1.fuPool.FUList3.opList1] 869type=OpDesc 870eventq_index=0	908 909[system.cpu1.fuPool.FUList3.opList0] 910type=OpDesc 911eventq_index=0 912opClass=FloatMult 913opLat=4 914pipelined=true 915 916[system.cpu1.fuPool.FUList3.opList1] 917type=OpDesc 918eventq_index=0
	919opClass=FloatMultAcc 920opLat=5 921pipelined=true 922 923[system.cpu1.fuPool.FUList3.opList2] 924type=OpDesc 925eventq_index=0 926opClass=FloatMisc 927opLat=3 928pipelined=true 929 930[system.cpu1.fuPool.FUList3.opList3] 931type=OpDesc 932eventq_index=0
871opClass=FloatDiv 872opLat=12 873pipelined=false 874	933opClass=FloatDiv 934opLat=12 935pipelined=false 936
875[system.cpu1.fuPool.FUList3.opList2]	937[system.cpu1.fuPool.FUList3.opList4]
876type=OpDesc 877eventq_index=0 878opClass=FloatSqrt 879opLat=24 880pipelined=false 881 882[system.cpu1.fuPool.FUList4] 883type=FUDesc	938type=OpDesc 939eventq_index=0 940opClass=FloatSqrt 941opLat=24 942pipelined=false 943 944[system.cpu1.fuPool.FUList4] 945type=FUDesc
884children=opList	946children=opList0 opList1
885count=0 886eventq_index=0	947count=0 948eventq_index=0
887opList=system.cpu1.fuPool.FUList4.opList	949opList=system.cpu1.fuPool.FUList4.opList0 system.cpu1.fuPool.FUList4.opList1
888	950
889[system.cpu1.fuPool.FUList4.opList]	951[system.cpu1.fuPool.FUList4.opList0]
890type=OpDesc 891eventq_index=0 892opClass=MemRead 893opLat=1 894pipelined=true 895	952type=OpDesc 953eventq_index=0 954opClass=MemRead 955opLat=1 956pipelined=true 957
	958[system.cpu1.fuPool.FUList4.opList1] 959type=OpDesc 960eventq_index=0 961opClass=FloatMemRead 962opLat=1 963pipelined=true 964
896[system.cpu1.fuPool.FUList5] 897type=FUDesc 898children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 899count=4 900eventq_index=0 901opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 902 903[system.cpu1.fuPool.FUList5.opList00] 904type=OpDesc 905eventq_index=0 906opClass=SimdAdd 907opLat=1 908pipelined=true 909 910[system.cpu1.fuPool.FUList5.opList01] 911type=OpDesc 912eventq_index=0 913opClass=SimdAddAcc 914opLat=1 915pipelined=true 916 917[system.cpu1.fuPool.FUList5.opList02] 918type=OpDesc 919eventq_index=0 920opClass=SimdAlu 921opLat=1 922pipelined=true 923 924[system.cpu1.fuPool.FUList5.opList03] 925type=OpDesc 926eventq_index=0 927opClass=SimdCmp 928opLat=1 929pipelined=true 930 931[system.cpu1.fuPool.FUList5.opList04] 932type=OpDesc 933eventq_index=0 934opClass=SimdCvt 935opLat=1 936pipelined=true 937 938[system.cpu1.fuPool.FUList5.opList05] 939type=OpDesc 940eventq_index=0 941opClass=SimdMisc 942opLat=1 943pipelined=true 944 945[system.cpu1.fuPool.FUList5.opList06] 946type=OpDesc 947eventq_index=0 948opClass=SimdMult 949opLat=1 950pipelined=true 951 952[system.cpu1.fuPool.FUList5.opList07] 953type=OpDesc 954eventq_index=0 955opClass=SimdMultAcc 956opLat=1 957pipelined=true 958 959[system.cpu1.fuPool.FUList5.opList08] 960type=OpDesc 961eventq_index=0 962opClass=SimdShift 963opLat=1 964pipelined=true 965 966[system.cpu1.fuPool.FUList5.opList09] 967type=OpDesc 968eventq_index=0 969opClass=SimdShiftAcc 970opLat=1 971pipelined=true 972 973[system.cpu1.fuPool.FUList5.opList10] 974type=OpDesc 975eventq_index=0 976opClass=SimdSqrt 977opLat=1 978pipelined=true 979 980[system.cpu1.fuPool.FUList5.opList11] 981type=OpDesc 982eventq_index=0 983opClass=SimdFloatAdd 984opLat=1 985pipelined=true 986 987[system.cpu1.fuPool.FUList5.opList12] 988type=OpDesc 989eventq_index=0 990opClass=SimdFloatAlu 991opLat=1 992pipelined=true 993 994[system.cpu1.fuPool.FUList5.opList13] 995type=OpDesc 996eventq_index=0 997opClass=SimdFloatCmp 998opLat=1 999pipelined=true 1000 1001[system.cpu1.fuPool.FUList5.opList14] 1002type=OpDesc 1003eventq_index=0 1004opClass=SimdFloatCvt 1005opLat=1 1006pipelined=true 1007 1008[system.cpu1.fuPool.FUList5.opList15] 1009type=OpDesc 1010eventq_index=0 1011opClass=SimdFloatDiv 1012opLat=1 1013pipelined=true 1014 1015[system.cpu1.fuPool.FUList5.opList16] 1016type=OpDesc 1017eventq_index=0 1018opClass=SimdFloatMisc 1019opLat=1 1020pipelined=true 1021 1022[system.cpu1.fuPool.FUList5.opList17] 1023type=OpDesc 1024eventq_index=0 1025opClass=SimdFloatMult 1026opLat=1 1027pipelined=true 1028 1029[system.cpu1.fuPool.FUList5.opList18] 1030type=OpDesc 1031eventq_index=0 1032opClass=SimdFloatMultAcc 1033opLat=1 1034pipelined=true 1035 1036[system.cpu1.fuPool.FUList5.opList19] 1037type=OpDesc 1038eventq_index=0 1039opClass=SimdFloatSqrt 1040opLat=1 1041pipelined=true 1042 1043[system.cpu1.fuPool.FUList6] 1044type=FUDesc	965[system.cpu1.fuPool.FUList5] 966type=FUDesc 967children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 968count=4 969eventq_index=0 970opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 971 972[system.cpu1.fuPool.FUList5.opList00] 973type=OpDesc 974eventq_index=0 975opClass=SimdAdd 976opLat=1 977pipelined=true 978 979[system.cpu1.fuPool.FUList5.opList01] 980type=OpDesc 981eventq_index=0 982opClass=SimdAddAcc 983opLat=1 984pipelined=true 985 986[system.cpu1.fuPool.FUList5.opList02] 987type=OpDesc 988eventq_index=0 989opClass=SimdAlu 990opLat=1 991pipelined=true 992 993[system.cpu1.fuPool.FUList5.opList03] 994type=OpDesc 995eventq_index=0 996opClass=SimdCmp 997opLat=1 998pipelined=true 999 1000[system.cpu1.fuPool.FUList5.opList04] 1001type=OpDesc 1002eventq_index=0 1003opClass=SimdCvt 1004opLat=1 1005pipelined=true 1006 1007[system.cpu1.fuPool.FUList5.opList05] 1008type=OpDesc 1009eventq_index=0 1010opClass=SimdMisc 1011opLat=1 1012pipelined=true 1013 1014[system.cpu1.fuPool.FUList5.opList06] 1015type=OpDesc 1016eventq_index=0 1017opClass=SimdMult 1018opLat=1 1019pipelined=true 1020 1021[system.cpu1.fuPool.FUList5.opList07] 1022type=OpDesc 1023eventq_index=0 1024opClass=SimdMultAcc 1025opLat=1 1026pipelined=true 1027 1028[system.cpu1.fuPool.FUList5.opList08] 1029type=OpDesc 1030eventq_index=0 1031opClass=SimdShift 1032opLat=1 1033pipelined=true 1034 1035[system.cpu1.fuPool.FUList5.opList09] 1036type=OpDesc 1037eventq_index=0 1038opClass=SimdShiftAcc 1039opLat=1 1040pipelined=true 1041 1042[system.cpu1.fuPool.FUList5.opList10] 1043type=OpDesc 1044eventq_index=0 1045opClass=SimdSqrt 1046opLat=1 1047pipelined=true 1048 1049[system.cpu1.fuPool.FUList5.opList11] 1050type=OpDesc 1051eventq_index=0 1052opClass=SimdFloatAdd 1053opLat=1 1054pipelined=true 1055 1056[system.cpu1.fuPool.FUList5.opList12] 1057type=OpDesc 1058eventq_index=0 1059opClass=SimdFloatAlu 1060opLat=1 1061pipelined=true 1062 1063[system.cpu1.fuPool.FUList5.opList13] 1064type=OpDesc 1065eventq_index=0 1066opClass=SimdFloatCmp 1067opLat=1 1068pipelined=true 1069 1070[system.cpu1.fuPool.FUList5.opList14] 1071type=OpDesc 1072eventq_index=0 1073opClass=SimdFloatCvt 1074opLat=1 1075pipelined=true 1076 1077[system.cpu1.fuPool.FUList5.opList15] 1078type=OpDesc 1079eventq_index=0 1080opClass=SimdFloatDiv 1081opLat=1 1082pipelined=true 1083 1084[system.cpu1.fuPool.FUList5.opList16] 1085type=OpDesc 1086eventq_index=0 1087opClass=SimdFloatMisc 1088opLat=1 1089pipelined=true 1090 1091[system.cpu1.fuPool.FUList5.opList17] 1092type=OpDesc 1093eventq_index=0 1094opClass=SimdFloatMult 1095opLat=1 1096pipelined=true 1097 1098[system.cpu1.fuPool.FUList5.opList18] 1099type=OpDesc 1100eventq_index=0 1101opClass=SimdFloatMultAcc 1102opLat=1 1103pipelined=true 1104 1105[system.cpu1.fuPool.FUList5.opList19] 1106type=OpDesc 1107eventq_index=0 1108opClass=SimdFloatSqrt 1109opLat=1 1110pipelined=true 1111 1112[system.cpu1.fuPool.FUList6] 1113type=FUDesc
1045children=opList	1114children=opList0 opList1
1046count=0 1047eventq_index=0	1115count=0 1116eventq_index=0
1048opList=system.cpu1.fuPool.FUList6.opList	1117opList=system.cpu1.fuPool.FUList6.opList0 system.cpu1.fuPool.FUList6.opList1
1049	1118
1050[system.cpu1.fuPool.FUList6.opList]	1119[system.cpu1.fuPool.FUList6.opList0]
1051type=OpDesc 1052eventq_index=0 1053opClass=MemWrite 1054opLat=1 1055pipelined=true 1056	1120type=OpDesc 1121eventq_index=0 1122opClass=MemWrite 1123opLat=1 1124pipelined=true 1125
	1126[system.cpu1.fuPool.FUList6.opList1] 1127type=OpDesc 1128eventq_index=0 1129opClass=FloatMemWrite 1130opLat=1 1131pipelined=true 1132
1057[system.cpu1.fuPool.FUList7] 1058type=FUDesc	1133[system.cpu1.fuPool.FUList7] 1134type=FUDesc
1059children=opList0 opList1	1135children=opList0 opList1 opList2 opList3
1060count=4 1061eventq_index=0	1136count=4 1137eventq_index=0
1062opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1	1138opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 system.cpu1.fuPool.FUList7.opList2 system.cpu1.fuPool.FUList7.opList3
1063 1064[system.cpu1.fuPool.FUList7.opList0] 1065type=OpDesc 1066eventq_index=0 1067opClass=MemRead 1068opLat=1 1069pipelined=true 1070 1071[system.cpu1.fuPool.FUList7.opList1] 1072type=OpDesc 1073eventq_index=0 1074opClass=MemWrite 1075opLat=1 1076pipelined=true 1077	1139 1140[system.cpu1.fuPool.FUList7.opList0] 1141type=OpDesc 1142eventq_index=0 1143opClass=MemRead 1144opLat=1 1145pipelined=true 1146 1147[system.cpu1.fuPool.FUList7.opList1] 1148type=OpDesc 1149eventq_index=0 1150opClass=MemWrite 1151opLat=1 1152pipelined=true 1153
	1154[system.cpu1.fuPool.FUList7.opList2] 1155type=OpDesc 1156eventq_index=0 1157opClass=FloatMemRead 1158opLat=1 1159pipelined=true 1160 1161[system.cpu1.fuPool.FUList7.opList3] 1162type=OpDesc 1163eventq_index=0 1164opClass=FloatMemWrite 1165opLat=1 1166pipelined=true 1167
1078[system.cpu1.fuPool.FUList8] 1079type=FUDesc 1080children=opList 1081count=1 1082eventq_index=0 1083opList=system.cpu1.fuPool.FUList8.opList 1084 1085[system.cpu1.fuPool.FUList8.opList] 1086type=OpDesc 1087eventq_index=0 1088opClass=IprAccess 1089opLat=3 1090pipelined=false 1091 1092[system.cpu1.icache] 1093type=Cache 1094children=tags 1095addr_ranges=0:18446744073709551615:0:0:0:0 1096assoc=1 1097clk_domain=system.cpu_clk_domain 1098clusivity=mostly_incl	1168[system.cpu1.fuPool.FUList8] 1169type=FUDesc 1170children=opList 1171count=1 1172eventq_index=0 1173opList=system.cpu1.fuPool.FUList8.opList 1174 1175[system.cpu1.fuPool.FUList8.opList] 1176type=OpDesc 1177eventq_index=0 1178opClass=IprAccess 1179opLat=3 1180pipelined=false 1181 1182[system.cpu1.icache] 1183type=Cache 1184children=tags 1185addr_ranges=0:18446744073709551615:0:0:0:0 1186assoc=1 1187clk_domain=system.cpu_clk_domain 1188clusivity=mostly_incl
	1189data_latency=2
1099default_p_state=UNDEFINED 1100demand_mshr_reserve=1 1101eventq_index=0	1190default_p_state=UNDEFINED 1191demand_mshr_reserve=1 1192eventq_index=0
1102hit_latency=2
1103is_read_only=true 1104max_miss_count=0 1105mshrs=4 1106p_state_clk_gate_bins=20 1107p_state_clk_gate_max=1000000000000 1108p_state_clk_gate_min=1000 1109power_model=Null 1110prefetch_on_access=false 1111prefetcher=Null 1112response_latency=2 1113sequential_access=false 1114size=32768 1115system=system	1193is_read_only=true 1194max_miss_count=0 1195mshrs=4 1196p_state_clk_gate_bins=20 1197p_state_clk_gate_max=1000000000000 1198p_state_clk_gate_min=1000 1199power_model=Null 1200prefetch_on_access=false 1201prefetcher=Null 1202response_latency=2 1203sequential_access=false 1204size=32768 1205system=system
	1206tag_latency=2
1116tags=system.cpu1.icache.tags 1117tgts_per_mshr=20 1118write_buffers=8 1119writeback_clean=true 1120cpu_side=system.cpu1.icache_port 1121mem_side=system.toL2Bus.slave[2] 1122 1123[system.cpu1.icache.tags] 1124type=LRU 1125assoc=1 1126block_size=64 1127clk_domain=system.cpu_clk_domain	1207tags=system.cpu1.icache.tags 1208tgts_per_mshr=20 1209write_buffers=8 1210writeback_clean=true 1211cpu_side=system.cpu1.icache_port 1212mem_side=system.toL2Bus.slave[2] 1213 1214[system.cpu1.icache.tags] 1215type=LRU 1216assoc=1 1217block_size=64 1218clk_domain=system.cpu_clk_domain
	1219data_latency=2
1128default_p_state=UNDEFINED 1129eventq_index=0	1220default_p_state=UNDEFINED 1221eventq_index=0
1130hit_latency=2
1131p_state_clk_gate_bins=20 1132p_state_clk_gate_max=1000000000000 1133p_state_clk_gate_min=1000 1134power_model=Null 1135sequential_access=false 1136size=32768	1222p_state_clk_gate_bins=20 1223p_state_clk_gate_max=1000000000000 1224p_state_clk_gate_min=1000 1225power_model=Null 1226sequential_access=false 1227size=32768
	1228tag_latency=2
1137 1138[system.cpu1.interrupts] 1139type=SparcInterrupts 1140eventq_index=0 1141 1142[system.cpu1.isa] 1143type=SparcISA 1144eventq_index=0 1145 1146[system.cpu1.itb] 1147type=SparcTLB 1148eventq_index=0 1149size=64 1150 1151[system.cpu1.tracer] 1152type=ExeTracer 1153eventq_index=0 1154 1155[system.cpu2] 1156type=DerivO3CPU 1157children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1158LFSTSize=1024 1159LQEntries=32 1160LSQCheckLoads=true 1161LSQDepCheckShift=4 1162SQEntries=32 1163SSITSize=1024 1164activity=0 1165backComSize=5 1166branchPred=system.cpu2.branchPred 1167cachePorts=200 1168checker=Null 1169clk_domain=system.cpu_clk_domain 1170commitToDecodeDelay=1 1171commitToFetchDelay=1 1172commitToIEWDelay=1 1173commitToRenameDelay=1 1174commitWidth=8 1175cpu_id=2 1176decodeToFetchDelay=1 1177decodeToRenameDelay=1 1178decodeWidth=8 1179default_p_state=UNDEFINED 1180dispatchWidth=8 1181do_checkpoint_insts=true 1182do_quiesce=true 1183do_statistics_insts=true 1184dtb=system.cpu2.dtb 1185eventq_index=0 1186fetchBufferSize=64 1187fetchQueueSize=32 1188fetchToDecodeDelay=1 1189fetchTrapLatency=1 1190fetchWidth=8 1191forwardComSize=5 1192fuPool=system.cpu2.fuPool 1193function_trace=false 1194function_trace_start=0 1195iewToCommitDelay=1 1196iewToDecodeDelay=1 1197iewToFetchDelay=1 1198iewToRenameDelay=1 1199interrupts=system.cpu2.interrupts 1200isa=system.cpu2.isa 1201issueToExecuteDelay=1 1202issueWidth=8 1203itb=system.cpu2.itb 1204max_insts_all_threads=0 1205max_insts_any_thread=0 1206max_loads_all_threads=0 1207max_loads_any_thread=0 1208needsTSO=false 1209numIQEntries=64 1210numPhysCCRegs=0 1211numPhysFloatRegs=256 1212numPhysIntRegs=256 1213numROBEntries=192 1214numRobs=1 1215numThreads=1 1216p_state_clk_gate_bins=20 1217p_state_clk_gate_max=1000000000000 1218p_state_clk_gate_min=1000 1219power_model=Null 1220profile=0 1221progress_interval=0 1222renameToDecodeDelay=1 1223renameToFetchDelay=1 1224renameToIEWDelay=2 1225renameToROBDelay=1 1226renameWidth=8 1227simpoint_start_insts= 1228smtCommitPolicy=RoundRobin 1229smtFetchPolicy=SingleThread 1230smtIQPolicy=Partitioned 1231smtIQThreshold=100 1232smtLSQPolicy=Partitioned 1233smtLSQThreshold=100 1234smtNumFetchingThreads=1 1235smtROBPolicy=Partitioned 1236smtROBThreshold=100 1237socket_id=0 1238squashWidth=8 1239store_set_clear_period=250000 1240switched_out=false 1241system=system 1242tracer=system.cpu2.tracer 1243trapLatency=13 1244wbWidth=8 1245workload=system.cpu0.workload 1246dcache_port=system.cpu2.dcache.cpu_side 1247icache_port=system.cpu2.icache.cpu_side 1248 1249[system.cpu2.branchPred] 1250type=TournamentBP 1251BTBEntries=4096 1252BTBTagSize=16 1253RASSize=16 1254choiceCtrBits=2 1255choicePredictorSize=8192 1256eventq_index=0 1257globalCtrBits=2 1258globalPredictorSize=8192 1259indirectHashGHR=true 1260indirectHashTargets=true 1261indirectPathLength=3 1262indirectSets=256 1263indirectTagSize=16 1264indirectWays=2 1265instShiftAmt=2 1266localCtrBits=2 1267localHistoryTableSize=2048 1268localPredictorSize=2048 1269numThreads=1 1270useIndirect=true 1271 1272[system.cpu2.dcache] 1273type=Cache 1274children=tags 1275addr_ranges=0:18446744073709551615:0:0:0:0 1276assoc=4 1277clk_domain=system.cpu_clk_domain 1278clusivity=mostly_incl	1229 1230[system.cpu1.interrupts] 1231type=SparcInterrupts 1232eventq_index=0 1233 1234[system.cpu1.isa] 1235type=SparcISA 1236eventq_index=0 1237 1238[system.cpu1.itb] 1239type=SparcTLB 1240eventq_index=0 1241size=64 1242 1243[system.cpu1.tracer] 1244type=ExeTracer 1245eventq_index=0 1246 1247[system.cpu2] 1248type=DerivO3CPU 1249children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1250LFSTSize=1024 1251LQEntries=32 1252LSQCheckLoads=true 1253LSQDepCheckShift=4 1254SQEntries=32 1255SSITSize=1024 1256activity=0 1257backComSize=5 1258branchPred=system.cpu2.branchPred 1259cachePorts=200 1260checker=Null 1261clk_domain=system.cpu_clk_domain 1262commitToDecodeDelay=1 1263commitToFetchDelay=1 1264commitToIEWDelay=1 1265commitToRenameDelay=1 1266commitWidth=8 1267cpu_id=2 1268decodeToFetchDelay=1 1269decodeToRenameDelay=1 1270decodeWidth=8 1271default_p_state=UNDEFINED 1272dispatchWidth=8 1273do_checkpoint_insts=true 1274do_quiesce=true 1275do_statistics_insts=true 1276dtb=system.cpu2.dtb 1277eventq_index=0 1278fetchBufferSize=64 1279fetchQueueSize=32 1280fetchToDecodeDelay=1 1281fetchTrapLatency=1 1282fetchWidth=8 1283forwardComSize=5 1284fuPool=system.cpu2.fuPool 1285function_trace=false 1286function_trace_start=0 1287iewToCommitDelay=1 1288iewToDecodeDelay=1 1289iewToFetchDelay=1 1290iewToRenameDelay=1 1291interrupts=system.cpu2.interrupts 1292isa=system.cpu2.isa 1293issueToExecuteDelay=1 1294issueWidth=8 1295itb=system.cpu2.itb 1296max_insts_all_threads=0 1297max_insts_any_thread=0 1298max_loads_all_threads=0 1299max_loads_any_thread=0 1300needsTSO=false 1301numIQEntries=64 1302numPhysCCRegs=0 1303numPhysFloatRegs=256 1304numPhysIntRegs=256 1305numROBEntries=192 1306numRobs=1 1307numThreads=1 1308p_state_clk_gate_bins=20 1309p_state_clk_gate_max=1000000000000 1310p_state_clk_gate_min=1000 1311power_model=Null 1312profile=0 1313progress_interval=0 1314renameToDecodeDelay=1 1315renameToFetchDelay=1 1316renameToIEWDelay=2 1317renameToROBDelay=1 1318renameWidth=8 1319simpoint_start_insts= 1320smtCommitPolicy=RoundRobin 1321smtFetchPolicy=SingleThread 1322smtIQPolicy=Partitioned 1323smtIQThreshold=100 1324smtLSQPolicy=Partitioned 1325smtLSQThreshold=100 1326smtNumFetchingThreads=1 1327smtROBPolicy=Partitioned 1328smtROBThreshold=100 1329socket_id=0 1330squashWidth=8 1331store_set_clear_period=250000 1332switched_out=false 1333system=system 1334tracer=system.cpu2.tracer 1335trapLatency=13 1336wbWidth=8 1337workload=system.cpu0.workload 1338dcache_port=system.cpu2.dcache.cpu_side 1339icache_port=system.cpu2.icache.cpu_side 1340 1341[system.cpu2.branchPred] 1342type=TournamentBP 1343BTBEntries=4096 1344BTBTagSize=16 1345RASSize=16 1346choiceCtrBits=2 1347choicePredictorSize=8192 1348eventq_index=0 1349globalCtrBits=2 1350globalPredictorSize=8192 1351indirectHashGHR=true 1352indirectHashTargets=true 1353indirectPathLength=3 1354indirectSets=256 1355indirectTagSize=16 1356indirectWays=2 1357instShiftAmt=2 1358localCtrBits=2 1359localHistoryTableSize=2048 1360localPredictorSize=2048 1361numThreads=1 1362useIndirect=true 1363 1364[system.cpu2.dcache] 1365type=Cache 1366children=tags 1367addr_ranges=0:18446744073709551615:0:0:0:0 1368assoc=4 1369clk_domain=system.cpu_clk_domain 1370clusivity=mostly_incl
	1371data_latency=2
1279default_p_state=UNDEFINED 1280demand_mshr_reserve=1 1281eventq_index=0	1372default_p_state=UNDEFINED 1373demand_mshr_reserve=1 1374eventq_index=0
1282hit_latency=2
1283is_read_only=false 1284max_miss_count=0 1285mshrs=4 1286p_state_clk_gate_bins=20 1287p_state_clk_gate_max=1000000000000 1288p_state_clk_gate_min=1000 1289power_model=Null 1290prefetch_on_access=false 1291prefetcher=Null 1292response_latency=2 1293sequential_access=false 1294size=32768 1295system=system	1375is_read_only=false 1376max_miss_count=0 1377mshrs=4 1378p_state_clk_gate_bins=20 1379p_state_clk_gate_max=1000000000000 1380p_state_clk_gate_min=1000 1381power_model=Null 1382prefetch_on_access=false 1383prefetcher=Null 1384response_latency=2 1385sequential_access=false 1386size=32768 1387system=system
	1388tag_latency=2
1296tags=system.cpu2.dcache.tags 1297tgts_per_mshr=20 1298write_buffers=8 1299writeback_clean=false 1300cpu_side=system.cpu2.dcache_port 1301mem_side=system.toL2Bus.slave[5] 1302 1303[system.cpu2.dcache.tags] 1304type=LRU 1305assoc=4 1306block_size=64 1307clk_domain=system.cpu_clk_domain	1389tags=system.cpu2.dcache.tags 1390tgts_per_mshr=20 1391write_buffers=8 1392writeback_clean=false 1393cpu_side=system.cpu2.dcache_port 1394mem_side=system.toL2Bus.slave[5] 1395 1396[system.cpu2.dcache.tags] 1397type=LRU 1398assoc=4 1399block_size=64 1400clk_domain=system.cpu_clk_domain
	1401data_latency=2
1308default_p_state=UNDEFINED 1309eventq_index=0	1402default_p_state=UNDEFINED 1403eventq_index=0
1310hit_latency=2
1311p_state_clk_gate_bins=20 1312p_state_clk_gate_max=1000000000000 1313p_state_clk_gate_min=1000 1314power_model=Null 1315sequential_access=false 1316size=32768	1404p_state_clk_gate_bins=20 1405p_state_clk_gate_max=1000000000000 1406p_state_clk_gate_min=1000 1407power_model=Null 1408sequential_access=false 1409size=32768
	1410tag_latency=2
1317 1318[system.cpu2.dtb] 1319type=SparcTLB 1320eventq_index=0 1321size=64 1322 1323[system.cpu2.fuPool] 1324type=FUPool 1325children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1326FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 1327eventq_index=0 1328 1329[system.cpu2.fuPool.FUList0] 1330type=FUDesc 1331children=opList 1332count=6 1333eventq_index=0 1334opList=system.cpu2.fuPool.FUList0.opList 1335 1336[system.cpu2.fuPool.FUList0.opList] 1337type=OpDesc 1338eventq_index=0 1339opClass=IntAlu 1340opLat=1 1341pipelined=true 1342 1343[system.cpu2.fuPool.FUList1] 1344type=FUDesc 1345children=opList0 opList1 1346count=2 1347eventq_index=0 1348opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 1349 1350[system.cpu2.fuPool.FUList1.opList0] 1351type=OpDesc 1352eventq_index=0 1353opClass=IntMult 1354opLat=3 1355pipelined=true 1356 1357[system.cpu2.fuPool.FUList1.opList1] 1358type=OpDesc 1359eventq_index=0 1360opClass=IntDiv 1361opLat=20 1362pipelined=false 1363 1364[system.cpu2.fuPool.FUList2] 1365type=FUDesc 1366children=opList0 opList1 opList2 1367count=4 1368eventq_index=0 1369opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 1370 1371[system.cpu2.fuPool.FUList2.opList0] 1372type=OpDesc 1373eventq_index=0 1374opClass=FloatAdd 1375opLat=2 1376pipelined=true 1377 1378[system.cpu2.fuPool.FUList2.opList1] 1379type=OpDesc 1380eventq_index=0 1381opClass=FloatCmp 1382opLat=2 1383pipelined=true 1384 1385[system.cpu2.fuPool.FUList2.opList2] 1386type=OpDesc 1387eventq_index=0 1388opClass=FloatCvt 1389opLat=2 1390pipelined=true 1391 1392[system.cpu2.fuPool.FUList3] 1393type=FUDesc	1411 1412[system.cpu2.dtb] 1413type=SparcTLB 1414eventq_index=0 1415size=64 1416 1417[system.cpu2.fuPool] 1418type=FUPool 1419children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1420FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 1421eventq_index=0 1422 1423[system.cpu2.fuPool.FUList0] 1424type=FUDesc 1425children=opList 1426count=6 1427eventq_index=0 1428opList=system.cpu2.fuPool.FUList0.opList 1429 1430[system.cpu2.fuPool.FUList0.opList] 1431type=OpDesc 1432eventq_index=0 1433opClass=IntAlu 1434opLat=1 1435pipelined=true 1436 1437[system.cpu2.fuPool.FUList1] 1438type=FUDesc 1439children=opList0 opList1 1440count=2 1441eventq_index=0 1442opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 1443 1444[system.cpu2.fuPool.FUList1.opList0] 1445type=OpDesc 1446eventq_index=0 1447opClass=IntMult 1448opLat=3 1449pipelined=true 1450 1451[system.cpu2.fuPool.FUList1.opList1] 1452type=OpDesc 1453eventq_index=0 1454opClass=IntDiv 1455opLat=20 1456pipelined=false 1457 1458[system.cpu2.fuPool.FUList2] 1459type=FUDesc 1460children=opList0 opList1 opList2 1461count=4 1462eventq_index=0 1463opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 1464 1465[system.cpu2.fuPool.FUList2.opList0] 1466type=OpDesc 1467eventq_index=0 1468opClass=FloatAdd 1469opLat=2 1470pipelined=true 1471 1472[system.cpu2.fuPool.FUList2.opList1] 1473type=OpDesc 1474eventq_index=0 1475opClass=FloatCmp 1476opLat=2 1477pipelined=true 1478 1479[system.cpu2.fuPool.FUList2.opList2] 1480type=OpDesc 1481eventq_index=0 1482opClass=FloatCvt 1483opLat=2 1484pipelined=true 1485 1486[system.cpu2.fuPool.FUList3] 1487type=FUDesc
1394children=opList0 opList1 opList2	1488children=opList0 opList1 opList2 opList3 opList4
1395count=2 1396eventq_index=0	1489count=2 1490eventq_index=0
1397opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2	1491opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 system.cpu2.fuPool.FUList3.opList3 system.cpu2.fuPool.FUList3.opList4
1398 1399[system.cpu2.fuPool.FUList3.opList0] 1400type=OpDesc 1401eventq_index=0 1402opClass=FloatMult 1403opLat=4 1404pipelined=true 1405 1406[system.cpu2.fuPool.FUList3.opList1] 1407type=OpDesc 1408eventq_index=0	1492 1493[system.cpu2.fuPool.FUList3.opList0] 1494type=OpDesc 1495eventq_index=0 1496opClass=FloatMult 1497opLat=4 1498pipelined=true 1499 1500[system.cpu2.fuPool.FUList3.opList1] 1501type=OpDesc 1502eventq_index=0
	1503opClass=FloatMultAcc 1504opLat=5 1505pipelined=true 1506 1507[system.cpu2.fuPool.FUList3.opList2] 1508type=OpDesc 1509eventq_index=0 1510opClass=FloatMisc 1511opLat=3 1512pipelined=true 1513 1514[system.cpu2.fuPool.FUList3.opList3] 1515type=OpDesc 1516eventq_index=0
1409opClass=FloatDiv 1410opLat=12 1411pipelined=false 1412	1517opClass=FloatDiv 1518opLat=12 1519pipelined=false 1520
1413[system.cpu2.fuPool.FUList3.opList2]	1521[system.cpu2.fuPool.FUList3.opList4]
1414type=OpDesc 1415eventq_index=0 1416opClass=FloatSqrt 1417opLat=24 1418pipelined=false 1419 1420[system.cpu2.fuPool.FUList4] 1421type=FUDesc	1522type=OpDesc 1523eventq_index=0 1524opClass=FloatSqrt 1525opLat=24 1526pipelined=false 1527 1528[system.cpu2.fuPool.FUList4] 1529type=FUDesc
1422children=opList	1530children=opList0 opList1
1423count=0 1424eventq_index=0	1531count=0 1532eventq_index=0
1425opList=system.cpu2.fuPool.FUList4.opList	1533opList=system.cpu2.fuPool.FUList4.opList0 system.cpu2.fuPool.FUList4.opList1
1426	1534
1427[system.cpu2.fuPool.FUList4.opList]	1535[system.cpu2.fuPool.FUList4.opList0]
1428type=OpDesc 1429eventq_index=0 1430opClass=MemRead 1431opLat=1 1432pipelined=true 1433	1536type=OpDesc 1537eventq_index=0 1538opClass=MemRead 1539opLat=1 1540pipelined=true 1541
	1542[system.cpu2.fuPool.FUList4.opList1] 1543type=OpDesc 1544eventq_index=0 1545opClass=FloatMemRead 1546opLat=1 1547pipelined=true 1548
1434[system.cpu2.fuPool.FUList5] 1435type=FUDesc 1436children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1437count=4 1438eventq_index=0 1439opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 1440 1441[system.cpu2.fuPool.FUList5.opList00] 1442type=OpDesc 1443eventq_index=0 1444opClass=SimdAdd 1445opLat=1 1446pipelined=true 1447 1448[system.cpu2.fuPool.FUList5.opList01] 1449type=OpDesc 1450eventq_index=0 1451opClass=SimdAddAcc 1452opLat=1 1453pipelined=true 1454 1455[system.cpu2.fuPool.FUList5.opList02] 1456type=OpDesc 1457eventq_index=0 1458opClass=SimdAlu 1459opLat=1 1460pipelined=true 1461 1462[system.cpu2.fuPool.FUList5.opList03] 1463type=OpDesc 1464eventq_index=0 1465opClass=SimdCmp 1466opLat=1 1467pipelined=true 1468 1469[system.cpu2.fuPool.FUList5.opList04] 1470type=OpDesc 1471eventq_index=0 1472opClass=SimdCvt 1473opLat=1 1474pipelined=true 1475 1476[system.cpu2.fuPool.FUList5.opList05] 1477type=OpDesc 1478eventq_index=0 1479opClass=SimdMisc 1480opLat=1 1481pipelined=true 1482 1483[system.cpu2.fuPool.FUList5.opList06] 1484type=OpDesc 1485eventq_index=0 1486opClass=SimdMult 1487opLat=1 1488pipelined=true 1489 1490[system.cpu2.fuPool.FUList5.opList07] 1491type=OpDesc 1492eventq_index=0 1493opClass=SimdMultAcc 1494opLat=1 1495pipelined=true 1496 1497[system.cpu2.fuPool.FUList5.opList08] 1498type=OpDesc 1499eventq_index=0 1500opClass=SimdShift 1501opLat=1 1502pipelined=true 1503 1504[system.cpu2.fuPool.FUList5.opList09] 1505type=OpDesc 1506eventq_index=0 1507opClass=SimdShiftAcc 1508opLat=1 1509pipelined=true 1510 1511[system.cpu2.fuPool.FUList5.opList10] 1512type=OpDesc 1513eventq_index=0 1514opClass=SimdSqrt 1515opLat=1 1516pipelined=true 1517 1518[system.cpu2.fuPool.FUList5.opList11] 1519type=OpDesc 1520eventq_index=0 1521opClass=SimdFloatAdd 1522opLat=1 1523pipelined=true 1524 1525[system.cpu2.fuPool.FUList5.opList12] 1526type=OpDesc 1527eventq_index=0 1528opClass=SimdFloatAlu 1529opLat=1 1530pipelined=true 1531 1532[system.cpu2.fuPool.FUList5.opList13] 1533type=OpDesc 1534eventq_index=0 1535opClass=SimdFloatCmp 1536opLat=1 1537pipelined=true 1538 1539[system.cpu2.fuPool.FUList5.opList14] 1540type=OpDesc 1541eventq_index=0 1542opClass=SimdFloatCvt 1543opLat=1 1544pipelined=true 1545 1546[system.cpu2.fuPool.FUList5.opList15] 1547type=OpDesc 1548eventq_index=0 1549opClass=SimdFloatDiv 1550opLat=1 1551pipelined=true 1552 1553[system.cpu2.fuPool.FUList5.opList16] 1554type=OpDesc 1555eventq_index=0 1556opClass=SimdFloatMisc 1557opLat=1 1558pipelined=true 1559 1560[system.cpu2.fuPool.FUList5.opList17] 1561type=OpDesc 1562eventq_index=0 1563opClass=SimdFloatMult 1564opLat=1 1565pipelined=true 1566 1567[system.cpu2.fuPool.FUList5.opList18] 1568type=OpDesc 1569eventq_index=0 1570opClass=SimdFloatMultAcc 1571opLat=1 1572pipelined=true 1573 1574[system.cpu2.fuPool.FUList5.opList19] 1575type=OpDesc 1576eventq_index=0 1577opClass=SimdFloatSqrt 1578opLat=1 1579pipelined=true 1580 1581[system.cpu2.fuPool.FUList6] 1582type=FUDesc	1549[system.cpu2.fuPool.FUList5] 1550type=FUDesc 1551children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1552count=4 1553eventq_index=0 1554opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 1555 1556[system.cpu2.fuPool.FUList5.opList00] 1557type=OpDesc 1558eventq_index=0 1559opClass=SimdAdd 1560opLat=1 1561pipelined=true 1562 1563[system.cpu2.fuPool.FUList5.opList01] 1564type=OpDesc 1565eventq_index=0 1566opClass=SimdAddAcc 1567opLat=1 1568pipelined=true 1569 1570[system.cpu2.fuPool.FUList5.opList02] 1571type=OpDesc 1572eventq_index=0 1573opClass=SimdAlu 1574opLat=1 1575pipelined=true 1576 1577[system.cpu2.fuPool.FUList5.opList03] 1578type=OpDesc 1579eventq_index=0 1580opClass=SimdCmp 1581opLat=1 1582pipelined=true 1583 1584[system.cpu2.fuPool.FUList5.opList04] 1585type=OpDesc 1586eventq_index=0 1587opClass=SimdCvt 1588opLat=1 1589pipelined=true 1590 1591[system.cpu2.fuPool.FUList5.opList05] 1592type=OpDesc 1593eventq_index=0 1594opClass=SimdMisc 1595opLat=1 1596pipelined=true 1597 1598[system.cpu2.fuPool.FUList5.opList06] 1599type=OpDesc 1600eventq_index=0 1601opClass=SimdMult 1602opLat=1 1603pipelined=true 1604 1605[system.cpu2.fuPool.FUList5.opList07] 1606type=OpDesc 1607eventq_index=0 1608opClass=SimdMultAcc 1609opLat=1 1610pipelined=true 1611 1612[system.cpu2.fuPool.FUList5.opList08] 1613type=OpDesc 1614eventq_index=0 1615opClass=SimdShift 1616opLat=1 1617pipelined=true 1618 1619[system.cpu2.fuPool.FUList5.opList09] 1620type=OpDesc 1621eventq_index=0 1622opClass=SimdShiftAcc 1623opLat=1 1624pipelined=true 1625 1626[system.cpu2.fuPool.FUList5.opList10] 1627type=OpDesc 1628eventq_index=0 1629opClass=SimdSqrt 1630opLat=1 1631pipelined=true 1632 1633[system.cpu2.fuPool.FUList5.opList11] 1634type=OpDesc 1635eventq_index=0 1636opClass=SimdFloatAdd 1637opLat=1 1638pipelined=true 1639 1640[system.cpu2.fuPool.FUList5.opList12] 1641type=OpDesc 1642eventq_index=0 1643opClass=SimdFloatAlu 1644opLat=1 1645pipelined=true 1646 1647[system.cpu2.fuPool.FUList5.opList13] 1648type=OpDesc 1649eventq_index=0 1650opClass=SimdFloatCmp 1651opLat=1 1652pipelined=true 1653 1654[system.cpu2.fuPool.FUList5.opList14] 1655type=OpDesc 1656eventq_index=0 1657opClass=SimdFloatCvt 1658opLat=1 1659pipelined=true 1660 1661[system.cpu2.fuPool.FUList5.opList15] 1662type=OpDesc 1663eventq_index=0 1664opClass=SimdFloatDiv 1665opLat=1 1666pipelined=true 1667 1668[system.cpu2.fuPool.FUList5.opList16] 1669type=OpDesc 1670eventq_index=0 1671opClass=SimdFloatMisc 1672opLat=1 1673pipelined=true 1674 1675[system.cpu2.fuPool.FUList5.opList17] 1676type=OpDesc 1677eventq_index=0 1678opClass=SimdFloatMult 1679opLat=1 1680pipelined=true 1681 1682[system.cpu2.fuPool.FUList5.opList18] 1683type=OpDesc 1684eventq_index=0 1685opClass=SimdFloatMultAcc 1686opLat=1 1687pipelined=true 1688 1689[system.cpu2.fuPool.FUList5.opList19] 1690type=OpDesc 1691eventq_index=0 1692opClass=SimdFloatSqrt 1693opLat=1 1694pipelined=true 1695 1696[system.cpu2.fuPool.FUList6] 1697type=FUDesc
1583children=opList	1698children=opList0 opList1
1584count=0 1585eventq_index=0	1699count=0 1700eventq_index=0
1586opList=system.cpu2.fuPool.FUList6.opList	1701opList=system.cpu2.fuPool.FUList6.opList0 system.cpu2.fuPool.FUList6.opList1
1587	1702
1588[system.cpu2.fuPool.FUList6.opList]	1703[system.cpu2.fuPool.FUList6.opList0]
1589type=OpDesc 1590eventq_index=0 1591opClass=MemWrite 1592opLat=1 1593pipelined=true 1594	1704type=OpDesc 1705eventq_index=0 1706opClass=MemWrite 1707opLat=1 1708pipelined=true 1709
	1710[system.cpu2.fuPool.FUList6.opList1] 1711type=OpDesc 1712eventq_index=0 1713opClass=FloatMemWrite 1714opLat=1 1715pipelined=true 1716
1595[system.cpu2.fuPool.FUList7] 1596type=FUDesc	1717[system.cpu2.fuPool.FUList7] 1718type=FUDesc
1597children=opList0 opList1	1719children=opList0 opList1 opList2 opList3
1598count=4 1599eventq_index=0	1720count=4 1721eventq_index=0
1600opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1	1722opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 system.cpu2.fuPool.FUList7.opList2 system.cpu2.fuPool.FUList7.opList3
1601 1602[system.cpu2.fuPool.FUList7.opList0] 1603type=OpDesc 1604eventq_index=0 1605opClass=MemRead 1606opLat=1 1607pipelined=true 1608 1609[system.cpu2.fuPool.FUList7.opList1] 1610type=OpDesc 1611eventq_index=0 1612opClass=MemWrite 1613opLat=1 1614pipelined=true 1615	1723 1724[system.cpu2.fuPool.FUList7.opList0] 1725type=OpDesc 1726eventq_index=0 1727opClass=MemRead 1728opLat=1 1729pipelined=true 1730 1731[system.cpu2.fuPool.FUList7.opList1] 1732type=OpDesc 1733eventq_index=0 1734opClass=MemWrite 1735opLat=1 1736pipelined=true 1737
	1738[system.cpu2.fuPool.FUList7.opList2] 1739type=OpDesc 1740eventq_index=0 1741opClass=FloatMemRead 1742opLat=1 1743pipelined=true 1744 1745[system.cpu2.fuPool.FUList7.opList3] 1746type=OpDesc 1747eventq_index=0 1748opClass=FloatMemWrite 1749opLat=1 1750pipelined=true 1751
1616[system.cpu2.fuPool.FUList8] 1617type=FUDesc 1618children=opList 1619count=1 1620eventq_index=0 1621opList=system.cpu2.fuPool.FUList8.opList 1622 1623[system.cpu2.fuPool.FUList8.opList] 1624type=OpDesc 1625eventq_index=0 1626opClass=IprAccess 1627opLat=3 1628pipelined=false 1629 1630[system.cpu2.icache] 1631type=Cache 1632children=tags 1633addr_ranges=0:18446744073709551615:0:0:0:0 1634assoc=1 1635clk_domain=system.cpu_clk_domain 1636clusivity=mostly_incl	1752[system.cpu2.fuPool.FUList8] 1753type=FUDesc 1754children=opList 1755count=1 1756eventq_index=0 1757opList=system.cpu2.fuPool.FUList8.opList 1758 1759[system.cpu2.fuPool.FUList8.opList] 1760type=OpDesc 1761eventq_index=0 1762opClass=IprAccess 1763opLat=3 1764pipelined=false 1765 1766[system.cpu2.icache] 1767type=Cache 1768children=tags 1769addr_ranges=0:18446744073709551615:0:0:0:0 1770assoc=1 1771clk_domain=system.cpu_clk_domain 1772clusivity=mostly_incl
	1773data_latency=2
1637default_p_state=UNDEFINED 1638demand_mshr_reserve=1 1639eventq_index=0	1774default_p_state=UNDEFINED 1775demand_mshr_reserve=1 1776eventq_index=0
1640hit_latency=2
1641is_read_only=true 1642max_miss_count=0 1643mshrs=4 1644p_state_clk_gate_bins=20 1645p_state_clk_gate_max=1000000000000 1646p_state_clk_gate_min=1000 1647power_model=Null 1648prefetch_on_access=false 1649prefetcher=Null 1650response_latency=2 1651sequential_access=false 1652size=32768 1653system=system	1777is_read_only=true 1778max_miss_count=0 1779mshrs=4 1780p_state_clk_gate_bins=20 1781p_state_clk_gate_max=1000000000000 1782p_state_clk_gate_min=1000 1783power_model=Null 1784prefetch_on_access=false 1785prefetcher=Null 1786response_latency=2 1787sequential_access=false 1788size=32768 1789system=system
	1790tag_latency=2
1654tags=system.cpu2.icache.tags 1655tgts_per_mshr=20 1656write_buffers=8 1657writeback_clean=true 1658cpu_side=system.cpu2.icache_port 1659mem_side=system.toL2Bus.slave[4] 1660 1661[system.cpu2.icache.tags] 1662type=LRU 1663assoc=1 1664block_size=64 1665clk_domain=system.cpu_clk_domain	1791tags=system.cpu2.icache.tags 1792tgts_per_mshr=20 1793write_buffers=8 1794writeback_clean=true 1795cpu_side=system.cpu2.icache_port 1796mem_side=system.toL2Bus.slave[4] 1797 1798[system.cpu2.icache.tags] 1799type=LRU 1800assoc=1 1801block_size=64 1802clk_domain=system.cpu_clk_domain
	1803data_latency=2
1666default_p_state=UNDEFINED 1667eventq_index=0	1804default_p_state=UNDEFINED 1805eventq_index=0
1668hit_latency=2
1669p_state_clk_gate_bins=20 1670p_state_clk_gate_max=1000000000000 1671p_state_clk_gate_min=1000 1672power_model=Null 1673sequential_access=false 1674size=32768	1806p_state_clk_gate_bins=20 1807p_state_clk_gate_max=1000000000000 1808p_state_clk_gate_min=1000 1809power_model=Null 1810sequential_access=false 1811size=32768
	1812tag_latency=2
1675 1676[system.cpu2.interrupts] 1677type=SparcInterrupts 1678eventq_index=0 1679 1680[system.cpu2.isa] 1681type=SparcISA 1682eventq_index=0 1683 1684[system.cpu2.itb] 1685type=SparcTLB 1686eventq_index=0 1687size=64 1688 1689[system.cpu2.tracer] 1690type=ExeTracer 1691eventq_index=0 1692 1693[system.cpu3] 1694type=DerivO3CPU 1695children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1696LFSTSize=1024 1697LQEntries=32 1698LSQCheckLoads=true 1699LSQDepCheckShift=4 1700SQEntries=32 1701SSITSize=1024 1702activity=0 1703backComSize=5 1704branchPred=system.cpu3.branchPred 1705cachePorts=200 1706checker=Null 1707clk_domain=system.cpu_clk_domain 1708commitToDecodeDelay=1 1709commitToFetchDelay=1 1710commitToIEWDelay=1 1711commitToRenameDelay=1 1712commitWidth=8 1713cpu_id=3 1714decodeToFetchDelay=1 1715decodeToRenameDelay=1 1716decodeWidth=8 1717default_p_state=UNDEFINED 1718dispatchWidth=8 1719do_checkpoint_insts=true 1720do_quiesce=true 1721do_statistics_insts=true 1722dtb=system.cpu3.dtb 1723eventq_index=0 1724fetchBufferSize=64 1725fetchQueueSize=32 1726fetchToDecodeDelay=1 1727fetchTrapLatency=1 1728fetchWidth=8 1729forwardComSize=5 1730fuPool=system.cpu3.fuPool 1731function_trace=false 1732function_trace_start=0 1733iewToCommitDelay=1 1734iewToDecodeDelay=1 1735iewToFetchDelay=1 1736iewToRenameDelay=1 1737interrupts=system.cpu3.interrupts 1738isa=system.cpu3.isa 1739issueToExecuteDelay=1 1740issueWidth=8 1741itb=system.cpu3.itb 1742max_insts_all_threads=0 1743max_insts_any_thread=0 1744max_loads_all_threads=0 1745max_loads_any_thread=0 1746needsTSO=false 1747numIQEntries=64 1748numPhysCCRegs=0 1749numPhysFloatRegs=256 1750numPhysIntRegs=256 1751numROBEntries=192 1752numRobs=1 1753numThreads=1 1754p_state_clk_gate_bins=20 1755p_state_clk_gate_max=1000000000000 1756p_state_clk_gate_min=1000 1757power_model=Null 1758profile=0 1759progress_interval=0 1760renameToDecodeDelay=1 1761renameToFetchDelay=1 1762renameToIEWDelay=2 1763renameToROBDelay=1 1764renameWidth=8 1765simpoint_start_insts= 1766smtCommitPolicy=RoundRobin 1767smtFetchPolicy=SingleThread 1768smtIQPolicy=Partitioned 1769smtIQThreshold=100 1770smtLSQPolicy=Partitioned 1771smtLSQThreshold=100 1772smtNumFetchingThreads=1 1773smtROBPolicy=Partitioned 1774smtROBThreshold=100 1775socket_id=0 1776squashWidth=8 1777store_set_clear_period=250000 1778switched_out=false 1779system=system 1780tracer=system.cpu3.tracer 1781trapLatency=13 1782wbWidth=8 1783workload=system.cpu0.workload 1784dcache_port=system.cpu3.dcache.cpu_side 1785icache_port=system.cpu3.icache.cpu_side 1786 1787[system.cpu3.branchPred] 1788type=TournamentBP 1789BTBEntries=4096 1790BTBTagSize=16 1791RASSize=16 1792choiceCtrBits=2 1793choicePredictorSize=8192 1794eventq_index=0 1795globalCtrBits=2 1796globalPredictorSize=8192 1797indirectHashGHR=true 1798indirectHashTargets=true 1799indirectPathLength=3 1800indirectSets=256 1801indirectTagSize=16 1802indirectWays=2 1803instShiftAmt=2 1804localCtrBits=2 1805localHistoryTableSize=2048 1806localPredictorSize=2048 1807numThreads=1 1808useIndirect=true 1809 1810[system.cpu3.dcache] 1811type=Cache 1812children=tags 1813addr_ranges=0:18446744073709551615:0:0:0:0 1814assoc=4 1815clk_domain=system.cpu_clk_domain 1816clusivity=mostly_incl	1813 1814[system.cpu2.interrupts] 1815type=SparcInterrupts 1816eventq_index=0 1817 1818[system.cpu2.isa] 1819type=SparcISA 1820eventq_index=0 1821 1822[system.cpu2.itb] 1823type=SparcTLB 1824eventq_index=0 1825size=64 1826 1827[system.cpu2.tracer] 1828type=ExeTracer 1829eventq_index=0 1830 1831[system.cpu3] 1832type=DerivO3CPU 1833children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1834LFSTSize=1024 1835LQEntries=32 1836LSQCheckLoads=true 1837LSQDepCheckShift=4 1838SQEntries=32 1839SSITSize=1024 1840activity=0 1841backComSize=5 1842branchPred=system.cpu3.branchPred 1843cachePorts=200 1844checker=Null 1845clk_domain=system.cpu_clk_domain 1846commitToDecodeDelay=1 1847commitToFetchDelay=1 1848commitToIEWDelay=1 1849commitToRenameDelay=1 1850commitWidth=8 1851cpu_id=3 1852decodeToFetchDelay=1 1853decodeToRenameDelay=1 1854decodeWidth=8 1855default_p_state=UNDEFINED 1856dispatchWidth=8 1857do_checkpoint_insts=true 1858do_quiesce=true 1859do_statistics_insts=true 1860dtb=system.cpu3.dtb 1861eventq_index=0 1862fetchBufferSize=64 1863fetchQueueSize=32 1864fetchToDecodeDelay=1 1865fetchTrapLatency=1 1866fetchWidth=8 1867forwardComSize=5 1868fuPool=system.cpu3.fuPool 1869function_trace=false 1870function_trace_start=0 1871iewToCommitDelay=1 1872iewToDecodeDelay=1 1873iewToFetchDelay=1 1874iewToRenameDelay=1 1875interrupts=system.cpu3.interrupts 1876isa=system.cpu3.isa 1877issueToExecuteDelay=1 1878issueWidth=8 1879itb=system.cpu3.itb 1880max_insts_all_threads=0 1881max_insts_any_thread=0 1882max_loads_all_threads=0 1883max_loads_any_thread=0 1884needsTSO=false 1885numIQEntries=64 1886numPhysCCRegs=0 1887numPhysFloatRegs=256 1888numPhysIntRegs=256 1889numROBEntries=192 1890numRobs=1 1891numThreads=1 1892p_state_clk_gate_bins=20 1893p_state_clk_gate_max=1000000000000 1894p_state_clk_gate_min=1000 1895power_model=Null 1896profile=0 1897progress_interval=0 1898renameToDecodeDelay=1 1899renameToFetchDelay=1 1900renameToIEWDelay=2 1901renameToROBDelay=1 1902renameWidth=8 1903simpoint_start_insts= 1904smtCommitPolicy=RoundRobin 1905smtFetchPolicy=SingleThread 1906smtIQPolicy=Partitioned 1907smtIQThreshold=100 1908smtLSQPolicy=Partitioned 1909smtLSQThreshold=100 1910smtNumFetchingThreads=1 1911smtROBPolicy=Partitioned 1912smtROBThreshold=100 1913socket_id=0 1914squashWidth=8 1915store_set_clear_period=250000 1916switched_out=false 1917system=system 1918tracer=system.cpu3.tracer 1919trapLatency=13 1920wbWidth=8 1921workload=system.cpu0.workload 1922dcache_port=system.cpu3.dcache.cpu_side 1923icache_port=system.cpu3.icache.cpu_side 1924 1925[system.cpu3.branchPred] 1926type=TournamentBP 1927BTBEntries=4096 1928BTBTagSize=16 1929RASSize=16 1930choiceCtrBits=2 1931choicePredictorSize=8192 1932eventq_index=0 1933globalCtrBits=2 1934globalPredictorSize=8192 1935indirectHashGHR=true 1936indirectHashTargets=true 1937indirectPathLength=3 1938indirectSets=256 1939indirectTagSize=16 1940indirectWays=2 1941instShiftAmt=2 1942localCtrBits=2 1943localHistoryTableSize=2048 1944localPredictorSize=2048 1945numThreads=1 1946useIndirect=true 1947 1948[system.cpu3.dcache] 1949type=Cache 1950children=tags 1951addr_ranges=0:18446744073709551615:0:0:0:0 1952assoc=4 1953clk_domain=system.cpu_clk_domain 1954clusivity=mostly_incl
	1955data_latency=2
1817default_p_state=UNDEFINED 1818demand_mshr_reserve=1 1819eventq_index=0	1956default_p_state=UNDEFINED 1957demand_mshr_reserve=1 1958eventq_index=0
1820hit_latency=2
1821is_read_only=false 1822max_miss_count=0 1823mshrs=4 1824p_state_clk_gate_bins=20 1825p_state_clk_gate_max=1000000000000 1826p_state_clk_gate_min=1000 1827power_model=Null 1828prefetch_on_access=false 1829prefetcher=Null 1830response_latency=2 1831sequential_access=false 1832size=32768 1833system=system	1959is_read_only=false 1960max_miss_count=0 1961mshrs=4 1962p_state_clk_gate_bins=20 1963p_state_clk_gate_max=1000000000000 1964p_state_clk_gate_min=1000 1965power_model=Null 1966prefetch_on_access=false 1967prefetcher=Null 1968response_latency=2 1969sequential_access=false 1970size=32768 1971system=system
	1972tag_latency=2
1834tags=system.cpu3.dcache.tags 1835tgts_per_mshr=20 1836write_buffers=8 1837writeback_clean=false 1838cpu_side=system.cpu3.dcache_port 1839mem_side=system.toL2Bus.slave[7] 1840 1841[system.cpu3.dcache.tags] 1842type=LRU 1843assoc=4 1844block_size=64 1845clk_domain=system.cpu_clk_domain	1973tags=system.cpu3.dcache.tags 1974tgts_per_mshr=20 1975write_buffers=8 1976writeback_clean=false 1977cpu_side=system.cpu3.dcache_port 1978mem_side=system.toL2Bus.slave[7] 1979 1980[system.cpu3.dcache.tags] 1981type=LRU 1982assoc=4 1983block_size=64 1984clk_domain=system.cpu_clk_domain
	1985data_latency=2
1846default_p_state=UNDEFINED 1847eventq_index=0	1986default_p_state=UNDEFINED 1987eventq_index=0
1848hit_latency=2
1849p_state_clk_gate_bins=20 1850p_state_clk_gate_max=1000000000000 1851p_state_clk_gate_min=1000 1852power_model=Null 1853sequential_access=false 1854size=32768	1988p_state_clk_gate_bins=20 1989p_state_clk_gate_max=1000000000000 1990p_state_clk_gate_min=1000 1991power_model=Null 1992sequential_access=false 1993size=32768
	1994tag_latency=2
1855 1856[system.cpu3.dtb] 1857type=SparcTLB 1858eventq_index=0 1859size=64 1860 1861[system.cpu3.fuPool] 1862type=FUPool 1863children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1864FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 1865eventq_index=0 1866 1867[system.cpu3.fuPool.FUList0] 1868type=FUDesc 1869children=opList 1870count=6 1871eventq_index=0 1872opList=system.cpu3.fuPool.FUList0.opList 1873 1874[system.cpu3.fuPool.FUList0.opList] 1875type=OpDesc 1876eventq_index=0 1877opClass=IntAlu 1878opLat=1 1879pipelined=true 1880 1881[system.cpu3.fuPool.FUList1] 1882type=FUDesc 1883children=opList0 opList1 1884count=2 1885eventq_index=0 1886opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 1887 1888[system.cpu3.fuPool.FUList1.opList0] 1889type=OpDesc 1890eventq_index=0 1891opClass=IntMult 1892opLat=3 1893pipelined=true 1894 1895[system.cpu3.fuPool.FUList1.opList1] 1896type=OpDesc 1897eventq_index=0 1898opClass=IntDiv 1899opLat=20 1900pipelined=false 1901 1902[system.cpu3.fuPool.FUList2] 1903type=FUDesc 1904children=opList0 opList1 opList2 1905count=4 1906eventq_index=0 1907opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 1908 1909[system.cpu3.fuPool.FUList2.opList0] 1910type=OpDesc 1911eventq_index=0 1912opClass=FloatAdd 1913opLat=2 1914pipelined=true 1915 1916[system.cpu3.fuPool.FUList2.opList1] 1917type=OpDesc 1918eventq_index=0 1919opClass=FloatCmp 1920opLat=2 1921pipelined=true 1922 1923[system.cpu3.fuPool.FUList2.opList2] 1924type=OpDesc 1925eventq_index=0 1926opClass=FloatCvt 1927opLat=2 1928pipelined=true 1929 1930[system.cpu3.fuPool.FUList3] 1931type=FUDesc	1995 1996[system.cpu3.dtb] 1997type=SparcTLB 1998eventq_index=0 1999size=64 2000 2001[system.cpu3.fuPool] 2002type=FUPool 2003children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 2004FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 2005eventq_index=0 2006 2007[system.cpu3.fuPool.FUList0] 2008type=FUDesc 2009children=opList 2010count=6 2011eventq_index=0 2012opList=system.cpu3.fuPool.FUList0.opList 2013 2014[system.cpu3.fuPool.FUList0.opList] 2015type=OpDesc 2016eventq_index=0 2017opClass=IntAlu 2018opLat=1 2019pipelined=true 2020 2021[system.cpu3.fuPool.FUList1] 2022type=FUDesc 2023children=opList0 opList1 2024count=2 2025eventq_index=0 2026opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 2027 2028[system.cpu3.fuPool.FUList1.opList0] 2029type=OpDesc 2030eventq_index=0 2031opClass=IntMult 2032opLat=3 2033pipelined=true 2034 2035[system.cpu3.fuPool.FUList1.opList1] 2036type=OpDesc 2037eventq_index=0 2038opClass=IntDiv 2039opLat=20 2040pipelined=false 2041 2042[system.cpu3.fuPool.FUList2] 2043type=FUDesc 2044children=opList0 opList1 opList2 2045count=4 2046eventq_index=0 2047opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 2048 2049[system.cpu3.fuPool.FUList2.opList0] 2050type=OpDesc 2051eventq_index=0 2052opClass=FloatAdd 2053opLat=2 2054pipelined=true 2055 2056[system.cpu3.fuPool.FUList2.opList1] 2057type=OpDesc 2058eventq_index=0 2059opClass=FloatCmp 2060opLat=2 2061pipelined=true 2062 2063[system.cpu3.fuPool.FUList2.opList2] 2064type=OpDesc 2065eventq_index=0 2066opClass=FloatCvt 2067opLat=2 2068pipelined=true 2069 2070[system.cpu3.fuPool.FUList3] 2071type=FUDesc
1932children=opList0 opList1 opList2	2072children=opList0 opList1 opList2 opList3 opList4
1933count=2 1934eventq_index=0	2073count=2 2074eventq_index=0
1935opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2	2075opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 system.cpu3.fuPool.FUList3.opList3 system.cpu3.fuPool.FUList3.opList4
1936 1937[system.cpu3.fuPool.FUList3.opList0] 1938type=OpDesc 1939eventq_index=0 1940opClass=FloatMult 1941opLat=4 1942pipelined=true 1943 1944[system.cpu3.fuPool.FUList3.opList1] 1945type=OpDesc 1946eventq_index=0	2076 2077[system.cpu3.fuPool.FUList3.opList0] 2078type=OpDesc 2079eventq_index=0 2080opClass=FloatMult 2081opLat=4 2082pipelined=true 2083 2084[system.cpu3.fuPool.FUList3.opList1] 2085type=OpDesc 2086eventq_index=0
	2087opClass=FloatMultAcc 2088opLat=5 2089pipelined=true 2090 2091[system.cpu3.fuPool.FUList3.opList2] 2092type=OpDesc 2093eventq_index=0 2094opClass=FloatMisc 2095opLat=3 2096pipelined=true 2097 2098[system.cpu3.fuPool.FUList3.opList3] 2099type=OpDesc 2100eventq_index=0
1947opClass=FloatDiv 1948opLat=12 1949pipelined=false 1950	2101opClass=FloatDiv 2102opLat=12 2103pipelined=false 2104
1951[system.cpu3.fuPool.FUList3.opList2]	2105[system.cpu3.fuPool.FUList3.opList4]
1952type=OpDesc 1953eventq_index=0 1954opClass=FloatSqrt 1955opLat=24 1956pipelined=false 1957 1958[system.cpu3.fuPool.FUList4] 1959type=FUDesc	2106type=OpDesc 2107eventq_index=0 2108opClass=FloatSqrt 2109opLat=24 2110pipelined=false 2111 2112[system.cpu3.fuPool.FUList4] 2113type=FUDesc
1960children=opList	2114children=opList0 opList1
1961count=0 1962eventq_index=0	2115count=0 2116eventq_index=0
1963opList=system.cpu3.fuPool.FUList4.opList	2117opList=system.cpu3.fuPool.FUList4.opList0 system.cpu3.fuPool.FUList4.opList1
1964	2118
1965[system.cpu3.fuPool.FUList4.opList]	2119[system.cpu3.fuPool.FUList4.opList0]
1966type=OpDesc 1967eventq_index=0 1968opClass=MemRead 1969opLat=1 1970pipelined=true 1971	2120type=OpDesc 2121eventq_index=0 2122opClass=MemRead 2123opLat=1 2124pipelined=true 2125
	2126[system.cpu3.fuPool.FUList4.opList1] 2127type=OpDesc 2128eventq_index=0 2129opClass=FloatMemRead 2130opLat=1 2131pipelined=true 2132
1972[system.cpu3.fuPool.FUList5] 1973type=FUDesc 1974children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1975count=4 1976eventq_index=0 1977opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 1978 1979[system.cpu3.fuPool.FUList5.opList00] 1980type=OpDesc 1981eventq_index=0 1982opClass=SimdAdd 1983opLat=1 1984pipelined=true 1985 1986[system.cpu3.fuPool.FUList5.opList01] 1987type=OpDesc 1988eventq_index=0 1989opClass=SimdAddAcc 1990opLat=1 1991pipelined=true 1992 1993[system.cpu3.fuPool.FUList5.opList02] 1994type=OpDesc 1995eventq_index=0 1996opClass=SimdAlu 1997opLat=1 1998pipelined=true 1999 2000[system.cpu3.fuPool.FUList5.opList03] 2001type=OpDesc 2002eventq_index=0 2003opClass=SimdCmp 2004opLat=1 2005pipelined=true 2006 2007[system.cpu3.fuPool.FUList5.opList04] 2008type=OpDesc 2009eventq_index=0 2010opClass=SimdCvt 2011opLat=1 2012pipelined=true 2013 2014[system.cpu3.fuPool.FUList5.opList05] 2015type=OpDesc 2016eventq_index=0 2017opClass=SimdMisc 2018opLat=1 2019pipelined=true 2020 2021[system.cpu3.fuPool.FUList5.opList06] 2022type=OpDesc 2023eventq_index=0 2024opClass=SimdMult 2025opLat=1 2026pipelined=true 2027 2028[system.cpu3.fuPool.FUList5.opList07] 2029type=OpDesc 2030eventq_index=0 2031opClass=SimdMultAcc 2032opLat=1 2033pipelined=true 2034 2035[system.cpu3.fuPool.FUList5.opList08] 2036type=OpDesc 2037eventq_index=0 2038opClass=SimdShift 2039opLat=1 2040pipelined=true 2041 2042[system.cpu3.fuPool.FUList5.opList09] 2043type=OpDesc 2044eventq_index=0 2045opClass=SimdShiftAcc 2046opLat=1 2047pipelined=true 2048 2049[system.cpu3.fuPool.FUList5.opList10] 2050type=OpDesc 2051eventq_index=0 2052opClass=SimdSqrt 2053opLat=1 2054pipelined=true 2055 2056[system.cpu3.fuPool.FUList5.opList11] 2057type=OpDesc 2058eventq_index=0 2059opClass=SimdFloatAdd 2060opLat=1 2061pipelined=true 2062 2063[system.cpu3.fuPool.FUList5.opList12] 2064type=OpDesc 2065eventq_index=0 2066opClass=SimdFloatAlu 2067opLat=1 2068pipelined=true 2069 2070[system.cpu3.fuPool.FUList5.opList13] 2071type=OpDesc 2072eventq_index=0 2073opClass=SimdFloatCmp 2074opLat=1 2075pipelined=true 2076 2077[system.cpu3.fuPool.FUList5.opList14] 2078type=OpDesc 2079eventq_index=0 2080opClass=SimdFloatCvt 2081opLat=1 2082pipelined=true 2083 2084[system.cpu3.fuPool.FUList5.opList15] 2085type=OpDesc 2086eventq_index=0 2087opClass=SimdFloatDiv 2088opLat=1 2089pipelined=true 2090 2091[system.cpu3.fuPool.FUList5.opList16] 2092type=OpDesc 2093eventq_index=0 2094opClass=SimdFloatMisc 2095opLat=1 2096pipelined=true 2097 2098[system.cpu3.fuPool.FUList5.opList17] 2099type=OpDesc 2100eventq_index=0 2101opClass=SimdFloatMult 2102opLat=1 2103pipelined=true 2104 2105[system.cpu3.fuPool.FUList5.opList18] 2106type=OpDesc 2107eventq_index=0 2108opClass=SimdFloatMultAcc 2109opLat=1 2110pipelined=true 2111 2112[system.cpu3.fuPool.FUList5.opList19] 2113type=OpDesc 2114eventq_index=0 2115opClass=SimdFloatSqrt 2116opLat=1 2117pipelined=true 2118 2119[system.cpu3.fuPool.FUList6] 2120type=FUDesc	2133[system.cpu3.fuPool.FUList5] 2134type=FUDesc 2135children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 2136count=4 2137eventq_index=0 2138opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 2139 2140[system.cpu3.fuPool.FUList5.opList00] 2141type=OpDesc 2142eventq_index=0 2143opClass=SimdAdd 2144opLat=1 2145pipelined=true 2146 2147[system.cpu3.fuPool.FUList5.opList01] 2148type=OpDesc 2149eventq_index=0 2150opClass=SimdAddAcc 2151opLat=1 2152pipelined=true 2153 2154[system.cpu3.fuPool.FUList5.opList02] 2155type=OpDesc 2156eventq_index=0 2157opClass=SimdAlu 2158opLat=1 2159pipelined=true 2160 2161[system.cpu3.fuPool.FUList5.opList03] 2162type=OpDesc 2163eventq_index=0 2164opClass=SimdCmp 2165opLat=1 2166pipelined=true 2167 2168[system.cpu3.fuPool.FUList5.opList04] 2169type=OpDesc 2170eventq_index=0 2171opClass=SimdCvt 2172opLat=1 2173pipelined=true 2174 2175[system.cpu3.fuPool.FUList5.opList05] 2176type=OpDesc 2177eventq_index=0 2178opClass=SimdMisc 2179opLat=1 2180pipelined=true 2181 2182[system.cpu3.fuPool.FUList5.opList06] 2183type=OpDesc 2184eventq_index=0 2185opClass=SimdMult 2186opLat=1 2187pipelined=true 2188 2189[system.cpu3.fuPool.FUList5.opList07] 2190type=OpDesc 2191eventq_index=0 2192opClass=SimdMultAcc 2193opLat=1 2194pipelined=true 2195 2196[system.cpu3.fuPool.FUList5.opList08] 2197type=OpDesc 2198eventq_index=0 2199opClass=SimdShift 2200opLat=1 2201pipelined=true 2202 2203[system.cpu3.fuPool.FUList5.opList09] 2204type=OpDesc 2205eventq_index=0 2206opClass=SimdShiftAcc 2207opLat=1 2208pipelined=true 2209 2210[system.cpu3.fuPool.FUList5.opList10] 2211type=OpDesc 2212eventq_index=0 2213opClass=SimdSqrt 2214opLat=1 2215pipelined=true 2216 2217[system.cpu3.fuPool.FUList5.opList11] 2218type=OpDesc 2219eventq_index=0 2220opClass=SimdFloatAdd 2221opLat=1 2222pipelined=true 2223 2224[system.cpu3.fuPool.FUList5.opList12] 2225type=OpDesc 2226eventq_index=0 2227opClass=SimdFloatAlu 2228opLat=1 2229pipelined=true 2230 2231[system.cpu3.fuPool.FUList5.opList13] 2232type=OpDesc 2233eventq_index=0 2234opClass=SimdFloatCmp 2235opLat=1 2236pipelined=true 2237 2238[system.cpu3.fuPool.FUList5.opList14] 2239type=OpDesc 2240eventq_index=0 2241opClass=SimdFloatCvt 2242opLat=1 2243pipelined=true 2244 2245[system.cpu3.fuPool.FUList5.opList15] 2246type=OpDesc 2247eventq_index=0 2248opClass=SimdFloatDiv 2249opLat=1 2250pipelined=true 2251 2252[system.cpu3.fuPool.FUList5.opList16] 2253type=OpDesc 2254eventq_index=0 2255opClass=SimdFloatMisc 2256opLat=1 2257pipelined=true 2258 2259[system.cpu3.fuPool.FUList5.opList17] 2260type=OpDesc 2261eventq_index=0 2262opClass=SimdFloatMult 2263opLat=1 2264pipelined=true 2265 2266[system.cpu3.fuPool.FUList5.opList18] 2267type=OpDesc 2268eventq_index=0 2269opClass=SimdFloatMultAcc 2270opLat=1 2271pipelined=true 2272 2273[system.cpu3.fuPool.FUList5.opList19] 2274type=OpDesc 2275eventq_index=0 2276opClass=SimdFloatSqrt 2277opLat=1 2278pipelined=true 2279 2280[system.cpu3.fuPool.FUList6] 2281type=FUDesc
2121children=opList	2282children=opList0 opList1
2122count=0 2123eventq_index=0	2283count=0 2284eventq_index=0
2124opList=system.cpu3.fuPool.FUList6.opList	2285opList=system.cpu3.fuPool.FUList6.opList0 system.cpu3.fuPool.FUList6.opList1
2125	2286
2126[system.cpu3.fuPool.FUList6.opList]	2287[system.cpu3.fuPool.FUList6.opList0]
2127type=OpDesc 2128eventq_index=0 2129opClass=MemWrite 2130opLat=1 2131pipelined=true 2132	2288type=OpDesc 2289eventq_index=0 2290opClass=MemWrite 2291opLat=1 2292pipelined=true 2293
	2294[system.cpu3.fuPool.FUList6.opList1] 2295type=OpDesc 2296eventq_index=0 2297opClass=FloatMemWrite 2298opLat=1 2299pipelined=true 2300
2133[system.cpu3.fuPool.FUList7] 2134type=FUDesc	2301[system.cpu3.fuPool.FUList7] 2302type=FUDesc
2135children=opList0 opList1	2303children=opList0 opList1 opList2 opList3
2136count=4 2137eventq_index=0	2304count=4 2305eventq_index=0
2138opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1	2306opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 system.cpu3.fuPool.FUList7.opList2 system.cpu3.fuPool.FUList7.opList3
2139 2140[system.cpu3.fuPool.FUList7.opList0] 2141type=OpDesc 2142eventq_index=0 2143opClass=MemRead 2144opLat=1 2145pipelined=true 2146 2147[system.cpu3.fuPool.FUList7.opList1] 2148type=OpDesc 2149eventq_index=0 2150opClass=MemWrite 2151opLat=1 2152pipelined=true 2153	2307 2308[system.cpu3.fuPool.FUList7.opList0] 2309type=OpDesc 2310eventq_index=0 2311opClass=MemRead 2312opLat=1 2313pipelined=true 2314 2315[system.cpu3.fuPool.FUList7.opList1] 2316type=OpDesc 2317eventq_index=0 2318opClass=MemWrite 2319opLat=1 2320pipelined=true 2321
	2322[system.cpu3.fuPool.FUList7.opList2] 2323type=OpDesc 2324eventq_index=0 2325opClass=FloatMemRead 2326opLat=1 2327pipelined=true 2328 2329[system.cpu3.fuPool.FUList7.opList3] 2330type=OpDesc 2331eventq_index=0 2332opClass=FloatMemWrite 2333opLat=1 2334pipelined=true 2335
2154[system.cpu3.fuPool.FUList8] 2155type=FUDesc 2156children=opList 2157count=1 2158eventq_index=0 2159opList=system.cpu3.fuPool.FUList8.opList 2160 2161[system.cpu3.fuPool.FUList8.opList] 2162type=OpDesc 2163eventq_index=0 2164opClass=IprAccess 2165opLat=3 2166pipelined=false 2167 2168[system.cpu3.icache] 2169type=Cache 2170children=tags 2171addr_ranges=0:18446744073709551615:0:0:0:0 2172assoc=1 2173clk_domain=system.cpu_clk_domain 2174clusivity=mostly_incl	2336[system.cpu3.fuPool.FUList8] 2337type=FUDesc 2338children=opList 2339count=1 2340eventq_index=0 2341opList=system.cpu3.fuPool.FUList8.opList 2342 2343[system.cpu3.fuPool.FUList8.opList] 2344type=OpDesc 2345eventq_index=0 2346opClass=IprAccess 2347opLat=3 2348pipelined=false 2349 2350[system.cpu3.icache] 2351type=Cache 2352children=tags 2353addr_ranges=0:18446744073709551615:0:0:0:0 2354assoc=1 2355clk_domain=system.cpu_clk_domain 2356clusivity=mostly_incl
	2357data_latency=2
2175default_p_state=UNDEFINED 2176demand_mshr_reserve=1 2177eventq_index=0	2358default_p_state=UNDEFINED 2359demand_mshr_reserve=1 2360eventq_index=0
2178hit_latency=2
2179is_read_only=true 2180max_miss_count=0 2181mshrs=4 2182p_state_clk_gate_bins=20 2183p_state_clk_gate_max=1000000000000 2184p_state_clk_gate_min=1000 2185power_model=Null 2186prefetch_on_access=false 2187prefetcher=Null 2188response_latency=2 2189sequential_access=false 2190size=32768 2191system=system	2361is_read_only=true 2362max_miss_count=0 2363mshrs=4 2364p_state_clk_gate_bins=20 2365p_state_clk_gate_max=1000000000000 2366p_state_clk_gate_min=1000 2367power_model=Null 2368prefetch_on_access=false 2369prefetcher=Null 2370response_latency=2 2371sequential_access=false 2372size=32768 2373system=system
	2374tag_latency=2
2192tags=system.cpu3.icache.tags 2193tgts_per_mshr=20 2194write_buffers=8 2195writeback_clean=true 2196cpu_side=system.cpu3.icache_port 2197mem_side=system.toL2Bus.slave[6] 2198 2199[system.cpu3.icache.tags] 2200type=LRU 2201assoc=1 2202block_size=64 2203clk_domain=system.cpu_clk_domain	2375tags=system.cpu3.icache.tags 2376tgts_per_mshr=20 2377write_buffers=8 2378writeback_clean=true 2379cpu_side=system.cpu3.icache_port 2380mem_side=system.toL2Bus.slave[6] 2381 2382[system.cpu3.icache.tags] 2383type=LRU 2384assoc=1 2385block_size=64 2386clk_domain=system.cpu_clk_domain
	2387data_latency=2
2204default_p_state=UNDEFINED 2205eventq_index=0	2388default_p_state=UNDEFINED 2389eventq_index=0
2206hit_latency=2
2207p_state_clk_gate_bins=20 2208p_state_clk_gate_max=1000000000000 2209p_state_clk_gate_min=1000 2210power_model=Null 2211sequential_access=false 2212size=32768	2390p_state_clk_gate_bins=20 2391p_state_clk_gate_max=1000000000000 2392p_state_clk_gate_min=1000 2393power_model=Null 2394sequential_access=false 2395size=32768
	2396tag_latency=2
2213 2214[system.cpu3.interrupts] 2215type=SparcInterrupts 2216eventq_index=0 2217 2218[system.cpu3.isa] 2219type=SparcISA 2220eventq_index=0 2221 2222[system.cpu3.itb] 2223type=SparcTLB 2224eventq_index=0 2225size=64 2226 2227[system.cpu3.tracer] 2228type=ExeTracer 2229eventq_index=0 2230 2231[system.cpu_clk_domain] 2232type=SrcClockDomain 2233clock=500 2234domain_id=-1 2235eventq_index=0 2236init_perf_level=0 2237voltage_domain=system.voltage_domain 2238 2239[system.dvfs_handler] 2240type=DVFSHandler 2241domains= 2242enable=false 2243eventq_index=0 2244sys_clk_domain=system.clk_domain 2245transition_latency=100000000 2246 2247[system.l2c] 2248type=Cache 2249children=tags 2250addr_ranges=0:18446744073709551615:0:0:0:0 2251assoc=8 2252clk_domain=system.cpu_clk_domain 2253clusivity=mostly_incl	2397 2398[system.cpu3.interrupts] 2399type=SparcInterrupts 2400eventq_index=0 2401 2402[system.cpu3.isa] 2403type=SparcISA 2404eventq_index=0 2405 2406[system.cpu3.itb] 2407type=SparcTLB 2408eventq_index=0 2409size=64 2410 2411[system.cpu3.tracer] 2412type=ExeTracer 2413eventq_index=0 2414 2415[system.cpu_clk_domain] 2416type=SrcClockDomain 2417clock=500 2418domain_id=-1 2419eventq_index=0 2420init_perf_level=0 2421voltage_domain=system.voltage_domain 2422 2423[system.dvfs_handler] 2424type=DVFSHandler 2425domains= 2426enable=false 2427eventq_index=0 2428sys_clk_domain=system.clk_domain 2429transition_latency=100000000 2430 2431[system.l2c] 2432type=Cache 2433children=tags 2434addr_ranges=0:18446744073709551615:0:0:0:0 2435assoc=8 2436clk_domain=system.cpu_clk_domain 2437clusivity=mostly_incl
	2438data_latency=20
2254default_p_state=UNDEFINED 2255demand_mshr_reserve=1 2256eventq_index=0	2439default_p_state=UNDEFINED 2440demand_mshr_reserve=1 2441eventq_index=0
2257hit_latency=20
2258is_read_only=false 2259max_miss_count=0 2260mshrs=20 2261p_state_clk_gate_bins=20 2262p_state_clk_gate_max=1000000000000 2263p_state_clk_gate_min=1000 2264power_model=Null 2265prefetch_on_access=false 2266prefetcher=Null 2267response_latency=20 2268sequential_access=false 2269size=4194304 2270system=system	2442is_read_only=false 2443max_miss_count=0 2444mshrs=20 2445p_state_clk_gate_bins=20 2446p_state_clk_gate_max=1000000000000 2447p_state_clk_gate_min=1000 2448power_model=Null 2449prefetch_on_access=false 2450prefetcher=Null 2451response_latency=20 2452sequential_access=false 2453size=4194304 2454system=system
	2455tag_latency=20
2271tags=system.l2c.tags 2272tgts_per_mshr=12 2273write_buffers=8 2274writeback_clean=false 2275cpu_side=system.toL2Bus.master[0] 2276mem_side=system.membus.slave[1] 2277 2278[system.l2c.tags] 2279type=LRU 2280assoc=8 2281block_size=64 2282clk_domain=system.cpu_clk_domain	2456tags=system.l2c.tags 2457tgts_per_mshr=12 2458write_buffers=8 2459writeback_clean=false 2460cpu_side=system.toL2Bus.master[0] 2461mem_side=system.membus.slave[1] 2462 2463[system.l2c.tags] 2464type=LRU 2465assoc=8 2466block_size=64 2467clk_domain=system.cpu_clk_domain
	2468data_latency=20
2283default_p_state=UNDEFINED 2284eventq_index=0	2469default_p_state=UNDEFINED 2470eventq_index=0
2285hit_latency=20
2286p_state_clk_gate_bins=20 2287p_state_clk_gate_max=1000000000000 2288p_state_clk_gate_min=1000 2289power_model=Null 2290sequential_access=false 2291size=4194304	2471p_state_clk_gate_bins=20 2472p_state_clk_gate_max=1000000000000 2473p_state_clk_gate_min=1000 2474power_model=Null 2475sequential_access=false 2476size=4194304
	2477tag_latency=20
2292 2293[system.membus] 2294type=CoherentXBar 2295children=snoop_filter 2296clk_domain=system.clk_domain 2297default_p_state=UNDEFINED 2298eventq_index=0 2299forward_latency=4 2300frontend_latency=3 2301p_state_clk_gate_bins=20 2302p_state_clk_gate_max=1000000000000 2303p_state_clk_gate_min=1000 2304point_of_coherency=true 2305power_model=Null 2306response_latency=2 2307snoop_filter=system.membus.snoop_filter 2308snoop_response_latency=4 2309system=system 2310use_default_range=false 2311width=16 2312master=system.physmem.port 2313slave=system.system_port system.l2c.mem_side 2314 2315[system.membus.snoop_filter] 2316type=SnoopFilter 2317eventq_index=0 2318lookup_latency=1 2319max_capacity=8388608 2320system=system 2321 2322[system.physmem] 2323type=DRAMCtrl 2324IDD0=0.055000 2325IDD02=0.000000 2326IDD2N=0.032000 2327IDD2N2=0.000000 2328IDD2P0=0.000000 2329IDD2P02=0.000000 2330IDD2P1=0.032000 2331IDD2P12=0.000000 2332IDD3N=0.038000 2333IDD3N2=0.000000 2334IDD3P0=0.000000 2335IDD3P02=0.000000 2336IDD3P1=0.038000 2337IDD3P12=0.000000 2338IDD4R=0.157000 2339IDD4R2=0.000000 2340IDD4W=0.125000 2341IDD4W2=0.000000 2342IDD5=0.235000 2343IDD52=0.000000 2344IDD6=0.020000 2345IDD62=0.000000 2346VDD=1.500000 2347VDD2=0.000000 2348activation_limit=4 2349addr_mapping=RoRaBaCoCh 2350bank_groups_per_rank=0 2351banks_per_rank=8 2352burst_length=8 2353channels=1 2354clk_domain=system.clk_domain 2355conf_table_reported=true 2356default_p_state=UNDEFINED 2357device_bus_width=8 2358device_rowbuffer_size=1024 2359device_size=536870912 2360devices_per_rank=8 2361dll=true 2362eventq_index=0 2363in_addr_map=true 2364kvm_map=true 2365max_accesses_per_row=16 2366mem_sched_policy=frfcfs 2367min_writes_per_switch=16 2368null=false 2369p_state_clk_gate_bins=20 2370p_state_clk_gate_max=1000000000000 2371p_state_clk_gate_min=1000 2372page_policy=open_adaptive 2373power_model=Null 2374range=0:134217727:0:0:0:0 2375ranks_per_channel=2 2376read_buffer_size=32 2377static_backend_latency=10000 2378static_frontend_latency=10000 2379tBURST=5000 2380tCCD_L=0 2381tCK=1250 2382tCL=13750 2383tCS=2500 2384tRAS=35000 2385tRCD=13750 2386tREFI=7800000 2387tRFC=260000 2388tRP=13750 2389tRRD=6000 2390tRRD_L=0 2391tRTP=7500 2392tRTW=2500 2393tWR=15000 2394tWTR=7500 2395tXAW=30000 2396tXP=6000 2397tXPDLL=0 2398tXS=270000 2399tXSDLL=0 2400write_buffer_size=64 2401write_high_thresh_perc=85 2402write_low_thresh_perc=50 2403port=system.membus.master[0] 2404 2405[system.toL2Bus] 2406type=CoherentXBar 2407children=snoop_filter 2408clk_domain=system.cpu_clk_domain 2409default_p_state=UNDEFINED 2410eventq_index=0 2411forward_latency=0 2412frontend_latency=1 2413p_state_clk_gate_bins=20 2414p_state_clk_gate_max=1000000000000 2415p_state_clk_gate_min=1000 2416point_of_coherency=false 2417power_model=Null 2418response_latency=1 2419snoop_filter=system.toL2Bus.snoop_filter 2420snoop_response_latency=1 2421system=system 2422use_default_range=false 2423width=32 2424master=system.l2c.cpu_side 2425slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 2426 2427[system.toL2Bus.snoop_filter] 2428type=SnoopFilter 2429eventq_index=0 2430lookup_latency=0 2431max_capacity=8388608 2432system=system 2433 2434[system.voltage_domain] 2435type=VoltageDomain 2436eventq_index=0 2437voltage=1.000000 2438	2478 2479[system.membus] 2480type=CoherentXBar 2481children=snoop_filter 2482clk_domain=system.clk_domain 2483default_p_state=UNDEFINED 2484eventq_index=0 2485forward_latency=4 2486frontend_latency=3 2487p_state_clk_gate_bins=20 2488p_state_clk_gate_max=1000000000000 2489p_state_clk_gate_min=1000 2490point_of_coherency=true 2491power_model=Null 2492response_latency=2 2493snoop_filter=system.membus.snoop_filter 2494snoop_response_latency=4 2495system=system 2496use_default_range=false 2497width=16 2498master=system.physmem.port 2499slave=system.system_port system.l2c.mem_side 2500 2501[system.membus.snoop_filter] 2502type=SnoopFilter 2503eventq_index=0 2504lookup_latency=1 2505max_capacity=8388608 2506system=system 2507 2508[system.physmem] 2509type=DRAMCtrl 2510IDD0=0.055000 2511IDD02=0.000000 2512IDD2N=0.032000 2513IDD2N2=0.000000 2514IDD2P0=0.000000 2515IDD2P02=0.000000 2516IDD2P1=0.032000 2517IDD2P12=0.000000 2518IDD3N=0.038000 2519IDD3N2=0.000000 2520IDD3P0=0.000000 2521IDD3P02=0.000000 2522IDD3P1=0.038000 2523IDD3P12=0.000000 2524IDD4R=0.157000 2525IDD4R2=0.000000 2526IDD4W=0.125000 2527IDD4W2=0.000000 2528IDD5=0.235000 2529IDD52=0.000000 2530IDD6=0.020000 2531IDD62=0.000000 2532VDD=1.500000 2533VDD2=0.000000 2534activation_limit=4 2535addr_mapping=RoRaBaCoCh 2536bank_groups_per_rank=0 2537banks_per_rank=8 2538burst_length=8 2539channels=1 2540clk_domain=system.clk_domain 2541conf_table_reported=true 2542default_p_state=UNDEFINED 2543device_bus_width=8 2544device_rowbuffer_size=1024 2545device_size=536870912 2546devices_per_rank=8 2547dll=true 2548eventq_index=0 2549in_addr_map=true 2550kvm_map=true 2551max_accesses_per_row=16 2552mem_sched_policy=frfcfs 2553min_writes_per_switch=16 2554null=false 2555p_state_clk_gate_bins=20 2556p_state_clk_gate_max=1000000000000 2557p_state_clk_gate_min=1000 2558page_policy=open_adaptive 2559power_model=Null 2560range=0:134217727:0:0:0:0 2561ranks_per_channel=2 2562read_buffer_size=32 2563static_backend_latency=10000 2564static_frontend_latency=10000 2565tBURST=5000 2566tCCD_L=0 2567tCK=1250 2568tCL=13750 2569tCS=2500 2570tRAS=35000 2571tRCD=13750 2572tREFI=7800000 2573tRFC=260000 2574tRP=13750 2575tRRD=6000 2576tRRD_L=0 2577tRTP=7500 2578tRTW=2500 2579tWR=15000 2580tWTR=7500 2581tXAW=30000 2582tXP=6000 2583tXPDLL=0 2584tXS=270000 2585tXSDLL=0 2586write_buffer_size=64 2587write_high_thresh_perc=85 2588write_low_thresh_perc=50 2589port=system.membus.master[0] 2590 2591[system.toL2Bus] 2592type=CoherentXBar 2593children=snoop_filter 2594clk_domain=system.cpu_clk_domain 2595default_p_state=UNDEFINED 2596eventq_index=0 2597forward_latency=0 2598frontend_latency=1 2599p_state_clk_gate_bins=20 2600p_state_clk_gate_max=1000000000000 2601p_state_clk_gate_min=1000 2602point_of_coherency=false 2603power_model=Null 2604response_latency=1 2605snoop_filter=system.toL2Bus.snoop_filter 2606snoop_response_latency=1 2607system=system 2608use_default_range=false 2609width=32 2610master=system.l2c.cpu_side 2611slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 2612 2613[system.toL2Bus.snoop_filter] 2614type=SnoopFilter 2615eventq_index=0 2616lookup_latency=0 2617max_capacity=8388608 2618system=system 2619 2620[system.voltage_domain] 2621type=VoltageDomain 2622eventq_index=0 2623voltage=1.000000 2624