1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
--- 163 unchanged lines hidden (view full) ---
172
173[system.cpu0.dcache]
174type=Cache
175children=tags
176addr_ranges=0:18446744073709551615:0:0:0:0
177assoc=4
178clk_domain=system.cpu_clk_domain
179clusivity=mostly_incl
180default_p_state=UNDEFINED
181demand_mshr_reserve=1
182eventq_index=0
183hit_latency=2
184is_read_only=false
185max_miss_count=0
186mshrs=4
187p_state_clk_gate_bins=20
188p_state_clk_gate_max=1000000000000
189p_state_clk_gate_min=1000
190power_model=Null
191prefetch_on_access=false
192prefetcher=Null
193response_latency=2
194sequential_access=false
195size=32768
196system=system
197tags=system.cpu0.dcache.tags
198tgts_per_mshr=20
199write_buffers=8
200writeback_clean=false
201cpu_side=system.cpu0.dcache_port
202mem_side=system.toL2Bus.slave[1]
203
204[system.cpu0.dcache.tags]
205type=LRU
206assoc=4
207block_size=64
208clk_domain=system.cpu_clk_domain
209default_p_state=UNDEFINED
210eventq_index=0
211hit_latency=2
212p_state_clk_gate_bins=20
213p_state_clk_gate_max=1000000000000
214p_state_clk_gate_min=1000
215power_model=Null
216sequential_access=false
217size=32768
218
219[system.cpu0.dtb]
220type=SparcTLB
221eventq_index=0
222size=64
223
224[system.cpu0.fuPool]
225type=FUPool
--- 61 unchanged lines hidden (view full) ---
287type=OpDesc
288eventq_index=0
289opClass=FloatCvt
290opLat=2
291pipelined=true
292
293[system.cpu0.fuPool.FUList3]
294type=FUDesc
295children=opList0 opList1 opList2
296count=2
297eventq_index=0
298opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
299
300[system.cpu0.fuPool.FUList3.opList0]
301type=OpDesc
302eventq_index=0
303opClass=FloatMult
304opLat=4
305pipelined=true
306
307[system.cpu0.fuPool.FUList3.opList1]
308type=OpDesc
309eventq_index=0
310opClass=FloatDiv
311opLat=12
312pipelined=false
313
314[system.cpu0.fuPool.FUList3.opList2]
315type=OpDesc
316eventq_index=0
317opClass=FloatSqrt
318opLat=24
319pipelined=false
320
321[system.cpu0.fuPool.FUList4]
322type=FUDesc
323children=opList
324count=0
325eventq_index=0
326opList=system.cpu0.fuPool.FUList4.opList
327
328[system.cpu0.fuPool.FUList4.opList]
329type=OpDesc
330eventq_index=0
331opClass=MemRead
332opLat=1
333pipelined=true
334
335[system.cpu0.fuPool.FUList5]
336type=FUDesc
337children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
338count=4
339eventq_index=0
340opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19
341
342[system.cpu0.fuPool.FUList5.opList00]
--- 133 unchanged lines hidden (view full) ---
476type=OpDesc
477eventq_index=0
478opClass=SimdFloatSqrt
479opLat=1
480pipelined=true
481
482[system.cpu0.fuPool.FUList6]
483type=FUDesc
484children=opList
485count=0
486eventq_index=0
487opList=system.cpu0.fuPool.FUList6.opList
488
489[system.cpu0.fuPool.FUList6.opList]
490type=OpDesc
491eventq_index=0
492opClass=MemWrite
493opLat=1
494pipelined=true
495
496[system.cpu0.fuPool.FUList7]
497type=FUDesc
498children=opList0 opList1
499count=4
500eventq_index=0
501opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
502
503[system.cpu0.fuPool.FUList7.opList0]
504type=OpDesc
505eventq_index=0
506opClass=MemRead
507opLat=1
508pipelined=true
509
510[system.cpu0.fuPool.FUList7.opList1]
511type=OpDesc
512eventq_index=0
513opClass=MemWrite
514opLat=1
515pipelined=true
516
517[system.cpu0.fuPool.FUList8]
518type=FUDesc
519children=opList
520count=1
521eventq_index=0
522opList=system.cpu0.fuPool.FUList8.opList
523
524[system.cpu0.fuPool.FUList8.opList]
--- 5 unchanged lines hidden (view full) ---
530
531[system.cpu0.icache]
532type=Cache
533children=tags
534addr_ranges=0:18446744073709551615:0:0:0:0
535assoc=1
536clk_domain=system.cpu_clk_domain
537clusivity=mostly_incl
538default_p_state=UNDEFINED
539demand_mshr_reserve=1
540eventq_index=0
541hit_latency=2
542is_read_only=true
543max_miss_count=0
544mshrs=4
545p_state_clk_gate_bins=20
546p_state_clk_gate_max=1000000000000
547p_state_clk_gate_min=1000
548power_model=Null
549prefetch_on_access=false
550prefetcher=Null
551response_latency=2
552sequential_access=false
553size=32768
554system=system
555tags=system.cpu0.icache.tags
556tgts_per_mshr=20
557write_buffers=8
558writeback_clean=true
559cpu_side=system.cpu0.icache_port
560mem_side=system.toL2Bus.slave[0]
561
562[system.cpu0.icache.tags]
563type=LRU
564assoc=1
565block_size=64
566clk_domain=system.cpu_clk_domain
567default_p_state=UNDEFINED
568eventq_index=0
569hit_latency=2
570p_state_clk_gate_bins=20
571p_state_clk_gate_max=1000000000000
572p_state_clk_gate_min=1000
573power_model=Null
574sequential_access=false
575size=32768
576
577[system.cpu0.interrupts]
578type=SparcInterrupts
579eventq_index=0
580
581[system.cpu0.isa]
582type=SparcISA
583eventq_index=0
--- 12 unchanged lines hidden (view full) ---
596cmd=test_atomic 4
597cwd=
598drivers=
599egid=100
600env=
601errout=cerr
602euid=100
603eventq_index=0
604executable=/arm/projectscratch/randd/systems/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
605gid=100
606input=cin
607kvmInSE=false
608max_stack_size=67108864
609output=cout
610pid=100
611ppid=99
612simpoint=0
--- 120 unchanged lines hidden (view full) ---
733
734[system.cpu1.dcache]
735type=Cache
736children=tags
737addr_ranges=0:18446744073709551615:0:0:0:0
738assoc=4
739clk_domain=system.cpu_clk_domain
740clusivity=mostly_incl
741default_p_state=UNDEFINED
742demand_mshr_reserve=1
743eventq_index=0
744hit_latency=2
745is_read_only=false
746max_miss_count=0
747mshrs=4
748p_state_clk_gate_bins=20
749p_state_clk_gate_max=1000000000000
750p_state_clk_gate_min=1000
751power_model=Null
752prefetch_on_access=false
753prefetcher=Null
754response_latency=2
755sequential_access=false
756size=32768
757system=system
758tags=system.cpu1.dcache.tags
759tgts_per_mshr=20
760write_buffers=8
761writeback_clean=false
762cpu_side=system.cpu1.dcache_port
763mem_side=system.toL2Bus.slave[3]
764
765[system.cpu1.dcache.tags]
766type=LRU
767assoc=4
768block_size=64
769clk_domain=system.cpu_clk_domain
770default_p_state=UNDEFINED
771eventq_index=0
772hit_latency=2
773p_state_clk_gate_bins=20
774p_state_clk_gate_max=1000000000000
775p_state_clk_gate_min=1000
776power_model=Null
777sequential_access=false
778size=32768
779
780[system.cpu1.dtb]
781type=SparcTLB
782eventq_index=0
783size=64
784
785[system.cpu1.fuPool]
786type=FUPool
--- 61 unchanged lines hidden (view full) ---
848type=OpDesc
849eventq_index=0
850opClass=FloatCvt
851opLat=2
852pipelined=true
853
854[system.cpu1.fuPool.FUList3]
855type=FUDesc
856children=opList0 opList1 opList2
857count=2
858eventq_index=0
859opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2
860
861[system.cpu1.fuPool.FUList3.opList0]
862type=OpDesc
863eventq_index=0
864opClass=FloatMult
865opLat=4
866pipelined=true
867
868[system.cpu1.fuPool.FUList3.opList1]
869type=OpDesc
870eventq_index=0
871opClass=FloatDiv
872opLat=12
873pipelined=false
874
875[system.cpu1.fuPool.FUList3.opList2]
876type=OpDesc
877eventq_index=0
878opClass=FloatSqrt
879opLat=24
880pipelined=false
881
882[system.cpu1.fuPool.FUList4]
883type=FUDesc
884children=opList
885count=0
886eventq_index=0
887opList=system.cpu1.fuPool.FUList4.opList
888
889[system.cpu1.fuPool.FUList4.opList]
890type=OpDesc
891eventq_index=0
892opClass=MemRead
893opLat=1
894pipelined=true
895
896[system.cpu1.fuPool.FUList5]
897type=FUDesc
898children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
899count=4
900eventq_index=0
901opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19
902
903[system.cpu1.fuPool.FUList5.opList00]
--- 133 unchanged lines hidden (view full) ---
1037type=OpDesc
1038eventq_index=0
1039opClass=SimdFloatSqrt
1040opLat=1
1041pipelined=true
1042
1043[system.cpu1.fuPool.FUList6]
1044type=FUDesc
1045children=opList
1046count=0
1047eventq_index=0
1048opList=system.cpu1.fuPool.FUList6.opList
1049
1050[system.cpu1.fuPool.FUList6.opList]
1051type=OpDesc
1052eventq_index=0
1053opClass=MemWrite
1054opLat=1
1055pipelined=true
1056
1057[system.cpu1.fuPool.FUList7]
1058type=FUDesc
1059children=opList0 opList1
1060count=4
1061eventq_index=0
1062opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
1063
1064[system.cpu1.fuPool.FUList7.opList0]
1065type=OpDesc
1066eventq_index=0
1067opClass=MemRead
1068opLat=1
1069pipelined=true
1070
1071[system.cpu1.fuPool.FUList7.opList1]
1072type=OpDesc
1073eventq_index=0
1074opClass=MemWrite
1075opLat=1
1076pipelined=true
1077
1078[system.cpu1.fuPool.FUList8]
1079type=FUDesc
1080children=opList
1081count=1
1082eventq_index=0
1083opList=system.cpu1.fuPool.FUList8.opList
1084
1085[system.cpu1.fuPool.FUList8.opList]
--- 5 unchanged lines hidden (view full) ---
1091
1092[system.cpu1.icache]
1093type=Cache
1094children=tags
1095addr_ranges=0:18446744073709551615:0:0:0:0
1096assoc=1
1097clk_domain=system.cpu_clk_domain
1098clusivity=mostly_incl
1099default_p_state=UNDEFINED
1100demand_mshr_reserve=1
1101eventq_index=0
1102hit_latency=2
1103is_read_only=true
1104max_miss_count=0
1105mshrs=4
1106p_state_clk_gate_bins=20
1107p_state_clk_gate_max=1000000000000
1108p_state_clk_gate_min=1000
1109power_model=Null
1110prefetch_on_access=false
1111prefetcher=Null
1112response_latency=2
1113sequential_access=false
1114size=32768
1115system=system
1116tags=system.cpu1.icache.tags
1117tgts_per_mshr=20
1118write_buffers=8
1119writeback_clean=true
1120cpu_side=system.cpu1.icache_port
1121mem_side=system.toL2Bus.slave[2]
1122
1123[system.cpu1.icache.tags]
1124type=LRU
1125assoc=1
1126block_size=64
1127clk_domain=system.cpu_clk_domain
1128default_p_state=UNDEFINED
1129eventq_index=0
1130hit_latency=2
1131p_state_clk_gate_bins=20
1132p_state_clk_gate_max=1000000000000
1133p_state_clk_gate_min=1000
1134power_model=Null
1135sequential_access=false
1136size=32768
1137
1138[system.cpu1.interrupts]
1139type=SparcInterrupts
1140eventq_index=0
1141
1142[system.cpu1.isa]
1143type=SparcISA
1144eventq_index=0
--- 126 unchanged lines hidden (view full) ---
1271
1272[system.cpu2.dcache]
1273type=Cache
1274children=tags
1275addr_ranges=0:18446744073709551615:0:0:0:0
1276assoc=4
1277clk_domain=system.cpu_clk_domain
1278clusivity=mostly_incl
1279default_p_state=UNDEFINED
1280demand_mshr_reserve=1
1281eventq_index=0
1282hit_latency=2
1283is_read_only=false
1284max_miss_count=0
1285mshrs=4
1286p_state_clk_gate_bins=20
1287p_state_clk_gate_max=1000000000000
1288p_state_clk_gate_min=1000
1289power_model=Null
1290prefetch_on_access=false
1291prefetcher=Null
1292response_latency=2
1293sequential_access=false
1294size=32768
1295system=system
1296tags=system.cpu2.dcache.tags
1297tgts_per_mshr=20
1298write_buffers=8
1299writeback_clean=false
1300cpu_side=system.cpu2.dcache_port
1301mem_side=system.toL2Bus.slave[5]
1302
1303[system.cpu2.dcache.tags]
1304type=LRU
1305assoc=4
1306block_size=64
1307clk_domain=system.cpu_clk_domain
1308default_p_state=UNDEFINED
1309eventq_index=0
1310hit_latency=2
1311p_state_clk_gate_bins=20
1312p_state_clk_gate_max=1000000000000
1313p_state_clk_gate_min=1000
1314power_model=Null
1315sequential_access=false
1316size=32768
1317
1318[system.cpu2.dtb]
1319type=SparcTLB
1320eventq_index=0
1321size=64
1322
1323[system.cpu2.fuPool]
1324type=FUPool
--- 61 unchanged lines hidden (view full) ---
1386type=OpDesc
1387eventq_index=0
1388opClass=FloatCvt
1389opLat=2
1390pipelined=true
1391
1392[system.cpu2.fuPool.FUList3]
1393type=FUDesc
1394children=opList0 opList1 opList2
1395count=2
1396eventq_index=0
1397opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2
1398
1399[system.cpu2.fuPool.FUList3.opList0]
1400type=OpDesc
1401eventq_index=0
1402opClass=FloatMult
1403opLat=4
1404pipelined=true
1405
1406[system.cpu2.fuPool.FUList3.opList1]
1407type=OpDesc
1408eventq_index=0
1409opClass=FloatDiv
1410opLat=12
1411pipelined=false
1412
1413[system.cpu2.fuPool.FUList3.opList2]
1414type=OpDesc
1415eventq_index=0
1416opClass=FloatSqrt
1417opLat=24
1418pipelined=false
1419
1420[system.cpu2.fuPool.FUList4]
1421type=FUDesc
1422children=opList
1423count=0
1424eventq_index=0
1425opList=system.cpu2.fuPool.FUList4.opList
1426
1427[system.cpu2.fuPool.FUList4.opList]
1428type=OpDesc
1429eventq_index=0
1430opClass=MemRead
1431opLat=1
1432pipelined=true
1433
1434[system.cpu2.fuPool.FUList5]
1435type=FUDesc
1436children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
1437count=4
1438eventq_index=0
1439opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19
1440
1441[system.cpu2.fuPool.FUList5.opList00]
--- 133 unchanged lines hidden (view full) ---
1575type=OpDesc
1576eventq_index=0
1577opClass=SimdFloatSqrt
1578opLat=1
1579pipelined=true
1580
1581[system.cpu2.fuPool.FUList6]
1582type=FUDesc
1583children=opList
1584count=0
1585eventq_index=0
1586opList=system.cpu2.fuPool.FUList6.opList
1587
1588[system.cpu2.fuPool.FUList6.opList]
1589type=OpDesc
1590eventq_index=0
1591opClass=MemWrite
1592opLat=1
1593pipelined=true
1594
1595[system.cpu2.fuPool.FUList7]
1596type=FUDesc
1597children=opList0 opList1
1598count=4
1599eventq_index=0
1600opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
1601
1602[system.cpu2.fuPool.FUList7.opList0]
1603type=OpDesc
1604eventq_index=0
1605opClass=MemRead
1606opLat=1
1607pipelined=true
1608
1609[system.cpu2.fuPool.FUList7.opList1]
1610type=OpDesc
1611eventq_index=0
1612opClass=MemWrite
1613opLat=1
1614pipelined=true
1615
1616[system.cpu2.fuPool.FUList8]
1617type=FUDesc
1618children=opList
1619count=1
1620eventq_index=0
1621opList=system.cpu2.fuPool.FUList8.opList
1622
1623[system.cpu2.fuPool.FUList8.opList]
--- 5 unchanged lines hidden (view full) ---
1629
1630[system.cpu2.icache]
1631type=Cache
1632children=tags
1633addr_ranges=0:18446744073709551615:0:0:0:0
1634assoc=1
1635clk_domain=system.cpu_clk_domain
1636clusivity=mostly_incl
1637default_p_state=UNDEFINED
1638demand_mshr_reserve=1
1639eventq_index=0
1640hit_latency=2
1641is_read_only=true
1642max_miss_count=0
1643mshrs=4
1644p_state_clk_gate_bins=20
1645p_state_clk_gate_max=1000000000000
1646p_state_clk_gate_min=1000
1647power_model=Null
1648prefetch_on_access=false
1649prefetcher=Null
1650response_latency=2
1651sequential_access=false
1652size=32768
1653system=system
1654tags=system.cpu2.icache.tags
1655tgts_per_mshr=20
1656write_buffers=8
1657writeback_clean=true
1658cpu_side=system.cpu2.icache_port
1659mem_side=system.toL2Bus.slave[4]
1660
1661[system.cpu2.icache.tags]
1662type=LRU
1663assoc=1
1664block_size=64
1665clk_domain=system.cpu_clk_domain
1666default_p_state=UNDEFINED
1667eventq_index=0
1668hit_latency=2
1669p_state_clk_gate_bins=20
1670p_state_clk_gate_max=1000000000000
1671p_state_clk_gate_min=1000
1672power_model=Null
1673sequential_access=false
1674size=32768
1675
1676[system.cpu2.interrupts]
1677type=SparcInterrupts
1678eventq_index=0
1679
1680[system.cpu2.isa]
1681type=SparcISA
1682eventq_index=0
--- 126 unchanged lines hidden (view full) ---
1809
1810[system.cpu3.dcache]
1811type=Cache
1812children=tags
1813addr_ranges=0:18446744073709551615:0:0:0:0
1814assoc=4
1815clk_domain=system.cpu_clk_domain
1816clusivity=mostly_incl
1817default_p_state=UNDEFINED
1818demand_mshr_reserve=1
1819eventq_index=0
1820hit_latency=2
1821is_read_only=false
1822max_miss_count=0
1823mshrs=4
1824p_state_clk_gate_bins=20
1825p_state_clk_gate_max=1000000000000
1826p_state_clk_gate_min=1000
1827power_model=Null
1828prefetch_on_access=false
1829prefetcher=Null
1830response_latency=2
1831sequential_access=false
1832size=32768
1833system=system
1834tags=system.cpu3.dcache.tags
1835tgts_per_mshr=20
1836write_buffers=8
1837writeback_clean=false
1838cpu_side=system.cpu3.dcache_port
1839mem_side=system.toL2Bus.slave[7]
1840
1841[system.cpu3.dcache.tags]
1842type=LRU
1843assoc=4
1844block_size=64
1845clk_domain=system.cpu_clk_domain
1846default_p_state=UNDEFINED
1847eventq_index=0
1848hit_latency=2
1849p_state_clk_gate_bins=20
1850p_state_clk_gate_max=1000000000000
1851p_state_clk_gate_min=1000
1852power_model=Null
1853sequential_access=false
1854size=32768
1855
1856[system.cpu3.dtb]
1857type=SparcTLB
1858eventq_index=0
1859size=64
1860
1861[system.cpu3.fuPool]
1862type=FUPool
--- 61 unchanged lines hidden (view full) ---
1924type=OpDesc
1925eventq_index=0
1926opClass=FloatCvt
1927opLat=2
1928pipelined=true
1929
1930[system.cpu3.fuPool.FUList3]
1931type=FUDesc
1932children=opList0 opList1 opList2
1933count=2
1934eventq_index=0
1935opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2
1936
1937[system.cpu3.fuPool.FUList3.opList0]
1938type=OpDesc
1939eventq_index=0
1940opClass=FloatMult
1941opLat=4
1942pipelined=true
1943
1944[system.cpu3.fuPool.FUList3.opList1]
1945type=OpDesc
1946eventq_index=0
1947opClass=FloatDiv
1948opLat=12
1949pipelined=false
1950
1951[system.cpu3.fuPool.FUList3.opList2]
1952type=OpDesc
1953eventq_index=0
1954opClass=FloatSqrt
1955opLat=24
1956pipelined=false
1957
1958[system.cpu3.fuPool.FUList4]
1959type=FUDesc
1960children=opList
1961count=0
1962eventq_index=0
1963opList=system.cpu3.fuPool.FUList4.opList
1964
1965[system.cpu3.fuPool.FUList4.opList]
1966type=OpDesc
1967eventq_index=0
1968opClass=MemRead
1969opLat=1
1970pipelined=true
1971
1972[system.cpu3.fuPool.FUList5]
1973type=FUDesc
1974children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
1975count=4
1976eventq_index=0
1977opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19
1978
1979[system.cpu3.fuPool.FUList5.opList00]
--- 133 unchanged lines hidden (view full) ---
2113type=OpDesc
2114eventq_index=0
2115opClass=SimdFloatSqrt
2116opLat=1
2117pipelined=true
2118
2119[system.cpu3.fuPool.FUList6]
2120type=FUDesc
2121children=opList
2122count=0
2123eventq_index=0
2124opList=system.cpu3.fuPool.FUList6.opList
2125
2126[system.cpu3.fuPool.FUList6.opList]
2127type=OpDesc
2128eventq_index=0
2129opClass=MemWrite
2130opLat=1
2131pipelined=true
2132
2133[system.cpu3.fuPool.FUList7]
2134type=FUDesc
2135children=opList0 opList1
2136count=4
2137eventq_index=0
2138opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1
2139
2140[system.cpu3.fuPool.FUList7.opList0]
2141type=OpDesc
2142eventq_index=0
2143opClass=MemRead
2144opLat=1
2145pipelined=true
2146
2147[system.cpu3.fuPool.FUList7.opList1]
2148type=OpDesc
2149eventq_index=0
2150opClass=MemWrite
2151opLat=1
2152pipelined=true
2153
2154[system.cpu3.fuPool.FUList8]
2155type=FUDesc
2156children=opList
2157count=1
2158eventq_index=0
2159opList=system.cpu3.fuPool.FUList8.opList
2160
2161[system.cpu3.fuPool.FUList8.opList]
--- 5 unchanged lines hidden (view full) ---
2167
2168[system.cpu3.icache]
2169type=Cache
2170children=tags
2171addr_ranges=0:18446744073709551615:0:0:0:0
2172assoc=1
2173clk_domain=system.cpu_clk_domain
2174clusivity=mostly_incl
2175default_p_state=UNDEFINED
2176demand_mshr_reserve=1
2177eventq_index=0
2178hit_latency=2
2179is_read_only=true
2180max_miss_count=0
2181mshrs=4
2182p_state_clk_gate_bins=20
2183p_state_clk_gate_max=1000000000000
2184p_state_clk_gate_min=1000
2185power_model=Null
2186prefetch_on_access=false
2187prefetcher=Null
2188response_latency=2
2189sequential_access=false
2190size=32768
2191system=system
2192tags=system.cpu3.icache.tags
2193tgts_per_mshr=20
2194write_buffers=8
2195writeback_clean=true
2196cpu_side=system.cpu3.icache_port
2197mem_side=system.toL2Bus.slave[6]
2198
2199[system.cpu3.icache.tags]
2200type=LRU
2201assoc=1
2202block_size=64
2203clk_domain=system.cpu_clk_domain
2204default_p_state=UNDEFINED
2205eventq_index=0
2206hit_latency=2
2207p_state_clk_gate_bins=20
2208p_state_clk_gate_max=1000000000000
2209p_state_clk_gate_min=1000
2210power_model=Null
2211sequential_access=false
2212size=32768
2213
2214[system.cpu3.interrupts]
2215type=SparcInterrupts
2216eventq_index=0
2217
2218[system.cpu3.isa]
2219type=SparcISA
2220eventq_index=0
--- 25 unchanged lines hidden (view full) ---
2246
2247[system.l2c]
2248type=Cache
2249children=tags
2250addr_ranges=0:18446744073709551615:0:0:0:0
2251assoc=8
2252clk_domain=system.cpu_clk_domain
2253clusivity=mostly_incl
2254default_p_state=UNDEFINED
2255demand_mshr_reserve=1
2256eventq_index=0
2257hit_latency=20
2258is_read_only=false
2259max_miss_count=0
2260mshrs=20
2261p_state_clk_gate_bins=20
2262p_state_clk_gate_max=1000000000000
2263p_state_clk_gate_min=1000
2264power_model=Null
2265prefetch_on_access=false
2266prefetcher=Null
2267response_latency=20
2268sequential_access=false
2269size=4194304
2270system=system
2271tags=system.l2c.tags
2272tgts_per_mshr=12
2273write_buffers=8
2274writeback_clean=false
2275cpu_side=system.toL2Bus.master[0]
2276mem_side=system.membus.slave[1]
2277
2278[system.l2c.tags]
2279type=LRU
2280assoc=8
2281block_size=64
2282clk_domain=system.cpu_clk_domain
2283default_p_state=UNDEFINED
2284eventq_index=0
2285hit_latency=20
2286p_state_clk_gate_bins=20
2287p_state_clk_gate_max=1000000000000
2288p_state_clk_gate_min=1000
2289power_model=Null
2290sequential_access=false
2291size=4194304
2292
2293[system.membus]
2294type=CoherentXBar
2295children=snoop_filter
2296clk_domain=system.clk_domain
2297default_p_state=UNDEFINED
2298eventq_index=0
2299forward_latency=4
--- 139 unchanged lines hidden ---
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
--- 163 unchanged lines hidden (view full) ---
172
173[system.cpu0.dcache]
174type=Cache
175children=tags
176addr_ranges=0:18446744073709551615:0:0:0:0
177assoc=4
178clk_domain=system.cpu_clk_domain
179clusivity=mostly_incl
180default_p_state=UNDEFINED
181demand_mshr_reserve=1
182eventq_index=0
183hit_latency=2
184is_read_only=false
185max_miss_count=0
186mshrs=4
187p_state_clk_gate_bins=20
188p_state_clk_gate_max=1000000000000
189p_state_clk_gate_min=1000
190power_model=Null
191prefetch_on_access=false
192prefetcher=Null
193response_latency=2
194sequential_access=false
195size=32768
196system=system
197tags=system.cpu0.dcache.tags
198tgts_per_mshr=20
199write_buffers=8
200writeback_clean=false
201cpu_side=system.cpu0.dcache_port
202mem_side=system.toL2Bus.slave[1]
203
204[system.cpu0.dcache.tags]
205type=LRU
206assoc=4
207block_size=64
208clk_domain=system.cpu_clk_domain
209default_p_state=UNDEFINED
210eventq_index=0
211hit_latency=2
212p_state_clk_gate_bins=20
213p_state_clk_gate_max=1000000000000
214p_state_clk_gate_min=1000
215power_model=Null
216sequential_access=false
217size=32768
218
219[system.cpu0.dtb]
220type=SparcTLB
221eventq_index=0
222size=64
223
224[system.cpu0.fuPool]
225type=FUPool
--- 61 unchanged lines hidden (view full) ---
287type=OpDesc
288eventq_index=0
289opClass=FloatCvt
290opLat=2
291pipelined=true
292
293[system.cpu0.fuPool.FUList3]
294type=FUDesc
295children=opList0 opList1 opList2
296count=2
297eventq_index=0
298opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
299
300[system.cpu0.fuPool.FUList3.opList0]
301type=OpDesc
302eventq_index=0
303opClass=FloatMult
304opLat=4
305pipelined=true
306
307[system.cpu0.fuPool.FUList3.opList1]
308type=OpDesc
309eventq_index=0
310opClass=FloatDiv
311opLat=12
312pipelined=false
313
314[system.cpu0.fuPool.FUList3.opList2]
315type=OpDesc
316eventq_index=0
317opClass=FloatSqrt
318opLat=24
319pipelined=false
320
321[system.cpu0.fuPool.FUList4]
322type=FUDesc
323children=opList
324count=0
325eventq_index=0
326opList=system.cpu0.fuPool.FUList4.opList
327
328[system.cpu0.fuPool.FUList4.opList]
329type=OpDesc
330eventq_index=0
331opClass=MemRead
332opLat=1
333pipelined=true
334
335[system.cpu0.fuPool.FUList5]
336type=FUDesc
337children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
338count=4
339eventq_index=0
340opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19
341
342[system.cpu0.fuPool.FUList5.opList00]
--- 133 unchanged lines hidden (view full) ---
476type=OpDesc
477eventq_index=0
478opClass=SimdFloatSqrt
479opLat=1
480pipelined=true
481
482[system.cpu0.fuPool.FUList6]
483type=FUDesc
484children=opList
485count=0
486eventq_index=0
487opList=system.cpu0.fuPool.FUList6.opList
488
489[system.cpu0.fuPool.FUList6.opList]
490type=OpDesc
491eventq_index=0
492opClass=MemWrite
493opLat=1
494pipelined=true
495
496[system.cpu0.fuPool.FUList7]
497type=FUDesc
498children=opList0 opList1
499count=4
500eventq_index=0
501opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
502
503[system.cpu0.fuPool.FUList7.opList0]
504type=OpDesc
505eventq_index=0
506opClass=MemRead
507opLat=1
508pipelined=true
509
510[system.cpu0.fuPool.FUList7.opList1]
511type=OpDesc
512eventq_index=0
513opClass=MemWrite
514opLat=1
515pipelined=true
516
517[system.cpu0.fuPool.FUList8]
518type=FUDesc
519children=opList
520count=1
521eventq_index=0
522opList=system.cpu0.fuPool.FUList8.opList
523
524[system.cpu0.fuPool.FUList8.opList]
--- 5 unchanged lines hidden (view full) ---
530
531[system.cpu0.icache]
532type=Cache
533children=tags
534addr_ranges=0:18446744073709551615:0:0:0:0
535assoc=1
536clk_domain=system.cpu_clk_domain
537clusivity=mostly_incl
538default_p_state=UNDEFINED
539demand_mshr_reserve=1
540eventq_index=0
541hit_latency=2
542is_read_only=true
543max_miss_count=0
544mshrs=4
545p_state_clk_gate_bins=20
546p_state_clk_gate_max=1000000000000
547p_state_clk_gate_min=1000
548power_model=Null
549prefetch_on_access=false
550prefetcher=Null
551response_latency=2
552sequential_access=false
553size=32768
554system=system
555tags=system.cpu0.icache.tags
556tgts_per_mshr=20
557write_buffers=8
558writeback_clean=true
559cpu_side=system.cpu0.icache_port
560mem_side=system.toL2Bus.slave[0]
561
562[system.cpu0.icache.tags]
563type=LRU
564assoc=1
565block_size=64
566clk_domain=system.cpu_clk_domain
567default_p_state=UNDEFINED
568eventq_index=0
569hit_latency=2
570p_state_clk_gate_bins=20
571p_state_clk_gate_max=1000000000000
572p_state_clk_gate_min=1000
573power_model=Null
574sequential_access=false
575size=32768
576
577[system.cpu0.interrupts]
578type=SparcInterrupts
579eventq_index=0
580
581[system.cpu0.isa]
582type=SparcISA
583eventq_index=0
--- 12 unchanged lines hidden (view full) ---
596cmd=test_atomic 4
597cwd=
598drivers=
599egid=100
600env=
601errout=cerr
602euid=100
603eventq_index=0
604executable=/arm/projectscratch/randd/systems/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
605gid=100
606input=cin
607kvmInSE=false
608max_stack_size=67108864
609output=cout
610pid=100
611ppid=99
612simpoint=0
--- 120 unchanged lines hidden (view full) ---
733
734[system.cpu1.dcache]
735type=Cache
736children=tags
737addr_ranges=0:18446744073709551615:0:0:0:0
738assoc=4
739clk_domain=system.cpu_clk_domain
740clusivity=mostly_incl
741default_p_state=UNDEFINED
742demand_mshr_reserve=1
743eventq_index=0
744hit_latency=2
745is_read_only=false
746max_miss_count=0
747mshrs=4
748p_state_clk_gate_bins=20
749p_state_clk_gate_max=1000000000000
750p_state_clk_gate_min=1000
751power_model=Null
752prefetch_on_access=false
753prefetcher=Null
754response_latency=2
755sequential_access=false
756size=32768
757system=system
758tags=system.cpu1.dcache.tags
759tgts_per_mshr=20
760write_buffers=8
761writeback_clean=false
762cpu_side=system.cpu1.dcache_port
763mem_side=system.toL2Bus.slave[3]
764
765[system.cpu1.dcache.tags]
766type=LRU
767assoc=4
768block_size=64
769clk_domain=system.cpu_clk_domain
770default_p_state=UNDEFINED
771eventq_index=0
772hit_latency=2
773p_state_clk_gate_bins=20
774p_state_clk_gate_max=1000000000000
775p_state_clk_gate_min=1000
776power_model=Null
777sequential_access=false
778size=32768
779
780[system.cpu1.dtb]
781type=SparcTLB
782eventq_index=0
783size=64
784
785[system.cpu1.fuPool]
786type=FUPool
--- 61 unchanged lines hidden (view full) ---
848type=OpDesc
849eventq_index=0
850opClass=FloatCvt
851opLat=2
852pipelined=true
853
854[system.cpu1.fuPool.FUList3]
855type=FUDesc
856children=opList0 opList1 opList2
857count=2
858eventq_index=0
859opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2
860
861[system.cpu1.fuPool.FUList3.opList0]
862type=OpDesc
863eventq_index=0
864opClass=FloatMult
865opLat=4
866pipelined=true
867
868[system.cpu1.fuPool.FUList3.opList1]
869type=OpDesc
870eventq_index=0
871opClass=FloatDiv
872opLat=12
873pipelined=false
874
875[system.cpu1.fuPool.FUList3.opList2]
876type=OpDesc
877eventq_index=0
878opClass=FloatSqrt
879opLat=24
880pipelined=false
881
882[system.cpu1.fuPool.FUList4]
883type=FUDesc
884children=opList
885count=0
886eventq_index=0
887opList=system.cpu1.fuPool.FUList4.opList
888
889[system.cpu1.fuPool.FUList4.opList]
890type=OpDesc
891eventq_index=0
892opClass=MemRead
893opLat=1
894pipelined=true
895
896[system.cpu1.fuPool.FUList5]
897type=FUDesc
898children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
899count=4
900eventq_index=0
901opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19
902
903[system.cpu1.fuPool.FUList5.opList00]
--- 133 unchanged lines hidden (view full) ---
1037type=OpDesc
1038eventq_index=0
1039opClass=SimdFloatSqrt
1040opLat=1
1041pipelined=true
1042
1043[system.cpu1.fuPool.FUList6]
1044type=FUDesc
1045children=opList
1046count=0
1047eventq_index=0
1048opList=system.cpu1.fuPool.FUList6.opList
1049
1050[system.cpu1.fuPool.FUList6.opList]
1051type=OpDesc
1052eventq_index=0
1053opClass=MemWrite
1054opLat=1
1055pipelined=true
1056
1057[system.cpu1.fuPool.FUList7]
1058type=FUDesc
1059children=opList0 opList1
1060count=4
1061eventq_index=0
1062opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
1063
1064[system.cpu1.fuPool.FUList7.opList0]
1065type=OpDesc
1066eventq_index=0
1067opClass=MemRead
1068opLat=1
1069pipelined=true
1070
1071[system.cpu1.fuPool.FUList7.opList1]
1072type=OpDesc
1073eventq_index=0
1074opClass=MemWrite
1075opLat=1
1076pipelined=true
1077
1078[system.cpu1.fuPool.FUList8]
1079type=FUDesc
1080children=opList
1081count=1
1082eventq_index=0
1083opList=system.cpu1.fuPool.FUList8.opList
1084
1085[system.cpu1.fuPool.FUList8.opList]
--- 5 unchanged lines hidden (view full) ---
1091
1092[system.cpu1.icache]
1093type=Cache
1094children=tags
1095addr_ranges=0:18446744073709551615:0:0:0:0
1096assoc=1
1097clk_domain=system.cpu_clk_domain
1098clusivity=mostly_incl
1099default_p_state=UNDEFINED
1100demand_mshr_reserve=1
1101eventq_index=0
1102hit_latency=2
1103is_read_only=true
1104max_miss_count=0
1105mshrs=4
1106p_state_clk_gate_bins=20
1107p_state_clk_gate_max=1000000000000
1108p_state_clk_gate_min=1000
1109power_model=Null
1110prefetch_on_access=false
1111prefetcher=Null
1112response_latency=2
1113sequential_access=false
1114size=32768
1115system=system
1116tags=system.cpu1.icache.tags
1117tgts_per_mshr=20
1118write_buffers=8
1119writeback_clean=true
1120cpu_side=system.cpu1.icache_port
1121mem_side=system.toL2Bus.slave[2]
1122
1123[system.cpu1.icache.tags]
1124type=LRU
1125assoc=1
1126block_size=64
1127clk_domain=system.cpu_clk_domain
1128default_p_state=UNDEFINED
1129eventq_index=0
1130hit_latency=2
1131p_state_clk_gate_bins=20
1132p_state_clk_gate_max=1000000000000
1133p_state_clk_gate_min=1000
1134power_model=Null
1135sequential_access=false
1136size=32768
1137
1138[system.cpu1.interrupts]
1139type=SparcInterrupts
1140eventq_index=0
1141
1142[system.cpu1.isa]
1143type=SparcISA
1144eventq_index=0
--- 126 unchanged lines hidden (view full) ---
1271
1272[system.cpu2.dcache]
1273type=Cache
1274children=tags
1275addr_ranges=0:18446744073709551615:0:0:0:0
1276assoc=4
1277clk_domain=system.cpu_clk_domain
1278clusivity=mostly_incl
1279default_p_state=UNDEFINED
1280demand_mshr_reserve=1
1281eventq_index=0
1282hit_latency=2
1283is_read_only=false
1284max_miss_count=0
1285mshrs=4
1286p_state_clk_gate_bins=20
1287p_state_clk_gate_max=1000000000000
1288p_state_clk_gate_min=1000
1289power_model=Null
1290prefetch_on_access=false
1291prefetcher=Null
1292response_latency=2
1293sequential_access=false
1294size=32768
1295system=system
1296tags=system.cpu2.dcache.tags
1297tgts_per_mshr=20
1298write_buffers=8
1299writeback_clean=false
1300cpu_side=system.cpu2.dcache_port
1301mem_side=system.toL2Bus.slave[5]
1302
1303[system.cpu2.dcache.tags]
1304type=LRU
1305assoc=4
1306block_size=64
1307clk_domain=system.cpu_clk_domain
1308default_p_state=UNDEFINED
1309eventq_index=0
1310hit_latency=2
1311p_state_clk_gate_bins=20
1312p_state_clk_gate_max=1000000000000
1313p_state_clk_gate_min=1000
1314power_model=Null
1315sequential_access=false
1316size=32768
1317
1318[system.cpu2.dtb]
1319type=SparcTLB
1320eventq_index=0
1321size=64
1322
1323[system.cpu2.fuPool]
1324type=FUPool
--- 61 unchanged lines hidden (view full) ---
1386type=OpDesc
1387eventq_index=0
1388opClass=FloatCvt
1389opLat=2
1390pipelined=true
1391
1392[system.cpu2.fuPool.FUList3]
1393type=FUDesc
1394children=opList0 opList1 opList2
1395count=2
1396eventq_index=0
1397opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2
1398
1399[system.cpu2.fuPool.FUList3.opList0]
1400type=OpDesc
1401eventq_index=0
1402opClass=FloatMult
1403opLat=4
1404pipelined=true
1405
1406[system.cpu2.fuPool.FUList3.opList1]
1407type=OpDesc
1408eventq_index=0
1409opClass=FloatDiv
1410opLat=12
1411pipelined=false
1412
1413[system.cpu2.fuPool.FUList3.opList2]
1414type=OpDesc
1415eventq_index=0
1416opClass=FloatSqrt
1417opLat=24
1418pipelined=false
1419
1420[system.cpu2.fuPool.FUList4]
1421type=FUDesc
1422children=opList
1423count=0
1424eventq_index=0
1425opList=system.cpu2.fuPool.FUList4.opList
1426
1427[system.cpu2.fuPool.FUList4.opList]
1428type=OpDesc
1429eventq_index=0
1430opClass=MemRead
1431opLat=1
1432pipelined=true
1433
1434[system.cpu2.fuPool.FUList5]
1435type=FUDesc
1436children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
1437count=4
1438eventq_index=0
1439opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19
1440
1441[system.cpu2.fuPool.FUList5.opList00]
--- 133 unchanged lines hidden (view full) ---
1575type=OpDesc
1576eventq_index=0
1577opClass=SimdFloatSqrt
1578opLat=1
1579pipelined=true
1580
1581[system.cpu2.fuPool.FUList6]
1582type=FUDesc
1583children=opList
1584count=0
1585eventq_index=0
1586opList=system.cpu2.fuPool.FUList6.opList
1587
1588[system.cpu2.fuPool.FUList6.opList]
1589type=OpDesc
1590eventq_index=0
1591opClass=MemWrite
1592opLat=1
1593pipelined=true
1594
1595[system.cpu2.fuPool.FUList7]
1596type=FUDesc
1597children=opList0 opList1
1598count=4
1599eventq_index=0
1600opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
1601
1602[system.cpu2.fuPool.FUList7.opList0]
1603type=OpDesc
1604eventq_index=0
1605opClass=MemRead
1606opLat=1
1607pipelined=true
1608
1609[system.cpu2.fuPool.FUList7.opList1]
1610type=OpDesc
1611eventq_index=0
1612opClass=MemWrite
1613opLat=1
1614pipelined=true
1615
1616[system.cpu2.fuPool.FUList8]
1617type=FUDesc
1618children=opList
1619count=1
1620eventq_index=0
1621opList=system.cpu2.fuPool.FUList8.opList
1622
1623[system.cpu2.fuPool.FUList8.opList]
--- 5 unchanged lines hidden (view full) ---
1629
1630[system.cpu2.icache]
1631type=Cache
1632children=tags
1633addr_ranges=0:18446744073709551615:0:0:0:0
1634assoc=1
1635clk_domain=system.cpu_clk_domain
1636clusivity=mostly_incl
1637default_p_state=UNDEFINED
1638demand_mshr_reserve=1
1639eventq_index=0
1640hit_latency=2
1641is_read_only=true
1642max_miss_count=0
1643mshrs=4
1644p_state_clk_gate_bins=20
1645p_state_clk_gate_max=1000000000000
1646p_state_clk_gate_min=1000
1647power_model=Null
1648prefetch_on_access=false
1649prefetcher=Null
1650response_latency=2
1651sequential_access=false
1652size=32768
1653system=system
1654tags=system.cpu2.icache.tags
1655tgts_per_mshr=20
1656write_buffers=8
1657writeback_clean=true
1658cpu_side=system.cpu2.icache_port
1659mem_side=system.toL2Bus.slave[4]
1660
1661[system.cpu2.icache.tags]
1662type=LRU
1663assoc=1
1664block_size=64
1665clk_domain=system.cpu_clk_domain
1666default_p_state=UNDEFINED
1667eventq_index=0
1668hit_latency=2
1669p_state_clk_gate_bins=20
1670p_state_clk_gate_max=1000000000000
1671p_state_clk_gate_min=1000
1672power_model=Null
1673sequential_access=false
1674size=32768
1675
1676[system.cpu2.interrupts]
1677type=SparcInterrupts
1678eventq_index=0
1679
1680[system.cpu2.isa]
1681type=SparcISA
1682eventq_index=0
--- 126 unchanged lines hidden (view full) ---
1809
1810[system.cpu3.dcache]
1811type=Cache
1812children=tags
1813addr_ranges=0:18446744073709551615:0:0:0:0
1814assoc=4
1815clk_domain=system.cpu_clk_domain
1816clusivity=mostly_incl
1817default_p_state=UNDEFINED
1818demand_mshr_reserve=1
1819eventq_index=0
1820hit_latency=2
1821is_read_only=false
1822max_miss_count=0
1823mshrs=4
1824p_state_clk_gate_bins=20
1825p_state_clk_gate_max=1000000000000
1826p_state_clk_gate_min=1000
1827power_model=Null
1828prefetch_on_access=false
1829prefetcher=Null
1830response_latency=2
1831sequential_access=false
1832size=32768
1833system=system
1834tags=system.cpu3.dcache.tags
1835tgts_per_mshr=20
1836write_buffers=8
1837writeback_clean=false
1838cpu_side=system.cpu3.dcache_port
1839mem_side=system.toL2Bus.slave[7]
1840
1841[system.cpu3.dcache.tags]
1842type=LRU
1843assoc=4
1844block_size=64
1845clk_domain=system.cpu_clk_domain
1846default_p_state=UNDEFINED
1847eventq_index=0
1848hit_latency=2
1849p_state_clk_gate_bins=20
1850p_state_clk_gate_max=1000000000000
1851p_state_clk_gate_min=1000
1852power_model=Null
1853sequential_access=false
1854size=32768
1855
1856[system.cpu3.dtb]
1857type=SparcTLB
1858eventq_index=0
1859size=64
1860
1861[system.cpu3.fuPool]
1862type=FUPool
--- 61 unchanged lines hidden (view full) ---
1924type=OpDesc
1925eventq_index=0
1926opClass=FloatCvt
1927opLat=2
1928pipelined=true
1929
1930[system.cpu3.fuPool.FUList3]
1931type=FUDesc
1932children=opList0 opList1 opList2
1933count=2
1934eventq_index=0
1935opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2
1936
1937[system.cpu3.fuPool.FUList3.opList0]
1938type=OpDesc
1939eventq_index=0
1940opClass=FloatMult
1941opLat=4
1942pipelined=true
1943
1944[system.cpu3.fuPool.FUList3.opList1]
1945type=OpDesc
1946eventq_index=0
1947opClass=FloatDiv
1948opLat=12
1949pipelined=false
1950
1951[system.cpu3.fuPool.FUList3.opList2]
1952type=OpDesc
1953eventq_index=0
1954opClass=FloatSqrt
1955opLat=24
1956pipelined=false
1957
1958[system.cpu3.fuPool.FUList4]
1959type=FUDesc
1960children=opList
1961count=0
1962eventq_index=0
1963opList=system.cpu3.fuPool.FUList4.opList
1964
1965[system.cpu3.fuPool.FUList4.opList]
1966type=OpDesc
1967eventq_index=0
1968opClass=MemRead
1969opLat=1
1970pipelined=true
1971
1972[system.cpu3.fuPool.FUList5]
1973type=FUDesc
1974children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
1975count=4
1976eventq_index=0
1977opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19
1978
1979[system.cpu3.fuPool.FUList5.opList00]
--- 133 unchanged lines hidden (view full) ---
2113type=OpDesc
2114eventq_index=0
2115opClass=SimdFloatSqrt
2116opLat=1
2117pipelined=true
2118
2119[system.cpu3.fuPool.FUList6]
2120type=FUDesc
2121children=opList
2122count=0
2123eventq_index=0
2124opList=system.cpu3.fuPool.FUList6.opList
2125
2126[system.cpu3.fuPool.FUList6.opList]
2127type=OpDesc
2128eventq_index=0
2129opClass=MemWrite
2130opLat=1
2131pipelined=true
2132
2133[system.cpu3.fuPool.FUList7]
2134type=FUDesc
2135children=opList0 opList1
2136count=4
2137eventq_index=0
2138opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1
2139
2140[system.cpu3.fuPool.FUList7.opList0]
2141type=OpDesc
2142eventq_index=0
2143opClass=MemRead
2144opLat=1
2145pipelined=true
2146
2147[system.cpu3.fuPool.FUList7.opList1]
2148type=OpDesc
2149eventq_index=0
2150opClass=MemWrite
2151opLat=1
2152pipelined=true
2153
2154[system.cpu3.fuPool.FUList8]
2155type=FUDesc
2156children=opList
2157count=1
2158eventq_index=0
2159opList=system.cpu3.fuPool.FUList8.opList
2160
2161[system.cpu3.fuPool.FUList8.opList]
--- 5 unchanged lines hidden (view full) ---
2167
2168[system.cpu3.icache]
2169type=Cache
2170children=tags
2171addr_ranges=0:18446744073709551615:0:0:0:0
2172assoc=1
2173clk_domain=system.cpu_clk_domain
2174clusivity=mostly_incl
2175default_p_state=UNDEFINED
2176demand_mshr_reserve=1
2177eventq_index=0
2178hit_latency=2
2179is_read_only=true
2180max_miss_count=0
2181mshrs=4
2182p_state_clk_gate_bins=20
2183p_state_clk_gate_max=1000000000000
2184p_state_clk_gate_min=1000
2185power_model=Null
2186prefetch_on_access=false
2187prefetcher=Null
2188response_latency=2
2189sequential_access=false
2190size=32768
2191system=system
2192tags=system.cpu3.icache.tags
2193tgts_per_mshr=20
2194write_buffers=8
2195writeback_clean=true
2196cpu_side=system.cpu3.icache_port
2197mem_side=system.toL2Bus.slave[6]
2198
2199[system.cpu3.icache.tags]
2200type=LRU
2201assoc=1
2202block_size=64
2203clk_domain=system.cpu_clk_domain
2204default_p_state=UNDEFINED
2205eventq_index=0
2206hit_latency=2
2207p_state_clk_gate_bins=20
2208p_state_clk_gate_max=1000000000000
2209p_state_clk_gate_min=1000
2210power_model=Null
2211sequential_access=false
2212size=32768
2213
2214[system.cpu3.interrupts]
2215type=SparcInterrupts
2216eventq_index=0
2217
2218[system.cpu3.isa]
2219type=SparcISA
2220eventq_index=0
--- 25 unchanged lines hidden (view full) ---
2246
2247[system.l2c]
2248type=Cache
2249children=tags
2250addr_ranges=0:18446744073709551615:0:0:0:0
2251assoc=8
2252clk_domain=system.cpu_clk_domain
2253clusivity=mostly_incl
2254default_p_state=UNDEFINED
2255demand_mshr_reserve=1
2256eventq_index=0
2257hit_latency=20
2258is_read_only=false
2259max_miss_count=0
2260mshrs=20
2261p_state_clk_gate_bins=20
2262p_state_clk_gate_max=1000000000000
2263p_state_clk_gate_min=1000
2264power_model=Null
2265prefetch_on_access=false
2266prefetcher=Null
2267response_latency=20
2268sequential_access=false
2269size=4194304
2270system=system
2271tags=system.l2c.tags
2272tgts_per_mshr=12
2273write_buffers=8
2274writeback_clean=false
2275cpu_side=system.toL2Bus.master[0]
2276mem_side=system.membus.slave[1]
2277
2278[system.l2c.tags]
2279type=LRU
2280assoc=8
2281block_size=64
2282clk_domain=system.cpu_clk_domain
2283default_p_state=UNDEFINED
2284eventq_index=0
2285hit_latency=20
2286p_state_clk_gate_bins=20
2287p_state_clk_gate_max=1000000000000
2288p_state_clk_gate_min=1000
2289power_model=Null
2290sequential_access=false
2291size=4194304
2292
2293[system.membus]
2294type=CoherentXBar
2295children=snoop_filter
2296clk_domain=system.clk_domain
2297default_p_state=UNDEFINED
2298eventq_index=0
2299forward_latency=4
--- 139 unchanged lines hidden ---