1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

--- 9 unchanged lines hidden (view full) ---

18init_param=0
19kernel=
20kernel_addr_check=true
21load_addr_mask=1099511627775
22load_offset=0
23mem_mode=timing
24mem_ranges=
25memories=system.physmem
26mmap_using_noreserve=false
27num_work_ids=16
28readfile=
29symbolfile=
30work_begin_ckpt_count=0
31work_begin_cpu_id_exit=-1
32work_begin_exit_count=0
33work_cpus_ckpt_count=0
34work_end_ckpt_count=0

--- 2111 unchanged lines hidden (view full) ---

2146hit_latency=20
2147sequential_access=false
2148size=4194304
2149
2150[system.membus]
2151type=CoherentXBar
2152clk_domain=system.clk_domain
2153eventq_index=0
2154forward_latency=4
2155frontend_latency=3
2156response_latency=2
2157snoop_filter=Null
2158snoop_response_latency=4
2159system=system
2160use_default_range=false
2161width=16
2162master=system.physmem.port
2163slave=system.system_port system.l2c.mem_side
2164
2165[system.physmem]
2166type=DRAMCtrl
2167IDD0=0.075000
2168IDD02=0.000000
2169IDD2N=0.050000

--- 14 unchanged lines hidden (view full) ---

2184IDD4W2=0.000000
2185IDD5=0.220000
2186IDD52=0.000000
2187IDD6=0.000000
2188IDD62=0.000000
2189VDD=1.500000
2190VDD2=0.000000
2191activation_limit=4
2192addr_mapping=RoRaBaCoCh
2193bank_groups_per_rank=0
2194banks_per_rank=8
2195burst_length=8
2196channels=1
2197clk_domain=system.clk_domain
2198conf_table_reported=true
2199device_bus_width=8
2200device_rowbuffer_size=1024

--- 37 unchanged lines hidden (view full) ---

2238write_high_thresh_perc=85
2239write_low_thresh_perc=50
2240port=system.membus.master[0]
2241
2242[system.toL2Bus]
2243type=CoherentXBar
2244clk_domain=system.cpu_clk_domain
2245eventq_index=0
2246forward_latency=0
2247frontend_latency=1
2248response_latency=1
2249snoop_filter=Null
2250snoop_response_latency=1
2251system=system
2252use_default_range=false
2253width=32
2254master=system.l2c.cpu_side
2255slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
2256
2257[system.voltage_domain]
2258type=VoltageDomain
2259eventq_index=0
2260voltage=1.000000
2261