Cross Reference: /gem5/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 0.147149 # Number of seconds simulated
4sim_ticks 147148719500 # Number of ticks simulated
5final_tick 147148719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 0.147164 # Number of seconds simulated
4sim_ticks 147164058500 # Number of ticks simulated
5final_tick 147164058500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 664401 # Simulator instruction rate (inst/s)
8host_op_rate 667702 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1079367051 # Simulator tick rate (ticks/s)
10host_mem_usage 398392 # Number of bytes of host memory used
11host_seconds 136.33 # Real time elapsed on the host

7host_inst_rate 748296 # Simulator instruction rate (inst/s)
8host_op_rate 752015 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1215788381 # Simulator tick rate (ticks/s)
10host_mem_usage 404056 # Number of bytes of host memory used
11host_seconds 121.04 # Real time elapsed on the host

12sim_insts 90576862 # Number of instructions simulated
13sim_ops 91026991 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states

16system.physmem.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states

17system.physmem.bytes_read::cpu.inst 36928 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 944832 # Number of bytes read from this memory
19system.physmem.bytes_read::total 981760 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 36928 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 36928 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 577 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 14763 # Number of read requests responded to by this memory
24system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory

25system.physmem.bw_read::cpu.inst 250957 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::cpu.data 6420933 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 6671890 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 250957 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 250957 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_total::cpu.inst 250957 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::cpu.data 6420933 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bw_total::total 6671890 # Total bandwidth to/from this memory (bytes/s)
33system.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states

25system.physmem.bw_read::cpu.inst 250931 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::cpu.data 6420263 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 6671194 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 250931 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 250931 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_total::cpu.inst 250931 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::cpu.data 6420263 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bw_total::total 6671194 # Total bandwidth to/from this memory (bytes/s)
33system.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states

34system.cpu_clk_domain.clock 500 # Clock period in ticks

35system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states

35system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states

36system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

57system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
58system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
59system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
60system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
61system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
62system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
63system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
64system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

65system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states

65system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states

66system.cpu.dtb.walker.walks 0 # Table walker walks requested
67system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
68system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
69system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
70system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
71system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
72system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
73system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

87system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
88system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
89system.cpu.dtb.read_accesses 0 # DTB read accesses
90system.cpu.dtb.write_accesses 0 # DTB write accesses
91system.cpu.dtb.inst_accesses 0 # ITB inst accesses
92system.cpu.dtb.hits 0 # DTB hits
93system.cpu.dtb.misses 0 # DTB misses
94system.cpu.dtb.accesses 0 # DTB accesses

95system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states

95system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states

96system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

117system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
118system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
119system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
120system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
121system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
122system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
123system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
124system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

125system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states

125system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states

126system.cpu.itb.walker.walks 0 # Table walker walks requested
127system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
128system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
129system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
130system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
131system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
132system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
133system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

148system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
149system.cpu.itb.read_accesses 0 # DTB read accesses
150system.cpu.itb.write_accesses 0 # DTB write accesses
151system.cpu.itb.inst_accesses 0 # ITB inst accesses
152system.cpu.itb.hits 0 # DTB hits
153system.cpu.itb.misses 0 # DTB misses
154system.cpu.itb.accesses 0 # DTB accesses
155system.cpu.workload.num_syscalls 442 # Number of system calls

156system.cpu.pwrStateResidencyTicks::ON 147148719500 # Cumulative time (in ticks) in various power states
157system.cpu.numCycles 294297439 # number of cpu cycles simulated

156system.cpu.pwrStateResidencyTicks::ON 147164058500 # Cumulative time (in ticks) in various power states
157system.cpu.numCycles 294328117 # number of cpu cycles simulated

158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
160system.cpu.committedInsts 90576862 # Number of instructions committed
161system.cpu.committedOps 91026991 # Number of ops (including micro ops) committed
162system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses
163system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
164system.cpu.num_func_calls 112245 # number of times a function call or return occured
165system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls

--- 4 unchanged lines hidden (view full) ---

170system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
171system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
172system.cpu.num_cc_register_reads 339191621 # number of times the CC registers were read
173system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written
174system.cpu.num_mem_refs 27220755 # number of memory refs
175system.cpu.num_load_insts 22475911 # Number of load instructions
176system.cpu.num_store_insts 4744844 # Number of store instructions
177system.cpu.num_idle_cycles 0.002000 # Number of idle cycles

178system.cpu.num_busy_cycles 294297438.998000 # Number of busy cycles

178system.cpu.num_busy_cycles 294328116.998000 # Number of busy cycles

179system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
180system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
181system.cpu.Branches 18732305 # Number of branches fetched
182system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
183system.cpu.op_class::IntAlu 63822829 70.09% 70.09% # Class of executed instruction
184system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction
185system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction
186system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction

--- 22 unchanged lines hidden (view full) ---

209system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction
210system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction
211system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction
212system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction
213system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction
214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
216system.cpu.op_class::total 91054081 # Class of executed instruction

217system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states

217system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states

218system.cpu.dcache.tags.replacements 942702 # number of replacements

219system.cpu.dcache.tags.tagsinuse 3565.478025 # Cycle average of tags in use

219system.cpu.dcache.tags.tagsinuse 3565.461526 # Cycle average of tags in use

220system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks.
221system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks.
222system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks.

223system.cpu.dcache.tags.warmup_cycle 54453325500 # Cycle when the warmup percentage was hit.
224system.cpu.dcache.tags.occ_blocks::cpu.data 3565.478025 # Average occupied blocks per requestor
225system.cpu.dcache.tags.occ_percent::cpu.data 0.870478 # Average percentage of cache occupancy
226system.cpu.dcache.tags.occ_percent::total 0.870478 # Average percentage of cache occupancy

223system.cpu.dcache.tags.warmup_cycle 54459450500 # Cycle when the warmup percentage was hit.
224system.cpu.dcache.tags.occ_blocks::cpu.data 3565.461526 # Average occupied blocks per requestor
225system.cpu.dcache.tags.occ_percent::cpu.data 0.870474 # Average percentage of cache occupancy
226system.cpu.dcache.tags.occ_percent::total 0.870474 # Average percentage of cache occupancy

227system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id

228system.cpu.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
229system.cpu.dcache.tags.age_task_id_blocks_1024::1 1357 # Occupied blocks per task id
230system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id

228system.cpu.dcache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id
229system.cpu.dcache.tags.age_task_id_blocks_1024::1 1358 # Occupied blocks per task id
230system.cpu.dcache.tags.age_task_id_blocks_1024::2 2564 # Occupied blocks per task id

231system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id
232system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
233system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses
234system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses

235system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states

235system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states

236system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits
237system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits
238system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits
239system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits
240system.cpu.dcache.SoftPFReq_hits::cpu.data 507 # number of SoftPFReq hits
241system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits
242system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
243system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits

--- 8 unchanged lines hidden (view full) ---

252system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses
253system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses
254system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses
255system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses
256system.cpu.dcache.demand_misses::cpu.data 946796 # number of demand (read+write) misses
257system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses
258system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses
259system.cpu.dcache.overall_misses::total 946799 # number of overall misses

260system.cpu.dcache.ReadReq_miss_latency::cpu.data 11713009000 # number of ReadReq miss cycles
261system.cpu.dcache.ReadReq_miss_latency::total 11713009000 # number of ReadReq miss cycles
262system.cpu.dcache.WriteReq_miss_latency::cpu.data 1319019500 # number of WriteReq miss cycles
263system.cpu.dcache.WriteReq_miss_latency::total 1319019500 # number of WriteReq miss cycles
264system.cpu.dcache.demand_miss_latency::cpu.data 13032028500 # number of demand (read+write) miss cycles
265system.cpu.dcache.demand_miss_latency::total 13032028500 # number of demand (read+write) miss cycles
266system.cpu.dcache.overall_miss_latency::cpu.data 13032028500 # number of overall miss cycles
267system.cpu.dcache.overall_miss_latency::total 13032028500 # number of overall miss cycles

260system.cpu.dcache.ReadReq_miss_latency::cpu.data 11713223000 # number of ReadReq miss cycles
261system.cpu.dcache.ReadReq_miss_latency::total 11713223000 # number of ReadReq miss cycles
262system.cpu.dcache.WriteReq_miss_latency::cpu.data 1333567500 # number of WriteReq miss cycles
263system.cpu.dcache.WriteReq_miss_latency::total 1333567500 # number of WriteReq miss cycles
264system.cpu.dcache.demand_miss_latency::cpu.data 13046790500 # number of demand (read+write) miss cycles
265system.cpu.dcache.demand_miss_latency::total 13046790500 # number of demand (read+write) miss cycles
266system.cpu.dcache.overall_miss_latency::cpu.data 13046790500 # number of overall miss cycles
267system.cpu.dcache.overall_miss_latency::total 13046790500 # number of overall miss cycles

268system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses)
269system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses)
270system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
271system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
272system.cpu.dcache.SoftPFReq_accesses::cpu.data 510 # number of SoftPFReq accesses(hits+misses)
273system.cpu.dcache.SoftPFReq_accesses::total 510 # number of SoftPFReq accesses(hits+misses)
274system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
275system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)

--- 8 unchanged lines hidden (view full) ---

284system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses
285system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses
286system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005882 # miss rate for SoftPFReq accesses
287system.cpu.dcache.SoftPFReq_miss_rate::total 0.005882 # miss rate for SoftPFReq accesses
288system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 # miss rate for demand accesses
289system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses
290system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses
291system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses

292system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13011.750892 # average ReadReq miss latency
293system.cpu.dcache.ReadReq_avg_miss_latency::total 13011.750892 # average ReadReq miss latency
294system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28299.673883 # average WriteReq miss latency
295system.cpu.dcache.WriteReq_avg_miss_latency::total 28299.673883 # average WriteReq miss latency
296system.cpu.dcache.demand_avg_miss_latency::cpu.data 13764.346808 # average overall miss latency
297system.cpu.dcache.demand_avg_miss_latency::total 13764.346808 # average overall miss latency
298system.cpu.dcache.overall_avg_miss_latency::cpu.data 13764.303194 # average overall miss latency
299system.cpu.dcache.overall_avg_miss_latency::total 13764.303194 # average overall miss latency

292system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13011.988620 # average ReadReq miss latency
293system.cpu.dcache.ReadReq_avg_miss_latency::total 13011.988620 # average ReadReq miss latency
294system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28611.802442 # average WriteReq miss latency
295system.cpu.dcache.WriteReq_avg_miss_latency::total 28611.802442 # average WriteReq miss latency
296system.cpu.dcache.demand_avg_miss_latency::cpu.data 13779.938339 # average overall miss latency
297system.cpu.dcache.demand_avg_miss_latency::total 13779.938339 # average overall miss latency
298system.cpu.dcache.overall_avg_miss_latency::cpu.data 13779.894677 # average overall miss latency
299system.cpu.dcache.overall_avg_miss_latency::total 13779.894677 # average overall miss latency

300system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
301system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
302system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
303system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
304system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
305system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
306system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks
307system.cpu.dcache.writebacks::total 942334 # number of writebacks

--- 8 unchanged lines hidden (view full) ---

316system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses
317system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses
318system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
319system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
320system.cpu.dcache.demand_mshr_misses::cpu.data 946795 # number of demand (read+write) MSHR misses
321system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses
322system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses
323system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses

324system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10812776000 # number of ReadReq MSHR miss cycles
325system.cpu.dcache.ReadReq_mshr_miss_latency::total 10812776000 # number of ReadReq MSHR miss cycles
326system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1272410500 # number of WriteReq MSHR miss cycles
327system.cpu.dcache.WriteReq_mshr_miss_latency::total 1272410500 # number of WriteReq MSHR miss cycles
328system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 134000 # number of SoftPFReq MSHR miss cycles
329system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 134000 # number of SoftPFReq MSHR miss cycles
330system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12085186500 # number of demand (read+write) MSHR miss cycles
331system.cpu.dcache.demand_mshr_miss_latency::total 12085186500 # number of demand (read+write) MSHR miss cycles
332system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12085320500 # number of overall MSHR miss cycles
333system.cpu.dcache.overall_mshr_miss_latency::total 12085320500 # number of overall MSHR miss cycles

324system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10812989000 # number of ReadReq MSHR miss cycles
325system.cpu.dcache.ReadReq_mshr_miss_latency::total 10812989000 # number of ReadReq MSHR miss cycles
326system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1286958500 # number of WriteReq MSHR miss cycles
327system.cpu.dcache.WriteReq_mshr_miss_latency::total 1286958500 # number of WriteReq MSHR miss cycles
328system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 136000 # number of SoftPFReq MSHR miss cycles
329system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 136000 # number of SoftPFReq MSHR miss cycles
330system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12099947500 # number of demand (read+write) MSHR miss cycles
331system.cpu.dcache.demand_mshr_miss_latency::total 12099947500 # number of demand (read+write) MSHR miss cycles
332system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12100083500 # number of overall MSHR miss cycles
333system.cpu.dcache.overall_mshr_miss_latency::total 12100083500 # number of overall MSHR miss cycles

334system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses
335system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses
336system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses
337system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses
338system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005882 # mshr miss rate for SoftPFReq accesses
339system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005882 # mshr miss rate for SoftPFReq accesses
340system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 # mshr miss rate for demand accesses
341system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses
342system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses
343system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses

344system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12011.713135 # average ReadReq mshr miss latency
345system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12011.713135 # average ReadReq mshr miss latency
346system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27299.673883 # average WriteReq mshr miss latency
347system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27299.673883 # average WriteReq mshr miss latency
348system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44666.666667 # average SoftPFReq mshr miss latency
349system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44666.666667 # average SoftPFReq mshr miss latency
350system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12764.311704 # average overall mshr miss latency
351system.cpu.dcache.demand_avg_mshr_miss_latency::total 12764.311704 # average overall mshr miss latency
352system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12764.412789 # average overall mshr miss latency
353system.cpu.dcache.overall_avg_mshr_miss_latency::total 12764.412789 # average overall mshr miss latency
354system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states

344system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12011.949753 # average ReadReq mshr miss latency
345system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12011.949753 # average ReadReq mshr miss latency
346system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27611.802442 # average WriteReq mshr miss latency
347system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27611.802442 # average WriteReq mshr miss latency
348system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 45333.333333 # average SoftPFReq mshr miss latency
349system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 45333.333333 # average SoftPFReq mshr miss latency
350system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12779.902196 # average overall mshr miss latency
351system.cpu.dcache.demand_avg_mshr_miss_latency::total 12779.902196 # average overall mshr miss latency
352system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12780.005344 # average overall mshr miss latency
353system.cpu.dcache.overall_avg_mshr_miss_latency::total 12780.005344 # average overall mshr miss latency
354system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states

355system.cpu.icache.tags.replacements 2 # number of replacements

356system.cpu.icache.tags.tagsinuse 510.111710 # Cycle average of tags in use

356system.cpu.icache.tags.tagsinuse 510.110453 # Cycle average of tags in use

357system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks.
358system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks.
359system.cpu.icache.tags.avg_refs 180016.983306 # Average number of references to valid blocks.
360system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

361system.cpu.icache.tags.occ_blocks::cpu.inst 510.111710 # Average occupied blocks per requestor
362system.cpu.icache.tags.occ_percent::cpu.inst 0.249078 # Average percentage of cache occupancy
363system.cpu.icache.tags.occ_percent::total 0.249078 # Average percentage of cache occupancy

361system.cpu.icache.tags.occ_blocks::cpu.inst 510.110453 # Average occupied blocks per requestor
362system.cpu.icache.tags.occ_percent::cpu.inst 0.249077 # Average percentage of cache occupancy
363system.cpu.icache.tags.occ_percent::total 0.249077 # Average percentage of cache occupancy

364system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id
365system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
366system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
367system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
368system.cpu.icache.tags.age_task_id_blocks_1024::4 552 # Occupied blocks per task id
369system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id
370system.cpu.icache.tags.tag_accesses 215662143 # Number of tag accesses
371system.cpu.icache.tags.data_accesses 215662143 # Number of data accesses

372system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states

372system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states

373system.cpu.icache.ReadReq_hits::cpu.inst 107830173 # number of ReadReq hits
374system.cpu.icache.ReadReq_hits::total 107830173 # number of ReadReq hits
375system.cpu.icache.demand_hits::cpu.inst 107830173 # number of demand (read+write) hits
376system.cpu.icache.demand_hits::total 107830173 # number of demand (read+write) hits
377system.cpu.icache.overall_hits::cpu.inst 107830173 # number of overall hits
378system.cpu.icache.overall_hits::total 107830173 # number of overall hits
379system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses
380system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses
381system.cpu.icache.demand_misses::cpu.inst 599 # number of demand (read+write) misses
382system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses
383system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses
384system.cpu.icache.overall_misses::total 599 # number of overall misses

385system.cpu.icache.ReadReq_miss_latency::cpu.inst 36093000 # number of ReadReq miss cycles
386system.cpu.icache.ReadReq_miss_latency::total 36093000 # number of ReadReq miss cycles
387system.cpu.icache.demand_miss_latency::cpu.inst 36093000 # number of demand (read+write) miss cycles
388system.cpu.icache.demand_miss_latency::total 36093000 # number of demand (read+write) miss cycles
389system.cpu.icache.overall_miss_latency::cpu.inst 36093000 # number of overall miss cycles
390system.cpu.icache.overall_miss_latency::total 36093000 # number of overall miss cycles

385system.cpu.icache.ReadReq_miss_latency::cpu.inst 36670000 # number of ReadReq miss cycles
386system.cpu.icache.ReadReq_miss_latency::total 36670000 # number of ReadReq miss cycles
387system.cpu.icache.demand_miss_latency::cpu.inst 36670000 # number of demand (read+write) miss cycles
388system.cpu.icache.demand_miss_latency::total 36670000 # number of demand (read+write) miss cycles
389system.cpu.icache.overall_miss_latency::cpu.inst 36670000 # number of overall miss cycles
390system.cpu.icache.overall_miss_latency::total 36670000 # number of overall miss cycles

391system.cpu.icache.ReadReq_accesses::cpu.inst 107830772 # number of ReadReq accesses(hits+misses)
392system.cpu.icache.ReadReq_accesses::total 107830772 # number of ReadReq accesses(hits+misses)
393system.cpu.icache.demand_accesses::cpu.inst 107830772 # number of demand (read+write) accesses
394system.cpu.icache.demand_accesses::total 107830772 # number of demand (read+write) accesses
395system.cpu.icache.overall_accesses::cpu.inst 107830772 # number of overall (read+write) accesses
396system.cpu.icache.overall_accesses::total 107830772 # number of overall (read+write) accesses
397system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses
398system.cpu.icache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses
399system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses
400system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses
401system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses
402system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses

403system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60255.425710 # average ReadReq miss latency
404system.cpu.icache.ReadReq_avg_miss_latency::total 60255.425710 # average ReadReq miss latency
405system.cpu.icache.demand_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency
406system.cpu.icache.demand_avg_miss_latency::total 60255.425710 # average overall miss latency
407system.cpu.icache.overall_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency
408system.cpu.icache.overall_avg_miss_latency::total 60255.425710 # average overall miss latency

403system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61218.697830 # average ReadReq miss latency
404system.cpu.icache.ReadReq_avg_miss_latency::total 61218.697830 # average ReadReq miss latency
405system.cpu.icache.demand_avg_miss_latency::cpu.inst 61218.697830 # average overall miss latency
406system.cpu.icache.demand_avg_miss_latency::total 61218.697830 # average overall miss latency
407system.cpu.icache.overall_avg_miss_latency::cpu.inst 61218.697830 # average overall miss latency
408system.cpu.icache.overall_avg_miss_latency::total 61218.697830 # average overall miss latency

409system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
410system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
411system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
412system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
413system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
414system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
415system.cpu.icache.writebacks::writebacks 2 # number of writebacks
416system.cpu.icache.writebacks::total 2 # number of writebacks
417system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses
418system.cpu.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses
419system.cpu.icache.demand_mshr_misses::cpu.inst 599 # number of demand (read+write) MSHR misses
420system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses
421system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses
422system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses

423system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35494000 # number of ReadReq MSHR miss cycles
424system.cpu.icache.ReadReq_mshr_miss_latency::total 35494000 # number of ReadReq MSHR miss cycles
425system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35494000 # number of demand (read+write) MSHR miss cycles
426system.cpu.icache.demand_mshr_miss_latency::total 35494000 # number of demand (read+write) MSHR miss cycles
427system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35494000 # number of overall MSHR miss cycles
428system.cpu.icache.overall_mshr_miss_latency::total 35494000 # number of overall MSHR miss cycles

423system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36071000 # number of ReadReq MSHR miss cycles
424system.cpu.icache.ReadReq_mshr_miss_latency::total 36071000 # number of ReadReq MSHR miss cycles
425system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36071000 # number of demand (read+write) MSHR miss cycles
426system.cpu.icache.demand_mshr_miss_latency::total 36071000 # number of demand (read+write) MSHR miss cycles
427system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36071000 # number of overall MSHR miss cycles
428system.cpu.icache.overall_mshr_miss_latency::total 36071000 # number of overall MSHR miss cycles

429system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses
430system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
431system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses
432system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses
433system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses
434system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses

435system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59255.425710 # average ReadReq mshr miss latency
436system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59255.425710 # average ReadReq mshr miss latency
437system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency
438system.cpu.icache.demand_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency
439system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency
440system.cpu.icache.overall_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency
441system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states

435system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60218.697830 # average ReadReq mshr miss latency
436system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60218.697830 # average ReadReq mshr miss latency
437system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60218.697830 # average overall mshr miss latency
438system.cpu.icache.demand_avg_mshr_miss_latency::total 60218.697830 # average overall mshr miss latency
439system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60218.697830 # average overall mshr miss latency
440system.cpu.icache.overall_avg_mshr_miss_latency::total 60218.697830 # average overall mshr miss latency
441system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states

442system.cpu.l2cache.tags.replacements 0 # number of replacements

443system.cpu.l2cache.tags.tagsinuse 9564.658425 # Cycle average of tags in use
444system.cpu.l2cache.tags.total_refs 1827433 # Total number of references to valid blocks.
445system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks.
446system.cpu.l2cache.tags.avg_refs 119.260784 # Average number of references to valid blocks.

443system.cpu.l2cache.tags.tagsinuse 10666.571104 # Cycle average of tags in use
444system.cpu.l2cache.tags.total_refs 1874647 # Total number of references to valid blocks.
445system.cpu.l2cache.tags.sampled_refs 15340 # Sample count of references to valid blocks.
446system.cpu.l2cache.tags.avg_refs 122.206454 # Average number of references to valid blocks.

447system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

448system.cpu.l2cache.tags.occ_blocks::writebacks 8876.269803 # Average occupied blocks per requestor
449system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.164592 # Average occupied blocks per requestor
450system.cpu.l2cache.tags.occ_blocks::cpu.data 194.224030 # Average occupied blocks per requestor
451system.cpu.l2cache.tags.occ_percent::writebacks 0.270882 # Average percentage of cache occupancy

448system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.163402 # Average occupied blocks per requestor
449system.cpu.l2cache.tags.occ_blocks::cpu.data 10172.407702 # Average occupied blocks per requestor

452system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015081 # Average percentage of cache occupancy

450system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015081 # Average percentage of cache occupancy

453system.cpu.l2cache.tags.occ_percent::cpu.data 0.005927 # Average percentage of cache occupancy
454system.cpu.l2cache.tags.occ_percent::total 0.291890 # Average percentage of cache occupancy
455system.cpu.l2cache.tags.occ_task_id_blocks::1024 15323 # Occupied blocks per task id

451system.cpu.l2cache.tags.occ_percent::cpu.data 0.310437 # Average percentage of cache occupancy
452system.cpu.l2cache.tags.occ_percent::total 0.325518 # Average percentage of cache occupancy
453system.cpu.l2cache.tags.occ_task_id_blocks::1024 15340 # Occupied blocks per task id

456system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
457system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id

454system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
455system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id

458system.cpu.l2cache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id
459system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1473 # Occupied blocks per task id
460system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13704 # Occupied blocks per task id
461system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id
462system.cpu.l2cache.tags.tag_accesses 15181828 # Number of tag accesses
463system.cpu.l2cache.tags.data_accesses 15181828 # Number of data accesses
464system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states

456system.cpu.l2cache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id
457system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
458system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15229 # Occupied blocks per task id
459system.cpu.l2cache.tags.occ_task_id_percent::1024 0.468140 # Percentage of cache occupancy per task id
460system.cpu.l2cache.tags.tag_accesses 15135236 # Number of tag accesses
461system.cpu.l2cache.tags.data_accesses 15135236 # Number of data accesses
462system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states

465system.cpu.l2cache.WritebackDirty_hits::writebacks 942334 # number of WritebackDirty hits
466system.cpu.l2cache.WritebackDirty_hits::total 942334 # number of WritebackDirty hits
467system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits
468system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits
469system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits
470system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits
471system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits
472system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits

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485system.cpu.l2cache.ReadSharedReq_misses::cpu.data 215 # number of ReadSharedReq misses
486system.cpu.l2cache.ReadSharedReq_misses::total 215 # number of ReadSharedReq misses
487system.cpu.l2cache.demand_misses::cpu.inst 577 # number of demand (read+write) misses
488system.cpu.l2cache.demand_misses::cpu.data 14763 # number of demand (read+write) misses
489system.cpu.l2cache.demand_misses::total 15340 # number of demand (read+write) misses
490system.cpu.l2cache.overall_misses::cpu.inst 577 # number of overall misses
491system.cpu.l2cache.overall_misses::cpu.data 14763 # number of overall misses
492system.cpu.l2cache.overall_misses::total 15340 # number of overall misses

463system.cpu.l2cache.WritebackDirty_hits::writebacks 942334 # number of WritebackDirty hits
464system.cpu.l2cache.WritebackDirty_hits::total 942334 # number of WritebackDirty hits
465system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits
466system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits
467system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits
468system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits
469system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits
470system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits

--- 12 unchanged lines hidden (view full) ---

483system.cpu.l2cache.ReadSharedReq_misses::cpu.data 215 # number of ReadSharedReq misses
484system.cpu.l2cache.ReadSharedReq_misses::total 215 # number of ReadSharedReq misses
485system.cpu.l2cache.demand_misses::cpu.inst 577 # number of demand (read+write) misses
486system.cpu.l2cache.demand_misses::cpu.data 14763 # number of demand (read+write) misses
487system.cpu.l2cache.demand_misses::total 15340 # number of demand (read+write) misses
488system.cpu.l2cache.overall_misses::cpu.inst 577 # number of overall misses
489system.cpu.l2cache.overall_misses::cpu.data 14763 # number of overall misses
490system.cpu.l2cache.overall_misses::total 15340 # number of overall misses

493system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 865856500 # number of ReadExReq miss cycles
494system.cpu.l2cache.ReadExReq_miss_latency::total 865856500 # number of ReadExReq miss cycles
495system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 34343500 # number of ReadCleanReq miss cycles
496system.cpu.l2cache.ReadCleanReq_miss_latency::total 34343500 # number of ReadCleanReq miss cycles
497system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12794500 # number of ReadSharedReq miss cycles
498system.cpu.l2cache.ReadSharedReq_miss_latency::total 12794500 # number of ReadSharedReq miss cycles
499system.cpu.l2cache.demand_miss_latency::cpu.inst 34343500 # number of demand (read+write) miss cycles
500system.cpu.l2cache.demand_miss_latency::cpu.data 878651000 # number of demand (read+write) miss cycles
501system.cpu.l2cache.demand_miss_latency::total 912994500 # number of demand (read+write) miss cycles
502system.cpu.l2cache.overall_miss_latency::cpu.inst 34343500 # number of overall miss cycles
503system.cpu.l2cache.overall_miss_latency::cpu.data 878651000 # number of overall miss cycles
504system.cpu.l2cache.overall_miss_latency::total 912994500 # number of overall miss cycles

491system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 880404500 # number of ReadExReq miss cycles
492system.cpu.l2cache.ReadExReq_miss_latency::total 880404500 # number of ReadExReq miss cycles
493system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 34920500 # number of ReadCleanReq miss cycles
494system.cpu.l2cache.ReadCleanReq_miss_latency::total 34920500 # number of ReadCleanReq miss cycles
495system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13009500 # number of ReadSharedReq miss cycles
496system.cpu.l2cache.ReadSharedReq_miss_latency::total 13009500 # number of ReadSharedReq miss cycles
497system.cpu.l2cache.demand_miss_latency::cpu.inst 34920500 # number of demand (read+write) miss cycles
498system.cpu.l2cache.demand_miss_latency::cpu.data 893414000 # number of demand (read+write) miss cycles
499system.cpu.l2cache.demand_miss_latency::total 928334500 # number of demand (read+write) miss cycles
500system.cpu.l2cache.overall_miss_latency::cpu.inst 34920500 # number of overall miss cycles
501system.cpu.l2cache.overall_miss_latency::cpu.data 893414000 # number of overall miss cycles
502system.cpu.l2cache.overall_miss_latency::total 928334500 # number of overall miss cycles

505system.cpu.l2cache.WritebackDirty_accesses::writebacks 942334 # number of WritebackDirty accesses(hits+misses)
506system.cpu.l2cache.WritebackDirty_accesses::total 942334 # number of WritebackDirty accesses(hits+misses)
507system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses)
508system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses)
509system.cpu.l2cache.ReadExReq_accesses::cpu.data 46609 # number of ReadExReq accesses(hits+misses)
510system.cpu.l2cache.ReadExReq_accesses::total 46609 # number of ReadExReq accesses(hits+misses)
511system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 599 # number of ReadCleanReq accesses(hits+misses)
512system.cpu.l2cache.ReadCleanReq_accesses::total 599 # number of ReadCleanReq accesses(hits+misses)

--- 12 unchanged lines hidden (view full) ---

525system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000239 # miss rate for ReadSharedReq accesses
526system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000239 # miss rate for ReadSharedReq accesses
527system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963272 # miss rate for demand accesses
528system.cpu.l2cache.demand_miss_rate::cpu.data 0.015593 # miss rate for demand accesses
529system.cpu.l2cache.demand_miss_rate::total 0.016192 # miss rate for demand accesses
530system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963272 # miss rate for overall accesses
531system.cpu.l2cache.overall_miss_rate::cpu.data 0.015593 # miss rate for overall accesses
532system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses

503system.cpu.l2cache.WritebackDirty_accesses::writebacks 942334 # number of WritebackDirty accesses(hits+misses)
504system.cpu.l2cache.WritebackDirty_accesses::total 942334 # number of WritebackDirty accesses(hits+misses)
505system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses)
506system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses)
507system.cpu.l2cache.ReadExReq_accesses::cpu.data 46609 # number of ReadExReq accesses(hits+misses)
508system.cpu.l2cache.ReadExReq_accesses::total 46609 # number of ReadExReq accesses(hits+misses)
509system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 599 # number of ReadCleanReq accesses(hits+misses)
510system.cpu.l2cache.ReadCleanReq_accesses::total 599 # number of ReadCleanReq accesses(hits+misses)

--- 12 unchanged lines hidden (view full) ---

523system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000239 # miss rate for ReadSharedReq accesses
524system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000239 # miss rate for ReadSharedReq accesses
525system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963272 # miss rate for demand accesses
526system.cpu.l2cache.demand_miss_rate::cpu.data 0.015593 # miss rate for demand accesses
527system.cpu.l2cache.demand_miss_rate::total 0.016192 # miss rate for demand accesses
528system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963272 # miss rate for overall accesses
529system.cpu.l2cache.overall_miss_rate::cpu.data 0.015593 # miss rate for overall accesses
530system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses

533system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59517.218862 # average ReadExReq miss latency
534system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59517.218862 # average ReadExReq miss latency
535system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59520.797227 # average ReadCleanReq miss latency
536system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59520.797227 # average ReadCleanReq miss latency
537system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59509.302326 # average ReadSharedReq miss latency
538system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59509.302326 # average ReadSharedReq miss latency
539system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59520.797227 # average overall miss latency
540system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency
541system.cpu.l2cache.demand_avg_miss_latency::total 59517.242503 # average overall miss latency
542system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59520.797227 # average overall miss latency
543system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency
544system.cpu.l2cache.overall_avg_miss_latency::total 59517.242503 # average overall miss latency

531system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60517.218862 # average ReadExReq miss latency
532system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60517.218862 # average ReadExReq miss latency
533system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60520.797227 # average ReadCleanReq miss latency
534system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60520.797227 # average ReadCleanReq miss latency
535system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60509.302326 # average ReadSharedReq miss latency
536system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60509.302326 # average ReadSharedReq miss latency
537system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60520.797227 # average overall miss latency
538system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60517.103570 # average overall miss latency
539system.cpu.l2cache.demand_avg_miss_latency::total 60517.242503 # average overall miss latency
540system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60520.797227 # average overall miss latency
541system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60517.103570 # average overall miss latency
542system.cpu.l2cache.overall_avg_miss_latency::total 60517.242503 # average overall miss latency

545system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
546system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
547system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
548system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
549system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
550system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
551system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses
552system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses
553system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 577 # number of ReadCleanReq MSHR misses
554system.cpu.l2cache.ReadCleanReq_mshr_misses::total 577 # number of ReadCleanReq MSHR misses
555system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 215 # number of ReadSharedReq MSHR misses
556system.cpu.l2cache.ReadSharedReq_mshr_misses::total 215 # number of ReadSharedReq MSHR misses
557system.cpu.l2cache.demand_mshr_misses::cpu.inst 577 # number of demand (read+write) MSHR misses
558system.cpu.l2cache.demand_mshr_misses::cpu.data 14763 # number of demand (read+write) MSHR misses
559system.cpu.l2cache.demand_mshr_misses::total 15340 # number of demand (read+write) MSHR misses
560system.cpu.l2cache.overall_mshr_misses::cpu.inst 577 # number of overall MSHR misses
561system.cpu.l2cache.overall_mshr_misses::cpu.data 14763 # number of overall MSHR misses
562system.cpu.l2cache.overall_mshr_misses::total 15340 # number of overall MSHR misses

543system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
544system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
545system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
546system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
547system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
548system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
549system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses
550system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses
551system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 577 # number of ReadCleanReq MSHR misses
552system.cpu.l2cache.ReadCleanReq_mshr_misses::total 577 # number of ReadCleanReq MSHR misses
553system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 215 # number of ReadSharedReq MSHR misses
554system.cpu.l2cache.ReadSharedReq_mshr_misses::total 215 # number of ReadSharedReq MSHR misses
555system.cpu.l2cache.demand_mshr_misses::cpu.inst 577 # number of demand (read+write) MSHR misses
556system.cpu.l2cache.demand_mshr_misses::cpu.data 14763 # number of demand (read+write) MSHR misses
557system.cpu.l2cache.demand_mshr_misses::total 15340 # number of demand (read+write) MSHR misses
558system.cpu.l2cache.overall_mshr_misses::cpu.inst 577 # number of overall MSHR misses
559system.cpu.l2cache.overall_mshr_misses::cpu.data 14763 # number of overall MSHR misses
560system.cpu.l2cache.overall_mshr_misses::total 15340 # number of overall MSHR misses

563system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 720376500 # number of ReadExReq MSHR miss cycles
564system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 720376500 # number of ReadExReq MSHR miss cycles
565system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 28573500 # number of ReadCleanReq MSHR miss cycles
566system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 28573500 # number of ReadCleanReq MSHR miss cycles
567system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10644500 # number of ReadSharedReq MSHR miss cycles
568system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10644500 # number of ReadSharedReq MSHR miss cycles
569system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28573500 # number of demand (read+write) MSHR miss cycles
570system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 731021000 # number of demand (read+write) MSHR miss cycles
571system.cpu.l2cache.demand_mshr_miss_latency::total 759594500 # number of demand (read+write) MSHR miss cycles
572system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28573500 # number of overall MSHR miss cycles
573system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 731021000 # number of overall MSHR miss cycles
574system.cpu.l2cache.overall_mshr_miss_latency::total 759594500 # number of overall MSHR miss cycles

561system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 734924500 # number of ReadExReq MSHR miss cycles
562system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 734924500 # number of ReadExReq MSHR miss cycles
563system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 29150500 # number of ReadCleanReq MSHR miss cycles
564system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 29150500 # number of ReadCleanReq MSHR miss cycles
565system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10859500 # number of ReadSharedReq MSHR miss cycles
566system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10859500 # number of ReadSharedReq MSHR miss cycles
567system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29150500 # number of demand (read+write) MSHR miss cycles
568system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 745784000 # number of demand (read+write) MSHR miss cycles
569system.cpu.l2cache.demand_mshr_miss_latency::total 774934500 # number of demand (read+write) MSHR miss cycles
570system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29150500 # number of overall MSHR miss cycles
571system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 745784000 # number of overall MSHR miss cycles
572system.cpu.l2cache.overall_mshr_miss_latency::total 774934500 # number of overall MSHR miss cycles

575system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses
576system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses
577system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for ReadCleanReq accesses
578system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.963272 # mshr miss rate for ReadCleanReq accesses
579system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000239 # mshr miss rate for ReadSharedReq accesses
580system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000239 # mshr miss rate for ReadSharedReq accesses
581system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for demand accesses
582system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for demand accesses
583system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 # mshr miss rate for demand accesses
584system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for overall accesses
585system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for overall accesses
586system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses

573system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses
574system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses
575system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for ReadCleanReq accesses
576system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.963272 # mshr miss rate for ReadCleanReq accesses
577system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000239 # mshr miss rate for ReadSharedReq accesses
578system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000239 # mshr miss rate for ReadSharedReq accesses
579system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for demand accesses
580system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for demand accesses
581system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 # mshr miss rate for demand accesses
582system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for overall accesses
583system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for overall accesses
584system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses

587system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49517.218862 # average ReadExReq mshr miss latency
588system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49517.218862 # average ReadExReq mshr miss latency
589system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49520.797227 # average ReadCleanReq mshr miss latency
590system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49520.797227 # average ReadCleanReq mshr miss latency
591system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49509.302326 # average ReadSharedReq mshr miss latency
592system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49509.302326 # average ReadSharedReq mshr miss latency
593system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency
594system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency
595system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency
596system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency
597system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency
598system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency

585system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50517.218862 # average ReadExReq mshr miss latency
586system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50517.218862 # average ReadExReq mshr miss latency
587system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50520.797227 # average ReadCleanReq mshr miss latency
588system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50520.797227 # average ReadCleanReq mshr miss latency
589system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50509.302326 # average ReadSharedReq mshr miss latency
590system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50509.302326 # average ReadSharedReq mshr miss latency
591system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50520.797227 # average overall mshr miss latency
592system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50517.103570 # average overall mshr miss latency
593system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50517.242503 # average overall mshr miss latency
594system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50520.797227 # average overall mshr miss latency
595system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50517.103570 # average overall mshr miss latency
596system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50517.242503 # average overall mshr miss latency

599system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter.
600system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data.
601system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
602system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
603system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
604system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

597system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter.
598system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data.
599system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
600system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
601system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
602system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

605system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states

603system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states

606system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution
607system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 # Transaction distribution
608system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution
609system.cpu.toL2Bus.trans_dist::CleanEvict 368 # Transaction distribution
610system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution
611system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution
612system.cpu.toL2Bus.trans_dist::ReadCleanReq 599 # Transaction distribution
613system.cpu.toL2Bus.trans_dist::ReadSharedReq 900189 # Transaction distribution

--- 17 unchanged lines hidden (view full) ---

631system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
632system.cpu.toL2Bus.snoop_fanout::total 947397 # Request fanout histogram
633system.cpu.toL2Bus.reqLayer0.occupancy 1887386500 # Layer occupancy (ticks)
634system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
635system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks)
636system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
637system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks)
638system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)

604system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution
605system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 # Transaction distribution
606system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution
607system.cpu.toL2Bus.trans_dist::CleanEvict 368 # Transaction distribution
608system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution
609system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution
610system.cpu.toL2Bus.trans_dist::ReadCleanReq 599 # Transaction distribution
611system.cpu.toL2Bus.trans_dist::ReadSharedReq 900189 # Transaction distribution

--- 17 unchanged lines hidden (view full) ---

629system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
630system.cpu.toL2Bus.snoop_fanout::total 947397 # Request fanout histogram
631system.cpu.toL2Bus.reqLayer0.occupancy 1887386500 # Layer occupancy (ticks)
632system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
633system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks)
634system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
635system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks)
636system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)

639system.membus.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states

637system.membus.snoop_filter.tot_requests 15340 # Total number of requests made to the snoop filter.
638system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
639system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
640system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
641system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
642system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
643system.membus.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states