Cross Reference: /gem5/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt

stats.txt (11515:c48c7cc5a522)	stats.txt (11530:6e143fd2cabf)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.147149 # Number of seconds simulated 4sim_ticks 147148719500 # Number of ticks simulated 5final_tick 147148719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.147149 # Number of seconds simulated 4sim_ticks 147148719500 # Number of ticks simulated 5final_tick 147148719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1356153 # Simulator instruction rate (inst/s) 8host_op_rate 1362892 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2203169070 # Simulator tick rate (ticks/s) 10host_mem_usage 444740 # Number of bytes of host memory used 11host_seconds 66.79 # Real time elapsed on the host	7host_inst_rate 1337875 # Simulator instruction rate (inst/s) 8host_op_rate 1344524 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2173475460 # Simulator tick rate (ticks/s) 10host_mem_usage 445404 # Number of bytes of host memory used 11host_seconds 67.70 # Real time elapsed on the host
12sim_insts 90576862 # Number of instructions simulated 13sim_ops 91026991 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks	12sim_insts 90576862 # Number of instructions simulated 13sim_ops 91026991 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks
	16system.physmem.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
16system.physmem.bytes_read::cpu.inst 36928 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 944832 # Number of bytes read from this memory 18system.physmem.bytes_read::total 981760 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 36928 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 36928 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 577 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 14763 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 250957 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 6420933 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 6671890 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 250957 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 250957 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 250957 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 6420933 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 6671890 # Total bandwidth to/from this memory (bytes/s)	17system.physmem.bytes_read::cpu.inst 36928 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 944832 # Number of bytes read from this memory 19system.physmem.bytes_read::total 981760 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 36928 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 36928 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 577 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 14763 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 250957 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 6420933 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 6671890 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 250957 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 250957 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 250957 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 6420933 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 6671890 # Total bandwidth to/from this memory (bytes/s)
	33system.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
32system.cpu_clk_domain.clock 500 # Clock period in ticks	34system.cpu_clk_domain.clock 500 # Clock period in ticks
	35system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
33system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 34system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 36system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 54system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 55system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 56system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 57system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 58system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 59system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 60system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 61system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses	36system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 57system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 58system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 59system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 60system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 61system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 62system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 63system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 64system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
	65system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
62system.cpu.dtb.walker.walks 0 # Table walker walks requested 63system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 64system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 65system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 66system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 67system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 68system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 69system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 83system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 84system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 85system.cpu.dtb.read_accesses 0 # DTB read accesses 86system.cpu.dtb.write_accesses 0 # DTB write accesses 87system.cpu.dtb.inst_accesses 0 # ITB inst accesses 88system.cpu.dtb.hits 0 # DTB hits 89system.cpu.dtb.misses 0 # DTB misses 90system.cpu.dtb.accesses 0 # DTB accesses	66system.cpu.dtb.walker.walks 0 # Table walker walks requested 67system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 68system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 69system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 70system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 71system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 72system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 73system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 87system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 88system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 89system.cpu.dtb.read_accesses 0 # DTB read accesses 90system.cpu.dtb.write_accesses 0 # DTB write accesses 91system.cpu.dtb.inst_accesses 0 # ITB inst accesses 92system.cpu.dtb.hits 0 # DTB hits 93system.cpu.dtb.misses 0 # DTB misses 94system.cpu.dtb.accesses 0 # DTB accesses
	95system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
91system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 92system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 93system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 94system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 95system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 96system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 112system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 113system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 114system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 115system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 116system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 117system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 118system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 119system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses	96system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 117system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 118system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 119system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 120system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 121system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 122system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 123system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 124system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
	125system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
120system.cpu.itb.walker.walks 0 # Table walker walks requested 121system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 122system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 123system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 124system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 125system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 126system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 127system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 142system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 143system.cpu.itb.read_accesses 0 # DTB read accesses 144system.cpu.itb.write_accesses 0 # DTB write accesses 145system.cpu.itb.inst_accesses 0 # ITB inst accesses 146system.cpu.itb.hits 0 # DTB hits 147system.cpu.itb.misses 0 # DTB misses 148system.cpu.itb.accesses 0 # DTB accesses 149system.cpu.workload.num_syscalls 442 # Number of system calls	126system.cpu.itb.walker.walks 0 # Table walker walks requested 127system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 128system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 129system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 130system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 131system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 132system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 133system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 148system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 149system.cpu.itb.read_accesses 0 # DTB read accesses 150system.cpu.itb.write_accesses 0 # DTB write accesses 151system.cpu.itb.inst_accesses 0 # ITB inst accesses 152system.cpu.itb.hits 0 # DTB hits 153system.cpu.itb.misses 0 # DTB misses 154system.cpu.itb.accesses 0 # DTB accesses 155system.cpu.workload.num_syscalls 442 # Number of system calls
	156system.cpu.pwrStateResidencyTicks::ON 147148719500 # Cumulative time (in ticks) in various power states
150system.cpu.numCycles 294297439 # number of cpu cycles simulated 151system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 152system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 153system.cpu.committedInsts 90576862 # Number of instructions committed 154system.cpu.committedOps 91026991 # Number of ops (including micro ops) committed 155system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses 156system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses 157system.cpu.num_func_calls 112245 # number of times a function call or return occured --- 44 unchanged lines hidden (view full) --- 202system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction 203system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction 204system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction 205system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction 206system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction 207system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 208system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 209system.cpu.op_class::total 91054081 # Class of executed instruction	157system.cpu.numCycles 294297439 # number of cpu cycles simulated 158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 160system.cpu.committedInsts 90576862 # Number of instructions committed 161system.cpu.committedOps 91026991 # Number of ops (including micro ops) committed 162system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses 163system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses 164system.cpu.num_func_calls 112245 # number of times a function call or return occured --- 44 unchanged lines hidden (view full) --- 209system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction 210system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction 211system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction 212system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction 213system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction 214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 216system.cpu.op_class::total 91054081 # Class of executed instruction
	217system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
210system.cpu.dcache.tags.replacements 942702 # number of replacements 211system.cpu.dcache.tags.tagsinuse 3565.478025 # Cycle average of tags in use 212system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. 213system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. 214system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. 215system.cpu.dcache.tags.warmup_cycle 54453325500 # Cycle when the warmup percentage was hit. 216system.cpu.dcache.tags.occ_blocks::cpu.data 3565.478025 # Average occupied blocks per requestor 217system.cpu.dcache.tags.occ_percent::cpu.data 0.870478 # Average percentage of cache occupancy 218system.cpu.dcache.tags.occ_percent::total 0.870478 # Average percentage of cache occupancy 219system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 220system.cpu.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id 221system.cpu.dcache.tags.age_task_id_blocks_1024::1 1357 # Occupied blocks per task id 222system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id 223system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id 224system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 225system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses 226system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses	218system.cpu.dcache.tags.replacements 942702 # number of replacements 219system.cpu.dcache.tags.tagsinuse 3565.478025 # Cycle average of tags in use 220system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. 221system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. 222system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. 223system.cpu.dcache.tags.warmup_cycle 54453325500 # Cycle when the warmup percentage was hit. 224system.cpu.dcache.tags.occ_blocks::cpu.data 3565.478025 # Average occupied blocks per requestor 225system.cpu.dcache.tags.occ_percent::cpu.data 0.870478 # Average percentage of cache occupancy 226system.cpu.dcache.tags.occ_percent::total 0.870478 # Average percentage of cache occupancy 227system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 228system.cpu.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id 229system.cpu.dcache.tags.age_task_id_blocks_1024::1 1357 # Occupied blocks per task id 230system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id 231system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id 232system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 233system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses 234system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses
	235system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
227system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits 228system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits 229system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits 230system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits 231system.cpu.dcache.SoftPFReq_hits::cpu.data 507 # number of SoftPFReq hits 232system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits 233system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits 234system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits --- 102 unchanged lines hidden (view full) --- 337system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27299.673883 # average WriteReq mshr miss latency 338system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27299.673883 # average WriteReq mshr miss latency 339system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44666.666667 # average SoftPFReq mshr miss latency 340system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44666.666667 # average SoftPFReq mshr miss latency 341system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12764.311704 # average overall mshr miss latency 342system.cpu.dcache.demand_avg_mshr_miss_latency::total 12764.311704 # average overall mshr miss latency 343system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12764.412789 # average overall mshr miss latency 344system.cpu.dcache.overall_avg_mshr_miss_latency::total 12764.412789 # average overall mshr miss latency	236system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits 237system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits 238system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits 239system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits 240system.cpu.dcache.SoftPFReq_hits::cpu.data 507 # number of SoftPFReq hits 241system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits 242system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits 243system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits --- 102 unchanged lines hidden (view full) --- 346system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27299.673883 # average WriteReq mshr miss latency 347system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27299.673883 # average WriteReq mshr miss latency 348system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44666.666667 # average SoftPFReq mshr miss latency 349system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44666.666667 # average SoftPFReq mshr miss latency 350system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12764.311704 # average overall mshr miss latency 351system.cpu.dcache.demand_avg_mshr_miss_latency::total 12764.311704 # average overall mshr miss latency 352system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12764.412789 # average overall mshr miss latency 353system.cpu.dcache.overall_avg_mshr_miss_latency::total 12764.412789 # average overall mshr miss latency
	354system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
345system.cpu.icache.tags.replacements 2 # number of replacements 346system.cpu.icache.tags.tagsinuse 510.111710 # Cycle average of tags in use 347system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks. 348system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. 349system.cpu.icache.tags.avg_refs 180016.983306 # Average number of references to valid blocks. 350system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 351system.cpu.icache.tags.occ_blocks::cpu.inst 510.111710 # Average occupied blocks per requestor 352system.cpu.icache.tags.occ_percent::cpu.inst 0.249078 # Average percentage of cache occupancy 353system.cpu.icache.tags.occ_percent::total 0.249078 # Average percentage of cache occupancy 354system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id 355system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id 356system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 357system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 358system.cpu.icache.tags.age_task_id_blocks_1024::4 552 # Occupied blocks per task id 359system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id 360system.cpu.icache.tags.tag_accesses 215662143 # Number of tag accesses 361system.cpu.icache.tags.data_accesses 215662143 # Number of data accesses	355system.cpu.icache.tags.replacements 2 # number of replacements 356system.cpu.icache.tags.tagsinuse 510.111710 # Cycle average of tags in use 357system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks. 358system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. 359system.cpu.icache.tags.avg_refs 180016.983306 # Average number of references to valid blocks. 360system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 361system.cpu.icache.tags.occ_blocks::cpu.inst 510.111710 # Average occupied blocks per requestor 362system.cpu.icache.tags.occ_percent::cpu.inst 0.249078 # Average percentage of cache occupancy 363system.cpu.icache.tags.occ_percent::total 0.249078 # Average percentage of cache occupancy 364system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id 365system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id 366system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 367system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 368system.cpu.icache.tags.age_task_id_blocks_1024::4 552 # Occupied blocks per task id 369system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id 370system.cpu.icache.tags.tag_accesses 215662143 # Number of tag accesses 371system.cpu.icache.tags.data_accesses 215662143 # Number of data accesses
	372system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
362system.cpu.icache.ReadReq_hits::cpu.inst 107830173 # number of ReadReq hits 363system.cpu.icache.ReadReq_hits::total 107830173 # number of ReadReq hits 364system.cpu.icache.demand_hits::cpu.inst 107830173 # number of demand (read+write) hits 365system.cpu.icache.demand_hits::total 107830173 # number of demand (read+write) hits 366system.cpu.icache.overall_hits::cpu.inst 107830173 # number of overall hits 367system.cpu.icache.overall_hits::total 107830173 # number of overall hits 368system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses 369system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 422system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses 423system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses 424system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59255.425710 # average ReadReq mshr miss latency 425system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59255.425710 # average ReadReq mshr miss latency 426system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency 427system.cpu.icache.demand_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency 428system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency 429system.cpu.icache.overall_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency	373system.cpu.icache.ReadReq_hits::cpu.inst 107830173 # number of ReadReq hits 374system.cpu.icache.ReadReq_hits::total 107830173 # number of ReadReq hits 375system.cpu.icache.demand_hits::cpu.inst 107830173 # number of demand (read+write) hits 376system.cpu.icache.demand_hits::total 107830173 # number of demand (read+write) hits 377system.cpu.icache.overall_hits::cpu.inst 107830173 # number of overall hits 378system.cpu.icache.overall_hits::total 107830173 # number of overall hits 379system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses 380system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 433system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses 434system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses 435system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59255.425710 # average ReadReq mshr miss latency 436system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59255.425710 # average ReadReq mshr miss latency 437system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency 438system.cpu.icache.demand_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency 439system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency 440system.cpu.icache.overall_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency
	441system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
430system.cpu.l2cache.tags.replacements 0 # number of replacements 431system.cpu.l2cache.tags.tagsinuse 9564.658425 # Cycle average of tags in use 432system.cpu.l2cache.tags.total_refs 1827433 # Total number of references to valid blocks. 433system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. 434system.cpu.l2cache.tags.avg_refs 119.260784 # Average number of references to valid blocks. 435system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 436system.cpu.l2cache.tags.occ_blocks::writebacks 8876.269803 # Average occupied blocks per requestor 437system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.164592 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 444system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 445system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id 446system.cpu.l2cache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id 447system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1473 # Occupied blocks per task id 448system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13704 # Occupied blocks per task id 449system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id 450system.cpu.l2cache.tags.tag_accesses 15181828 # Number of tag accesses 451system.cpu.l2cache.tags.data_accesses 15181828 # Number of data accesses	442system.cpu.l2cache.tags.replacements 0 # number of replacements 443system.cpu.l2cache.tags.tagsinuse 9564.658425 # Cycle average of tags in use 444system.cpu.l2cache.tags.total_refs 1827433 # Total number of references to valid blocks. 445system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. 446system.cpu.l2cache.tags.avg_refs 119.260784 # Average number of references to valid blocks. 447system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 448system.cpu.l2cache.tags.occ_blocks::writebacks 8876.269803 # Average occupied blocks per requestor 449system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.164592 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 456system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 457system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id 458system.cpu.l2cache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id 459system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1473 # Occupied blocks per task id 460system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13704 # Occupied blocks per task id 461system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id 462system.cpu.l2cache.tags.tag_accesses 15181828 # Number of tag accesses 463system.cpu.l2cache.tags.data_accesses 15181828 # Number of data accesses
	464system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
452system.cpu.l2cache.WritebackDirty_hits::writebacks 942334 # number of WritebackDirty hits 453system.cpu.l2cache.WritebackDirty_hits::total 942334 # number of WritebackDirty hits 454system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits 455system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits 456system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits 457system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits 458system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits 459system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits --- 124 unchanged lines hidden (view full) --- 584system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency 585system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency 586system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter. 587system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data. 588system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 589system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 590system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 591system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.	465system.cpu.l2cache.WritebackDirty_hits::writebacks 942334 # number of WritebackDirty hits 466system.cpu.l2cache.WritebackDirty_hits::total 942334 # number of WritebackDirty hits 467system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits 468system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits 469system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits 470system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits 471system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits 472system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits --- 124 unchanged lines hidden (view full) --- 597system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency 598system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency 599system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter. 600system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data. 601system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 602system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 603system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 604system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
	605system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
592system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution 593system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 # Transaction distribution 594system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution 595system.cpu.toL2Bus.trans_dist::CleanEvict 368 # Transaction distribution 596system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution 597system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution 598system.cpu.toL2Bus.trans_dist::ReadCleanReq 599 # Transaction distribution 599system.cpu.toL2Bus.trans_dist::ReadSharedReq 900189 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 616system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 617system.cpu.toL2Bus.snoop_fanout::total 947397 # Request fanout histogram 618system.cpu.toL2Bus.reqLayer0.occupancy 1887386500 # Layer occupancy (ticks) 619system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 620system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks) 621system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 622system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks) 623system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)	606system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution 607system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 # Transaction distribution 608system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution 609system.cpu.toL2Bus.trans_dist::CleanEvict 368 # Transaction distribution 610system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution 611system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution 612system.cpu.toL2Bus.trans_dist::ReadCleanReq 599 # Transaction distribution 613system.cpu.toL2Bus.trans_dist::ReadSharedReq 900189 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 630system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 631system.cpu.toL2Bus.snoop_fanout::total 947397 # Request fanout histogram 632system.cpu.toL2Bus.reqLayer0.occupancy 1887386500 # Layer occupancy (ticks) 633system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 634system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks) 635system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 636system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks) 637system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
	638system.membus.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
624system.membus.trans_dist::ReadResp 792 # Transaction distribution 625system.membus.trans_dist::ReadExReq 14548 # Transaction distribution 626system.membus.trans_dist::ReadExResp 14548 # Transaction distribution 627system.membus.trans_dist::ReadSharedReq 792 # Transaction distribution 628system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes) 629system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes) 630system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes) 631system.membus.pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden ---	639system.membus.trans_dist::ReadResp 792 # Transaction distribution 640system.membus.trans_dist::ReadExReq 14548 # Transaction distribution 641system.membus.trans_dist::ReadExResp 14548 # Transaction distribution 642system.membus.trans_dist::ReadSharedReq 792 # Transaction distribution 643system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes) 644system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes) 645system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes) 646system.membus.pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden ---

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.147149 # Number of seconds simulated
4sim_ticks 147148719500 # Number of ticks simulated
5final_tick 147148719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 1356153 # Simulator instruction rate (inst/s)
8host_op_rate 1362892 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2203169070 # Simulator tick rate (ticks/s)
10host_mem_usage 444740 # Number of bytes of host memory used
11host_seconds 66.79 # Real time elapsed on the host

7host_inst_rate 1337875 # Simulator instruction rate (inst/s)
8host_op_rate 1344524 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2173475460 # Simulator tick rate (ticks/s)
10host_mem_usage 445404 # Number of bytes of host memory used
11host_seconds 67.70 # Real time elapsed on the host

12sim_insts 90576862 # Number of instructions simulated
13sim_ops 91026991 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states

16system.physmem.bytes_read::cpu.inst 36928 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 944832 # Number of bytes read from this memory
18system.physmem.bytes_read::total 981760 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 36928 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 36928 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 577 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 14763 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 250957 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 6420933 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 6671890 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 250957 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 250957 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 250957 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 6420933 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 6671890 # Total bandwidth to/from this memory (bytes/s)

17system.physmem.bytes_read::cpu.inst 36928 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 944832 # Number of bytes read from this memory
19system.physmem.bytes_read::total 981760 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 36928 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 36928 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 577 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 14763 # Number of read requests responded to by this memory
24system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory
25system.physmem.bw_read::cpu.inst 250957 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::cpu.data 6420933 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 6671890 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 250957 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 250957 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_total::cpu.inst 250957 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::cpu.data 6420933 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bw_total::total 6671890 # Total bandwidth to/from this memory (bytes/s)

33system.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states

32system.cpu_clk_domain.clock 500 # Clock period in ticks

34system.cpu_clk_domain.clock 500 # Clock period in ticks

35system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states

33system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
34system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
35system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
36system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

54system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
55system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
56system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
57system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
58system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
59system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
60system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
61system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

36system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

57system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
58system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
59system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
60system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
61system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
62system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
63system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
64system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

65system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states

62system.cpu.dtb.walker.walks 0 # Table walker walks requested
63system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
64system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
65system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
66system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
67system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
68system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
69system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

83system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
84system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
85system.cpu.dtb.read_accesses 0 # DTB read accesses
86system.cpu.dtb.write_accesses 0 # DTB write accesses
87system.cpu.dtb.inst_accesses 0 # ITB inst accesses
88system.cpu.dtb.hits 0 # DTB hits
89system.cpu.dtb.misses 0 # DTB misses
90system.cpu.dtb.accesses 0 # DTB accesses

66system.cpu.dtb.walker.walks 0 # Table walker walks requested
67system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
68system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
69system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
70system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
71system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
72system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
73system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

87system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
88system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
89system.cpu.dtb.read_accesses 0 # DTB read accesses
90system.cpu.dtb.write_accesses 0 # DTB write accesses
91system.cpu.dtb.inst_accesses 0 # ITB inst accesses
92system.cpu.dtb.hits 0 # DTB hits
93system.cpu.dtb.misses 0 # DTB misses
94system.cpu.dtb.accesses 0 # DTB accesses

95system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states

91system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
92system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
93system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
94system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
95system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
96system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

112system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
113system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
114system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
115system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
116system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
117system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
118system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
119system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

96system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

117system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
118system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
119system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
120system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
121system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
122system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
123system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
124system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

125system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states

120system.cpu.itb.walker.walks 0 # Table walker walks requested
121system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
122system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
123system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
124system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
125system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
126system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
127system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

142system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
143system.cpu.itb.read_accesses 0 # DTB read accesses
144system.cpu.itb.write_accesses 0 # DTB write accesses
145system.cpu.itb.inst_accesses 0 # ITB inst accesses
146system.cpu.itb.hits 0 # DTB hits
147system.cpu.itb.misses 0 # DTB misses
148system.cpu.itb.accesses 0 # DTB accesses
149system.cpu.workload.num_syscalls 442 # Number of system calls

126system.cpu.itb.walker.walks 0 # Table walker walks requested
127system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
128system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
129system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
130system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
131system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
132system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
133system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

148system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
149system.cpu.itb.read_accesses 0 # DTB read accesses
150system.cpu.itb.write_accesses 0 # DTB write accesses
151system.cpu.itb.inst_accesses 0 # ITB inst accesses
152system.cpu.itb.hits 0 # DTB hits
153system.cpu.itb.misses 0 # DTB misses
154system.cpu.itb.accesses 0 # DTB accesses
155system.cpu.workload.num_syscalls 442 # Number of system calls

156system.cpu.pwrStateResidencyTicks::ON 147148719500 # Cumulative time (in ticks) in various power states

150system.cpu.numCycles 294297439 # number of cpu cycles simulated
151system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
152system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
153system.cpu.committedInsts 90576862 # Number of instructions committed
154system.cpu.committedOps 91026991 # Number of ops (including micro ops) committed
155system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses
156system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
157system.cpu.num_func_calls 112245 # number of times a function call or return occured

--- 44 unchanged lines hidden (view full) ---

202system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction
203system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction
204system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction
205system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction
206system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction
207system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
208system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
209system.cpu.op_class::total 91054081 # Class of executed instruction

157system.cpu.numCycles 294297439 # number of cpu cycles simulated
158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
160system.cpu.committedInsts 90576862 # Number of instructions committed
161system.cpu.committedOps 91026991 # Number of ops (including micro ops) committed
162system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses
163system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
164system.cpu.num_func_calls 112245 # number of times a function call or return occured

--- 44 unchanged lines hidden (view full) ---

209system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction
210system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction
211system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction
212system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction
213system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction
214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
216system.cpu.op_class::total 91054081 # Class of executed instruction

217system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states

210system.cpu.dcache.tags.replacements 942702 # number of replacements
211system.cpu.dcache.tags.tagsinuse 3565.478025 # Cycle average of tags in use
212system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks.
213system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks.
214system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks.
215system.cpu.dcache.tags.warmup_cycle 54453325500 # Cycle when the warmup percentage was hit.
216system.cpu.dcache.tags.occ_blocks::cpu.data 3565.478025 # Average occupied blocks per requestor
217system.cpu.dcache.tags.occ_percent::cpu.data 0.870478 # Average percentage of cache occupancy
218system.cpu.dcache.tags.occ_percent::total 0.870478 # Average percentage of cache occupancy
219system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
220system.cpu.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
221system.cpu.dcache.tags.age_task_id_blocks_1024::1 1357 # Occupied blocks per task id
222system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id
223system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id
224system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
225system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses
226system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses

218system.cpu.dcache.tags.replacements 942702 # number of replacements
219system.cpu.dcache.tags.tagsinuse 3565.478025 # Cycle average of tags in use
220system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks.
221system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks.
222system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks.
223system.cpu.dcache.tags.warmup_cycle 54453325500 # Cycle when the warmup percentage was hit.
224system.cpu.dcache.tags.occ_blocks::cpu.data 3565.478025 # Average occupied blocks per requestor
225system.cpu.dcache.tags.occ_percent::cpu.data 0.870478 # Average percentage of cache occupancy
226system.cpu.dcache.tags.occ_percent::total 0.870478 # Average percentage of cache occupancy
227system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
228system.cpu.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
229system.cpu.dcache.tags.age_task_id_blocks_1024::1 1357 # Occupied blocks per task id
230system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id
231system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id
232system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
233system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses
234system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses

235system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states

227system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits
228system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits
229system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits
230system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits
231system.cpu.dcache.SoftPFReq_hits::cpu.data 507 # number of SoftPFReq hits
232system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits
233system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
234system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits

--- 102 unchanged lines hidden (view full) ---

337system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27299.673883 # average WriteReq mshr miss latency
338system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27299.673883 # average WriteReq mshr miss latency
339system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44666.666667 # average SoftPFReq mshr miss latency
340system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44666.666667 # average SoftPFReq mshr miss latency
341system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12764.311704 # average overall mshr miss latency
342system.cpu.dcache.demand_avg_mshr_miss_latency::total 12764.311704 # average overall mshr miss latency
343system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12764.412789 # average overall mshr miss latency
344system.cpu.dcache.overall_avg_mshr_miss_latency::total 12764.412789 # average overall mshr miss latency

236system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits
237system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits
238system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits
239system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits
240system.cpu.dcache.SoftPFReq_hits::cpu.data 507 # number of SoftPFReq hits
241system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits
242system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
243system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits

--- 102 unchanged lines hidden (view full) ---

346system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27299.673883 # average WriteReq mshr miss latency
347system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27299.673883 # average WriteReq mshr miss latency
348system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44666.666667 # average SoftPFReq mshr miss latency
349system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44666.666667 # average SoftPFReq mshr miss latency
350system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12764.311704 # average overall mshr miss latency
351system.cpu.dcache.demand_avg_mshr_miss_latency::total 12764.311704 # average overall mshr miss latency
352system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12764.412789 # average overall mshr miss latency
353system.cpu.dcache.overall_avg_mshr_miss_latency::total 12764.412789 # average overall mshr miss latency

354system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states

345system.cpu.icache.tags.replacements 2 # number of replacements
346system.cpu.icache.tags.tagsinuse 510.111710 # Cycle average of tags in use
347system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks.
348system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks.
349system.cpu.icache.tags.avg_refs 180016.983306 # Average number of references to valid blocks.
350system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
351system.cpu.icache.tags.occ_blocks::cpu.inst 510.111710 # Average occupied blocks per requestor
352system.cpu.icache.tags.occ_percent::cpu.inst 0.249078 # Average percentage of cache occupancy
353system.cpu.icache.tags.occ_percent::total 0.249078 # Average percentage of cache occupancy
354system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id
355system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
356system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
357system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
358system.cpu.icache.tags.age_task_id_blocks_1024::4 552 # Occupied blocks per task id
359system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id
360system.cpu.icache.tags.tag_accesses 215662143 # Number of tag accesses
361system.cpu.icache.tags.data_accesses 215662143 # Number of data accesses

355system.cpu.icache.tags.replacements 2 # number of replacements
356system.cpu.icache.tags.tagsinuse 510.111710 # Cycle average of tags in use
357system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks.
358system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks.
359system.cpu.icache.tags.avg_refs 180016.983306 # Average number of references to valid blocks.
360system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
361system.cpu.icache.tags.occ_blocks::cpu.inst 510.111710 # Average occupied blocks per requestor
362system.cpu.icache.tags.occ_percent::cpu.inst 0.249078 # Average percentage of cache occupancy
363system.cpu.icache.tags.occ_percent::total 0.249078 # Average percentage of cache occupancy
364system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id
365system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
366system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
367system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
368system.cpu.icache.tags.age_task_id_blocks_1024::4 552 # Occupied blocks per task id
369system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id
370system.cpu.icache.tags.tag_accesses 215662143 # Number of tag accesses
371system.cpu.icache.tags.data_accesses 215662143 # Number of data accesses

372system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states

362system.cpu.icache.ReadReq_hits::cpu.inst 107830173 # number of ReadReq hits
363system.cpu.icache.ReadReq_hits::total 107830173 # number of ReadReq hits
364system.cpu.icache.demand_hits::cpu.inst 107830173 # number of demand (read+write) hits
365system.cpu.icache.demand_hits::total 107830173 # number of demand (read+write) hits
366system.cpu.icache.overall_hits::cpu.inst 107830173 # number of overall hits
367system.cpu.icache.overall_hits::total 107830173 # number of overall hits
368system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses
369system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses

--- 52 unchanged lines hidden (view full) ---

422system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses
423system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses
424system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59255.425710 # average ReadReq mshr miss latency
425system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59255.425710 # average ReadReq mshr miss latency
426system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency
427system.cpu.icache.demand_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency
428system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency
429system.cpu.icache.overall_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency

373system.cpu.icache.ReadReq_hits::cpu.inst 107830173 # number of ReadReq hits
374system.cpu.icache.ReadReq_hits::total 107830173 # number of ReadReq hits
375system.cpu.icache.demand_hits::cpu.inst 107830173 # number of demand (read+write) hits
376system.cpu.icache.demand_hits::total 107830173 # number of demand (read+write) hits
377system.cpu.icache.overall_hits::cpu.inst 107830173 # number of overall hits
378system.cpu.icache.overall_hits::total 107830173 # number of overall hits
379system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses
380system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses

--- 52 unchanged lines hidden (view full) ---

433system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses
434system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses
435system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59255.425710 # average ReadReq mshr miss latency
436system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59255.425710 # average ReadReq mshr miss latency
437system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency
438system.cpu.icache.demand_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency
439system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency
440system.cpu.icache.overall_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency

441system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states

430system.cpu.l2cache.tags.replacements 0 # number of replacements
431system.cpu.l2cache.tags.tagsinuse 9564.658425 # Cycle average of tags in use
432system.cpu.l2cache.tags.total_refs 1827433 # Total number of references to valid blocks.
433system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks.
434system.cpu.l2cache.tags.avg_refs 119.260784 # Average number of references to valid blocks.
435system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
436system.cpu.l2cache.tags.occ_blocks::writebacks 8876.269803 # Average occupied blocks per requestor
437system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.164592 # Average occupied blocks per requestor

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444system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
445system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
446system.cpu.l2cache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id
447system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1473 # Occupied blocks per task id
448system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13704 # Occupied blocks per task id
449system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id
450system.cpu.l2cache.tags.tag_accesses 15181828 # Number of tag accesses
451system.cpu.l2cache.tags.data_accesses 15181828 # Number of data accesses

442system.cpu.l2cache.tags.replacements 0 # number of replacements
443system.cpu.l2cache.tags.tagsinuse 9564.658425 # Cycle average of tags in use
444system.cpu.l2cache.tags.total_refs 1827433 # Total number of references to valid blocks.
445system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks.
446system.cpu.l2cache.tags.avg_refs 119.260784 # Average number of references to valid blocks.
447system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
448system.cpu.l2cache.tags.occ_blocks::writebacks 8876.269803 # Average occupied blocks per requestor
449system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.164592 # Average occupied blocks per requestor

--- 6 unchanged lines hidden (view full) ---

456system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
457system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
458system.cpu.l2cache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id
459system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1473 # Occupied blocks per task id
460system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13704 # Occupied blocks per task id
461system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id
462system.cpu.l2cache.tags.tag_accesses 15181828 # Number of tag accesses
463system.cpu.l2cache.tags.data_accesses 15181828 # Number of data accesses

464system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states

452system.cpu.l2cache.WritebackDirty_hits::writebacks 942334 # number of WritebackDirty hits
453system.cpu.l2cache.WritebackDirty_hits::total 942334 # number of WritebackDirty hits
454system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits
455system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits
456system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits
457system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits
458system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits
459system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits

--- 124 unchanged lines hidden (view full) ---

584system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency
585system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency
586system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter.
587system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data.
588system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
589system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
590system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
591system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

465system.cpu.l2cache.WritebackDirty_hits::writebacks 942334 # number of WritebackDirty hits
466system.cpu.l2cache.WritebackDirty_hits::total 942334 # number of WritebackDirty hits
467system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits
468system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits
469system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits
470system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits
471system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits
472system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits

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597system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency
598system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency
599system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter.
600system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data.
601system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
602system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
603system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
604system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

605system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states

592system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution
593system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 # Transaction distribution
594system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution
595system.cpu.toL2Bus.trans_dist::CleanEvict 368 # Transaction distribution
596system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution
597system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution
598system.cpu.toL2Bus.trans_dist::ReadCleanReq 599 # Transaction distribution
599system.cpu.toL2Bus.trans_dist::ReadSharedReq 900189 # Transaction distribution

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616system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
617system.cpu.toL2Bus.snoop_fanout::total 947397 # Request fanout histogram
618system.cpu.toL2Bus.reqLayer0.occupancy 1887386500 # Layer occupancy (ticks)
619system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
620system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks)
621system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
622system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks)
623system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)

606system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution
607system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 # Transaction distribution
608system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution
609system.cpu.toL2Bus.trans_dist::CleanEvict 368 # Transaction distribution
610system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution
611system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution
612system.cpu.toL2Bus.trans_dist::ReadCleanReq 599 # Transaction distribution
613system.cpu.toL2Bus.trans_dist::ReadSharedReq 900189 # Transaction distribution

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630system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
631system.cpu.toL2Bus.snoop_fanout::total 947397 # Request fanout histogram
632system.cpu.toL2Bus.reqLayer0.occupancy 1887386500 # Layer occupancy (ticks)
633system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
634system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks)
635system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
636system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks)
637system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)

638system.membus.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states