| stats.txt (11336:b318499f676c) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.147149 # Number of seconds simulated 4sim_ticks 147148719500 # Number of ticks simulated 5final_tick 147148719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.147149 # Number of seconds simulated 4sim_ticks 147148719500 # Number of ticks simulated 5final_tick 147148719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1174056 # Simulator instruction rate (inst/s) 8host_op_rate 1179890 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1907338487 # Simulator tick rate (ticks/s) 10host_mem_usage 402756 # Number of bytes of host memory used 11host_seconds 77.15 # Real time elapsed on the host | 7host_inst_rate 1067474 # Simulator instruction rate (inst/s) 8host_op_rate 1072778 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1734188097 # Simulator tick rate (ticks/s) 10host_mem_usage 402040 # Number of bytes of host memory used 11host_seconds 84.85 # Real time elapsed on the host |
| 12sim_insts 90576862 # Number of instructions simulated 13sim_ops 91026991 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 36928 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 944832 # Number of bytes read from this memory 18system.physmem.bytes_read::total 981760 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 36928 # Number of instructions bytes read from this memory --- 269 unchanged lines hidden (view full) --- 289system.cpu.dcache.overall_avg_miss_latency::cpu.data 13764.303194 # average overall miss latency 290system.cpu.dcache.overall_avg_miss_latency::total 13764.303194 # average overall miss latency 291system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 292system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 293system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 294system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 295system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 296system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 90576862 # Number of instructions simulated 13sim_ops 91026991 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 36928 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 944832 # Number of bytes read from this memory 18system.physmem.bytes_read::total 981760 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 36928 # Number of instructions bytes read from this memory --- 269 unchanged lines hidden (view full) --- 289system.cpu.dcache.overall_avg_miss_latency::cpu.data 13764.303194 # average overall miss latency 290system.cpu.dcache.overall_avg_miss_latency::total 13764.303194 # average overall miss latency 291system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 292system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 293system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 294system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 295system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 296system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 297system.cpu.dcache.fast_writes 0 # number of fast writes performed 298system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 299system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks 300system.cpu.dcache.writebacks::total 942334 # number of writebacks 301system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 302system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 303system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 304system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 305system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 306system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits --- 32 unchanged lines hidden (view full) --- 339system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27299.673883 # average WriteReq mshr miss latency 340system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27299.673883 # average WriteReq mshr miss latency 341system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44666.666667 # average SoftPFReq mshr miss latency 342system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44666.666667 # average SoftPFReq mshr miss latency 343system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12764.311704 # average overall mshr miss latency 344system.cpu.dcache.demand_avg_mshr_miss_latency::total 12764.311704 # average overall mshr miss latency 345system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12764.412789 # average overall mshr miss latency 346system.cpu.dcache.overall_avg_mshr_miss_latency::total 12764.412789 # average overall mshr miss latency | 297system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks 298system.cpu.dcache.writebacks::total 942334 # number of writebacks 299system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 300system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 301system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 302system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 303system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 304system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits --- 32 unchanged lines hidden (view full) --- 337system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27299.673883 # average WriteReq mshr miss latency 338system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27299.673883 # average WriteReq mshr miss latency 339system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44666.666667 # average SoftPFReq mshr miss latency 340system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44666.666667 # average SoftPFReq mshr miss latency 341system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12764.311704 # average overall mshr miss latency 342system.cpu.dcache.demand_avg_mshr_miss_latency::total 12764.311704 # average overall mshr miss latency 343system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12764.412789 # average overall mshr miss latency 344system.cpu.dcache.overall_avg_mshr_miss_latency::total 12764.412789 # average overall mshr miss latency |
| 347system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 348system.cpu.icache.tags.replacements 2 # number of replacements 349system.cpu.icache.tags.tagsinuse 510.111710 # Cycle average of tags in use 350system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks. 351system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. 352system.cpu.icache.tags.avg_refs 180016.983306 # Average number of references to valid blocks. 353system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 354system.cpu.icache.tags.occ_blocks::cpu.inst 510.111710 # Average occupied blocks per requestor 355system.cpu.icache.tags.occ_percent::cpu.inst 0.249078 # Average percentage of cache occupancy --- 43 unchanged lines hidden (view full) --- 399system.cpu.icache.overall_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency 400system.cpu.icache.overall_avg_miss_latency::total 60255.425710 # average overall miss latency 401system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 402system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 403system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 404system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 405system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 406system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 345system.cpu.icache.tags.replacements 2 # number of replacements 346system.cpu.icache.tags.tagsinuse 510.111710 # Cycle average of tags in use 347system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks. 348system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. 349system.cpu.icache.tags.avg_refs 180016.983306 # Average number of references to valid blocks. 350system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 351system.cpu.icache.tags.occ_blocks::cpu.inst 510.111710 # Average occupied blocks per requestor 352system.cpu.icache.tags.occ_percent::cpu.inst 0.249078 # Average percentage of cache occupancy --- 43 unchanged lines hidden (view full) --- 396system.cpu.icache.overall_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency 397system.cpu.icache.overall_avg_miss_latency::total 60255.425710 # average overall miss latency 398system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 399system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 400system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 401system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 402system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 403system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 407system.cpu.icache.fast_writes 0 # number of fast writes performed 408system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 409system.cpu.icache.writebacks::writebacks 2 # number of writebacks 410system.cpu.icache.writebacks::total 2 # number of writebacks 411system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses 412system.cpu.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses 413system.cpu.icache.demand_mshr_misses::cpu.inst 599 # number of demand (read+write) MSHR misses 414system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses 415system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses 416system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 427system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses 428system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses 429system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59255.425710 # average ReadReq mshr miss latency 430system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59255.425710 # average ReadReq mshr miss latency 431system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency 432system.cpu.icache.demand_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency 433system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency 434system.cpu.icache.overall_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency | 404system.cpu.icache.writebacks::writebacks 2 # number of writebacks 405system.cpu.icache.writebacks::total 2 # number of writebacks 406system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses 407system.cpu.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses 408system.cpu.icache.demand_mshr_misses::cpu.inst 599 # number of demand (read+write) MSHR misses 409system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses 410system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses 411system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 422system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses 423system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses 424system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59255.425710 # average ReadReq mshr miss latency 425system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59255.425710 # average ReadReq mshr miss latency 426system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency 427system.cpu.icache.demand_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency 428system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency 429system.cpu.icache.overall_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency |
| 435system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 436system.cpu.l2cache.tags.replacements 0 # number of replacements 437system.cpu.l2cache.tags.tagsinuse 9564.658425 # Cycle average of tags in use 438system.cpu.l2cache.tags.total_refs 1827433 # Total number of references to valid blocks. 439system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. 440system.cpu.l2cache.tags.avg_refs 119.260784 # Average number of references to valid blocks. 441system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 442system.cpu.l2cache.tags.occ_blocks::writebacks 8876.269803 # Average occupied blocks per requestor 443system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.164592 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 536system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency 537system.cpu.l2cache.overall_avg_miss_latency::total 59517.242503 # average overall miss latency 538system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 539system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 540system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 541system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 542system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 543system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 430system.cpu.l2cache.tags.replacements 0 # number of replacements 431system.cpu.l2cache.tags.tagsinuse 9564.658425 # Cycle average of tags in use 432system.cpu.l2cache.tags.total_refs 1827433 # Total number of references to valid blocks. 433system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. 434system.cpu.l2cache.tags.avg_refs 119.260784 # Average number of references to valid blocks. 435system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 436system.cpu.l2cache.tags.occ_blocks::writebacks 8876.269803 # Average occupied blocks per requestor 437system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.164592 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 530system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency 531system.cpu.l2cache.overall_avg_miss_latency::total 59517.242503 # average overall miss latency 532system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 533system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 534system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 535system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 536system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 537system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 544system.cpu.l2cache.fast_writes 0 # number of fast writes performed 545system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 546system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses 547system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses 548system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 577 # number of ReadCleanReq MSHR misses 549system.cpu.l2cache.ReadCleanReq_mshr_misses::total 577 # number of ReadCleanReq MSHR misses 550system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 215 # number of ReadSharedReq MSHR misses 551system.cpu.l2cache.ReadSharedReq_mshr_misses::total 215 # number of ReadSharedReq MSHR misses 552system.cpu.l2cache.demand_mshr_misses::cpu.inst 577 # number of demand (read+write) MSHR misses 553system.cpu.l2cache.demand_mshr_misses::cpu.data 14763 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 586system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49509.302326 # average ReadSharedReq mshr miss latency 587system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49509.302326 # average ReadSharedReq mshr miss latency 588system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency 589system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency 590system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency 591system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency 592system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency 593system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency | 538system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses 539system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses 540system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 577 # number of ReadCleanReq MSHR misses 541system.cpu.l2cache.ReadCleanReq_mshr_misses::total 577 # number of ReadCleanReq MSHR misses 542system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 215 # number of ReadSharedReq MSHR misses 543system.cpu.l2cache.ReadSharedReq_mshr_misses::total 215 # number of ReadSharedReq MSHR misses 544system.cpu.l2cache.demand_mshr_misses::cpu.inst 577 # number of demand (read+write) MSHR misses 545system.cpu.l2cache.demand_mshr_misses::cpu.data 14763 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 578system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49509.302326 # average ReadSharedReq mshr miss latency 579system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49509.302326 # average ReadSharedReq mshr miss latency 580system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency 581system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency 582system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency 583system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency 584system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency 585system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency |
| 594system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 595system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter. 596system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data. 597system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 598system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 599system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 600system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 601system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution 602system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 # Transaction distribution --- 55 unchanged lines hidden --- | 586system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter. 587system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data. 588system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 589system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 590system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 591system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 592system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution 593system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 # Transaction distribution --- 55 unchanged lines hidden --- |