Cross Reference: /gem5/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.147041 # Number of seconds simulated

4sim_ticks 147041221500 # Number of ticks simulated
5final_tick 147041221500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

4sim_ticks 147041346500 # Number of ticks simulated
5final_tick 147041346500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 1077194 # Simulator instruction rate (inst/s)
8host_op_rate 1082547 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1748701394 # Simulator tick rate (ticks/s)
10host_mem_usage 444972 # Number of bytes of host memory used
11host_seconds 84.09 # Real time elapsed on the host

7host_inst_rate 870528 # Simulator instruction rate (inst/s)
8host_op_rate 874854 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1413203999 # Simulator tick rate (ticks/s)
10host_mem_usage 449664 # Number of bytes of host memory used
11host_seconds 104.05 # Real time elapsed on the host

12sim_insts 90576862 # Number of instructions simulated
13sim_ops 91026991 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 36928 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 944832 # Number of bytes read from this memory
18system.physmem.bytes_read::total 981760 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 36928 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 36928 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 577 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 14763 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 251140 # Total read bandwidth from this memory (bytes/s)

25system.physmem.bw_read::cpu.data 6425627 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 6676767 # Total read bandwidth from this memory (bytes/s)

25system.physmem.bw_read::cpu.data 6425621 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 6676761 # Total read bandwidth from this memory (bytes/s)

27system.physmem.bw_inst_read::cpu.inst 251140 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 251140 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 251140 # Total bandwidth to/from this memory (bytes/s)

30system.physmem.bw_total::cpu.data 6425627 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 6676767 # Total bandwidth to/from this memory (bytes/s)

30system.physmem.bw_total::cpu.data 6425621 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 6676761 # Total bandwidth to/from this memory (bytes/s)

32system.cpu_clk_domain.clock 500 # Clock period in ticks
33system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
34system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
35system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
36system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 102 unchanged lines hidden (view full) ---

142system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
143system.cpu.itb.read_accesses 0 # DTB read accesses
144system.cpu.itb.write_accesses 0 # DTB write accesses
145system.cpu.itb.inst_accesses 0 # ITB inst accesses
146system.cpu.itb.hits 0 # DTB hits
147system.cpu.itb.misses 0 # DTB misses
148system.cpu.itb.accesses 0 # DTB accesses
149system.cpu.workload.num_syscalls 442 # Number of system calls

150system.cpu.numCycles 294082443 # number of cpu cycles simulated

150system.cpu.numCycles 294082693 # number of cpu cycles simulated

151system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
152system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
153system.cpu.committedInsts 90576862 # Number of instructions committed
154system.cpu.committedOps 91026991 # Number of ops (including micro ops) committed
155system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses
156system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
157system.cpu.num_func_calls 112245 # number of times a function call or return occured
158system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls

--- 4 unchanged lines hidden (view full) ---

163system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
164system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
165system.cpu.num_cc_register_reads 339191621 # number of times the CC registers were read
166system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written
167system.cpu.num_mem_refs 27220755 # number of memory refs
168system.cpu.num_load_insts 22475911 # Number of load instructions
169system.cpu.num_store_insts 4744844 # Number of store instructions
170system.cpu.num_idle_cycles 0.002000 # Number of idle cycles

171system.cpu.num_busy_cycles 294082442.998000 # Number of busy cycles

171system.cpu.num_busy_cycles 294082692.998000 # Number of busy cycles

172system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
173system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
174system.cpu.Branches 18732305 # Number of branches fetched
175system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
176system.cpu.op_class::IntAlu 63822829 70.09% 70.09% # Class of executed instruction
177system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction
178system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction
179system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction

--- 23 unchanged lines hidden (view full) ---

203system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction
204system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction
205system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction
206system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction
207system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
208system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
209system.cpu.op_class::total 91054081 # Class of executed instruction
210system.cpu.dcache.tags.replacements 942702 # number of replacements

211system.cpu.dcache.tags.tagsinuse 3565.593910 # Cycle average of tags in use

211system.cpu.dcache.tags.tagsinuse 3565.593612 # Cycle average of tags in use

212system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks.
213system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks.
214system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks.

215system.cpu.dcache.tags.warmup_cycle 54410415500 # Cycle when the warmup percentage was hit.
216system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593910 # Average occupied blocks per requestor

215system.cpu.dcache.tags.warmup_cycle 54410450500 # Cycle when the warmup percentage was hit.
216system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593612 # Average occupied blocks per requestor

217system.cpu.dcache.tags.occ_percent::cpu.data 0.870506 # Average percentage of cache occupancy
218system.cpu.dcache.tags.occ_percent::total 0.870506 # Average percentage of cache occupancy
219system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
220system.cpu.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id
221system.cpu.dcache.tags.age_task_id_blocks_1024::1 1355 # Occupied blocks per task id
222system.cpu.dcache.tags.age_task_id_blocks_1024::2 2550 # Occupied blocks per task id
223system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id
224system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id

--- 18 unchanged lines hidden (view full) ---

243system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses
244system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses
245system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses
246system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses
247system.cpu.dcache.demand_misses::cpu.data 946796 # number of demand (read+write) misses
248system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses
249system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses
250system.cpu.dcache.overall_misses::total 946799 # number of overall misses

251system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711406000 # number of ReadReq miss cycles
252system.cpu.dcache.ReadReq_miss_latency::total 11711406000 # number of ReadReq miss cycles

251system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711511000 # number of ReadReq miss cycles
252system.cpu.dcache.ReadReq_miss_latency::total 11711511000 # number of ReadReq miss cycles

253system.cpu.dcache.WriteReq_miss_latency::cpu.data 1217183500 # number of WriteReq miss cycles
254system.cpu.dcache.WriteReq_miss_latency::total 1217183500 # number of WriteReq miss cycles

255system.cpu.dcache.demand_miss_latency::cpu.data 12928589500 # number of demand (read+write) miss cycles
256system.cpu.dcache.demand_miss_latency::total 12928589500 # number of demand (read+write) miss cycles
257system.cpu.dcache.overall_miss_latency::cpu.data 12928589500 # number of overall miss cycles
258system.cpu.dcache.overall_miss_latency::total 12928589500 # number of overall miss cycles

255system.cpu.dcache.demand_miss_latency::cpu.data 12928694500 # number of demand (read+write) miss cycles
256system.cpu.dcache.demand_miss_latency::total 12928694500 # number of demand (read+write) miss cycles
257system.cpu.dcache.overall_miss_latency::cpu.data 12928694500 # number of overall miss cycles
258system.cpu.dcache.overall_miss_latency::total 12928694500 # number of overall miss cycles

259system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses)
260system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses)
261system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
262system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
263system.cpu.dcache.SoftPFReq_accesses::cpu.data 510 # number of SoftPFReq accesses(hits+misses)
264system.cpu.dcache.SoftPFReq_accesses::total 510 # number of SoftPFReq accesses(hits+misses)
265system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
266system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)

--- 8 unchanged lines hidden (view full) ---

275system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses
276system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses
277system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005882 # miss rate for SoftPFReq accesses
278system.cpu.dcache.SoftPFReq_miss_rate::total 0.005882 # miss rate for SoftPFReq accesses
279system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 # miss rate for demand accesses
280system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses
281system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses
282system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses

283system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.970151 # average ReadReq miss latency
284system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.970151 # average ReadReq miss latency

283system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13010.086793 # average ReadReq miss latency
284system.cpu.dcache.ReadReq_avg_miss_latency::total 13010.086793 # average ReadReq miss latency

285system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26114.773971 # average WriteReq miss latency
286system.cpu.dcache.WriteReq_avg_miss_latency::total 26114.773971 # average WriteReq miss latency

287system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.095184 # average overall miss latency
288system.cpu.dcache.demand_avg_miss_latency::total 13655.095184 # average overall miss latency
289system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.051917 # average overall miss latency
290system.cpu.dcache.overall_avg_miss_latency::total 13655.051917 # average overall miss latency

287system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.206085 # average overall miss latency
288system.cpu.dcache.demand_avg_miss_latency::total 13655.206085 # average overall miss latency
289system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.162817 # average overall miss latency
290system.cpu.dcache.overall_avg_miss_latency::total 13655.162817 # average overall miss latency

291system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
292system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
293system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
294system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
295system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
296system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
297system.cpu.dcache.fast_writes 0 # number of fast writes performed
298system.cpu.dcache.cache_copies 0 # number of cache copies performed

--- 10 unchanged lines hidden (view full) ---

309system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses
310system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses
311system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
312system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
313system.cpu.dcache.demand_mshr_misses::cpu.data 946795 # number of demand (read+write) MSHR misses
314system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses
315system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses
316system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses

317system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10811180000 # number of ReadReq MSHR miss cycles
318system.cpu.dcache.ReadReq_mshr_miss_latency::total 10811180000 # number of ReadReq MSHR miss cycles

317system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10811285000 # number of ReadReq MSHR miss cycles
318system.cpu.dcache.ReadReq_mshr_miss_latency::total 10811285000 # number of ReadReq MSHR miss cycles

319system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1170574500 # number of WriteReq MSHR miss cycles
320system.cpu.dcache.WriteReq_mshr_miss_latency::total 1170574500 # number of WriteReq MSHR miss cycles
321system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 120000 # number of SoftPFReq MSHR miss cycles
322system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 120000 # number of SoftPFReq MSHR miss cycles

323system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11981754500 # number of demand (read+write) MSHR miss cycles
324system.cpu.dcache.demand_mshr_miss_latency::total 11981754500 # number of demand (read+write) MSHR miss cycles
325system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11981874500 # number of overall MSHR miss cycles
326system.cpu.dcache.overall_mshr_miss_latency::total 11981874500 # number of overall MSHR miss cycles

323system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11981859500 # number of demand (read+write) MSHR miss cycles
324system.cpu.dcache.demand_mshr_miss_latency::total 11981859500 # number of demand (read+write) MSHR miss cycles
325system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11981979500 # number of overall MSHR miss cycles
326system.cpu.dcache.overall_mshr_miss_latency::total 11981979500 # number of overall MSHR miss cycles

327system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses
328system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses
329system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses
330system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses
331system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005882 # mshr miss rate for SoftPFReq accesses
332system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005882 # mshr miss rate for SoftPFReq accesses
333system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 # mshr miss rate for demand accesses
334system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses
335system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses
336system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses

337system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12009.940168 # average ReadReq mshr miss latency
338system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12009.940168 # average ReadReq mshr miss latency

337system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12010.056810 # average ReadReq mshr miss latency
338system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12010.056810 # average ReadReq mshr miss latency

339system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25114.773971 # average WriteReq mshr miss latency
340system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25114.773971 # average WriteReq mshr miss latency
341system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 40000 # average SoftPFReq mshr miss latency
342system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 40000 # average SoftPFReq mshr miss latency

343system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12655.067359 # average overall mshr miss latency
344system.cpu.dcache.demand_avg_mshr_miss_latency::total 12655.067359 # average overall mshr miss latency
345system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12655.154003 # average overall mshr miss latency
346system.cpu.dcache.overall_avg_mshr_miss_latency::total 12655.154003 # average overall mshr miss latency

343system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12655.178259 # average overall mshr miss latency
344system.cpu.dcache.demand_avg_mshr_miss_latency::total 12655.178259 # average overall mshr miss latency
345system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12655.264903 # average overall mshr miss latency
346system.cpu.dcache.overall_avg_mshr_miss_latency::total 12655.264903 # average overall mshr miss latency

347system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
348system.cpu.icache.tags.replacements 2 # number of replacements

349system.cpu.icache.tags.tagsinuse 510.120565 # Cycle average of tags in use

349system.cpu.icache.tags.tagsinuse 510.120518 # Cycle average of tags in use

350system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks.
351system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks.
352system.cpu.icache.tags.avg_refs 180016.983306 # Average number of references to valid blocks.
353system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

354system.cpu.icache.tags.occ_blocks::cpu.inst 510.120565 # Average occupied blocks per requestor

354system.cpu.icache.tags.occ_blocks::cpu.inst 510.120518 # Average occupied blocks per requestor

355system.cpu.icache.tags.occ_percent::cpu.inst 0.249082 # Average percentage of cache occupancy
356system.cpu.icache.tags.occ_percent::total 0.249082 # Average percentage of cache occupancy
357system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id
358system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
359system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
360system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
361system.cpu.icache.tags.age_task_id_blocks_1024::4 552 # Occupied blocks per task id
362system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id

--- 6 unchanged lines hidden (view full) ---

369system.cpu.icache.overall_hits::cpu.inst 107830173 # number of overall hits
370system.cpu.icache.overall_hits::total 107830173 # number of overall hits
371system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses
372system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses
373system.cpu.icache.demand_misses::cpu.inst 599 # number of demand (read+write) misses
374system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses
375system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses
376system.cpu.icache.overall_misses::total 599 # number of overall misses

377system.cpu.icache.ReadReq_miss_latency::cpu.inst 32034000 # number of ReadReq miss cycles
378system.cpu.icache.ReadReq_miss_latency::total 32034000 # number of ReadReq miss cycles
379system.cpu.icache.demand_miss_latency::cpu.inst 32034000 # number of demand (read+write) miss cycles
380system.cpu.icache.demand_miss_latency::total 32034000 # number of demand (read+write) miss cycles
381system.cpu.icache.overall_miss_latency::cpu.inst 32034000 # number of overall miss cycles
382system.cpu.icache.overall_miss_latency::total 32034000 # number of overall miss cycles

377system.cpu.icache.ReadReq_miss_latency::cpu.inst 32054000 # number of ReadReq miss cycles
378system.cpu.icache.ReadReq_miss_latency::total 32054000 # number of ReadReq miss cycles
379system.cpu.icache.demand_miss_latency::cpu.inst 32054000 # number of demand (read+write) miss cycles
380system.cpu.icache.demand_miss_latency::total 32054000 # number of demand (read+write) miss cycles
381system.cpu.icache.overall_miss_latency::cpu.inst 32054000 # number of overall miss cycles
382system.cpu.icache.overall_miss_latency::total 32054000 # number of overall miss cycles

383system.cpu.icache.ReadReq_accesses::cpu.inst 107830772 # number of ReadReq accesses(hits+misses)
384system.cpu.icache.ReadReq_accesses::total 107830772 # number of ReadReq accesses(hits+misses)
385system.cpu.icache.demand_accesses::cpu.inst 107830772 # number of demand (read+write) accesses
386system.cpu.icache.demand_accesses::total 107830772 # number of demand (read+write) accesses
387system.cpu.icache.overall_accesses::cpu.inst 107830772 # number of overall (read+write) accesses
388system.cpu.icache.overall_accesses::total 107830772 # number of overall (read+write) accesses
389system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses
390system.cpu.icache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses
391system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses
392system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses
393system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses
394system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses

395system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53479.131886 # average ReadReq miss latency
396system.cpu.icache.ReadReq_avg_miss_latency::total 53479.131886 # average ReadReq miss latency
397system.cpu.icache.demand_avg_miss_latency::cpu.inst 53479.131886 # average overall miss latency
398system.cpu.icache.demand_avg_miss_latency::total 53479.131886 # average overall miss latency
399system.cpu.icache.overall_avg_miss_latency::cpu.inst 53479.131886 # average overall miss latency
400system.cpu.icache.overall_avg_miss_latency::total 53479.131886 # average overall miss latency

395system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53512.520868 # average ReadReq miss latency
396system.cpu.icache.ReadReq_avg_miss_latency::total 53512.520868 # average ReadReq miss latency
397system.cpu.icache.demand_avg_miss_latency::cpu.inst 53512.520868 # average overall miss latency
398system.cpu.icache.demand_avg_miss_latency::total 53512.520868 # average overall miss latency
399system.cpu.icache.overall_avg_miss_latency::cpu.inst 53512.520868 # average overall miss latency
400system.cpu.icache.overall_avg_miss_latency::total 53512.520868 # average overall miss latency

401system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
402system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
403system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
404system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
405system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
406system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
407system.cpu.icache.fast_writes 0 # number of fast writes performed
408system.cpu.icache.cache_copies 0 # number of cache copies performed
409system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses
410system.cpu.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses
411system.cpu.icache.demand_mshr_misses::cpu.inst 599 # number of demand (read+write) MSHR misses
412system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses
413system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses
414system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses

415system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31435000 # number of ReadReq MSHR miss cycles
416system.cpu.icache.ReadReq_mshr_miss_latency::total 31435000 # number of ReadReq MSHR miss cycles
417system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31435000 # number of demand (read+write) MSHR miss cycles
418system.cpu.icache.demand_mshr_miss_latency::total 31435000 # number of demand (read+write) MSHR miss cycles
419system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31435000 # number of overall MSHR miss cycles
420system.cpu.icache.overall_mshr_miss_latency::total 31435000 # number of overall MSHR miss cycles

415system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31455000 # number of ReadReq MSHR miss cycles
416system.cpu.icache.ReadReq_mshr_miss_latency::total 31455000 # number of ReadReq MSHR miss cycles
417system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31455000 # number of demand (read+write) MSHR miss cycles
418system.cpu.icache.demand_mshr_miss_latency::total 31455000 # number of demand (read+write) MSHR miss cycles
419system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31455000 # number of overall MSHR miss cycles
420system.cpu.icache.overall_mshr_miss_latency::total 31455000 # number of overall MSHR miss cycles

421system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses
422system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
423system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses
424system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses
425system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses
426system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses

427system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52479.131886 # average ReadReq mshr miss latency
428system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52479.131886 # average ReadReq mshr miss latency
429system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52479.131886 # average overall mshr miss latency
430system.cpu.icache.demand_avg_mshr_miss_latency::total 52479.131886 # average overall mshr miss latency
431system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52479.131886 # average overall mshr miss latency
432system.cpu.icache.overall_avg_mshr_miss_latency::total 52479.131886 # average overall mshr miss latency

427system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52512.520868 # average ReadReq mshr miss latency
428system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52512.520868 # average ReadReq mshr miss latency
429system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52512.520868 # average overall mshr miss latency
430system.cpu.icache.demand_avg_mshr_miss_latency::total 52512.520868 # average overall mshr miss latency
431system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52512.520868 # average overall mshr miss latency
432system.cpu.icache.overall_avg_mshr_miss_latency::total 52512.520868 # average overall mshr miss latency

433system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
434system.cpu.l2cache.tags.replacements 0 # number of replacements

435system.cpu.l2cache.tags.tagsinuse 9567.852238 # Cycle average of tags in use

435system.cpu.l2cache.tags.tagsinuse 9567.853327 # Cycle average of tags in use

436system.cpu.l2cache.tags.total_refs 1827433 # Total number of references to valid blocks.
437system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks.
438system.cpu.l2cache.tags.avg_refs 119.260784 # Average number of references to valid blocks.
439system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

440system.cpu.l2cache.tags.occ_blocks::writebacks 8879.446176 # Average occupied blocks per requestor
441system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.172976 # Average occupied blocks per requestor
442system.cpu.l2cache.tags.occ_blocks::cpu.data 194.233086 # Average occupied blocks per requestor

440system.cpu.l2cache.tags.occ_blocks::writebacks 8879.447332 # Average occupied blocks per requestor
441system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.172931 # Average occupied blocks per requestor
442system.cpu.l2cache.tags.occ_blocks::cpu.data 194.233064 # Average occupied blocks per requestor

443system.cpu.l2cache.tags.occ_percent::writebacks 0.270979 # Average percentage of cache occupancy
444system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015081 # Average percentage of cache occupancy
445system.cpu.l2cache.tags.occ_percent::cpu.data 0.005928 # Average percentage of cache occupancy
446system.cpu.l2cache.tags.occ_percent::total 0.291988 # Average percentage of cache occupancy
447system.cpu.l2cache.tags.occ_task_id_blocks::1024 15323 # Occupied blocks per task id
448system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
449system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
450system.cpu.l2cache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id

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581system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42509.302326 # average ReadSharedReq mshr miss latency
582system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42520.797227 # average overall mshr miss latency
583system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42517.103570 # average overall mshr miss latency
584system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42517.242503 # average overall mshr miss latency
585system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42520.797227 # average overall mshr miss latency
586system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42517.103570 # average overall mshr miss latency
587system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42517.242503 # average overall mshr miss latency
588system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

589system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter.
590system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data.
591system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
592system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
593system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
594system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

589system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution
590system.cpu.toL2Bus.trans_dist::Writeback 942334 # Transaction distribution
591system.cpu.toL2Bus.trans_dist::CleanEvict 256 # Transaction distribution
592system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution
593system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution
594system.cpu.toL2Bus.trans_dist::ReadCleanReq 599 # Transaction distribution
595system.cpu.toL2Bus.trans_dist::ReadSharedReq 900189 # Transaction distribution
596system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1199 # Packet count per connected master and slave (bytes)
597system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2836185 # Packet count per connected master and slave (bytes)
598system.cpu.toL2Bus.pkt_count::total 2837384 # Packet count per connected master and slave (bytes)
599system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38336 # Cumulative packet size per connected master and slave (bytes)
600system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes)
601system.cpu.toL2Bus.pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes)
602system.cpu.toL2Bus.snoops 0 # Total snoops (count)
603system.cpu.toL2Bus.snoop_fanout::samples 1890101 # Request fanout histogram

595system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution
596system.cpu.toL2Bus.trans_dist::Writeback 942334 # Transaction distribution
597system.cpu.toL2Bus.trans_dist::CleanEvict 256 # Transaction distribution
598system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution
599system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution
600system.cpu.toL2Bus.trans_dist::ReadCleanReq 599 # Transaction distribution
601system.cpu.toL2Bus.trans_dist::ReadSharedReq 900189 # Transaction distribution
602system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1199 # Packet count per connected master and slave (bytes)
603system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2836185 # Packet count per connected master and slave (bytes)
604system.cpu.toL2Bus.pkt_count::total 2837384 # Packet count per connected master and slave (bytes)
605system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38336 # Cumulative packet size per connected master and slave (bytes)
606system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes)
607system.cpu.toL2Bus.pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes)
608system.cpu.toL2Bus.snoops 0 # Total snoops (count)
609system.cpu.toL2Bus.snoop_fanout::samples 1890101 # Request fanout histogram

604system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
605system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram

610system.cpu.toL2Bus.snoop_fanout::mean 0.000126 # Request fanout histogram
611system.cpu.toL2Bus.snoop_fanout::stdev 0.011244 # Request fanout histogram

606system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

612system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

607system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
608system.cpu.toL2Bus.snoop_fanout::1 1890101 100.00% 100.00% # Request fanout histogram

613system.cpu.toL2Bus.snoop_fanout::0 1889862 99.99% 99.99% # Request fanout histogram
614system.cpu.toL2Bus.snoop_fanout::1 239 0.01% 100.00% # Request fanout histogram

609system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
610system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

615system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
616system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

611system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram

617system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram