3,5c3,5
< sim_seconds 0.147149 # Number of seconds simulated
< sim_ticks 147148719500 # Number of ticks simulated
< final_tick 147148719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.147164 # Number of seconds simulated
> sim_ticks 147164058500 # Number of ticks simulated
> final_tick 147164058500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 664401 # Simulator instruction rate (inst/s)
< host_op_rate 667702 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1079367051 # Simulator tick rate (ticks/s)
< host_mem_usage 398392 # Number of bytes of host memory used
< host_seconds 136.33 # Real time elapsed on the host
---
> host_inst_rate 748296 # Simulator instruction rate (inst/s)
> host_op_rate 752015 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1215788381 # Simulator tick rate (ticks/s)
> host_mem_usage 404056 # Number of bytes of host memory used
> host_seconds 121.04 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
25,33c25,33
< system.physmem.bw_read::cpu.inst 250957 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 6420933 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 6671890 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 250957 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 250957 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 250957 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 6420933 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 6671890 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
---
> system.physmem.bw_read::cpu.inst 250931 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 6420263 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 6671194 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 250931 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 250931 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 250931 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 6420263 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 6671194 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
35c35
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
65c65
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
95c95
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
125c125
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
156,157c156,157
< system.cpu.pwrStateResidencyTicks::ON 147148719500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 294297439 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 147164058500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 294328117 # number of cpu cycles simulated
178c178
< system.cpu.num_busy_cycles 294297438.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 294328116.998000 # Number of busy cycles
217c217
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
219c219
< system.cpu.dcache.tags.tagsinuse 3565.478025 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 3565.461526 # Cycle average of tags in use
223,226c223,226
< system.cpu.dcache.tags.warmup_cycle 54453325500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 3565.478025 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.870478 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.870478 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.warmup_cycle 54459450500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 3565.461526 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.870474 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.870474 # Average percentage of cache occupancy
228,230c228,230
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 1357 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 1358 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 2564 # Occupied blocks per task id
235c235
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
260,267c260,267
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11713009000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11713009000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 1319019500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 1319019500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 13032028500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 13032028500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 13032028500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 13032028500 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11713223000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11713223000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 1333567500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 1333567500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 13046790500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 13046790500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 13046790500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 13046790500 # number of overall miss cycles
292,299c292,299
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13011.750892 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 13011.750892 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28299.673883 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 28299.673883 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 13764.346808 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 13764.346808 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 13764.303194 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 13764.303194 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13011.988620 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 13011.988620 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28611.802442 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 28611.802442 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 13779.938339 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 13779.938339 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 13779.894677 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 13779.894677 # average overall miss latency
324,333c324,333
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10812776000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 10812776000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1272410500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 1272410500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 134000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 134000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12085186500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 12085186500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12085320500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 12085320500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10812989000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10812989000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1286958500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 1286958500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 136000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 136000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12099947500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 12099947500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12100083500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 12100083500 # number of overall MSHR miss cycles
344,354c344,354
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12011.713135 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12011.713135 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27299.673883 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27299.673883 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44666.666667 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44666.666667 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12764.311704 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 12764.311704 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12764.412789 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 12764.412789 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12011.949753 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12011.949753 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27611.802442 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27611.802442 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 45333.333333 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 45333.333333 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12779.902196 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 12779.902196 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12780.005344 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 12780.005344 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
356c356
< system.cpu.icache.tags.tagsinuse 510.111710 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 510.110453 # Cycle average of tags in use
361,363c361,363
< system.cpu.icache.tags.occ_blocks::cpu.inst 510.111710 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.249078 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.249078 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 510.110453 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.249077 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.249077 # Average percentage of cache occupancy
372c372
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
385,390c385,390
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 36093000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 36093000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 36093000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 36093000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 36093000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 36093000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 36670000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 36670000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 36670000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 36670000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 36670000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 36670000 # number of overall miss cycles
403,408c403,408
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60255.425710 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 60255.425710 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 60255.425710 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 60255.425710 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61218.697830 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 61218.697830 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 61218.697830 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 61218.697830 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 61218.697830 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 61218.697830 # average overall miss latency
423,428c423,428
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35494000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 35494000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35494000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 35494000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35494000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 35494000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36071000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 36071000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36071000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 36071000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36071000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 36071000 # number of overall MSHR miss cycles
435,441c435,441
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59255.425710 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59255.425710 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60218.697830 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60218.697830 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60218.697830 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 60218.697830 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60218.697830 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 60218.697830 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
443,446c443,446
< system.cpu.l2cache.tags.tagsinuse 9564.658425 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 1827433 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 119.260784 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 10666.571104 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 1874647 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 15340 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 122.206454 # Average number of references to valid blocks.
448,451c448,449
< system.cpu.l2cache.tags.occ_blocks::writebacks 8876.269803 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.164592 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 194.224030 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.270882 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.163402 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 10172.407702 # Average occupied blocks per requestor
453,455c451,453
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.005927 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.291890 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 15323 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.310437 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.325518 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 15340 # Occupied blocks per task id
458,464c456,462
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1473 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13704 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 15181828 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 15181828 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15229 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.468140 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 15135236 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 15135236 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
493,504c491,502
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 865856500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 865856500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 34343500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 34343500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12794500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 12794500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 34343500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 878651000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 912994500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 34343500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 878651000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 912994500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 880404500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 880404500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 34920500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 34920500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13009500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 13009500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 34920500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 893414000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 928334500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 34920500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 893414000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 928334500 # number of overall miss cycles
533,544c531,542
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59517.218862 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59517.218862 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59520.797227 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59520.797227 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59509.302326 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59509.302326 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59520.797227 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59517.242503 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59520.797227 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59517.242503 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60517.218862 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60517.218862 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60520.797227 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60520.797227 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60509.302326 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60509.302326 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60520.797227 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60517.103570 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60517.242503 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60520.797227 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60517.103570 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60517.242503 # average overall miss latency
563,574c561,572
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 720376500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 720376500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 28573500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 28573500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10644500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10644500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28573500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 731021000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 759594500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28573500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 731021000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 759594500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 734924500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 734924500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 29150500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 29150500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10859500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10859500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29150500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 745784000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 774934500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29150500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 745784000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 774934500 # number of overall MSHR miss cycles
587,598c585,596
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49517.218862 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49517.218862 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49520.797227 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49520.797227 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49509.302326 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49509.302326 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50517.218862 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50517.218862 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50520.797227 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50520.797227 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50509.302326 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50509.302326 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50520.797227 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50517.103570 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50517.242503 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50520.797227 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50517.103570 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50517.242503 # average overall mshr miss latency
605c603
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
639c637,643
< system.membus.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 15340 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
< sim_seconds 0.147149 # Number of seconds simulated
< sim_ticks 147148719500 # Number of ticks simulated
< final_tick 147148719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.147164 # Number of seconds simulated
> sim_ticks 147164058500 # Number of ticks simulated
> final_tick 147164058500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 664401 # Simulator instruction rate (inst/s)
< host_op_rate 667702 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1079367051 # Simulator tick rate (ticks/s)
< host_mem_usage 398392 # Number of bytes of host memory used
< host_seconds 136.33 # Real time elapsed on the host
---
> host_inst_rate 748296 # Simulator instruction rate (inst/s)
> host_op_rate 752015 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1215788381 # Simulator tick rate (ticks/s)
> host_mem_usage 404056 # Number of bytes of host memory used
> host_seconds 121.04 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
25,33c25,33
< system.physmem.bw_read::cpu.inst 250957 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 6420933 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 6671890 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 250957 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 250957 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 250957 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 6420933 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 6671890 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
---
> system.physmem.bw_read::cpu.inst 250931 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 6420263 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 6671194 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 250931 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 250931 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 250931 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 6420263 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 6671194 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
35c35
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
65c65
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
95c95
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
125c125
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
156,157c156,157
< system.cpu.pwrStateResidencyTicks::ON 147148719500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 294297439 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 147164058500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 294328117 # number of cpu cycles simulated
178c178
< system.cpu.num_busy_cycles 294297438.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 294328116.998000 # Number of busy cycles
217c217
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
219c219
< system.cpu.dcache.tags.tagsinuse 3565.478025 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 3565.461526 # Cycle average of tags in use
223,226c223,226
< system.cpu.dcache.tags.warmup_cycle 54453325500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 3565.478025 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.870478 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.870478 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.warmup_cycle 54459450500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 3565.461526 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.870474 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.870474 # Average percentage of cache occupancy
228,230c228,230
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 1357 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 1358 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 2564 # Occupied blocks per task id
235c235
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
260,267c260,267
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11713009000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11713009000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 1319019500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 1319019500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 13032028500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 13032028500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 13032028500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 13032028500 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11713223000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11713223000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 1333567500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 1333567500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 13046790500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 13046790500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 13046790500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 13046790500 # number of overall miss cycles
292,299c292,299
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13011.750892 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 13011.750892 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28299.673883 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 28299.673883 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 13764.346808 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 13764.346808 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 13764.303194 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 13764.303194 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13011.988620 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 13011.988620 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28611.802442 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 28611.802442 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 13779.938339 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 13779.938339 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 13779.894677 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 13779.894677 # average overall miss latency
324,333c324,333
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10812776000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 10812776000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1272410500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 1272410500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 134000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 134000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12085186500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 12085186500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12085320500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 12085320500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10812989000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10812989000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1286958500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 1286958500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 136000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 136000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12099947500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 12099947500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12100083500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 12100083500 # number of overall MSHR miss cycles
344,354c344,354
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12011.713135 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12011.713135 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27299.673883 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27299.673883 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44666.666667 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44666.666667 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12764.311704 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 12764.311704 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12764.412789 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 12764.412789 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12011.949753 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12011.949753 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27611.802442 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27611.802442 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 45333.333333 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 45333.333333 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12779.902196 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 12779.902196 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12780.005344 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 12780.005344 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
356c356
< system.cpu.icache.tags.tagsinuse 510.111710 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 510.110453 # Cycle average of tags in use
361,363c361,363
< system.cpu.icache.tags.occ_blocks::cpu.inst 510.111710 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.249078 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.249078 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 510.110453 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.249077 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.249077 # Average percentage of cache occupancy
372c372
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
385,390c385,390
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 36093000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 36093000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 36093000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 36093000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 36093000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 36093000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 36670000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 36670000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 36670000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 36670000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 36670000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 36670000 # number of overall miss cycles
403,408c403,408
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60255.425710 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 60255.425710 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 60255.425710 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 60255.425710 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61218.697830 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 61218.697830 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 61218.697830 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 61218.697830 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 61218.697830 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 61218.697830 # average overall miss latency
423,428c423,428
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35494000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 35494000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35494000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 35494000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35494000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 35494000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36071000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 36071000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36071000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 36071000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36071000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 36071000 # number of overall MSHR miss cycles
435,441c435,441
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59255.425710 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59255.425710 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60218.697830 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60218.697830 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60218.697830 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 60218.697830 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60218.697830 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 60218.697830 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
443,446c443,446
< system.cpu.l2cache.tags.tagsinuse 9564.658425 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 1827433 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 119.260784 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 10666.571104 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 1874647 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 15340 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 122.206454 # Average number of references to valid blocks.
448,451c448,449
< system.cpu.l2cache.tags.occ_blocks::writebacks 8876.269803 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.164592 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 194.224030 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.270882 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.163402 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 10172.407702 # Average occupied blocks per requestor
453,455c451,453
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.005927 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.291890 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 15323 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.310437 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.325518 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 15340 # Occupied blocks per task id
458,464c456,462
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1473 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13704 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 15181828 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 15181828 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15229 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.468140 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 15135236 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 15135236 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
493,504c491,502
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 865856500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 865856500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 34343500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 34343500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12794500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 12794500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 34343500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 878651000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 912994500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 34343500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 878651000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 912994500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 880404500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 880404500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 34920500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 34920500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13009500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 13009500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 34920500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 893414000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 928334500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 34920500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 893414000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 928334500 # number of overall miss cycles
533,544c531,542
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59517.218862 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59517.218862 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59520.797227 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59520.797227 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59509.302326 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59509.302326 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59520.797227 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59517.242503 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59520.797227 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59517.242503 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60517.218862 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60517.218862 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60520.797227 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60520.797227 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60509.302326 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60509.302326 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60520.797227 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60517.103570 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60517.242503 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60520.797227 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60517.103570 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60517.242503 # average overall miss latency
563,574c561,572
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 720376500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 720376500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 28573500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 28573500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10644500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10644500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28573500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 731021000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 759594500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28573500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 731021000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 759594500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 734924500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 734924500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 29150500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 29150500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10859500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10859500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29150500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 745784000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 774934500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29150500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 745784000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 774934500 # number of overall MSHR miss cycles
587,598c585,596
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49517.218862 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49517.218862 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49520.797227 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49520.797227 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49509.302326 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49509.302326 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50517.218862 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50517.218862 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50520.797227 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50520.797227 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50509.302326 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50509.302326 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50520.797227 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50517.103570 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50517.242503 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50520.797227 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50517.103570 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50517.242503 # average overall mshr miss latency
605c603
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
639c637,643
< system.membus.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 15340 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states