4,5c4,5
< sim_ticks 147041221500 # Number of ticks simulated
< final_tick 147041221500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 147041346500 # Number of ticks simulated
> final_tick 147041346500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 1077194 # Simulator instruction rate (inst/s)
< host_op_rate 1082547 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1748701394 # Simulator tick rate (ticks/s)
< host_mem_usage 444972 # Number of bytes of host memory used
< host_seconds 84.09 # Real time elapsed on the host
---
> host_inst_rate 870528 # Simulator instruction rate (inst/s)
> host_op_rate 874854 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1413203999 # Simulator tick rate (ticks/s)
> host_mem_usage 449664 # Number of bytes of host memory used
> host_seconds 104.05 # Real time elapsed on the host
25,26c25,26
< system.physmem.bw_read::cpu.data 6425627 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 6676767 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 6425621 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 6676761 # Total read bandwidth from this memory (bytes/s)
30,31c30,31
< system.physmem.bw_total::cpu.data 6425627 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 6676767 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 6425621 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 6676761 # Total bandwidth to/from this memory (bytes/s)
150c150
< system.cpu.numCycles 294082443 # number of cpu cycles simulated
---
> system.cpu.numCycles 294082693 # number of cpu cycles simulated
171c171
< system.cpu.num_busy_cycles 294082442.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 294082692.998000 # Number of busy cycles
211c211
< system.cpu.dcache.tags.tagsinuse 3565.593910 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 3565.593612 # Cycle average of tags in use
215,216c215,216
< system.cpu.dcache.tags.warmup_cycle 54410415500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593910 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.warmup_cycle 54410450500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593612 # Average occupied blocks per requestor
251,252c251,252
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711406000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11711406000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711511000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11711511000 # number of ReadReq miss cycles
255,258c255,258
< system.cpu.dcache.demand_miss_latency::cpu.data 12928589500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 12928589500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 12928589500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 12928589500 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 12928694500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 12928694500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 12928694500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 12928694500 # number of overall miss cycles
283,284c283,284
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.970151 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.970151 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13010.086793 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 13010.086793 # average ReadReq miss latency
287,290c287,290
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.095184 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 13655.095184 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.051917 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 13655.051917 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.206085 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 13655.206085 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.162817 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 13655.162817 # average overall miss latency
317,318c317,318
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10811180000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 10811180000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10811285000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10811285000 # number of ReadReq MSHR miss cycles
323,326c323,326
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11981754500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 11981754500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11981874500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 11981874500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11981859500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 11981859500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11981979500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 11981979500 # number of overall MSHR miss cycles
337,338c337,338
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12009.940168 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12009.940168 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12010.056810 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12010.056810 # average ReadReq mshr miss latency
343,346c343,346
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12655.067359 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 12655.067359 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12655.154003 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 12655.154003 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12655.178259 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 12655.178259 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12655.264903 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 12655.264903 # average overall mshr miss latency
349c349
< system.cpu.icache.tags.tagsinuse 510.120565 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 510.120518 # Cycle average of tags in use
354c354
< system.cpu.icache.tags.occ_blocks::cpu.inst 510.120565 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 510.120518 # Average occupied blocks per requestor
377,382c377,382
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 32034000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 32034000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 32034000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 32034000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 32034000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 32034000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 32054000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 32054000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 32054000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 32054000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 32054000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 32054000 # number of overall miss cycles
395,400c395,400
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53479.131886 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 53479.131886 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 53479.131886 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 53479.131886 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 53479.131886 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 53479.131886 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53512.520868 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 53512.520868 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 53512.520868 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 53512.520868 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 53512.520868 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 53512.520868 # average overall miss latency
415,420c415,420
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31435000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 31435000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31435000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 31435000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31435000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 31435000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31455000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 31455000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31455000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 31455000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31455000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 31455000 # number of overall MSHR miss cycles
427,432c427,432
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52479.131886 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52479.131886 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52479.131886 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 52479.131886 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52479.131886 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 52479.131886 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52512.520868 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52512.520868 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52512.520868 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 52512.520868 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52512.520868 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 52512.520868 # average overall mshr miss latency
435c435
< system.cpu.l2cache.tags.tagsinuse 9567.852238 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 9567.853327 # Cycle average of tags in use
440,442c440,442
< system.cpu.l2cache.tags.occ_blocks::writebacks 8879.446176 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.172976 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 194.233086 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 8879.447332 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.172931 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 194.233064 # Average occupied blocks per requestor
588a589,594
> system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
604,605c610,611
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.000126 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.011244 # Request fanout histogram
607,608c613,614
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 1890101 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 1889862 99.99% 99.99% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 239 0.01% 100.00% # Request fanout histogram
611c617
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
< sim_ticks 147041221500 # Number of ticks simulated
< final_tick 147041221500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 147041346500 # Number of ticks simulated
> final_tick 147041346500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 1077194 # Simulator instruction rate (inst/s)
< host_op_rate 1082547 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1748701394 # Simulator tick rate (ticks/s)
< host_mem_usage 444972 # Number of bytes of host memory used
< host_seconds 84.09 # Real time elapsed on the host
---
> host_inst_rate 870528 # Simulator instruction rate (inst/s)
> host_op_rate 874854 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1413203999 # Simulator tick rate (ticks/s)
> host_mem_usage 449664 # Number of bytes of host memory used
> host_seconds 104.05 # Real time elapsed on the host
25,26c25,26
< system.physmem.bw_read::cpu.data 6425627 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 6676767 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 6425621 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 6676761 # Total read bandwidth from this memory (bytes/s)
30,31c30,31
< system.physmem.bw_total::cpu.data 6425627 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 6676767 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 6425621 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 6676761 # Total bandwidth to/from this memory (bytes/s)
150c150
< system.cpu.numCycles 294082443 # number of cpu cycles simulated
---
> system.cpu.numCycles 294082693 # number of cpu cycles simulated
171c171
< system.cpu.num_busy_cycles 294082442.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 294082692.998000 # Number of busy cycles
211c211
< system.cpu.dcache.tags.tagsinuse 3565.593910 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 3565.593612 # Cycle average of tags in use
215,216c215,216
< system.cpu.dcache.tags.warmup_cycle 54410415500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593910 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.warmup_cycle 54410450500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593612 # Average occupied blocks per requestor
251,252c251,252
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711406000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11711406000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711511000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11711511000 # number of ReadReq miss cycles
255,258c255,258
< system.cpu.dcache.demand_miss_latency::cpu.data 12928589500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 12928589500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 12928589500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 12928589500 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 12928694500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 12928694500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 12928694500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 12928694500 # number of overall miss cycles
283,284c283,284
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.970151 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.970151 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13010.086793 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 13010.086793 # average ReadReq miss latency
287,290c287,290
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.095184 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 13655.095184 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.051917 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 13655.051917 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.206085 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 13655.206085 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.162817 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 13655.162817 # average overall miss latency
317,318c317,318
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10811180000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 10811180000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10811285000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10811285000 # number of ReadReq MSHR miss cycles
323,326c323,326
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11981754500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 11981754500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11981874500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 11981874500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11981859500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 11981859500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11981979500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 11981979500 # number of overall MSHR miss cycles
337,338c337,338
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12009.940168 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12009.940168 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12010.056810 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12010.056810 # average ReadReq mshr miss latency
343,346c343,346
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12655.067359 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 12655.067359 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12655.154003 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 12655.154003 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12655.178259 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 12655.178259 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12655.264903 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 12655.264903 # average overall mshr miss latency
349c349
< system.cpu.icache.tags.tagsinuse 510.120565 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 510.120518 # Cycle average of tags in use
354c354
< system.cpu.icache.tags.occ_blocks::cpu.inst 510.120565 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 510.120518 # Average occupied blocks per requestor
377,382c377,382
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 32034000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 32034000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 32034000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 32034000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 32034000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 32034000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 32054000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 32054000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 32054000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 32054000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 32054000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 32054000 # number of overall miss cycles
395,400c395,400
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53479.131886 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 53479.131886 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 53479.131886 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 53479.131886 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 53479.131886 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 53479.131886 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53512.520868 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 53512.520868 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 53512.520868 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 53512.520868 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 53512.520868 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 53512.520868 # average overall miss latency
415,420c415,420
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31435000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 31435000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31435000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 31435000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31435000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 31435000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31455000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 31455000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31455000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 31455000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31455000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 31455000 # number of overall MSHR miss cycles
427,432c427,432
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52479.131886 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52479.131886 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52479.131886 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 52479.131886 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52479.131886 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 52479.131886 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52512.520868 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52512.520868 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52512.520868 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 52512.520868 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52512.520868 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 52512.520868 # average overall mshr miss latency
435c435
< system.cpu.l2cache.tags.tagsinuse 9567.852238 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 9567.853327 # Cycle average of tags in use
440,442c440,442
< system.cpu.l2cache.tags.occ_blocks::writebacks 8879.446176 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.172976 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 194.233086 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 8879.447332 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.172931 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 194.233064 # Average occupied blocks per requestor
588a589,594
> system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
604,605c610,611
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.000126 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.011244 # Request fanout histogram
607,608c613,614
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 1890101 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 1889862 99.99% 99.99% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 239 0.01% 100.00% # Request fanout histogram
611c617
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram