Cross Reference: /gem5/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt

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stats.txt (11312:3d7a85d71bd1)	stats.txt (11336:b318499f676c)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.147149 # Number of seconds simulated 4sim_ticks 147148719500 # Number of ticks simulated 5final_tick 147148719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.147149 # Number of seconds simulated 4sim_ticks 147148719500 # Number of ticks simulated 5final_tick 147148719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 392484 # Simulator instruction rate (inst/s) 8host_op_rate 394434 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 637618235 # Simulator tick rate (ticks/s) 10host_mem_usage 382304 # Number of bytes of host memory used 11host_seconds 230.78 # Real time elapsed on the host	7host_inst_rate 1174056 # Simulator instruction rate (inst/s) 8host_op_rate 1179890 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1907338487 # Simulator tick rate (ticks/s) 10host_mem_usage 402756 # Number of bytes of host memory used 11host_seconds 77.15 # Real time elapsed on the host
12sim_insts 90576862 # Number of instructions simulated 13sim_ops 91026991 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 36928 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 944832 # Number of bytes read from this memory 18system.physmem.bytes_read::total 981760 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 36928 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 36928 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 577 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 14763 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 250957 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 6420933 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 6671890 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 250957 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 250957 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 250957 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 6420933 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 6671890 # Total bandwidth to/from this memory (bytes/s) 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 34system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 36system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 41system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 42system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 43system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 44system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 45system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 46system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 47system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 48system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 49system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 50system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 51system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 52system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 53system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 54system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 55system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 56system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 57system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 58system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 59system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 60system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 61system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 62system.cpu.dtb.walker.walks 0 # Table walker walks requested 63system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 64system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 65system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 66system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 67system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 68system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 69system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 70system.cpu.dtb.inst_hits 0 # ITB inst hits 71system.cpu.dtb.inst_misses 0 # ITB inst misses 72system.cpu.dtb.read_hits 0 # DTB read hits 73system.cpu.dtb.read_misses 0 # DTB read misses 74system.cpu.dtb.write_hits 0 # DTB write hits 75system.cpu.dtb.write_misses 0 # DTB write misses 76system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 77system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 78system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 79system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 80system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 81system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 82system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 83system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 84system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 85system.cpu.dtb.read_accesses 0 # DTB read accesses 86system.cpu.dtb.write_accesses 0 # DTB write accesses 87system.cpu.dtb.inst_accesses 0 # ITB inst accesses 88system.cpu.dtb.hits 0 # DTB hits 89system.cpu.dtb.misses 0 # DTB misses 90system.cpu.dtb.accesses 0 # DTB accesses 91system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 92system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 93system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 94system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 95system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 96system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 99system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 100system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 101system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 102system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 103system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 104system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 105system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 106system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 107system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 108system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 109system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 110system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 111system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 112system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 113system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 114system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 115system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 116system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 117system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 118system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 119system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 120system.cpu.itb.walker.walks 0 # Table walker walks requested 121system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 122system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 123system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 124system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 125system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 126system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 127system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 128system.cpu.itb.inst_hits 0 # ITB inst hits 129system.cpu.itb.inst_misses 0 # ITB inst misses 130system.cpu.itb.read_hits 0 # DTB read hits 131system.cpu.itb.read_misses 0 # DTB read misses 132system.cpu.itb.write_hits 0 # DTB write hits 133system.cpu.itb.write_misses 0 # DTB write misses 134system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 135system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 136system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 137system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 138system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 139system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 140system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 141system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 142system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 143system.cpu.itb.read_accesses 0 # DTB read accesses 144system.cpu.itb.write_accesses 0 # DTB write accesses 145system.cpu.itb.inst_accesses 0 # ITB inst accesses 146system.cpu.itb.hits 0 # DTB hits 147system.cpu.itb.misses 0 # DTB misses 148system.cpu.itb.accesses 0 # DTB accesses 149system.cpu.workload.num_syscalls 442 # Number of system calls 150system.cpu.numCycles 294297439 # number of cpu cycles simulated 151system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 152system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 153system.cpu.committedInsts 90576862 # Number of instructions committed 154system.cpu.committedOps 91026991 # Number of ops (including micro ops) committed 155system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses 156system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses 157system.cpu.num_func_calls 112245 # number of times a function call or return occured 158system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls 159system.cpu.num_int_insts 72326352 # number of integer instructions 160system.cpu.num_fp_insts 48 # number of float instructions 161system.cpu.num_int_register_reads 124237033 # number of times the integer registers were read 162system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written 163system.cpu.num_fp_register_reads 54 # number of times the floating registers were read 164system.cpu.num_fp_register_writes 30 # number of times the floating registers were written 165system.cpu.num_cc_register_reads 339191621 # number of times the CC registers were read 166system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written 167system.cpu.num_mem_refs 27220755 # number of memory refs 168system.cpu.num_load_insts 22475911 # Number of load instructions 169system.cpu.num_store_insts 4744844 # Number of store instructions 170system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 171system.cpu.num_busy_cycles 294297438.998000 # Number of busy cycles 172system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 173system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 174system.cpu.Branches 18732305 # Number of branches fetched 175system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 176system.cpu.op_class::IntAlu 63822829 70.09% 70.09% # Class of executed instruction 177system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction 178system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction 179system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction 180system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction 181system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction 182system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction 183system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction 184system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction 185system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction 186system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction 187system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction 188system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction 189system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction 190system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction 191system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction 192system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction 193system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction 194system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction 195system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction 196system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction 197system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction 198system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction 199system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction 200system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction 201system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction 202system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction 203system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction 204system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction 205system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction 206system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction 207system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 208system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 209system.cpu.op_class::total 91054081 # Class of executed instruction 210system.cpu.dcache.tags.replacements 942702 # number of replacements 211system.cpu.dcache.tags.tagsinuse 3565.478025 # Cycle average of tags in use 212system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. 213system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. 214system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. 215system.cpu.dcache.tags.warmup_cycle 54453325500 # Cycle when the warmup percentage was hit. 216system.cpu.dcache.tags.occ_blocks::cpu.data 3565.478025 # Average occupied blocks per requestor 217system.cpu.dcache.tags.occ_percent::cpu.data 0.870478 # Average percentage of cache occupancy 218system.cpu.dcache.tags.occ_percent::total 0.870478 # Average percentage of cache occupancy 219system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 220system.cpu.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id 221system.cpu.dcache.tags.age_task_id_blocks_1024::1 1357 # Occupied blocks per task id 222system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id 223system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id 224system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 225system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses 226system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses 227system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits 228system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits 229system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits 230system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits 231system.cpu.dcache.SoftPFReq_hits::cpu.data 507 # number of SoftPFReq hits 232system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits 233system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits 234system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits 235system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 236system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits 237system.cpu.dcache.demand_hits::cpu.data 26245320 # number of demand (read+write) hits 238system.cpu.dcache.demand_hits::total 26245320 # number of demand (read+write) hits 239system.cpu.dcache.overall_hits::cpu.data 26245827 # number of overall hits 240system.cpu.dcache.overall_hits::total 26245827 # number of overall hits 241system.cpu.dcache.ReadReq_misses::cpu.data 900187 # number of ReadReq misses 242system.cpu.dcache.ReadReq_misses::total 900187 # number of ReadReq misses 243system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses 244system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses 245system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses 246system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses 247system.cpu.dcache.demand_misses::cpu.data 946796 # number of demand (read+write) misses 248system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses 249system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses 250system.cpu.dcache.overall_misses::total 946799 # number of overall misses 251system.cpu.dcache.ReadReq_miss_latency::cpu.data 11713009000 # number of ReadReq miss cycles 252system.cpu.dcache.ReadReq_miss_latency::total 11713009000 # number of ReadReq miss cycles 253system.cpu.dcache.WriteReq_miss_latency::cpu.data 1319019500 # number of WriteReq miss cycles 254system.cpu.dcache.WriteReq_miss_latency::total 1319019500 # number of WriteReq miss cycles 255system.cpu.dcache.demand_miss_latency::cpu.data 13032028500 # number of demand (read+write) miss cycles 256system.cpu.dcache.demand_miss_latency::total 13032028500 # number of demand (read+write) miss cycles 257system.cpu.dcache.overall_miss_latency::cpu.data 13032028500 # number of overall miss cycles 258system.cpu.dcache.overall_miss_latency::total 13032028500 # number of overall miss cycles 259system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses) 260system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses) 261system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 262system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 263system.cpu.dcache.SoftPFReq_accesses::cpu.data 510 # number of SoftPFReq accesses(hits+misses) 264system.cpu.dcache.SoftPFReq_accesses::total 510 # number of SoftPFReq accesses(hits+misses) 265system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 266system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 267system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 268system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) 269system.cpu.dcache.demand_accesses::cpu.data 27192116 # number of demand (read+write) accesses 270system.cpu.dcache.demand_accesses::total 27192116 # number of demand (read+write) accesses 271system.cpu.dcache.overall_accesses::cpu.data 27192626 # number of overall (read+write) accesses 272system.cpu.dcache.overall_accesses::total 27192626 # number of overall (read+write) accesses 273system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040085 # miss rate for ReadReq accesses 274system.cpu.dcache.ReadReq_miss_rate::total 0.040085 # miss rate for ReadReq accesses 275system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses 276system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses 277system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005882 # miss rate for SoftPFReq accesses 278system.cpu.dcache.SoftPFReq_miss_rate::total 0.005882 # miss rate for SoftPFReq accesses 279system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 # miss rate for demand accesses 280system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses 281system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses 282system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses 283system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13011.750892 # average ReadReq miss latency 284system.cpu.dcache.ReadReq_avg_miss_latency::total 13011.750892 # average ReadReq miss latency 285system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28299.673883 # average WriteReq miss latency 286system.cpu.dcache.WriteReq_avg_miss_latency::total 28299.673883 # average WriteReq miss latency 287system.cpu.dcache.demand_avg_miss_latency::cpu.data 13764.346808 # average overall miss latency 288system.cpu.dcache.demand_avg_miss_latency::total 13764.346808 # average overall miss latency 289system.cpu.dcache.overall_avg_miss_latency::cpu.data 13764.303194 # average overall miss latency 290system.cpu.dcache.overall_avg_miss_latency::total 13764.303194 # average overall miss latency 291system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 292system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 293system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 294system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 295system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 296system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 297system.cpu.dcache.fast_writes 0 # number of fast writes performed 298system.cpu.dcache.cache_copies 0 # number of cache copies performed 299system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks 300system.cpu.dcache.writebacks::total 942334 # number of writebacks 301system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 302system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 303system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 304system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 305system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 306system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits 307system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900186 # number of ReadReq MSHR misses 308system.cpu.dcache.ReadReq_mshr_misses::total 900186 # number of ReadReq MSHR misses 309system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses 310system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses 311system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 312system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 313system.cpu.dcache.demand_mshr_misses::cpu.data 946795 # number of demand (read+write) MSHR misses 314system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses 315system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses 316system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses 317system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10812776000 # number of ReadReq MSHR miss cycles 318system.cpu.dcache.ReadReq_mshr_miss_latency::total 10812776000 # number of ReadReq MSHR miss cycles 319system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1272410500 # number of WriteReq MSHR miss cycles 320system.cpu.dcache.WriteReq_mshr_miss_latency::total 1272410500 # number of WriteReq MSHR miss cycles 321system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 134000 # number of SoftPFReq MSHR miss cycles 322system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 134000 # number of SoftPFReq MSHR miss cycles 323system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12085186500 # number of demand (read+write) MSHR miss cycles 324system.cpu.dcache.demand_mshr_miss_latency::total 12085186500 # number of demand (read+write) MSHR miss cycles 325system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12085320500 # number of overall MSHR miss cycles 326system.cpu.dcache.overall_mshr_miss_latency::total 12085320500 # number of overall MSHR miss cycles 327system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses 328system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses 329system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses 330system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses 331system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005882 # mshr miss rate for SoftPFReq accesses 332system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005882 # mshr miss rate for SoftPFReq accesses 333system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 # mshr miss rate for demand accesses 334system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses 335system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses 336system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses 337system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12011.713135 # average ReadReq mshr miss latency 338system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12011.713135 # average ReadReq mshr miss latency 339system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27299.673883 # average WriteReq mshr miss latency 340system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27299.673883 # average WriteReq mshr miss latency 341system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44666.666667 # average SoftPFReq mshr miss latency 342system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44666.666667 # average SoftPFReq mshr miss latency 343system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12764.311704 # average overall mshr miss latency 344system.cpu.dcache.demand_avg_mshr_miss_latency::total 12764.311704 # average overall mshr miss latency 345system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12764.412789 # average overall mshr miss latency 346system.cpu.dcache.overall_avg_mshr_miss_latency::total 12764.412789 # average overall mshr miss latency 347system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 348system.cpu.icache.tags.replacements 2 # number of replacements 349system.cpu.icache.tags.tagsinuse 510.111710 # Cycle average of tags in use 350system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks. 351system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. 352system.cpu.icache.tags.avg_refs 180016.983306 # Average number of references to valid blocks. 353system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 354system.cpu.icache.tags.occ_blocks::cpu.inst 510.111710 # Average occupied blocks per requestor 355system.cpu.icache.tags.occ_percent::cpu.inst 0.249078 # Average percentage of cache occupancy 356system.cpu.icache.tags.occ_percent::total 0.249078 # Average percentage of cache occupancy 357system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id 358system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id 359system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 360system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 361system.cpu.icache.tags.age_task_id_blocks_1024::4 552 # Occupied blocks per task id 362system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id 363system.cpu.icache.tags.tag_accesses 215662143 # Number of tag accesses 364system.cpu.icache.tags.data_accesses 215662143 # Number of data accesses 365system.cpu.icache.ReadReq_hits::cpu.inst 107830173 # number of ReadReq hits 366system.cpu.icache.ReadReq_hits::total 107830173 # number of ReadReq hits 367system.cpu.icache.demand_hits::cpu.inst 107830173 # number of demand (read+write) hits 368system.cpu.icache.demand_hits::total 107830173 # number of demand (read+write) hits 369system.cpu.icache.overall_hits::cpu.inst 107830173 # number of overall hits 370system.cpu.icache.overall_hits::total 107830173 # number of overall hits 371system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses 372system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses 373system.cpu.icache.demand_misses::cpu.inst 599 # number of demand (read+write) misses 374system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses 375system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses 376system.cpu.icache.overall_misses::total 599 # number of overall misses 377system.cpu.icache.ReadReq_miss_latency::cpu.inst 36093000 # number of ReadReq miss cycles 378system.cpu.icache.ReadReq_miss_latency::total 36093000 # number of ReadReq miss cycles 379system.cpu.icache.demand_miss_latency::cpu.inst 36093000 # number of demand (read+write) miss cycles 380system.cpu.icache.demand_miss_latency::total 36093000 # number of demand (read+write) miss cycles 381system.cpu.icache.overall_miss_latency::cpu.inst 36093000 # number of overall miss cycles 382system.cpu.icache.overall_miss_latency::total 36093000 # number of overall miss cycles 383system.cpu.icache.ReadReq_accesses::cpu.inst 107830772 # number of ReadReq accesses(hits+misses) 384system.cpu.icache.ReadReq_accesses::total 107830772 # number of ReadReq accesses(hits+misses) 385system.cpu.icache.demand_accesses::cpu.inst 107830772 # number of demand (read+write) accesses 386system.cpu.icache.demand_accesses::total 107830772 # number of demand (read+write) accesses 387system.cpu.icache.overall_accesses::cpu.inst 107830772 # number of overall (read+write) accesses 388system.cpu.icache.overall_accesses::total 107830772 # number of overall (read+write) accesses 389system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses 390system.cpu.icache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses 391system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses 392system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses 393system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses 394system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses 395system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60255.425710 # average ReadReq miss latency 396system.cpu.icache.ReadReq_avg_miss_latency::total 60255.425710 # average ReadReq miss latency 397system.cpu.icache.demand_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency 398system.cpu.icache.demand_avg_miss_latency::total 60255.425710 # average overall miss latency 399system.cpu.icache.overall_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency 400system.cpu.icache.overall_avg_miss_latency::total 60255.425710 # average overall miss latency 401system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 402system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 403system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 404system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 405system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 406system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 407system.cpu.icache.fast_writes 0 # number of fast writes performed 408system.cpu.icache.cache_copies 0 # number of cache copies performed 409system.cpu.icache.writebacks::writebacks 2 # number of writebacks 410system.cpu.icache.writebacks::total 2 # number of writebacks 411system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses 412system.cpu.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses 413system.cpu.icache.demand_mshr_misses::cpu.inst 599 # number of demand (read+write) MSHR misses 414system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses 415system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses 416system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses 417system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35494000 # number of ReadReq MSHR miss cycles 418system.cpu.icache.ReadReq_mshr_miss_latency::total 35494000 # number of ReadReq MSHR miss cycles 419system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35494000 # number of demand (read+write) MSHR miss cycles 420system.cpu.icache.demand_mshr_miss_latency::total 35494000 # number of demand (read+write) MSHR miss cycles 421system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35494000 # number of overall MSHR miss cycles 422system.cpu.icache.overall_mshr_miss_latency::total 35494000 # number of overall MSHR miss cycles 423system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses 424system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses 425system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses 426system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses 427system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses 428system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses 429system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59255.425710 # average ReadReq mshr miss latency 430system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59255.425710 # average ReadReq mshr miss latency 431system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency 432system.cpu.icache.demand_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency 433system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency 434system.cpu.icache.overall_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency 435system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 436system.cpu.l2cache.tags.replacements 0 # number of replacements 437system.cpu.l2cache.tags.tagsinuse 9564.658425 # Cycle average of tags in use 438system.cpu.l2cache.tags.total_refs 1827433 # Total number of references to valid blocks. 439system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. 440system.cpu.l2cache.tags.avg_refs 119.260784 # Average number of references to valid blocks. 441system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 442system.cpu.l2cache.tags.occ_blocks::writebacks 8876.269803 # Average occupied blocks per requestor 443system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.164592 # Average occupied blocks per requestor 444system.cpu.l2cache.tags.occ_blocks::cpu.data 194.224030 # Average occupied blocks per requestor 445system.cpu.l2cache.tags.occ_percent::writebacks 0.270882 # Average percentage of cache occupancy 446system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015081 # Average percentage of cache occupancy 447system.cpu.l2cache.tags.occ_percent::cpu.data 0.005927 # Average percentage of cache occupancy 448system.cpu.l2cache.tags.occ_percent::total 0.291890 # Average percentage of cache occupancy 449system.cpu.l2cache.tags.occ_task_id_blocks::1024 15323 # Occupied blocks per task id 450system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 451system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id 452system.cpu.l2cache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id 453system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1473 # Occupied blocks per task id 454system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13704 # Occupied blocks per task id 455system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id 456system.cpu.l2cache.tags.tag_accesses 15181828 # Number of tag accesses 457system.cpu.l2cache.tags.data_accesses 15181828 # Number of data accesses 458system.cpu.l2cache.WritebackDirty_hits::writebacks 942334 # number of WritebackDirty hits 459system.cpu.l2cache.WritebackDirty_hits::total 942334 # number of WritebackDirty hits 460system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits 461system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits 462system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits 463system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits 464system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits 465system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits 466system.cpu.l2cache.ReadSharedReq_hits::cpu.data 899974 # number of ReadSharedReq hits 467system.cpu.l2cache.ReadSharedReq_hits::total 899974 # number of ReadSharedReq hits 468system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits 469system.cpu.l2cache.demand_hits::cpu.data 932035 # number of demand (read+write) hits 470system.cpu.l2cache.demand_hits::total 932057 # number of demand (read+write) hits 471system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits 472system.cpu.l2cache.overall_hits::cpu.data 932035 # number of overall hits 473system.cpu.l2cache.overall_hits::total 932057 # number of overall hits 474system.cpu.l2cache.ReadExReq_misses::cpu.data 14548 # number of ReadExReq misses 475system.cpu.l2cache.ReadExReq_misses::total 14548 # number of ReadExReq misses 476system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 577 # number of ReadCleanReq misses 477system.cpu.l2cache.ReadCleanReq_misses::total 577 # number of ReadCleanReq misses 478system.cpu.l2cache.ReadSharedReq_misses::cpu.data 215 # number of ReadSharedReq misses 479system.cpu.l2cache.ReadSharedReq_misses::total 215 # number of ReadSharedReq misses 480system.cpu.l2cache.demand_misses::cpu.inst 577 # number of demand (read+write) misses 481system.cpu.l2cache.demand_misses::cpu.data 14763 # number of demand (read+write) misses 482system.cpu.l2cache.demand_misses::total 15340 # number of demand (read+write) misses 483system.cpu.l2cache.overall_misses::cpu.inst 577 # number of overall misses 484system.cpu.l2cache.overall_misses::cpu.data 14763 # number of overall misses 485system.cpu.l2cache.overall_misses::total 15340 # number of overall misses 486system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 865856500 # number of ReadExReq miss cycles 487system.cpu.l2cache.ReadExReq_miss_latency::total 865856500 # number of ReadExReq miss cycles 488system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 34343500 # number of ReadCleanReq miss cycles 489system.cpu.l2cache.ReadCleanReq_miss_latency::total 34343500 # number of ReadCleanReq miss cycles 490system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12794500 # number of ReadSharedReq miss cycles 491system.cpu.l2cache.ReadSharedReq_miss_latency::total 12794500 # number of ReadSharedReq miss cycles 492system.cpu.l2cache.demand_miss_latency::cpu.inst 34343500 # number of demand (read+write) miss cycles 493system.cpu.l2cache.demand_miss_latency::cpu.data 878651000 # number of demand (read+write) miss cycles 494system.cpu.l2cache.demand_miss_latency::total 912994500 # number of demand (read+write) miss cycles 495system.cpu.l2cache.overall_miss_latency::cpu.inst 34343500 # number of overall miss cycles 496system.cpu.l2cache.overall_miss_latency::cpu.data 878651000 # number of overall miss cycles 497system.cpu.l2cache.overall_miss_latency::total 912994500 # number of overall miss cycles 498system.cpu.l2cache.WritebackDirty_accesses::writebacks 942334 # number of WritebackDirty accesses(hits+misses) 499system.cpu.l2cache.WritebackDirty_accesses::total 942334 # number of WritebackDirty accesses(hits+misses) 500system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) 501system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) 502system.cpu.l2cache.ReadExReq_accesses::cpu.data 46609 # number of ReadExReq accesses(hits+misses) 503system.cpu.l2cache.ReadExReq_accesses::total 46609 # number of ReadExReq accesses(hits+misses) 504system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 599 # number of ReadCleanReq accesses(hits+misses) 505system.cpu.l2cache.ReadCleanReq_accesses::total 599 # number of ReadCleanReq accesses(hits+misses) 506system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 900189 # number of ReadSharedReq accesses(hits+misses) 507system.cpu.l2cache.ReadSharedReq_accesses::total 900189 # number of ReadSharedReq accesses(hits+misses) 508system.cpu.l2cache.demand_accesses::cpu.inst 599 # number of demand (read+write) accesses 509system.cpu.l2cache.demand_accesses::cpu.data 946798 # number of demand (read+write) accesses 510system.cpu.l2cache.demand_accesses::total 947397 # number of demand (read+write) accesses 511system.cpu.l2cache.overall_accesses::cpu.inst 599 # number of overall (read+write) accesses 512system.cpu.l2cache.overall_accesses::cpu.data 946798 # number of overall (read+write) accesses 513system.cpu.l2cache.overall_accesses::total 947397 # number of overall (read+write) accesses 514system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.312129 # miss rate for ReadExReq accesses 515system.cpu.l2cache.ReadExReq_miss_rate::total 0.312129 # miss rate for ReadExReq accesses 516system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.963272 # miss rate for ReadCleanReq accesses 517system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.963272 # miss rate for ReadCleanReq accesses 518system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000239 # miss rate for ReadSharedReq accesses 519system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000239 # miss rate for ReadSharedReq accesses 520system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963272 # miss rate for demand accesses 521system.cpu.l2cache.demand_miss_rate::cpu.data 0.015593 # miss rate for demand accesses 522system.cpu.l2cache.demand_miss_rate::total 0.016192 # miss rate for demand accesses 523system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963272 # miss rate for overall accesses 524system.cpu.l2cache.overall_miss_rate::cpu.data 0.015593 # miss rate for overall accesses 525system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses 526system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59517.218862 # average ReadExReq miss latency 527system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59517.218862 # average ReadExReq miss latency 528system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59520.797227 # average ReadCleanReq miss latency 529system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59520.797227 # average ReadCleanReq miss latency 530system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59509.302326 # average ReadSharedReq miss latency 531system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59509.302326 # average ReadSharedReq miss latency 532system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59520.797227 # average overall miss latency 533system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency 534system.cpu.l2cache.demand_avg_miss_latency::total 59517.242503 # average overall miss latency 535system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59520.797227 # average overall miss latency 536system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency 537system.cpu.l2cache.overall_avg_miss_latency::total 59517.242503 # average overall miss latency 538system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 539system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 540system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 541system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 542system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 543system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 544system.cpu.l2cache.fast_writes 0 # number of fast writes performed 545system.cpu.l2cache.cache_copies 0 # number of cache copies performed 546system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses 547system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses 548system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 577 # number of ReadCleanReq MSHR misses 549system.cpu.l2cache.ReadCleanReq_mshr_misses::total 577 # number of ReadCleanReq MSHR misses 550system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 215 # number of ReadSharedReq MSHR misses 551system.cpu.l2cache.ReadSharedReq_mshr_misses::total 215 # number of ReadSharedReq MSHR misses 552system.cpu.l2cache.demand_mshr_misses::cpu.inst 577 # number of demand (read+write) MSHR misses 553system.cpu.l2cache.demand_mshr_misses::cpu.data 14763 # number of demand (read+write) MSHR misses 554system.cpu.l2cache.demand_mshr_misses::total 15340 # number of demand (read+write) MSHR misses 555system.cpu.l2cache.overall_mshr_misses::cpu.inst 577 # number of overall MSHR misses 556system.cpu.l2cache.overall_mshr_misses::cpu.data 14763 # number of overall MSHR misses 557system.cpu.l2cache.overall_mshr_misses::total 15340 # number of overall MSHR misses 558system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 720376500 # number of ReadExReq MSHR miss cycles 559system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 720376500 # number of ReadExReq MSHR miss cycles 560system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 28573500 # number of ReadCleanReq MSHR miss cycles 561system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 28573500 # number of ReadCleanReq MSHR miss cycles 562system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10644500 # number of ReadSharedReq MSHR miss cycles 563system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10644500 # number of ReadSharedReq MSHR miss cycles 564system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28573500 # number of demand (read+write) MSHR miss cycles 565system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 731021000 # number of demand (read+write) MSHR miss cycles 566system.cpu.l2cache.demand_mshr_miss_latency::total 759594500 # number of demand (read+write) MSHR miss cycles 567system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28573500 # number of overall MSHR miss cycles 568system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 731021000 # number of overall MSHR miss cycles 569system.cpu.l2cache.overall_mshr_miss_latency::total 759594500 # number of overall MSHR miss cycles 570system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses 571system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses 572system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for ReadCleanReq accesses 573system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.963272 # mshr miss rate for ReadCleanReq accesses 574system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000239 # mshr miss rate for ReadSharedReq accesses 575system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000239 # mshr miss rate for ReadSharedReq accesses 576system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for demand accesses 577system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for demand accesses 578system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 # mshr miss rate for demand accesses 579system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for overall accesses 580system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for overall accesses 581system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses 582system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49517.218862 # average ReadExReq mshr miss latency 583system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49517.218862 # average ReadExReq mshr miss latency 584system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49520.797227 # average ReadCleanReq mshr miss latency 585system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49520.797227 # average ReadCleanReq mshr miss latency 586system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49509.302326 # average ReadSharedReq mshr miss latency 587system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49509.302326 # average ReadSharedReq mshr miss latency 588system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency 589system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency 590system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency 591system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency 592system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency 593system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency 594system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 595system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter. 596system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data. 597system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 598system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 599system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 600system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 601system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution 602system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 # Transaction distribution	12sim_insts 90576862 # Number of instructions simulated 13sim_ops 91026991 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 36928 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 944832 # Number of bytes read from this memory 18system.physmem.bytes_read::total 981760 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 36928 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 36928 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 577 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 14763 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 250957 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 6420933 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 6671890 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 250957 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 250957 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 250957 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 6420933 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 6671890 # Total bandwidth to/from this memory (bytes/s) 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 34system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 36system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 41system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 42system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 43system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 44system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 45system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 46system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 47system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 48system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 49system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 50system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 51system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 52system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 53system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 54system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 55system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 56system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 57system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 58system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 59system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 60system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 61system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 62system.cpu.dtb.walker.walks 0 # Table walker walks requested 63system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 64system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 65system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 66system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 67system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 68system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 69system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 70system.cpu.dtb.inst_hits 0 # ITB inst hits 71system.cpu.dtb.inst_misses 0 # ITB inst misses 72system.cpu.dtb.read_hits 0 # DTB read hits 73system.cpu.dtb.read_misses 0 # DTB read misses 74system.cpu.dtb.write_hits 0 # DTB write hits 75system.cpu.dtb.write_misses 0 # DTB write misses 76system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 77system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 78system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 79system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 80system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 81system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 82system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 83system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 84system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 85system.cpu.dtb.read_accesses 0 # DTB read accesses 86system.cpu.dtb.write_accesses 0 # DTB write accesses 87system.cpu.dtb.inst_accesses 0 # ITB inst accesses 88system.cpu.dtb.hits 0 # DTB hits 89system.cpu.dtb.misses 0 # DTB misses 90system.cpu.dtb.accesses 0 # DTB accesses 91system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 92system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 93system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 94system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 95system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 96system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 99system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 100system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 101system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 102system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 103system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 104system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 105system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 106system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 107system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 108system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 109system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 110system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 111system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 112system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 113system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 114system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 115system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 116system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 117system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 118system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 119system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 120system.cpu.itb.walker.walks 0 # Table walker walks requested 121system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 122system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 123system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 124system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 125system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 126system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 127system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 128system.cpu.itb.inst_hits 0 # ITB inst hits 129system.cpu.itb.inst_misses 0 # ITB inst misses 130system.cpu.itb.read_hits 0 # DTB read hits 131system.cpu.itb.read_misses 0 # DTB read misses 132system.cpu.itb.write_hits 0 # DTB write hits 133system.cpu.itb.write_misses 0 # DTB write misses 134system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 135system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 136system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 137system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 138system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 139system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 140system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 141system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 142system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 143system.cpu.itb.read_accesses 0 # DTB read accesses 144system.cpu.itb.write_accesses 0 # DTB write accesses 145system.cpu.itb.inst_accesses 0 # ITB inst accesses 146system.cpu.itb.hits 0 # DTB hits 147system.cpu.itb.misses 0 # DTB misses 148system.cpu.itb.accesses 0 # DTB accesses 149system.cpu.workload.num_syscalls 442 # Number of system calls 150system.cpu.numCycles 294297439 # number of cpu cycles simulated 151system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 152system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 153system.cpu.committedInsts 90576862 # Number of instructions committed 154system.cpu.committedOps 91026991 # Number of ops (including micro ops) committed 155system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses 156system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses 157system.cpu.num_func_calls 112245 # number of times a function call or return occured 158system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls 159system.cpu.num_int_insts 72326352 # number of integer instructions 160system.cpu.num_fp_insts 48 # number of float instructions 161system.cpu.num_int_register_reads 124237033 # number of times the integer registers were read 162system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written 163system.cpu.num_fp_register_reads 54 # number of times the floating registers were read 164system.cpu.num_fp_register_writes 30 # number of times the floating registers were written 165system.cpu.num_cc_register_reads 339191621 # number of times the CC registers were read 166system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written 167system.cpu.num_mem_refs 27220755 # number of memory refs 168system.cpu.num_load_insts 22475911 # Number of load instructions 169system.cpu.num_store_insts 4744844 # Number of store instructions 170system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 171system.cpu.num_busy_cycles 294297438.998000 # Number of busy cycles 172system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 173system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 174system.cpu.Branches 18732305 # Number of branches fetched 175system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 176system.cpu.op_class::IntAlu 63822829 70.09% 70.09% # Class of executed instruction 177system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction 178system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction 179system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction 180system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction 181system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction 182system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction 183system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction 184system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction 185system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction 186system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction 187system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction 188system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction 189system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction 190system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction 191system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction 192system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction 193system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction 194system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction 195system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction 196system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction 197system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction 198system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction 199system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction 200system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction 201system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction 202system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction 203system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction 204system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction 205system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction 206system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction 207system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 208system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 209system.cpu.op_class::total 91054081 # Class of executed instruction 210system.cpu.dcache.tags.replacements 942702 # number of replacements 211system.cpu.dcache.tags.tagsinuse 3565.478025 # Cycle average of tags in use 212system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. 213system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. 214system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. 215system.cpu.dcache.tags.warmup_cycle 54453325500 # Cycle when the warmup percentage was hit. 216system.cpu.dcache.tags.occ_blocks::cpu.data 3565.478025 # Average occupied blocks per requestor 217system.cpu.dcache.tags.occ_percent::cpu.data 0.870478 # Average percentage of cache occupancy 218system.cpu.dcache.tags.occ_percent::total 0.870478 # Average percentage of cache occupancy 219system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 220system.cpu.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id 221system.cpu.dcache.tags.age_task_id_blocks_1024::1 1357 # Occupied blocks per task id 222system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id 223system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id 224system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 225system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses 226system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses 227system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits 228system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits 229system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits 230system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits 231system.cpu.dcache.SoftPFReq_hits::cpu.data 507 # number of SoftPFReq hits 232system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits 233system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits 234system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits 235system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 236system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits 237system.cpu.dcache.demand_hits::cpu.data 26245320 # number of demand (read+write) hits 238system.cpu.dcache.demand_hits::total 26245320 # number of demand (read+write) hits 239system.cpu.dcache.overall_hits::cpu.data 26245827 # number of overall hits 240system.cpu.dcache.overall_hits::total 26245827 # number of overall hits 241system.cpu.dcache.ReadReq_misses::cpu.data 900187 # number of ReadReq misses 242system.cpu.dcache.ReadReq_misses::total 900187 # number of ReadReq misses 243system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses 244system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses 245system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses 246system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses 247system.cpu.dcache.demand_misses::cpu.data 946796 # number of demand (read+write) misses 248system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses 249system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses 250system.cpu.dcache.overall_misses::total 946799 # number of overall misses 251system.cpu.dcache.ReadReq_miss_latency::cpu.data 11713009000 # number of ReadReq miss cycles 252system.cpu.dcache.ReadReq_miss_latency::total 11713009000 # number of ReadReq miss cycles 253system.cpu.dcache.WriteReq_miss_latency::cpu.data 1319019500 # number of WriteReq miss cycles 254system.cpu.dcache.WriteReq_miss_latency::total 1319019500 # number of WriteReq miss cycles 255system.cpu.dcache.demand_miss_latency::cpu.data 13032028500 # number of demand (read+write) miss cycles 256system.cpu.dcache.demand_miss_latency::total 13032028500 # number of demand (read+write) miss cycles 257system.cpu.dcache.overall_miss_latency::cpu.data 13032028500 # number of overall miss cycles 258system.cpu.dcache.overall_miss_latency::total 13032028500 # number of overall miss cycles 259system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses) 260system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses) 261system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 262system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 263system.cpu.dcache.SoftPFReq_accesses::cpu.data 510 # number of SoftPFReq accesses(hits+misses) 264system.cpu.dcache.SoftPFReq_accesses::total 510 # number of SoftPFReq accesses(hits+misses) 265system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 266system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 267system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 268system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) 269system.cpu.dcache.demand_accesses::cpu.data 27192116 # number of demand (read+write) accesses 270system.cpu.dcache.demand_accesses::total 27192116 # number of demand (read+write) accesses 271system.cpu.dcache.overall_accesses::cpu.data 27192626 # number of overall (read+write) accesses 272system.cpu.dcache.overall_accesses::total 27192626 # number of overall (read+write) accesses 273system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040085 # miss rate for ReadReq accesses 274system.cpu.dcache.ReadReq_miss_rate::total 0.040085 # miss rate for ReadReq accesses 275system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses 276system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses 277system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005882 # miss rate for SoftPFReq accesses 278system.cpu.dcache.SoftPFReq_miss_rate::total 0.005882 # miss rate for SoftPFReq accesses 279system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 # miss rate for demand accesses 280system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses 281system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses 282system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses 283system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13011.750892 # average ReadReq miss latency 284system.cpu.dcache.ReadReq_avg_miss_latency::total 13011.750892 # average ReadReq miss latency 285system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28299.673883 # average WriteReq miss latency 286system.cpu.dcache.WriteReq_avg_miss_latency::total 28299.673883 # average WriteReq miss latency 287system.cpu.dcache.demand_avg_miss_latency::cpu.data 13764.346808 # average overall miss latency 288system.cpu.dcache.demand_avg_miss_latency::total 13764.346808 # average overall miss latency 289system.cpu.dcache.overall_avg_miss_latency::cpu.data 13764.303194 # average overall miss latency 290system.cpu.dcache.overall_avg_miss_latency::total 13764.303194 # average overall miss latency 291system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 292system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 293system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 294system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 295system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 296system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 297system.cpu.dcache.fast_writes 0 # number of fast writes performed 298system.cpu.dcache.cache_copies 0 # number of cache copies performed 299system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks 300system.cpu.dcache.writebacks::total 942334 # number of writebacks 301system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 302system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 303system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 304system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 305system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 306system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits 307system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900186 # number of ReadReq MSHR misses 308system.cpu.dcache.ReadReq_mshr_misses::total 900186 # number of ReadReq MSHR misses 309system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses 310system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses 311system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 312system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 313system.cpu.dcache.demand_mshr_misses::cpu.data 946795 # number of demand (read+write) MSHR misses 314system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses 315system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses 316system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses 317system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10812776000 # number of ReadReq MSHR miss cycles 318system.cpu.dcache.ReadReq_mshr_miss_latency::total 10812776000 # number of ReadReq MSHR miss cycles 319system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1272410500 # number of WriteReq MSHR miss cycles 320system.cpu.dcache.WriteReq_mshr_miss_latency::total 1272410500 # number of WriteReq MSHR miss cycles 321system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 134000 # number of SoftPFReq MSHR miss cycles 322system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 134000 # number of SoftPFReq MSHR miss cycles 323system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12085186500 # number of demand (read+write) MSHR miss cycles 324system.cpu.dcache.demand_mshr_miss_latency::total 12085186500 # number of demand (read+write) MSHR miss cycles 325system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12085320500 # number of overall MSHR miss cycles 326system.cpu.dcache.overall_mshr_miss_latency::total 12085320500 # number of overall MSHR miss cycles 327system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses 328system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses 329system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses 330system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses 331system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005882 # mshr miss rate for SoftPFReq accesses 332system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005882 # mshr miss rate for SoftPFReq accesses 333system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 # mshr miss rate for demand accesses 334system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses 335system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses 336system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses 337system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12011.713135 # average ReadReq mshr miss latency 338system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12011.713135 # average ReadReq mshr miss latency 339system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27299.673883 # average WriteReq mshr miss latency 340system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27299.673883 # average WriteReq mshr miss latency 341system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44666.666667 # average SoftPFReq mshr miss latency 342system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44666.666667 # average SoftPFReq mshr miss latency 343system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12764.311704 # average overall mshr miss latency 344system.cpu.dcache.demand_avg_mshr_miss_latency::total 12764.311704 # average overall mshr miss latency 345system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12764.412789 # average overall mshr miss latency 346system.cpu.dcache.overall_avg_mshr_miss_latency::total 12764.412789 # average overall mshr miss latency 347system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 348system.cpu.icache.tags.replacements 2 # number of replacements 349system.cpu.icache.tags.tagsinuse 510.111710 # Cycle average of tags in use 350system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks. 351system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. 352system.cpu.icache.tags.avg_refs 180016.983306 # Average number of references to valid blocks. 353system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 354system.cpu.icache.tags.occ_blocks::cpu.inst 510.111710 # Average occupied blocks per requestor 355system.cpu.icache.tags.occ_percent::cpu.inst 0.249078 # Average percentage of cache occupancy 356system.cpu.icache.tags.occ_percent::total 0.249078 # Average percentage of cache occupancy 357system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id 358system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id 359system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 360system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 361system.cpu.icache.tags.age_task_id_blocks_1024::4 552 # Occupied blocks per task id 362system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id 363system.cpu.icache.tags.tag_accesses 215662143 # Number of tag accesses 364system.cpu.icache.tags.data_accesses 215662143 # Number of data accesses 365system.cpu.icache.ReadReq_hits::cpu.inst 107830173 # number of ReadReq hits 366system.cpu.icache.ReadReq_hits::total 107830173 # number of ReadReq hits 367system.cpu.icache.demand_hits::cpu.inst 107830173 # number of demand (read+write) hits 368system.cpu.icache.demand_hits::total 107830173 # number of demand (read+write) hits 369system.cpu.icache.overall_hits::cpu.inst 107830173 # number of overall hits 370system.cpu.icache.overall_hits::total 107830173 # number of overall hits 371system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses 372system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses 373system.cpu.icache.demand_misses::cpu.inst 599 # number of demand (read+write) misses 374system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses 375system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses 376system.cpu.icache.overall_misses::total 599 # number of overall misses 377system.cpu.icache.ReadReq_miss_latency::cpu.inst 36093000 # number of ReadReq miss cycles 378system.cpu.icache.ReadReq_miss_latency::total 36093000 # number of ReadReq miss cycles 379system.cpu.icache.demand_miss_latency::cpu.inst 36093000 # number of demand (read+write) miss cycles 380system.cpu.icache.demand_miss_latency::total 36093000 # number of demand (read+write) miss cycles 381system.cpu.icache.overall_miss_latency::cpu.inst 36093000 # number of overall miss cycles 382system.cpu.icache.overall_miss_latency::total 36093000 # number of overall miss cycles 383system.cpu.icache.ReadReq_accesses::cpu.inst 107830772 # number of ReadReq accesses(hits+misses) 384system.cpu.icache.ReadReq_accesses::total 107830772 # number of ReadReq accesses(hits+misses) 385system.cpu.icache.demand_accesses::cpu.inst 107830772 # number of demand (read+write) accesses 386system.cpu.icache.demand_accesses::total 107830772 # number of demand (read+write) accesses 387system.cpu.icache.overall_accesses::cpu.inst 107830772 # number of overall (read+write) accesses 388system.cpu.icache.overall_accesses::total 107830772 # number of overall (read+write) accesses 389system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses 390system.cpu.icache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses 391system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses 392system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses 393system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses 394system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses 395system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60255.425710 # average ReadReq miss latency 396system.cpu.icache.ReadReq_avg_miss_latency::total 60255.425710 # average ReadReq miss latency 397system.cpu.icache.demand_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency 398system.cpu.icache.demand_avg_miss_latency::total 60255.425710 # average overall miss latency 399system.cpu.icache.overall_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency 400system.cpu.icache.overall_avg_miss_latency::total 60255.425710 # average overall miss latency 401system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 402system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 403system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 404system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 405system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 406system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 407system.cpu.icache.fast_writes 0 # number of fast writes performed 408system.cpu.icache.cache_copies 0 # number of cache copies performed 409system.cpu.icache.writebacks::writebacks 2 # number of writebacks 410system.cpu.icache.writebacks::total 2 # number of writebacks 411system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses 412system.cpu.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses 413system.cpu.icache.demand_mshr_misses::cpu.inst 599 # number of demand (read+write) MSHR misses 414system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses 415system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses 416system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses 417system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35494000 # number of ReadReq MSHR miss cycles 418system.cpu.icache.ReadReq_mshr_miss_latency::total 35494000 # number of ReadReq MSHR miss cycles 419system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35494000 # number of demand (read+write) MSHR miss cycles 420system.cpu.icache.demand_mshr_miss_latency::total 35494000 # number of demand (read+write) MSHR miss cycles 421system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35494000 # number of overall MSHR miss cycles 422system.cpu.icache.overall_mshr_miss_latency::total 35494000 # number of overall MSHR miss cycles 423system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses 424system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses 425system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses 426system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses 427system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses 428system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses 429system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59255.425710 # average ReadReq mshr miss latency 430system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59255.425710 # average ReadReq mshr miss latency 431system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency 432system.cpu.icache.demand_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency 433system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency 434system.cpu.icache.overall_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency 435system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 436system.cpu.l2cache.tags.replacements 0 # number of replacements 437system.cpu.l2cache.tags.tagsinuse 9564.658425 # Cycle average of tags in use 438system.cpu.l2cache.tags.total_refs 1827433 # Total number of references to valid blocks. 439system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. 440system.cpu.l2cache.tags.avg_refs 119.260784 # Average number of references to valid blocks. 441system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 442system.cpu.l2cache.tags.occ_blocks::writebacks 8876.269803 # Average occupied blocks per requestor 443system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.164592 # Average occupied blocks per requestor 444system.cpu.l2cache.tags.occ_blocks::cpu.data 194.224030 # Average occupied blocks per requestor 445system.cpu.l2cache.tags.occ_percent::writebacks 0.270882 # Average percentage of cache occupancy 446system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015081 # Average percentage of cache occupancy 447system.cpu.l2cache.tags.occ_percent::cpu.data 0.005927 # Average percentage of cache occupancy 448system.cpu.l2cache.tags.occ_percent::total 0.291890 # Average percentage of cache occupancy 449system.cpu.l2cache.tags.occ_task_id_blocks::1024 15323 # Occupied blocks per task id 450system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 451system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id 452system.cpu.l2cache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id 453system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1473 # Occupied blocks per task id 454system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13704 # Occupied blocks per task id 455system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id 456system.cpu.l2cache.tags.tag_accesses 15181828 # Number of tag accesses 457system.cpu.l2cache.tags.data_accesses 15181828 # Number of data accesses 458system.cpu.l2cache.WritebackDirty_hits::writebacks 942334 # number of WritebackDirty hits 459system.cpu.l2cache.WritebackDirty_hits::total 942334 # number of WritebackDirty hits 460system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits 461system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits 462system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits 463system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits 464system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits 465system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits 466system.cpu.l2cache.ReadSharedReq_hits::cpu.data 899974 # number of ReadSharedReq hits 467system.cpu.l2cache.ReadSharedReq_hits::total 899974 # number of ReadSharedReq hits 468system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits 469system.cpu.l2cache.demand_hits::cpu.data 932035 # number of demand (read+write) hits 470system.cpu.l2cache.demand_hits::total 932057 # number of demand (read+write) hits 471system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits 472system.cpu.l2cache.overall_hits::cpu.data 932035 # number of overall hits 473system.cpu.l2cache.overall_hits::total 932057 # number of overall hits 474system.cpu.l2cache.ReadExReq_misses::cpu.data 14548 # number of ReadExReq misses 475system.cpu.l2cache.ReadExReq_misses::total 14548 # number of ReadExReq misses 476system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 577 # number of ReadCleanReq misses 477system.cpu.l2cache.ReadCleanReq_misses::total 577 # number of ReadCleanReq misses 478system.cpu.l2cache.ReadSharedReq_misses::cpu.data 215 # number of ReadSharedReq misses 479system.cpu.l2cache.ReadSharedReq_misses::total 215 # number of ReadSharedReq misses 480system.cpu.l2cache.demand_misses::cpu.inst 577 # number of demand (read+write) misses 481system.cpu.l2cache.demand_misses::cpu.data 14763 # number of demand (read+write) misses 482system.cpu.l2cache.demand_misses::total 15340 # number of demand (read+write) misses 483system.cpu.l2cache.overall_misses::cpu.inst 577 # number of overall misses 484system.cpu.l2cache.overall_misses::cpu.data 14763 # number of overall misses 485system.cpu.l2cache.overall_misses::total 15340 # number of overall misses 486system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 865856500 # number of ReadExReq miss cycles 487system.cpu.l2cache.ReadExReq_miss_latency::total 865856500 # number of ReadExReq miss cycles 488system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 34343500 # number of ReadCleanReq miss cycles 489system.cpu.l2cache.ReadCleanReq_miss_latency::total 34343500 # number of ReadCleanReq miss cycles 490system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12794500 # number of ReadSharedReq miss cycles 491system.cpu.l2cache.ReadSharedReq_miss_latency::total 12794500 # number of ReadSharedReq miss cycles 492system.cpu.l2cache.demand_miss_latency::cpu.inst 34343500 # number of demand (read+write) miss cycles 493system.cpu.l2cache.demand_miss_latency::cpu.data 878651000 # number of demand (read+write) miss cycles 494system.cpu.l2cache.demand_miss_latency::total 912994500 # number of demand (read+write) miss cycles 495system.cpu.l2cache.overall_miss_latency::cpu.inst 34343500 # number of overall miss cycles 496system.cpu.l2cache.overall_miss_latency::cpu.data 878651000 # number of overall miss cycles 497system.cpu.l2cache.overall_miss_latency::total 912994500 # number of overall miss cycles 498system.cpu.l2cache.WritebackDirty_accesses::writebacks 942334 # number of WritebackDirty accesses(hits+misses) 499system.cpu.l2cache.WritebackDirty_accesses::total 942334 # number of WritebackDirty accesses(hits+misses) 500system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) 501system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) 502system.cpu.l2cache.ReadExReq_accesses::cpu.data 46609 # number of ReadExReq accesses(hits+misses) 503system.cpu.l2cache.ReadExReq_accesses::total 46609 # number of ReadExReq accesses(hits+misses) 504system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 599 # number of ReadCleanReq accesses(hits+misses) 505system.cpu.l2cache.ReadCleanReq_accesses::total 599 # number of ReadCleanReq accesses(hits+misses) 506system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 900189 # number of ReadSharedReq accesses(hits+misses) 507system.cpu.l2cache.ReadSharedReq_accesses::total 900189 # number of ReadSharedReq accesses(hits+misses) 508system.cpu.l2cache.demand_accesses::cpu.inst 599 # number of demand (read+write) accesses 509system.cpu.l2cache.demand_accesses::cpu.data 946798 # number of demand (read+write) accesses 510system.cpu.l2cache.demand_accesses::total 947397 # number of demand (read+write) accesses 511system.cpu.l2cache.overall_accesses::cpu.inst 599 # number of overall (read+write) accesses 512system.cpu.l2cache.overall_accesses::cpu.data 946798 # number of overall (read+write) accesses 513system.cpu.l2cache.overall_accesses::total 947397 # number of overall (read+write) accesses 514system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.312129 # miss rate for ReadExReq accesses 515system.cpu.l2cache.ReadExReq_miss_rate::total 0.312129 # miss rate for ReadExReq accesses 516system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.963272 # miss rate for ReadCleanReq accesses 517system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.963272 # miss rate for ReadCleanReq accesses 518system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000239 # miss rate for ReadSharedReq accesses 519system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000239 # miss rate for ReadSharedReq accesses 520system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963272 # miss rate for demand accesses 521system.cpu.l2cache.demand_miss_rate::cpu.data 0.015593 # miss rate for demand accesses 522system.cpu.l2cache.demand_miss_rate::total 0.016192 # miss rate for demand accesses 523system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963272 # miss rate for overall accesses 524system.cpu.l2cache.overall_miss_rate::cpu.data 0.015593 # miss rate for overall accesses 525system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses 526system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59517.218862 # average ReadExReq miss latency 527system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59517.218862 # average ReadExReq miss latency 528system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59520.797227 # average ReadCleanReq miss latency 529system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59520.797227 # average ReadCleanReq miss latency 530system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59509.302326 # average ReadSharedReq miss latency 531system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59509.302326 # average ReadSharedReq miss latency 532system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59520.797227 # average overall miss latency 533system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency 534system.cpu.l2cache.demand_avg_miss_latency::total 59517.242503 # average overall miss latency 535system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59520.797227 # average overall miss latency 536system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency 537system.cpu.l2cache.overall_avg_miss_latency::total 59517.242503 # average overall miss latency 538system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 539system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 540system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 541system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 542system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 543system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 544system.cpu.l2cache.fast_writes 0 # number of fast writes performed 545system.cpu.l2cache.cache_copies 0 # number of cache copies performed 546system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses 547system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses 548system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 577 # number of ReadCleanReq MSHR misses 549system.cpu.l2cache.ReadCleanReq_mshr_misses::total 577 # number of ReadCleanReq MSHR misses 550system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 215 # number of ReadSharedReq MSHR misses 551system.cpu.l2cache.ReadSharedReq_mshr_misses::total 215 # number of ReadSharedReq MSHR misses 552system.cpu.l2cache.demand_mshr_misses::cpu.inst 577 # number of demand (read+write) MSHR misses 553system.cpu.l2cache.demand_mshr_misses::cpu.data 14763 # number of demand (read+write) MSHR misses 554system.cpu.l2cache.demand_mshr_misses::total 15340 # number of demand (read+write) MSHR misses 555system.cpu.l2cache.overall_mshr_misses::cpu.inst 577 # number of overall MSHR misses 556system.cpu.l2cache.overall_mshr_misses::cpu.data 14763 # number of overall MSHR misses 557system.cpu.l2cache.overall_mshr_misses::total 15340 # number of overall MSHR misses 558system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 720376500 # number of ReadExReq MSHR miss cycles 559system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 720376500 # number of ReadExReq MSHR miss cycles 560system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 28573500 # number of ReadCleanReq MSHR miss cycles 561system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 28573500 # number of ReadCleanReq MSHR miss cycles 562system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10644500 # number of ReadSharedReq MSHR miss cycles 563system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10644500 # number of ReadSharedReq MSHR miss cycles 564system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28573500 # number of demand (read+write) MSHR miss cycles 565system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 731021000 # number of demand (read+write) MSHR miss cycles 566system.cpu.l2cache.demand_mshr_miss_latency::total 759594500 # number of demand (read+write) MSHR miss cycles 567system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28573500 # number of overall MSHR miss cycles 568system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 731021000 # number of overall MSHR miss cycles 569system.cpu.l2cache.overall_mshr_miss_latency::total 759594500 # number of overall MSHR miss cycles 570system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses 571system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses 572system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for ReadCleanReq accesses 573system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.963272 # mshr miss rate for ReadCleanReq accesses 574system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000239 # mshr miss rate for ReadSharedReq accesses 575system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000239 # mshr miss rate for ReadSharedReq accesses 576system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for demand accesses 577system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for demand accesses 578system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 # mshr miss rate for demand accesses 579system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for overall accesses 580system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for overall accesses 581system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses 582system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49517.218862 # average ReadExReq mshr miss latency 583system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49517.218862 # average ReadExReq mshr miss latency 584system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49520.797227 # average ReadCleanReq mshr miss latency 585system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49520.797227 # average ReadCleanReq mshr miss latency 586system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49509.302326 # average ReadSharedReq mshr miss latency 587system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49509.302326 # average ReadSharedReq mshr miss latency 588system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency 589system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency 590system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency 591system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency 592system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency 593system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency 594system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 595system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter. 596system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data. 597system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 598system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 599system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 600system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 601system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution 602system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 # Transaction distribution
603system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution 604system.cpu.toL2Bus.trans_dist::CleanEvict 255 # Transaction distribution	603system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution 604system.cpu.toL2Bus.trans_dist::CleanEvict 368 # Transaction distribution
605system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution 606system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution 607system.cpu.toL2Bus.trans_dist::ReadCleanReq 599 # Transaction distribution 608system.cpu.toL2Bus.trans_dist::ReadSharedReq 900189 # Transaction distribution	605system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution 606system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution 607system.cpu.toL2Bus.trans_dist::ReadCleanReq 599 # Transaction distribution 608system.cpu.toL2Bus.trans_dist::ReadSharedReq 900189 # Transaction distribution
609system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1199 # Packet count per connected master and slave (bytes) 610system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2836185 # Packet count per connected master and slave (bytes) 611system.cpu.toL2Bus.pkt_count::total 2837384 # Packet count per connected master and slave (bytes) 612system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38400 # Cumulative packet size per connected master and slave (bytes)	609system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1200 # Packet count per connected master and slave (bytes) 610system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2836298 # Packet count per connected master and slave (bytes) 611system.cpu.toL2Bus.pkt_count::total 2837498 # Packet count per connected master and slave (bytes) 612system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38464 # Cumulative packet size per connected master and slave (bytes)
613system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes)	613system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes)
614system.cpu.toL2Bus.pkt_size::total 120942848 # Cumulative packet size per connected master and slave (bytes)	614system.cpu.toL2Bus.pkt_size::total 120942912 # Cumulative packet size per connected master and slave (bytes)
615system.cpu.toL2Bus.snoops 0 # Total snoops (count) 616system.cpu.toL2Bus.snoop_fanout::samples 947397 # Request fanout histogram 617system.cpu.toL2Bus.snoop_fanout::mean 0.000132 # Request fanout histogram 618system.cpu.toL2Bus.snoop_fanout::stdev 0.011486 # Request fanout histogram 619system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 620system.cpu.toL2Bus.snoop_fanout::0 947272 99.99% 99.99% # Request fanout histogram 621system.cpu.toL2Bus.snoop_fanout::1 125 0.01% 100.00% # Request fanout histogram 622system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 623system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 624system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 625system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 626system.cpu.toL2Bus.snoop_fanout::total 947397 # Request fanout histogram 627system.cpu.toL2Bus.reqLayer0.occupancy 1887386500 # Layer occupancy (ticks) 628system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 629system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks) 630system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 631system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks) 632system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) 633system.membus.trans_dist::ReadResp 792 # Transaction distribution 634system.membus.trans_dist::ReadExReq 14548 # Transaction distribution 635system.membus.trans_dist::ReadExResp 14548 # Transaction distribution 636system.membus.trans_dist::ReadSharedReq 792 # Transaction distribution 637system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes) 638system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes) 639system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes) 640system.membus.pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes) 641system.membus.snoops 0 # Total snoops (count) 642system.membus.snoop_fanout::samples 15340 # Request fanout histogram 643system.membus.snoop_fanout::mean 0 # Request fanout histogram 644system.membus.snoop_fanout::stdev 0 # Request fanout histogram 645system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 646system.membus.snoop_fanout::0 15340 100.00% 100.00% # Request fanout histogram 647system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 648system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 649system.membus.snoop_fanout::min_value 0 # Request fanout histogram 650system.membus.snoop_fanout::max_value 0 # Request fanout histogram 651system.membus.snoop_fanout::total 15340 # Request fanout histogram 652system.membus.reqLayer0.occupancy 15604500 # Layer occupancy (ticks) 653system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 654system.membus.respLayer1.occupancy 76700000 # Layer occupancy (ticks) 655system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 656 657---------- End Simulation Statistics ----------	615system.cpu.toL2Bus.snoops 0 # Total snoops (count) 616system.cpu.toL2Bus.snoop_fanout::samples 947397 # Request fanout histogram 617system.cpu.toL2Bus.snoop_fanout::mean 0.000132 # Request fanout histogram 618system.cpu.toL2Bus.snoop_fanout::stdev 0.011486 # Request fanout histogram 619system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 620system.cpu.toL2Bus.snoop_fanout::0 947272 99.99% 99.99% # Request fanout histogram 621system.cpu.toL2Bus.snoop_fanout::1 125 0.01% 100.00% # Request fanout histogram 622system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 623system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 624system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 625system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 626system.cpu.toL2Bus.snoop_fanout::total 947397 # Request fanout histogram 627system.cpu.toL2Bus.reqLayer0.occupancy 1887386500 # Layer occupancy (ticks) 628system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 629system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks) 630system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 631system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks) 632system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) 633system.membus.trans_dist::ReadResp 792 # Transaction distribution 634system.membus.trans_dist::ReadExReq 14548 # Transaction distribution 635system.membus.trans_dist::ReadExResp 14548 # Transaction distribution 636system.membus.trans_dist::ReadSharedReq 792 # Transaction distribution 637system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes) 638system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes) 639system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes) 640system.membus.pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes) 641system.membus.snoops 0 # Total snoops (count) 642system.membus.snoop_fanout::samples 15340 # Request fanout histogram 643system.membus.snoop_fanout::mean 0 # Request fanout histogram 644system.membus.snoop_fanout::stdev 0 # Request fanout histogram 645system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 646system.membus.snoop_fanout::0 15340 100.00% 100.00% # Request fanout histogram 647system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 648system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 649system.membus.snoop_fanout::min_value 0 # Request fanout histogram 650system.membus.snoop_fanout::max_value 0 # Request fanout histogram 651system.membus.snoop_fanout::total 15340 # Request fanout histogram 652system.membus.reqLayer0.occupancy 15604500 # Layer occupancy (ticks) 653system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 654system.membus.respLayer1.occupancy 76700000 # Layer occupancy (ticks) 655system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 656 657---------- End Simulation Statistics ----------