| stats.txt (11687:b3d5f0e9e258) | stats.txt (11731:c473ca7cc650) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000668 # Number of seconds simulated 4sim_ticks 668137500 # Number of ticks simulated 5final_tick 668137500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000667 # Number of seconds simulated 4sim_ticks 667407500 # Number of ticks simulated 5final_tick 667407500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 245703 # Simulator instruction rate (inst/s) 8host_op_rate 505252 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2451366703 # Simulator tick rate (ticks/s) 10host_mem_usage 1323744 # Number of bytes of host memory used 11host_seconds 0.27 # Real time elapsed on the host | 7host_inst_rate 72185 # Simulator instruction rate (inst/s) 8host_op_rate 148440 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 719412350 # Simulator tick rate (ticks/s) 10host_mem_usage 1308600 # Number of bytes of host memory used 11host_seconds 0.93 # Real time elapsed on the host |
| 12sim_insts 66963 # Number of instructions simulated 13sim_ops 137705 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 66963 # Number of instructions simulated 13sim_ops 137705 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 17system.mem_ctrls.bytes_read::dir_cntrl0 99264 # Number of bytes read from this memory 18system.mem_ctrls.bytes_read::total 99264 # Number of bytes read from this memory 19system.mem_ctrls.num_reads::dir_cntrl0 1551 # Number of read requests responded to by this memory 20system.mem_ctrls.num_reads::total 1551 # Number of read requests responded to by this memory 21system.mem_ctrls.bw_read::dir_cntrl0 148568221 # Total read bandwidth from this memory (bytes/s) 22system.mem_ctrls.bw_read::total 148568221 # Total read bandwidth from this memory (bytes/s) 23system.mem_ctrls.bw_total::dir_cntrl0 148568221 # Total bandwidth to/from this memory (bytes/s) 24system.mem_ctrls.bw_total::total 148568221 # Total bandwidth to/from this memory (bytes/s) 25system.mem_ctrls.readReqs 1551 # Number of read requests accepted | 16system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 17system.mem_ctrls.bytes_read::dir_cntrl0 99136 # Number of bytes read from this memory 18system.mem_ctrls.bytes_read::total 99136 # Number of bytes read from this memory 19system.mem_ctrls.num_reads::dir_cntrl0 1549 # Number of read requests responded to by this memory 20system.mem_ctrls.num_reads::total 1549 # Number of read requests responded to by this memory 21system.mem_ctrls.bw_read::dir_cntrl0 148538936 # Total read bandwidth from this memory (bytes/s) 22system.mem_ctrls.bw_read::total 148538936 # Total read bandwidth from this memory (bytes/s) 23system.mem_ctrls.bw_total::dir_cntrl0 148538936 # Total bandwidth to/from this memory (bytes/s) 24system.mem_ctrls.bw_total::total 148538936 # Total bandwidth to/from this memory (bytes/s) 25system.mem_ctrls.readReqs 1549 # Number of read requests accepted |
| 26system.mem_ctrls.writeReqs 0 # Number of write requests accepted | 26system.mem_ctrls.writeReqs 0 # Number of write requests accepted |
| 27system.mem_ctrls.readBursts 1551 # Number of DRAM read bursts, including those serviced by the write queue | 27system.mem_ctrls.readBursts 1549 # Number of DRAM read bursts, including those serviced by the write queue |
| 28system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 28system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 29system.mem_ctrls.bytesReadDRAM 99264 # Total number of bytes read from DRAM | 29system.mem_ctrls.bytesReadDRAM 99136 # Total number of bytes read from DRAM |
| 30system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue 31system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM | 30system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue 31system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM |
| 32system.mem_ctrls.bytesReadSys 99264 # Total read bytes from the system interface side | 32system.mem_ctrls.bytesReadSys 99136 # Total read bytes from the system interface side |
| 33system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side 34system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 35system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 36system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 37system.mem_ctrls.perBankRdBursts::0 122 # Per bank write bursts 38system.mem_ctrls.perBankRdBursts::1 192 # Per bank write bursts | 33system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side 34system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 35system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 36system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 37system.mem_ctrls.perBankRdBursts::0 122 # Per bank write bursts 38system.mem_ctrls.perBankRdBursts::1 192 # Per bank write bursts |
| 39system.mem_ctrls.perBankRdBursts::2 93 # Per bank write bursts | 39system.mem_ctrls.perBankRdBursts::2 91 # Per bank write bursts |
| 40system.mem_ctrls.perBankRdBursts::3 44 # Per bank write bursts 41system.mem_ctrls.perBankRdBursts::4 61 # Per bank write bursts 42system.mem_ctrls.perBankRdBursts::5 79 # Per bank write bursts 43system.mem_ctrls.perBankRdBursts::6 52 # Per bank write bursts 44system.mem_ctrls.perBankRdBursts::7 42 # Per bank write bursts 45system.mem_ctrls.perBankRdBursts::8 54 # Per bank write bursts 46system.mem_ctrls.perBankRdBursts::9 56 # Per bank write bursts 47system.mem_ctrls.perBankRdBursts::10 174 # Per bank write bursts --- 15 unchanged lines hidden (view full) --- 63system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts 64system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts 65system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts 66system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts 67system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts 68system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts 69system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry 70system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry | 40system.mem_ctrls.perBankRdBursts::3 44 # Per bank write bursts 41system.mem_ctrls.perBankRdBursts::4 61 # Per bank write bursts 42system.mem_ctrls.perBankRdBursts::5 79 # Per bank write bursts 43system.mem_ctrls.perBankRdBursts::6 52 # Per bank write bursts 44system.mem_ctrls.perBankRdBursts::7 42 # Per bank write bursts 45system.mem_ctrls.perBankRdBursts::8 54 # Per bank write bursts 46system.mem_ctrls.perBankRdBursts::9 56 # Per bank write bursts 47system.mem_ctrls.perBankRdBursts::10 174 # Per bank write bursts --- 15 unchanged lines hidden (view full) --- 63system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts 64system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts 65system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts 66system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts 67system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts 68system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts 69system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry 70system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry |
| 71system.mem_ctrls.totGap 667904000 # Total gap between requests | 71system.mem_ctrls.totGap 667174000 # Total gap between requests |
| 72system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) 73system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) 74system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) 75system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) 76system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) 77system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) | 72system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) 73system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) 74system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) 75system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) 76system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) 77system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) |
| 78system.mem_ctrls.readPktSize::6 1551 # Read request sizes (log2) | 78system.mem_ctrls.readPktSize::6 1549 # Read request sizes (log2) |
| 79system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) 80system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) 81system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) 82system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) 83system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) 84system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) 85system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) | 79system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) 80system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) 81system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) 82system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) 83system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) 84system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) 85system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) |
| 86system.mem_ctrls.rdQLenPdf::0 1542 # What read queue length does an incoming req see | 86system.mem_ctrls.rdQLenPdf::0 1540 # What read queue length does an incoming req see |
| 87system.mem_ctrls.rdQLenPdf::1 2 # What read queue length does an incoming req see 88system.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see 89system.mem_ctrls.rdQLenPdf::3 1 # What read queue length does an incoming req see | 87system.mem_ctrls.rdQLenPdf::1 2 # What read queue length does an incoming req see 88system.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see 89system.mem_ctrls.rdQLenPdf::3 1 # What read queue length does an incoming req see |
| 90system.mem_ctrls.rdQLenPdf::4 1 # What read queue length does an incoming req see | 90system.mem_ctrls.rdQLenPdf::4 2 # What read queue length does an incoming req see |
| 91system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see | 91system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see |
| 92system.mem_ctrls.rdQLenPdf::6 2 # What read queue length does an incoming req see | 92system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see |
| 93system.mem_ctrls.rdQLenPdf::7 1 # What read queue length does an incoming req see 94system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see 95system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see 96system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see 97system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see 98system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see 99system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see 100system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see --- 74 unchanged lines hidden (view full) --- 175system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see 176system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see 177system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see 178system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see 179system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see 180system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see 181system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see 182system.mem_ctrls.bytesPerActivate::samples 484 # Bytes accessed per row activation | 93system.mem_ctrls.rdQLenPdf::7 1 # What read queue length does an incoming req see 94system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see 95system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see 96system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see 97system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see 98system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see 99system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see 100system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see --- 74 unchanged lines hidden (view full) --- 175system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see 176system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see 177system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see 178system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see 179system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see 180system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see 181system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see 182system.mem_ctrls.bytesPerActivate::samples 484 # Bytes accessed per row activation |
| 183system.mem_ctrls.bytesPerActivate::mean 203.636364 # Bytes accessed per row activation 184system.mem_ctrls.bytesPerActivate::gmean 145.087483 # Bytes accessed per row activation 185system.mem_ctrls.bytesPerActivate::stdev 194.740960 # Bytes accessed per row activation | 183system.mem_ctrls.bytesPerActivate::mean 203.371901 # Bytes accessed per row activation 184system.mem_ctrls.bytesPerActivate::gmean 144.930715 # Bytes accessed per row activation 185system.mem_ctrls.bytesPerActivate::stdev 194.713066 # Bytes accessed per row activation |
| 186system.mem_ctrls.bytesPerActivate::0-127 177 36.57% 36.57% # Bytes accessed per row activation | 186system.mem_ctrls.bytesPerActivate::0-127 177 36.57% 36.57% # Bytes accessed per row activation |
| 187system.mem_ctrls.bytesPerActivate::128-255 167 34.50% 71.07% # Bytes accessed per row activation 188system.mem_ctrls.bytesPerActivate::256-383 64 13.22% 84.30% # Bytes accessed per row activation | 187system.mem_ctrls.bytesPerActivate::128-255 168 34.71% 71.28% # Bytes accessed per row activation 188system.mem_ctrls.bytesPerActivate::256-383 63 13.02% 84.30% # Bytes accessed per row activation |
| 189system.mem_ctrls.bytesPerActivate::384-511 29 5.99% 90.29% # Bytes accessed per row activation | 189system.mem_ctrls.bytesPerActivate::384-511 29 5.99% 90.29% # Bytes accessed per row activation |
| 190system.mem_ctrls.bytesPerActivate::512-639 20 4.13% 94.42% # Bytes accessed per row activation 191system.mem_ctrls.bytesPerActivate::640-767 10 2.07% 96.49% # Bytes accessed per row activation | 190system.mem_ctrls.bytesPerActivate::512-639 19 3.93% 94.21% # Bytes accessed per row activation 191system.mem_ctrls.bytesPerActivate::640-767 11 2.27% 96.49% # Bytes accessed per row activation |
| 192system.mem_ctrls.bytesPerActivate::768-895 10 2.07% 98.55% # Bytes accessed per row activation 193system.mem_ctrls.bytesPerActivate::896-1023 2 0.41% 98.97% # Bytes accessed per row activation 194system.mem_ctrls.bytesPerActivate::1024-1151 5 1.03% 100.00% # Bytes accessed per row activation 195system.mem_ctrls.bytesPerActivate::total 484 # Bytes accessed per row activation | 192system.mem_ctrls.bytesPerActivate::768-895 10 2.07% 98.55% # Bytes accessed per row activation 193system.mem_ctrls.bytesPerActivate::896-1023 2 0.41% 98.97% # Bytes accessed per row activation 194system.mem_ctrls.bytesPerActivate::1024-1151 5 1.03% 100.00% # Bytes accessed per row activation 195system.mem_ctrls.bytesPerActivate::total 484 # Bytes accessed per row activation |
| 196system.mem_ctrls.totQLat 31097995 # Total ticks spent queuing 197system.mem_ctrls.totMemAccLat 60179245 # Total ticks spent from burst creation until serviced by the DRAM 198system.mem_ctrls.totBusLat 7755000 # Total ticks spent in databus transfers 199system.mem_ctrls.avgQLat 20050.29 # Average queueing delay per DRAM burst | 196system.mem_ctrls.totQLat 31625750 # Total ticks spent queuing 197system.mem_ctrls.totMemAccLat 60669500 # Total ticks spent from burst creation until serviced by the DRAM 198system.mem_ctrls.totBusLat 7745000 # Total ticks spent in databus transfers 199system.mem_ctrls.avgQLat 20416.88 # Average queueing delay per DRAM burst |
| 200system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst | 200system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 201system.mem_ctrls.avgMemAccLat 38800.29 # Average memory access latency per DRAM burst 202system.mem_ctrls.avgRdBW 148.57 # Average DRAM read bandwidth in MiByte/s | 201system.mem_ctrls.avgMemAccLat 39166.88 # Average memory access latency per DRAM burst 202system.mem_ctrls.avgRdBW 148.54 # Average DRAM read bandwidth in MiByte/s |
| 203system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 203system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 204system.mem_ctrls.avgRdBWSys 148.57 # Average system read bandwidth in MiByte/s | 204system.mem_ctrls.avgRdBWSys 148.54 # Average system read bandwidth in MiByte/s |
| 205system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 206system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 207system.mem_ctrls.busUtil 1.16 # Data bus utilization in percentage 208system.mem_ctrls.busUtilRead 1.16 # Data bus utilization in percentage for reads 209system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes 210system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing 211system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing | 205system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 206system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 207system.mem_ctrls.busUtil 1.16 # Data bus utilization in percentage 208system.mem_ctrls.busUtilRead 1.16 # Data bus utilization in percentage for reads 209system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes 210system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing 211system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 212system.mem_ctrls.readRowHits 1062 # Number of row buffer hits during reads | 212system.mem_ctrls.readRowHits 1060 # Number of row buffer hits during reads |
| 213system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes | 213system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes |
| 214system.mem_ctrls.readRowHitRate 68.47 # Row buffer hit rate for reads | 214system.mem_ctrls.readRowHitRate 68.43 # Row buffer hit rate for reads |
| 215system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes | 215system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes |
| 216system.mem_ctrls.avgGap 430627.98 # Average gap between requests 217system.mem_ctrls.pageHitRate 68.47 # Row buffer hit rate, read and write combined | 216system.mem_ctrls.avgGap 430712.72 # Average gap between requests 217system.mem_ctrls.pageHitRate 68.43 # Row buffer hit rate, read and write combined |
| 218system.mem_ctrls_0.actEnergy 1320900 # Energy for activate commands per rank (pJ) 219system.mem_ctrls_0.preEnergy 694485 # Energy for precharge commands per rank (pJ) | 218system.mem_ctrls_0.actEnergy 1320900 # Energy for activate commands per rank (pJ) 219system.mem_ctrls_0.preEnergy 694485 # Energy for precharge commands per rank (pJ) |
| 220system.mem_ctrls_0.readEnergy 4890900 # Energy for read commands per rank (pJ) | 220system.mem_ctrls_0.readEnergy 4876620 # Energy for read commands per rank (pJ) |
| 221system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) 222system.mem_ctrls_0.refreshEnergy 51629760.000000 # Energy for refresh commands per rank (pJ) | 221system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) 222system.mem_ctrls_0.refreshEnergy 51629760.000000 # Energy for refresh commands per rank (pJ) |
| 223system.mem_ctrls_0.actBackEnergy 18618480 # Energy for active background per rank (pJ) | 223system.mem_ctrls_0.actBackEnergy 18588840 # Energy for active background per rank (pJ) |
| 224system.mem_ctrls_0.preBackEnergy 1670400 # Energy for precharge background per rank (pJ) | 224system.mem_ctrls_0.preBackEnergy 1670400 # Energy for precharge background per rank (pJ) |
| 225system.mem_ctrls_0.actPowerDownEnergy 210199470 # Energy for active power-down per rank (pJ) 226system.mem_ctrls_0.prePowerDownEnergy 42511680 # Energy for precharge power-down per rank (pJ) 227system.mem_ctrls_0.selfRefreshEnergy 15622140 # Energy for self refresh per rank (pJ) 228system.mem_ctrls_0.totalEnergy 347158215 # Total energy per rank (pJ) 229system.mem_ctrls_0.averagePower 519.590975 # Core power per rank (mW) 230system.mem_ctrls_0.totalIdleTime 622801252 # Total Idle time Per DRAM Rank | 225system.mem_ctrls_0.actPowerDownEnergy 210561990 # Energy for active power-down per rank (pJ) 226system.mem_ctrls_0.prePowerDownEnergy 42231360 # Energy for precharge power-down per rank (pJ) 227system.mem_ctrls_0.selfRefreshEnergy 15446940 # Energy for self refresh per rank (pJ) 228system.mem_ctrls_0.totalEnergy 347021295 # Total energy per rank (pJ) 229system.mem_ctrls_0.averagePower 519.954143 # Core power per rank (mW) 230system.mem_ctrls_0.totalIdleTime 622134250 # Total Idle time Per DRAM Rank |
| 231system.mem_ctrls_0.memoryStateTime::IDLE 2030000 # Time in different power states 232system.mem_ctrls_0.memoryStateTime::REF 21876000 # Time in different power states | 231system.mem_ctrls_0.memoryStateTime::IDLE 2030000 # Time in different power states 232system.mem_ctrls_0.memoryStateTime::REF 21876000 # Time in different power states |
| 233system.mem_ctrls_0.memoryStateTime::SREF 51287000 # Time in different power states 234system.mem_ctrls_0.memoryStateTime::PRE_PDN 110705750 # Time in different power states 235system.mem_ctrls_0.memoryStateTime::ACT 21255248 # Time in different power states 236system.mem_ctrls_0.memoryStateTime::ACT_PDN 460983502 # Time in different power states | 233system.mem_ctrls_0.memoryStateTime::SREF 50557000 # Time in different power states 234system.mem_ctrls_0.memoryStateTime::PRE_PDN 109975750 # Time in different power states 235system.mem_ctrls_0.memoryStateTime::ACT 21192250 # Time in different power states 236system.mem_ctrls_0.memoryStateTime::ACT_PDN 461776500 # Time in different power states |
| 237system.mem_ctrls_1.actEnergy 2170560 # Energy for activate commands per rank (pJ) 238system.mem_ctrls_1.preEnergy 1142295 # Energy for precharge commands per rank (pJ) 239system.mem_ctrls_1.readEnergy 6183240 # Energy for read commands per rank (pJ) 240system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) 241system.mem_ctrls_1.refreshEnergy 52244400.000000 # Energy for refresh commands per rank (pJ) | 237system.mem_ctrls_1.actEnergy 2170560 # Energy for activate commands per rank (pJ) 238system.mem_ctrls_1.preEnergy 1142295 # Energy for precharge commands per rank (pJ) 239system.mem_ctrls_1.readEnergy 6183240 # Energy for read commands per rank (pJ) 240system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) 241system.mem_ctrls_1.refreshEnergy 52244400.000000 # Energy for refresh commands per rank (pJ) |
| 242system.mem_ctrls_1.actBackEnergy 21589320 # Energy for active background per rank (pJ) | 242system.mem_ctrls_1.actBackEnergy 21584190 # Energy for active background per rank (pJ) |
| 243system.mem_ctrls_1.preBackEnergy 1299360 # Energy for precharge background per rank (pJ) | 243system.mem_ctrls_1.preBackEnergy 1299360 # Energy for precharge background per rank (pJ) |
| 244system.mem_ctrls_1.actPowerDownEnergy 243172830 # Energy for active power-down per rank (pJ) 245system.mem_ctrls_1.prePowerDownEnergy 28283040 # Energy for precharge power-down per rank (pJ) 246system.mem_ctrls_1.selfRefreshEnergy 3067740 # Energy for self refresh per rank (pJ) 247system.mem_ctrls_1.totalEnergy 359152785 # Total energy per rank (pJ) 248system.mem_ctrls_1.averagePower 537.543223 # Core power per rank (mW) 249system.mem_ctrls_1.totalIdleTime 616852750 # Total Idle time Per DRAM Rank | 244system.mem_ctrls_1.actPowerDownEnergy 243510840 # Energy for active power-down per rank (pJ) 245system.mem_ctrls_1.prePowerDownEnergy 28002720 # Energy for precharge power-down per rank (pJ) 246system.mem_ctrls_1.selfRefreshEnergy 2892540 # Energy for self refresh per rank (pJ) 247system.mem_ctrls_1.totalEnergy 359030145 # Total energy per rank (pJ) 248system.mem_ctrls_1.averagePower 537.947423 # Core power per rank (mW) 249system.mem_ctrls_1.totalIdleTime 616133750 # Total Idle time Per DRAM Rank |
| 250system.mem_ctrls_1.memoryStateTime::IDLE 980000 # Time in different power states 251system.mem_ctrls_1.memoryStateTime::REF 22106000 # Time in different power states | 250system.mem_ctrls_1.memoryStateTime::IDLE 980000 # Time in different power states 251system.mem_ctrls_1.memoryStateTime::REF 22106000 # Time in different power states |
| 252system.mem_ctrls_1.memoryStateTime::SREF 10481250 # Time in different power states 253system.mem_ctrls_1.memoryStateTime::PRE_PDN 73643500 # Time in different power states 254system.mem_ctrls_1.memoryStateTime::ACT 27629000 # Time in different power states 255system.mem_ctrls_1.memoryStateTime::ACT_PDN 533297750 # Time in different power states | 252system.mem_ctrls_1.memoryStateTime::SREF 9751250 # Time in different power states 253system.mem_ctrls_1.memoryStateTime::PRE_PDN 72913500 # Time in different power states 254system.mem_ctrls_1.memoryStateTime::ACT 27618000 # Time in different power states 255system.mem_ctrls_1.memoryStateTime::ACT_PDN 534038750 # Time in different power states |
| 256system.ruby.clk_domain.clock 500 # Clock period in ticks | 256system.ruby.clk_domain.clock 500 # Clock period in ticks |
| 257system.ruby.phys_mem.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states | 257system.ruby.phys_mem.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states |
| 258system.ruby.phys_mem.bytes_read::cpu0.inst 696760 # Number of bytes read from this memory 259system.ruby.phys_mem.bytes_read::cpu0.data 119832 # Number of bytes read from this memory | 258system.ruby.phys_mem.bytes_read::cpu0.inst 696760 # Number of bytes read from this memory 259system.ruby.phys_mem.bytes_read::cpu0.data 119832 # Number of bytes read from this memory |
| 260system.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 3280 # Number of bytes read from this memory 261system.ruby.phys_mem.bytes_read::cpu1.CUs1.ComputeUnit 3280 # Number of bytes read from this memory 262system.ruby.phys_mem.bytes_read::total 823152 # Number of bytes read from this memory | 260system.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 2856 # Number of bytes read from this memory 261system.ruby.phys_mem.bytes_read::cpu1.CUs1.ComputeUnit 2856 # Number of bytes read from this memory 262system.ruby.phys_mem.bytes_read::total 822304 # Number of bytes read from this memory |
| 263system.ruby.phys_mem.bytes_inst_read::cpu0.inst 696760 # Number of instructions bytes read from this memory | 263system.ruby.phys_mem.bytes_inst_read::cpu0.inst 696760 # Number of instructions bytes read from this memory |
| 264system.ruby.phys_mem.bytes_inst_read::cpu1.CUs0.ComputeUnit 2000 # Number of instructions bytes read from this memory 265system.ruby.phys_mem.bytes_inst_read::cpu1.CUs1.ComputeUnit 2000 # Number of instructions bytes read from this memory 266system.ruby.phys_mem.bytes_inst_read::total 700760 # Number of instructions bytes read from this memory | 264system.ruby.phys_mem.bytes_inst_read::cpu1.CUs0.ComputeUnit 1576 # Number of instructions bytes read from this memory 265system.ruby.phys_mem.bytes_inst_read::cpu1.CUs1.ComputeUnit 1576 # Number of instructions bytes read from this memory 266system.ruby.phys_mem.bytes_inst_read::total 699912 # Number of instructions bytes read from this memory |
| 267system.ruby.phys_mem.bytes_written::cpu0.data 72767 # Number of bytes written to this memory 268system.ruby.phys_mem.bytes_written::cpu1.CUs0.ComputeUnit 256 # Number of bytes written to this memory 269system.ruby.phys_mem.bytes_written::cpu1.CUs1.ComputeUnit 256 # Number of bytes written to this memory 270system.ruby.phys_mem.bytes_written::total 73279 # Number of bytes written to this memory 271system.ruby.phys_mem.num_reads::cpu0.inst 87095 # Number of read requests responded to by this memory 272system.ruby.phys_mem.num_reads::cpu0.data 16686 # Number of read requests responded to by this memory | 267system.ruby.phys_mem.bytes_written::cpu0.data 72767 # Number of bytes written to this memory 268system.ruby.phys_mem.bytes_written::cpu1.CUs0.ComputeUnit 256 # Number of bytes written to this memory 269system.ruby.phys_mem.bytes_written::cpu1.CUs1.ComputeUnit 256 # Number of bytes written to this memory 270system.ruby.phys_mem.bytes_written::total 73279 # Number of bytes written to this memory 271system.ruby.phys_mem.num_reads::cpu0.inst 87095 # Number of read requests responded to by this memory 272system.ruby.phys_mem.num_reads::cpu0.data 16686 # Number of read requests responded to by this memory |
| 273system.ruby.phys_mem.num_reads::cpu1.CUs0.ComputeUnit 555 # Number of read requests responded to by this memory 274system.ruby.phys_mem.num_reads::cpu1.CUs1.ComputeUnit 555 # Number of read requests responded to by this memory 275system.ruby.phys_mem.num_reads::total 104891 # Number of read requests responded to by this memory | 273system.ruby.phys_mem.num_reads::cpu1.CUs0.ComputeUnit 547 # Number of read requests responded to by this memory 274system.ruby.phys_mem.num_reads::cpu1.CUs1.ComputeUnit 547 # Number of read requests responded to by this memory 275system.ruby.phys_mem.num_reads::total 104875 # Number of read requests responded to by this memory |
| 276system.ruby.phys_mem.num_writes::cpu0.data 10422 # Number of write requests responded to by this memory 277system.ruby.phys_mem.num_writes::cpu1.CUs0.ComputeUnit 256 # Number of write requests responded to by this memory 278system.ruby.phys_mem.num_writes::cpu1.CUs1.ComputeUnit 256 # Number of write requests responded to by this memory 279system.ruby.phys_mem.num_writes::total 10934 # Number of write requests responded to by this memory | 276system.ruby.phys_mem.num_writes::cpu0.data 10422 # Number of write requests responded to by this memory 277system.ruby.phys_mem.num_writes::cpu1.CUs0.ComputeUnit 256 # Number of write requests responded to by this memory 278system.ruby.phys_mem.num_writes::cpu1.CUs1.ComputeUnit 256 # Number of write requests responded to by this memory 279system.ruby.phys_mem.num_writes::total 10934 # Number of write requests responded to by this memory |
| 280system.ruby.phys_mem.bw_read::cpu0.inst 1042839236 # Total read bandwidth from this memory (bytes/s) 281system.ruby.phys_mem.bw_read::cpu0.data 179352304 # Total read bandwidth from this memory (bytes/s) 282system.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit 4909169 # Total read bandwidth from this memory (bytes/s) 283system.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit 4909169 # Total read bandwidth from this memory (bytes/s) 284system.ruby.phys_mem.bw_read::total 1232009878 # Total read bandwidth from this memory (bytes/s) 285system.ruby.phys_mem.bw_inst_read::cpu0.inst 1042839236 # Instruction read bandwidth from this memory (bytes/s) 286system.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit 2993396 # Instruction read bandwidth from this memory (bytes/s) 287system.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit 2993396 # Instruction read bandwidth from this memory (bytes/s) 288system.ruby.phys_mem.bw_inst_read::total 1048826028 # Instruction read bandwidth from this memory (bytes/s) 289system.ruby.phys_mem.bw_write::cpu0.data 108910217 # Write bandwidth from this memory (bytes/s) 290system.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit 383155 # Write bandwidth from this memory (bytes/s) 291system.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit 383155 # Write bandwidth from this memory (bytes/s) 292system.ruby.phys_mem.bw_write::total 109676526 # Write bandwidth from this memory (bytes/s) 293system.ruby.phys_mem.bw_total::cpu0.inst 1042839236 # Total bandwidth to/from this memory (bytes/s) 294system.ruby.phys_mem.bw_total::cpu0.data 288262521 # Total bandwidth to/from this memory (bytes/s) 295system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 5292324 # Total bandwidth to/from this memory (bytes/s) 296system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 5292324 # Total bandwidth to/from this memory (bytes/s) 297system.ruby.phys_mem.bw_total::total 1341686404 # Total bandwidth to/from this memory (bytes/s) 298system.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 299system.ruby.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states | 280system.ruby.phys_mem.bw_read::cpu0.inst 1043979877 # Total read bandwidth from this memory (bytes/s) 281system.ruby.phys_mem.bw_read::cpu0.data 179548477 # Total read bandwidth from this memory (bytes/s) 282system.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit 4279245 # Total read bandwidth from this memory (bytes/s) 283system.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit 4279245 # Total read bandwidth from this memory (bytes/s) 284system.ruby.phys_mem.bw_read::total 1232086843 # Total read bandwidth from this memory (bytes/s) 285system.ruby.phys_mem.bw_inst_read::cpu0.inst 1043979877 # Instruction read bandwidth from this memory (bytes/s) 286system.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit 2361376 # Instruction read bandwidth from this memory (bytes/s) 287system.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit 2361376 # Instruction read bandwidth from this memory (bytes/s) 288system.ruby.phys_mem.bw_inst_read::total 1048702629 # Instruction read bandwidth from this memory (bytes/s) 289system.ruby.phys_mem.bw_write::cpu0.data 109029341 # Write bandwidth from this memory (bytes/s) 290system.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit 383574 # Write bandwidth from this memory (bytes/s) 291system.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit 383574 # Write bandwidth from this memory (bytes/s) 292system.ruby.phys_mem.bw_write::total 109796489 # Write bandwidth from this memory (bytes/s) 293system.ruby.phys_mem.bw_total::cpu0.inst 1043979877 # Total bandwidth to/from this memory (bytes/s) 294system.ruby.phys_mem.bw_total::cpu0.data 288577818 # Total bandwidth to/from this memory (bytes/s) 295system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 4662818 # Total bandwidth to/from this memory (bytes/s) 296system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 4662818 # Total bandwidth to/from this memory (bytes/s) 297system.ruby.phys_mem.bw_total::total 1341883332 # Total bandwidth to/from this memory (bytes/s) 298system.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 299system.ruby.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states |
| 300system.ruby.outstanding_req_hist_seqr::bucket_size 1 301system.ruby.outstanding_req_hist_seqr::max_bucket 9 302system.ruby.outstanding_req_hist_seqr::samples 114203 303system.ruby.outstanding_req_hist_seqr::mean 1.000035 304system.ruby.outstanding_req_hist_seqr::gmean 1.000024 305system.ruby.outstanding_req_hist_seqr::stdev 0.005918 306system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 114199 100.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 307system.ruby.outstanding_req_hist_seqr::total 114203 308system.ruby.outstanding_req_hist_coalsr::bucket_size 1 309system.ruby.outstanding_req_hist_coalsr::max_bucket 9 310system.ruby.outstanding_req_hist_coalsr::samples 27 | 300system.ruby.outstanding_req_hist_seqr::bucket_size 1 301system.ruby.outstanding_req_hist_seqr::max_bucket 9 302system.ruby.outstanding_req_hist_seqr::samples 114203 303system.ruby.outstanding_req_hist_seqr::mean 1.000035 304system.ruby.outstanding_req_hist_seqr::gmean 1.000024 305system.ruby.outstanding_req_hist_seqr::stdev 0.005918 306system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 114199 100.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 307system.ruby.outstanding_req_hist_seqr::total 114203 308system.ruby.outstanding_req_hist_coalsr::bucket_size 1 309system.ruby.outstanding_req_hist_coalsr::max_bucket 9 310system.ruby.outstanding_req_hist_coalsr::samples 27 |
| 311system.ruby.outstanding_req_hist_coalsr::mean 1.629630 312system.ruby.outstanding_req_hist_coalsr::gmean 1.438746 313system.ruby.outstanding_req_hist_coalsr::stdev 0.926040 314system.ruby.outstanding_req_hist_coalsr | 0 0.00% 0.00% | 16 59.26% 59.26% | 7 25.93% 85.19% | 2 7.41% 92.59% | 2 7.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 311system.ruby.outstanding_req_hist_coalsr::mean 2.074074 312system.ruby.outstanding_req_hist_coalsr::gmean 1.820631 313system.ruby.outstanding_req_hist_coalsr::stdev 1.071517 314system.ruby.outstanding_req_hist_coalsr | 0 0.00% 0.00% | 10 37.04% 37.04% | 9 33.33% 70.37% | 4 14.81% 85.19% | 4 14.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 315system.ruby.outstanding_req_hist_coalsr::total 27 316system.ruby.latency_hist_seqr::bucket_size 64 317system.ruby.latency_hist_seqr::max_bucket 639 318system.ruby.latency_hist_seqr::samples 114203 319system.ruby.latency_hist_seqr::mean 4.823332 320system.ruby.latency_hist_seqr::gmean 2.131609 321system.ruby.latency_hist_seqr::stdev 24.449444 322system.ruby.latency_hist_seqr | 112668 98.66% 98.66% | 0 0.00% 98.66% | 0 0.00% 98.66% | 1490 1.30% 99.96% | 18 0.02% 99.98% | 18 0.02% 99.99% | 2 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 7 0.01% 100.00% 323system.ruby.latency_hist_seqr::total 114203 324system.ruby.latency_hist_coalsr::bucket_size 64 325system.ruby.latency_hist_coalsr::max_bucket 639 326system.ruby.latency_hist_coalsr::samples 27 | 315system.ruby.outstanding_req_hist_coalsr::total 27 316system.ruby.latency_hist_seqr::bucket_size 64 317system.ruby.latency_hist_seqr::max_bucket 639 318system.ruby.latency_hist_seqr::samples 114203 319system.ruby.latency_hist_seqr::mean 4.823332 320system.ruby.latency_hist_seqr::gmean 2.131609 321system.ruby.latency_hist_seqr::stdev 24.449444 322system.ruby.latency_hist_seqr | 112668 98.66% 98.66% | 0 0.00% 98.66% | 0 0.00% 98.66% | 1490 1.30% 99.96% | 18 0.02% 99.98% | 18 0.02% 99.99% | 2 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 7 0.01% 100.00% 323system.ruby.latency_hist_seqr::total 114203 324system.ruby.latency_hist_coalsr::bucket_size 64 325system.ruby.latency_hist_coalsr::max_bucket 639 326system.ruby.latency_hist_coalsr::samples 27 |
| 327system.ruby.latency_hist_coalsr::mean 171 328system.ruby.latency_hist_coalsr::gmean 22.942606 329system.ruby.latency_hist_coalsr::stdev 184.818206 330system.ruby.latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 7 25.93% 74.07% | 2 7.41% 81.48% | 1 3.70% 85.19% | 1 3.70% 88.89% | 1 3.70% 92.59% | 2 7.41% 100.00% | 0 0.00% 100.00% | 327system.ruby.latency_hist_coalsr::mean 175.777778 328system.ruby.latency_hist_coalsr::gmean 29.086037 329system.ruby.latency_hist_coalsr::stdev 175.084668 330system.ruby.latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 1 3.70% 51.85% | 2 7.41% 59.26% | 7 25.93% 85.19% | 4 14.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 331system.ruby.latency_hist_coalsr::total 27 332system.ruby.hit_latency_hist_seqr::bucket_size 64 333system.ruby.hit_latency_hist_seqr::max_bucket 639 334system.ruby.hit_latency_hist_seqr::samples 1535 335system.ruby.hit_latency_hist_seqr::mean 211.362215 336system.ruby.hit_latency_hist_seqr::gmean 209.793806 337system.ruby.hit_latency_hist_seqr::stdev 34.965177 338system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1490 97.07% 97.07% | 18 1.17% 98.24% | 18 1.17% 99.41% | 2 0.13% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 7 0.46% 100.00% --- 4 unchanged lines hidden (view full) --- 343system.ruby.miss_latency_hist_seqr::mean 2.009426 344system.ruby.miss_latency_hist_seqr::gmean 2.002413 345system.ruby.miss_latency_hist_seqr::stdev 0.411800 346system.ruby.miss_latency_hist_seqr | 112609 99.95% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 59 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 347system.ruby.miss_latency_hist_seqr::total 112668 348system.ruby.miss_latency_hist_coalsr::bucket_size 64 349system.ruby.miss_latency_hist_coalsr::max_bucket 639 350system.ruby.miss_latency_hist_coalsr::samples 27 | 331system.ruby.latency_hist_coalsr::total 27 332system.ruby.hit_latency_hist_seqr::bucket_size 64 333system.ruby.hit_latency_hist_seqr::max_bucket 639 334system.ruby.hit_latency_hist_seqr::samples 1535 335system.ruby.hit_latency_hist_seqr::mean 211.362215 336system.ruby.hit_latency_hist_seqr::gmean 209.793806 337system.ruby.hit_latency_hist_seqr::stdev 34.965177 338system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1490 97.07% 97.07% | 18 1.17% 98.24% | 18 1.17% 99.41% | 2 0.13% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 7 0.46% 100.00% --- 4 unchanged lines hidden (view full) --- 343system.ruby.miss_latency_hist_seqr::mean 2.009426 344system.ruby.miss_latency_hist_seqr::gmean 2.002413 345system.ruby.miss_latency_hist_seqr::stdev 0.411800 346system.ruby.miss_latency_hist_seqr | 112609 99.95% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 59 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 347system.ruby.miss_latency_hist_seqr::total 112668 348system.ruby.miss_latency_hist_coalsr::bucket_size 64 349system.ruby.miss_latency_hist_coalsr::max_bucket 639 350system.ruby.miss_latency_hist_coalsr::samples 27 |
| 351system.ruby.miss_latency_hist_coalsr::mean 171 352system.ruby.miss_latency_hist_coalsr::gmean 22.942606 353system.ruby.miss_latency_hist_coalsr::stdev 184.818206 354system.ruby.miss_latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 7 25.93% 74.07% | 2 7.41% 81.48% | 1 3.70% 85.19% | 1 3.70% 88.89% | 1 3.70% 92.59% | 2 7.41% 100.00% | 0 0.00% 100.00% | 351system.ruby.miss_latency_hist_coalsr::mean 175.777778 352system.ruby.miss_latency_hist_coalsr::gmean 29.086037 353system.ruby.miss_latency_hist_coalsr::stdev 175.084668 354system.ruby.miss_latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 1 3.70% 51.85% | 2 7.41% 59.26% | 7 25.93% 85.19% | 4 14.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 355system.ruby.miss_latency_hist_coalsr::total 27 356system.ruby.L1Cache.incomplete_times_seqr 112609 357system.ruby.L2Cache.incomplete_times_seqr 59 358system.cp_cntrl0.L1D0cache.demand_hits 0 # Number of cache demand hits 359system.cp_cntrl0.L1D0cache.demand_misses 506 # Number of cache demand misses 360system.cp_cntrl0.L1D0cache.demand_accesses 506 # Number of cache demand accesses 361system.cp_cntrl0.L1D0cache.num_data_array_reads 16155 # number of data array reads 362system.cp_cntrl0.L1D0cache.num_data_array_writes 11985 # number of data array writes --- 9 unchanged lines hidden (view full) --- 372system.cp_cntrl0.L1Icache.num_data_array_writes 54 # number of data array writes 373system.cp_cntrl0.L1Icache.num_tag_array_reads 87684 # number of tag array reads 374system.cp_cntrl0.L1Icache.num_tag_array_writes 54 # number of tag array writes 375system.cp_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits 376system.cp_cntrl0.L2cache.demand_misses 1535 # Number of cache demand misses 377system.cp_cntrl0.L2cache.demand_accesses 1535 # Number of cache demand accesses 378system.cp_cntrl0.L2cache.num_data_array_reads 120 # number of data array reads 379system.cp_cntrl0.L2cache.num_data_array_writes 11982 # number of data array writes | 355system.ruby.miss_latency_hist_coalsr::total 27 356system.ruby.L1Cache.incomplete_times_seqr 112609 357system.ruby.L2Cache.incomplete_times_seqr 59 358system.cp_cntrl0.L1D0cache.demand_hits 0 # Number of cache demand hits 359system.cp_cntrl0.L1D0cache.demand_misses 506 # Number of cache demand misses 360system.cp_cntrl0.L1D0cache.demand_accesses 506 # Number of cache demand accesses 361system.cp_cntrl0.L1D0cache.num_data_array_reads 16155 # number of data array reads 362system.cp_cntrl0.L1D0cache.num_data_array_writes 11985 # number of data array writes --- 9 unchanged lines hidden (view full) --- 372system.cp_cntrl0.L1Icache.num_data_array_writes 54 # number of data array writes 373system.cp_cntrl0.L1Icache.num_tag_array_reads 87684 # number of tag array reads 374system.cp_cntrl0.L1Icache.num_tag_array_writes 54 # number of tag array writes 375system.cp_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits 376system.cp_cntrl0.L2cache.demand_misses 1535 # Number of cache demand misses 377system.cp_cntrl0.L2cache.demand_accesses 1535 # Number of cache demand accesses 378system.cp_cntrl0.L2cache.num_data_array_reads 120 # number of data array reads 379system.cp_cntrl0.L2cache.num_data_array_writes 11982 # number of data array writes |
| 380system.cp_cntrl0.L2cache.num_tag_array_reads 12059 # number of tag array reads | 380system.cp_cntrl0.L2cache.num_tag_array_reads 12057 # number of tag array reads |
| 381system.cp_cntrl0.L2cache.num_tag_array_writes 1649 # number of tag array writes | 381system.cp_cntrl0.L2cache.num_tag_array_writes 1649 # number of tag array writes |
| 382system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 383system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 384system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states | 382system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 383system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 384system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states |
| 385system.cpu0.clk_domain.clock 500 # Clock period in ticks | 385system.cpu0.clk_domain.clock 500 # Clock period in ticks |
| 386system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states | 386system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states |
| 387system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks | 387system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks |
| 388system.cpu0.interrupts.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 389system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states | 388system.cpu0.interrupts.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 389system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states |
| 390system.cpu0.workload.num_syscalls 21 # Number of system calls 391system.cpu0.numPwrStateTransitions 2 # Number of power state transitions 392system.cpu0.pwrStateClkGateDist::samples 1 # Distribution of time spent in the clock gated state | 390system.cpu0.workload.num_syscalls 21 # Number of system calls 391system.cpu0.numPwrStateTransitions 2 # Number of power state transitions 392system.cpu0.pwrStateClkGateDist::samples 1 # Distribution of time spent in the clock gated state |
| 393system.cpu0.pwrStateClkGateDist::mean 2825501 # Distribution of time spent in the clock gated state | 393system.cpu0.pwrStateClkGateDist::mean 2095501 # Distribution of time spent in the clock gated state |
| 394system.cpu0.pwrStateClkGateDist::1000-5e+10 1 100.00% 100.00% # Distribution of time spent in the clock gated state | 394system.cpu0.pwrStateClkGateDist::1000-5e+10 1 100.00% 100.00% # Distribution of time spent in the clock gated state |
| 395system.cpu0.pwrStateClkGateDist::min_value 2825501 # Distribution of time spent in the clock gated state 396system.cpu0.pwrStateClkGateDist::max_value 2825501 # Distribution of time spent in the clock gated state | 395system.cpu0.pwrStateClkGateDist::min_value 2095501 # Distribution of time spent in the clock gated state 396system.cpu0.pwrStateClkGateDist::max_value 2095501 # Distribution of time spent in the clock gated state |
| 397system.cpu0.pwrStateClkGateDist::total 1 # Distribution of time spent in the clock gated state 398system.cpu0.pwrStateResidencyTicks::ON 665311999 # Cumulative time (in ticks) in various power states | 397system.cpu0.pwrStateClkGateDist::total 1 # Distribution of time spent in the clock gated state 398system.cpu0.pwrStateResidencyTicks::ON 665311999 # Cumulative time (in ticks) in various power states |
| 399system.cpu0.pwrStateResidencyTicks::CLK_GATED 2825501 # Cumulative time (in ticks) in various power states 400system.cpu0.numCycles 1336275 # number of cpu cycles simulated | 399system.cpu0.pwrStateResidencyTicks::CLK_GATED 2095501 # Cumulative time (in ticks) in various power states 400system.cpu0.numCycles 1334815 # number of cpu cycles simulated |
| 401system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 402system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 403system.cpu0.committedInsts 66963 # Number of instructions committed 404system.cpu0.committedOps 137705 # Number of ops (including micro ops) committed 405system.cpu0.num_int_alu_accesses 136380 # Number of integer alu accesses 406system.cpu0.num_fp_alu_accesses 1279 # Number of float alu accesses 407system.cpu0.num_func_calls 3196 # number of times a function call or return occured 408system.cpu0.num_conditional_control_insts 12151 # number of instructions that are conditional controls 409system.cpu0.num_int_insts 136380 # number of integer instructions 410system.cpu0.num_fp_insts 1279 # number of float instructions 411system.cpu0.num_int_register_reads 257490 # number of times the integer registers were read 412system.cpu0.num_int_register_writes 110039 # number of times the integer registers were written 413system.cpu0.num_fp_register_reads 1981 # number of times the floating registers were read 414system.cpu0.num_fp_register_writes 981 # number of times the floating registers were written 415system.cpu0.num_cc_register_reads 78262 # number of times the CC registers were read 416system.cpu0.num_cc_register_writes 42183 # number of times the CC registers were written 417system.cpu0.num_mem_refs 27198 # number of memory refs 418system.cpu0.num_load_insts 16684 # Number of load instructions 419system.cpu0.num_store_insts 10514 # Number of store instructions | 401system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 402system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 403system.cpu0.committedInsts 66963 # Number of instructions committed 404system.cpu0.committedOps 137705 # Number of ops (including micro ops) committed 405system.cpu0.num_int_alu_accesses 136380 # Number of integer alu accesses 406system.cpu0.num_fp_alu_accesses 1279 # Number of float alu accesses 407system.cpu0.num_func_calls 3196 # number of times a function call or return occured 408system.cpu0.num_conditional_control_insts 12151 # number of instructions that are conditional controls 409system.cpu0.num_int_insts 136380 # number of integer instructions 410system.cpu0.num_fp_insts 1279 # number of float instructions 411system.cpu0.num_int_register_reads 257490 # number of times the integer registers were read 412system.cpu0.num_int_register_writes 110039 # number of times the integer registers were written 413system.cpu0.num_fp_register_reads 1981 # number of times the floating registers were read 414system.cpu0.num_fp_register_writes 981 # number of times the floating registers were written 415system.cpu0.num_cc_register_reads 78262 # number of times the CC registers were read 416system.cpu0.num_cc_register_writes 42183 # number of times the CC registers were written 417system.cpu0.num_mem_refs 27198 # number of memory refs 418system.cpu0.num_load_insts 16684 # Number of load instructions 419system.cpu0.num_store_insts 10514 # Number of store instructions |
| 420system.cpu0.num_idle_cycles 5651.003992 # Number of idle cycles 421system.cpu0.num_busy_cycles 1330623.996008 # Number of busy cycles 422system.cpu0.not_idle_fraction 0.995771 # Percentage of non-idle cycles 423system.cpu0.idle_fraction 0.004229 # Percentage of idle cycles | 420system.cpu0.num_idle_cycles 4191.003994 # Number of idle cycles 421system.cpu0.num_busy_cycles 1330623.996006 # Number of busy cycles 422system.cpu0.not_idle_fraction 0.996860 # Percentage of non-idle cycles 423system.cpu0.idle_fraction 0.003140 # Percentage of idle cycles |
| 424system.cpu0.Branches 16199 # Number of branches fetched 425system.cpu0.op_class::No_OpClass 615 0.45% 0.45% # Class of executed instruction 426system.cpu0.op_class::IntAlu 108791 79.00% 79.45% # Class of executed instruction 427system.cpu0.op_class::IntMult 13 0.01% 79.46% # Class of executed instruction 428system.cpu0.op_class::IntDiv 138 0.10% 79.56% # Class of executed instruction 429system.cpu0.op_class::FloatAdd 950 0.69% 80.25% # Class of executed instruction 430system.cpu0.op_class::FloatCmp 0 0.00% 80.25% # Class of executed instruction 431system.cpu0.op_class::FloatCvt 0 0.00% 80.25% # Class of executed instruction --- 26 unchanged lines hidden (view full) --- 458system.cpu0.op_class::MemWrite 10514 7.64% 99.78% # Class of executed instruction 459system.cpu0.op_class::FloatMemRead 302 0.22% 100.00% # Class of executed instruction 460system.cpu0.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 461system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 462system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 463system.cpu0.op_class::total 137705 # Class of executed instruction 464system.cpu1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 465system.cpu1.clk_domain.clock 1000 # Clock period in ticks | 424system.cpu0.Branches 16199 # Number of branches fetched 425system.cpu0.op_class::No_OpClass 615 0.45% 0.45% # Class of executed instruction 426system.cpu0.op_class::IntAlu 108791 79.00% 79.45% # Class of executed instruction 427system.cpu0.op_class::IntMult 13 0.01% 79.46% # Class of executed instruction 428system.cpu0.op_class::IntDiv 138 0.10% 79.56% # Class of executed instruction 429system.cpu0.op_class::FloatAdd 950 0.69% 80.25% # Class of executed instruction 430system.cpu0.op_class::FloatCmp 0 0.00% 80.25% # Class of executed instruction 431system.cpu0.op_class::FloatCvt 0 0.00% 80.25% # Class of executed instruction --- 26 unchanged lines hidden (view full) --- 458system.cpu0.op_class::MemWrite 10514 7.64% 99.78% # Class of executed instruction 459system.cpu0.op_class::FloatMemRead 302 0.22% 100.00% # Class of executed instruction 460system.cpu0.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 461system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 462system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 463system.cpu0.op_class::total 137705 # Class of executed instruction 464system.cpu1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 465system.cpu1.clk_domain.clock 1000 # Clock period in ticks |
| 466system.cpu1.CUs0.localDataStore.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states | 466system.cpu1.CUs0.localDataStore.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states |
| 467system.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 468system.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies | 467system.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 468system.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies |
| 469system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 498 # number of times the wf's instructions are blocked due to RAW dependencies | 469system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 309 # number of times the wf's instructions are blocked due to RAW dependencies |
| 470system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands 471system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands 472system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands 473system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 474system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands 475system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands 476system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 477system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands --- 175 unchanged lines hidden (view full) --- 653system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 654system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 655system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 656system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 657system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 658system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 659system.cpu1.CUs0.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 660system.cpu1.CUs0.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies | 470system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands 471system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands 472system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands 473system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 474system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands 475system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands 476system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 477system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands --- 175 unchanged lines hidden (view full) --- 653system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 654system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 655system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 656system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 657system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 658system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 659system.cpu1.CUs0.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 660system.cpu1.CUs0.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies |
| 661system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 470 # number of times the wf's instructions are blocked due to RAW dependencies | 661system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 284 # number of times the wf's instructions are blocked due to RAW dependencies |
| 662system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 663system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 664system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 665system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 666system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 667system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 668system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 669system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands --- 175 unchanged lines hidden (view full) --- 845system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 846system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 847system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 848system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 849system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 850system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 851system.cpu1.CUs0.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 852system.cpu1.CUs0.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies | 662system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 663system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 664system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 665system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 666system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 667system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 668system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 669system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands --- 175 unchanged lines hidden (view full) --- 845system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 846system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 847system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 848system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 849system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 850system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 851system.cpu1.CUs0.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 852system.cpu1.CUs0.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies |
| 853system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 473 # number of times the wf's instructions are blocked due to RAW dependencies | 853system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 279 # number of times the wf's instructions are blocked due to RAW dependencies |
| 854system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 855system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 856system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 857system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 858system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 859system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 860system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 861system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands --- 175 unchanged lines hidden (view full) --- 1037system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1038system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1039system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1040system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1041system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1042system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1043system.cpu1.CUs0.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1044system.cpu1.CUs0.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies | 854system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 855system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 856system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 857system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 858system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 859system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 860system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 861system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands --- 175 unchanged lines hidden (view full) --- 1037system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1038system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1039system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1040system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1041system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1042system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1043system.cpu1.CUs0.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1044system.cpu1.CUs0.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies |
| 1045system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 467 # number of times the wf's instructions are blocked due to RAW dependencies | 1045system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 274 # number of times the wf's instructions are blocked due to RAW dependencies |
| 1046system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 1047system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 1048system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 1049system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 1050system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 1051system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 1052system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 1053system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands --- 173 unchanged lines hidden (view full) --- 1227system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1228system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1229system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1230system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1231system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1232system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1233system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1234system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands | 1046system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 1047system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 1048system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 1049system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 1050system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 1051system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 1052system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 1053system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands --- 173 unchanged lines hidden (view full) --- 1227system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1228system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1229system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1230system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1231system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1232system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1233system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1234system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands |
| 1235system.cpu1.CUs0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 1236system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it 1237system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it 1238system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it | 1235system.cpu1.CUs0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 1236system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 35 # For each instruction fetch request recieved record how many instructions you got from it 1237system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 11.257143 # For each instruction fetch request recieved record how many instructions you got from it 1238system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 5.595917 # For each instruction fetch request recieved record how many instructions you got from it |
| 1239system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 1240system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it | 1239system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 1240system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it |
| 1241system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it 1242system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it 1243system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it 1244system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it 1245system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it 1246system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it 1247system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1248system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1249system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1250system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1251system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1252system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1253system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1254system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1255system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it | 1241system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::2 4 11.43% 11.43% # For each instruction fetch request recieved record how many instructions you got from it 1242system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::3 4 11.43% 22.86% # For each instruction fetch request recieved record how many instructions you got from it 1243system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::4 1 2.86% 25.71% # For each instruction fetch request recieved record how many instructions you got from it 1244system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::5 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it 1245system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::6 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it 1246system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::7 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it 1247system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::8 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it 1248system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::9 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it 1249system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::10 4 11.43% 37.14% # For each instruction fetch request recieved record how many instructions you got from it 1250system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::11 4 11.43% 48.57% # For each instruction fetch request recieved record how many instructions you got from it 1251system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::12 0 0.00% 48.57% # For each instruction fetch request recieved record how many instructions you got from it 1252system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::13 0 0.00% 48.57% # For each instruction fetch request recieved record how many instructions you got from it 1253system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::14 1 2.86% 51.43% # For each instruction fetch request recieved record how many instructions you got from it 1254system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::15 0 0.00% 51.43% # For each instruction fetch request recieved record how many instructions you got from it 1255system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::16 17 48.57% 100.00% # For each instruction fetch request recieved record how many instructions you got from it |
| 1256system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1257system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1258system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1259system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1260system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1261system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1262system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1263system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1264system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1265system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1266system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1267system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1268system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1269system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1270system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1271system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1272system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1273system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it | 1256system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1257system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1258system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1259system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1260system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1261system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1262system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1263system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1264system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1265system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1266system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1267system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1268system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1269system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1270system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1271system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1272system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1273system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it |
| 1274system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it 1275system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it 1276system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 3471 # number of cycles the CU issues nothing | 1274system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value 16 # For each instruction fetch request recieved record how many instructions you got from it 1275system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total 35 # For each instruction fetch request recieved record how many instructions you got from it 1276system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 2741 # number of cycles the CU issues nothing |
| 1277system.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued 99 # number of cycles the CU issued at least one instruction 1278system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued 1279system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued 1280system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued 1281system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued 1282system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued 1283system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued | 1277system.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued 99 # number of cycles the CU issued at least one instruction 1278system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued 1279system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued 1280system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued 1281system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued 1282system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued 1283system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued |
| 1284system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 970 # Number of cycles no instruction of specific type issued 1285system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 548 # Number of cycles no instruction of specific type issued 1286system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 566 # Number of cycles no instruction of specific type issued 1287system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 523 # Number of cycles no instruction of specific type issued 1288system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 398 # Number of cycles no instruction of specific type issued | 1284system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 625 # Number of cycles no instruction of specific type issued 1285system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 340 # Number of cycles no instruction of specific type issued 1286system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 338 # Number of cycles no instruction of specific type issued 1287system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 335 # Number of cycles no instruction of specific type issued 1288system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 404 # Number of cycles no instruction of specific type issued |
| 1289system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM 22 # Number of cycles no instruction of specific type issued | 1289system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM 22 # Number of cycles no instruction of specific type issued |
| 1290system.cpu1.CUs0.ExecStage.spc::samples 3570 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1291system.cpu1.CUs0.ExecStage.spc::mean 0.039496 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1292system.cpu1.CUs0.ExecStage.spc::stdev 0.250206 # Execution units active per cycle (Exec unit=SIMD,MemPipe) | 1290system.cpu1.CUs0.ExecStage.spc::samples 2840 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1291system.cpu1.CUs0.ExecStage.spc::mean 0.049648 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1292system.cpu1.CUs0.ExecStage.spc::stdev 0.277106 # Execution units active per cycle (Exec unit=SIMD,MemPipe) |
| 1293system.cpu1.CUs0.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) | 1293system.cpu1.CUs0.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) |
| 1294system.cpu1.CUs0.ExecStage.spc::0 3471 97.23% 97.23% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1295system.cpu1.CUs0.ExecStage.spc::1 59 1.65% 98.88% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1296system.cpu1.CUs0.ExecStage.spc::2 38 1.06% 99.94% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1297system.cpu1.CUs0.ExecStage.spc::3 2 0.06% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) | 1294system.cpu1.CUs0.ExecStage.spc::0 2741 96.51% 96.51% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1295system.cpu1.CUs0.ExecStage.spc::1 57 2.01% 98.52% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1296system.cpu1.CUs0.ExecStage.spc::2 42 1.48% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1297system.cpu1.CUs0.ExecStage.spc::3 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) |
| 1298system.cpu1.CUs0.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1299system.cpu1.CUs0.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1300system.cpu1.CUs0.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1301system.cpu1.CUs0.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1302system.cpu1.CUs0.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) | 1298system.cpu1.CUs0.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1299system.cpu1.CUs0.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1300system.cpu1.CUs0.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1301system.cpu1.CUs0.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1302system.cpu1.CUs0.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) |
| 1303system.cpu1.CUs0.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1304system.cpu1.CUs0.ExecStage.spc::total 3570 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1305system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 93 # number of CU transitions from active to idle 1306system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 93 # duration of idle periods in cycles 1307system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 37.225806 # duration of idle periods in cycles 1308system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 154.644552 # duration of idle periods in cycles | 1303system.cpu1.CUs0.ExecStage.spc::max_value 2 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1304system.cpu1.CUs0.ExecStage.spc::total 2840 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1305system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 90 # number of CU transitions from active to idle 1306system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 90 # duration of idle periods in cycles 1307system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 29.322222 # duration of idle periods in cycles 1308system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 145.995831 # duration of idle periods in cycles |
| 1309system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles | 1309system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles |
| 1310system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 74 79.57% 79.57% # duration of idle periods in cycles 1311system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 7 7.53% 87.10% # duration of idle periods in cycles 1312system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 1 1.08% 88.17% # duration of idle periods in cycles 1313system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 1 1.08% 89.25% # duration of idle periods in cycles 1314system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 2 2.15% 91.40% # duration of idle periods in cycles 1315system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.08% 92.47% # duration of idle periods in cycles 1316system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 92.47% # duration of idle periods in cycles 1317system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 92.47% # duration of idle periods in cycles 1318system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 92.47% # duration of idle periods in cycles 1319system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 92.47% # duration of idle periods in cycles 1320system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 92.47% # duration of idle periods in cycles 1321system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 92.47% # duration of idle periods in cycles 1322system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 92.47% # duration of idle periods in cycles 1323system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 92.47% # duration of idle periods in cycles 1324system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 92.47% # duration of idle periods in cycles 1325system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 92.47% # duration of idle periods in cycles 1326system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 7 7.53% 100.00% # duration of idle periods in cycles | 1310system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 76 84.44% 84.44% # duration of idle periods in cycles 1311system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 7 7.78% 92.22% # duration of idle periods in cycles 1312system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 92.22% # duration of idle periods in cycles 1313system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 0 0.00% 92.22% # duration of idle periods in cycles 1314system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 0 0.00% 92.22% # duration of idle periods in cycles 1315system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.11% 93.33% # duration of idle periods in cycles 1316system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 93.33% # duration of idle periods in cycles 1317system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 93.33% # duration of idle periods in cycles 1318system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 93.33% # duration of idle periods in cycles 1319system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 93.33% # duration of idle periods in cycles 1320system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 93.33% # duration of idle periods in cycles 1321system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 93.33% # duration of idle periods in cycles 1322system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 93.33% # duration of idle periods in cycles 1323system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 93.33% # duration of idle periods in cycles 1324system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 93.33% # duration of idle periods in cycles 1325system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 93.33% # duration of idle periods in cycles 1326system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 6 6.67% 100.00% # duration of idle periods in cycles |
| 1327system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles 1328system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::max_value 1291 # duration of idle periods in cycles | 1327system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles 1328system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::max_value 1291 # duration of idle periods in cycles |
| 1329system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 93 # duration of idle periods in cycles | 1329system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 90 # duration of idle periods in cycles |
| 1330system.cpu1.CUs0.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF 1331system.cpu1.CUs0.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF | 1330system.cpu1.CUs0.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF 1331system.cpu1.CUs0.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF |
| 1332system.cpu1.CUs0.valu_insts 68 # Number of vector ALU insts issued. 1333system.cpu1.CUs0.valu_insts_per_wf 17 # The avg. number of vector ALU insts issued per-wavefront. 1334system.cpu1.CUs0.salu_insts 0 # Number of scalar ALU insts issued. 1335system.cpu1.CUs0.salu_insts_per_wf 0 # The avg. number of scalar ALU insts issued per-wavefront. 1336system.cpu1.CUs0.inst_cycles_valu 68 # Number of cycles needed to execute VALU insts. 1337system.cpu1.CUs0.inst_cycles_salu 0 # Number of cycles needed to execute SALU insts. 1338system.cpu1.CUs0.thread_cycles_valu 3076 # Number of thread cycles used to execute vector ALU ops. Similar to instCyclesVALU but multiplied by the number of active threads. 1339system.cpu1.CUs0.valu_utilization 70.680147 # Percentage of active vector ALU threads in a wave. 1340system.cpu1.CUs0.lds_no_flat_insts 6 # Number of LDS insts issued, not including FLAT accesses that resolve to LDS. 1341system.cpu1.CUs0.lds_no_flat_insts_per_wf 1.500000 # The avg. number of LDS insts (not including FLAT accesses that resolve to LDS) per-wavefront. 1342system.cpu1.CUs0.flat_vmem_insts 0 # The number of FLAT insts that resolve to vmem issued. 1343system.cpu1.CUs0.flat_vmem_insts_per_wf 0 # The average number of FLAT insts that resolve to vmem issued per-wavefront. 1344system.cpu1.CUs0.flat_lds_insts 0 # The number of FLAT insts that resolve to LDS issued. 1345system.cpu1.CUs0.flat_lds_insts_per_wf 0 # The average number of FLAT insts that resolve to LDS issued per-wavefront. 1346system.cpu1.CUs0.vector_mem_writes 8 # Number of vector mem write insts (excluding FLAT insts). 1347system.cpu1.CUs0.vector_mem_writes_per_wf 2 # The average number of vector mem write insts (excluding FLAT insts) per-wavefront. 1348system.cpu1.CUs0.vector_mem_reads 29 # Number of vector mem read insts (excluding FLAT insts). 1349system.cpu1.CUs0.vector_mem_reads_per_wf 7.250000 # The avg. number of vector mem read insts (excluding FLAT insts) per-wavefront. 1350system.cpu1.CUs0.scalar_mem_writes 0 # Number of scalar mem write insts. 1351system.cpu1.CUs0.scalar_mem_writes_per_wf 0 # The average number of scalar mem write insts per-wavefront. 1352system.cpu1.CUs0.scalar_mem_reads 0 # Number of scalar mem read insts. 1353system.cpu1.CUs0.scalar_mem_reads_per_wf 0 # The average number of scalar mem read insts per-wavefront. |
|
| 1332system.cpu1.CUs0.tlb_requests 769 # number of uncoalesced requests | 1354system.cpu1.CUs0.tlb_requests 769 # number of uncoalesced requests |
| 1333system.cpu1.CUs0.tlb_cycles -455223738000 # total number of cycles for all uncoalesced requests 1334system.cpu1.CUs0.avg_translation_latency -591968449.934981 # Avg. translation latency for data translations | 1355system.cpu1.CUs0.tlb_cycles -454892896000 # total number of cycles for all uncoalesced requests 1356system.cpu1.CUs0.avg_translation_latency -591538226.267880 # Avg. translation latency for data translations |
| 1335system.cpu1.CUs0.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB 1336system.cpu1.CUs0.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 1337system.cpu1.CUs0.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 1338system.cpu1.CUs0.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 1339system.cpu1.CUs0.lds_bank_access_cnt 54 # Total number of LDS bank accesses 1340system.cpu1.CUs0.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet 1341system.cpu1.CUs0.lds_bank_conflicts::mean 8 # Number of bank conflicts per LDS memory packet 1342system.cpu1.CUs0.lds_bank_conflicts::stdev 6.196773 # Number of bank conflicts per LDS memory packet --- 59 unchanged lines hidden (view full) --- 1402system.cpu1.CUs0.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.) 1403system.cpu1.CUs0.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.) 1404system.cpu1.CUs0.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.) 1405system.cpu1.CUs0.global_mem_instr_cnt 17 # dynamic global memory instructions count 1406system.cpu1.CUs0.local_mem_instr_cnt 6 # dynamic local memory intruction count 1407system.cpu1.CUs0.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity 1408system.cpu1.CUs0.num_instr_executed 141 # number of instructions executed 1409system.cpu1.CUs0.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle | 1357system.cpu1.CUs0.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB 1358system.cpu1.CUs0.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 1359system.cpu1.CUs0.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 1360system.cpu1.CUs0.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 1361system.cpu1.CUs0.lds_bank_access_cnt 54 # Total number of LDS bank accesses 1362system.cpu1.CUs0.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet 1363system.cpu1.CUs0.lds_bank_conflicts::mean 8 # Number of bank conflicts per LDS memory packet 1364system.cpu1.CUs0.lds_bank_conflicts::stdev 6.196773 # Number of bank conflicts per LDS memory packet --- 59 unchanged lines hidden (view full) --- 1424system.cpu1.CUs0.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.) 1425system.cpu1.CUs0.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.) 1426system.cpu1.CUs0.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.) 1427system.cpu1.CUs0.global_mem_instr_cnt 17 # dynamic global memory instructions count 1428system.cpu1.CUs0.local_mem_instr_cnt 6 # dynamic local memory intruction count 1429system.cpu1.CUs0.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity 1430system.cpu1.CUs0.num_instr_executed 141 # number of instructions executed 1431system.cpu1.CUs0.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle |
| 1410system.cpu1.CUs0.inst_exec_rate::mean 92.127660 # Instruction Execution Rate: Number of executed vector instructions per cycle 1411system.cpu1.CUs0.inst_exec_rate::stdev 237.147810 # Instruction Execution Rate: Number of executed vector instructions per cycle | 1432system.cpu1.CUs0.inst_exec_rate::mean 71.028369 # Instruction Execution Rate: Number of executed vector instructions per cycle 1433system.cpu1.CUs0.inst_exec_rate::stdev 225.061514 # Instruction Execution Rate: Number of executed vector instructions per cycle |
| 1412system.cpu1.CUs0.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 1413system.cpu1.CUs0.inst_exec_rate::0-1 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 1414system.cpu1.CUs0.inst_exec_rate::2-3 12 8.51% 8.51% # Instruction Execution Rate: Number of executed vector instructions per cycle | 1434system.cpu1.CUs0.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 1435system.cpu1.CUs0.inst_exec_rate::0-1 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 1436system.cpu1.CUs0.inst_exec_rate::2-3 12 8.51% 8.51% # Instruction Execution Rate: Number of executed vector instructions per cycle |
| 1415system.cpu1.CUs0.inst_exec_rate::4-5 52 36.88% 45.39% # Instruction Execution Rate: Number of executed vector instructions per cycle 1416system.cpu1.CUs0.inst_exec_rate::6-7 31 21.99% 67.38% # Instruction Execution Rate: Number of executed vector instructions per cycle 1417system.cpu1.CUs0.inst_exec_rate::8-9 3 2.13% 69.50% # Instruction Execution Rate: Number of executed vector instructions per cycle 1418system.cpu1.CUs0.inst_exec_rate::10 3 2.13% 71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle 1419system.cpu1.CUs0.inst_exec_rate::overflows 40 28.37% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle | 1437system.cpu1.CUs0.inst_exec_rate::4-5 61 43.26% 51.77% # Instruction Execution Rate: Number of executed vector instructions per cycle 1438system.cpu1.CUs0.inst_exec_rate::6-7 32 22.70% 74.47% # Instruction Execution Rate: Number of executed vector instructions per cycle 1439system.cpu1.CUs0.inst_exec_rate::8-9 3 2.13% 76.60% # Instruction Execution Rate: Number of executed vector instructions per cycle 1440system.cpu1.CUs0.inst_exec_rate::10 3 2.13% 78.72% # Instruction Execution Rate: Number of executed vector instructions per cycle 1441system.cpu1.CUs0.inst_exec_rate::overflows 30 21.28% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle |
| 1420system.cpu1.CUs0.inst_exec_rate::min_value 2 # Instruction Execution Rate: Number of executed vector instructions per cycle 1421system.cpu1.CUs0.inst_exec_rate::max_value 1297 # Instruction Execution Rate: Number of executed vector instructions per cycle 1422system.cpu1.CUs0.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle 1423system.cpu1.CUs0.num_vec_ops_executed 6769 # number of vec ops executed (e.g. WF size/inst) | 1442system.cpu1.CUs0.inst_exec_rate::min_value 2 # Instruction Execution Rate: Number of executed vector instructions per cycle 1443system.cpu1.CUs0.inst_exec_rate::max_value 1297 # Instruction Execution Rate: Number of executed vector instructions per cycle 1444system.cpu1.CUs0.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle 1445system.cpu1.CUs0.num_vec_ops_executed 6769 # number of vec ops executed (e.g. WF size/inst) |
| 1424system.cpu1.CUs0.num_total_cycles 3570 # number of cycles the CU ran for 1425system.cpu1.CUs0.vpc 1.896078 # Vector Operations per cycle (this CU only) 1426system.cpu1.CUs0.ipc 0.039496 # Instructions per cycle (this CU only) | 1446system.cpu1.CUs0.num_total_cycles 2840 # number of cycles the CU ran for 1447system.cpu1.CUs0.vpc 2.383451 # Vector Operations per cycle (this CU only) 1448system.cpu1.CUs0.ipc 0.049648 # Instructions per cycle (this CU only) |
| 1427system.cpu1.CUs0.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) 1428system.cpu1.CUs0.warp_execution_dist::mean 48.007092 # number of lanes active per instruction (oval all instructions) 1429system.cpu1.CUs0.warp_execution_dist::stdev 23.719942 # number of lanes active per instruction (oval all instructions) 1430system.cpu1.CUs0.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions) 1431system.cpu1.CUs0.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions) 1432system.cpu1.CUs0.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) 1433system.cpu1.CUs0.warp_execution_dist::9-12 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) 1434system.cpu1.CUs0.warp_execution_dist::13-16 36 25.53% 29.08% # number of lanes active per instruction (oval all instructions) --- 61 unchanged lines hidden (view full) --- 1496system.cpu1.CUs0.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction 1497system.cpu1.CUs0.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction 1498system.cpu1.CUs0.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction 1499system.cpu1.CUs0.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed 1500system.cpu1.CUs0.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD 1501system.cpu1.CUs0.num_CAS_ops 0 # number of compare and swap operations 1502system.cpu1.CUs0.num_failed_CAS_ops 0 # number of compare and swap operations that failed 1503system.cpu1.CUs0.num_completed_wfs 4 # number of completed wavefronts | 1449system.cpu1.CUs0.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) 1450system.cpu1.CUs0.warp_execution_dist::mean 48.007092 # number of lanes active per instruction (oval all instructions) 1451system.cpu1.CUs0.warp_execution_dist::stdev 23.719942 # number of lanes active per instruction (oval all instructions) 1452system.cpu1.CUs0.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions) 1453system.cpu1.CUs0.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions) 1454system.cpu1.CUs0.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) 1455system.cpu1.CUs0.warp_execution_dist::9-12 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) 1456system.cpu1.CUs0.warp_execution_dist::13-16 36 25.53% 29.08% # number of lanes active per instruction (oval all instructions) --- 61 unchanged lines hidden (view full) --- 1518system.cpu1.CUs0.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction 1519system.cpu1.CUs0.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction 1520system.cpu1.CUs0.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction 1521system.cpu1.CUs0.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed 1522system.cpu1.CUs0.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD 1523system.cpu1.CUs0.num_CAS_ops 0 # number of compare and swap operations 1524system.cpu1.CUs0.num_failed_CAS_ops 0 # number of compare and swap operations that failed 1525system.cpu1.CUs0.num_completed_wfs 4 # number of completed wavefronts |
| 1504system.cpu1.CUs1.localDataStore.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states | 1526system.cpu1.CUs1.localDataStore.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states |
| 1505system.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1506system.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies | 1527system.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1528system.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies |
| 1507system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 591 # number of times the wf's instructions are blocked due to RAW dependencies | 1529system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 406 # number of times the wf's instructions are blocked due to RAW dependencies |
| 1508system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands 1509system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands 1510system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands 1511system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 1512system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands 1513system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands 1514system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 1515system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands --- 175 unchanged lines hidden (view full) --- 1691system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1692system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1693system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1694system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1695system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1696system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1697system.cpu1.CUs1.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1698system.cpu1.CUs1.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies | 1530system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands 1531system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands 1532system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands 1533system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 1534system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands 1535system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands 1536system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 1537system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands --- 175 unchanged lines hidden (view full) --- 1713system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1714system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1715system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1716system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1717system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1718system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1719system.cpu1.CUs1.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1720system.cpu1.CUs1.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies |
| 1699system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 562 # number of times the wf's instructions are blocked due to RAW dependencies | 1721system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 381 # number of times the wf's instructions are blocked due to RAW dependencies |
| 1700system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 1701system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 1702system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 1703system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 1704system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 1705system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 1706system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 1707system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands --- 175 unchanged lines hidden (view full) --- 1883system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1884system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1885system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1886system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1887system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1888system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1889system.cpu1.CUs1.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1890system.cpu1.CUs1.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies | 1722system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 1723system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 1724system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 1725system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 1726system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 1727system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 1728system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 1729system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands --- 175 unchanged lines hidden (view full) --- 1905system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1906system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1907system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1908system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1909system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1910system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1911system.cpu1.CUs1.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1912system.cpu1.CUs1.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies |
| 1891system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 561 # number of times the wf's instructions are blocked due to RAW dependencies | 1913system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 372 # number of times the wf's instructions are blocked due to RAW dependencies |
| 1892system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 1893system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 1894system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 1895system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 1896system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 1897system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 1898system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 1899system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands --- 175 unchanged lines hidden (view full) --- 2075system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 2076system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 2077system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 2078system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2079system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 2080system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 2081system.cpu1.CUs1.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 2082system.cpu1.CUs1.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies | 1914system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 1915system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 1916system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 1917system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 1918system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 1919system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 1920system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 1921system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands --- 175 unchanged lines hidden (view full) --- 2097system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 2098system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 2099system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 2100system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2101system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 2102system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 2103system.cpu1.CUs1.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 2104system.cpu1.CUs1.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies |
| 2083system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 551 # number of times the wf's instructions are blocked due to RAW dependencies | 2105system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 364 # number of times the wf's instructions are blocked due to RAW dependencies |
| 2084system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 2085system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 2086system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 2087system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 2088system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 2089system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 2090system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 2091system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands --- 173 unchanged lines hidden (view full) --- 2265system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 2266system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 2267system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 2268system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 2269system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 2270system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2271system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 2272system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands | 2106system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 2107system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 2108system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 2109system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 2110system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 2111system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 2112system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 2113system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands --- 173 unchanged lines hidden (view full) --- 2287system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 2288system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 2289system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 2290system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 2291system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 2292system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2293system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 2294system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands |
| 2273system.cpu1.CUs1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2274system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it 2275system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it 2276system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it | 2295system.cpu1.CUs1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 2296system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 35 # For each instruction fetch request recieved record how many instructions you got from it 2297system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 11.257143 # For each instruction fetch request recieved record how many instructions you got from it 2298system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 5.595917 # For each instruction fetch request recieved record how many instructions you got from it |
| 2277system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 2278system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it | 2299system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 2300system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it |
| 2279system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it 2280system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it 2281system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it 2282system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it 2283system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it 2284system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it 2285system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2286system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2287system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2288system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2289system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2290system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2291system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2292system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2293system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it | 2301system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::2 4 11.43% 11.43% # For each instruction fetch request recieved record how many instructions you got from it 2302system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::3 4 11.43% 22.86% # For each instruction fetch request recieved record how many instructions you got from it 2303system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::4 1 2.86% 25.71% # For each instruction fetch request recieved record how many instructions you got from it 2304system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::5 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it 2305system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::6 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it 2306system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::7 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it 2307system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::8 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it 2308system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::9 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it 2309system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::10 4 11.43% 37.14% # For each instruction fetch request recieved record how many instructions you got from it 2310system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::11 4 11.43% 48.57% # For each instruction fetch request recieved record how many instructions you got from it 2311system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::12 0 0.00% 48.57% # For each instruction fetch request recieved record how many instructions you got from it 2312system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::13 0 0.00% 48.57% # For each instruction fetch request recieved record how many instructions you got from it 2313system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::14 1 2.86% 51.43% # For each instruction fetch request recieved record how many instructions you got from it 2314system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::15 0 0.00% 51.43% # For each instruction fetch request recieved record how many instructions you got from it 2315system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::16 17 48.57% 100.00% # For each instruction fetch request recieved record how many instructions you got from it |
| 2294system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2295system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2296system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2297system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2298system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2299system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2300system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2301system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2302system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2303system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2304system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2305system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2306system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2307system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2308system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2309system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2310system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2311system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it | 2316system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2317system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2318system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2319system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2320system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2321system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2322system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2323system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2324system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2325system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2326system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2327system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2328system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2329system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2330system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2331system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2332system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2333system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it |
| 2312system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it 2313system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it 2314system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 3471 # number of cycles the CU issues nothing 2315system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 99 # number of cycles the CU issued at least one instruction | 2334system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value 16 # For each instruction fetch request recieved record how many instructions you got from it 2335system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total 35 # For each instruction fetch request recieved record how many instructions you got from it 2336system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 2740 # number of cycles the CU issues nothing 2337system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 100 # number of cycles the CU issued at least one instruction |
| 2316system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued 2317system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued 2318system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued 2319system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued 2320system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued 2321system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued | 2338system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued 2339system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued 2340system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued 2341system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued 2342system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued 2343system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued |
| 2322system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 973 # Number of cycles no instruction of specific type issued 2323system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 662 # Number of cycles no instruction of specific type issued 2324system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 634 # Number of cycles no instruction of specific type issued 2325system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 606 # Number of cycles no instruction of specific type issued 2326system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 404 # Number of cycles no instruction of specific type issued | 2344system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 795 # Number of cycles no instruction of specific type issued 2345system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 437 # Number of cycles no instruction of specific type issued 2346system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 431 # Number of cycles no instruction of specific type issued 2347system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 422 # Number of cycles no instruction of specific type issued 2348system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 408 # Number of cycles no instruction of specific type issued |
| 2327system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM 22 # Number of cycles no instruction of specific type issued | 2349system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM 22 # Number of cycles no instruction of specific type issued |
| 2328system.cpu1.CUs1.ExecStage.spc::samples 3570 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2329system.cpu1.CUs1.ExecStage.spc::mean 0.039496 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2330system.cpu1.CUs1.ExecStage.spc::stdev 0.249084 # Execution units active per cycle (Exec unit=SIMD,MemPipe) | 2350system.cpu1.CUs1.ExecStage.spc::samples 2840 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2351system.cpu1.CUs1.ExecStage.spc::mean 0.049648 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2352system.cpu1.CUs1.ExecStage.spc::stdev 0.275831 # Execution units active per cycle (Exec unit=SIMD,MemPipe) |
| 2331system.cpu1.CUs1.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) | 2353system.cpu1.CUs1.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) |
| 2332system.cpu1.CUs1.ExecStage.spc::0 3471 97.23% 97.23% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2333system.cpu1.CUs1.ExecStage.spc::1 58 1.62% 98.85% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2334system.cpu1.CUs1.ExecStage.spc::2 40 1.12% 99.97% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2335system.cpu1.CUs1.ExecStage.spc::3 1 0.03% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) | 2354system.cpu1.CUs1.ExecStage.spc::0 2740 96.48% 96.48% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2355system.cpu1.CUs1.ExecStage.spc::1 59 2.08% 98.56% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2356system.cpu1.CUs1.ExecStage.spc::2 41 1.44% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2357system.cpu1.CUs1.ExecStage.spc::3 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) |
| 2336system.cpu1.CUs1.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2337system.cpu1.CUs1.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2338system.cpu1.CUs1.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2339system.cpu1.CUs1.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2340system.cpu1.CUs1.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) | 2358system.cpu1.CUs1.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2359system.cpu1.CUs1.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2360system.cpu1.CUs1.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2361system.cpu1.CUs1.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2362system.cpu1.CUs1.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) |
| 2341system.cpu1.CUs1.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2342system.cpu1.CUs1.ExecStage.spc::total 3570 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2343system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 94 # number of CU transitions from active to idle 2344system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 94 # duration of idle periods in cycles 2345system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 35.776596 # duration of idle periods in cycles 2346system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 153.908027 # duration of idle periods in cycles | 2363system.cpu1.CUs1.ExecStage.spc::max_value 2 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2364system.cpu1.CUs1.ExecStage.spc::total 2840 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2365system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 91 # number of CU transitions from active to idle 2366system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 91 # duration of idle periods in cycles 2367system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 30.010989 # duration of idle periods in cycles 2368system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 148.108031 # duration of idle periods in cycles |
| 2347system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles | 2369system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles |
| 2348system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 75 79.79% 79.79% # duration of idle periods in cycles 2349system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 8 8.51% 88.30% # duration of idle periods in cycles 2350system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 88.30% # duration of idle periods in cycles 2351system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 1 1.06% 89.36% # duration of idle periods in cycles 2352system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 2 2.13% 91.49% # duration of idle periods in cycles 2353system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 1 1.06% 92.55% # duration of idle periods in cycles 2354system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 92.55% # duration of idle periods in cycles 2355system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 92.55% # duration of idle periods in cycles 2356system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 92.55% # duration of idle periods in cycles 2357system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 92.55% # duration of idle periods in cycles 2358system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 92.55% # duration of idle periods in cycles 2359system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 92.55% # duration of idle periods in cycles 2360system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 92.55% # duration of idle periods in cycles 2361system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 92.55% # duration of idle periods in cycles 2362system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 92.55% # duration of idle periods in cycles 2363system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 92.55% # duration of idle periods in cycles 2364system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 7 7.45% 100.00% # duration of idle periods in cycles | 2370system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 76 83.52% 83.52% # duration of idle periods in cycles 2371system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 8 8.79% 92.31% # duration of idle periods in cycles 2372system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 92.31% # duration of idle periods in cycles 2373system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 0 0.00% 92.31% # duration of idle periods in cycles 2374system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 0 0.00% 92.31% # duration of idle periods in cycles 2375system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 1 1.10% 93.41% # duration of idle periods in cycles 2376system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 93.41% # duration of idle periods in cycles 2377system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 93.41% # duration of idle periods in cycles 2378system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 93.41% # duration of idle periods in cycles 2379system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 93.41% # duration of idle periods in cycles 2380system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 93.41% # duration of idle periods in cycles 2381system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 93.41% # duration of idle periods in cycles 2382system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 93.41% # duration of idle periods in cycles 2383system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 93.41% # duration of idle periods in cycles 2384system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 93.41% # duration of idle periods in cycles 2385system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 93.41% # duration of idle periods in cycles 2386system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 6 6.59% 100.00% # duration of idle periods in cycles |
| 2365system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles 2366system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::max_value 1299 # duration of idle periods in cycles | 2387system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles 2388system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::max_value 1299 # duration of idle periods in cycles |
| 2367system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 94 # duration of idle periods in cycles | 2389system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 91 # duration of idle periods in cycles |
| 2368system.cpu1.CUs1.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF 2369system.cpu1.CUs1.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF | 2390system.cpu1.CUs1.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF 2391system.cpu1.CUs1.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF |
| 2392system.cpu1.CUs1.valu_insts 68 # Number of vector ALU insts issued. 2393system.cpu1.CUs1.valu_insts_per_wf 17 # The avg. number of vector ALU insts issued per-wavefront. 2394system.cpu1.CUs1.salu_insts 0 # Number of scalar ALU insts issued. 2395system.cpu1.CUs1.salu_insts_per_wf 0 # The avg. number of scalar ALU insts issued per-wavefront. 2396system.cpu1.CUs1.inst_cycles_valu 68 # Number of cycles needed to execute VALU insts. 2397system.cpu1.CUs1.inst_cycles_salu 0 # Number of cycles needed to execute SALU insts. 2398system.cpu1.CUs1.thread_cycles_valu 3071 # Number of thread cycles used to execute vector ALU ops. Similar to instCyclesVALU but multiplied by the number of active threads. 2399system.cpu1.CUs1.valu_utilization 70.565257 # Percentage of active vector ALU threads in a wave. 2400system.cpu1.CUs1.lds_no_flat_insts 6 # Number of LDS insts issued, not including FLAT accesses that resolve to LDS. 2401system.cpu1.CUs1.lds_no_flat_insts_per_wf 1.500000 # The avg. number of LDS insts (not including FLAT accesses that resolve to LDS) per-wavefront. 2402system.cpu1.CUs1.flat_vmem_insts 0 # The number of FLAT insts that resolve to vmem issued. 2403system.cpu1.CUs1.flat_vmem_insts_per_wf 0 # The average number of FLAT insts that resolve to vmem issued per-wavefront. 2404system.cpu1.CUs1.flat_lds_insts 0 # The number of FLAT insts that resolve to LDS issued. 2405system.cpu1.CUs1.flat_lds_insts_per_wf 0 # The average number of FLAT insts that resolve to LDS issued per-wavefront. 2406system.cpu1.CUs1.vector_mem_writes 8 # Number of vector mem write insts (excluding FLAT insts). 2407system.cpu1.CUs1.vector_mem_writes_per_wf 2 # The average number of vector mem write insts (excluding FLAT insts) per-wavefront. 2408system.cpu1.CUs1.vector_mem_reads 29 # Number of vector mem read insts (excluding FLAT insts). 2409system.cpu1.CUs1.vector_mem_reads_per_wf 7.250000 # The avg. number of vector mem read insts (excluding FLAT insts) per-wavefront. 2410system.cpu1.CUs1.scalar_mem_writes 0 # Number of scalar mem write insts. 2411system.cpu1.CUs1.scalar_mem_writes_per_wf 0 # The average number of scalar mem write insts per-wavefront. 2412system.cpu1.CUs1.scalar_mem_reads 0 # Number of scalar mem read insts. 2413system.cpu1.CUs1.scalar_mem_reads_per_wf 0 # The average number of scalar mem read insts per-wavefront. |
|
| 2370system.cpu1.CUs1.tlb_requests 769 # number of uncoalesced requests | 2414system.cpu1.CUs1.tlb_requests 769 # number of uncoalesced requests |
| 2371system.cpu1.CUs1.tlb_cycles -455230572000 # total number of cycles for all uncoalesced requests 2372system.cpu1.CUs1.avg_translation_latency -591977336.801040 # Avg. translation latency for data translations | 2415system.cpu1.CUs1.tlb_cycles -454919630000 # total number of cycles for all uncoalesced requests 2416system.cpu1.CUs1.avg_translation_latency -591572990.897269 # Avg. translation latency for data translations |
| 2373system.cpu1.CUs1.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB 2374system.cpu1.CUs1.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 2375system.cpu1.CUs1.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 2376system.cpu1.CUs1.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 2377system.cpu1.CUs1.lds_bank_access_cnt 53 # Total number of LDS bank accesses 2378system.cpu1.CUs1.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet 2379system.cpu1.CUs1.lds_bank_conflicts::mean 7.833333 # Number of bank conflicts per LDS memory packet 2380system.cpu1.CUs1.lds_bank_conflicts::stdev 6.080022 # Number of bank conflicts per LDS memory packet --- 59 unchanged lines hidden (view full) --- 2440system.cpu1.CUs1.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.) 2441system.cpu1.CUs1.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.) 2442system.cpu1.CUs1.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.) 2443system.cpu1.CUs1.global_mem_instr_cnt 17 # dynamic global memory instructions count 2444system.cpu1.CUs1.local_mem_instr_cnt 6 # dynamic local memory intruction count 2445system.cpu1.CUs1.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity 2446system.cpu1.CUs1.num_instr_executed 141 # number of instructions executed 2447system.cpu1.CUs1.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle | 2417system.cpu1.CUs1.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB 2418system.cpu1.CUs1.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 2419system.cpu1.CUs1.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 2420system.cpu1.CUs1.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 2421system.cpu1.CUs1.lds_bank_access_cnt 53 # Total number of LDS bank accesses 2422system.cpu1.CUs1.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet 2423system.cpu1.CUs1.lds_bank_conflicts::mean 7.833333 # Number of bank conflicts per LDS memory packet 2424system.cpu1.CUs1.lds_bank_conflicts::stdev 6.080022 # Number of bank conflicts per LDS memory packet --- 59 unchanged lines hidden (view full) --- 2484system.cpu1.CUs1.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.) 2485system.cpu1.CUs1.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.) 2486system.cpu1.CUs1.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.) 2487system.cpu1.CUs1.global_mem_instr_cnt 17 # dynamic global memory instructions count 2488system.cpu1.CUs1.local_mem_instr_cnt 6 # dynamic local memory intruction count 2489system.cpu1.CUs1.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity 2490system.cpu1.CUs1.num_instr_executed 141 # number of instructions executed 2491system.cpu1.CUs1.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle |
| 2448system.cpu1.CUs1.inst_exec_rate::mean 91.269504 # Instruction Execution Rate: Number of executed vector instructions per cycle 2449system.cpu1.CUs1.inst_exec_rate::stdev 240.230451 # Instruction Execution Rate: Number of executed vector instructions per cycle | 2492system.cpu1.CUs1.inst_exec_rate::mean 72.113475 # Instruction Execution Rate: Number of executed vector instructions per cycle 2493system.cpu1.CUs1.inst_exec_rate::stdev 228.065470 # Instruction Execution Rate: Number of executed vector instructions per cycle |
| 2450system.cpu1.CUs1.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 2451system.cpu1.CUs1.inst_exec_rate::0-1 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 2452system.cpu1.CUs1.inst_exec_rate::2-3 13 9.22% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle | 2494system.cpu1.CUs1.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 2495system.cpu1.CUs1.inst_exec_rate::0-1 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 2496system.cpu1.CUs1.inst_exec_rate::2-3 13 9.22% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle |
| 2453system.cpu1.CUs1.inst_exec_rate::4-5 52 36.88% 46.10% # Instruction Execution Rate: Number of executed vector instructions per cycle 2454system.cpu1.CUs1.inst_exec_rate::6-7 33 23.40% 69.50% # Instruction Execution Rate: Number of executed vector instructions per cycle 2455system.cpu1.CUs1.inst_exec_rate::8-9 6 4.26% 73.76% # Instruction Execution Rate: Number of executed vector instructions per cycle 2456system.cpu1.CUs1.inst_exec_rate::10 0 0.00% 73.76% # Instruction Execution Rate: Number of executed vector instructions per cycle 2457system.cpu1.CUs1.inst_exec_rate::overflows 37 26.24% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle | 2497system.cpu1.CUs1.inst_exec_rate::4-5 60 42.55% 51.77% # Instruction Execution Rate: Number of executed vector instructions per cycle 2498system.cpu1.CUs1.inst_exec_rate::6-7 34 24.11% 75.89% # Instruction Execution Rate: Number of executed vector instructions per cycle 2499system.cpu1.CUs1.inst_exec_rate::8-9 3 2.13% 78.01% # Instruction Execution Rate: Number of executed vector instructions per cycle 2500system.cpu1.CUs1.inst_exec_rate::10 1 0.71% 78.72% # Instruction Execution Rate: Number of executed vector instructions per cycle 2501system.cpu1.CUs1.inst_exec_rate::overflows 30 21.28% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle |
| 2458system.cpu1.CUs1.inst_exec_rate::min_value 2 # Instruction Execution Rate: Number of executed vector instructions per cycle 2459system.cpu1.CUs1.inst_exec_rate::max_value 1305 # Instruction Execution Rate: Number of executed vector instructions per cycle 2460system.cpu1.CUs1.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle 2461system.cpu1.CUs1.num_vec_ops_executed 6762 # number of vec ops executed (e.g. WF size/inst) | 2502system.cpu1.CUs1.inst_exec_rate::min_value 2 # Instruction Execution Rate: Number of executed vector instructions per cycle 2503system.cpu1.CUs1.inst_exec_rate::max_value 1305 # Instruction Execution Rate: Number of executed vector instructions per cycle 2504system.cpu1.CUs1.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle 2505system.cpu1.CUs1.num_vec_ops_executed 6762 # number of vec ops executed (e.g. WF size/inst) |
| 2462system.cpu1.CUs1.num_total_cycles 3570 # number of cycles the CU ran for 2463system.cpu1.CUs1.vpc 1.894118 # Vector Operations per cycle (this CU only) 2464system.cpu1.CUs1.ipc 0.039496 # Instructions per cycle (this CU only) | 2506system.cpu1.CUs1.num_total_cycles 2840 # number of cycles the CU ran for 2507system.cpu1.CUs1.vpc 2.380986 # Vector Operations per cycle (this CU only) 2508system.cpu1.CUs1.ipc 0.049648 # Instructions per cycle (this CU only) |
| 2465system.cpu1.CUs1.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) 2466system.cpu1.CUs1.warp_execution_dist::mean 47.957447 # number of lanes active per instruction (oval all instructions) 2467system.cpu1.CUs1.warp_execution_dist::stdev 23.818022 # number of lanes active per instruction (oval all instructions) 2468system.cpu1.CUs1.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions) 2469system.cpu1.CUs1.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions) 2470system.cpu1.CUs1.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) 2471system.cpu1.CUs1.warp_execution_dist::9-12 9 6.38% 9.93% # number of lanes active per instruction (oval all instructions) 2472system.cpu1.CUs1.warp_execution_dist::13-16 27 19.15% 29.08% # number of lanes active per instruction (oval all instructions) --- 61 unchanged lines hidden (view full) --- 2534system.cpu1.CUs1.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction 2535system.cpu1.CUs1.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction 2536system.cpu1.CUs1.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction 2537system.cpu1.CUs1.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed 2538system.cpu1.CUs1.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD 2539system.cpu1.CUs1.num_CAS_ops 0 # number of compare and swap operations 2540system.cpu1.CUs1.num_failed_CAS_ops 0 # number of compare and swap operations that failed 2541system.cpu1.CUs1.num_completed_wfs 4 # number of completed wavefronts | 2509system.cpu1.CUs1.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) 2510system.cpu1.CUs1.warp_execution_dist::mean 47.957447 # number of lanes active per instruction (oval all instructions) 2511system.cpu1.CUs1.warp_execution_dist::stdev 23.818022 # number of lanes active per instruction (oval all instructions) 2512system.cpu1.CUs1.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions) 2513system.cpu1.CUs1.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions) 2514system.cpu1.CUs1.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) 2515system.cpu1.CUs1.warp_execution_dist::9-12 9 6.38% 9.93% # number of lanes active per instruction (oval all instructions) 2516system.cpu1.CUs1.warp_execution_dist::13-16 27 19.15% 29.08% # number of lanes active per instruction (oval all instructions) --- 61 unchanged lines hidden (view full) --- 2578system.cpu1.CUs1.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction 2579system.cpu1.CUs1.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction 2580system.cpu1.CUs1.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction 2581system.cpu1.CUs1.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed 2582system.cpu1.CUs1.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD 2583system.cpu1.CUs1.num_CAS_ops 0 # number of compare and swap operations 2584system.cpu1.CUs1.num_failed_CAS_ops 0 # number of compare and swap operations that failed 2585system.cpu1.CUs1.num_completed_wfs 4 # number of completed wavefronts |
| 2542system.cpu1.CUs0.ldsBus.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2543system.cpu1.CUs1.ldsBus.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2544system.cpu2.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states | 2586system.cpu1.CUs0.ldsBus.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 2587system.cpu1.CUs1.ldsBus.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 2588system.cpu2.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states |
| 2545system.cpu2.num_kernel_launched 1 # number of kernel launched 2546system.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits 2547system.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses 2548system.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses | 2589system.cpu2.num_kernel_launched 1 # number of kernel launched 2590system.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits 2591system.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses 2592system.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses |
| 2549system.dir_cntrl0.L3CacheMemory.num_data_array_writes 1551 # number of data array writes 2550system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1551 # number of tag array reads 2551system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1551 # number of tag array writes 2552system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states | 2593system.dir_cntrl0.L3CacheMemory.num_data_array_writes 1549 # number of data array writes 2594system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1549 # number of tag array reads 2595system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1549 # number of tag array writes 2596system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states |
| 2553system.dispatcher_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2554system.dispatcher_coalescer.clk_domain.clock 1000 # Clock period in ticks | 2597system.dispatcher_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2598system.dispatcher_coalescer.clk_domain.clock 1000 # Clock period in ticks |
| 2555system.dispatcher_coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states | 2599system.dispatcher_coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states |
| 2556system.dispatcher_coalescer.uncoalesced_accesses 0 # Number of uncoalesced TLB accesses 2557system.dispatcher_coalescer.coalesced_accesses 0 # Number of coalesced TLB accesses 2558system.dispatcher_coalescer.queuing_cycles 0 # Number of cycles spent in queue 2559system.dispatcher_coalescer.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 2560system.dispatcher_coalescer.local_latency nan # Avg. latency over all incoming pkts 2561system.dispatcher_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2562system.dispatcher_tlb.clk_domain.clock 1000 # Clock period in ticks | 2600system.dispatcher_coalescer.uncoalesced_accesses 0 # Number of uncoalesced TLB accesses 2601system.dispatcher_coalescer.coalesced_accesses 0 # Number of coalesced TLB accesses 2602system.dispatcher_coalescer.queuing_cycles 0 # Number of cycles spent in queue 2603system.dispatcher_coalescer.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 2604system.dispatcher_coalescer.local_latency nan # Avg. latency over all incoming pkts 2605system.dispatcher_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2606system.dispatcher_tlb.clk_domain.clock 1000 # Clock period in ticks |
| 2563system.dispatcher_tlb.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states | 2607system.dispatcher_tlb.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states |
| 2564system.dispatcher_tlb.local_TLB_accesses 0 # Number of TLB accesses 2565system.dispatcher_tlb.local_TLB_hits 0 # Number of TLB hits 2566system.dispatcher_tlb.local_TLB_misses 0 # Number of TLB misses 2567system.dispatcher_tlb.local_TLB_miss_rate nan # TLB miss rate 2568system.dispatcher_tlb.global_TLB_accesses 0 # Number of TLB accesses 2569system.dispatcher_tlb.global_TLB_hits 0 # Number of TLB hits 2570system.dispatcher_tlb.global_TLB_misses 0 # Number of TLB misses 2571system.dispatcher_tlb.global_TLB_miss_rate nan # TLB miss rate 2572system.dispatcher_tlb.access_cycles 0 # Cycles spent accessing this TLB level 2573system.dispatcher_tlb.page_table_cycles 0 # Cycles spent accessing the page table 2574system.dispatcher_tlb.unique_pages 0 # Number of unique pages touched 2575system.dispatcher_tlb.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 2576system.dispatcher_tlb.local_latency nan # Avg. latency over incoming coalesced reqs 2577system.dispatcher_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 2578system.l1_coalescer0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2579system.l1_coalescer0.clk_domain.clock 1000 # Clock period in ticks | 2608system.dispatcher_tlb.local_TLB_accesses 0 # Number of TLB accesses 2609system.dispatcher_tlb.local_TLB_hits 0 # Number of TLB hits 2610system.dispatcher_tlb.local_TLB_misses 0 # Number of TLB misses 2611system.dispatcher_tlb.local_TLB_miss_rate nan # TLB miss rate 2612system.dispatcher_tlb.global_TLB_accesses 0 # Number of TLB accesses 2613system.dispatcher_tlb.global_TLB_hits 0 # Number of TLB hits 2614system.dispatcher_tlb.global_TLB_misses 0 # Number of TLB misses 2615system.dispatcher_tlb.global_TLB_miss_rate nan # TLB miss rate 2616system.dispatcher_tlb.access_cycles 0 # Cycles spent accessing this TLB level 2617system.dispatcher_tlb.page_table_cycles 0 # Cycles spent accessing the page table 2618system.dispatcher_tlb.unique_pages 0 # Number of unique pages touched 2619system.dispatcher_tlb.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 2620system.dispatcher_tlb.local_latency nan # Avg. latency over incoming coalesced reqs 2621system.dispatcher_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 2622system.l1_coalescer0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2623system.l1_coalescer0.clk_domain.clock 1000 # Clock period in ticks |
| 2580system.l1_coalescer0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states | 2624system.l1_coalescer0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states |
| 2581system.l1_coalescer0.uncoalesced_accesses 778 # Number of uncoalesced TLB accesses 2582system.l1_coalescer0.coalesced_accesses 0 # Number of coalesced TLB accesses 2583system.l1_coalescer0.queuing_cycles 0 # Number of cycles spent in queue 2584system.l1_coalescer0.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 2585system.l1_coalescer0.local_latency 0 # Avg. latency over all incoming pkts 2586system.l1_coalescer1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2587system.l1_coalescer1.clk_domain.clock 1000 # Clock period in ticks | 2625system.l1_coalescer0.uncoalesced_accesses 778 # Number of uncoalesced TLB accesses 2626system.l1_coalescer0.coalesced_accesses 0 # Number of coalesced TLB accesses 2627system.l1_coalescer0.queuing_cycles 0 # Number of cycles spent in queue 2628system.l1_coalescer0.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 2629system.l1_coalescer0.local_latency 0 # Avg. latency over all incoming pkts 2630system.l1_coalescer1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2631system.l1_coalescer1.clk_domain.clock 1000 # Clock period in ticks |
| 2588system.l1_coalescer1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states | 2632system.l1_coalescer1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states |
| 2589system.l1_coalescer1.uncoalesced_accesses 769 # Number of uncoalesced TLB accesses 2590system.l1_coalescer1.coalesced_accesses 0 # Number of coalesced TLB accesses 2591system.l1_coalescer1.queuing_cycles 0 # Number of cycles spent in queue 2592system.l1_coalescer1.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 2593system.l1_coalescer1.local_latency 0 # Avg. latency over all incoming pkts 2594system.l1_tlb0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2595system.l1_tlb0.clk_domain.clock 1000 # Clock period in ticks | 2633system.l1_coalescer1.uncoalesced_accesses 769 # Number of uncoalesced TLB accesses 2634system.l1_coalescer1.coalesced_accesses 0 # Number of coalesced TLB accesses 2635system.l1_coalescer1.queuing_cycles 0 # Number of cycles spent in queue 2636system.l1_coalescer1.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 2637system.l1_coalescer1.local_latency 0 # Avg. latency over all incoming pkts 2638system.l1_tlb0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2639system.l1_tlb0.clk_domain.clock 1000 # Clock period in ticks |
| 2596system.l1_tlb0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states | 2640system.l1_tlb0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states |
| 2597system.l1_tlb0.local_TLB_accesses 778 # Number of TLB accesses 2598system.l1_tlb0.local_TLB_hits 774 # Number of TLB hits 2599system.l1_tlb0.local_TLB_misses 4 # Number of TLB misses 2600system.l1_tlb0.local_TLB_miss_rate 0.514139 # TLB miss rate 2601system.l1_tlb0.global_TLB_accesses 778 # Number of TLB accesses 2602system.l1_tlb0.global_TLB_hits 774 # Number of TLB hits 2603system.l1_tlb0.global_TLB_misses 4 # Number of TLB misses 2604system.l1_tlb0.global_TLB_miss_rate 0.514139 # TLB miss rate 2605system.l1_tlb0.access_cycles 0 # Cycles spent accessing this TLB level 2606system.l1_tlb0.page_table_cycles 0 # Cycles spent accessing the page table 2607system.l1_tlb0.unique_pages 4 # Number of unique pages touched 2608system.l1_tlb0.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 2609system.l1_tlb0.local_latency 0 # Avg. latency over incoming coalesced reqs 2610system.l1_tlb0.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 2611system.l1_tlb1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2612system.l1_tlb1.clk_domain.clock 1000 # Clock period in ticks | 2641system.l1_tlb0.local_TLB_accesses 778 # Number of TLB accesses 2642system.l1_tlb0.local_TLB_hits 774 # Number of TLB hits 2643system.l1_tlb0.local_TLB_misses 4 # Number of TLB misses 2644system.l1_tlb0.local_TLB_miss_rate 0.514139 # TLB miss rate 2645system.l1_tlb0.global_TLB_accesses 778 # Number of TLB accesses 2646system.l1_tlb0.global_TLB_hits 774 # Number of TLB hits 2647system.l1_tlb0.global_TLB_misses 4 # Number of TLB misses 2648system.l1_tlb0.global_TLB_miss_rate 0.514139 # TLB miss rate 2649system.l1_tlb0.access_cycles 0 # Cycles spent accessing this TLB level 2650system.l1_tlb0.page_table_cycles 0 # Cycles spent accessing the page table 2651system.l1_tlb0.unique_pages 4 # Number of unique pages touched 2652system.l1_tlb0.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 2653system.l1_tlb0.local_latency 0 # Avg. latency over incoming coalesced reqs 2654system.l1_tlb0.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 2655system.l1_tlb1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2656system.l1_tlb1.clk_domain.clock 1000 # Clock period in ticks |
| 2613system.l1_tlb1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states | 2657system.l1_tlb1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states |
| 2614system.l1_tlb1.local_TLB_accesses 769 # Number of TLB accesses 2615system.l1_tlb1.local_TLB_hits 766 # Number of TLB hits 2616system.l1_tlb1.local_TLB_misses 3 # Number of TLB misses 2617system.l1_tlb1.local_TLB_miss_rate 0.390117 # TLB miss rate 2618system.l1_tlb1.global_TLB_accesses 769 # Number of TLB accesses 2619system.l1_tlb1.global_TLB_hits 766 # Number of TLB hits 2620system.l1_tlb1.global_TLB_misses 3 # Number of TLB misses 2621system.l1_tlb1.global_TLB_miss_rate 0.390117 # TLB miss rate 2622system.l1_tlb1.access_cycles 0 # Cycles spent accessing this TLB level 2623system.l1_tlb1.page_table_cycles 0 # Cycles spent accessing the page table 2624system.l1_tlb1.unique_pages 3 # Number of unique pages touched 2625system.l1_tlb1.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 2626system.l1_tlb1.local_latency 0 # Avg. latency over incoming coalesced reqs 2627system.l1_tlb1.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 2628system.l2_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2629system.l2_coalescer.clk_domain.clock 1000 # Clock period in ticks | 2658system.l1_tlb1.local_TLB_accesses 769 # Number of TLB accesses 2659system.l1_tlb1.local_TLB_hits 766 # Number of TLB hits 2660system.l1_tlb1.local_TLB_misses 3 # Number of TLB misses 2661system.l1_tlb1.local_TLB_miss_rate 0.390117 # TLB miss rate 2662system.l1_tlb1.global_TLB_accesses 769 # Number of TLB accesses 2663system.l1_tlb1.global_TLB_hits 766 # Number of TLB hits 2664system.l1_tlb1.global_TLB_misses 3 # Number of TLB misses 2665system.l1_tlb1.global_TLB_miss_rate 0.390117 # TLB miss rate 2666system.l1_tlb1.access_cycles 0 # Cycles spent accessing this TLB level 2667system.l1_tlb1.page_table_cycles 0 # Cycles spent accessing the page table 2668system.l1_tlb1.unique_pages 3 # Number of unique pages touched 2669system.l1_tlb1.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 2670system.l1_tlb1.local_latency 0 # Avg. latency over incoming coalesced reqs 2671system.l1_tlb1.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 2672system.l2_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2673system.l2_coalescer.clk_domain.clock 1000 # Clock period in ticks |
| 2630system.l2_coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states | 2674system.l2_coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states |
| 2631system.l2_coalescer.uncoalesced_accesses 8 # Number of uncoalesced TLB accesses 2632system.l2_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses 2633system.l2_coalescer.queuing_cycles 8000 # Number of cycles spent in queue 2634system.l2_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs 2635system.l2_coalescer.local_latency 125 # Avg. latency over all incoming pkts 2636system.l2_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2637system.l2_tlb.clk_domain.clock 1000 # Clock period in ticks | 2675system.l2_coalescer.uncoalesced_accesses 8 # Number of uncoalesced TLB accesses 2676system.l2_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses 2677system.l2_coalescer.queuing_cycles 8000 # Number of cycles spent in queue 2678system.l2_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs 2679system.l2_coalescer.local_latency 125 # Avg. latency over all incoming pkts 2680system.l2_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2681system.l2_tlb.clk_domain.clock 1000 # Clock period in ticks |
| 2638system.l2_tlb.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states | 2682system.l2_tlb.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states |
| 2639system.l2_tlb.local_TLB_accesses 8 # Number of TLB accesses 2640system.l2_tlb.local_TLB_hits 3 # Number of TLB hits 2641system.l2_tlb.local_TLB_misses 5 # Number of TLB misses 2642system.l2_tlb.local_TLB_miss_rate 62.500000 # TLB miss rate 2643system.l2_tlb.global_TLB_accesses 15 # Number of TLB accesses 2644system.l2_tlb.global_TLB_hits 3 # Number of TLB hits 2645system.l2_tlb.global_TLB_misses 12 # Number of TLB misses 2646system.l2_tlb.global_TLB_miss_rate 80 # TLB miss rate 2647system.l2_tlb.access_cycles 552008 # Cycles spent accessing this TLB level 2648system.l2_tlb.page_table_cycles 0 # Cycles spent accessing the page table 2649system.l2_tlb.unique_pages 5 # Number of unique pages touched 2650system.l2_tlb.local_cycles 69001 # Number of cycles spent in queue for all incoming reqs 2651system.l2_tlb.local_latency 8625.125000 # Avg. latency over incoming coalesced reqs 2652system.l2_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 2653system.l3_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2654system.l3_coalescer.clk_domain.clock 1000 # Clock period in ticks | 2683system.l2_tlb.local_TLB_accesses 8 # Number of TLB accesses 2684system.l2_tlb.local_TLB_hits 3 # Number of TLB hits 2685system.l2_tlb.local_TLB_misses 5 # Number of TLB misses 2686system.l2_tlb.local_TLB_miss_rate 62.500000 # TLB miss rate 2687system.l2_tlb.global_TLB_accesses 15 # Number of TLB accesses 2688system.l2_tlb.global_TLB_hits 3 # Number of TLB hits 2689system.l2_tlb.global_TLB_misses 12 # Number of TLB misses 2690system.l2_tlb.global_TLB_miss_rate 80 # TLB miss rate 2691system.l2_tlb.access_cycles 552008 # Cycles spent accessing this TLB level 2692system.l2_tlb.page_table_cycles 0 # Cycles spent accessing the page table 2693system.l2_tlb.unique_pages 5 # Number of unique pages touched 2694system.l2_tlb.local_cycles 69001 # Number of cycles spent in queue for all incoming reqs 2695system.l2_tlb.local_latency 8625.125000 # Avg. latency over incoming coalesced reqs 2696system.l2_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 2697system.l3_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2698system.l3_coalescer.clk_domain.clock 1000 # Clock period in ticks |
| 2655system.l3_coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states | 2699system.l3_coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states |
| 2656system.l3_coalescer.uncoalesced_accesses 5 # Number of uncoalesced TLB accesses 2657system.l3_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses 2658system.l3_coalescer.queuing_cycles 8000 # Number of cycles spent in queue 2659system.l3_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs 2660system.l3_coalescer.local_latency 200 # Avg. latency over all incoming pkts 2661system.l3_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2662system.l3_tlb.clk_domain.clock 1000 # Clock period in ticks | 2700system.l3_coalescer.uncoalesced_accesses 5 # Number of uncoalesced TLB accesses 2701system.l3_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses 2702system.l3_coalescer.queuing_cycles 8000 # Number of cycles spent in queue 2703system.l3_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs 2704system.l3_coalescer.local_latency 200 # Avg. latency over all incoming pkts 2705system.l3_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2706system.l3_tlb.clk_domain.clock 1000 # Clock period in ticks |
| 2663system.l3_tlb.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states | 2707system.l3_tlb.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states |
| 2664system.l3_tlb.local_TLB_accesses 5 # Number of TLB accesses 2665system.l3_tlb.local_TLB_hits 0 # Number of TLB hits 2666system.l3_tlb.local_TLB_misses 5 # Number of TLB misses 2667system.l3_tlb.local_TLB_miss_rate 100 # TLB miss rate 2668system.l3_tlb.global_TLB_accesses 12 # Number of TLB accesses 2669system.l3_tlb.global_TLB_hits 0 # Number of TLB hits 2670system.l3_tlb.global_TLB_misses 12 # Number of TLB misses 2671system.l3_tlb.global_TLB_miss_rate 100 # TLB miss rate 2672system.l3_tlb.access_cycles 1200000 # Cycles spent accessing this TLB level 2673system.l3_tlb.page_table_cycles 6000000 # Cycles spent accessing the page table 2674system.l3_tlb.unique_pages 5 # Number of unique pages touched 2675system.l3_tlb.local_cycles 150000 # Number of cycles spent in queue for all incoming reqs 2676system.l3_tlb.local_latency 30000 # Avg. latency over incoming coalesced reqs 2677system.l3_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) | 2708system.l3_tlb.local_TLB_accesses 5 # Number of TLB accesses 2709system.l3_tlb.local_TLB_hits 0 # Number of TLB hits 2710system.l3_tlb.local_TLB_misses 5 # Number of TLB misses 2711system.l3_tlb.local_TLB_miss_rate 100 # TLB miss rate 2712system.l3_tlb.global_TLB_accesses 12 # Number of TLB accesses 2713system.l3_tlb.global_TLB_hits 0 # Number of TLB hits 2714system.l3_tlb.global_TLB_misses 12 # Number of TLB misses 2715system.l3_tlb.global_TLB_miss_rate 100 # TLB miss rate 2716system.l3_tlb.access_cycles 1200000 # Cycles spent accessing this TLB level 2717system.l3_tlb.page_table_cycles 6000000 # Cycles spent accessing the page table 2718system.l3_tlb.unique_pages 5 # Number of unique pages touched 2719system.l3_tlb.local_cycles 150000 # Number of cycles spent in queue for all incoming reqs 2720system.l3_tlb.local_latency 30000 # Avg. latency over incoming coalesced reqs 2721system.l3_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) |
| 2678system.piobus.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states | 2722system.piobus.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states |
| 2679system.piobus.trans_dist::WriteReq 94 # Transaction distribution 2680system.piobus.trans_dist::WriteResp 94 # Transaction distribution 2681system.piobus.pkt_count_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 188 # Packet count per connected master and slave (bytes) 2682system.piobus.pkt_count::total 188 # Packet count per connected master and slave (bytes) 2683system.piobus.pkt_size_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 748 # Cumulative packet size per connected master and slave (bytes) 2684system.piobus.pkt_size::total 748 # Cumulative packet size per connected master and slave (bytes) 2685system.piobus.reqLayer0.occupancy 188000 # Layer occupancy (ticks) 2686system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2687system.piobus.respLayer0.occupancy 94000 # Layer occupancy (ticks) 2688system.piobus.respLayer0.utilization 0.0 # Layer utilization (%) | 2723system.piobus.trans_dist::WriteReq 94 # Transaction distribution 2724system.piobus.trans_dist::WriteResp 94 # Transaction distribution 2725system.piobus.pkt_count_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 188 # Packet count per connected master and slave (bytes) 2726system.piobus.pkt_count::total 188 # Packet count per connected master and slave (bytes) 2727system.piobus.pkt_size_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 748 # Cumulative packet size per connected master and slave (bytes) 2728system.piobus.pkt_size::total 748 # Cumulative packet size per connected master and slave (bytes) 2729system.piobus.reqLayer0.occupancy 188000 # Layer occupancy (ticks) 2730system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2731system.piobus.respLayer0.occupancy 94000 # Layer occupancy (ticks) 2732system.piobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2689system.ruby.network.ext_links0.int_node.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2690system.ruby.network.ext_links0.int_node.percent_links_utilized 0.007896 2691system.ruby.network.ext_links0.int_node.msg_count.Control::0 1551 2692system.ruby.network.ext_links0.int_node.msg_count.Request_Control::0 1551 2693system.ruby.network.ext_links0.int_node.msg_count.Response_Data::2 1563 2694system.ruby.network.ext_links0.int_node.msg_count.Response_Control::2 1539 2695system.ruby.network.ext_links0.int_node.msg_count.Unblock_Control::4 1551 2696system.ruby.network.ext_links0.int_node.msg_bytes.Control::0 12408 2697system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0 12408 2698system.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2 112536 2699system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2 12312 2700system.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4 12408 2701system.ruby.network.ext_links1.int_node.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2702system.ruby.network.ext_links1.int_node.percent_links_utilized 0.009900 2703system.ruby.network.ext_links1.int_node.msg_count.Control::0 16 | 2733system.ruby.network.ext_links0.int_node.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 2734system.ruby.network.ext_links0.int_node.percent_links_utilized 0.007895 2735system.ruby.network.ext_links0.int_node.msg_count.Control::0 1549 2736system.ruby.network.ext_links0.int_node.msg_count.Request_Control::0 1549 2737system.ruby.network.ext_links0.int_node.msg_count.Response_Data::2 1561 2738system.ruby.network.ext_links0.int_node.msg_count.Response_Control::2 1537 2739system.ruby.network.ext_links0.int_node.msg_count.Unblock_Control::4 1549 2740system.ruby.network.ext_links0.int_node.msg_bytes.Control::0 12392 2741system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0 12392 2742system.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2 112392 2743system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2 12296 2744system.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4 12392 2745system.ruby.network.ext_links1.int_node.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 2746system.ruby.network.ext_links1.int_node.percent_links_utilized 0.009908 2747system.ruby.network.ext_links1.int_node.msg_count.Control::0 14 |
| 2704system.ruby.network.ext_links1.int_node.msg_count.Request_Control::0 1535 2705system.ruby.network.ext_links1.int_node.msg_count.Response_Data::2 1537 | 2748system.ruby.network.ext_links1.int_node.msg_count.Request_Control::0 1535 2749system.ruby.network.ext_links1.int_node.msg_count.Response_Data::2 1537 |
| 2706system.ruby.network.ext_links1.int_node.msg_count.Response_Control::2 14 | 2750system.ruby.network.ext_links1.int_node.msg_count.Response_Control::2 12 |
| 2707system.ruby.network.ext_links1.int_node.msg_count.Unblock_Control::4 1535 | 2751system.ruby.network.ext_links1.int_node.msg_count.Unblock_Control::4 1535 |
| 2708system.ruby.network.ext_links1.int_node.msg_bytes.Control::0 128 | 2752system.ruby.network.ext_links1.int_node.msg_bytes.Control::0 112 |
| 2709system.ruby.network.ext_links1.int_node.msg_bytes.Request_Control::0 12280 2710system.ruby.network.ext_links1.int_node.msg_bytes.Response_Data::2 110664 | 2753system.ruby.network.ext_links1.int_node.msg_bytes.Request_Control::0 12280 2754system.ruby.network.ext_links1.int_node.msg_bytes.Response_Data::2 110664 |
| 2711system.ruby.network.ext_links1.int_node.msg_bytes.Response_Control::2 112 | 2755system.ruby.network.ext_links1.int_node.msg_bytes.Response_Control::2 96 |
| 2712system.ruby.network.ext_links1.int_node.msg_bytes.Unblock_Control::4 12280 2713system.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits 2714system.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses 2715system.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses | 2756system.ruby.network.ext_links1.int_node.msg_bytes.Unblock_Control::4 12280 2757system.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits 2758system.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses 2759system.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses |
| 2716system.tcp_cntrl0.L1cache.num_data_array_reads 9 # number of data array reads | 2760system.tcp_cntrl0.L1cache.num_data_array_reads 8 # number of data array reads |
| 2717system.tcp_cntrl0.L1cache.num_data_array_writes 11 # number of data array writes 2718system.tcp_cntrl0.L1cache.num_tag_array_reads 26 # number of tag array reads 2719system.tcp_cntrl0.L1cache.num_tag_array_writes 18 # number of tag array writes | 2761system.tcp_cntrl0.L1cache.num_data_array_writes 11 # number of data array writes 2762system.tcp_cntrl0.L1cache.num_tag_array_reads 26 # number of tag array reads 2763system.tcp_cntrl0.L1cache.num_tag_array_writes 18 # number of tag array writes |
| 2720system.tcp_cntrl0.L1cache.num_data_array_stalls 2 # number of stalls caused by data array 2721system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states | 2764system.tcp_cntrl0.L1cache.num_data_array_stalls 6 # number of stalls caused by data array 2765system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states |
| 2722system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 2 # loads that hit in the TCP 2723system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers 2724system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 2725system.tcp_cntrl0.coalescer.gpu_ld_misses 2 # loads that miss in the GPU 2726system.tcp_cntrl0.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP | 2766system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 2 # loads that hit in the TCP 2767system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers 2768system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 2769system.tcp_cntrl0.coalescer.gpu_ld_misses 2 # loads that miss in the GPU 2770system.tcp_cntrl0.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP |
| 2727system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 1 # TCP to TCP store transfers | 2771system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers |
| 2728system.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC | 2772system.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC |
| 2729system.tcp_cntrl0.coalescer.gpu_st_misses 4 # stores that miss in the GPU | 2773system.tcp_cntrl0.coalescer.gpu_st_misses 5 # stores that miss in the GPU |
| 2730system.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 2731system.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 2732system.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 2733system.tcp_cntrl0.coalescer.cp_ld_misses 0 # loads that miss in the GPU 2734system.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 2735system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 2736system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 2737system.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU | 2774system.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 2775system.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 2776system.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 2777system.tcp_cntrl0.coalescer.cp_ld_misses 0 # loads that miss in the GPU 2778system.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 2779system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 2780system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 2781system.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU |
| 2738system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2739system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2740system.ruby.network.ext_links2.int_node.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2741system.ruby.network.ext_links2.int_node.percent_links_utilized 0.000716 | 2782system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 2783system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 2784system.ruby.network.ext_links2.int_node.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 2785system.ruby.network.ext_links2.int_node.percent_links_utilized 0.000708 |
| 2742system.ruby.network.ext_links2.int_node.msg_count.Control::0 1535 2743system.ruby.network.ext_links2.int_node.msg_count.Control::1 14 | 2786system.ruby.network.ext_links2.int_node.msg_count.Control::0 1535 2787system.ruby.network.ext_links2.int_node.msg_count.Control::1 14 |
| 2744system.ruby.network.ext_links2.int_node.msg_count.Request_Control::0 16 2745system.ruby.network.ext_links2.int_node.msg_count.Request_Control::1 19 2746system.ruby.network.ext_links2.int_node.msg_count.Response_Data::2 26 2747system.ruby.network.ext_links2.int_node.msg_count.Response_Data::3 33 | 2788system.ruby.network.ext_links2.int_node.msg_count.Request_Control::0 14 2789system.ruby.network.ext_links2.int_node.msg_count.Request_Control::1 17 2790system.ruby.network.ext_links2.int_node.msg_count.Response_Data::2 24 2791system.ruby.network.ext_links2.int_node.msg_count.Response_Data::3 31 |
| 2748system.ruby.network.ext_links2.int_node.msg_count.Response_Control::2 1525 | 2792system.ruby.network.ext_links2.int_node.msg_count.Response_Control::2 1525 |
| 2749system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::4 16 2750system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::5 19 | 2793system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::4 14 2794system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::5 17 |
| 2751system.ruby.network.ext_links2.int_node.msg_bytes.Control::0 12280 2752system.ruby.network.ext_links2.int_node.msg_bytes.Control::1 112 | 2795system.ruby.network.ext_links2.int_node.msg_bytes.Control::0 12280 2796system.ruby.network.ext_links2.int_node.msg_bytes.Control::1 112 |
| 2753system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::0 128 2754system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::1 152 2755system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::2 1872 2756system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::3 2376 | 2797system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::0 112 2798system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::1 136 2799system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::2 1728 2800system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::3 2232 |
| 2757system.ruby.network.ext_links2.int_node.msg_bytes.Response_Control::2 12200 | 2801system.ruby.network.ext_links2.int_node.msg_bytes.Response_Control::2 12200 |
| 2758system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::4 128 2759system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::5 152 | 2802system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::4 112 2803system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::5 136 |
| 2760system.tcp_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits 2761system.tcp_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses 2762system.tcp_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses | 2804system.tcp_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits 2805system.tcp_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses 2806system.tcp_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses |
| 2763system.tcp_cntrl1.L1cache.num_data_array_reads 7 # number of data array reads | 2807system.tcp_cntrl1.L1cache.num_data_array_reads 8 # number of data array reads |
| 2764system.tcp_cntrl1.L1cache.num_data_array_writes 11 # number of data array writes 2765system.tcp_cntrl1.L1cache.num_tag_array_reads 25 # number of tag array reads 2766system.tcp_cntrl1.L1cache.num_tag_array_writes 18 # number of tag array writes 2767system.tcp_cntrl1.L1cache.num_tag_array_stalls 2 # number of stalls caused by tag array | 2808system.tcp_cntrl1.L1cache.num_data_array_writes 11 # number of data array writes 2809system.tcp_cntrl1.L1cache.num_tag_array_reads 25 # number of tag array reads 2810system.tcp_cntrl1.L1cache.num_tag_array_writes 18 # number of tag array writes 2811system.tcp_cntrl1.L1cache.num_tag_array_stalls 2 # number of stalls caused by tag array |
| 2768system.tcp_cntrl1.L1cache.num_data_array_stalls 2 # number of stalls caused by data array 2769system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states | 2812system.tcp_cntrl1.L1cache.num_data_array_stalls 6 # number of stalls caused by data array 2813system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states |
| 2770system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 3 # loads that hit in the TCP 2771system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 2 # TCP to TCP load transfers 2772system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 2773system.tcp_cntrl1.coalescer.gpu_ld_misses 0 # loads that miss in the GPU 2774system.tcp_cntrl1.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP | 2814system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 3 # loads that hit in the TCP 2815system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 2 # TCP to TCP load transfers 2816system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 2817system.tcp_cntrl1.coalescer.gpu_ld_misses 0 # loads that miss in the GPU 2818system.tcp_cntrl1.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP |
| 2775system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers | 2819system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 1 # TCP to TCP store transfers |
| 2776system.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC | 2820system.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC |
| 2777system.tcp_cntrl1.coalescer.gpu_st_misses 5 # stores that miss in the GPU | 2821system.tcp_cntrl1.coalescer.gpu_st_misses 4 # stores that miss in the GPU |
| 2778system.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 2779system.tcp_cntrl1.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 2780system.tcp_cntrl1.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 2781system.tcp_cntrl1.coalescer.cp_ld_misses 0 # loads that miss in the GPU 2782system.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 2783system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 2784system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 2785system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU | 2822system.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 2823system.tcp_cntrl1.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 2824system.tcp_cntrl1.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 2825system.tcp_cntrl1.coalescer.cp_ld_misses 0 # loads that miss in the GPU 2826system.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 2827system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 2828system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 2829system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU |
| 2786system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2787system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states | 2830system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 2831system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states |
| 2788system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits 2789system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses 2790system.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses | 2832system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits 2833system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses 2834system.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses |
| 2791system.sqc_cntrl0.L1cache.num_data_array_reads 86 # number of data array reads 2792system.sqc_cntrl0.L1cache.num_data_array_writes 5 # number of data array writes 2793system.sqc_cntrl0.L1cache.num_tag_array_reads 86 # number of tag array reads 2794system.sqc_cntrl0.L1cache.num_tag_array_writes 5 # number of tag array writes 2795system.sqc_cntrl0.L1cache.num_data_array_stalls 47 # number of stalls caused by data array 2796system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2797system.sqc_cntrl0.sequencer.load_waiting_on_load 120 # Number of times a load aliased with a pending load 2798system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states | 2835system.sqc_cntrl0.L1cache.num_data_array_reads 70 # number of data array reads 2836system.sqc_cntrl0.L1cache.num_data_array_writes 3 # number of data array writes 2837system.sqc_cntrl0.L1cache.num_tag_array_reads 70 # number of tag array reads 2838system.sqc_cntrl0.L1cache.num_tag_array_writes 3 # number of tag array writes 2839system.sqc_cntrl0.L1cache.num_data_array_stalls 28 # number of stalls caused by data array 2840system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 2841system.sqc_cntrl0.sequencer.load_waiting_on_load 75 # Number of times a load aliased with a pending load 2842system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states |
| 2799system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits 2800system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses 2801system.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses | 2843system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits 2844system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses 2845system.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses |
| 2802system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states | 2846system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states |
| 2803system.tccdir_cntrl0.directory.demand_hits 0 # Number of cache demand hits 2804system.tccdir_cntrl0.directory.demand_misses 0 # Number of cache demand misses 2805system.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses | 2847system.tccdir_cntrl0.directory.demand_hits 0 # Number of cache demand hits 2848system.tccdir_cntrl0.directory.demand_misses 0 # Number of cache demand misses 2849system.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses |
| 2806system.tccdir_cntrl0.directory.num_tag_array_reads 1554 # number of tag array reads 2807system.tccdir_cntrl0.directory.num_tag_array_writes 27 # number of tag array writes 2808system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2809system.ruby.network.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2810system.ruby.network.msg_count.Control 3116 2811system.ruby.network.msg_count.Request_Control 3121 2812system.ruby.network.msg_count.Response_Data 3159 2813system.ruby.network.msg_count.Response_Control 3078 2814system.ruby.network.msg_count.Unblock_Control 3121 2815system.ruby.network.msg_byte.Control 24928 2816system.ruby.network.msg_byte.Request_Control 24968 2817system.ruby.network.msg_byte.Response_Data 227448 2818system.ruby.network.msg_byte.Response_Control 24624 2819system.ruby.network.msg_byte.Unblock_Control 24968 | 2850system.tccdir_cntrl0.directory.num_tag_array_reads 1552 # number of tag array reads 2851system.tccdir_cntrl0.directory.num_tag_array_writes 25 # number of tag array writes 2852system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 2853system.ruby.network.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 2854system.ruby.network.msg_count.Control 3112 2855system.ruby.network.msg_count.Request_Control 3115 2856system.ruby.network.msg_count.Response_Data 3153 2857system.ruby.network.msg_count.Response_Control 3074 2858system.ruby.network.msg_count.Unblock_Control 3115 2859system.ruby.network.msg_byte.Control 24896 2860system.ruby.network.msg_byte.Request_Control 24920 2861system.ruby.network.msg_byte.Response_Data 227016 2862system.ruby.network.msg_byte.Response_Control 24592 2863system.ruby.network.msg_byte.Unblock_Control 24920 |
| 2820system.sqc_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2821system.sqc_coalescer.clk_domain.clock 1000 # Clock period in ticks | 2864system.sqc_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2865system.sqc_coalescer.clk_domain.clock 1000 # Clock period in ticks |
| 2822system.sqc_coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2823system.sqc_coalescer.uncoalesced_accesses 86 # Number of uncoalesced TLB accesses 2824system.sqc_coalescer.coalesced_accesses 60 # Number of coalesced TLB accesses 2825system.sqc_coalescer.queuing_cycles 108000 # Number of cycles spent in queue 2826system.sqc_coalescer.local_queuing_cycles 108000 # Number of cycles spent in queue for all incoming reqs 2827system.sqc_coalescer.local_latency 1255.813953 # Avg. latency over all incoming pkts | 2866system.sqc_coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 2867system.sqc_coalescer.uncoalesced_accesses 70 # Number of uncoalesced TLB accesses 2868system.sqc_coalescer.coalesced_accesses 50 # Number of coalesced TLB accesses 2869system.sqc_coalescer.queuing_cycles 100000 # Number of cycles spent in queue 2870system.sqc_coalescer.local_queuing_cycles 100000 # Number of cycles spent in queue for all incoming reqs 2871system.sqc_coalescer.local_latency 1428.571429 # Avg. latency over all incoming pkts |
| 2828system.sqc_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2829system.sqc_tlb.clk_domain.clock 1000 # Clock period in ticks | 2872system.sqc_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2873system.sqc_tlb.clk_domain.clock 1000 # Clock period in ticks |
| 2830system.sqc_tlb.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2831system.sqc_tlb.local_TLB_accesses 60 # Number of TLB accesses 2832system.sqc_tlb.local_TLB_hits 59 # Number of TLB hits | 2874system.sqc_tlb.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 2875system.sqc_tlb.local_TLB_accesses 50 # Number of TLB accesses 2876system.sqc_tlb.local_TLB_hits 49 # Number of TLB hits |
| 2833system.sqc_tlb.local_TLB_misses 1 # Number of TLB misses | 2877system.sqc_tlb.local_TLB_misses 1 # Number of TLB misses |
| 2834system.sqc_tlb.local_TLB_miss_rate 1.666667 # TLB miss rate 2835system.sqc_tlb.global_TLB_accesses 86 # Number of TLB accesses 2836system.sqc_tlb.global_TLB_hits 78 # Number of TLB hits | 2878system.sqc_tlb.local_TLB_miss_rate 2 # TLB miss rate 2879system.sqc_tlb.global_TLB_accesses 70 # Number of TLB accesses 2880system.sqc_tlb.global_TLB_hits 62 # Number of TLB hits |
| 2837system.sqc_tlb.global_TLB_misses 8 # Number of TLB misses | 2881system.sqc_tlb.global_TLB_misses 8 # Number of TLB misses |
| 2838system.sqc_tlb.global_TLB_miss_rate 9.302326 # TLB miss rate 2839system.sqc_tlb.access_cycles 86008 # Cycles spent accessing this TLB level | 2882system.sqc_tlb.global_TLB_miss_rate 11.428571 # TLB miss rate 2883system.sqc_tlb.access_cycles 70008 # Cycles spent accessing this TLB level |
| 2840system.sqc_tlb.page_table_cycles 0 # Cycles spent accessing the page table 2841system.sqc_tlb.unique_pages 1 # Number of unique pages touched | 2884system.sqc_tlb.page_table_cycles 0 # Cycles spent accessing the page table 2885system.sqc_tlb.unique_pages 1 # Number of unique pages touched |
| 2842system.sqc_tlb.local_cycles 60001 # Number of cycles spent in queue for all incoming reqs 2843system.sqc_tlb.local_latency 1000.016667 # Avg. latency over incoming coalesced reqs | 2886system.sqc_tlb.local_cycles 50001 # Number of cycles spent in queue for all incoming reqs 2887system.sqc_tlb.local_latency 1000.020000 # Avg. latency over incoming coalesced reqs |
| 2844system.sqc_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) | 2888system.sqc_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) |
| 2845system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2846system.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.005553 2847system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1551 | 2889system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 2890system.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.005552 2891system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1549 |
| 2848system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Data::2 12 | 2892system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Data::2 12 |
| 2849system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2 1539 2850system.ruby.network.ext_links0.int_node.throttle0.msg_count.Unblock_Control::4 1551 2851system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0 12408 | 2893system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2 1537 2894system.ruby.network.ext_links0.int_node.throttle0.msg_count.Unblock_Control::4 1549 2895system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0 12392 |
| 2852system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Data::2 864 | 2896system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Data::2 864 |
| 2853system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Control::2 12312 2854system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Unblock_Control::4 12408 2855system.ruby.network.ext_links0.int_node.throttle1.link_utilization 0.016173 2856system.ruby.network.ext_links0.int_node.throttle1.msg_count.Control::0 16 | 2897system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Control::2 12296 2898system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Unblock_Control::4 12392 2899system.ruby.network.ext_links0.int_node.throttle1.link_utilization 0.016188 2900system.ruby.network.ext_links0.int_node.throttle1.msg_count.Control::0 14 |
| 2857system.ruby.network.ext_links0.int_node.throttle1.msg_count.Response_Data::2 1535 | 2901system.ruby.network.ext_links0.int_node.throttle1.msg_count.Response_Data::2 1535 |
| 2858system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Control::0 128 | 2902system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Control::0 112 |
| 2859system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Response_Data::2 110520 | 2903system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Response_Data::2 110520 |
| 2860system.ruby.network.ext_links0.int_node.throttle2.link_utilization 0.001963 | 2904system.ruby.network.ext_links0.int_node.throttle2.link_utilization 0.001944 |
| 2861system.ruby.network.ext_links0.int_node.throttle2.msg_count.Control::0 1535 | 2905system.ruby.network.ext_links0.int_node.throttle2.msg_count.Control::0 1535 |
| 2862system.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Data::2 16 | 2906system.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Data::2 14 |
| 2863system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Control::0 12280 | 2907system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Control::0 12280 |
| 2864system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Data::2 1152 2865system.ruby.network.ext_links1.int_node.throttle0.link_utilization 0.016173 2866system.ruby.network.ext_links1.int_node.throttle0.msg_count.Control::0 16 | 2908system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Data::2 1008 2909system.ruby.network.ext_links1.int_node.throttle0.link_utilization 0.016188 2910system.ruby.network.ext_links1.int_node.throttle0.msg_count.Control::0 14 |
| 2867system.ruby.network.ext_links1.int_node.throttle0.msg_count.Response_Data::2 1535 | 2911system.ruby.network.ext_links1.int_node.throttle0.msg_count.Response_Data::2 1535 |
| 2868system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Control::0 128 | 2912system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Control::0 112 |
| 2869system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Response_Data::2 110520 | 2913system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Response_Data::2 110520 |
| 2870system.ruby.network.ext_links1.int_node.throttle1.link_utilization 0.003627 | 2914system.ruby.network.ext_links1.int_node.throttle1.link_utilization 0.003629 |
| 2871system.ruby.network.ext_links1.int_node.throttle1.msg_count.Request_Control::0 1535 2872system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Data::2 2 | 2915system.ruby.network.ext_links1.int_node.throttle1.msg_count.Request_Control::0 1535 2916system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Data::2 2 |
| 2873system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Control::2 14 | 2917system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Control::2 12 |
| 2874system.ruby.network.ext_links1.int_node.throttle1.msg_count.Unblock_Control::4 1535 2875system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Request_Control::0 12280 2876system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Data::2 144 | 2918system.ruby.network.ext_links1.int_node.throttle1.msg_count.Unblock_Control::4 1535 2919system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Request_Control::0 12280 2920system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Data::2 144 |
| 2877system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Control::2 112 | 2921system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Control::2 96 |
| 2878system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Unblock_Control::4 12280 2879system.ruby.network.ext_links2.int_node.throttle0.link_utilization 0.000083 2880system.ruby.network.ext_links2.int_node.throttle0.msg_count.Control::1 8 2881system.ruby.network.ext_links2.int_node.throttle0.msg_count.Response_Data::3 7 2882system.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Control::1 64 2883system.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Response_Data::3 504 2884system.ruby.network.ext_links2.int_node.throttle1.link_utilization 0.000081 2885system.ruby.network.ext_links2.int_node.throttle1.msg_count.Control::1 6 2886system.ruby.network.ext_links2.int_node.throttle1.msg_count.Response_Data::3 7 2887system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Control::1 48 2888system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Response_Data::3 504 2889system.ruby.network.ext_links2.int_node.throttle2.link_utilization 0 | 2922system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Unblock_Control::4 12280 2923system.ruby.network.ext_links2.int_node.throttle0.link_utilization 0.000083 2924system.ruby.network.ext_links2.int_node.throttle0.msg_count.Control::1 8 2925system.ruby.network.ext_links2.int_node.throttle0.msg_count.Response_Data::3 7 2926system.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Control::1 64 2927system.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Response_Data::3 504 2928system.ruby.network.ext_links2.int_node.throttle1.link_utilization 0.000081 2929system.ruby.network.ext_links2.int_node.throttle1.msg_count.Control::1 6 2930system.ruby.network.ext_links2.int_node.throttle1.msg_count.Response_Data::3 7 2931system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Control::1 48 2932system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Response_Data::3 504 2933system.ruby.network.ext_links2.int_node.throttle2.link_utilization 0 |
| 2890system.ruby.network.ext_links2.int_node.throttle3.link_utilization 0.002155 | 2934system.ruby.network.ext_links2.int_node.throttle3.link_utilization 0.002132 |
| 2891system.ruby.network.ext_links2.int_node.throttle3.msg_count.Control::0 1535 | 2935system.ruby.network.ext_links2.int_node.throttle3.msg_count.Control::0 1535 |
| 2892system.ruby.network.ext_links2.int_node.throttle3.msg_count.Request_Control::1 19 2893system.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::2 16 | 2936system.ruby.network.ext_links2.int_node.throttle3.msg_count.Request_Control::1 17 2937system.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::2 14 |
| 2894system.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::3 14 | 2938system.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::3 14 |
| 2895system.ruby.network.ext_links2.int_node.throttle3.msg_count.Unblock_Control::5 19 | 2939system.ruby.network.ext_links2.int_node.throttle3.msg_count.Unblock_Control::5 17 |
| 2896system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Control::0 12280 | 2940system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Control::0 12280 |
| 2897system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Request_Control::1 152 2898system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Response_Data::2 1152 | 2941system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Request_Control::1 136 2942system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Response_Data::2 1008 |
| 2899system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Response_Data::3 1008 | 2943system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Response_Data::3 1008 |
| 2900system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Unblock_Control::5 152 2901system.ruby.network.ext_links2.int_node.throttle4.link_utilization 0.000053 2902system.ruby.network.ext_links2.int_node.throttle4.msg_count.Response_Data::3 5 2903system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Response_Data::3 360 2904system.ruby.network.ext_links2.int_node.throttle5.link_utilization 0.001926 2905system.ruby.network.ext_links2.int_node.throttle5.msg_count.Request_Control::0 16 | 2944system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Unblock_Control::5 136 2945system.ruby.network.ext_links2.int_node.throttle4.link_utilization 0.000032 2946system.ruby.network.ext_links2.int_node.throttle4.msg_count.Response_Data::3 3 2947system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Response_Data::3 216 2948system.ruby.network.ext_links2.int_node.throttle5.link_utilization 0.001923 2949system.ruby.network.ext_links2.int_node.throttle5.msg_count.Request_Control::0 14 |
| 2906system.ruby.network.ext_links2.int_node.throttle5.msg_count.Response_Data::2 10 2907system.ruby.network.ext_links2.int_node.throttle5.msg_count.Response_Control::2 1525 | 2950system.ruby.network.ext_links2.int_node.throttle5.msg_count.Response_Data::2 10 2951system.ruby.network.ext_links2.int_node.throttle5.msg_count.Response_Control::2 1525 |
| 2908system.ruby.network.ext_links2.int_node.throttle5.msg_count.Unblock_Control::4 16 2909system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Request_Control::0 128 | 2952system.ruby.network.ext_links2.int_node.throttle5.msg_count.Unblock_Control::4 14 2953system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Request_Control::0 112 |
| 2910system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Response_Data::2 720 2911system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Response_Control::2 12200 | 2954system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Response_Data::2 720 2955system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Response_Control::2 12200 |
| 2912system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Unblock_Control::4 128 | 2956system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Unblock_Control::4 112 |
| 2913system.ruby.CorePair_Controller.C0_Load_L1miss 180 0.00% 0.00% 2914system.ruby.CorePair_Controller.C0_Load_L1hit 16155 0.00% 0.00% 2915system.ruby.CorePair_Controller.Ifetch0_L1hit 86007 0.00% 0.00% 2916system.ruby.CorePair_Controller.Ifetch0_L1miss 1088 0.00% 0.00% 2917system.ruby.CorePair_Controller.C0_Store_L1miss 325 0.00% 0.00% 2918system.ruby.CorePair_Controller.C0_Store_L1hit 10448 0.00% 0.00% 2919system.ruby.CorePair_Controller.NB_AckS 1043 0.00% 0.00% 2920system.ruby.CorePair_Controller.NB_AckM 326 0.00% 0.00% 2921system.ruby.CorePair_Controller.NB_AckE 166 0.00% 0.00% 2922system.ruby.CorePair_Controller.L1I_Repl 589 0.00% 0.00% 2923system.ruby.CorePair_Controller.L1D0_Repl 24 0.00% 0.00% 2924system.ruby.CorePair_Controller.L2_to_L1D0 5 0.00% 0.00% 2925system.ruby.CorePair_Controller.L2_to_L1I 54 0.00% 0.00% 2926system.ruby.CorePair_Controller.PrbInvData 9 0.00% 0.00% | 2957system.ruby.CorePair_Controller.C0_Load_L1miss 180 0.00% 0.00% 2958system.ruby.CorePair_Controller.C0_Load_L1hit 16155 0.00% 0.00% 2959system.ruby.CorePair_Controller.Ifetch0_L1hit 86007 0.00% 0.00% 2960system.ruby.CorePair_Controller.Ifetch0_L1miss 1088 0.00% 0.00% 2961system.ruby.CorePair_Controller.C0_Store_L1miss 325 0.00% 0.00% 2962system.ruby.CorePair_Controller.C0_Store_L1hit 10448 0.00% 0.00% 2963system.ruby.CorePair_Controller.NB_AckS 1043 0.00% 0.00% 2964system.ruby.CorePair_Controller.NB_AckM 326 0.00% 0.00% 2965system.ruby.CorePair_Controller.NB_AckE 166 0.00% 0.00% 2966system.ruby.CorePair_Controller.L1I_Repl 589 0.00% 0.00% 2967system.ruby.CorePair_Controller.L1D0_Repl 24 0.00% 0.00% 2968system.ruby.CorePair_Controller.L2_to_L1D0 5 0.00% 0.00% 2969system.ruby.CorePair_Controller.L2_to_L1I 54 0.00% 0.00% 2970system.ruby.CorePair_Controller.PrbInvData 9 0.00% 0.00% |
| 2927system.ruby.CorePair_Controller.PrbShrData 7 0.00% 0.00% | 2971system.ruby.CorePair_Controller.PrbShrData 5 0.00% 0.00% |
| 2928system.ruby.CorePair_Controller.I.C0_Load_L1miss 175 0.00% 0.00% 2929system.ruby.CorePair_Controller.I.Ifetch0_L1miss 1034 0.00% 0.00% 2930system.ruby.CorePair_Controller.I.C0_Store_L1miss 325 0.00% 0.00% 2931system.ruby.CorePair_Controller.I.PrbInvData 8 0.00% 0.00% | 2972system.ruby.CorePair_Controller.I.C0_Load_L1miss 175 0.00% 0.00% 2973system.ruby.CorePair_Controller.I.Ifetch0_L1miss 1034 0.00% 0.00% 2974system.ruby.CorePair_Controller.I.C0_Store_L1miss 325 0.00% 0.00% 2975system.ruby.CorePair_Controller.I.PrbInvData 8 0.00% 0.00% |
| 2932system.ruby.CorePair_Controller.I.PrbShrData 5 0.00% 0.00% | 2976system.ruby.CorePair_Controller.I.PrbShrData 3 0.00% 0.00% |
| 2933system.ruby.CorePair_Controller.S.C0_Load_L1hit 635 0.00% 0.00% 2934system.ruby.CorePair_Controller.S.Ifetch0_L1hit 86007 0.00% 0.00% 2935system.ruby.CorePair_Controller.S.Ifetch0_L1miss 54 0.00% 0.00% 2936system.ruby.CorePair_Controller.S.L1I_Repl 589 0.00% 0.00% 2937system.ruby.CorePair_Controller.E0.C0_Load_L1miss 2 0.00% 0.00% 2938system.ruby.CorePair_Controller.E0.C0_Load_L1hit 2721 0.00% 0.00% 2939system.ruby.CorePair_Controller.E0.C0_Store_L1hit 46 0.00% 0.00% 2940system.ruby.CorePair_Controller.E0.L1D0_Repl 16 0.00% 0.00% --- 9 unchanged lines hidden (view full) --- 2950system.ruby.CorePair_Controller.I_M0.NB_AckM 325 0.00% 0.00% 2951system.ruby.CorePair_Controller.I_E0S.NB_AckS 9 0.00% 0.00% 2952system.ruby.CorePair_Controller.I_E0S.NB_AckE 166 0.00% 0.00% 2953system.ruby.CorePair_Controller.Si_F0.L2_to_L1I 54 0.00% 0.00% 2954system.ruby.CorePair_Controller.O_M0.NB_AckM 1 0.00% 0.00% 2955system.ruby.CorePair_Controller.S0.NB_AckS 1034 0.00% 0.00% 2956system.ruby.CorePair_Controller.E0_F.L2_to_L1D0 2 0.00% 0.00% 2957system.ruby.CorePair_Controller.M0_F.L2_to_L1D0 3 0.00% 0.00% | 2977system.ruby.CorePair_Controller.S.C0_Load_L1hit 635 0.00% 0.00% 2978system.ruby.CorePair_Controller.S.Ifetch0_L1hit 86007 0.00% 0.00% 2979system.ruby.CorePair_Controller.S.Ifetch0_L1miss 54 0.00% 0.00% 2980system.ruby.CorePair_Controller.S.L1I_Repl 589 0.00% 0.00% 2981system.ruby.CorePair_Controller.E0.C0_Load_L1miss 2 0.00% 0.00% 2982system.ruby.CorePair_Controller.E0.C0_Load_L1hit 2721 0.00% 0.00% 2983system.ruby.CorePair_Controller.E0.C0_Store_L1hit 46 0.00% 0.00% 2984system.ruby.CorePair_Controller.E0.L1D0_Repl 16 0.00% 0.00% --- 9 unchanged lines hidden (view full) --- 2994system.ruby.CorePair_Controller.I_M0.NB_AckM 325 0.00% 0.00% 2995system.ruby.CorePair_Controller.I_E0S.NB_AckS 9 0.00% 0.00% 2996system.ruby.CorePair_Controller.I_E0S.NB_AckE 166 0.00% 0.00% 2997system.ruby.CorePair_Controller.Si_F0.L2_to_L1I 54 0.00% 0.00% 2998system.ruby.CorePair_Controller.O_M0.NB_AckM 1 0.00% 0.00% 2999system.ruby.CorePair_Controller.S0.NB_AckS 1034 0.00% 0.00% 3000system.ruby.CorePair_Controller.E0_F.L2_to_L1D0 2 0.00% 0.00% 3001system.ruby.CorePair_Controller.M0_F.L2_to_L1D0 3 0.00% 0.00% |
| 2958system.ruby.Directory_Controller.RdBlkS 1039 0.00% 0.00% | 3002system.ruby.Directory_Controller.RdBlkS 1037 0.00% 0.00% |
| 2959system.ruby.Directory_Controller.RdBlkM 335 0.00% 0.00% 2960system.ruby.Directory_Controller.RdBlk 177 0.00% 0.00% | 3003system.ruby.Directory_Controller.RdBlkM 335 0.00% 0.00% 3004system.ruby.Directory_Controller.RdBlk 177 0.00% 0.00% |
| 2961system.ruby.Directory_Controller.CPUPrbResp 1551 0.00% 0.00% 2962system.ruby.Directory_Controller.ProbeAcksComplete 1551 0.00% 0.00% 2963system.ruby.Directory_Controller.MemData 1551 0.00% 0.00% 2964system.ruby.Directory_Controller.CoreUnblock 1551 0.00% 0.00% 2965system.ruby.Directory_Controller.U.RdBlkS 1039 0.00% 0.00% | 3005system.ruby.Directory_Controller.CPUPrbResp 1549 0.00% 0.00% 3006system.ruby.Directory_Controller.ProbeAcksComplete 1549 0.00% 0.00% 3007system.ruby.Directory_Controller.MemData 1549 0.00% 0.00% 3008system.ruby.Directory_Controller.CoreUnblock 1549 0.00% 0.00% 3009system.ruby.Directory_Controller.U.RdBlkS 1037 0.00% 0.00% |
| 2966system.ruby.Directory_Controller.U.RdBlkM 335 0.00% 0.00% 2967system.ruby.Directory_Controller.U.RdBlk 177 0.00% 0.00% | 3010system.ruby.Directory_Controller.U.RdBlkM 335 0.00% 0.00% 3011system.ruby.Directory_Controller.U.RdBlk 177 0.00% 0.00% |
| 2968system.ruby.Directory_Controller.BS_M.MemData 36 0.00% 0.00% 2969system.ruby.Directory_Controller.BM_M.MemData 13 0.00% 0.00% 2970system.ruby.Directory_Controller.B_M.MemData 12 0.00% 0.00% 2971system.ruby.Directory_Controller.BS_PM.CPUPrbResp 36 0.00% 0.00% 2972system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 36 0.00% 0.00% 2973system.ruby.Directory_Controller.BS_PM.MemData 1003 0.00% 0.00% 2974system.ruby.Directory_Controller.BM_PM.CPUPrbResp 14 0.00% 0.00% 2975system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 13 0.00% 0.00% 2976system.ruby.Directory_Controller.BM_PM.MemData 322 0.00% 0.00% 2977system.ruby.Directory_Controller.B_PM.CPUPrbResp 12 0.00% 0.00% 2978system.ruby.Directory_Controller.B_PM.ProbeAcksComplete 12 0.00% 0.00% 2979system.ruby.Directory_Controller.B_PM.MemData 165 0.00% 0.00% 2980system.ruby.Directory_Controller.BS_Pm.CPUPrbResp 1003 0.00% 0.00% 2981system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 1003 0.00% 0.00% 2982system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 321 0.00% 0.00% 2983system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 322 0.00% 0.00% 2984system.ruby.Directory_Controller.B_Pm.CPUPrbResp 165 0.00% 0.00% 2985system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 165 0.00% 0.00% 2986system.ruby.Directory_Controller.B.CoreUnblock 1551 0.00% 0.00% | 3012system.ruby.Directory_Controller.BS_M.MemData 35 0.00% 0.00% 3013system.ruby.Directory_Controller.BM_M.MemData 18 0.00% 0.00% 3014system.ruby.Directory_Controller.B_M.MemData 11 0.00% 0.00% 3015system.ruby.Directory_Controller.BS_PM.CPUPrbResp 35 0.00% 0.00% 3016system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 35 0.00% 0.00% 3017system.ruby.Directory_Controller.BS_PM.MemData 1002 0.00% 0.00% 3018system.ruby.Directory_Controller.BM_PM.CPUPrbResp 18 0.00% 0.00% 3019system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 18 0.00% 0.00% 3020system.ruby.Directory_Controller.BM_PM.MemData 317 0.00% 0.00% 3021system.ruby.Directory_Controller.B_PM.CPUPrbResp 11 0.00% 0.00% 3022system.ruby.Directory_Controller.B_PM.ProbeAcksComplete 11 0.00% 0.00% 3023system.ruby.Directory_Controller.B_PM.MemData 166 0.00% 0.00% 3024system.ruby.Directory_Controller.BS_Pm.CPUPrbResp 1002 0.00% 0.00% 3025system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 1002 0.00% 0.00% 3026system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 317 0.00% 0.00% 3027system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 317 0.00% 0.00% 3028system.ruby.Directory_Controller.B_Pm.CPUPrbResp 166 0.00% 0.00% 3029system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 166 0.00% 0.00% 3030system.ruby.Directory_Controller.B.CoreUnblock 1549 0.00% 0.00% |
| 2987system.ruby.LD.latency_hist_seqr::bucket_size 64 2988system.ruby.LD.latency_hist_seqr::max_bucket 639 2989system.ruby.LD.latency_hist_seqr::samples 16335 2990system.ruby.LD.latency_hist_seqr::mean 4.314539 2991system.ruby.LD.latency_hist_seqr::gmean 2.104196 2992system.ruby.LD.latency_hist_seqr::stdev 22.794494 2993system.ruby.LD.latency_hist_seqr | 16160 98.93% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 166 1.02% 99.94% | 6 0.04% 99.98% | 1 0.01% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 2 0.01% 100.00% 2994system.ruby.LD.latency_hist_seqr::total 16335 2995system.ruby.LD.latency_hist_coalsr::bucket_size 64 2996system.ruby.LD.latency_hist_coalsr::max_bucket 639 2997system.ruby.LD.latency_hist_coalsr::samples 9 | 3031system.ruby.LD.latency_hist_seqr::bucket_size 64 3032system.ruby.LD.latency_hist_seqr::max_bucket 639 3033system.ruby.LD.latency_hist_seqr::samples 16335 3034system.ruby.LD.latency_hist_seqr::mean 4.314539 3035system.ruby.LD.latency_hist_seqr::gmean 2.104196 3036system.ruby.LD.latency_hist_seqr::stdev 22.794494 3037system.ruby.LD.latency_hist_seqr | 16160 98.93% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 166 1.02% 99.94% | 6 0.04% 99.98% | 1 0.01% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 2 0.01% 100.00% 3038system.ruby.LD.latency_hist_seqr::total 16335 3039system.ruby.LD.latency_hist_coalsr::bucket_size 64 3040system.ruby.LD.latency_hist_coalsr::max_bucket 639 3041system.ruby.LD.latency_hist_coalsr::samples 9 |
| 2998system.ruby.LD.latency_hist_coalsr::mean 219.555556 2999system.ruby.LD.latency_hist_coalsr::gmean 24.880500 3000system.ruby.LD.latency_hist_coalsr::stdev 259.591078 3001system.ruby.LD.latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 1 11.11% 66.67% | 1 11.11% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% | 3042system.ruby.LD.latency_hist_coalsr::mean 133.666667 3043system.ruby.LD.latency_hist_coalsr::gmean 19.860866 3044system.ruby.LD.latency_hist_coalsr::stdev 158.801763 3045system.ruby.LD.latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 1 11.11% 66.67% | 1 11.11% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 3002system.ruby.LD.latency_hist_coalsr::total 9 3003system.ruby.LD.hit_latency_hist_seqr::bucket_size 64 3004system.ruby.LD.hit_latency_hist_seqr::max_bucket 639 3005system.ruby.LD.hit_latency_hist_seqr::samples 175 3006system.ruby.LD.hit_latency_hist_seqr::mean 217.531429 3007system.ruby.LD.hit_latency_hist_seqr::gmean 214.409561 3008system.ruby.LD.hit_latency_hist_seqr::stdev 50.482703 3009system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 166 94.86% 94.86% | 6 3.43% 98.29% | 1 0.57% 98.86% | 0 0.00% 98.86% | 0 0.00% 98.86% | 0 0.00% 98.86% | 2 1.14% 100.00% --- 4 unchanged lines hidden (view full) --- 3014system.ruby.LD.miss_latency_hist_seqr::mean 2.005569 3015system.ruby.LD.miss_latency_hist_seqr::gmean 2.001425 3016system.ruby.LD.miss_latency_hist_seqr::stdev 0.316580 3017system.ruby.LD.miss_latency_hist_seqr | 16155 99.97% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 5 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 3018system.ruby.LD.miss_latency_hist_seqr::total 16160 3019system.ruby.LD.miss_latency_hist_coalsr::bucket_size 64 3020system.ruby.LD.miss_latency_hist_coalsr::max_bucket 639 3021system.ruby.LD.miss_latency_hist_coalsr::samples 9 | 3046system.ruby.LD.latency_hist_coalsr::total 9 3047system.ruby.LD.hit_latency_hist_seqr::bucket_size 64 3048system.ruby.LD.hit_latency_hist_seqr::max_bucket 639 3049system.ruby.LD.hit_latency_hist_seqr::samples 175 3050system.ruby.LD.hit_latency_hist_seqr::mean 217.531429 3051system.ruby.LD.hit_latency_hist_seqr::gmean 214.409561 3052system.ruby.LD.hit_latency_hist_seqr::stdev 50.482703 3053system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 166 94.86% 94.86% | 6 3.43% 98.29% | 1 0.57% 98.86% | 0 0.00% 98.86% | 0 0.00% 98.86% | 0 0.00% 98.86% | 2 1.14% 100.00% --- 4 unchanged lines hidden (view full) --- 3058system.ruby.LD.miss_latency_hist_seqr::mean 2.005569 3059system.ruby.LD.miss_latency_hist_seqr::gmean 2.001425 3060system.ruby.LD.miss_latency_hist_seqr::stdev 0.316580 3061system.ruby.LD.miss_latency_hist_seqr | 16155 99.97% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 5 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 3062system.ruby.LD.miss_latency_hist_seqr::total 16160 3063system.ruby.LD.miss_latency_hist_coalsr::bucket_size 64 3064system.ruby.LD.miss_latency_hist_coalsr::max_bucket 639 3065system.ruby.LD.miss_latency_hist_coalsr::samples 9 |
| 3022system.ruby.LD.miss_latency_hist_coalsr::mean 219.555556 3023system.ruby.LD.miss_latency_hist_coalsr::gmean 24.880500 3024system.ruby.LD.miss_latency_hist_coalsr::stdev 259.591078 3025system.ruby.LD.miss_latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 1 11.11% 66.67% | 1 11.11% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% | 3066system.ruby.LD.miss_latency_hist_coalsr::mean 133.666667 3067system.ruby.LD.miss_latency_hist_coalsr::gmean 19.860866 3068system.ruby.LD.miss_latency_hist_coalsr::stdev 158.801763 3069system.ruby.LD.miss_latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 1 11.11% 66.67% | 1 11.11% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 3026system.ruby.LD.miss_latency_hist_coalsr::total 9 3027system.ruby.ST.latency_hist_seqr::bucket_size 64 3028system.ruby.ST.latency_hist_seqr::max_bucket 639 3029system.ruby.ST.latency_hist_seqr::samples 10412 3030system.ruby.ST.latency_hist_seqr::mean 8.469939 3031system.ruby.ST.latency_hist_seqr::gmean 2.309412 3032system.ruby.ST.latency_hist_seqr::stdev 36.833690 3033system.ruby.ST.latency_hist_seqr | 10090 96.91% 96.91% | 0 0.00% 96.91% | 0 0.00% 96.91% | 314 3.02% 99.92% | 1 0.01% 99.93% | 5 0.05% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 2 0.02% 100.00% 3034system.ruby.ST.latency_hist_seqr::total 10412 | 3070system.ruby.LD.miss_latency_hist_coalsr::total 9 3071system.ruby.ST.latency_hist_seqr::bucket_size 64 3072system.ruby.ST.latency_hist_seqr::max_bucket 639 3073system.ruby.ST.latency_hist_seqr::samples 10412 3074system.ruby.ST.latency_hist_seqr::mean 8.469939 3075system.ruby.ST.latency_hist_seqr::gmean 2.309412 3076system.ruby.ST.latency_hist_seqr::stdev 36.833690 3077system.ruby.ST.latency_hist_seqr | 10090 96.91% 96.91% | 0 0.00% 96.91% | 0 0.00% 96.91% | 314 3.02% 99.92% | 1 0.01% 99.93% | 5 0.05% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 2 0.02% 100.00% 3078system.ruby.ST.latency_hist_seqr::total 10412 |
| 3035system.ruby.ST.latency_hist_coalsr::bucket_size 32 3036system.ruby.ST.latency_hist_coalsr::max_bucket 319 | 3079system.ruby.ST.latency_hist_coalsr::bucket_size 64 3080system.ruby.ST.latency_hist_coalsr::max_bucket 639 |
| 3037system.ruby.ST.latency_hist_coalsr::samples 16 | 3081system.ruby.ST.latency_hist_coalsr::samples 16 |
| 3038system.ruby.ST.latency_hist_coalsr::mean 125.375000 3039system.ruby.ST.latency_hist_coalsr::gmean 15.802815 3040system.ruby.ST.latency_hist_coalsr::stdev 128.476133 3041system.ruby.ST.latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 7 43.75% 93.75% | 1 6.25% 100.00% | 0 0.00% 100.00% | 3082system.ruby.ST.latency_hist_coalsr::mean 184.500000 3083system.ruby.ST.latency_hist_coalsr::gmean 27.004823 3084system.ruby.ST.latency_hist_coalsr::stdev 190.921974 3085system.ruby.ST.latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 4 25.00% 75.00% | 4 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 3042system.ruby.ST.latency_hist_coalsr::total 16 3043system.ruby.ST.hit_latency_hist_seqr::bucket_size 64 3044system.ruby.ST.hit_latency_hist_seqr::max_bucket 639 3045system.ruby.ST.hit_latency_hist_seqr::samples 322 3046system.ruby.ST.hit_latency_hist_seqr::mean 211.208075 3047system.ruby.ST.hit_latency_hist_seqr::gmean 209.444324 3048system.ruby.ST.hit_latency_hist_seqr::stdev 38.157121 3049system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 314 97.52% 97.52% | 1 0.31% 97.83% | 5 1.55% 99.38% | 0 0.00% 99.38% | 0 0.00% 99.38% | 0 0.00% 99.38% | 2 0.62% 100.00% 3050system.ruby.ST.hit_latency_hist_seqr::total 322 3051system.ruby.ST.miss_latency_hist_seqr::bucket_size 1 3052system.ruby.ST.miss_latency_hist_seqr::max_bucket 9 3053system.ruby.ST.miss_latency_hist_seqr::samples 10090 3054system.ruby.ST.miss_latency_hist_seqr::mean 2 3055system.ruby.ST.miss_latency_hist_seqr::gmean 2.000000 3056system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10090 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 3057system.ruby.ST.miss_latency_hist_seqr::total 10090 | 3086system.ruby.ST.latency_hist_coalsr::total 16 3087system.ruby.ST.hit_latency_hist_seqr::bucket_size 64 3088system.ruby.ST.hit_latency_hist_seqr::max_bucket 639 3089system.ruby.ST.hit_latency_hist_seqr::samples 322 3090system.ruby.ST.hit_latency_hist_seqr::mean 211.208075 3091system.ruby.ST.hit_latency_hist_seqr::gmean 209.444324 3092system.ruby.ST.hit_latency_hist_seqr::stdev 38.157121 3093system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 314 97.52% 97.52% | 1 0.31% 97.83% | 5 1.55% 99.38% | 0 0.00% 99.38% | 0 0.00% 99.38% | 0 0.00% 99.38% | 2 0.62% 100.00% 3094system.ruby.ST.hit_latency_hist_seqr::total 322 3095system.ruby.ST.miss_latency_hist_seqr::bucket_size 1 3096system.ruby.ST.miss_latency_hist_seqr::max_bucket 9 3097system.ruby.ST.miss_latency_hist_seqr::samples 10090 3098system.ruby.ST.miss_latency_hist_seqr::mean 2 3099system.ruby.ST.miss_latency_hist_seqr::gmean 2.000000 3100system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10090 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 3101system.ruby.ST.miss_latency_hist_seqr::total 10090 |
| 3058system.ruby.ST.miss_latency_hist_coalsr::bucket_size 32 3059system.ruby.ST.miss_latency_hist_coalsr::max_bucket 319 | 3102system.ruby.ST.miss_latency_hist_coalsr::bucket_size 64 3103system.ruby.ST.miss_latency_hist_coalsr::max_bucket 639 |
| 3060system.ruby.ST.miss_latency_hist_coalsr::samples 16 | 3104system.ruby.ST.miss_latency_hist_coalsr::samples 16 |
| 3061system.ruby.ST.miss_latency_hist_coalsr::mean 125.375000 3062system.ruby.ST.miss_latency_hist_coalsr::gmean 15.802815 3063system.ruby.ST.miss_latency_hist_coalsr::stdev 128.476133 3064system.ruby.ST.miss_latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 7 43.75% 93.75% | 1 6.25% 100.00% | 0 0.00% 100.00% | 3105system.ruby.ST.miss_latency_hist_coalsr::mean 184.500000 3106system.ruby.ST.miss_latency_hist_coalsr::gmean 27.004823 3107system.ruby.ST.miss_latency_hist_coalsr::stdev 190.921974 3108system.ruby.ST.miss_latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 4 25.00% 75.00% | 4 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 3065system.ruby.ST.miss_latency_hist_coalsr::total 16 3066system.ruby.ATOMIC.latency_hist_coalsr::bucket_size 64 3067system.ruby.ATOMIC.latency_hist_coalsr::max_bucket 639 3068system.ruby.ATOMIC.latency_hist_coalsr::samples 2 | 3109system.ruby.ST.miss_latency_hist_coalsr::total 16 3110system.ruby.ATOMIC.latency_hist_coalsr::bucket_size 64 3111system.ruby.ATOMIC.latency_hist_coalsr::max_bucket 639 3112system.ruby.ATOMIC.latency_hist_coalsr::samples 2 |
| 3069system.ruby.ATOMIC.latency_hist_coalsr::mean 317.500000 3070system.ruby.ATOMIC.latency_hist_coalsr::gmean 314.366029 3071system.ruby.ATOMIC.latency_hist_coalsr::stdev 62.932504 | 3113system.ruby.ATOMIC.latency_hist_coalsr::mean 295.500000 3114system.ruby.ATOMIC.latency_hist_coalsr::gmean 293.237105 3115system.ruby.ATOMIC.latency_hist_coalsr::stdev 51.618795 |
| 3072system.ruby.ATOMIC.latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 3073system.ruby.ATOMIC.latency_hist_coalsr::total 2 3074system.ruby.ATOMIC.miss_latency_hist_coalsr::bucket_size 64 3075system.ruby.ATOMIC.miss_latency_hist_coalsr::max_bucket 639 3076system.ruby.ATOMIC.miss_latency_hist_coalsr::samples 2 | 3116system.ruby.ATOMIC.latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 3117system.ruby.ATOMIC.latency_hist_coalsr::total 2 3118system.ruby.ATOMIC.miss_latency_hist_coalsr::bucket_size 64 3119system.ruby.ATOMIC.miss_latency_hist_coalsr::max_bucket 639 3120system.ruby.ATOMIC.miss_latency_hist_coalsr::samples 2 |
| 3077system.ruby.ATOMIC.miss_latency_hist_coalsr::mean 317.500000 3078system.ruby.ATOMIC.miss_latency_hist_coalsr::gmean 314.366029 3079system.ruby.ATOMIC.miss_latency_hist_coalsr::stdev 62.932504 | 3121system.ruby.ATOMIC.miss_latency_hist_coalsr::mean 295.500000 3122system.ruby.ATOMIC.miss_latency_hist_coalsr::gmean 293.237105 3123system.ruby.ATOMIC.miss_latency_hist_coalsr::stdev 51.618795 |
| 3080system.ruby.ATOMIC.miss_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 3081system.ruby.ATOMIC.miss_latency_hist_coalsr::total 2 3082system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 3083system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 3084system.ruby.IFETCH.latency_hist_seqr::samples 87095 3085system.ruby.IFETCH.latency_hist_seqr::mean 4.485148 3086system.ruby.IFETCH.latency_hist_seqr::gmean 2.116532 3087system.ruby.IFETCH.latency_hist_seqr::stdev 22.815865 --- 85 unchanged lines hidden (view full) --- 3173system.ruby.Directory.hit_mach_latency_hist_seqr::mean 211.362215 3174system.ruby.Directory.hit_mach_latency_hist_seqr::gmean 209.793806 3175system.ruby.Directory.hit_mach_latency_hist_seqr::stdev 34.965177 3176system.ruby.Directory.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1490 97.07% 97.07% | 18 1.17% 98.24% | 18 1.17% 99.41% | 2 0.13% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 7 0.46% 100.00% 3177system.ruby.Directory.hit_mach_latency_hist_seqr::total 1535 3178system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::bucket_size 64 3179system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::max_bucket 639 3180system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::samples 3 | 3124system.ruby.ATOMIC.miss_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 3125system.ruby.ATOMIC.miss_latency_hist_coalsr::total 2 3126system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 3127system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 3128system.ruby.IFETCH.latency_hist_seqr::samples 87095 3129system.ruby.IFETCH.latency_hist_seqr::mean 4.485148 3130system.ruby.IFETCH.latency_hist_seqr::gmean 2.116532 3131system.ruby.IFETCH.latency_hist_seqr::stdev 22.815865 --- 85 unchanged lines hidden (view full) --- 3217system.ruby.Directory.hit_mach_latency_hist_seqr::mean 211.362215 3218system.ruby.Directory.hit_mach_latency_hist_seqr::gmean 209.793806 3219system.ruby.Directory.hit_mach_latency_hist_seqr::stdev 34.965177 3220system.ruby.Directory.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1490 97.07% 97.07% | 18 1.17% 98.24% | 18 1.17% 99.41% | 2 0.13% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 7 0.46% 100.00% 3221system.ruby.Directory.hit_mach_latency_hist_seqr::total 1535 3222system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::bucket_size 64 3223system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::max_bucket 639 3224system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::samples 3 |
| 3181system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean 478.666667 3182system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 470.839796 3183system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 101.159939 3184system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 2 66.67% 100.00% | 0 0.00% 100.00% | 3225system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean 338.666667 3226system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 338.633640 3227system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 5.773503 3228system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 3185system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::total 3 3186system.ruby.TCP.miss_mach_latency_hist_coalsr::bucket_size 1 3187system.ruby.TCP.miss_mach_latency_hist_coalsr::max_bucket 9 3188system.ruby.TCP.miss_mach_latency_hist_coalsr::samples 13 | 3229system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::total 3 3230system.ruby.TCP.miss_mach_latency_hist_coalsr::bucket_size 1 3231system.ruby.TCP.miss_mach_latency_hist_coalsr::max_bucket 9 3232system.ruby.TCP.miss_mach_latency_hist_coalsr::samples 13 |
| 3189system.ruby.TCP.miss_mach_latency_hist_coalsr::mean 1.538462 3190system.ruby.TCP.miss_mach_latency_hist_coalsr::gmean 1.377009 3191system.ruby.TCP.miss_mach_latency_hist_coalsr::stdev 0.877058 3192system.ruby.TCP.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 8 61.54% 61.54% | 4 30.77% 92.31% | 0 0.00% 92.31% | 1 7.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 3233system.ruby.TCP.miss_mach_latency_hist_coalsr::mean 2.153846 3234system.ruby.TCP.miss_mach_latency_hist_coalsr::gmean 2.109532 3235system.ruby.TCP.miss_mach_latency_hist_coalsr::stdev 0.554700 3236system.ruby.TCP.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 12 92.31% 92.31% | 0 0.00% 92.31% | 1 7.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 3193system.ruby.TCP.miss_mach_latency_hist_coalsr::total 13 3194system.ruby.TCCdir.miss_mach_latency_hist_coalsr::bucket_size 64 3195system.ruby.TCCdir.miss_mach_latency_hist_coalsr::max_bucket 639 3196system.ruby.TCCdir.miss_mach_latency_hist_coalsr::samples 11 | 3237system.ruby.TCP.miss_mach_latency_hist_coalsr::total 13 3238system.ruby.TCCdir.miss_mach_latency_hist_coalsr::bucket_size 64 3239system.ruby.TCCdir.miss_mach_latency_hist_coalsr::max_bucket 639 3240system.ruby.TCCdir.miss_mach_latency_hist_coalsr::samples 11 |
| 3197system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 287.363636 3198system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 279.637814 3199system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 78.345737 3200system.ruby.TCCdir.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 63.64% 63.64% | 2 18.18% 81.82% | 0 0.00% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 3241system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 336.545455 3242system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 330.845159 3243system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 64.151950 3244system.ruby.TCCdir.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 9.09% 9.09% | 2 18.18% 27.27% | 4 36.36% 63.64% | 4 36.36% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 3201system.ruby.TCCdir.miss_mach_latency_hist_coalsr::total 11 3202system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 3203system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 3204system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::samples 16155 3205system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 3206system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000 3207system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 16155 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 3208system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::total 16155 --- 10 unchanged lines hidden (view full) --- 3219system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::mean 217.531429 3220system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::gmean 214.409561 3221system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::stdev 50.482703 3222system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 166 94.86% 94.86% | 6 3.43% 98.29% | 1 0.57% 98.86% | 0 0.00% 98.86% | 0 0.00% 98.86% | 0 0.00% 98.86% | 2 1.14% 100.00% 3223system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::total 175 3224system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64 3225system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639 3226system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 2 | 3245system.ruby.TCCdir.miss_mach_latency_hist_coalsr::total 11 3246system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 3247system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 3248system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::samples 16155 3249system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 3250system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000 3251system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 16155 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 3252system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::total 16155 --- 10 unchanged lines hidden (view full) --- 3263system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::mean 217.531429 3264system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::gmean 214.409561 3265system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::stdev 50.482703 3266system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 166 94.86% 94.86% | 6 3.43% 98.29% | 1 0.57% 98.86% | 0 0.00% 98.86% | 0 0.00% 98.86% | 0 0.00% 98.86% | 2 1.14% 100.00% 3267system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::total 175 3268system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64 3269system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639 3270system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 2 |
| 3227system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 537 3228system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 536.976722 3229system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev 7.071068 3230system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 3271system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 342 3272system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 342.000000 3273system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 3231system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 2 3232system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 3233system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 3234system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::samples 5 3235system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::mean 2.400000 3236system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::gmean 2.297397 3237system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::stdev 0.894427 3238system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 80.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 3239system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::total 5 | 3274system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 2 3275system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 3276system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 3277system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::samples 5 3278system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::mean 2.400000 3279system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::gmean 2.297397 3280system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::stdev 0.894427 3281system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 80.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 3282system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::total 5 |
| 3240system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 64 3241system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 639 | 3283system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32 3284system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319 |
| 3242system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::samples 2 | 3285system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::samples 2 |
| 3243system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean 445 3244system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 444.959549 3245system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 8.485281 3246system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 3286system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean 253.500000 3287system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 253.440328 3288system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 7.778175 3289system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% |
| 3247system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::total 2 3248system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 3249system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 3250system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::samples 10090 3251system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 3252system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000 3253system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10090 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 3254system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::total 10090 3255system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::bucket_size 64 3256system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::max_bucket 639 3257system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::samples 322 3258system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::mean 211.208075 3259system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::gmean 209.444324 3260system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::stdev 38.157121 3261system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 314 97.52% 97.52% | 1 0.31% 97.83% | 5 1.55% 99.38% | 0 0.00% 99.38% | 0 0.00% 99.38% | 0 0.00% 99.38% | 2 0.62% 100.00% 3262system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::total 322 3263system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 3264system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 3265system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::samples 8 | 3290system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::total 2 3291system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 3292system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 3293system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::samples 10090 3294system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 3295system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000 3296system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10090 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 3297system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::total 10090 3298system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::bucket_size 64 3299system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::max_bucket 639 3300system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::samples 322 3301system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::mean 211.208075 3302system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::gmean 209.444324 3303system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::stdev 38.157121 3304system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 314 97.52% 97.52% | 1 0.31% 97.83% | 5 1.55% 99.38% | 0 0.00% 99.38% | 0 0.00% 99.38% | 0 0.00% 99.38% | 2 0.62% 100.00% 3305system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::total 322 3306system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 3307system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 3308system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::samples 8 |
| 3266system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::mean 1 3267system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::gmean 1 3268system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 8 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 3309system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::mean 2 3310system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::gmean 2 3311system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 8 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 3269system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::total 8 | 3312system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::total 8 |
| 3270system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32 3271system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319 | 3313system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 64 3314system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 639 |
| 3272system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::samples 8 | 3315system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::samples 8 |
| 3273system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 249.750000 3274system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 249.728954 3275system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 3.494894 3276system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 87.50% 87.50% | 1 12.50% 100.00% | 0 0.00% 100.00% | 3316system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 367 3317system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 364.630235 3318system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 44.510031 3319system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 50.00% 50.00% | 4 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 3277system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::total 8 3278system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64 3279system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639 3280system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 1 | 3320system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::total 8 3321system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64 3322system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639 3323system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 1 |
| 3281system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 362 3282system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 362.000000 | 3324system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 332 3325system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 332.000000 |
| 3283system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev nan 3284system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 3285system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 1 3286system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32 3287system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319 3288system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::samples 1 | 3326system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev nan 3327system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 3328system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 1 3329system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32 3330system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319 3331system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::samples 1 |
| 3289system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::mean 273 3290system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 273 | 3332system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::mean 259 3333system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 259.000000 |
| 3291system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::stdev nan 3292system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% 3293system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::total 1 3294system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 3295system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 3296system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::samples 86007 3297system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 3298system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000 --- 37 unchanged lines hidden (view full) --- 3336system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::total 10 3337system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 3338system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 3339system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::samples 10 3340system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 3341system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2 3342system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 3343system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::total 10 | 3334system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::stdev nan 3335system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% 3336system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::total 1 3337system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 3338system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 3339system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::samples 86007 3340system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 3341system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000 --- 37 unchanged lines hidden (view full) --- 3379system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::total 10 3380system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 3381system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 3382system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::samples 10 3383system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 3384system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2 3385system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 3386system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::total 10 |
| 3344system.ruby.SQC_Controller.Fetch 86 0.00% 0.00% 3345system.ruby.SQC_Controller.TCC_AckS 5 0.00% 0.00% 3346system.ruby.SQC_Controller.I.Fetch 5 0.00% 0.00% 3347system.ruby.SQC_Controller.S.Fetch 81 0.00% 0.00% 3348system.ruby.SQC_Controller.I_S.TCC_AckS 5 0.00% 0.00% 3349system.ruby.TCCdir_Controller.RdBlk 93 0.00% 0.00% 3350system.ruby.TCCdir_Controller.RdBlkM 37 0.00% 0.00% 3351system.ruby.TCCdir_Controller.RdBlkS 5 0.00% 0.00% | 3387system.ruby.SQC_Controller.Fetch 70 0.00% 0.00% 3388system.ruby.SQC_Controller.TCC_AckS 3 0.00% 0.00% 3389system.ruby.SQC_Controller.I.Fetch 3 0.00% 0.00% 3390system.ruby.SQC_Controller.S.Fetch 67 0.00% 0.00% 3391system.ruby.SQC_Controller.I_S.TCC_AckS 3 0.00% 0.00% 3392system.ruby.TCCdir_Controller.RdBlk 54 0.00% 0.00% 3393system.ruby.TCCdir_Controller.RdBlkM 34 0.00% 0.00% 3394system.ruby.TCCdir_Controller.RdBlkS 3 0.00% 0.00% |
| 3352system.ruby.TCCdir_Controller.CPUPrbResp 14 0.00% 0.00% 3353system.ruby.TCCdir_Controller.ProbeAcksComplete 13 0.00% 0.00% | 3395system.ruby.TCCdir_Controller.CPUPrbResp 14 0.00% 0.00% 3396system.ruby.TCCdir_Controller.ProbeAcksComplete 13 0.00% 0.00% |
| 3354system.ruby.TCCdir_Controller.CoreUnblock 17 0.00% 0.00% | 3397system.ruby.TCCdir_Controller.CoreUnblock 15 0.00% 0.00% |
| 3355system.ruby.TCCdir_Controller.LastCoreUnblock 2 0.00% 0.00% | 3398system.ruby.TCCdir_Controller.LastCoreUnblock 2 0.00% 0.00% |
| 3356system.ruby.TCCdir_Controller.NB_AckS 7 0.00% 0.00% | 3399system.ruby.TCCdir_Controller.NB_AckS 5 0.00% 0.00% |
| 3357system.ruby.TCCdir_Controller.NB_AckM 9 0.00% 0.00% 3358system.ruby.TCCdir_Controller.PrbInvData 326 0.00% 0.00% 3359system.ruby.TCCdir_Controller.PrbShrData 1209 0.00% 0.00% 3360system.ruby.TCCdir_Controller.I.RdBlk 2 0.00% 0.00% 3361system.ruby.TCCdir_Controller.I.RdBlkM 9 0.00% 0.00% | 3400system.ruby.TCCdir_Controller.NB_AckM 9 0.00% 0.00% 3401system.ruby.TCCdir_Controller.PrbInvData 326 0.00% 0.00% 3402system.ruby.TCCdir_Controller.PrbShrData 1209 0.00% 0.00% 3403system.ruby.TCCdir_Controller.I.RdBlk 2 0.00% 0.00% 3404system.ruby.TCCdir_Controller.I.RdBlkM 9 0.00% 0.00% |
| 3362system.ruby.TCCdir_Controller.I.RdBlkS 5 0.00% 0.00% | 3405system.ruby.TCCdir_Controller.I.RdBlkS 3 0.00% 0.00% |
| 3363system.ruby.TCCdir_Controller.I.PrbInvData 325 0.00% 0.00% 3364system.ruby.TCCdir_Controller.I.PrbShrData 1200 0.00% 0.00% 3365system.ruby.TCCdir_Controller.S.RdBlk 2 0.00% 0.00% 3366system.ruby.TCCdir_Controller.S.PrbInvData 1 0.00% 0.00% 3367system.ruby.TCCdir_Controller.M.RdBlkM 1 0.00% 0.00% 3368system.ruby.TCCdir_Controller.M.PrbShrData 9 0.00% 0.00% 3369system.ruby.TCCdir_Controller.CP_I.CPUPrbResp 2 0.00% 0.00% 3370system.ruby.TCCdir_Controller.CP_I.ProbeAcksComplete 1 0.00% 0.00% 3371system.ruby.TCCdir_Controller.CP_O.CPUPrbResp 9 0.00% 0.00% 3372system.ruby.TCCdir_Controller.CP_O.ProbeAcksComplete 9 0.00% 0.00% | 3406system.ruby.TCCdir_Controller.I.PrbInvData 325 0.00% 0.00% 3407system.ruby.TCCdir_Controller.I.PrbShrData 1200 0.00% 0.00% 3408system.ruby.TCCdir_Controller.S.RdBlk 2 0.00% 0.00% 3409system.ruby.TCCdir_Controller.S.PrbInvData 1 0.00% 0.00% 3410system.ruby.TCCdir_Controller.M.RdBlkM 1 0.00% 0.00% 3411system.ruby.TCCdir_Controller.M.PrbShrData 9 0.00% 0.00% 3412system.ruby.TCCdir_Controller.CP_I.CPUPrbResp 2 0.00% 0.00% 3413system.ruby.TCCdir_Controller.CP_I.ProbeAcksComplete 1 0.00% 0.00% 3414system.ruby.TCCdir_Controller.CP_O.CPUPrbResp 9 0.00% 0.00% 3415system.ruby.TCCdir_Controller.CP_O.ProbeAcksComplete 9 0.00% 0.00% |
| 3373system.ruby.TCCdir_Controller.I_M.RdBlkM 22 0.00% 0.00% | 3416system.ruby.TCCdir_Controller.I_M.RdBlkM 20 0.00% 0.00% |
| 3374system.ruby.TCCdir_Controller.I_M.NB_AckM 9 0.00% 0.00% | 3417system.ruby.TCCdir_Controller.I_M.NB_AckM 9 0.00% 0.00% |
| 3375system.ruby.TCCdir_Controller.I_ES.RdBlk 79 0.00% 0.00% | 3418system.ruby.TCCdir_Controller.I_ES.RdBlk 41 0.00% 0.00% |
| 3376system.ruby.TCCdir_Controller.I_ES.NB_AckS 2 0.00% 0.00% | 3419system.ruby.TCCdir_Controller.I_ES.NB_AckS 2 0.00% 0.00% |
| 3377system.ruby.TCCdir_Controller.I_S.NB_AckS 5 0.00% 0.00% | 3420system.ruby.TCCdir_Controller.I_S.NB_AckS 3 0.00% 0.00% |
| 3378system.ruby.TCCdir_Controller.BBS_S.CPUPrbResp 2 0.00% 0.00% 3379system.ruby.TCCdir_Controller.BBS_S.ProbeAcksComplete 2 0.00% 0.00% 3380system.ruby.TCCdir_Controller.BBM_M.CPUPrbResp 1 0.00% 0.00% 3381system.ruby.TCCdir_Controller.BBM_M.ProbeAcksComplete 1 0.00% 0.00% 3382system.ruby.TCCdir_Controller.BB_M.CoreUnblock 1 0.00% 0.00% 3383system.ruby.TCCdir_Controller.BB_S.LastCoreUnblock 2 0.00% 0.00% | 3421system.ruby.TCCdir_Controller.BBS_S.CPUPrbResp 2 0.00% 0.00% 3422system.ruby.TCCdir_Controller.BBS_S.ProbeAcksComplete 2 0.00% 0.00% 3423system.ruby.TCCdir_Controller.BBM_M.CPUPrbResp 1 0.00% 0.00% 3424system.ruby.TCCdir_Controller.BBM_M.ProbeAcksComplete 1 0.00% 0.00% 3425system.ruby.TCCdir_Controller.BB_M.CoreUnblock 1 0.00% 0.00% 3426system.ruby.TCCdir_Controller.BB_S.LastCoreUnblock 2 0.00% 0.00% |
| 3384system.ruby.TCCdir_Controller.BBB_S.RdBlk 10 0.00% 0.00% 3385system.ruby.TCCdir_Controller.BBB_S.CoreUnblock 7 0.00% 0.00% 3386system.ruby.TCCdir_Controller.BBB_M.RdBlkM 5 0.00% 0.00% | 3427system.ruby.TCCdir_Controller.BBB_S.RdBlk 9 0.00% 0.00% 3428system.ruby.TCCdir_Controller.BBB_S.CoreUnblock 5 0.00% 0.00% 3429system.ruby.TCCdir_Controller.BBB_M.RdBlkM 4 0.00% 0.00% |
| 3387system.ruby.TCCdir_Controller.BBB_M.CoreUnblock 9 0.00% 0.00% 3388system.ruby.TCP_Controller.Load | 4 44.44% 44.44% | 5 55.56% 100.00% 3389system.ruby.TCP_Controller.Load::total 9 3390system.ruby.TCP_Controller.Store | 9 50.00% 50.00% | 9 50.00% 100.00% 3391system.ruby.TCP_Controller.Store::total 18 3392system.ruby.TCP_Controller.TCC_AckS | 2 50.00% 50.00% | 2 50.00% 100.00% 3393system.ruby.TCP_Controller.TCC_AckS::total 4 3394system.ruby.TCP_Controller.TCC_AckM | 5 50.00% 50.00% | 5 50.00% 100.00% 3395system.ruby.TCP_Controller.TCC_AckM::total 10 | 3430system.ruby.TCCdir_Controller.BBB_M.CoreUnblock 9 0.00% 0.00% 3431system.ruby.TCP_Controller.Load | 4 44.44% 44.44% | 5 55.56% 100.00% 3432system.ruby.TCP_Controller.Load::total 9 3433system.ruby.TCP_Controller.Store | 9 50.00% 50.00% | 9 50.00% 100.00% 3434system.ruby.TCP_Controller.Store::total 18 3435system.ruby.TCP_Controller.TCC_AckS | 2 50.00% 50.00% | 2 50.00% 100.00% 3436system.ruby.TCP_Controller.TCC_AckS::total 4 3437system.ruby.TCP_Controller.TCC_AckM | 5 50.00% 50.00% | 5 50.00% 100.00% 3438system.ruby.TCP_Controller.TCC_AckM::total 10 |
| 3396system.ruby.TCP_Controller.PrbInvData | 1 33.33% 33.33% | 2 66.67% 100.00% | 3439system.ruby.TCP_Controller.PrbInvData | 2 66.67% 66.67% | 1 33.33% 100.00% |
| 3397system.ruby.TCP_Controller.PrbInvData::total 3 | 3440system.ruby.TCP_Controller.PrbInvData::total 3 |
| 3398system.ruby.TCP_Controller.PrbShrData | 7 63.64% 63.64% | 4 36.36% 100.00% | 3441system.ruby.TCP_Controller.PrbShrData | 6 54.55% 54.55% | 5 45.45% 100.00% |
| 3399system.ruby.TCP_Controller.PrbShrData::total 11 3400system.ruby.TCP_Controller.I.Load | 2 50.00% 50.00% | 2 50.00% 100.00% 3401system.ruby.TCP_Controller.I.Load::total 4 3402system.ruby.TCP_Controller.I.Store | 5 50.00% 50.00% | 5 50.00% 100.00% 3403system.ruby.TCP_Controller.I.Store::total 10 3404system.ruby.TCP_Controller.S.Load | 2 40.00% 40.00% | 3 60.00% 100.00% 3405system.ruby.TCP_Controller.S.Load::total 5 3406system.ruby.TCP_Controller.S.PrbInvData | 1 50.00% 50.00% | 1 50.00% 100.00% 3407system.ruby.TCP_Controller.S.PrbInvData::total 2 3408system.ruby.TCP_Controller.S.PrbShrData | 2 100.00% 100.00% | 0 0.00% 100.00% 3409system.ruby.TCP_Controller.S.PrbShrData::total 2 3410system.ruby.TCP_Controller.M.Store | 4 50.00% 50.00% | 4 50.00% 100.00% 3411system.ruby.TCP_Controller.M.Store::total 8 | 3442system.ruby.TCP_Controller.PrbShrData::total 11 3443system.ruby.TCP_Controller.I.Load | 2 50.00% 50.00% | 2 50.00% 100.00% 3444system.ruby.TCP_Controller.I.Load::total 4 3445system.ruby.TCP_Controller.I.Store | 5 50.00% 50.00% | 5 50.00% 100.00% 3446system.ruby.TCP_Controller.I.Store::total 10 3447system.ruby.TCP_Controller.S.Load | 2 40.00% 40.00% | 3 60.00% 100.00% 3448system.ruby.TCP_Controller.S.Load::total 5 3449system.ruby.TCP_Controller.S.PrbInvData | 1 50.00% 50.00% | 1 50.00% 100.00% 3450system.ruby.TCP_Controller.S.PrbInvData::total 2 3451system.ruby.TCP_Controller.S.PrbShrData | 2 100.00% 100.00% | 0 0.00% 100.00% 3452system.ruby.TCP_Controller.S.PrbShrData::total 2 3453system.ruby.TCP_Controller.M.Store | 4 50.00% 50.00% | 4 50.00% 100.00% 3454system.ruby.TCP_Controller.M.Store::total 8 |
| 3412system.ruby.TCP_Controller.M.PrbInvData | 0 0.00% 0.00% | 1 100.00% 100.00% | 3455system.ruby.TCP_Controller.M.PrbInvData | 1 100.00% 100.00% | 0 0.00% 100.00% |
| 3413system.ruby.TCP_Controller.M.PrbInvData::total 1 | 3456system.ruby.TCP_Controller.M.PrbInvData::total 1 |
| 3414system.ruby.TCP_Controller.M.PrbShrData | 5 55.56% 55.56% | 4 44.44% 100.00% | 3457system.ruby.TCP_Controller.M.PrbShrData | 4 44.44% 44.44% | 5 55.56% 100.00% |
| 3415system.ruby.TCP_Controller.M.PrbShrData::total 9 3416system.ruby.TCP_Controller.I_M.TCC_AckM | 5 50.00% 50.00% | 5 50.00% 100.00% 3417system.ruby.TCP_Controller.I_M.TCC_AckM::total 10 3418system.ruby.TCP_Controller.I_ES.TCC_AckS | 2 50.00% 50.00% | 2 50.00% 100.00% 3419system.ruby.TCP_Controller.I_ES.TCC_AckS::total 4 3420 3421---------- End Simulation Statistics ---------- | 3458system.ruby.TCP_Controller.M.PrbShrData::total 9 3459system.ruby.TCP_Controller.I_M.TCC_AckM | 5 50.00% 50.00% | 5 50.00% 100.00% 3460system.ruby.TCP_Controller.I_M.TCC_AckM::total 10 3461system.ruby.TCP_Controller.I_ES.TCC_AckS | 2 50.00% 50.00% | 2 50.00% 100.00% 3462system.ruby.TCP_Controller.I_ES.TCC_AckS::total 4 3463 3464---------- End Simulation Statistics ---------- |