| stats.txt (11502:e273e86a873d) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000663 # Number of seconds simulated 4sim_ticks 663454500 # Number of ticks simulated 5final_tick 663454500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000663 # Number of seconds simulated 4sim_ticks 663454500 # Number of ticks simulated 5final_tick 663454500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 153021 # Simulator instruction rate (inst/s) 8host_op_rate 314663 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1515963159 # Simulator tick rate (ticks/s) 10host_mem_usage 1308268 # Number of bytes of host memory used 11host_seconds 0.44 # Real time elapsed on the host | 7host_inst_rate 237471 # Simulator instruction rate (inst/s) 8host_op_rate 488329 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2352682974 # Simulator tick rate (ticks/s) 10host_mem_usage 1358064 # Number of bytes of host memory used 11host_seconds 0.28 # Real time elapsed on the host |
| 12sim_insts 66963 # Number of instructions simulated 13sim_ops 137705 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 66963 # Number of instructions simulated 13sim_ops 137705 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 16system.mem_ctrls.bytes_read::dir_cntrl0 99264 # Number of bytes read from this memory 17system.mem_ctrls.bytes_read::total 99264 # Number of bytes read from this memory 18system.mem_ctrls.num_reads::dir_cntrl0 1551 # Number of read requests responded to by this memory 19system.mem_ctrls.num_reads::total 1551 # Number of read requests responded to by this memory 20system.mem_ctrls.bw_read::dir_cntrl0 149616892 # Total read bandwidth from this memory (bytes/s) 21system.mem_ctrls.bw_read::total 149616892 # Total read bandwidth from this memory (bytes/s) 22system.mem_ctrls.bw_total::dir_cntrl0 149616892 # Total bandwidth to/from this memory (bytes/s) 23system.mem_ctrls.bw_total::total 149616892 # Total bandwidth to/from this memory (bytes/s) --- 214 unchanged lines hidden (view full) --- 238system.mem_ctrls_1.totalEnergy 496405380 # Total energy per rank (pJ) 239system.mem_ctrls_1.averagePower 749.753724 # Core power per rank (mW) 240system.mem_ctrls_1.memoryStateTime::IDLE 115859750 # Time in different power states 241system.mem_ctrls_1.memoryStateTime::REF 22100000 # Time in different power states 242system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states 243system.mem_ctrls_1.memoryStateTime::ACT 524145250 # Time in different power states 244system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states 245system.ruby.clk_domain.clock 500 # Clock period in ticks | 17system.mem_ctrls.bytes_read::dir_cntrl0 99264 # Number of bytes read from this memory 18system.mem_ctrls.bytes_read::total 99264 # Number of bytes read from this memory 19system.mem_ctrls.num_reads::dir_cntrl0 1551 # Number of read requests responded to by this memory 20system.mem_ctrls.num_reads::total 1551 # Number of read requests responded to by this memory 21system.mem_ctrls.bw_read::dir_cntrl0 149616892 # Total read bandwidth from this memory (bytes/s) 22system.mem_ctrls.bw_read::total 149616892 # Total read bandwidth from this memory (bytes/s) 23system.mem_ctrls.bw_total::dir_cntrl0 149616892 # Total bandwidth to/from this memory (bytes/s) 24system.mem_ctrls.bw_total::total 149616892 # Total bandwidth to/from this memory (bytes/s) --- 214 unchanged lines hidden (view full) --- 239system.mem_ctrls_1.totalEnergy 496405380 # Total energy per rank (pJ) 240system.mem_ctrls_1.averagePower 749.753724 # Core power per rank (mW) 241system.mem_ctrls_1.memoryStateTime::IDLE 115859750 # Time in different power states 242system.mem_ctrls_1.memoryStateTime::REF 22100000 # Time in different power states 243system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states 244system.mem_ctrls_1.memoryStateTime::ACT 524145250 # Time in different power states 245system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states 246system.ruby.clk_domain.clock 500 # Clock period in ticks |
| 247system.ruby.phys_mem.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 246system.ruby.phys_mem.bytes_read::cpu0.inst 696760 # Number of bytes read from this memory 247system.ruby.phys_mem.bytes_read::cpu0.data 119832 # Number of bytes read from this memory 248system.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 3280 # Number of bytes read from this memory 249system.ruby.phys_mem.bytes_read::cpu1.CUs1.ComputeUnit 3280 # Number of bytes read from this memory 250system.ruby.phys_mem.bytes_read::total 823152 # Number of bytes read from this memory 251system.ruby.phys_mem.bytes_inst_read::cpu0.inst 696760 # Number of instructions bytes read from this memory 252system.ruby.phys_mem.bytes_inst_read::cpu1.CUs0.ComputeUnit 2000 # Number of instructions bytes read from this memory 253system.ruby.phys_mem.bytes_inst_read::cpu1.CUs1.ComputeUnit 2000 # Number of instructions bytes read from this memory --- 24 unchanged lines hidden (view full) --- 278system.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit 385859 # Write bandwidth from this memory (bytes/s) 279system.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit 385859 # Write bandwidth from this memory (bytes/s) 280system.ruby.phys_mem.bw_write::total 110450679 # Write bandwidth from this memory (bytes/s) 281system.ruby.phys_mem.bw_total::cpu0.inst 1050200127 # Total bandwidth to/from this memory (bytes/s) 282system.ruby.phys_mem.bw_total::cpu0.data 290297225 # Total bandwidth to/from this memory (bytes/s) 283system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 5329680 # Total bandwidth to/from this memory (bytes/s) 284system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 5329680 # Total bandwidth to/from this memory (bytes/s) 285system.ruby.phys_mem.bw_total::total 1351156711 # Total bandwidth to/from this memory (bytes/s) | 248system.ruby.phys_mem.bytes_read::cpu0.inst 696760 # Number of bytes read from this memory 249system.ruby.phys_mem.bytes_read::cpu0.data 119832 # Number of bytes read from this memory 250system.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 3280 # Number of bytes read from this memory 251system.ruby.phys_mem.bytes_read::cpu1.CUs1.ComputeUnit 3280 # Number of bytes read from this memory 252system.ruby.phys_mem.bytes_read::total 823152 # Number of bytes read from this memory 253system.ruby.phys_mem.bytes_inst_read::cpu0.inst 696760 # Number of instructions bytes read from this memory 254system.ruby.phys_mem.bytes_inst_read::cpu1.CUs0.ComputeUnit 2000 # Number of instructions bytes read from this memory 255system.ruby.phys_mem.bytes_inst_read::cpu1.CUs1.ComputeUnit 2000 # Number of instructions bytes read from this memory --- 24 unchanged lines hidden (view full) --- 280system.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit 385859 # Write bandwidth from this memory (bytes/s) 281system.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit 385859 # Write bandwidth from this memory (bytes/s) 282system.ruby.phys_mem.bw_write::total 110450679 # Write bandwidth from this memory (bytes/s) 283system.ruby.phys_mem.bw_total::cpu0.inst 1050200127 # Total bandwidth to/from this memory (bytes/s) 284system.ruby.phys_mem.bw_total::cpu0.data 290297225 # Total bandwidth to/from this memory (bytes/s) 285system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 5329680 # Total bandwidth to/from this memory (bytes/s) 286system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 5329680 # Total bandwidth to/from this memory (bytes/s) 287system.ruby.phys_mem.bw_total::total 1351156711 # Total bandwidth to/from this memory (bytes/s) |
| 288system.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states 289system.ruby.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 286system.ruby.outstanding_req_hist_seqr::bucket_size 1 287system.ruby.outstanding_req_hist_seqr::max_bucket 9 288system.ruby.outstanding_req_hist_seqr::samples 114203 289system.ruby.outstanding_req_hist_seqr::mean 1.000035 290system.ruby.outstanding_req_hist_seqr::gmean 1.000024 291system.ruby.outstanding_req_hist_seqr::stdev 0.005918 292system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 114199 100.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 293system.ruby.outstanding_req_hist_seqr::total 114203 --- 66 unchanged lines hidden (view full) --- 360system.cp_cntrl0.L1Icache.num_tag_array_writes 54 # number of tag array writes 361system.cp_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits 362system.cp_cntrl0.L2cache.demand_misses 1535 # Number of cache demand misses 363system.cp_cntrl0.L2cache.demand_accesses 1535 # Number of cache demand accesses 364system.cp_cntrl0.L2cache.num_data_array_reads 120 # number of data array reads 365system.cp_cntrl0.L2cache.num_data_array_writes 11982 # number of data array writes 366system.cp_cntrl0.L2cache.num_tag_array_reads 12059 # number of tag array reads 367system.cp_cntrl0.L2cache.num_tag_array_writes 1649 # number of tag array writes | 290system.ruby.outstanding_req_hist_seqr::bucket_size 1 291system.ruby.outstanding_req_hist_seqr::max_bucket 9 292system.ruby.outstanding_req_hist_seqr::samples 114203 293system.ruby.outstanding_req_hist_seqr::mean 1.000035 294system.ruby.outstanding_req_hist_seqr::gmean 1.000024 295system.ruby.outstanding_req_hist_seqr::stdev 0.005918 296system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 114199 100.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 297system.ruby.outstanding_req_hist_seqr::total 114203 --- 66 unchanged lines hidden (view full) --- 364system.cp_cntrl0.L1Icache.num_tag_array_writes 54 # number of tag array writes 365system.cp_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits 366system.cp_cntrl0.L2cache.demand_misses 1535 # Number of cache demand misses 367system.cp_cntrl0.L2cache.demand_accesses 1535 # Number of cache demand accesses 368system.cp_cntrl0.L2cache.num_data_array_reads 120 # number of data array reads 369system.cp_cntrl0.L2cache.num_data_array_writes 11982 # number of data array writes 370system.cp_cntrl0.L2cache.num_tag_array_reads 12059 # number of tag array reads 371system.cp_cntrl0.L2cache.num_tag_array_writes 1649 # number of tag array writes |
| 372system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states 373system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states 374system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 368system.cpu0.clk_domain.clock 500 # Clock period in ticks | 375system.cpu0.clk_domain.clock 500 # Clock period in ticks |
| 376system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 369system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks | 377system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks |
| 378system.cpu0.interrupts.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states 379system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 370system.cpu0.workload.num_syscalls 21 # Number of system calls | 380system.cpu0.workload.num_syscalls 21 # Number of system calls |
| 381system.cpu0.numPwrStateTransitions 2 # Number of power state transitions 382system.cpu0.pwrStateClkGateDist::samples 1 # Distribution of time spent in the clock gated state 383system.cpu0.pwrStateClkGateDist::mean 2615501 # Distribution of time spent in the clock gated state 384system.cpu0.pwrStateClkGateDist::1000-5e+10 1 100.00% 100.00% # Distribution of time spent in the clock gated state 385system.cpu0.pwrStateClkGateDist::min_value 2615501 # Distribution of time spent in the clock gated state 386system.cpu0.pwrStateClkGateDist::max_value 2615501 # Distribution of time spent in the clock gated state 387system.cpu0.pwrStateClkGateDist::total 1 # Distribution of time spent in the clock gated state 388system.cpu0.pwrStateResidencyTicks::ON 660838999 # Cumulative time (in ticks) in various power states 389system.cpu0.pwrStateResidencyTicks::CLK_GATED 2615501 # Cumulative time (in ticks) in various power states |
|
| 371system.cpu0.numCycles 1326909 # number of cpu cycles simulated 372system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 373system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 374system.cpu0.committedInsts 66963 # Number of instructions committed 375system.cpu0.committedOps 137705 # Number of ops (including micro ops) committed 376system.cpu0.num_int_alu_accesses 136380 # Number of integer alu accesses 377system.cpu0.num_fp_alu_accesses 1279 # Number of float alu accesses 378system.cpu0.num_func_calls 3196 # number of times a function call or return occured --- 46 unchanged lines hidden (view full) --- 425system.cpu0.op_class::SimdFloatSqrt 0 0.00% 80.25% # Class of executed instruction 426system.cpu0.op_class::MemRead 16684 12.12% 92.36% # Class of executed instruction 427system.cpu0.op_class::MemWrite 10514 7.64% 100.00% # Class of executed instruction 428system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 429system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 430system.cpu0.op_class::total 137705 # Class of executed instruction 431system.cpu1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 432system.cpu1.clk_domain.clock 1000 # Clock period in ticks | 390system.cpu0.numCycles 1326909 # number of cpu cycles simulated 391system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 392system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 393system.cpu0.committedInsts 66963 # Number of instructions committed 394system.cpu0.committedOps 137705 # Number of ops (including micro ops) committed 395system.cpu0.num_int_alu_accesses 136380 # Number of integer alu accesses 396system.cpu0.num_fp_alu_accesses 1279 # Number of float alu accesses 397system.cpu0.num_func_calls 3196 # number of times a function call or return occured --- 46 unchanged lines hidden (view full) --- 444system.cpu0.op_class::SimdFloatSqrt 0 0.00% 80.25% # Class of executed instruction 445system.cpu0.op_class::MemRead 16684 12.12% 92.36% # Class of executed instruction 446system.cpu0.op_class::MemWrite 10514 7.64% 100.00% # Class of executed instruction 447system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 448system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 449system.cpu0.op_class::total 137705 # Class of executed instruction 450system.cpu1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 451system.cpu1.clk_domain.clock 1000 # Clock period in ticks |
| 452system.cpu1.CUs0.localDataStore.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 433system.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 434system.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 435system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 307 # number of times the wf's instructions are blocked due to RAW dependencies 436system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands 437system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands 438system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands 439system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 440system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands --- 752 unchanged lines hidden (view full) --- 1193system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1194system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1195system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1196system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1197system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1198system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1199system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1200system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands | 453system.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 454system.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 455system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 307 # number of times the wf's instructions are blocked due to RAW dependencies 456system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands 457system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands 458system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands 459system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 460system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands --- 752 unchanged lines hidden (view full) --- 1213system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1214system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1215system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1216system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1217system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1218system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1219system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1220system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands |
| 1221system.cpu1.CUs0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 1201system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it 1202system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it 1203system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it 1204system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 1205system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 1206system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it 1207system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it 1208system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it --- 252 unchanged lines hidden (view full) --- 1461system.cpu1.CUs0.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction 1462system.cpu1.CUs0.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction 1463system.cpu1.CUs0.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction 1464system.cpu1.CUs0.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed 1465system.cpu1.CUs0.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD 1466system.cpu1.CUs0.num_CAS_ops 0 # number of compare and swap operations 1467system.cpu1.CUs0.num_failed_CAS_ops 0 # number of compare and swap operations that failed 1468system.cpu1.CUs0.num_completed_wfs 4 # number of completed wavefronts | 1222system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it 1223system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it 1224system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it 1225system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 1226system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 1227system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it 1228system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it 1229system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it --- 252 unchanged lines hidden (view full) --- 1482system.cpu1.CUs0.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction 1483system.cpu1.CUs0.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction 1484system.cpu1.CUs0.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction 1485system.cpu1.CUs0.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed 1486system.cpu1.CUs0.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD 1487system.cpu1.CUs0.num_CAS_ops 0 # number of compare and swap operations 1488system.cpu1.CUs0.num_failed_CAS_ops 0 # number of compare and swap operations that failed 1489system.cpu1.CUs0.num_completed_wfs 4 # number of completed wavefronts |
| 1490system.cpu1.CUs1.localDataStore.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 1469system.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1470system.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1471system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 401 # number of times the wf's instructions are blocked due to RAW dependencies 1472system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands 1473system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands 1474system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands 1475system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 1476system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands --- 752 unchanged lines hidden (view full) --- 2229system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 2230system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 2231system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 2232system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 2233system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 2234system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2235system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 2236system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands | 1491system.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1492system.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1493system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 401 # number of times the wf's instructions are blocked due to RAW dependencies 1494system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands 1495system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands 1496system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands 1497system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 1498system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands --- 752 unchanged lines hidden (view full) --- 2251system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 2252system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 2253system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 2254system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 2255system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 2256system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2257system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 2258system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands |
| 2259system.cpu1.CUs1.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 2237system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it 2238system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it 2239system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it 2240system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 2241system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 2242system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it 2243system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it 2244system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it --- 252 unchanged lines hidden (view full) --- 2497system.cpu1.CUs1.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction 2498system.cpu1.CUs1.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction 2499system.cpu1.CUs1.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction 2500system.cpu1.CUs1.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed 2501system.cpu1.CUs1.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD 2502system.cpu1.CUs1.num_CAS_ops 0 # number of compare and swap operations 2503system.cpu1.CUs1.num_failed_CAS_ops 0 # number of compare and swap operations that failed 2504system.cpu1.CUs1.num_completed_wfs 4 # number of completed wavefronts | 2260system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it 2261system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it 2262system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it 2263system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 2264system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 2265system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it 2266system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it 2267system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it --- 252 unchanged lines hidden (view full) --- 2520system.cpu1.CUs1.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction 2521system.cpu1.CUs1.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction 2522system.cpu1.CUs1.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction 2523system.cpu1.CUs1.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed 2524system.cpu1.CUs1.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD 2525system.cpu1.CUs1.num_CAS_ops 0 # number of compare and swap operations 2526system.cpu1.CUs1.num_failed_CAS_ops 0 # number of compare and swap operations that failed 2527system.cpu1.CUs1.num_completed_wfs 4 # number of completed wavefronts |
| 2528system.cpu1.CUs0.ldsBus.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states 2529system.cpu1.CUs1.ldsBus.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states 2530system.cpu2.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 2505system.cpu2.num_kernel_launched 1 # number of kernel launched 2506system.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits 2507system.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses 2508system.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses 2509system.dir_cntrl0.L3CacheMemory.num_data_array_writes 1551 # number of data array writes 2510system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1551 # number of tag array reads 2511system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1551 # number of tag array writes | 2531system.cpu2.num_kernel_launched 1 # number of kernel launched 2532system.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits 2533system.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses 2534system.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses 2535system.dir_cntrl0.L3CacheMemory.num_data_array_writes 1551 # number of data array writes 2536system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1551 # number of tag array reads 2537system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1551 # number of tag array writes |
| 2538system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 2512system.dispatcher_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2513system.dispatcher_coalescer.clk_domain.clock 1000 # Clock period in ticks | 2539system.dispatcher_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2540system.dispatcher_coalescer.clk_domain.clock 1000 # Clock period in ticks |
| 2541system.dispatcher_coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 2514system.dispatcher_coalescer.uncoalesced_accesses 0 # Number of uncoalesced TLB accesses 2515system.dispatcher_coalescer.coalesced_accesses 0 # Number of coalesced TLB accesses 2516system.dispatcher_coalescer.queuing_cycles 0 # Number of cycles spent in queue 2517system.dispatcher_coalescer.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 2518system.dispatcher_coalescer.local_latency nan # Avg. latency over all incoming pkts 2519system.dispatcher_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2520system.dispatcher_tlb.clk_domain.clock 1000 # Clock period in ticks | 2542system.dispatcher_coalescer.uncoalesced_accesses 0 # Number of uncoalesced TLB accesses 2543system.dispatcher_coalescer.coalesced_accesses 0 # Number of coalesced TLB accesses 2544system.dispatcher_coalescer.queuing_cycles 0 # Number of cycles spent in queue 2545system.dispatcher_coalescer.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 2546system.dispatcher_coalescer.local_latency nan # Avg. latency over all incoming pkts 2547system.dispatcher_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2548system.dispatcher_tlb.clk_domain.clock 1000 # Clock period in ticks |
| 2549system.dispatcher_tlb.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 2521system.dispatcher_tlb.local_TLB_accesses 0 # Number of TLB accesses 2522system.dispatcher_tlb.local_TLB_hits 0 # Number of TLB hits 2523system.dispatcher_tlb.local_TLB_misses 0 # Number of TLB misses 2524system.dispatcher_tlb.local_TLB_miss_rate nan # TLB miss rate 2525system.dispatcher_tlb.global_TLB_accesses 0 # Number of TLB accesses 2526system.dispatcher_tlb.global_TLB_hits 0 # Number of TLB hits 2527system.dispatcher_tlb.global_TLB_misses 0 # Number of TLB misses 2528system.dispatcher_tlb.global_TLB_miss_rate nan # TLB miss rate 2529system.dispatcher_tlb.access_cycles 0 # Cycles spent accessing this TLB level 2530system.dispatcher_tlb.page_table_cycles 0 # Cycles spent accessing the page table 2531system.dispatcher_tlb.unique_pages 0 # Number of unique pages touched 2532system.dispatcher_tlb.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 2533system.dispatcher_tlb.local_latency nan # Avg. latency over incoming coalesced reqs 2534system.dispatcher_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 2535system.l1_coalescer0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2536system.l1_coalescer0.clk_domain.clock 1000 # Clock period in ticks | 2550system.dispatcher_tlb.local_TLB_accesses 0 # Number of TLB accesses 2551system.dispatcher_tlb.local_TLB_hits 0 # Number of TLB hits 2552system.dispatcher_tlb.local_TLB_misses 0 # Number of TLB misses 2553system.dispatcher_tlb.local_TLB_miss_rate nan # TLB miss rate 2554system.dispatcher_tlb.global_TLB_accesses 0 # Number of TLB accesses 2555system.dispatcher_tlb.global_TLB_hits 0 # Number of TLB hits 2556system.dispatcher_tlb.global_TLB_misses 0 # Number of TLB misses 2557system.dispatcher_tlb.global_TLB_miss_rate nan # TLB miss rate 2558system.dispatcher_tlb.access_cycles 0 # Cycles spent accessing this TLB level 2559system.dispatcher_tlb.page_table_cycles 0 # Cycles spent accessing the page table 2560system.dispatcher_tlb.unique_pages 0 # Number of unique pages touched 2561system.dispatcher_tlb.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 2562system.dispatcher_tlb.local_latency nan # Avg. latency over incoming coalesced reqs 2563system.dispatcher_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 2564system.l1_coalescer0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2565system.l1_coalescer0.clk_domain.clock 1000 # Clock period in ticks |
| 2566system.l1_coalescer0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 2537system.l1_coalescer0.uncoalesced_accesses 778 # Number of uncoalesced TLB accesses 2538system.l1_coalescer0.coalesced_accesses 0 # Number of coalesced TLB accesses 2539system.l1_coalescer0.queuing_cycles 0 # Number of cycles spent in queue 2540system.l1_coalescer0.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 2541system.l1_coalescer0.local_latency 0 # Avg. latency over all incoming pkts 2542system.l1_coalescer1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2543system.l1_coalescer1.clk_domain.clock 1000 # Clock period in ticks | 2567system.l1_coalescer0.uncoalesced_accesses 778 # Number of uncoalesced TLB accesses 2568system.l1_coalescer0.coalesced_accesses 0 # Number of coalesced TLB accesses 2569system.l1_coalescer0.queuing_cycles 0 # Number of cycles spent in queue 2570system.l1_coalescer0.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 2571system.l1_coalescer0.local_latency 0 # Avg. latency over all incoming pkts 2572system.l1_coalescer1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2573system.l1_coalescer1.clk_domain.clock 1000 # Clock period in ticks |
| 2574system.l1_coalescer1.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 2544system.l1_coalescer1.uncoalesced_accesses 769 # Number of uncoalesced TLB accesses 2545system.l1_coalescer1.coalesced_accesses 0 # Number of coalesced TLB accesses 2546system.l1_coalescer1.queuing_cycles 0 # Number of cycles spent in queue 2547system.l1_coalescer1.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 2548system.l1_coalescer1.local_latency 0 # Avg. latency over all incoming pkts 2549system.l1_tlb0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2550system.l1_tlb0.clk_domain.clock 1000 # Clock period in ticks | 2575system.l1_coalescer1.uncoalesced_accesses 769 # Number of uncoalesced TLB accesses 2576system.l1_coalescer1.coalesced_accesses 0 # Number of coalesced TLB accesses 2577system.l1_coalescer1.queuing_cycles 0 # Number of cycles spent in queue 2578system.l1_coalescer1.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 2579system.l1_coalescer1.local_latency 0 # Avg. latency over all incoming pkts 2580system.l1_tlb0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2581system.l1_tlb0.clk_domain.clock 1000 # Clock period in ticks |
| 2582system.l1_tlb0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 2551system.l1_tlb0.local_TLB_accesses 778 # Number of TLB accesses 2552system.l1_tlb0.local_TLB_hits 774 # Number of TLB hits 2553system.l1_tlb0.local_TLB_misses 4 # Number of TLB misses 2554system.l1_tlb0.local_TLB_miss_rate 0.514139 # TLB miss rate 2555system.l1_tlb0.global_TLB_accesses 778 # Number of TLB accesses 2556system.l1_tlb0.global_TLB_hits 774 # Number of TLB hits 2557system.l1_tlb0.global_TLB_misses 4 # Number of TLB misses 2558system.l1_tlb0.global_TLB_miss_rate 0.514139 # TLB miss rate 2559system.l1_tlb0.access_cycles 0 # Cycles spent accessing this TLB level 2560system.l1_tlb0.page_table_cycles 0 # Cycles spent accessing the page table 2561system.l1_tlb0.unique_pages 4 # Number of unique pages touched 2562system.l1_tlb0.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 2563system.l1_tlb0.local_latency 0 # Avg. latency over incoming coalesced reqs 2564system.l1_tlb0.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 2565system.l1_tlb1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2566system.l1_tlb1.clk_domain.clock 1000 # Clock period in ticks | 2583system.l1_tlb0.local_TLB_accesses 778 # Number of TLB accesses 2584system.l1_tlb0.local_TLB_hits 774 # Number of TLB hits 2585system.l1_tlb0.local_TLB_misses 4 # Number of TLB misses 2586system.l1_tlb0.local_TLB_miss_rate 0.514139 # TLB miss rate 2587system.l1_tlb0.global_TLB_accesses 778 # Number of TLB accesses 2588system.l1_tlb0.global_TLB_hits 774 # Number of TLB hits 2589system.l1_tlb0.global_TLB_misses 4 # Number of TLB misses 2590system.l1_tlb0.global_TLB_miss_rate 0.514139 # TLB miss rate 2591system.l1_tlb0.access_cycles 0 # Cycles spent accessing this TLB level 2592system.l1_tlb0.page_table_cycles 0 # Cycles spent accessing the page table 2593system.l1_tlb0.unique_pages 4 # Number of unique pages touched 2594system.l1_tlb0.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 2595system.l1_tlb0.local_latency 0 # Avg. latency over incoming coalesced reqs 2596system.l1_tlb0.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 2597system.l1_tlb1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2598system.l1_tlb1.clk_domain.clock 1000 # Clock period in ticks |
| 2599system.l1_tlb1.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 2567system.l1_tlb1.local_TLB_accesses 769 # Number of TLB accesses 2568system.l1_tlb1.local_TLB_hits 766 # Number of TLB hits 2569system.l1_tlb1.local_TLB_misses 3 # Number of TLB misses 2570system.l1_tlb1.local_TLB_miss_rate 0.390117 # TLB miss rate 2571system.l1_tlb1.global_TLB_accesses 769 # Number of TLB accesses 2572system.l1_tlb1.global_TLB_hits 766 # Number of TLB hits 2573system.l1_tlb1.global_TLB_misses 3 # Number of TLB misses 2574system.l1_tlb1.global_TLB_miss_rate 0.390117 # TLB miss rate 2575system.l1_tlb1.access_cycles 0 # Cycles spent accessing this TLB level 2576system.l1_tlb1.page_table_cycles 0 # Cycles spent accessing the page table 2577system.l1_tlb1.unique_pages 3 # Number of unique pages touched 2578system.l1_tlb1.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 2579system.l1_tlb1.local_latency 0 # Avg. latency over incoming coalesced reqs 2580system.l1_tlb1.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 2581system.l2_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2582system.l2_coalescer.clk_domain.clock 1000 # Clock period in ticks | 2600system.l1_tlb1.local_TLB_accesses 769 # Number of TLB accesses 2601system.l1_tlb1.local_TLB_hits 766 # Number of TLB hits 2602system.l1_tlb1.local_TLB_misses 3 # Number of TLB misses 2603system.l1_tlb1.local_TLB_miss_rate 0.390117 # TLB miss rate 2604system.l1_tlb1.global_TLB_accesses 769 # Number of TLB accesses 2605system.l1_tlb1.global_TLB_hits 766 # Number of TLB hits 2606system.l1_tlb1.global_TLB_misses 3 # Number of TLB misses 2607system.l1_tlb1.global_TLB_miss_rate 0.390117 # TLB miss rate 2608system.l1_tlb1.access_cycles 0 # Cycles spent accessing this TLB level 2609system.l1_tlb1.page_table_cycles 0 # Cycles spent accessing the page table 2610system.l1_tlb1.unique_pages 3 # Number of unique pages touched 2611system.l1_tlb1.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 2612system.l1_tlb1.local_latency 0 # Avg. latency over incoming coalesced reqs 2613system.l1_tlb1.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 2614system.l2_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2615system.l2_coalescer.clk_domain.clock 1000 # Clock period in ticks |
| 2616system.l2_coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 2583system.l2_coalescer.uncoalesced_accesses 8 # Number of uncoalesced TLB accesses 2584system.l2_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses 2585system.l2_coalescer.queuing_cycles 8000 # Number of cycles spent in queue 2586system.l2_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs 2587system.l2_coalescer.local_latency 125 # Avg. latency over all incoming pkts 2588system.l2_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2589system.l2_tlb.clk_domain.clock 1000 # Clock period in ticks | 2617system.l2_coalescer.uncoalesced_accesses 8 # Number of uncoalesced TLB accesses 2618system.l2_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses 2619system.l2_coalescer.queuing_cycles 8000 # Number of cycles spent in queue 2620system.l2_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs 2621system.l2_coalescer.local_latency 125 # Avg. latency over all incoming pkts 2622system.l2_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2623system.l2_tlb.clk_domain.clock 1000 # Clock period in ticks |
| 2624system.l2_tlb.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 2590system.l2_tlb.local_TLB_accesses 8 # Number of TLB accesses 2591system.l2_tlb.local_TLB_hits 3 # Number of TLB hits 2592system.l2_tlb.local_TLB_misses 5 # Number of TLB misses 2593system.l2_tlb.local_TLB_miss_rate 62.500000 # TLB miss rate 2594system.l2_tlb.global_TLB_accesses 15 # Number of TLB accesses 2595system.l2_tlb.global_TLB_hits 3 # Number of TLB hits 2596system.l2_tlb.global_TLB_misses 12 # Number of TLB misses 2597system.l2_tlb.global_TLB_miss_rate 80 # TLB miss rate 2598system.l2_tlb.access_cycles 552008 # Cycles spent accessing this TLB level 2599system.l2_tlb.page_table_cycles 0 # Cycles spent accessing the page table 2600system.l2_tlb.unique_pages 5 # Number of unique pages touched 2601system.l2_tlb.local_cycles 69001 # Number of cycles spent in queue for all incoming reqs 2602system.l2_tlb.local_latency 8625.125000 # Avg. latency over incoming coalesced reqs 2603system.l2_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 2604system.l3_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2605system.l3_coalescer.clk_domain.clock 1000 # Clock period in ticks | 2625system.l2_tlb.local_TLB_accesses 8 # Number of TLB accesses 2626system.l2_tlb.local_TLB_hits 3 # Number of TLB hits 2627system.l2_tlb.local_TLB_misses 5 # Number of TLB misses 2628system.l2_tlb.local_TLB_miss_rate 62.500000 # TLB miss rate 2629system.l2_tlb.global_TLB_accesses 15 # Number of TLB accesses 2630system.l2_tlb.global_TLB_hits 3 # Number of TLB hits 2631system.l2_tlb.global_TLB_misses 12 # Number of TLB misses 2632system.l2_tlb.global_TLB_miss_rate 80 # TLB miss rate 2633system.l2_tlb.access_cycles 552008 # Cycles spent accessing this TLB level 2634system.l2_tlb.page_table_cycles 0 # Cycles spent accessing the page table 2635system.l2_tlb.unique_pages 5 # Number of unique pages touched 2636system.l2_tlb.local_cycles 69001 # Number of cycles spent in queue for all incoming reqs 2637system.l2_tlb.local_latency 8625.125000 # Avg. latency over incoming coalesced reqs 2638system.l2_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 2639system.l3_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2640system.l3_coalescer.clk_domain.clock 1000 # Clock period in ticks |
| 2641system.l3_coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 2606system.l3_coalescer.uncoalesced_accesses 5 # Number of uncoalesced TLB accesses 2607system.l3_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses 2608system.l3_coalescer.queuing_cycles 8000 # Number of cycles spent in queue 2609system.l3_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs 2610system.l3_coalescer.local_latency 200 # Avg. latency over all incoming pkts 2611system.l3_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2612system.l3_tlb.clk_domain.clock 1000 # Clock period in ticks | 2642system.l3_coalescer.uncoalesced_accesses 5 # Number of uncoalesced TLB accesses 2643system.l3_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses 2644system.l3_coalescer.queuing_cycles 8000 # Number of cycles spent in queue 2645system.l3_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs 2646system.l3_coalescer.local_latency 200 # Avg. latency over all incoming pkts 2647system.l3_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2648system.l3_tlb.clk_domain.clock 1000 # Clock period in ticks |
| 2649system.l3_tlb.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 2613system.l3_tlb.local_TLB_accesses 5 # Number of TLB accesses 2614system.l3_tlb.local_TLB_hits 0 # Number of TLB hits 2615system.l3_tlb.local_TLB_misses 5 # Number of TLB misses 2616system.l3_tlb.local_TLB_miss_rate 100 # TLB miss rate 2617system.l3_tlb.global_TLB_accesses 12 # Number of TLB accesses 2618system.l3_tlb.global_TLB_hits 0 # Number of TLB hits 2619system.l3_tlb.global_TLB_misses 12 # Number of TLB misses 2620system.l3_tlb.global_TLB_miss_rate 100 # TLB miss rate 2621system.l3_tlb.access_cycles 1200000 # Cycles spent accessing this TLB level 2622system.l3_tlb.page_table_cycles 6000000 # Cycles spent accessing the page table 2623system.l3_tlb.unique_pages 5 # Number of unique pages touched 2624system.l3_tlb.local_cycles 150000 # Number of cycles spent in queue for all incoming reqs 2625system.l3_tlb.local_latency 30000 # Avg. latency over incoming coalesced reqs 2626system.l3_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) | 2650system.l3_tlb.local_TLB_accesses 5 # Number of TLB accesses 2651system.l3_tlb.local_TLB_hits 0 # Number of TLB hits 2652system.l3_tlb.local_TLB_misses 5 # Number of TLB misses 2653system.l3_tlb.local_TLB_miss_rate 100 # TLB miss rate 2654system.l3_tlb.global_TLB_accesses 12 # Number of TLB accesses 2655system.l3_tlb.global_TLB_hits 0 # Number of TLB hits 2656system.l3_tlb.global_TLB_misses 12 # Number of TLB misses 2657system.l3_tlb.global_TLB_miss_rate 100 # TLB miss rate 2658system.l3_tlb.access_cycles 1200000 # Cycles spent accessing this TLB level 2659system.l3_tlb.page_table_cycles 6000000 # Cycles spent accessing the page table 2660system.l3_tlb.unique_pages 5 # Number of unique pages touched 2661system.l3_tlb.local_cycles 150000 # Number of cycles spent in queue for all incoming reqs 2662system.l3_tlb.local_latency 30000 # Avg. latency over incoming coalesced reqs 2663system.l3_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) |
| 2664system.piobus.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 2627system.piobus.trans_dist::WriteReq 94 # Transaction distribution 2628system.piobus.trans_dist::WriteResp 94 # Transaction distribution 2629system.piobus.pkt_count_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 188 # Packet count per connected master and slave (bytes) 2630system.piobus.pkt_count::total 188 # Packet count per connected master and slave (bytes) 2631system.piobus.pkt_size_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 748 # Cumulative packet size per connected master and slave (bytes) 2632system.piobus.pkt_size::total 748 # Cumulative packet size per connected master and slave (bytes) 2633system.piobus.reqLayer0.occupancy 188000 # Layer occupancy (ticks) 2634system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2635system.piobus.respLayer0.occupancy 94000 # Layer occupancy (ticks) 2636system.piobus.respLayer0.utilization 0.0 # Layer utilization (%) | 2665system.piobus.trans_dist::WriteReq 94 # Transaction distribution 2666system.piobus.trans_dist::WriteResp 94 # Transaction distribution 2667system.piobus.pkt_count_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 188 # Packet count per connected master and slave (bytes) 2668system.piobus.pkt_count::total 188 # Packet count per connected master and slave (bytes) 2669system.piobus.pkt_size_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 748 # Cumulative packet size per connected master and slave (bytes) 2670system.piobus.pkt_size::total 748 # Cumulative packet size per connected master and slave (bytes) 2671system.piobus.reqLayer0.occupancy 188000 # Layer occupancy (ticks) 2672system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2673system.piobus.respLayer0.occupancy 94000 # Layer occupancy (ticks) 2674system.piobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2675system.ruby.network.ext_links0.int_node.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 2637system.ruby.network.ext_links0.int_node.percent_links_utilized 0.007952 2638system.ruby.network.ext_links0.int_node.msg_count.Control::0 1551 2639system.ruby.network.ext_links0.int_node.msg_count.Request_Control::0 1551 2640system.ruby.network.ext_links0.int_node.msg_count.Response_Data::2 1563 2641system.ruby.network.ext_links0.int_node.msg_count.Response_Control::2 1539 2642system.ruby.network.ext_links0.int_node.msg_count.Unblock_Control::4 1551 2643system.ruby.network.ext_links0.int_node.msg_bytes.Control::0 12408 2644system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0 12408 2645system.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2 112536 2646system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2 12312 2647system.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4 12408 | 2676system.ruby.network.ext_links0.int_node.percent_links_utilized 0.007952 2677system.ruby.network.ext_links0.int_node.msg_count.Control::0 1551 2678system.ruby.network.ext_links0.int_node.msg_count.Request_Control::0 1551 2679system.ruby.network.ext_links0.int_node.msg_count.Response_Data::2 1563 2680system.ruby.network.ext_links0.int_node.msg_count.Response_Control::2 1539 2681system.ruby.network.ext_links0.int_node.msg_count.Unblock_Control::4 1551 2682system.ruby.network.ext_links0.int_node.msg_bytes.Control::0 12408 2683system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0 12408 2684system.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2 112536 2685system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2 12312 2686system.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4 12408 |
| 2687system.ruby.network.ext_links1.int_node.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 2648system.ruby.network.ext_links1.int_node.percent_links_utilized 0.009970 2649system.ruby.network.ext_links1.int_node.msg_count.Control::0 16 2650system.ruby.network.ext_links1.int_node.msg_count.Request_Control::0 1535 2651system.ruby.network.ext_links1.int_node.msg_count.Response_Data::2 1537 2652system.ruby.network.ext_links1.int_node.msg_count.Response_Control::2 14 2653system.ruby.network.ext_links1.int_node.msg_count.Unblock_Control::4 1535 2654system.ruby.network.ext_links1.int_node.msg_bytes.Control::0 128 2655system.ruby.network.ext_links1.int_node.msg_bytes.Request_Control::0 12280 2656system.ruby.network.ext_links1.int_node.msg_bytes.Response_Data::2 110664 2657system.ruby.network.ext_links1.int_node.msg_bytes.Response_Control::2 112 2658system.ruby.network.ext_links1.int_node.msg_bytes.Unblock_Control::4 12280 2659system.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits 2660system.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses 2661system.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses 2662system.tcp_cntrl0.L1cache.num_data_array_reads 9 # number of data array reads 2663system.tcp_cntrl0.L1cache.num_data_array_writes 11 # number of data array writes 2664system.tcp_cntrl0.L1cache.num_tag_array_reads 26 # number of tag array reads 2665system.tcp_cntrl0.L1cache.num_tag_array_writes 18 # number of tag array writes 2666system.tcp_cntrl0.L1cache.num_data_array_stalls 2 # number of stalls caused by data array | 2688system.ruby.network.ext_links1.int_node.percent_links_utilized 0.009970 2689system.ruby.network.ext_links1.int_node.msg_count.Control::0 16 2690system.ruby.network.ext_links1.int_node.msg_count.Request_Control::0 1535 2691system.ruby.network.ext_links1.int_node.msg_count.Response_Data::2 1537 2692system.ruby.network.ext_links1.int_node.msg_count.Response_Control::2 14 2693system.ruby.network.ext_links1.int_node.msg_count.Unblock_Control::4 1535 2694system.ruby.network.ext_links1.int_node.msg_bytes.Control::0 128 2695system.ruby.network.ext_links1.int_node.msg_bytes.Request_Control::0 12280 2696system.ruby.network.ext_links1.int_node.msg_bytes.Response_Data::2 110664 2697system.ruby.network.ext_links1.int_node.msg_bytes.Response_Control::2 112 2698system.ruby.network.ext_links1.int_node.msg_bytes.Unblock_Control::4 12280 2699system.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits 2700system.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses 2701system.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses 2702system.tcp_cntrl0.L1cache.num_data_array_reads 9 # number of data array reads 2703system.tcp_cntrl0.L1cache.num_data_array_writes 11 # number of data array writes 2704system.tcp_cntrl0.L1cache.num_tag_array_reads 26 # number of tag array reads 2705system.tcp_cntrl0.L1cache.num_tag_array_writes 18 # number of tag array writes 2706system.tcp_cntrl0.L1cache.num_data_array_stalls 2 # number of stalls caused by data array |
| 2707system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 2667system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 2 # loads that hit in the TCP 2668system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers 2669system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 2670system.tcp_cntrl0.coalescer.gpu_ld_misses 2 # loads that miss in the GPU 2671system.tcp_cntrl0.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP 2672system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 1 # TCP to TCP store transfers 2673system.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 2674system.tcp_cntrl0.coalescer.gpu_st_misses 4 # stores that miss in the GPU 2675system.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 2676system.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 2677system.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 2678system.tcp_cntrl0.coalescer.cp_ld_misses 0 # loads that miss in the GPU 2679system.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 2680system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 2681system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 2682system.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU | 2708system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 2 # loads that hit in the TCP 2709system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers 2710system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 2711system.tcp_cntrl0.coalescer.gpu_ld_misses 2 # loads that miss in the GPU 2712system.tcp_cntrl0.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP 2713system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 1 # TCP to TCP store transfers 2714system.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 2715system.tcp_cntrl0.coalescer.gpu_st_misses 4 # stores that miss in the GPU 2716system.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 2717system.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 2718system.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 2719system.tcp_cntrl0.coalescer.cp_ld_misses 0 # loads that miss in the GPU 2720system.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 2721system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 2722system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 2723system.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU |
| 2724system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states 2725system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states 2726system.ruby.network.ext_links2.int_node.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 2683system.ruby.network.ext_links2.int_node.percent_links_utilized 0.000721 2684system.ruby.network.ext_links2.int_node.msg_count.Control::0 1535 2685system.ruby.network.ext_links2.int_node.msg_count.Control::1 14 2686system.ruby.network.ext_links2.int_node.msg_count.Request_Control::0 16 2687system.ruby.network.ext_links2.int_node.msg_count.Request_Control::1 19 2688system.ruby.network.ext_links2.int_node.msg_count.Response_Data::2 26 2689system.ruby.network.ext_links2.int_node.msg_count.Response_Data::3 33 2690system.ruby.network.ext_links2.int_node.msg_count.Response_Control::2 1525 --- 12 unchanged lines hidden (view full) --- 2703system.tcp_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses 2704system.tcp_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses 2705system.tcp_cntrl1.L1cache.num_data_array_reads 7 # number of data array reads 2706system.tcp_cntrl1.L1cache.num_data_array_writes 11 # number of data array writes 2707system.tcp_cntrl1.L1cache.num_tag_array_reads 25 # number of tag array reads 2708system.tcp_cntrl1.L1cache.num_tag_array_writes 18 # number of tag array writes 2709system.tcp_cntrl1.L1cache.num_tag_array_stalls 2 # number of stalls caused by tag array 2710system.tcp_cntrl1.L1cache.num_data_array_stalls 2 # number of stalls caused by data array | 2727system.ruby.network.ext_links2.int_node.percent_links_utilized 0.000721 2728system.ruby.network.ext_links2.int_node.msg_count.Control::0 1535 2729system.ruby.network.ext_links2.int_node.msg_count.Control::1 14 2730system.ruby.network.ext_links2.int_node.msg_count.Request_Control::0 16 2731system.ruby.network.ext_links2.int_node.msg_count.Request_Control::1 19 2732system.ruby.network.ext_links2.int_node.msg_count.Response_Data::2 26 2733system.ruby.network.ext_links2.int_node.msg_count.Response_Data::3 33 2734system.ruby.network.ext_links2.int_node.msg_count.Response_Control::2 1525 --- 12 unchanged lines hidden (view full) --- 2747system.tcp_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses 2748system.tcp_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses 2749system.tcp_cntrl1.L1cache.num_data_array_reads 7 # number of data array reads 2750system.tcp_cntrl1.L1cache.num_data_array_writes 11 # number of data array writes 2751system.tcp_cntrl1.L1cache.num_tag_array_reads 25 # number of tag array reads 2752system.tcp_cntrl1.L1cache.num_tag_array_writes 18 # number of tag array writes 2753system.tcp_cntrl1.L1cache.num_tag_array_stalls 2 # number of stalls caused by tag array 2754system.tcp_cntrl1.L1cache.num_data_array_stalls 2 # number of stalls caused by data array |
| 2755system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 2711system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 3 # loads that hit in the TCP 2712system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 2 # TCP to TCP load transfers 2713system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 2714system.tcp_cntrl1.coalescer.gpu_ld_misses 0 # loads that miss in the GPU 2715system.tcp_cntrl1.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP 2716system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers 2717system.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 2718system.tcp_cntrl1.coalescer.gpu_st_misses 5 # stores that miss in the GPU 2719system.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 2720system.tcp_cntrl1.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 2721system.tcp_cntrl1.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 2722system.tcp_cntrl1.coalescer.cp_ld_misses 0 # loads that miss in the GPU 2723system.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 2724system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 2725system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 2726system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU | 2756system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 3 # loads that hit in the TCP 2757system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 2 # TCP to TCP load transfers 2758system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 2759system.tcp_cntrl1.coalescer.gpu_ld_misses 0 # loads that miss in the GPU 2760system.tcp_cntrl1.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP 2761system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers 2762system.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 2763system.tcp_cntrl1.coalescer.gpu_st_misses 5 # stores that miss in the GPU 2764system.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 2765system.tcp_cntrl1.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 2766system.tcp_cntrl1.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 2767system.tcp_cntrl1.coalescer.cp_ld_misses 0 # loads that miss in the GPU 2768system.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 2769system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 2770system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 2771system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU |
| 2772system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states 2773system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 2727system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits 2728system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses 2729system.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses 2730system.sqc_cntrl0.L1cache.num_data_array_reads 86 # number of data array reads 2731system.sqc_cntrl0.L1cache.num_data_array_writes 5 # number of data array writes 2732system.sqc_cntrl0.L1cache.num_tag_array_reads 86 # number of tag array reads 2733system.sqc_cntrl0.L1cache.num_tag_array_writes 5 # number of tag array writes 2734system.sqc_cntrl0.L1cache.num_data_array_stalls 47 # number of stalls caused by data array | 2774system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits 2775system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses 2776system.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses 2777system.sqc_cntrl0.L1cache.num_data_array_reads 86 # number of data array reads 2778system.sqc_cntrl0.L1cache.num_data_array_writes 5 # number of data array writes 2779system.sqc_cntrl0.L1cache.num_tag_array_reads 86 # number of tag array reads 2780system.sqc_cntrl0.L1cache.num_tag_array_writes 5 # number of tag array writes 2781system.sqc_cntrl0.L1cache.num_data_array_stalls 47 # number of stalls caused by data array |
| 2782system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 2735system.sqc_cntrl0.sequencer.load_waiting_on_load 120 # Number of times a load aliased with a pending load | 2783system.sqc_cntrl0.sequencer.load_waiting_on_load 120 # Number of times a load aliased with a pending load |
| 2784system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 2736system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits 2737system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses 2738system.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses | 2785system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits 2786system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses 2787system.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses |
| 2788system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 2739system.tccdir_cntrl0.directory.demand_hits 0 # Number of cache demand hits 2740system.tccdir_cntrl0.directory.demand_misses 0 # Number of cache demand misses 2741system.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses 2742system.tccdir_cntrl0.directory.num_tag_array_reads 1554 # number of tag array reads 2743system.tccdir_cntrl0.directory.num_tag_array_writes 27 # number of tag array writes | 2789system.tccdir_cntrl0.directory.demand_hits 0 # Number of cache demand hits 2790system.tccdir_cntrl0.directory.demand_misses 0 # Number of cache demand misses 2791system.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses 2792system.tccdir_cntrl0.directory.num_tag_array_reads 1554 # number of tag array reads 2793system.tccdir_cntrl0.directory.num_tag_array_writes 27 # number of tag array writes |
| 2794system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states 2795system.ruby.network.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 2744system.ruby.network.msg_count.Control 3116 2745system.ruby.network.msg_count.Request_Control 3121 2746system.ruby.network.msg_count.Response_Data 3159 2747system.ruby.network.msg_count.Response_Control 3078 2748system.ruby.network.msg_count.Unblock_Control 3121 2749system.ruby.network.msg_byte.Control 24928 2750system.ruby.network.msg_byte.Request_Control 24968 2751system.ruby.network.msg_byte.Response_Data 227448 2752system.ruby.network.msg_byte.Response_Control 24624 2753system.ruby.network.msg_byte.Unblock_Control 24968 2754system.sqc_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2755system.sqc_coalescer.clk_domain.clock 1000 # Clock period in ticks | 2796system.ruby.network.msg_count.Control 3116 2797system.ruby.network.msg_count.Request_Control 3121 2798system.ruby.network.msg_count.Response_Data 3159 2799system.ruby.network.msg_count.Response_Control 3078 2800system.ruby.network.msg_count.Unblock_Control 3121 2801system.ruby.network.msg_byte.Control 24928 2802system.ruby.network.msg_byte.Request_Control 24968 2803system.ruby.network.msg_byte.Response_Data 227448 2804system.ruby.network.msg_byte.Response_Control 24624 2805system.ruby.network.msg_byte.Unblock_Control 24968 2806system.sqc_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2807system.sqc_coalescer.clk_domain.clock 1000 # Clock period in ticks |
| 2808system.sqc_coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 2756system.sqc_coalescer.uncoalesced_accesses 86 # Number of uncoalesced TLB accesses 2757system.sqc_coalescer.coalesced_accesses 60 # Number of coalesced TLB accesses 2758system.sqc_coalescer.queuing_cycles 108000 # Number of cycles spent in queue 2759system.sqc_coalescer.local_queuing_cycles 108000 # Number of cycles spent in queue for all incoming reqs 2760system.sqc_coalescer.local_latency 1255.813953 # Avg. latency over all incoming pkts 2761system.sqc_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2762system.sqc_tlb.clk_domain.clock 1000 # Clock period in ticks | 2809system.sqc_coalescer.uncoalesced_accesses 86 # Number of uncoalesced TLB accesses 2810system.sqc_coalescer.coalesced_accesses 60 # Number of coalesced TLB accesses 2811system.sqc_coalescer.queuing_cycles 108000 # Number of cycles spent in queue 2812system.sqc_coalescer.local_queuing_cycles 108000 # Number of cycles spent in queue for all incoming reqs 2813system.sqc_coalescer.local_latency 1255.813953 # Avg. latency over all incoming pkts 2814system.sqc_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2815system.sqc_tlb.clk_domain.clock 1000 # Clock period in ticks |
| 2816system.sqc_tlb.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 2763system.sqc_tlb.local_TLB_accesses 60 # Number of TLB accesses 2764system.sqc_tlb.local_TLB_hits 59 # Number of TLB hits 2765system.sqc_tlb.local_TLB_misses 1 # Number of TLB misses 2766system.sqc_tlb.local_TLB_miss_rate 1.666667 # TLB miss rate 2767system.sqc_tlb.global_TLB_accesses 86 # Number of TLB accesses 2768system.sqc_tlb.global_TLB_hits 78 # Number of TLB hits 2769system.sqc_tlb.global_TLB_misses 8 # Number of TLB misses 2770system.sqc_tlb.global_TLB_miss_rate 9.302326 # TLB miss rate 2771system.sqc_tlb.access_cycles 86008 # Cycles spent accessing this TLB level 2772system.sqc_tlb.page_table_cycles 0 # Cycles spent accessing the page table 2773system.sqc_tlb.unique_pages 1 # Number of unique pages touched 2774system.sqc_tlb.local_cycles 60001 # Number of cycles spent in queue for all incoming reqs 2775system.sqc_tlb.local_latency 1000.016667 # Avg. latency over incoming coalesced reqs 2776system.sqc_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) | 2817system.sqc_tlb.local_TLB_accesses 60 # Number of TLB accesses 2818system.sqc_tlb.local_TLB_hits 59 # Number of TLB hits 2819system.sqc_tlb.local_TLB_misses 1 # Number of TLB misses 2820system.sqc_tlb.local_TLB_miss_rate 1.666667 # TLB miss rate 2821system.sqc_tlb.global_TLB_accesses 86 # Number of TLB accesses 2822system.sqc_tlb.global_TLB_hits 78 # Number of TLB hits 2823system.sqc_tlb.global_TLB_misses 8 # Number of TLB misses 2824system.sqc_tlb.global_TLB_miss_rate 9.302326 # TLB miss rate 2825system.sqc_tlb.access_cycles 86008 # Cycles spent accessing this TLB level 2826system.sqc_tlb.page_table_cycles 0 # Cycles spent accessing the page table 2827system.sqc_tlb.unique_pages 1 # Number of unique pages touched 2828system.sqc_tlb.local_cycles 60001 # Number of cycles spent in queue for all incoming reqs 2829system.sqc_tlb.local_latency 1000.016667 # Avg. latency over incoming coalesced reqs 2830system.sqc_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) |
| 2831system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states |
|
| 2777system.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.005592 2778system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1551 2779system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Data::2 12 2780system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2 1539 2781system.ruby.network.ext_links0.int_node.throttle0.msg_count.Unblock_Control::4 1551 2782system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0 12408 2783system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Data::2 864 2784system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Control::2 12312 --- 567 unchanged lines hidden --- | 2832system.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.005592 2833system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1551 2834system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Data::2 12 2835system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2 1539 2836system.ruby.network.ext_links0.int_node.throttle0.msg_count.Unblock_Control::4 1551 2837system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0 12408 2838system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Data::2 864 2839system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Control::2 12312 --- 567 unchanged lines hidden --- |