Cross Reference: /gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000663 # Number of seconds simulated
4sim_ticks 663454500 # Number of ticks simulated
5final_tick 663454500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 74039 # Simulator instruction rate (inst/s)
8host_op_rate 152254 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 733530611 # Simulator tick rate (ticks/s)
10host_mem_usage 1301780 # Number of bytes of host memory used
11host_seconds 0.90 # Real time elapsed on the host

7host_inst_rate 97803 # Simulator instruction rate (inst/s)
8host_op_rate 201121 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 968968514 # Simulator tick rate (ticks/s)
10host_mem_usage 1290208 # Number of bytes of host memory used
11host_seconds 0.68 # Real time elapsed on the host

12sim_insts 66963 # Number of instructions simulated
13sim_ops 137705 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.mem_ctrls.bytes_read::dir_cntrl0 99264 # Number of bytes read from this memory
17system.mem_ctrls.bytes_read::total 99264 # Number of bytes read from this memory
18system.mem_ctrls.num_reads::dir_cntrl0 1551 # Number of read requests responded to by this memory
19system.mem_ctrls.num_reads::total 1551 # Number of read requests responded to by this memory

--- 62 unchanged lines hidden (view full) ---

82system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
83system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
84system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2)
85system.mem_ctrls.rdQLenPdf::0 1542 # What read queue length does an incoming req see
86system.mem_ctrls.rdQLenPdf::1 2 # What read queue length does an incoming req see
87system.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see
88system.mem_ctrls.rdQLenPdf::3 1 # What read queue length does an incoming req see
89system.mem_ctrls.rdQLenPdf::4 2 # What read queue length does an incoming req see

90system.mem_ctrls.rdQLenPdf::5 3 # What read queue length does an incoming req see
91system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see

90system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see
91system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see

92system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
93system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
94system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
95system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
96system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
97system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
98system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
99system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see

--- 87 unchanged lines hidden (view full) ---

187system.mem_ctrls.bytesPerActivate::256-383 70 14.43% 83.30% # Bytes accessed per row activation
188system.mem_ctrls.bytesPerActivate::384-511 40 8.25% 91.55% # Bytes accessed per row activation
189system.mem_ctrls.bytesPerActivate::512-639 15 3.09% 94.64% # Bytes accessed per row activation
190system.mem_ctrls.bytesPerActivate::640-767 10 2.06% 96.70% # Bytes accessed per row activation
191system.mem_ctrls.bytesPerActivate::768-895 9 1.86% 98.56% # Bytes accessed per row activation
192system.mem_ctrls.bytesPerActivate::896-1023 2 0.41% 98.97% # Bytes accessed per row activation
193system.mem_ctrls.bytesPerActivate::1024-1151 5 1.03% 100.00% # Bytes accessed per row activation
194system.mem_ctrls.bytesPerActivate::total 485 # Bytes accessed per row activation

195system.mem_ctrls.totQLat 15500500 # Total ticks spent queuing
196system.mem_ctrls.totMemAccLat 44581750 # Total ticks spent from burst creation until serviced by the DRAM

195system.mem_ctrls.totQLat 15500495 # Total ticks spent queuing
196system.mem_ctrls.totMemAccLat 44581745 # Total ticks spent from burst creation until serviced by the DRAM

197system.mem_ctrls.totBusLat 7755000 # Total ticks spent in databus transfers
198system.mem_ctrls.avgQLat 9993.87 # Average queueing delay per DRAM burst
199system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst
200system.mem_ctrls.avgMemAccLat 28743.87 # Average memory access latency per DRAM burst
201system.mem_ctrls.avgRdBW 149.62 # Average DRAM read bandwidth in MiByte/s
202system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
203system.mem_ctrls.avgRdBWSys 149.62 # Average system read bandwidth in MiByte/s
204system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s

--- 83 unchanged lines hidden (view full) ---

288system.ruby.outstanding_req_hist_seqr::samples 114203
289system.ruby.outstanding_req_hist_seqr::mean 1.000035
290system.ruby.outstanding_req_hist_seqr::gmean 1.000024
291system.ruby.outstanding_req_hist_seqr::stdev 0.005918
292system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 114199 100.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
293system.ruby.outstanding_req_hist_seqr::total 114203
294system.ruby.outstanding_req_hist_coalsr::bucket_size 1
295system.ruby.outstanding_req_hist_coalsr::max_bucket 9

296system.ruby.outstanding_req_hist_coalsr::samples 28
297system.ruby.outstanding_req_hist_coalsr::mean 1.642857
298system.ruby.outstanding_req_hist_coalsr::gmean 1.455771
299system.ruby.outstanding_req_hist_coalsr::stdev 0.911421
300system.ruby.outstanding_req_hist_coalsr | 0 0.00% 0.00% | 16 57.14% 57.14% | 8 28.57% 85.71% | 2 7.14% 92.86% | 2 7.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
301system.ruby.outstanding_req_hist_coalsr::total 28

296system.ruby.outstanding_req_hist_coalsr::samples 27
297system.ruby.outstanding_req_hist_coalsr::mean 1.629630
298system.ruby.outstanding_req_hist_coalsr::gmean 1.438746
299system.ruby.outstanding_req_hist_coalsr::stdev 0.926040
300system.ruby.outstanding_req_hist_coalsr | 0 0.00% 0.00% | 16 59.26% 59.26% | 7 25.93% 85.19% | 2 7.41% 92.59% | 2 7.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
301system.ruby.outstanding_req_hist_coalsr::total 27

302system.ruby.latency_hist_seqr::bucket_size 64
303system.ruby.latency_hist_seqr::max_bucket 639
304system.ruby.latency_hist_seqr::samples 114203

305system.ruby.latency_hist_seqr::mean 4.784183

305system.ruby.latency_hist_seqr::mean 4.784165

306system.ruby.latency_hist_seqr::gmean 2.131364

307system.ruby.latency_hist_seqr::stdev 23.846744

307system.ruby.latency_hist_seqr::stdev 23.846473

308system.ruby.latency_hist_seqr | 112668 98.66% 98.66% | 0 0.00% 98.66% | 0 0.00% 98.66% | 1506 1.32% 99.97% | 19 0.02% 99.99% | 10 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
309system.ruby.latency_hist_seqr::total 114203
310system.ruby.latency_hist_coalsr::bucket_size 64
311system.ruby.latency_hist_coalsr::max_bucket 639

312system.ruby.latency_hist_coalsr::samples 28
313system.ruby.latency_hist_coalsr::mean 136.285714
314system.ruby.latency_hist_coalsr::gmean 19.975449
315system.ruby.latency_hist_coalsr::stdev 139.699905
316system.ruby.latency_hist_coalsr | 14 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 10 35.71% 85.71% | 1 3.57% 89.29% | 3 10.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
317system.ruby.latency_hist_coalsr::total 28

312system.ruby.latency_hist_coalsr::samples 27
313system.ruby.latency_hist_coalsr::mean 141.296296
314system.ruby.latency_hist_coalsr::gmean 21.202698
315system.ruby.latency_hist_coalsr::stdev 140.217089
316system.ruby.latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 10 37.04% 85.19% | 1 3.70% 88.89% | 3 11.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
317system.ruby.latency_hist_coalsr::total 27

318system.ruby.hit_latency_hist_seqr::bucket_size 64
319system.ruby.hit_latency_hist_seqr::max_bucket 639
320system.ruby.hit_latency_hist_seqr::samples 1535

321system.ruby.hit_latency_hist_seqr::mean 208.449511
322system.ruby.hit_latency_hist_seqr::gmean 208.002927
323system.ruby.hit_latency_hist_seqr::stdev 15.847049

321system.ruby.hit_latency_hist_seqr::mean 208.448208
322system.ruby.hit_latency_hist_seqr::gmean 208.002202
323system.ruby.hit_latency_hist_seqr::stdev 15.833423

324system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1506 98.11% 98.11% | 19 1.24% 99.35% | 10 0.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
325system.ruby.hit_latency_hist_seqr::total 1535
326system.ruby.miss_latency_hist_seqr::bucket_size 4
327system.ruby.miss_latency_hist_seqr::max_bucket 39
328system.ruby.miss_latency_hist_seqr::samples 112668
329system.ruby.miss_latency_hist_seqr::mean 2.009426
330system.ruby.miss_latency_hist_seqr::gmean 2.002413
331system.ruby.miss_latency_hist_seqr::stdev 0.411800
332system.ruby.miss_latency_hist_seqr | 112609 99.95% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 59 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
333system.ruby.miss_latency_hist_seqr::total 112668
334system.ruby.miss_latency_hist_coalsr::bucket_size 64
335system.ruby.miss_latency_hist_coalsr::max_bucket 639

336system.ruby.miss_latency_hist_coalsr::samples 28
337system.ruby.miss_latency_hist_coalsr::mean 136.285714
338system.ruby.miss_latency_hist_coalsr::gmean 19.975449
339system.ruby.miss_latency_hist_coalsr::stdev 139.699905
340system.ruby.miss_latency_hist_coalsr | 14 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 10 35.71% 85.71% | 1 3.57% 89.29% | 3 10.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
341system.ruby.miss_latency_hist_coalsr::total 28

336system.ruby.miss_latency_hist_coalsr::samples 27
337system.ruby.miss_latency_hist_coalsr::mean 141.296296
338system.ruby.miss_latency_hist_coalsr::gmean 21.202698
339system.ruby.miss_latency_hist_coalsr::stdev 140.217089
340system.ruby.miss_latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 10 37.04% 85.19% | 1 3.70% 88.89% | 3 11.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
341system.ruby.miss_latency_hist_coalsr::total 27

342system.ruby.L1Cache.incomplete_times_seqr 112609
343system.ruby.L2Cache.incomplete_times_seqr 59
344system.cp_cntrl0.L1D0cache.demand_hits 0 # Number of cache demand hits
345system.cp_cntrl0.L1D0cache.demand_misses 506 # Number of cache demand misses
346system.cp_cntrl0.L1D0cache.demand_accesses 506 # Number of cache demand accesses
347system.cp_cntrl0.L1D0cache.num_data_array_reads 16155 # number of data array reads
348system.cp_cntrl0.L1D0cache.num_data_array_writes 11985 # number of data array writes
349system.cp_cntrl0.L1D0cache.num_tag_array_reads 27132 # number of tag array reads

--- 33 unchanged lines hidden (view full) ---

383system.cpu0.num_int_register_writes 110039 # number of times the integer registers were written
384system.cpu0.num_fp_register_reads 1981 # number of times the floating registers were read
385system.cpu0.num_fp_register_writes 981 # number of times the floating registers were written
386system.cpu0.num_cc_register_reads 78262 # number of times the CC registers were read
387system.cpu0.num_cc_register_writes 42183 # number of times the CC registers were written
388system.cpu0.num_mem_refs 27198 # number of memory refs
389system.cpu0.num_load_insts 16684 # Number of load instructions
390system.cpu0.num_store_insts 10514 # Number of store instructions

391system.cpu0.num_idle_cycles 5227.003992 # Number of idle cycles
392system.cpu0.num_busy_cycles 1321681.996008 # Number of busy cycles
393system.cpu0.not_idle_fraction 0.996061 # Percentage of non-idle cycles
394system.cpu0.idle_fraction 0.003939 # Percentage of idle cycles

391system.cpu0.num_idle_cycles 5231.003992 # Number of idle cycles
392system.cpu0.num_busy_cycles 1321677.996008 # Number of busy cycles
393system.cpu0.not_idle_fraction 0.996058 # Percentage of non-idle cycles
394system.cpu0.idle_fraction 0.003942 # Percentage of idle cycles

395system.cpu0.Branches 16199 # Number of branches fetched
396system.cpu0.op_class::No_OpClass 615 0.45% 0.45% # Class of executed instruction
397system.cpu0.op_class::IntAlu 108791 79.00% 79.45% # Class of executed instruction
398system.cpu0.op_class::IntMult 13 0.01% 79.46% # Class of executed instruction
399system.cpu0.op_class::IntDiv 138 0.10% 79.56% # Class of executed instruction
400system.cpu0.op_class::FloatAdd 950 0.69% 80.25% # Class of executed instruction
401system.cpu0.op_class::FloatCmp 0 0.00% 80.25% # Class of executed instruction
402system.cpu0.op_class::FloatCvt 0 0.00% 80.25% # Class of executed instruction

--- 24 unchanged lines hidden (view full) ---

427system.cpu0.op_class::MemWrite 10514 7.64% 100.00% # Class of executed instruction
428system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
429system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
430system.cpu0.op_class::total 137705 # Class of executed instruction
431system.cpu1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
432system.cpu1.clk_domain.clock 1000 # Clock period in ticks
433system.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
434system.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies

435system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 297 # number of times the wf's instructions are blocked due to RAW dependencies

435system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 307 # number of times the wf's instructions are blocked due to RAW dependencies

436system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands
437system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands
438system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands
439system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
440system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands
441system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands
442system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
443system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands

--- 175 unchanged lines hidden (view full) ---

619system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
620system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
621system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
622system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
623system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
624system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
625system.cpu1.CUs0.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
626system.cpu1.CUs0.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies

627system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 273 # number of times the wf's instructions are blocked due to RAW dependencies

627system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 279 # number of times the wf's instructions are blocked due to RAW dependencies

628system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
629system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
630system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
631system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
632system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
633system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
634system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
635system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands

--- 175 unchanged lines hidden (view full) ---

811system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
812system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
813system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
814system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
815system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
816system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
817system.cpu1.CUs0.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
818system.cpu1.CUs0.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies

819system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 272 # number of times the wf's instructions are blocked due to RAW dependencies

819system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 282 # number of times the wf's instructions are blocked due to RAW dependencies

820system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
821system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
822system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
823system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
824system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
825system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
826system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
827system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands

--- 175 unchanged lines hidden (view full) ---

1003system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
1004system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
1005system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
1006system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
1007system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
1008system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
1009system.cpu1.CUs0.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
1010system.cpu1.CUs0.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies

1011system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 256 # number of times the wf's instructions are blocked due to RAW dependencies

1011system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 276 # number of times the wf's instructions are blocked due to RAW dependencies

1012system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
1013system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
1014system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
1015system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
1016system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
1017system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
1018system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
1019system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands

--- 213 unchanged lines hidden (view full) ---

1233system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
1234system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
1235system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
1236system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
1237system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
1238system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it
1239system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it
1240system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it

1241system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 3230 # number of cycles the CU issues nothing
1242system.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued 128 # number of cycles the CU issued at least one instruction

1241system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 3261 # number of cycles the CU issues nothing
1242system.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued 99 # number of cycles the CU issued at least one instruction

1243system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued
1244system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued
1245system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued
1246system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued
1247system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued
1248system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued

1249system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 780 # Number of cycles no instruction of specific type issued
1250system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 367 # Number of cycles no instruction of specific type issued
1251system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 384 # Number of cycles no instruction of specific type issued
1252system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 327 # Number of cycles no instruction of specific type issued
1253system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 414 # Number of cycles no instruction of specific type issued
1254system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM 30 # Number of cycles no instruction of specific type issued
1255system.cpu1.CUs0.ExecStage.spc::samples 3358 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1256system.cpu1.CUs0.ExecStage.spc::mean 0.041989 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1257system.cpu1.CUs0.ExecStage.spc::stdev 0.220406 # Execution units active per cycle (Exec unit=SIMD,MemPipe)

1249system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 769 # Number of cycles no instruction of specific type issued
1250system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 357 # Number of cycles no instruction of specific type issued
1251system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 375 # Number of cycles no instruction of specific type issued
1252system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 332 # Number of cycles no instruction of specific type issued
1253system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 398 # Number of cycles no instruction of specific type issued
1254system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM 22 # Number of cycles no instruction of specific type issued
1255system.cpu1.CUs0.ExecStage.spc::samples 3360 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1256system.cpu1.CUs0.ExecStage.spc::mean 0.041964 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1257system.cpu1.CUs0.ExecStage.spc::stdev 0.257708 # Execution units active per cycle (Exec unit=SIMD,MemPipe)

1258system.cpu1.CUs0.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)

1259system.cpu1.CUs0.ExecStage.spc::0 3230 96.19% 96.19% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1260system.cpu1.CUs0.ExecStage.spc::1 116 3.45% 99.64% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1261system.cpu1.CUs0.ExecStage.spc::2 11 0.33% 99.97% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1262system.cpu1.CUs0.ExecStage.spc::3 1 0.03% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)

1259system.cpu1.CUs0.ExecStage.spc::0 3261 97.05% 97.05% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1260system.cpu1.CUs0.ExecStage.spc::1 59 1.76% 98.81% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1261system.cpu1.CUs0.ExecStage.spc::2 38 1.13% 99.94% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1262system.cpu1.CUs0.ExecStage.spc::3 2 0.06% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)

1263system.cpu1.CUs0.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1264system.cpu1.CUs0.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1265system.cpu1.CUs0.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1266system.cpu1.CUs0.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1267system.cpu1.CUs0.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1268system.cpu1.CUs0.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe)

1269system.cpu1.CUs0.ExecStage.spc::total 3358 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1270system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 82 # number of CU transitions from active to idle
1271system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 82 # duration of idle periods in cycles
1272system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 39.280488 # duration of idle periods in cycles
1273system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 158.161058 # duration of idle periods in cycles

1269system.cpu1.CUs0.ExecStage.spc::total 3360 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1270system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 93 # number of CU transitions from active to idle
1271system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 93 # duration of idle periods in cycles
1272system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 34.967742 # duration of idle periods in cycles
1273system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 149.478110 # duration of idle periods in cycles

1274system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles

1275system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 62 75.61% 75.61% # duration of idle periods in cycles
1276system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 9 10.98% 86.59% # duration of idle periods in cycles
1277system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 1 1.22% 87.80% # duration of idle periods in cycles
1278system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 0 0.00% 87.80% # duration of idle periods in cycles
1279system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 2 2.44% 90.24% # duration of idle periods in cycles
1280system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.22% 91.46% # duration of idle periods in cycles
1281system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 91.46% # duration of idle periods in cycles
1282system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 91.46% # duration of idle periods in cycles
1283system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 91.46% # duration of idle periods in cycles
1284system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 91.46% # duration of idle periods in cycles
1285system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 91.46% # duration of idle periods in cycles
1286system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 91.46% # duration of idle periods in cycles
1287system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 91.46% # duration of idle periods in cycles
1288system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 91.46% # duration of idle periods in cycles
1289system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 91.46% # duration of idle periods in cycles
1290system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 91.46% # duration of idle periods in cycles
1291system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 7 8.54% 100.00% # duration of idle periods in cycles

1275system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 74 79.57% 79.57% # duration of idle periods in cycles
1276system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 7 7.53% 87.10% # duration of idle periods in cycles
1277system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 1 1.08% 88.17% # duration of idle periods in cycles
1278system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 1 1.08% 89.25% # duration of idle periods in cycles
1279system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 2 2.15% 91.40% # duration of idle periods in cycles
1280system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.08% 92.47% # duration of idle periods in cycles
1281system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 92.47% # duration of idle periods in cycles
1282system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 92.47% # duration of idle periods in cycles
1283system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 92.47% # duration of idle periods in cycles
1284system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 92.47% # duration of idle periods in cycles
1285system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 92.47% # duration of idle periods in cycles
1286system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 92.47% # duration of idle periods in cycles
1287system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 92.47% # duration of idle periods in cycles
1288system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 92.47% # duration of idle periods in cycles
1289system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 92.47% # duration of idle periods in cycles
1290system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 92.47% # duration of idle periods in cycles
1291system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 7 7.53% 100.00% # duration of idle periods in cycles

1292system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles
1293system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::max_value 1285 # duration of idle periods in cycles

1294system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 82 # duration of idle periods in cycles

1294system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 93 # duration of idle periods in cycles

1295system.cpu1.CUs0.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF
1296system.cpu1.CUs0.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF
1297system.cpu1.CUs0.tlb_requests 769 # number of uncoalesced requests

1298system.cpu1.CUs0.tlb_cycles -452460956000 # total number of cycles for all uncoalesced requests
1299system.cpu1.CUs0.avg_translation_latency -588375755.526658 # Avg. translation latency for data translations

1298system.cpu1.CUs0.tlb_cycles -452453001000 # total number of cycles for all uncoalesced requests
1299system.cpu1.CUs0.avg_translation_latency -588365410.923277 # Avg. translation latency for data translations

1300system.cpu1.CUs0.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB
1301system.cpu1.CUs0.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
1302system.cpu1.CUs0.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
1303system.cpu1.CUs0.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
1304system.cpu1.CUs0.lds_bank_access_cnt 54 # Total number of LDS bank accesses
1305system.cpu1.CUs0.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet
1306system.cpu1.CUs0.lds_bank_conflicts::mean 8 # Number of bank conflicts per LDS memory packet
1307system.cpu1.CUs0.lds_bank_conflicts::stdev 6.196773 # Number of bank conflicts per LDS memory packet

--- 60 unchanged lines hidden (view full) ---

1368system.cpu1.CUs0.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.)
1369system.cpu1.CUs0.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.)
1370system.cpu1.CUs0.global_mem_instr_cnt 17 # dynamic global memory instructions count
1371system.cpu1.CUs0.local_mem_instr_cnt 6 # dynamic local memory intruction count
1372system.cpu1.CUs0.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity
1373system.cpu1.CUs0.num_instr_executed 141 # number of instructions executed
1374system.cpu1.CUs0.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle
1375system.cpu1.CUs0.inst_exec_rate::mean 86.382979 # Instruction Execution Rate: Number of executed vector instructions per cycle

1376system.cpu1.CUs0.inst_exec_rate::stdev 229.391669 # Instruction Execution Rate: Number of executed vector instructions per cycle

1376system.cpu1.CUs0.inst_exec_rate::stdev 229.706697 # Instruction Execution Rate: Number of executed vector instructions per cycle

1377system.cpu1.CUs0.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle

1378system.cpu1.CUs0.inst_exec_rate::0-1 1 0.71% 0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle
1379system.cpu1.CUs0.inst_exec_rate::2-3 12 8.51% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle
1380system.cpu1.CUs0.inst_exec_rate::4-5 51 36.17% 45.39% # Instruction Execution Rate: Number of executed vector instructions per cycle
1381system.cpu1.CUs0.inst_exec_rate::6-7 32 22.70% 68.09% # Instruction Execution Rate: Number of executed vector instructions per cycle
1382system.cpu1.CUs0.inst_exec_rate::8-9 2 1.42% 69.50% # Instruction Execution Rate: Number of executed vector instructions per cycle
1383system.cpu1.CUs0.inst_exec_rate::10 2 1.42% 70.92% # Instruction Execution Rate: Number of executed vector instructions per cycle
1384system.cpu1.CUs0.inst_exec_rate::overflows 41 29.08% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
1385system.cpu1.CUs0.inst_exec_rate::min_value 1 # Instruction Execution Rate: Number of executed vector instructions per cycle

1378system.cpu1.CUs0.inst_exec_rate::0-1 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
1379system.cpu1.CUs0.inst_exec_rate::2-3 12 8.51% 8.51% # Instruction Execution Rate: Number of executed vector instructions per cycle
1380system.cpu1.CUs0.inst_exec_rate::4-5 52 36.88% 45.39% # Instruction Execution Rate: Number of executed vector instructions per cycle
1381system.cpu1.CUs0.inst_exec_rate::6-7 31 21.99% 67.38% # Instruction Execution Rate: Number of executed vector instructions per cycle
1382system.cpu1.CUs0.inst_exec_rate::8-9 3 2.13% 69.50% # Instruction Execution Rate: Number of executed vector instructions per cycle
1383system.cpu1.CUs0.inst_exec_rate::10 3 2.13% 71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle
1384system.cpu1.CUs0.inst_exec_rate::overflows 40 28.37% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
1385system.cpu1.CUs0.inst_exec_rate::min_value 2 # Instruction Execution Rate: Number of executed vector instructions per cycle

1386system.cpu1.CUs0.inst_exec_rate::max_value 1291 # Instruction Execution Rate: Number of executed vector instructions per cycle
1387system.cpu1.CUs0.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle
1388system.cpu1.CUs0.num_vec_ops_executed 6769 # number of vec ops executed (e.g. VSZ/inst)

1389system.cpu1.CUs0.num_total_cycles 3358 # number of cycles the CU ran for
1390system.cpu1.CUs0.vpc 2.015783 # Vector Operations per cycle (this CU only)
1391system.cpu1.CUs0.ipc 0.041989 # Instructions per cycle (this CU only)

1389system.cpu1.CUs0.num_total_cycles 3360 # number of cycles the CU ran for
1390system.cpu1.CUs0.vpc 2.014583 # Vector Operations per cycle (this CU only)
1391system.cpu1.CUs0.ipc 0.041964 # Instructions per cycle (this CU only)

1392system.cpu1.CUs0.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions)
1393system.cpu1.CUs0.warp_execution_dist::mean 48.007092 # number of lanes active per instruction (oval all instructions)
1394system.cpu1.CUs0.warp_execution_dist::stdev 23.719942 # number of lanes active per instruction (oval all instructions)
1395system.cpu1.CUs0.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions)
1396system.cpu1.CUs0.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions)
1397system.cpu1.CUs0.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions)
1398system.cpu1.CUs0.warp_execution_dist::9-12 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions)
1399system.cpu1.CUs0.warp_execution_dist::13-16 36 25.53% 29.08% # number of lanes active per instruction (oval all instructions)

--- 63 unchanged lines hidden (view full) ---

1463system.cpu1.CUs0.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction
1464system.cpu1.CUs0.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed
1465system.cpu1.CUs0.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD
1466system.cpu1.CUs0.num_CAS_ops 0 # number of compare and swap operations
1467system.cpu1.CUs0.num_failed_CAS_ops 0 # number of compare and swap operations that failed
1468system.cpu1.CUs0.num_completed_wfs 4 # number of completed wavefronts
1469system.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
1470system.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies

1471system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 381 # number of times the wf's instructions are blocked due to RAW dependencies

1471system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 401 # number of times the wf's instructions are blocked due to RAW dependencies

1472system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands
1473system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands
1474system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands
1475system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
1476system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands
1477system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands
1478system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
1479system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands

--- 175 unchanged lines hidden (view full) ---

1655system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
1656system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
1657system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
1658system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
1659system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
1660system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
1661system.cpu1.CUs1.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
1662system.cpu1.CUs1.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies

1663system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 356 # number of times the wf's instructions are blocked due to RAW dependencies

1663system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 372 # number of times the wf's instructions are blocked due to RAW dependencies

1664system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
1665system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
1666system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
1667system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
1668system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
1669system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
1670system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
1671system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands

--- 175 unchanged lines hidden (view full) ---

1847system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
1848system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
1849system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
1850system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
1851system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
1852system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
1853system.cpu1.CUs1.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
1854system.cpu1.CUs1.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies

1855system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 356 # number of times the wf's instructions are blocked due to RAW dependencies

1855system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 371 # number of times the wf's instructions are blocked due to RAW dependencies

1856system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
1857system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
1858system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
1859system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
1860system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
1861system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
1862system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
1863system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands

--- 175 unchanged lines hidden (view full) ---

2039system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
2040system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
2041system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
2042system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
2043system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
2044system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
2045system.cpu1.CUs1.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
2046system.cpu1.CUs1.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies

2047system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 339 # number of times the wf's instructions are blocked due to RAW dependencies

2047system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 361 # number of times the wf's instructions are blocked due to RAW dependencies

2048system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
2049system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
2050system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
2051system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
2052system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
2053system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
2054system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
2055system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands

--- 213 unchanged lines hidden (view full) ---

2269system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
2270system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
2271system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
2272system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
2273system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
2274system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it
2275system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it
2276system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it

2277system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 3228 # number of cycles the CU issues nothing
2278system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 130 # number of cycles the CU issued at least one instruction

2277system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 3261 # number of cycles the CU issues nothing
2278system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 99 # number of cycles the CU issued at least one instruction

2279system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued
2280system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued
2281system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued
2282system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued
2283system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued
2284system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued

2285system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 778 # Number of cycles no instruction of specific type issued

2285system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 777 # Number of cycles no instruction of specific type issued

2286system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 472 # Number of cycles no instruction of specific type issued

2287system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 447 # Number of cycles no instruction of specific type issued
2288system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 411 # Number of cycles no instruction of specific type issued
2289system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 417 # Number of cycles no instruction of specific type issued
2290system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM 26 # Number of cycles no instruction of specific type issued
2291system.cpu1.CUs1.ExecStage.spc::samples 3358 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2292system.cpu1.CUs1.ExecStage.spc::mean 0.041989 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2293system.cpu1.CUs1.ExecStage.spc::stdev 0.217686 # Execution units active per cycle (Exec unit=SIMD,MemPipe)

2287system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 444 # Number of cycles no instruction of specific type issued
2288system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 416 # Number of cycles no instruction of specific type issued
2289system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 404 # Number of cycles no instruction of specific type issued
2290system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM 22 # Number of cycles no instruction of specific type issued
2291system.cpu1.CUs1.ExecStage.spc::samples 3360 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2292system.cpu1.CUs1.ExecStage.spc::mean 0.041964 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2293system.cpu1.CUs1.ExecStage.spc::stdev 0.256550 # Execution units active per cycle (Exec unit=SIMD,MemPipe)

2294system.cpu1.CUs1.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)

2295system.cpu1.CUs1.ExecStage.spc::0 3228 96.13% 96.13% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2296system.cpu1.CUs1.ExecStage.spc::1 120 3.57% 99.70% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2297system.cpu1.CUs1.ExecStage.spc::2 9 0.27% 99.97% # Execution units active per cycle (Exec unit=SIMD,MemPipe)

2295system.cpu1.CUs1.ExecStage.spc::0 3261 97.05% 97.05% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2296system.cpu1.CUs1.ExecStage.spc::1 58 1.73% 98.78% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2297system.cpu1.CUs1.ExecStage.spc::2 40 1.19% 99.97% # Execution units active per cycle (Exec unit=SIMD,MemPipe)

2298system.cpu1.CUs1.ExecStage.spc::3 1 0.03% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2299system.cpu1.CUs1.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2300system.cpu1.CUs1.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2301system.cpu1.CUs1.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2302system.cpu1.CUs1.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2303system.cpu1.CUs1.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2304system.cpu1.CUs1.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe)

2305system.cpu1.CUs1.ExecStage.spc::total 3358 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2306system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 81 # number of CU transitions from active to idle
2307system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 81 # duration of idle periods in cycles
2308system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 38.617284 # duration of idle periods in cycles
2309system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 158.076213 # duration of idle periods in cycles

2305system.cpu1.CUs1.ExecStage.spc::total 3360 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2306system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 94 # number of CU transitions from active to idle
2307system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 94 # duration of idle periods in cycles
2308system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 33.585106 # duration of idle periods in cycles
2309system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 147.747562 # duration of idle periods in cycles

2310system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles

2311system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 60 74.07% 74.07% # duration of idle periods in cycles
2312system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 10 12.35% 86.42% # duration of idle periods in cycles
2313system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 86.42% # duration of idle periods in cycles
2314system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 2 2.47% 88.89% # duration of idle periods in cycles
2315system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 2 2.47% 91.36% # duration of idle periods in cycles
2316system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 0 0.00% 91.36% # duration of idle periods in cycles
2317system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 91.36% # duration of idle periods in cycles
2318system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 91.36% # duration of idle periods in cycles
2319system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 91.36% # duration of idle periods in cycles
2320system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 91.36% # duration of idle periods in cycles
2321system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 91.36% # duration of idle periods in cycles
2322system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 91.36% # duration of idle periods in cycles
2323system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 91.36% # duration of idle periods in cycles
2324system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 91.36% # duration of idle periods in cycles
2325system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 91.36% # duration of idle periods in cycles
2326system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 91.36% # duration of idle periods in cycles
2327system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 7 8.64% 100.00% # duration of idle periods in cycles

2311system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 75 79.79% 79.79% # duration of idle periods in cycles
2312system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 8 8.51% 88.30% # duration of idle periods in cycles
2313system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 88.30% # duration of idle periods in cycles
2314system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 1 1.06% 89.36% # duration of idle periods in cycles
2315system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 2 2.13% 91.49% # duration of idle periods in cycles
2316system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 1 1.06% 92.55% # duration of idle periods in cycles
2317system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 92.55% # duration of idle periods in cycles
2318system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 92.55% # duration of idle periods in cycles
2319system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 92.55% # duration of idle periods in cycles
2320system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 92.55% # duration of idle periods in cycles
2321system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 92.55% # duration of idle periods in cycles
2322system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 92.55% # duration of idle periods in cycles
2323system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 92.55% # duration of idle periods in cycles
2324system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 92.55% # duration of idle periods in cycles
2325system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 92.55% # duration of idle periods in cycles
2326system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 92.55% # duration of idle periods in cycles
2327system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 7 7.45% 100.00% # duration of idle periods in cycles

2328system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles
2329system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::max_value 1293 # duration of idle periods in cycles

2330system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 81 # duration of idle periods in cycles

2330system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 94 # duration of idle periods in cycles

2331system.cpu1.CUs1.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF
2332system.cpu1.CUs1.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF
2333system.cpu1.CUs1.tlb_requests 769 # number of uncoalesced requests

2334system.cpu1.CUs1.tlb_cycles -452466433000 # total number of cycles for all uncoalesced requests
2335system.cpu1.CUs1.avg_translation_latency -588382877.763329 # Avg. translation latency for data translations

2334system.cpu1.CUs1.tlb_cycles -452459838000 # total number of cycles for all uncoalesced requests
2335system.cpu1.CUs1.avg_translation_latency -588374301.690507 # Avg. translation latency for data translations

2336system.cpu1.CUs1.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB
2337system.cpu1.CUs1.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
2338system.cpu1.CUs1.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
2339system.cpu1.CUs1.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
2340system.cpu1.CUs1.lds_bank_access_cnt 53 # Total number of LDS bank accesses
2341system.cpu1.CUs1.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet
2342system.cpu1.CUs1.lds_bank_conflicts::mean 7.833333 # Number of bank conflicts per LDS memory packet
2343system.cpu1.CUs1.lds_bank_conflicts::stdev 6.080022 # Number of bank conflicts per LDS memory packet

--- 59 unchanged lines hidden (view full) ---

2403system.cpu1.CUs1.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.)
2404system.cpu1.CUs1.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.)
2405system.cpu1.CUs1.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.)
2406system.cpu1.CUs1.global_mem_instr_cnt 17 # dynamic global memory instructions count
2407system.cpu1.CUs1.local_mem_instr_cnt 6 # dynamic local memory intruction count
2408system.cpu1.CUs1.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity
2409system.cpu1.CUs1.num_instr_executed 141 # number of instructions executed
2410system.cpu1.CUs1.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle

2411system.cpu1.CUs1.inst_exec_rate::mean 85.666667 # Instruction Execution Rate: Number of executed vector instructions per cycle
2412system.cpu1.CUs1.inst_exec_rate::stdev 230.212531 # Instruction Execution Rate: Number of executed vector instructions per cycle

2411system.cpu1.CUs1.inst_exec_rate::mean 85.553191 # Instruction Execution Rate: Number of executed vector instructions per cycle
2412system.cpu1.CUs1.inst_exec_rate::stdev 230.829913 # Instruction Execution Rate: Number of executed vector instructions per cycle

2413system.cpu1.CUs1.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle

2414system.cpu1.CUs1.inst_exec_rate::0-1 1 0.71% 0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle
2415system.cpu1.CUs1.inst_exec_rate::2-3 12 8.51% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle

2414system.cpu1.CUs1.inst_exec_rate::0-1 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
2415system.cpu1.CUs1.inst_exec_rate::2-3 13 9.22% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle

2416system.cpu1.CUs1.inst_exec_rate::4-5 52 36.88% 46.10% # Instruction Execution Rate: Number of executed vector instructions per cycle
2417system.cpu1.CUs1.inst_exec_rate::6-7 33 23.40% 69.50% # Instruction Execution Rate: Number of executed vector instructions per cycle

2418system.cpu1.CUs1.inst_exec_rate::8-9 4 2.84% 72.34% # Instruction Execution Rate: Number of executed vector instructions per cycle
2419system.cpu1.CUs1.inst_exec_rate::10 1 0.71% 73.05% # Instruction Execution Rate: Number of executed vector instructions per cycle
2420system.cpu1.CUs1.inst_exec_rate::overflows 38 26.95% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
2421system.cpu1.CUs1.inst_exec_rate::min_value 1 # Instruction Execution Rate: Number of executed vector instructions per cycle

2418system.cpu1.CUs1.inst_exec_rate::8-9 6 4.26% 73.76% # Instruction Execution Rate: Number of executed vector instructions per cycle
2419system.cpu1.CUs1.inst_exec_rate::10 0 0.00% 73.76% # Instruction Execution Rate: Number of executed vector instructions per cycle
2420system.cpu1.CUs1.inst_exec_rate::overflows 37 26.24% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
2421system.cpu1.CUs1.inst_exec_rate::min_value 2 # Instruction Execution Rate: Number of executed vector instructions per cycle

2422system.cpu1.CUs1.inst_exec_rate::max_value 1299 # Instruction Execution Rate: Number of executed vector instructions per cycle
2423system.cpu1.CUs1.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle
2424system.cpu1.CUs1.num_vec_ops_executed 6762 # number of vec ops executed (e.g. VSZ/inst)

2425system.cpu1.CUs1.num_total_cycles 3358 # number of cycles the CU ran for
2426system.cpu1.CUs1.vpc 2.013699 # Vector Operations per cycle (this CU only)
2427system.cpu1.CUs1.ipc 0.041989 # Instructions per cycle (this CU only)

2425system.cpu1.CUs1.num_total_cycles 3360 # number of cycles the CU ran for
2426system.cpu1.CUs1.vpc 2.012500 # Vector Operations per cycle (this CU only)
2427system.cpu1.CUs1.ipc 0.041964 # Instructions per cycle (this CU only)

2428system.cpu1.CUs1.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions)
2429system.cpu1.CUs1.warp_execution_dist::mean 47.957447 # number of lanes active per instruction (oval all instructions)
2430system.cpu1.CUs1.warp_execution_dist::stdev 23.818022 # number of lanes active per instruction (oval all instructions)
2431system.cpu1.CUs1.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions)
2432system.cpu1.CUs1.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions)
2433system.cpu1.CUs1.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions)
2434system.cpu1.CUs1.warp_execution_dist::9-12 9 6.38% 9.93% # number of lanes active per instruction (oval all instructions)
2435system.cpu1.CUs1.warp_execution_dist::13-16 27 19.15% 29.08% # number of lanes active per instruction (oval all instructions)

--- 218 unchanged lines hidden (view full) ---

2654system.ruby.network.ext_links1.int_node.msg_bytes.Control::0 128
2655system.ruby.network.ext_links1.int_node.msg_bytes.Request_Control::0 12280
2656system.ruby.network.ext_links1.int_node.msg_bytes.Response_Data::2 110664
2657system.ruby.network.ext_links1.int_node.msg_bytes.Response_Control::2 112
2658system.ruby.network.ext_links1.int_node.msg_bytes.Unblock_Control::4 12280
2659system.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits
2660system.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses
2661system.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses

2662system.tcp_cntrl0.L1cache.num_data_array_reads 10 # number of data array reads

2662system.tcp_cntrl0.L1cache.num_data_array_reads 9 # number of data array reads

2663system.tcp_cntrl0.L1cache.num_data_array_writes 11 # number of data array writes

2664system.tcp_cntrl0.L1cache.num_tag_array_reads 27 # number of tag array reads

2664system.tcp_cntrl0.L1cache.num_tag_array_reads 26 # number of tag array reads

2665system.tcp_cntrl0.L1cache.num_tag_array_writes 18 # number of tag array writes

2666system.tcp_cntrl0.L1cache.num_tag_array_stalls 2 # number of stalls caused by tag array

2667system.tcp_cntrl0.L1cache.num_data_array_stalls 2 # number of stalls caused by data array

2666system.tcp_cntrl0.L1cache.num_data_array_stalls 2 # number of stalls caused by data array

2668system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 3 # loads that hit in the TCP

2667system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 2 # loads that hit in the TCP

2669system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers
2670system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
2671system.tcp_cntrl0.coalescer.gpu_ld_misses 2 # loads that miss in the GPU
2672system.tcp_cntrl0.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP
2673system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 1 # TCP to TCP store transfers
2674system.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC
2675system.tcp_cntrl0.coalescer.gpu_st_misses 4 # stores that miss in the GPU
2676system.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP

--- 50 unchanged lines hidden (view full) ---

2727system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU
2728system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits
2729system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses
2730system.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses
2731system.sqc_cntrl0.L1cache.num_data_array_reads 86 # number of data array reads
2732system.sqc_cntrl0.L1cache.num_data_array_writes 5 # number of data array writes
2733system.sqc_cntrl0.L1cache.num_tag_array_reads 86 # number of tag array reads
2734system.sqc_cntrl0.L1cache.num_tag_array_writes 5 # number of tag array writes

2668system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers
2669system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
2670system.tcp_cntrl0.coalescer.gpu_ld_misses 2 # loads that miss in the GPU
2671system.tcp_cntrl0.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP
2672system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 1 # TCP to TCP store transfers
2673system.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC
2674system.tcp_cntrl0.coalescer.gpu_st_misses 4 # stores that miss in the GPU
2675system.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP

--- 50 unchanged lines hidden (view full) ---

2726system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU
2727system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits
2728system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses
2729system.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses
2730system.sqc_cntrl0.L1cache.num_data_array_reads 86 # number of data array reads
2731system.sqc_cntrl0.L1cache.num_data_array_writes 5 # number of data array writes
2732system.sqc_cntrl0.L1cache.num_tag_array_reads 86 # number of tag array reads
2733system.sqc_cntrl0.L1cache.num_tag_array_writes 5 # number of tag array writes

2735system.sqc_cntrl0.L1cache.num_data_array_stalls 44 # number of stalls caused by data array

2734system.sqc_cntrl0.L1cache.num_data_array_stalls 47 # number of stalls caused by data array

2736system.sqc_cntrl0.sequencer.load_waiting_on_load 120 # Number of times a load aliased with a pending load
2737system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits
2738system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses
2739system.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses
2740system.tccdir_cntrl0.directory.demand_hits 0 # Number of cache demand hits
2741system.tccdir_cntrl0.directory.demand_misses 0 # Number of cache demand misses
2742system.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses
2743system.tccdir_cntrl0.directory.num_tag_array_reads 1554 # number of tag array reads

--- 6 unchanged lines hidden (view full) ---

2750system.ruby.network.msg_byte.Control 24928
2751system.ruby.network.msg_byte.Request_Control 24968
2752system.ruby.network.msg_byte.Response_Data 227448
2753system.ruby.network.msg_byte.Response_Control 24624
2754system.ruby.network.msg_byte.Unblock_Control 24968
2755system.sqc_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
2756system.sqc_coalescer.clk_domain.clock 1000 # Clock period in ticks
2757system.sqc_coalescer.uncoalesced_accesses 86 # Number of uncoalesced TLB accesses

2735system.sqc_cntrl0.sequencer.load_waiting_on_load 120 # Number of times a load aliased with a pending load
2736system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits
2737system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses
2738system.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses
2739system.tccdir_cntrl0.directory.demand_hits 0 # Number of cache demand hits
2740system.tccdir_cntrl0.directory.demand_misses 0 # Number of cache demand misses
2741system.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses
2742system.tccdir_cntrl0.directory.num_tag_array_reads 1554 # number of tag array reads

--- 6 unchanged lines hidden (view full) ---

2749system.ruby.network.msg_byte.Control 24928
2750system.ruby.network.msg_byte.Request_Control 24968
2751system.ruby.network.msg_byte.Response_Data 227448
2752system.ruby.network.msg_byte.Response_Control 24624
2753system.ruby.network.msg_byte.Unblock_Control 24968
2754system.sqc_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
2755system.sqc_coalescer.clk_domain.clock 1000 # Clock period in ticks
2756system.sqc_coalescer.uncoalesced_accesses 86 # Number of uncoalesced TLB accesses

2758system.sqc_coalescer.coalesced_accesses 63 # Number of coalesced TLB accesses
2759system.sqc_coalescer.queuing_cycles 100000 # Number of cycles spent in queue
2760system.sqc_coalescer.local_queuing_cycles 100000 # Number of cycles spent in queue for all incoming reqs
2761system.sqc_coalescer.local_latency 1162.790698 # Avg. latency over all incoming pkts

2757system.sqc_coalescer.coalesced_accesses 60 # Number of coalesced TLB accesses
2758system.sqc_coalescer.queuing_cycles 108000 # Number of cycles spent in queue
2759system.sqc_coalescer.local_queuing_cycles 108000 # Number of cycles spent in queue for all incoming reqs
2760system.sqc_coalescer.local_latency 1255.813953 # Avg. latency over all incoming pkts

2762system.sqc_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
2763system.sqc_tlb.clk_domain.clock 1000 # Clock period in ticks

2761system.sqc_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
2762system.sqc_tlb.clk_domain.clock 1000 # Clock period in ticks

2764system.sqc_tlb.local_TLB_accesses 63 # Number of TLB accesses
2765system.sqc_tlb.local_TLB_hits 62 # Number of TLB hits

2763system.sqc_tlb.local_TLB_accesses 60 # Number of TLB accesses
2764system.sqc_tlb.local_TLB_hits 59 # Number of TLB hits

2766system.sqc_tlb.local_TLB_misses 1 # Number of TLB misses

2765system.sqc_tlb.local_TLB_misses 1 # Number of TLB misses

2767system.sqc_tlb.local_TLB_miss_rate 1.587302 # TLB miss rate

2766system.sqc_tlb.local_TLB_miss_rate 1.666667 # TLB miss rate

2768system.sqc_tlb.global_TLB_accesses 86 # Number of TLB accesses
2769system.sqc_tlb.global_TLB_hits 78 # Number of TLB hits
2770system.sqc_tlb.global_TLB_misses 8 # Number of TLB misses
2771system.sqc_tlb.global_TLB_miss_rate 9.302326 # TLB miss rate
2772system.sqc_tlb.access_cycles 86008 # Cycles spent accessing this TLB level
2773system.sqc_tlb.page_table_cycles 0 # Cycles spent accessing the page table
2774system.sqc_tlb.unique_pages 1 # Number of unique pages touched

2767system.sqc_tlb.global_TLB_accesses 86 # Number of TLB accesses
2768system.sqc_tlb.global_TLB_hits 78 # Number of TLB hits
2769system.sqc_tlb.global_TLB_misses 8 # Number of TLB misses
2770system.sqc_tlb.global_TLB_miss_rate 9.302326 # TLB miss rate
2771system.sqc_tlb.access_cycles 86008 # Cycles spent accessing this TLB level
2772system.sqc_tlb.page_table_cycles 0 # Cycles spent accessing the page table
2773system.sqc_tlb.unique_pages 1 # Number of unique pages touched

2775system.sqc_tlb.local_cycles 63001 # Number of cycles spent in queue for all incoming reqs
2776system.sqc_tlb.local_latency 1000.015873 # Avg. latency over incoming coalesced reqs

2774system.sqc_tlb.local_cycles 60001 # Number of cycles spent in queue for all incoming reqs
2775system.sqc_tlb.local_latency 1000.016667 # Avg. latency over incoming coalesced reqs

2777system.sqc_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
2778system.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.005592
2779system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1551
2780system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Data::2 12
2781system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2 1539
2782system.ruby.network.ext_links0.int_node.throttle0.msg_count.Unblock_Control::4 1551
2783system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0 12408
2784system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Data::2 864

--- 107 unchanged lines hidden (view full) ---

2892system.ruby.Directory_Controller.RdBlk 177 0.00% 0.00%
2893system.ruby.Directory_Controller.CPUPrbResp 1551 0.00% 0.00%
2894system.ruby.Directory_Controller.ProbeAcksComplete 1551 0.00% 0.00%
2895system.ruby.Directory_Controller.MemData 1551 0.00% 0.00%
2896system.ruby.Directory_Controller.CoreUnblock 1551 0.00% 0.00%
2897system.ruby.Directory_Controller.U.RdBlkS 1039 0.00% 0.00%
2898system.ruby.Directory_Controller.U.RdBlkM 335 0.00% 0.00%
2899system.ruby.Directory_Controller.U.RdBlk 177 0.00% 0.00%

2776system.sqc_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
2777system.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.005592
2778system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1551
2779system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Data::2 12
2780system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2 1539
2781system.ruby.network.ext_links0.int_node.throttle0.msg_count.Unblock_Control::4 1551
2782system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0 12408
2783system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Data::2 864

--- 107 unchanged lines hidden (view full) ---

2891system.ruby.Directory_Controller.RdBlk 177 0.00% 0.00%
2892system.ruby.Directory_Controller.CPUPrbResp 1551 0.00% 0.00%
2893system.ruby.Directory_Controller.ProbeAcksComplete 1551 0.00% 0.00%
2894system.ruby.Directory_Controller.MemData 1551 0.00% 0.00%
2895system.ruby.Directory_Controller.CoreUnblock 1551 0.00% 0.00%
2896system.ruby.Directory_Controller.U.RdBlkS 1039 0.00% 0.00%
2897system.ruby.Directory_Controller.U.RdBlkM 335 0.00% 0.00%
2898system.ruby.Directory_Controller.U.RdBlk 177 0.00% 0.00%

2900system.ruby.Directory_Controller.BS_M.MemData 29 0.00% 0.00%
2901system.ruby.Directory_Controller.BM_M.MemData 12 0.00% 0.00%

2899system.ruby.Directory_Controller.BS_M.MemData 30 0.00% 0.00%
2900system.ruby.Directory_Controller.BM_M.MemData 11 0.00% 0.00%

2902system.ruby.Directory_Controller.B_M.MemData 1 0.00% 0.00%

2901system.ruby.Directory_Controller.B_M.MemData 1 0.00% 0.00%

2903system.ruby.Directory_Controller.BS_PM.CPUPrbResp 29 0.00% 0.00%
2904system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 29 0.00% 0.00%
2905system.ruby.Directory_Controller.BS_PM.MemData 1010 0.00% 0.00%
2906system.ruby.Directory_Controller.BM_PM.CPUPrbResp 12 0.00% 0.00%
2907system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 12 0.00% 0.00%
2908system.ruby.Directory_Controller.BM_PM.MemData 323 0.00% 0.00%

2902system.ruby.Directory_Controller.BS_PM.CPUPrbResp 30 0.00% 0.00%
2903system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 30 0.00% 0.00%
2904system.ruby.Directory_Controller.BS_PM.MemData 1009 0.00% 0.00%
2905system.ruby.Directory_Controller.BM_PM.CPUPrbResp 11 0.00% 0.00%
2906system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 11 0.00% 0.00%
2907system.ruby.Directory_Controller.BM_PM.MemData 324 0.00% 0.00%

2909system.ruby.Directory_Controller.B_PM.CPUPrbResp 1 0.00% 0.00%
2910system.ruby.Directory_Controller.B_PM.ProbeAcksComplete 1 0.00% 0.00%
2911system.ruby.Directory_Controller.B_PM.MemData 176 0.00% 0.00%

2908system.ruby.Directory_Controller.B_PM.CPUPrbResp 1 0.00% 0.00%
2909system.ruby.Directory_Controller.B_PM.ProbeAcksComplete 1 0.00% 0.00%
2910system.ruby.Directory_Controller.B_PM.MemData 176 0.00% 0.00%

2912system.ruby.Directory_Controller.BS_Pm.CPUPrbResp 1010 0.00% 0.00%
2913system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 1010 0.00% 0.00%
2914system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 323 0.00% 0.00%
2915system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 323 0.00% 0.00%

2911system.ruby.Directory_Controller.BS_Pm.CPUPrbResp 1009 0.00% 0.00%
2912system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 1009 0.00% 0.00%
2913system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 324 0.00% 0.00%
2914system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 324 0.00% 0.00%

2916system.ruby.Directory_Controller.B_Pm.CPUPrbResp 176 0.00% 0.00%
2917system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 176 0.00% 0.00%
2918system.ruby.Directory_Controller.B.CoreUnblock 1551 0.00% 0.00%
2919system.ruby.LD.latency_hist_seqr::bucket_size 32
2920system.ruby.LD.latency_hist_seqr::max_bucket 319
2921system.ruby.LD.latency_hist_seqr::samples 16335
2922system.ruby.LD.latency_hist_seqr::mean 4.217447
2923system.ruby.LD.latency_hist_seqr::gmean 2.103537
2924system.ruby.LD.latency_hist_seqr::stdev 21.286370
2925system.ruby.LD.latency_hist_seqr | 16160 98.93% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 166 1.02% 99.94% | 9 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
2926system.ruby.LD.latency_hist_seqr::total 16335
2927system.ruby.LD.latency_hist_coalsr::bucket_size 64
2928system.ruby.LD.latency_hist_coalsr::max_bucket 639

2915system.ruby.Directory_Controller.B_Pm.CPUPrbResp 176 0.00% 0.00%
2916system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 176 0.00% 0.00%
2917system.ruby.Directory_Controller.B.CoreUnblock 1551 0.00% 0.00%
2918system.ruby.LD.latency_hist_seqr::bucket_size 32
2919system.ruby.LD.latency_hist_seqr::max_bucket 319
2920system.ruby.LD.latency_hist_seqr::samples 16335
2921system.ruby.LD.latency_hist_seqr::mean 4.217447
2922system.ruby.LD.latency_hist_seqr::gmean 2.103537
2923system.ruby.LD.latency_hist_seqr::stdev 21.286370
2924system.ruby.LD.latency_hist_seqr | 16160 98.93% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 166 1.02% 99.94% | 9 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
2925system.ruby.LD.latency_hist_seqr::total 16335
2926system.ruby.LD.latency_hist_coalsr::bucket_size 64
2927system.ruby.LD.latency_hist_coalsr::max_bucket 639

2929system.ruby.LD.latency_hist_coalsr::samples 10
2930system.ruby.LD.latency_hist_coalsr::mean 119.100000
2931system.ruby.LD.latency_hist_coalsr::gmean 16.830524
2932system.ruby.LD.latency_hist_coalsr::stdev 153.079827
2933system.ruby.LD.latency_hist_coalsr | 6 60.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 2 20.00% 80.00% | 0 0.00% 80.00% | 2 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
2934system.ruby.LD.latency_hist_coalsr::total 10

2928system.ruby.LD.latency_hist_coalsr::samples 9
2929system.ruby.LD.latency_hist_coalsr::mean 133
2930system.ruby.LD.latency_hist_coalsr::gmean 19.809210
2931system.ruby.LD.latency_hist_coalsr::stdev 158.221364
2932system.ruby.LD.latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 2 22.22% 77.78% | 0 0.00% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
2933system.ruby.LD.latency_hist_coalsr::total 9

2935system.ruby.LD.hit_latency_hist_seqr::bucket_size 32
2936system.ruby.LD.hit_latency_hist_seqr::max_bucket 319
2937system.ruby.LD.hit_latency_hist_seqr::samples 175
2938system.ruby.LD.hit_latency_hist_seqr::mean 208.468571
2939system.ruby.LD.hit_latency_hist_seqr::gmean 208.231054
2940system.ruby.LD.hit_latency_hist_seqr::stdev 10.632194
2941system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 166 94.86% 94.86% | 9 5.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
2942system.ruby.LD.hit_latency_hist_seqr::total 175
2943system.ruby.LD.miss_latency_hist_seqr::bucket_size 4
2944system.ruby.LD.miss_latency_hist_seqr::max_bucket 39
2945system.ruby.LD.miss_latency_hist_seqr::samples 16160
2946system.ruby.LD.miss_latency_hist_seqr::mean 2.005569
2947system.ruby.LD.miss_latency_hist_seqr::gmean 2.001425
2948system.ruby.LD.miss_latency_hist_seqr::stdev 0.316580
2949system.ruby.LD.miss_latency_hist_seqr | 16155 99.97% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 5 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
2950system.ruby.LD.miss_latency_hist_seqr::total 16160
2951system.ruby.LD.miss_latency_hist_coalsr::bucket_size 64
2952system.ruby.LD.miss_latency_hist_coalsr::max_bucket 639

2934system.ruby.LD.hit_latency_hist_seqr::bucket_size 32
2935system.ruby.LD.hit_latency_hist_seqr::max_bucket 319
2936system.ruby.LD.hit_latency_hist_seqr::samples 175
2937system.ruby.LD.hit_latency_hist_seqr::mean 208.468571
2938system.ruby.LD.hit_latency_hist_seqr::gmean 208.231054
2939system.ruby.LD.hit_latency_hist_seqr::stdev 10.632194
2940system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 166 94.86% 94.86% | 9 5.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
2941system.ruby.LD.hit_latency_hist_seqr::total 175
2942system.ruby.LD.miss_latency_hist_seqr::bucket_size 4
2943system.ruby.LD.miss_latency_hist_seqr::max_bucket 39
2944system.ruby.LD.miss_latency_hist_seqr::samples 16160
2945system.ruby.LD.miss_latency_hist_seqr::mean 2.005569
2946system.ruby.LD.miss_latency_hist_seqr::gmean 2.001425
2947system.ruby.LD.miss_latency_hist_seqr::stdev 0.316580
2948system.ruby.LD.miss_latency_hist_seqr | 16155 99.97% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 5 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
2949system.ruby.LD.miss_latency_hist_seqr::total 16160
2950system.ruby.LD.miss_latency_hist_coalsr::bucket_size 64
2951system.ruby.LD.miss_latency_hist_coalsr::max_bucket 639

2953system.ruby.LD.miss_latency_hist_coalsr::samples 10
2954system.ruby.LD.miss_latency_hist_coalsr::mean 119.100000
2955system.ruby.LD.miss_latency_hist_coalsr::gmean 16.830524
2956system.ruby.LD.miss_latency_hist_coalsr::stdev 153.079827
2957system.ruby.LD.miss_latency_hist_coalsr | 6 60.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 2 20.00% 80.00% | 0 0.00% 80.00% | 2 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
2958system.ruby.LD.miss_latency_hist_coalsr::total 10

2952system.ruby.LD.miss_latency_hist_coalsr::samples 9
2953system.ruby.LD.miss_latency_hist_coalsr::mean 133
2954system.ruby.LD.miss_latency_hist_coalsr::gmean 19.809210
2955system.ruby.LD.miss_latency_hist_coalsr::stdev 158.221364
2956system.ruby.LD.miss_latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 2 22.22% 77.78% | 0 0.00% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
2957system.ruby.LD.miss_latency_hist_coalsr::total 9

2959system.ruby.ST.latency_hist_seqr::bucket_size 64
2960system.ruby.ST.latency_hist_seqr::max_bucket 639
2961system.ruby.ST.latency_hist_seqr::samples 10412
2962system.ruby.ST.latency_hist_seqr::mean 8.385709
2963system.ruby.ST.latency_hist_seqr::gmean 2.308923
2964system.ruby.ST.latency_hist_seqr::stdev 35.862445
2965system.ruby.ST.latency_hist_seqr | 10090 96.91% 96.91% | 0 0.00% 96.91% | 0 0.00% 96.91% | 316 3.03% 99.94% | 3 0.03% 99.97% | 3 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
2966system.ruby.ST.latency_hist_seqr::total 10412
2967system.ruby.ST.latency_hist_coalsr::bucket_size 32
2968system.ruby.ST.latency_hist_coalsr::max_bucket 319
2969system.ruby.ST.latency_hist_coalsr::samples 16

2958system.ruby.ST.latency_hist_seqr::bucket_size 64
2959system.ruby.ST.latency_hist_seqr::max_bucket 639
2960system.ruby.ST.latency_hist_seqr::samples 10412
2961system.ruby.ST.latency_hist_seqr::mean 8.385709
2962system.ruby.ST.latency_hist_seqr::gmean 2.308923
2963system.ruby.ST.latency_hist_seqr::stdev 35.862445
2964system.ruby.ST.latency_hist_seqr | 10090 96.91% 96.91% | 0 0.00% 96.91% | 0 0.00% 96.91% | 316 3.03% 99.94% | 3 0.03% 99.97% | 3 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
2965system.ruby.ST.latency_hist_seqr::total 10412
2966system.ruby.ST.latency_hist_coalsr::bucket_size 32
2967system.ruby.ST.latency_hist_coalsr::max_bucket 319
2968system.ruby.ST.latency_hist_coalsr::samples 16

2970system.ruby.ST.latency_hist_coalsr::mean 125.375000
2971system.ruby.ST.latency_hist_coalsr::gmean 15.803091
2972system.ruby.ST.latency_hist_coalsr::stdev 128.466792

2969system.ruby.ST.latency_hist_coalsr::mean 124.937500
2970system.ruby.ST.latency_hist_coalsr::gmean 15.775436
2971system.ruby.ST.latency_hist_coalsr::stdev 128.013264

2973system.ruby.ST.latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 8 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
2974system.ruby.ST.latency_hist_coalsr::total 16
2975system.ruby.ST.hit_latency_hist_seqr::bucket_size 64
2976system.ruby.ST.hit_latency_hist_seqr::max_bucket 639
2977system.ruby.ST.hit_latency_hist_seqr::samples 322
2978system.ruby.ST.hit_latency_hist_seqr::mean 208.484472
2979system.ruby.ST.hit_latency_hist_seqr::gmean 208.014366
2980system.ruby.ST.hit_latency_hist_seqr::stdev 16.327683

--- 4 unchanged lines hidden (view full) ---

2985system.ruby.ST.miss_latency_hist_seqr::samples 10090
2986system.ruby.ST.miss_latency_hist_seqr::mean 2
2987system.ruby.ST.miss_latency_hist_seqr::gmean 2.000000
2988system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10090 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
2989system.ruby.ST.miss_latency_hist_seqr::total 10090
2990system.ruby.ST.miss_latency_hist_coalsr::bucket_size 32
2991system.ruby.ST.miss_latency_hist_coalsr::max_bucket 319
2992system.ruby.ST.miss_latency_hist_coalsr::samples 16

2972system.ruby.ST.latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 8 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
2973system.ruby.ST.latency_hist_coalsr::total 16
2974system.ruby.ST.hit_latency_hist_seqr::bucket_size 64
2975system.ruby.ST.hit_latency_hist_seqr::max_bucket 639
2976system.ruby.ST.hit_latency_hist_seqr::samples 322
2977system.ruby.ST.hit_latency_hist_seqr::mean 208.484472
2978system.ruby.ST.hit_latency_hist_seqr::gmean 208.014366
2979system.ruby.ST.hit_latency_hist_seqr::stdev 16.327683

--- 4 unchanged lines hidden (view full) ---

2984system.ruby.ST.miss_latency_hist_seqr::samples 10090
2985system.ruby.ST.miss_latency_hist_seqr::mean 2
2986system.ruby.ST.miss_latency_hist_seqr::gmean 2.000000
2987system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10090 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
2988system.ruby.ST.miss_latency_hist_seqr::total 10090
2989system.ruby.ST.miss_latency_hist_coalsr::bucket_size 32
2990system.ruby.ST.miss_latency_hist_coalsr::max_bucket 319
2991system.ruby.ST.miss_latency_hist_coalsr::samples 16

2993system.ruby.ST.miss_latency_hist_coalsr::mean 125.375000
2994system.ruby.ST.miss_latency_hist_coalsr::gmean 15.803091
2995system.ruby.ST.miss_latency_hist_coalsr::stdev 128.466792

2992system.ruby.ST.miss_latency_hist_coalsr::mean 124.937500
2993system.ruby.ST.miss_latency_hist_coalsr::gmean 15.775436
2994system.ruby.ST.miss_latency_hist_coalsr::stdev 128.013264

2996system.ruby.ST.miss_latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 8 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
2997system.ruby.ST.miss_latency_hist_coalsr::total 16
2998system.ruby.ATOMIC.latency_hist_coalsr::bucket_size 64
2999system.ruby.ATOMIC.latency_hist_coalsr::max_bucket 639
3000system.ruby.ATOMIC.latency_hist_coalsr::samples 2
3001system.ruby.ATOMIC.latency_hist_coalsr::mean 309.500000
3002system.ruby.ATOMIC.latency_hist_coalsr::gmean 306.568100
3003system.ruby.ATOMIC.latency_hist_coalsr::stdev 60.104076

--- 5 unchanged lines hidden (view full) ---

3009system.ruby.ATOMIC.miss_latency_hist_coalsr::mean 309.500000
3010system.ruby.ATOMIC.miss_latency_hist_coalsr::gmean 306.568100
3011system.ruby.ATOMIC.miss_latency_hist_coalsr::stdev 60.104076
3012system.ruby.ATOMIC.miss_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3013system.ruby.ATOMIC.miss_latency_hist_coalsr::total 2
3014system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
3015system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
3016system.ruby.IFETCH.latency_hist_seqr::samples 87095

2995system.ruby.ST.miss_latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 8 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
2996system.ruby.ST.miss_latency_hist_coalsr::total 16
2997system.ruby.ATOMIC.latency_hist_coalsr::bucket_size 64
2998system.ruby.ATOMIC.latency_hist_coalsr::max_bucket 639
2999system.ruby.ATOMIC.latency_hist_coalsr::samples 2
3000system.ruby.ATOMIC.latency_hist_coalsr::mean 309.500000
3001system.ruby.ATOMIC.latency_hist_coalsr::gmean 306.568100
3002system.ruby.ATOMIC.latency_hist_coalsr::stdev 60.104076

--- 5 unchanged lines hidden (view full) ---

3008system.ruby.ATOMIC.miss_latency_hist_coalsr::mean 309.500000
3009system.ruby.ATOMIC.miss_latency_hist_coalsr::gmean 306.568100
3010system.ruby.ATOMIC.miss_latency_hist_coalsr::stdev 60.104076
3011system.ruby.ATOMIC.miss_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3012system.ruby.ATOMIC.miss_latency_hist_coalsr::total 2
3013system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
3014system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
3015system.ruby.IFETCH.latency_hist_seqr::samples 87095

3017system.ruby.IFETCH.latency_hist_seqr::mean 4.462093

3016system.ruby.IFETCH.latency_hist_seqr::mean 4.462070

3018system.ruby.IFETCH.latency_hist_seqr::gmean 2.116390

3017system.ruby.IFETCH.latency_hist_seqr::gmean 2.116390

3019system.ruby.IFETCH.latency_hist_seqr::stdev 22.435279

3018system.ruby.IFETCH.latency_hist_seqr::stdev 22.434900

3020system.ruby.IFETCH.latency_hist_seqr | 86061 98.81% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1011 1.16% 99.97% | 16 0.02% 99.99% | 7 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3021system.ruby.IFETCH.latency_hist_seqr::total 87095
3022system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 64
3023system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 639
3024system.ruby.IFETCH.hit_latency_hist_seqr::samples 1034

3019system.ruby.IFETCH.latency_hist_seqr | 86061 98.81% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1011 1.16% 99.97% | 16 0.02% 99.99% | 7 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3020system.ruby.IFETCH.latency_hist_seqr::total 87095
3021system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 64
3022system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 639
3023system.ruby.IFETCH.hit_latency_hist_seqr::samples 1034

3025system.ruby.IFETCH.hit_latency_hist_seqr::mean 208.444874
3026system.ruby.IFETCH.hit_latency_hist_seqr::gmean 207.968565
3027system.ruby.IFETCH.hit_latency_hist_seqr::stdev 16.462617

3024system.ruby.IFETCH.hit_latency_hist_seqr::mean 208.442940
3025system.ruby.IFETCH.hit_latency_hist_seqr::gmean 207.967489
3026system.ruby.IFETCH.hit_latency_hist_seqr::stdev 16.443135

3028system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1011 97.78% 97.78% | 16 1.55% 99.32% | 7 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3029system.ruby.IFETCH.hit_latency_hist_seqr::total 1034
3030system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 4
3031system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 39
3032system.ruby.IFETCH.miss_latency_hist_seqr::samples 86061
3033system.ruby.IFETCH.miss_latency_hist_seqr::mean 2.011294
3034system.ruby.IFETCH.miss_latency_hist_seqr::gmean 2.002892
3035system.ruby.IFETCH.miss_latency_hist_seqr::stdev 0.450747

--- 61 unchanged lines hidden (view full) ---

3097system.ruby.L2Cache.miss_mach_latency_hist_seqr::samples 59
3098system.ruby.L2Cache.miss_mach_latency_hist_seqr::mean 20
3099system.ruby.L2Cache.miss_mach_latency_hist_seqr::gmean 20.000000
3100system.ruby.L2Cache.miss_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 59 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3101system.ruby.L2Cache.miss_mach_latency_hist_seqr::total 59
3102system.ruby.Directory.hit_mach_latency_hist_seqr::bucket_size 64
3103system.ruby.Directory.hit_mach_latency_hist_seqr::max_bucket 639
3104system.ruby.Directory.hit_mach_latency_hist_seqr::samples 1535

3027system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1011 97.78% 97.78% | 16 1.55% 99.32% | 7 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3028system.ruby.IFETCH.hit_latency_hist_seqr::total 1034
3029system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 4
3030system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 39
3031system.ruby.IFETCH.miss_latency_hist_seqr::samples 86061
3032system.ruby.IFETCH.miss_latency_hist_seqr::mean 2.011294
3033system.ruby.IFETCH.miss_latency_hist_seqr::gmean 2.002892
3034system.ruby.IFETCH.miss_latency_hist_seqr::stdev 0.450747

--- 61 unchanged lines hidden (view full) ---

3096system.ruby.L2Cache.miss_mach_latency_hist_seqr::samples 59
3097system.ruby.L2Cache.miss_mach_latency_hist_seqr::mean 20
3098system.ruby.L2Cache.miss_mach_latency_hist_seqr::gmean 20.000000
3099system.ruby.L2Cache.miss_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 59 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3100system.ruby.L2Cache.miss_mach_latency_hist_seqr::total 59
3101system.ruby.Directory.hit_mach_latency_hist_seqr::bucket_size 64
3102system.ruby.Directory.hit_mach_latency_hist_seqr::max_bucket 639
3103system.ruby.Directory.hit_mach_latency_hist_seqr::samples 1535

3105system.ruby.Directory.hit_mach_latency_hist_seqr::mean 208.449511
3106system.ruby.Directory.hit_mach_latency_hist_seqr::gmean 208.002927
3107system.ruby.Directory.hit_mach_latency_hist_seqr::stdev 15.847049

3104system.ruby.Directory.hit_mach_latency_hist_seqr::mean 208.448208
3105system.ruby.Directory.hit_mach_latency_hist_seqr::gmean 208.002202
3106system.ruby.Directory.hit_mach_latency_hist_seqr::stdev 15.833423

3108system.ruby.Directory.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1506 98.11% 98.11% | 19 1.24% 99.35% | 10 0.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3109system.ruby.Directory.hit_mach_latency_hist_seqr::total 1535
3110system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::bucket_size 64
3111system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::max_bucket 639
3112system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::samples 3

3107system.ruby.Directory.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1506 98.11% 98.11% | 19 1.24% 99.35% | 10 0.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3108system.ruby.Directory.hit_mach_latency_hist_seqr::total 1535
3109system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::bucket_size 64
3110system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::max_bucket 639
3111system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::samples 3

3113system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean 342
3114system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 341.902506
3115system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 10

3112system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean 345.333333
3113system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 345.301362
3114system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 5.773503

3116system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3117system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::total 3
3118system.ruby.TCP.miss_mach_latency_hist_coalsr::bucket_size 1
3119system.ruby.TCP.miss_mach_latency_hist_coalsr::max_bucket 9

3115system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3116system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::total 3
3117system.ruby.TCP.miss_mach_latency_hist_coalsr::bucket_size 1
3118system.ruby.TCP.miss_mach_latency_hist_coalsr::max_bucket 9

3120system.ruby.TCP.miss_mach_latency_hist_coalsr::samples 14
3121system.ruby.TCP.miss_mach_latency_hist_coalsr::mean 1.714286
3122system.ruby.TCP.miss_mach_latency_hist_coalsr::gmean 1.485994
3123system.ruby.TCP.miss_mach_latency_hist_coalsr::stdev 1.069045
3124system.ruby.TCP.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 8 57.14% 57.14% | 4 28.57% 85.71% | 0 0.00% 85.71% | 2 14.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3125system.ruby.TCP.miss_mach_latency_hist_coalsr::total 14

3119system.ruby.TCP.miss_mach_latency_hist_coalsr::samples 13
3120system.ruby.TCP.miss_mach_latency_hist_coalsr::mean 1.538462
3121system.ruby.TCP.miss_mach_latency_hist_coalsr::gmean 1.377009
3122system.ruby.TCP.miss_mach_latency_hist_coalsr::stdev 0.877058
3123system.ruby.TCP.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 8 61.54% 61.54% | 4 30.77% 92.31% | 0 0.00% 92.31% | 1 7.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3124system.ruby.TCP.miss_mach_latency_hist_coalsr::total 13

3126system.ruby.TCCdir.miss_mach_latency_hist_coalsr::bucket_size 32
3127system.ruby.TCCdir.miss_mach_latency_hist_coalsr::max_bucket 319
3128system.ruby.TCCdir.miss_mach_latency_hist_coalsr::samples 11

3125system.ruby.TCCdir.miss_mach_latency_hist_coalsr::bucket_size 32
3126system.ruby.TCCdir.miss_mach_latency_hist_coalsr::max_bucket 319
3127system.ruby.TCCdir.miss_mach_latency_hist_coalsr::samples 11

3129system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 251.454545
3130system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 251.396753
3131system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 5.733474

3128system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 250.818182
3129system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 250.757089
3130system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 5.896070

3132system.ruby.TCCdir.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 90.91% 90.91% | 1 9.09% 100.00% | 0 0.00% 100.00%
3133system.ruby.TCCdir.miss_mach_latency_hist_coalsr::total 11
3134system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1
3135system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9
3136system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::samples 16155
3137system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::mean 2
3138system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000
3139system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 16155 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%

--- 11 unchanged lines hidden (view full) ---

3151system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::mean 208.468571
3152system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::gmean 208.231054
3153system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::stdev 10.632194
3154system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 166 94.86% 94.86% | 9 5.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3155system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::total 175
3156system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64
3157system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639
3158system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 2

3131system.ruby.TCCdir.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 90.91% 90.91% | 1 9.09% 100.00% | 0 0.00% 100.00%
3132system.ruby.TCCdir.miss_mach_latency_hist_coalsr::total 11
3133system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1
3134system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9
3135system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::samples 16155
3136system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::mean 2
3137system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000
3138system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 16155 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%

--- 11 unchanged lines hidden (view full) ---

3150system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::mean 208.468571
3151system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::gmean 208.231054
3152system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::stdev 10.632194
3153system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 166 94.86% 94.86% | 9 5.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3154system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::total 175
3155system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64
3156system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639
3157system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 2

3159system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 337
3160system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 336.962906
3161system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev 7.071068

3158system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 342
3159system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 342.000000

3162system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3163system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 2
3164system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1
3165system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9

3160system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3161system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 2
3162system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1
3163system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9

3166system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::samples 6
3167system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::mean 2.666667
3168system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::gmean 2.519842
3169system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::stdev 1.032796
3170system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 66.67% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3171system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::total 6

3164system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::samples 5
3165system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::mean 2.400000
3166system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::gmean 2.297397
3167system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::stdev 0.894427
3168system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 80.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3169system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::total 5

3172system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32
3173system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319
3174system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::samples 2
3175system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean 250.500000
3176system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 250.487525
3177system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 3.535534
3178system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3179system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::total 2

--- 17 unchanged lines hidden (view full) ---

3197system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::samples 8
3198system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::mean 1
3199system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::gmean 1
3200system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 8 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3201system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::total 8
3202system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32
3203system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319
3204system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::samples 8

3170system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32
3171system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319
3172system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::samples 2
3173system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean 250.500000
3174system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 250.487525
3175system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 3.535534
3176system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3177system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::total 2

--- 17 unchanged lines hidden (view full) ---

3195system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::samples 8
3196system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::mean 1
3197system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::gmean 1
3198system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 8 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3199system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::total 8
3200system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32
3201system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319
3202system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::samples 8

3205system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 249.750000
3206system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 249.737699
3207system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 2.659216

3203system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 248.875000
3204system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 248.864382
3205system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 2.474874

3208system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 8 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3209system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::total 8
3210system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64
3211system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639
3212system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 1
3213system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 352
3214system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 352.000000
3215system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev nan

--- 19 unchanged lines hidden (view full) ---

3235system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::samples 54
3236system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::mean 20
3237system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::gmean 20.000000
3238system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 54 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3239system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::total 54
3240system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::bucket_size 64
3241system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::max_bucket 639
3242system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::samples 1034

3206system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 8 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3207system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::total 8
3208system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64
3209system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639
3210system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 1
3211system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 352
3212system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 352.000000
3213system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev nan

--- 19 unchanged lines hidden (view full) ---

3233system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::samples 54
3234system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::mean 20
3235system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::gmean 20.000000
3236system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 54 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3237system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::total 54
3238system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::bucket_size 64
3239system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::max_bucket 639
3240system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::samples 1034

3243system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::mean 208.444874
3244system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::gmean 207.968565
3245system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::stdev 16.462617

3241system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::mean 208.442940
3242system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::gmean 207.967489
3243system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::stdev 16.443135

3246system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1011 97.78% 97.78% | 16 1.55% 99.32% | 7 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3247system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::total 1034
3248system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1
3249system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9
3250system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::samples 337
3251system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::mean 2
3252system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000
3253system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%

--- 19 unchanged lines hidden (view full) ---

3273system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2
3274system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3275system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::total 10
3276system.ruby.SQC_Controller.Fetch 86 0.00% 0.00%
3277system.ruby.SQC_Controller.TCC_AckS 5 0.00% 0.00%
3278system.ruby.SQC_Controller.I.Fetch 5 0.00% 0.00%
3279system.ruby.SQC_Controller.S.Fetch 81 0.00% 0.00%
3280system.ruby.SQC_Controller.I_S.TCC_AckS 5 0.00% 0.00%

3244system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1011 97.78% 97.78% | 16 1.55% 99.32% | 7 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3245system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::total 1034
3246system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1
3247system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9
3248system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::samples 337
3249system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::mean 2
3250system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000
3251system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%

--- 19 unchanged lines hidden (view full) ---

3271system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2
3272system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3273system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::total 10
3274system.ruby.SQC_Controller.Fetch 86 0.00% 0.00%
3275system.ruby.SQC_Controller.TCC_AckS 5 0.00% 0.00%
3276system.ruby.SQC_Controller.I.Fetch 5 0.00% 0.00%
3277system.ruby.SQC_Controller.S.Fetch 81 0.00% 0.00%
3278system.ruby.SQC_Controller.I_S.TCC_AckS 5 0.00% 0.00%

3281system.ruby.TCCdir_Controller.RdBlk 53 0.00% 0.00%

3279system.ruby.TCCdir_Controller.RdBlk 54 0.00% 0.00%

3282system.ruby.TCCdir_Controller.RdBlkM 36 0.00% 0.00%
3283system.ruby.TCCdir_Controller.RdBlkS 5 0.00% 0.00%
3284system.ruby.TCCdir_Controller.CPUPrbResp 14 0.00% 0.00%
3285system.ruby.TCCdir_Controller.ProbeAcksComplete 13 0.00% 0.00%
3286system.ruby.TCCdir_Controller.CoreUnblock 17 0.00% 0.00%
3287system.ruby.TCCdir_Controller.LastCoreUnblock 2 0.00% 0.00%
3288system.ruby.TCCdir_Controller.NB_AckS 7 0.00% 0.00%
3289system.ruby.TCCdir_Controller.NB_AckM 9 0.00% 0.00%

--- 18 unchanged lines hidden (view full) ---

3308system.ruby.TCCdir_Controller.I_ES.NB_AckS 2 0.00% 0.00%
3309system.ruby.TCCdir_Controller.I_S.NB_AckS 5 0.00% 0.00%
3310system.ruby.TCCdir_Controller.BBS_S.CPUPrbResp 2 0.00% 0.00%
3311system.ruby.TCCdir_Controller.BBS_S.ProbeAcksComplete 2 0.00% 0.00%
3312system.ruby.TCCdir_Controller.BBM_M.CPUPrbResp 1 0.00% 0.00%
3313system.ruby.TCCdir_Controller.BBM_M.ProbeAcksComplete 1 0.00% 0.00%
3314system.ruby.TCCdir_Controller.BB_M.CoreUnblock 1 0.00% 0.00%
3315system.ruby.TCCdir_Controller.BB_S.LastCoreUnblock 2 0.00% 0.00%

3280system.ruby.TCCdir_Controller.RdBlkM 36 0.00% 0.00%
3281system.ruby.TCCdir_Controller.RdBlkS 5 0.00% 0.00%
3282system.ruby.TCCdir_Controller.CPUPrbResp 14 0.00% 0.00%
3283system.ruby.TCCdir_Controller.ProbeAcksComplete 13 0.00% 0.00%
3284system.ruby.TCCdir_Controller.CoreUnblock 17 0.00% 0.00%
3285system.ruby.TCCdir_Controller.LastCoreUnblock 2 0.00% 0.00%
3286system.ruby.TCCdir_Controller.NB_AckS 7 0.00% 0.00%
3287system.ruby.TCCdir_Controller.NB_AckM 9 0.00% 0.00%

--- 18 unchanged lines hidden (view full) ---

3306system.ruby.TCCdir_Controller.I_ES.NB_AckS 2 0.00% 0.00%
3307system.ruby.TCCdir_Controller.I_S.NB_AckS 5 0.00% 0.00%
3308system.ruby.TCCdir_Controller.BBS_S.CPUPrbResp 2 0.00% 0.00%
3309system.ruby.TCCdir_Controller.BBS_S.ProbeAcksComplete 2 0.00% 0.00%
3310system.ruby.TCCdir_Controller.BBM_M.CPUPrbResp 1 0.00% 0.00%
3311system.ruby.TCCdir_Controller.BBM_M.ProbeAcksComplete 1 0.00% 0.00%
3312system.ruby.TCCdir_Controller.BB_M.CoreUnblock 1 0.00% 0.00%
3313system.ruby.TCCdir_Controller.BB_S.LastCoreUnblock 2 0.00% 0.00%

3316system.ruby.TCCdir_Controller.BBB_S.RdBlk 8 0.00% 0.00%

3314system.ruby.TCCdir_Controller.BBB_S.RdBlk 9 0.00% 0.00%

3317system.ruby.TCCdir_Controller.BBB_S.CoreUnblock 7 0.00% 0.00%
3318system.ruby.TCCdir_Controller.BBB_M.RdBlkM 4 0.00% 0.00%
3319system.ruby.TCCdir_Controller.BBB_M.CoreUnblock 9 0.00% 0.00%

3315system.ruby.TCCdir_Controller.BBB_S.CoreUnblock 7 0.00% 0.00%
3316system.ruby.TCCdir_Controller.BBB_M.RdBlkM 4 0.00% 0.00%
3317system.ruby.TCCdir_Controller.BBB_M.CoreUnblock 9 0.00% 0.00%

3320system.ruby.TCP_Controller.Load | 5 50.00% 50.00% | 5 50.00% 100.00%
3321system.ruby.TCP_Controller.Load::total 10

3318system.ruby.TCP_Controller.Load | 4 44.44% 44.44% | 5 55.56% 100.00%
3319system.ruby.TCP_Controller.Load::total 9

3322system.ruby.TCP_Controller.Store | 9 50.00% 50.00% | 9 50.00% 100.00%
3323system.ruby.TCP_Controller.Store::total 18
3324system.ruby.TCP_Controller.TCC_AckS | 2 50.00% 50.00% | 2 50.00% 100.00%
3325system.ruby.TCP_Controller.TCC_AckS::total 4
3326system.ruby.TCP_Controller.TCC_AckM | 5 50.00% 50.00% | 5 50.00% 100.00%
3327system.ruby.TCP_Controller.TCC_AckM::total 10
3328system.ruby.TCP_Controller.PrbInvData | 1 33.33% 33.33% | 2 66.67% 100.00%
3329system.ruby.TCP_Controller.PrbInvData::total 3
3330system.ruby.TCP_Controller.PrbShrData | 7 63.64% 63.64% | 4 36.36% 100.00%
3331system.ruby.TCP_Controller.PrbShrData::total 11
3332system.ruby.TCP_Controller.I.Load | 2 50.00% 50.00% | 2 50.00% 100.00%
3333system.ruby.TCP_Controller.I.Load::total 4
3334system.ruby.TCP_Controller.I.Store | 5 50.00% 50.00% | 5 50.00% 100.00%
3335system.ruby.TCP_Controller.I.Store::total 10

3320system.ruby.TCP_Controller.Store | 9 50.00% 50.00% | 9 50.00% 100.00%
3321system.ruby.TCP_Controller.Store::total 18
3322system.ruby.TCP_Controller.TCC_AckS | 2 50.00% 50.00% | 2 50.00% 100.00%
3323system.ruby.TCP_Controller.TCC_AckS::total 4
3324system.ruby.TCP_Controller.TCC_AckM | 5 50.00% 50.00% | 5 50.00% 100.00%
3325system.ruby.TCP_Controller.TCC_AckM::total 10
3326system.ruby.TCP_Controller.PrbInvData | 1 33.33% 33.33% | 2 66.67% 100.00%
3327system.ruby.TCP_Controller.PrbInvData::total 3
3328system.ruby.TCP_Controller.PrbShrData | 7 63.64% 63.64% | 4 36.36% 100.00%
3329system.ruby.TCP_Controller.PrbShrData::total 11
3330system.ruby.TCP_Controller.I.Load | 2 50.00% 50.00% | 2 50.00% 100.00%
3331system.ruby.TCP_Controller.I.Load::total 4
3332system.ruby.TCP_Controller.I.Store | 5 50.00% 50.00% | 5 50.00% 100.00%
3333system.ruby.TCP_Controller.I.Store::total 10

3336system.ruby.TCP_Controller.S.Load | 3 50.00% 50.00% | 3 50.00% 100.00%
3337system.ruby.TCP_Controller.S.Load::total 6

3334system.ruby.TCP_Controller.S.Load | 2 40.00% 40.00% | 3 60.00% 100.00%
3335system.ruby.TCP_Controller.S.Load::total 5