3,5c3,5
< sim_seconds 0.000668 # Number of seconds simulated
< sim_ticks 668137500 # Number of ticks simulated
< final_tick 668137500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000667 # Number of seconds simulated
> sim_ticks 667407500 # Number of ticks simulated
> final_tick 667407500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 245703 # Simulator instruction rate (inst/s)
< host_op_rate 505252 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2451366703 # Simulator tick rate (ticks/s)
< host_mem_usage 1323744 # Number of bytes of host memory used
< host_seconds 0.27 # Real time elapsed on the host
---
> host_inst_rate 72185 # Simulator instruction rate (inst/s)
> host_op_rate 148440 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 719412350 # Simulator tick rate (ticks/s)
> host_mem_usage 1308600 # Number of bytes of host memory used
> host_seconds 0.93 # Real time elapsed on the host
16,25c16,25
< system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
< system.mem_ctrls.bytes_read::dir_cntrl0 99264 # Number of bytes read from this memory
< system.mem_ctrls.bytes_read::total 99264 # Number of bytes read from this memory
< system.mem_ctrls.num_reads::dir_cntrl0 1551 # Number of read requests responded to by this memory
< system.mem_ctrls.num_reads::total 1551 # Number of read requests responded to by this memory
< system.mem_ctrls.bw_read::dir_cntrl0 148568221 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrls.bw_read::total 148568221 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrls.bw_total::dir_cntrl0 148568221 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrls.bw_total::total 148568221 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrls.readReqs 1551 # Number of read requests accepted
---
> system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
> system.mem_ctrls.bytes_read::dir_cntrl0 99136 # Number of bytes read from this memory
> system.mem_ctrls.bytes_read::total 99136 # Number of bytes read from this memory
> system.mem_ctrls.num_reads::dir_cntrl0 1549 # Number of read requests responded to by this memory
> system.mem_ctrls.num_reads::total 1549 # Number of read requests responded to by this memory
> system.mem_ctrls.bw_read::dir_cntrl0 148538936 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrls.bw_read::total 148538936 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrls.bw_total::dir_cntrl0 148538936 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrls.bw_total::total 148538936 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrls.readReqs 1549 # Number of read requests accepted
27c27
< system.mem_ctrls.readBursts 1551 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.mem_ctrls.readBursts 1549 # Number of DRAM read bursts, including those serviced by the write queue
29c29
< system.mem_ctrls.bytesReadDRAM 99264 # Total number of bytes read from DRAM
---
> system.mem_ctrls.bytesReadDRAM 99136 # Total number of bytes read from DRAM
32c32
< system.mem_ctrls.bytesReadSys 99264 # Total read bytes from the system interface side
---
> system.mem_ctrls.bytesReadSys 99136 # Total read bytes from the system interface side
39c39
< system.mem_ctrls.perBankRdBursts::2 93 # Per bank write bursts
---
> system.mem_ctrls.perBankRdBursts::2 91 # Per bank write bursts
71c71
< system.mem_ctrls.totGap 667904000 # Total gap between requests
---
> system.mem_ctrls.totGap 667174000 # Total gap between requests
78c78
< system.mem_ctrls.readPktSize::6 1551 # Read request sizes (log2)
---
> system.mem_ctrls.readPktSize::6 1549 # Read request sizes (log2)
86c86
< system.mem_ctrls.rdQLenPdf::0 1542 # What read queue length does an incoming req see
---
> system.mem_ctrls.rdQLenPdf::0 1540 # What read queue length does an incoming req see
90c90
< system.mem_ctrls.rdQLenPdf::4 1 # What read queue length does an incoming req see
---
> system.mem_ctrls.rdQLenPdf::4 2 # What read queue length does an incoming req see
92c92
< system.mem_ctrls.rdQLenPdf::6 2 # What read queue length does an incoming req see
---
> system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see
183,185c183,185
< system.mem_ctrls.bytesPerActivate::mean 203.636364 # Bytes accessed per row activation
< system.mem_ctrls.bytesPerActivate::gmean 145.087483 # Bytes accessed per row activation
< system.mem_ctrls.bytesPerActivate::stdev 194.740960 # Bytes accessed per row activation
---
> system.mem_ctrls.bytesPerActivate::mean 203.371901 # Bytes accessed per row activation
> system.mem_ctrls.bytesPerActivate::gmean 144.930715 # Bytes accessed per row activation
> system.mem_ctrls.bytesPerActivate::stdev 194.713066 # Bytes accessed per row activation
187,188c187,188
< system.mem_ctrls.bytesPerActivate::128-255 167 34.50% 71.07% # Bytes accessed per row activation
< system.mem_ctrls.bytesPerActivate::256-383 64 13.22% 84.30% # Bytes accessed per row activation
---
> system.mem_ctrls.bytesPerActivate::128-255 168 34.71% 71.28% # Bytes accessed per row activation
> system.mem_ctrls.bytesPerActivate::256-383 63 13.02% 84.30% # Bytes accessed per row activation
190,191c190,191
< system.mem_ctrls.bytesPerActivate::512-639 20 4.13% 94.42% # Bytes accessed per row activation
< system.mem_ctrls.bytesPerActivate::640-767 10 2.07% 96.49% # Bytes accessed per row activation
---
> system.mem_ctrls.bytesPerActivate::512-639 19 3.93% 94.21% # Bytes accessed per row activation
> system.mem_ctrls.bytesPerActivate::640-767 11 2.27% 96.49% # Bytes accessed per row activation
196,199c196,199
< system.mem_ctrls.totQLat 31097995 # Total ticks spent queuing
< system.mem_ctrls.totMemAccLat 60179245 # Total ticks spent from burst creation until serviced by the DRAM
< system.mem_ctrls.totBusLat 7755000 # Total ticks spent in databus transfers
< system.mem_ctrls.avgQLat 20050.29 # Average queueing delay per DRAM burst
---
> system.mem_ctrls.totQLat 31625750 # Total ticks spent queuing
> system.mem_ctrls.totMemAccLat 60669500 # Total ticks spent from burst creation until serviced by the DRAM
> system.mem_ctrls.totBusLat 7745000 # Total ticks spent in databus transfers
> system.mem_ctrls.avgQLat 20416.88 # Average queueing delay per DRAM burst
201,202c201,202
< system.mem_ctrls.avgMemAccLat 38800.29 # Average memory access latency per DRAM burst
< system.mem_ctrls.avgRdBW 148.57 # Average DRAM read bandwidth in MiByte/s
---
> system.mem_ctrls.avgMemAccLat 39166.88 # Average memory access latency per DRAM burst
> system.mem_ctrls.avgRdBW 148.54 # Average DRAM read bandwidth in MiByte/s
204c204
< system.mem_ctrls.avgRdBWSys 148.57 # Average system read bandwidth in MiByte/s
---
> system.mem_ctrls.avgRdBWSys 148.54 # Average system read bandwidth in MiByte/s
212c212
< system.mem_ctrls.readRowHits 1062 # Number of row buffer hits during reads
---
> system.mem_ctrls.readRowHits 1060 # Number of row buffer hits during reads
214c214
< system.mem_ctrls.readRowHitRate 68.47 # Row buffer hit rate for reads
---
> system.mem_ctrls.readRowHitRate 68.43 # Row buffer hit rate for reads
216,217c216,217
< system.mem_ctrls.avgGap 430627.98 # Average gap between requests
< system.mem_ctrls.pageHitRate 68.47 # Row buffer hit rate, read and write combined
---
> system.mem_ctrls.avgGap 430712.72 # Average gap between requests
> system.mem_ctrls.pageHitRate 68.43 # Row buffer hit rate, read and write combined
220c220
< system.mem_ctrls_0.readEnergy 4890900 # Energy for read commands per rank (pJ)
---
> system.mem_ctrls_0.readEnergy 4876620 # Energy for read commands per rank (pJ)
223c223
< system.mem_ctrls_0.actBackEnergy 18618480 # Energy for active background per rank (pJ)
---
> system.mem_ctrls_0.actBackEnergy 18588840 # Energy for active background per rank (pJ)
225,230c225,230
< system.mem_ctrls_0.actPowerDownEnergy 210199470 # Energy for active power-down per rank (pJ)
< system.mem_ctrls_0.prePowerDownEnergy 42511680 # Energy for precharge power-down per rank (pJ)
< system.mem_ctrls_0.selfRefreshEnergy 15622140 # Energy for self refresh per rank (pJ)
< system.mem_ctrls_0.totalEnergy 347158215 # Total energy per rank (pJ)
< system.mem_ctrls_0.averagePower 519.590975 # Core power per rank (mW)
< system.mem_ctrls_0.totalIdleTime 622801252 # Total Idle time Per DRAM Rank
---
> system.mem_ctrls_0.actPowerDownEnergy 210561990 # Energy for active power-down per rank (pJ)
> system.mem_ctrls_0.prePowerDownEnergy 42231360 # Energy for precharge power-down per rank (pJ)
> system.mem_ctrls_0.selfRefreshEnergy 15446940 # Energy for self refresh per rank (pJ)
> system.mem_ctrls_0.totalEnergy 347021295 # Total energy per rank (pJ)
> system.mem_ctrls_0.averagePower 519.954143 # Core power per rank (mW)
> system.mem_ctrls_0.totalIdleTime 622134250 # Total Idle time Per DRAM Rank
233,236c233,236
< system.mem_ctrls_0.memoryStateTime::SREF 51287000 # Time in different power states
< system.mem_ctrls_0.memoryStateTime::PRE_PDN 110705750 # Time in different power states
< system.mem_ctrls_0.memoryStateTime::ACT 21255248 # Time in different power states
< system.mem_ctrls_0.memoryStateTime::ACT_PDN 460983502 # Time in different power states
---
> system.mem_ctrls_0.memoryStateTime::SREF 50557000 # Time in different power states
> system.mem_ctrls_0.memoryStateTime::PRE_PDN 109975750 # Time in different power states
> system.mem_ctrls_0.memoryStateTime::ACT 21192250 # Time in different power states
> system.mem_ctrls_0.memoryStateTime::ACT_PDN 461776500 # Time in different power states
242c242
< system.mem_ctrls_1.actBackEnergy 21589320 # Energy for active background per rank (pJ)
---
> system.mem_ctrls_1.actBackEnergy 21584190 # Energy for active background per rank (pJ)
244,249c244,249
< system.mem_ctrls_1.actPowerDownEnergy 243172830 # Energy for active power-down per rank (pJ)
< system.mem_ctrls_1.prePowerDownEnergy 28283040 # Energy for precharge power-down per rank (pJ)
< system.mem_ctrls_1.selfRefreshEnergy 3067740 # Energy for self refresh per rank (pJ)
< system.mem_ctrls_1.totalEnergy 359152785 # Total energy per rank (pJ)
< system.mem_ctrls_1.averagePower 537.543223 # Core power per rank (mW)
< system.mem_ctrls_1.totalIdleTime 616852750 # Total Idle time Per DRAM Rank
---
> system.mem_ctrls_1.actPowerDownEnergy 243510840 # Energy for active power-down per rank (pJ)
> system.mem_ctrls_1.prePowerDownEnergy 28002720 # Energy for precharge power-down per rank (pJ)
> system.mem_ctrls_1.selfRefreshEnergy 2892540 # Energy for self refresh per rank (pJ)
> system.mem_ctrls_1.totalEnergy 359030145 # Total energy per rank (pJ)
> system.mem_ctrls_1.averagePower 537.947423 # Core power per rank (mW)
> system.mem_ctrls_1.totalIdleTime 616133750 # Total Idle time Per DRAM Rank
252,255c252,255
< system.mem_ctrls_1.memoryStateTime::SREF 10481250 # Time in different power states
< system.mem_ctrls_1.memoryStateTime::PRE_PDN 73643500 # Time in different power states
< system.mem_ctrls_1.memoryStateTime::ACT 27629000 # Time in different power states
< system.mem_ctrls_1.memoryStateTime::ACT_PDN 533297750 # Time in different power states
---
> system.mem_ctrls_1.memoryStateTime::SREF 9751250 # Time in different power states
> system.mem_ctrls_1.memoryStateTime::PRE_PDN 72913500 # Time in different power states
> system.mem_ctrls_1.memoryStateTime::ACT 27618000 # Time in different power states
> system.mem_ctrls_1.memoryStateTime::ACT_PDN 534038750 # Time in different power states
257c257
< system.ruby.phys_mem.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
---
> system.ruby.phys_mem.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
260,262c260,262
< system.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 3280 # Number of bytes read from this memory
< system.ruby.phys_mem.bytes_read::cpu1.CUs1.ComputeUnit 3280 # Number of bytes read from this memory
< system.ruby.phys_mem.bytes_read::total 823152 # Number of bytes read from this memory
---
> system.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 2856 # Number of bytes read from this memory
> system.ruby.phys_mem.bytes_read::cpu1.CUs1.ComputeUnit 2856 # Number of bytes read from this memory
> system.ruby.phys_mem.bytes_read::total 822304 # Number of bytes read from this memory
264,266c264,266
< system.ruby.phys_mem.bytes_inst_read::cpu1.CUs0.ComputeUnit 2000 # Number of instructions bytes read from this memory
< system.ruby.phys_mem.bytes_inst_read::cpu1.CUs1.ComputeUnit 2000 # Number of instructions bytes read from this memory
< system.ruby.phys_mem.bytes_inst_read::total 700760 # Number of instructions bytes read from this memory
---
> system.ruby.phys_mem.bytes_inst_read::cpu1.CUs0.ComputeUnit 1576 # Number of instructions bytes read from this memory
> system.ruby.phys_mem.bytes_inst_read::cpu1.CUs1.ComputeUnit 1576 # Number of instructions bytes read from this memory
> system.ruby.phys_mem.bytes_inst_read::total 699912 # Number of instructions bytes read from this memory
273,275c273,275
< system.ruby.phys_mem.num_reads::cpu1.CUs0.ComputeUnit 555 # Number of read requests responded to by this memory
< system.ruby.phys_mem.num_reads::cpu1.CUs1.ComputeUnit 555 # Number of read requests responded to by this memory
< system.ruby.phys_mem.num_reads::total 104891 # Number of read requests responded to by this memory
---
> system.ruby.phys_mem.num_reads::cpu1.CUs0.ComputeUnit 547 # Number of read requests responded to by this memory
> system.ruby.phys_mem.num_reads::cpu1.CUs1.ComputeUnit 547 # Number of read requests responded to by this memory
> system.ruby.phys_mem.num_reads::total 104875 # Number of read requests responded to by this memory
280,299c280,299
< system.ruby.phys_mem.bw_read::cpu0.inst 1042839236 # Total read bandwidth from this memory (bytes/s)
< system.ruby.phys_mem.bw_read::cpu0.data 179352304 # Total read bandwidth from this memory (bytes/s)
< system.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit 4909169 # Total read bandwidth from this memory (bytes/s)
< system.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit 4909169 # Total read bandwidth from this memory (bytes/s)
< system.ruby.phys_mem.bw_read::total 1232009878 # Total read bandwidth from this memory (bytes/s)
< system.ruby.phys_mem.bw_inst_read::cpu0.inst 1042839236 # Instruction read bandwidth from this memory (bytes/s)
< system.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit 2993396 # Instruction read bandwidth from this memory (bytes/s)
< system.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit 2993396 # Instruction read bandwidth from this memory (bytes/s)
< system.ruby.phys_mem.bw_inst_read::total 1048826028 # Instruction read bandwidth from this memory (bytes/s)
< system.ruby.phys_mem.bw_write::cpu0.data 108910217 # Write bandwidth from this memory (bytes/s)
< system.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit 383155 # Write bandwidth from this memory (bytes/s)
< system.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit 383155 # Write bandwidth from this memory (bytes/s)
< system.ruby.phys_mem.bw_write::total 109676526 # Write bandwidth from this memory (bytes/s)
< system.ruby.phys_mem.bw_total::cpu0.inst 1042839236 # Total bandwidth to/from this memory (bytes/s)
< system.ruby.phys_mem.bw_total::cpu0.data 288262521 # Total bandwidth to/from this memory (bytes/s)
< system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 5292324 # Total bandwidth to/from this memory (bytes/s)
< system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 5292324 # Total bandwidth to/from this memory (bytes/s)
< system.ruby.phys_mem.bw_total::total 1341686404 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
< system.ruby.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
---
> system.ruby.phys_mem.bw_read::cpu0.inst 1043979877 # Total read bandwidth from this memory (bytes/s)
> system.ruby.phys_mem.bw_read::cpu0.data 179548477 # Total read bandwidth from this memory (bytes/s)
> system.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit 4279245 # Total read bandwidth from this memory (bytes/s)
> system.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit 4279245 # Total read bandwidth from this memory (bytes/s)
> system.ruby.phys_mem.bw_read::total 1232086843 # Total read bandwidth from this memory (bytes/s)
> system.ruby.phys_mem.bw_inst_read::cpu0.inst 1043979877 # Instruction read bandwidth from this memory (bytes/s)
> system.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit 2361376 # Instruction read bandwidth from this memory (bytes/s)
> system.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit 2361376 # Instruction read bandwidth from this memory (bytes/s)
> system.ruby.phys_mem.bw_inst_read::total 1048702629 # Instruction read bandwidth from this memory (bytes/s)
> system.ruby.phys_mem.bw_write::cpu0.data 109029341 # Write bandwidth from this memory (bytes/s)
> system.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit 383574 # Write bandwidth from this memory (bytes/s)
> system.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit 383574 # Write bandwidth from this memory (bytes/s)
> system.ruby.phys_mem.bw_write::total 109796489 # Write bandwidth from this memory (bytes/s)
> system.ruby.phys_mem.bw_total::cpu0.inst 1043979877 # Total bandwidth to/from this memory (bytes/s)
> system.ruby.phys_mem.bw_total::cpu0.data 288577818 # Total bandwidth to/from this memory (bytes/s)
> system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 4662818 # Total bandwidth to/from this memory (bytes/s)
> system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 4662818 # Total bandwidth to/from this memory (bytes/s)
> system.ruby.phys_mem.bw_total::total 1341883332 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
> system.ruby.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
311,314c311,314
< system.ruby.outstanding_req_hist_coalsr::mean 1.629630
< system.ruby.outstanding_req_hist_coalsr::gmean 1.438746
< system.ruby.outstanding_req_hist_coalsr::stdev 0.926040
< system.ruby.outstanding_req_hist_coalsr | 0 0.00% 0.00% | 16 59.26% 59.26% | 7 25.93% 85.19% | 2 7.41% 92.59% | 2 7.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
---
> system.ruby.outstanding_req_hist_coalsr::mean 2.074074
> system.ruby.outstanding_req_hist_coalsr::gmean 1.820631
> system.ruby.outstanding_req_hist_coalsr::stdev 1.071517
> system.ruby.outstanding_req_hist_coalsr | 0 0.00% 0.00% | 10 37.04% 37.04% | 9 33.33% 70.37% | 4 14.81% 85.19% | 4 14.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
327,330c327,330
< system.ruby.latency_hist_coalsr::mean 171
< system.ruby.latency_hist_coalsr::gmean 22.942606
< system.ruby.latency_hist_coalsr::stdev 184.818206
< system.ruby.latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 7 25.93% 74.07% | 2 7.41% 81.48% | 1 3.70% 85.19% | 1 3.70% 88.89% | 1 3.70% 92.59% | 2 7.41% 100.00% | 0 0.00% 100.00%
---
> system.ruby.latency_hist_coalsr::mean 175.777778
> system.ruby.latency_hist_coalsr::gmean 29.086037
> system.ruby.latency_hist_coalsr::stdev 175.084668
> system.ruby.latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 1 3.70% 51.85% | 2 7.41% 59.26% | 7 25.93% 85.19% | 4 14.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
351,354c351,354
< system.ruby.miss_latency_hist_coalsr::mean 171
< system.ruby.miss_latency_hist_coalsr::gmean 22.942606
< system.ruby.miss_latency_hist_coalsr::stdev 184.818206
< system.ruby.miss_latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 7 25.93% 74.07% | 2 7.41% 81.48% | 1 3.70% 85.19% | 1 3.70% 88.89% | 1 3.70% 92.59% | 2 7.41% 100.00% | 0 0.00% 100.00%
---
> system.ruby.miss_latency_hist_coalsr::mean 175.777778
> system.ruby.miss_latency_hist_coalsr::gmean 29.086037
> system.ruby.miss_latency_hist_coalsr::stdev 175.084668
> system.ruby.miss_latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 1 3.70% 51.85% | 2 7.41% 59.26% | 7 25.93% 85.19% | 4 14.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
380c380
< system.cp_cntrl0.L2cache.num_tag_array_reads 12059 # number of tag array reads
---
> system.cp_cntrl0.L2cache.num_tag_array_reads 12057 # number of tag array reads
382,384c382,384
< system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
< system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
< system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
---
> system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
> system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
> system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
386c386
< system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
---
> system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
388,389c388,389
< system.cpu0.interrupts.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
< system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
---
> system.cpu0.interrupts.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
> system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
393c393
< system.cpu0.pwrStateClkGateDist::mean 2825501 # Distribution of time spent in the clock gated state
---
> system.cpu0.pwrStateClkGateDist::mean 2095501 # Distribution of time spent in the clock gated state
395,396c395,396
< system.cpu0.pwrStateClkGateDist::min_value 2825501 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::max_value 2825501 # Distribution of time spent in the clock gated state
---
> system.cpu0.pwrStateClkGateDist::min_value 2095501 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::max_value 2095501 # Distribution of time spent in the clock gated state
399,400c399,400
< system.cpu0.pwrStateResidencyTicks::CLK_GATED 2825501 # Cumulative time (in ticks) in various power states
< system.cpu0.numCycles 1336275 # number of cpu cycles simulated
---
> system.cpu0.pwrStateResidencyTicks::CLK_GATED 2095501 # Cumulative time (in ticks) in various power states
> system.cpu0.numCycles 1334815 # number of cpu cycles simulated
420,423c420,423
< system.cpu0.num_idle_cycles 5651.003992 # Number of idle cycles
< system.cpu0.num_busy_cycles 1330623.996008 # Number of busy cycles
< system.cpu0.not_idle_fraction 0.995771 # Percentage of non-idle cycles
< system.cpu0.idle_fraction 0.004229 # Percentage of idle cycles
---
> system.cpu0.num_idle_cycles 4191.003994 # Number of idle cycles
> system.cpu0.num_busy_cycles 1330623.996006 # Number of busy cycles
> system.cpu0.not_idle_fraction 0.996860 # Percentage of non-idle cycles
> system.cpu0.idle_fraction 0.003140 # Percentage of idle cycles
466c466
< system.cpu1.CUs0.localDataStore.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
---
> system.cpu1.CUs0.localDataStore.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
469c469
< system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 498 # number of times the wf's instructions are blocked due to RAW dependencies
---
> system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 309 # number of times the wf's instructions are blocked due to RAW dependencies
661c661
< system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 470 # number of times the wf's instructions are blocked due to RAW dependencies
---
> system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 284 # number of times the wf's instructions are blocked due to RAW dependencies
853c853
< system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 473 # number of times the wf's instructions are blocked due to RAW dependencies
---
> system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 279 # number of times the wf's instructions are blocked due to RAW dependencies
1045c1045
< system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 467 # number of times the wf's instructions are blocked due to RAW dependencies
---
> system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 274 # number of times the wf's instructions are blocked due to RAW dependencies
1235,1238c1235,1238
< system.cpu1.CUs0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
< system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it
---
> system.cpu1.CUs0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
> system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 35 # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 11.257143 # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 5.595917 # For each instruction fetch request recieved record how many instructions you got from it
1241,1255c1241,1255
< system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
---
> system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::2 4 11.43% 11.43% # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::3 4 11.43% 22.86% # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::4 1 2.86% 25.71% # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::5 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::6 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::7 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::8 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::9 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::10 4 11.43% 37.14% # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::11 4 11.43% 48.57% # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::12 0 0.00% 48.57% # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::13 0 0.00% 48.57% # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::14 1 2.86% 51.43% # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::15 0 0.00% 51.43% # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::16 17 48.57% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
1274,1276c1274,1276
< system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 3471 # number of cycles the CU issues nothing
---
> system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value 16 # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total 35 # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 2741 # number of cycles the CU issues nothing
1284,1288c1284,1288
< system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 970 # Number of cycles no instruction of specific type issued
< system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 548 # Number of cycles no instruction of specific type issued
< system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 566 # Number of cycles no instruction of specific type issued
< system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 523 # Number of cycles no instruction of specific type issued
< system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 398 # Number of cycles no instruction of specific type issued
---
> system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 625 # Number of cycles no instruction of specific type issued
> system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 340 # Number of cycles no instruction of specific type issued
> system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 338 # Number of cycles no instruction of specific type issued
> system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 335 # Number of cycles no instruction of specific type issued
> system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 404 # Number of cycles no instruction of specific type issued
1290,1292c1290,1292
< system.cpu1.CUs0.ExecStage.spc::samples 3570 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs0.ExecStage.spc::mean 0.039496 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs0.ExecStage.spc::stdev 0.250206 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
---
> system.cpu1.CUs0.ExecStage.spc::samples 2840 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs0.ExecStage.spc::mean 0.049648 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs0.ExecStage.spc::stdev 0.277106 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1294,1297c1294,1297
< system.cpu1.CUs0.ExecStage.spc::0 3471 97.23% 97.23% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs0.ExecStage.spc::1 59 1.65% 98.88% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs0.ExecStage.spc::2 38 1.06% 99.94% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs0.ExecStage.spc::3 2 0.06% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
---
> system.cpu1.CUs0.ExecStage.spc::0 2741 96.51% 96.51% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs0.ExecStage.spc::1 57 2.01% 98.52% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs0.ExecStage.spc::2 42 1.48% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs0.ExecStage.spc::3 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1303,1308c1303,1308
< system.cpu1.CUs0.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs0.ExecStage.spc::total 3570 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 93 # number of CU transitions from active to idle
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 93 # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 37.225806 # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 154.644552 # duration of idle periods in cycles
---
> system.cpu1.CUs0.ExecStage.spc::max_value 2 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs0.ExecStage.spc::total 2840 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 90 # number of CU transitions from active to idle
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 90 # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 29.322222 # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 145.995831 # duration of idle periods in cycles
1310,1326c1310,1326
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 74 79.57% 79.57% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 7 7.53% 87.10% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 1 1.08% 88.17% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 1 1.08% 89.25% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 2 2.15% 91.40% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.08% 92.47% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 92.47% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 92.47% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 92.47% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 92.47% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 92.47% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 92.47% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 92.47% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 92.47% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 92.47% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 92.47% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 7 7.53% 100.00% # duration of idle periods in cycles
---
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 76 84.44% 84.44% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 7 7.78% 92.22% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 92.22% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 0 0.00% 92.22% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 0 0.00% 92.22% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.11% 93.33% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 93.33% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 93.33% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 93.33% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 93.33% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 93.33% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 93.33% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 93.33% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 93.33% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 93.33% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 93.33% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 6 6.67% 100.00% # duration of idle periods in cycles
1329c1329
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 93 # duration of idle periods in cycles
---
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 90 # duration of idle periods in cycles
1331a1332,1353
> system.cpu1.CUs0.valu_insts 68 # Number of vector ALU insts issued.
> system.cpu1.CUs0.valu_insts_per_wf 17 # The avg. number of vector ALU insts issued per-wavefront.
> system.cpu1.CUs0.salu_insts 0 # Number of scalar ALU insts issued.
> system.cpu1.CUs0.salu_insts_per_wf 0 # The avg. number of scalar ALU insts issued per-wavefront.
> system.cpu1.CUs0.inst_cycles_valu 68 # Number of cycles needed to execute VALU insts.
> system.cpu1.CUs0.inst_cycles_salu 0 # Number of cycles needed to execute SALU insts.
> system.cpu1.CUs0.thread_cycles_valu 3076 # Number of thread cycles used to execute vector ALU ops. Similar to instCyclesVALU but multiplied by the number of active threads.
> system.cpu1.CUs0.valu_utilization 70.680147 # Percentage of active vector ALU threads in a wave.
> system.cpu1.CUs0.lds_no_flat_insts 6 # Number of LDS insts issued, not including FLAT accesses that resolve to LDS.
> system.cpu1.CUs0.lds_no_flat_insts_per_wf 1.500000 # The avg. number of LDS insts (not including FLAT accesses that resolve to LDS) per-wavefront.
> system.cpu1.CUs0.flat_vmem_insts 0 # The number of FLAT insts that resolve to vmem issued.
> system.cpu1.CUs0.flat_vmem_insts_per_wf 0 # The average number of FLAT insts that resolve to vmem issued per-wavefront.
> system.cpu1.CUs0.flat_lds_insts 0 # The number of FLAT insts that resolve to LDS issued.
> system.cpu1.CUs0.flat_lds_insts_per_wf 0 # The average number of FLAT insts that resolve to LDS issued per-wavefront.
> system.cpu1.CUs0.vector_mem_writes 8 # Number of vector mem write insts (excluding FLAT insts).
> system.cpu1.CUs0.vector_mem_writes_per_wf 2 # The average number of vector mem write insts (excluding FLAT insts) per-wavefront.
> system.cpu1.CUs0.vector_mem_reads 29 # Number of vector mem read insts (excluding FLAT insts).
> system.cpu1.CUs0.vector_mem_reads_per_wf 7.250000 # The avg. number of vector mem read insts (excluding FLAT insts) per-wavefront.
> system.cpu1.CUs0.scalar_mem_writes 0 # Number of scalar mem write insts.
> system.cpu1.CUs0.scalar_mem_writes_per_wf 0 # The average number of scalar mem write insts per-wavefront.
> system.cpu1.CUs0.scalar_mem_reads 0 # Number of scalar mem read insts.
> system.cpu1.CUs0.scalar_mem_reads_per_wf 0 # The average number of scalar mem read insts per-wavefront.
1333,1334c1355,1356
< system.cpu1.CUs0.tlb_cycles -455223738000 # total number of cycles for all uncoalesced requests
< system.cpu1.CUs0.avg_translation_latency -591968449.934981 # Avg. translation latency for data translations
---
> system.cpu1.CUs0.tlb_cycles -454892896000 # total number of cycles for all uncoalesced requests
> system.cpu1.CUs0.avg_translation_latency -591538226.267880 # Avg. translation latency for data translations
1410,1411c1432,1433
< system.cpu1.CUs0.inst_exec_rate::mean 92.127660 # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs0.inst_exec_rate::stdev 237.147810 # Instruction Execution Rate: Number of executed vector instructions per cycle
---
> system.cpu1.CUs0.inst_exec_rate::mean 71.028369 # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs0.inst_exec_rate::stdev 225.061514 # Instruction Execution Rate: Number of executed vector instructions per cycle
1415,1419c1437,1441
< system.cpu1.CUs0.inst_exec_rate::4-5 52 36.88% 45.39% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs0.inst_exec_rate::6-7 31 21.99% 67.38% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs0.inst_exec_rate::8-9 3 2.13% 69.50% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs0.inst_exec_rate::10 3 2.13% 71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs0.inst_exec_rate::overflows 40 28.37% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
---
> system.cpu1.CUs0.inst_exec_rate::4-5 61 43.26% 51.77% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs0.inst_exec_rate::6-7 32 22.70% 74.47% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs0.inst_exec_rate::8-9 3 2.13% 76.60% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs0.inst_exec_rate::10 3 2.13% 78.72% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs0.inst_exec_rate::overflows 30 21.28% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
1424,1426c1446,1448
< system.cpu1.CUs0.num_total_cycles 3570 # number of cycles the CU ran for
< system.cpu1.CUs0.vpc 1.896078 # Vector Operations per cycle (this CU only)
< system.cpu1.CUs0.ipc 0.039496 # Instructions per cycle (this CU only)
---
> system.cpu1.CUs0.num_total_cycles 2840 # number of cycles the CU ran for
> system.cpu1.CUs0.vpc 2.383451 # Vector Operations per cycle (this CU only)
> system.cpu1.CUs0.ipc 0.049648 # Instructions per cycle (this CU only)
1504c1526
< system.cpu1.CUs1.localDataStore.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
---
> system.cpu1.CUs1.localDataStore.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
1507c1529
< system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 591 # number of times the wf's instructions are blocked due to RAW dependencies
---
> system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 406 # number of times the wf's instructions are blocked due to RAW dependencies
1699c1721
< system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 562 # number of times the wf's instructions are blocked due to RAW dependencies
---
> system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 381 # number of times the wf's instructions are blocked due to RAW dependencies
1891c1913
< system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 561 # number of times the wf's instructions are blocked due to RAW dependencies
---
> system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 372 # number of times the wf's instructions are blocked due to RAW dependencies
2083c2105
< system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 551 # number of times the wf's instructions are blocked due to RAW dependencies
---
> system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 364 # number of times the wf's instructions are blocked due to RAW dependencies
2273,2276c2295,2298
< system.cpu1.CUs1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
< system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it
---
> system.cpu1.CUs1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
> system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 35 # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 11.257143 # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 5.595917 # For each instruction fetch request recieved record how many instructions you got from it
2279,2293c2301,2315
< system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
---
> system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::2 4 11.43% 11.43% # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::3 4 11.43% 22.86% # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::4 1 2.86% 25.71% # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::5 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::6 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::7 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::8 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::9 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::10 4 11.43% 37.14% # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::11 4 11.43% 48.57% # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::12 0 0.00% 48.57% # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::13 0 0.00% 48.57% # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::14 1 2.86% 51.43% # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::15 0 0.00% 51.43% # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::16 17 48.57% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
2312,2315c2334,2337
< system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it
< system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 3471 # number of cycles the CU issues nothing
< system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 99 # number of cycles the CU issued at least one instruction
---
> system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value 16 # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total 35 # For each instruction fetch request recieved record how many instructions you got from it
> system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 2740 # number of cycles the CU issues nothing
> system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 100 # number of cycles the CU issued at least one instruction
2322,2326c2344,2348
< system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 973 # Number of cycles no instruction of specific type issued
< system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 662 # Number of cycles no instruction of specific type issued
< system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 634 # Number of cycles no instruction of specific type issued
< system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 606 # Number of cycles no instruction of specific type issued
< system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 404 # Number of cycles no instruction of specific type issued
---
> system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 795 # Number of cycles no instruction of specific type issued
> system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 437 # Number of cycles no instruction of specific type issued
> system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 431 # Number of cycles no instruction of specific type issued
> system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 422 # Number of cycles no instruction of specific type issued
> system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 408 # Number of cycles no instruction of specific type issued
2328,2330c2350,2352
< system.cpu1.CUs1.ExecStage.spc::samples 3570 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs1.ExecStage.spc::mean 0.039496 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs1.ExecStage.spc::stdev 0.249084 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
---
> system.cpu1.CUs1.ExecStage.spc::samples 2840 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs1.ExecStage.spc::mean 0.049648 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs1.ExecStage.spc::stdev 0.275831 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2332,2335c2354,2357
< system.cpu1.CUs1.ExecStage.spc::0 3471 97.23% 97.23% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs1.ExecStage.spc::1 58 1.62% 98.85% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs1.ExecStage.spc::2 40 1.12% 99.97% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs1.ExecStage.spc::3 1 0.03% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
---
> system.cpu1.CUs1.ExecStage.spc::0 2740 96.48% 96.48% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs1.ExecStage.spc::1 59 2.08% 98.56% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs1.ExecStage.spc::2 41 1.44% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs1.ExecStage.spc::3 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2341,2346c2363,2368
< system.cpu1.CUs1.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs1.ExecStage.spc::total 3570 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 94 # number of CU transitions from active to idle
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 94 # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 35.776596 # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 153.908027 # duration of idle periods in cycles
---
> system.cpu1.CUs1.ExecStage.spc::max_value 2 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs1.ExecStage.spc::total 2840 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 91 # number of CU transitions from active to idle
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 91 # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 30.010989 # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 148.108031 # duration of idle periods in cycles
2348,2364c2370,2386
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 75 79.79% 79.79% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 8 8.51% 88.30% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 88.30% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 1 1.06% 89.36% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 2 2.13% 91.49% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 1 1.06% 92.55% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 92.55% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 92.55% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 92.55% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 92.55% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 92.55% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 92.55% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 92.55% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 92.55% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 92.55% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 92.55% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 7 7.45% 100.00% # duration of idle periods in cycles
---
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 76 83.52% 83.52% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 8 8.79% 92.31% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 92.31% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 0 0.00% 92.31% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 0 0.00% 92.31% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 1 1.10% 93.41% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 93.41% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 93.41% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 93.41% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 93.41% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 93.41% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 93.41% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 93.41% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 93.41% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 93.41% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 93.41% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 6 6.59% 100.00% # duration of idle periods in cycles
2367c2389
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 94 # duration of idle periods in cycles
---
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 91 # duration of idle periods in cycles
2369a2392,2413
> system.cpu1.CUs1.valu_insts 68 # Number of vector ALU insts issued.
> system.cpu1.CUs1.valu_insts_per_wf 17 # The avg. number of vector ALU insts issued per-wavefront.
> system.cpu1.CUs1.salu_insts 0 # Number of scalar ALU insts issued.
> system.cpu1.CUs1.salu_insts_per_wf 0 # The avg. number of scalar ALU insts issued per-wavefront.
> system.cpu1.CUs1.inst_cycles_valu 68 # Number of cycles needed to execute VALU insts.
> system.cpu1.CUs1.inst_cycles_salu 0 # Number of cycles needed to execute SALU insts.
> system.cpu1.CUs1.thread_cycles_valu 3071 # Number of thread cycles used to execute vector ALU ops. Similar to instCyclesVALU but multiplied by the number of active threads.
> system.cpu1.CUs1.valu_utilization 70.565257 # Percentage of active vector ALU threads in a wave.
> system.cpu1.CUs1.lds_no_flat_insts 6 # Number of LDS insts issued, not including FLAT accesses that resolve to LDS.
> system.cpu1.CUs1.lds_no_flat_insts_per_wf 1.500000 # The avg. number of LDS insts (not including FLAT accesses that resolve to LDS) per-wavefront.
> system.cpu1.CUs1.flat_vmem_insts 0 # The number of FLAT insts that resolve to vmem issued.
> system.cpu1.CUs1.flat_vmem_insts_per_wf 0 # The average number of FLAT insts that resolve to vmem issued per-wavefront.
> system.cpu1.CUs1.flat_lds_insts 0 # The number of FLAT insts that resolve to LDS issued.
> system.cpu1.CUs1.flat_lds_insts_per_wf 0 # The average number of FLAT insts that resolve to LDS issued per-wavefront.
> system.cpu1.CUs1.vector_mem_writes 8 # Number of vector mem write insts (excluding FLAT insts).
> system.cpu1.CUs1.vector_mem_writes_per_wf 2 # The average number of vector mem write insts (excluding FLAT insts) per-wavefront.
> system.cpu1.CUs1.vector_mem_reads 29 # Number of vector mem read insts (excluding FLAT insts).
> system.cpu1.CUs1.vector_mem_reads_per_wf 7.250000 # The avg. number of vector mem read insts (excluding FLAT insts) per-wavefront.
> system.cpu1.CUs1.scalar_mem_writes 0 # Number of scalar mem write insts.
> system.cpu1.CUs1.scalar_mem_writes_per_wf 0 # The average number of scalar mem write insts per-wavefront.
> system.cpu1.CUs1.scalar_mem_reads 0 # Number of scalar mem read insts.
> system.cpu1.CUs1.scalar_mem_reads_per_wf 0 # The average number of scalar mem read insts per-wavefront.
2371,2372c2415,2416
< system.cpu1.CUs1.tlb_cycles -455230572000 # total number of cycles for all uncoalesced requests
< system.cpu1.CUs1.avg_translation_latency -591977336.801040 # Avg. translation latency for data translations
---
> system.cpu1.CUs1.tlb_cycles -454919630000 # total number of cycles for all uncoalesced requests
> system.cpu1.CUs1.avg_translation_latency -591572990.897269 # Avg. translation latency for data translations
2448,2449c2492,2493
< system.cpu1.CUs1.inst_exec_rate::mean 91.269504 # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs1.inst_exec_rate::stdev 240.230451 # Instruction Execution Rate: Number of executed vector instructions per cycle
---
> system.cpu1.CUs1.inst_exec_rate::mean 72.113475 # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs1.inst_exec_rate::stdev 228.065470 # Instruction Execution Rate: Number of executed vector instructions per cycle
2453,2457c2497,2501
< system.cpu1.CUs1.inst_exec_rate::4-5 52 36.88% 46.10% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs1.inst_exec_rate::6-7 33 23.40% 69.50% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs1.inst_exec_rate::8-9 6 4.26% 73.76% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs1.inst_exec_rate::10 0 0.00% 73.76% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs1.inst_exec_rate::overflows 37 26.24% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
---
> system.cpu1.CUs1.inst_exec_rate::4-5 60 42.55% 51.77% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs1.inst_exec_rate::6-7 34 24.11% 75.89% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs1.inst_exec_rate::8-9 3 2.13% 78.01% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs1.inst_exec_rate::10 1 0.71% 78.72% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs1.inst_exec_rate::overflows 30 21.28% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
2462,2464c2506,2508
< system.cpu1.CUs1.num_total_cycles 3570 # number of cycles the CU ran for
< system.cpu1.CUs1.vpc 1.894118 # Vector Operations per cycle (this CU only)
< system.cpu1.CUs1.ipc 0.039496 # Instructions per cycle (this CU only)
---
> system.cpu1.CUs1.num_total_cycles 2840 # number of cycles the CU ran for
> system.cpu1.CUs1.vpc 2.380986 # Vector Operations per cycle (this CU only)
> system.cpu1.CUs1.ipc 0.049648 # Instructions per cycle (this CU only)
2542,2544c2586,2588
< system.cpu1.CUs0.ldsBus.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
< system.cpu1.CUs1.ldsBus.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
< system.cpu2.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
---
> system.cpu1.CUs0.ldsBus.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
> system.cpu1.CUs1.ldsBus.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
> system.cpu2.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
2549,2552c2593,2596
< system.dir_cntrl0.L3CacheMemory.num_data_array_writes 1551 # number of data array writes
< system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1551 # number of tag array reads
< system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1551 # number of tag array writes
< system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
---
> system.dir_cntrl0.L3CacheMemory.num_data_array_writes 1549 # number of data array writes
> system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1549 # number of tag array reads
> system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1549 # number of tag array writes
> system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
2555c2599
< system.dispatcher_coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
---
> system.dispatcher_coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
2563c2607
< system.dispatcher_tlb.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
---
> system.dispatcher_tlb.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
2580c2624
< system.l1_coalescer0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
---
> system.l1_coalescer0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
2588c2632
< system.l1_coalescer1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
---
> system.l1_coalescer1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
2596c2640
< system.l1_tlb0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
---
> system.l1_tlb0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
2613c2657
< system.l1_tlb1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
---
> system.l1_tlb1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
2630c2674
< system.l2_coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
---
> system.l2_coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
2638c2682
< system.l2_tlb.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
---
> system.l2_tlb.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
2655c2699
< system.l3_coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
---
> system.l3_coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
2663c2707
< system.l3_tlb.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
---
> system.l3_tlb.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
2678c2722
< system.piobus.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
---
> system.piobus.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
2689,2703c2733,2747
< system.ruby.network.ext_links0.int_node.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
< system.ruby.network.ext_links0.int_node.percent_links_utilized 0.007896
< system.ruby.network.ext_links0.int_node.msg_count.Control::0 1551
< system.ruby.network.ext_links0.int_node.msg_count.Request_Control::0 1551
< system.ruby.network.ext_links0.int_node.msg_count.Response_Data::2 1563
< system.ruby.network.ext_links0.int_node.msg_count.Response_Control::2 1539
< system.ruby.network.ext_links0.int_node.msg_count.Unblock_Control::4 1551
< system.ruby.network.ext_links0.int_node.msg_bytes.Control::0 12408
< system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0 12408
< system.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2 112536
< system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2 12312
< system.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4 12408
< system.ruby.network.ext_links1.int_node.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
< system.ruby.network.ext_links1.int_node.percent_links_utilized 0.009900
< system.ruby.network.ext_links1.int_node.msg_count.Control::0 16
---
> system.ruby.network.ext_links0.int_node.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
> system.ruby.network.ext_links0.int_node.percent_links_utilized 0.007895
> system.ruby.network.ext_links0.int_node.msg_count.Control::0 1549
> system.ruby.network.ext_links0.int_node.msg_count.Request_Control::0 1549
> system.ruby.network.ext_links0.int_node.msg_count.Response_Data::2 1561
> system.ruby.network.ext_links0.int_node.msg_count.Response_Control::2 1537
> system.ruby.network.ext_links0.int_node.msg_count.Unblock_Control::4 1549
> system.ruby.network.ext_links0.int_node.msg_bytes.Control::0 12392
> system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0 12392
> system.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2 112392
> system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2 12296
> system.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4 12392
> system.ruby.network.ext_links1.int_node.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
> system.ruby.network.ext_links1.int_node.percent_links_utilized 0.009908
> system.ruby.network.ext_links1.int_node.msg_count.Control::0 14
2706c2750
< system.ruby.network.ext_links1.int_node.msg_count.Response_Control::2 14
---
> system.ruby.network.ext_links1.int_node.msg_count.Response_Control::2 12
2708c2752
< system.ruby.network.ext_links1.int_node.msg_bytes.Control::0 128
---
> system.ruby.network.ext_links1.int_node.msg_bytes.Control::0 112
2711c2755
< system.ruby.network.ext_links1.int_node.msg_bytes.Response_Control::2 112
---
> system.ruby.network.ext_links1.int_node.msg_bytes.Response_Control::2 96
2716c2760
< system.tcp_cntrl0.L1cache.num_data_array_reads 9 # number of data array reads
---
> system.tcp_cntrl0.L1cache.num_data_array_reads 8 # number of data array reads
2720,2721c2764,2765
< system.tcp_cntrl0.L1cache.num_data_array_stalls 2 # number of stalls caused by data array
< system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
---
> system.tcp_cntrl0.L1cache.num_data_array_stalls 6 # number of stalls caused by data array
> system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
2727c2771
< system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 1 # TCP to TCP store transfers
---
> system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers
2729c2773
< system.tcp_cntrl0.coalescer.gpu_st_misses 4 # stores that miss in the GPU
---
> system.tcp_cntrl0.coalescer.gpu_st_misses 5 # stores that miss in the GPU
2738,2741c2782,2785
< system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
< system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
< system.ruby.network.ext_links2.int_node.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
< system.ruby.network.ext_links2.int_node.percent_links_utilized 0.000716
---
> system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
> system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
> system.ruby.network.ext_links2.int_node.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
> system.ruby.network.ext_links2.int_node.percent_links_utilized 0.000708
2744,2747c2788,2791
< system.ruby.network.ext_links2.int_node.msg_count.Request_Control::0 16
< system.ruby.network.ext_links2.int_node.msg_count.Request_Control::1 19
< system.ruby.network.ext_links2.int_node.msg_count.Response_Data::2 26
< system.ruby.network.ext_links2.int_node.msg_count.Response_Data::3 33
---
> system.ruby.network.ext_links2.int_node.msg_count.Request_Control::0 14
> system.ruby.network.ext_links2.int_node.msg_count.Request_Control::1 17
> system.ruby.network.ext_links2.int_node.msg_count.Response_Data::2 24
> system.ruby.network.ext_links2.int_node.msg_count.Response_Data::3 31
2749,2750c2793,2794
< system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::4 16
< system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::5 19
---
> system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::4 14
> system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::5 17
2753,2756c2797,2800
< system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::0 128
< system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::1 152
< system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::2 1872
< system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::3 2376
---
> system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::0 112
> system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::1 136
> system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::2 1728
> system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::3 2232
2758,2759c2802,2803
< system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::4 128
< system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::5 152
---
> system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::4 112
> system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::5 136
2763c2807
< system.tcp_cntrl1.L1cache.num_data_array_reads 7 # number of data array reads
---
> system.tcp_cntrl1.L1cache.num_data_array_reads 8 # number of data array reads
2768,2769c2812,2813
< system.tcp_cntrl1.L1cache.num_data_array_stalls 2 # number of stalls caused by data array
< system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
---
> system.tcp_cntrl1.L1cache.num_data_array_stalls 6 # number of stalls caused by data array
> system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
2775c2819
< system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers
---
> system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 1 # TCP to TCP store transfers
2777c2821
< system.tcp_cntrl1.coalescer.gpu_st_misses 5 # stores that miss in the GPU
---
> system.tcp_cntrl1.coalescer.gpu_st_misses 4 # stores that miss in the GPU
2786,2787c2830,2831
< system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
< system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
---
> system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
> system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
2791,2798c2835,2842
< system.sqc_cntrl0.L1cache.num_data_array_reads 86 # number of data array reads
< system.sqc_cntrl0.L1cache.num_data_array_writes 5 # number of data array writes
< system.sqc_cntrl0.L1cache.num_tag_array_reads 86 # number of tag array reads
< system.sqc_cntrl0.L1cache.num_tag_array_writes 5 # number of tag array writes
< system.sqc_cntrl0.L1cache.num_data_array_stalls 47 # number of stalls caused by data array
< system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
< system.sqc_cntrl0.sequencer.load_waiting_on_load 120 # Number of times a load aliased with a pending load
< system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
---
> system.sqc_cntrl0.L1cache.num_data_array_reads 70 # number of data array reads
> system.sqc_cntrl0.L1cache.num_data_array_writes 3 # number of data array writes
> system.sqc_cntrl0.L1cache.num_tag_array_reads 70 # number of tag array reads
> system.sqc_cntrl0.L1cache.num_tag_array_writes 3 # number of tag array writes
> system.sqc_cntrl0.L1cache.num_data_array_stalls 28 # number of stalls caused by data array
> system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
> system.sqc_cntrl0.sequencer.load_waiting_on_load 75 # Number of times a load aliased with a pending load
> system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
2802c2846
< system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
---
> system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
2806,2819c2850,2863
< system.tccdir_cntrl0.directory.num_tag_array_reads 1554 # number of tag array reads
< system.tccdir_cntrl0.directory.num_tag_array_writes 27 # number of tag array writes
< system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
< system.ruby.network.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
< system.ruby.network.msg_count.Control 3116
< system.ruby.network.msg_count.Request_Control 3121
< system.ruby.network.msg_count.Response_Data 3159
< system.ruby.network.msg_count.Response_Control 3078
< system.ruby.network.msg_count.Unblock_Control 3121
< system.ruby.network.msg_byte.Control 24928
< system.ruby.network.msg_byte.Request_Control 24968
< system.ruby.network.msg_byte.Response_Data 227448
< system.ruby.network.msg_byte.Response_Control 24624
< system.ruby.network.msg_byte.Unblock_Control 24968
---
> system.tccdir_cntrl0.directory.num_tag_array_reads 1552 # number of tag array reads
> system.tccdir_cntrl0.directory.num_tag_array_writes 25 # number of tag array writes
> system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
> system.ruby.network.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
> system.ruby.network.msg_count.Control 3112
> system.ruby.network.msg_count.Request_Control 3115
> system.ruby.network.msg_count.Response_Data 3153
> system.ruby.network.msg_count.Response_Control 3074
> system.ruby.network.msg_count.Unblock_Control 3115
> system.ruby.network.msg_byte.Control 24896
> system.ruby.network.msg_byte.Request_Control 24920
> system.ruby.network.msg_byte.Response_Data 227016
> system.ruby.network.msg_byte.Response_Control 24592
> system.ruby.network.msg_byte.Unblock_Control 24920
2822,2827c2866,2871
< system.sqc_coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
< system.sqc_coalescer.uncoalesced_accesses 86 # Number of uncoalesced TLB accesses
< system.sqc_coalescer.coalesced_accesses 60 # Number of coalesced TLB accesses
< system.sqc_coalescer.queuing_cycles 108000 # Number of cycles spent in queue
< system.sqc_coalescer.local_queuing_cycles 108000 # Number of cycles spent in queue for all incoming reqs
< system.sqc_coalescer.local_latency 1255.813953 # Avg. latency over all incoming pkts
---
> system.sqc_coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
> system.sqc_coalescer.uncoalesced_accesses 70 # Number of uncoalesced TLB accesses
> system.sqc_coalescer.coalesced_accesses 50 # Number of coalesced TLB accesses
> system.sqc_coalescer.queuing_cycles 100000 # Number of cycles spent in queue
> system.sqc_coalescer.local_queuing_cycles 100000 # Number of cycles spent in queue for all incoming reqs
> system.sqc_coalescer.local_latency 1428.571429 # Avg. latency over all incoming pkts
2830,2832c2874,2876
< system.sqc_tlb.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
< system.sqc_tlb.local_TLB_accesses 60 # Number of TLB accesses
< system.sqc_tlb.local_TLB_hits 59 # Number of TLB hits
---
> system.sqc_tlb.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
> system.sqc_tlb.local_TLB_accesses 50 # Number of TLB accesses
> system.sqc_tlb.local_TLB_hits 49 # Number of TLB hits
2834,2836c2878,2880
< system.sqc_tlb.local_TLB_miss_rate 1.666667 # TLB miss rate
< system.sqc_tlb.global_TLB_accesses 86 # Number of TLB accesses
< system.sqc_tlb.global_TLB_hits 78 # Number of TLB hits
---
> system.sqc_tlb.local_TLB_miss_rate 2 # TLB miss rate
> system.sqc_tlb.global_TLB_accesses 70 # Number of TLB accesses
> system.sqc_tlb.global_TLB_hits 62 # Number of TLB hits
2838,2839c2882,2883
< system.sqc_tlb.global_TLB_miss_rate 9.302326 # TLB miss rate
< system.sqc_tlb.access_cycles 86008 # Cycles spent accessing this TLB level
---
> system.sqc_tlb.global_TLB_miss_rate 11.428571 # TLB miss rate
> system.sqc_tlb.access_cycles 70008 # Cycles spent accessing this TLB level
2842,2843c2886,2887
< system.sqc_tlb.local_cycles 60001 # Number of cycles spent in queue for all incoming reqs
< system.sqc_tlb.local_latency 1000.016667 # Avg. latency over incoming coalesced reqs
---
> system.sqc_tlb.local_cycles 50001 # Number of cycles spent in queue for all incoming reqs
> system.sqc_tlb.local_latency 1000.020000 # Avg. latency over incoming coalesced reqs
2845,2847c2889,2891
< system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states
< system.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.005553
< system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1551
---
> system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
> system.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.005552
> system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1549
2849,2851c2893,2895
< system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2 1539
< system.ruby.network.ext_links0.int_node.throttle0.msg_count.Unblock_Control::4 1551
< system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0 12408
---
> system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2 1537
> system.ruby.network.ext_links0.int_node.throttle0.msg_count.Unblock_Control::4 1549
> system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0 12392
2853,2856c2897,2900
< system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Control::2 12312
< system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Unblock_Control::4 12408
< system.ruby.network.ext_links0.int_node.throttle1.link_utilization 0.016173
< system.ruby.network.ext_links0.int_node.throttle1.msg_count.Control::0 16
---
> system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Control::2 12296
> system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Unblock_Control::4 12392
> system.ruby.network.ext_links0.int_node.throttle1.link_utilization 0.016188
> system.ruby.network.ext_links0.int_node.throttle1.msg_count.Control::0 14
2858c2902
< system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Control::0 128
---
> system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Control::0 112
2860c2904
< system.ruby.network.ext_links0.int_node.throttle2.link_utilization 0.001963
---
> system.ruby.network.ext_links0.int_node.throttle2.link_utilization 0.001944
2862c2906
< system.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Data::2 16
---
> system.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Data::2 14
2864,2866c2908,2910
< system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Data::2 1152
< system.ruby.network.ext_links1.int_node.throttle0.link_utilization 0.016173
< system.ruby.network.ext_links1.int_node.throttle0.msg_count.Control::0 16
---
> system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Data::2 1008
> system.ruby.network.ext_links1.int_node.throttle0.link_utilization 0.016188
> system.ruby.network.ext_links1.int_node.throttle0.msg_count.Control::0 14
2868c2912
< system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Control::0 128
---
> system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Control::0 112
2870c2914
< system.ruby.network.ext_links1.int_node.throttle1.link_utilization 0.003627
---
> system.ruby.network.ext_links1.int_node.throttle1.link_utilization 0.003629
2873c2917
< system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Control::2 14
---
> system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Control::2 12
2877c2921
< system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Control::2 112
---
> system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Control::2 96
2890c2934
< system.ruby.network.ext_links2.int_node.throttle3.link_utilization 0.002155
---
> system.ruby.network.ext_links2.int_node.throttle3.link_utilization 0.002132
2892,2893c2936,2937
< system.ruby.network.ext_links2.int_node.throttle3.msg_count.Request_Control::1 19
< system.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::2 16
---
> system.ruby.network.ext_links2.int_node.throttle3.msg_count.Request_Control::1 17
> system.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::2 14
2895c2939
< system.ruby.network.ext_links2.int_node.throttle3.msg_count.Unblock_Control::5 19
---
> system.ruby.network.ext_links2.int_node.throttle3.msg_count.Unblock_Control::5 17
2897,2898c2941,2942
< system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Request_Control::1 152
< system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Response_Data::2 1152
---
> system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Request_Control::1 136
> system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Response_Data::2 1008
2900,2905c2944,2949
< system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Unblock_Control::5 152
< system.ruby.network.ext_links2.int_node.throttle4.link_utilization 0.000053
< system.ruby.network.ext_links2.int_node.throttle4.msg_count.Response_Data::3 5
< system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Response_Data::3 360
< system.ruby.network.ext_links2.int_node.throttle5.link_utilization 0.001926
< system.ruby.network.ext_links2.int_node.throttle5.msg_count.Request_Control::0 16
---
> system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Unblock_Control::5 136
> system.ruby.network.ext_links2.int_node.throttle4.link_utilization 0.000032
> system.ruby.network.ext_links2.int_node.throttle4.msg_count.Response_Data::3 3
> system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Response_Data::3 216
> system.ruby.network.ext_links2.int_node.throttle5.link_utilization 0.001923
> system.ruby.network.ext_links2.int_node.throttle5.msg_count.Request_Control::0 14
2908,2909c2952,2953
< system.ruby.network.ext_links2.int_node.throttle5.msg_count.Unblock_Control::4 16
< system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Request_Control::0 128
---
> system.ruby.network.ext_links2.int_node.throttle5.msg_count.Unblock_Control::4 14
> system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Request_Control::0 112
2912c2956
< system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Unblock_Control::4 128
---
> system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Unblock_Control::4 112
2927c2971
< system.ruby.CorePair_Controller.PrbShrData 7 0.00% 0.00%
---
> system.ruby.CorePair_Controller.PrbShrData 5 0.00% 0.00%
2932c2976
< system.ruby.CorePair_Controller.I.PrbShrData 5 0.00% 0.00%
---
> system.ruby.CorePair_Controller.I.PrbShrData 3 0.00% 0.00%
2958c3002
< system.ruby.Directory_Controller.RdBlkS 1039 0.00% 0.00%
---
> system.ruby.Directory_Controller.RdBlkS 1037 0.00% 0.00%
2961,2965c3005,3009
< system.ruby.Directory_Controller.CPUPrbResp 1551 0.00% 0.00%
< system.ruby.Directory_Controller.ProbeAcksComplete 1551 0.00% 0.00%
< system.ruby.Directory_Controller.MemData 1551 0.00% 0.00%
< system.ruby.Directory_Controller.CoreUnblock 1551 0.00% 0.00%
< system.ruby.Directory_Controller.U.RdBlkS 1039 0.00% 0.00%
---
> system.ruby.Directory_Controller.CPUPrbResp 1549 0.00% 0.00%
> system.ruby.Directory_Controller.ProbeAcksComplete 1549 0.00% 0.00%
> system.ruby.Directory_Controller.MemData 1549 0.00% 0.00%
> system.ruby.Directory_Controller.CoreUnblock 1549 0.00% 0.00%
> system.ruby.Directory_Controller.U.RdBlkS 1037 0.00% 0.00%
2968,2986c3012,3030
< system.ruby.Directory_Controller.BS_M.MemData 36 0.00% 0.00%
< system.ruby.Directory_Controller.BM_M.MemData 13 0.00% 0.00%
< system.ruby.Directory_Controller.B_M.MemData 12 0.00% 0.00%
< system.ruby.Directory_Controller.BS_PM.CPUPrbResp 36 0.00% 0.00%
< system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 36 0.00% 0.00%
< system.ruby.Directory_Controller.BS_PM.MemData 1003 0.00% 0.00%
< system.ruby.Directory_Controller.BM_PM.CPUPrbResp 14 0.00% 0.00%
< system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 13 0.00% 0.00%
< system.ruby.Directory_Controller.BM_PM.MemData 322 0.00% 0.00%
< system.ruby.Directory_Controller.B_PM.CPUPrbResp 12 0.00% 0.00%
< system.ruby.Directory_Controller.B_PM.ProbeAcksComplete 12 0.00% 0.00%
< system.ruby.Directory_Controller.B_PM.MemData 165 0.00% 0.00%
< system.ruby.Directory_Controller.BS_Pm.CPUPrbResp 1003 0.00% 0.00%
< system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 1003 0.00% 0.00%
< system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 321 0.00% 0.00%
< system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 322 0.00% 0.00%
< system.ruby.Directory_Controller.B_Pm.CPUPrbResp 165 0.00% 0.00%
< system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 165 0.00% 0.00%
< system.ruby.Directory_Controller.B.CoreUnblock 1551 0.00% 0.00%
---
> system.ruby.Directory_Controller.BS_M.MemData 35 0.00% 0.00%
> system.ruby.Directory_Controller.BM_M.MemData 18 0.00% 0.00%
> system.ruby.Directory_Controller.B_M.MemData 11 0.00% 0.00%
> system.ruby.Directory_Controller.BS_PM.CPUPrbResp 35 0.00% 0.00%
> system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 35 0.00% 0.00%
> system.ruby.Directory_Controller.BS_PM.MemData 1002 0.00% 0.00%
> system.ruby.Directory_Controller.BM_PM.CPUPrbResp 18 0.00% 0.00%
> system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 18 0.00% 0.00%
> system.ruby.Directory_Controller.BM_PM.MemData 317 0.00% 0.00%
> system.ruby.Directory_Controller.B_PM.CPUPrbResp 11 0.00% 0.00%
> system.ruby.Directory_Controller.B_PM.ProbeAcksComplete 11 0.00% 0.00%
> system.ruby.Directory_Controller.B_PM.MemData 166 0.00% 0.00%
> system.ruby.Directory_Controller.BS_Pm.CPUPrbResp 1002 0.00% 0.00%
> system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 1002 0.00% 0.00%
> system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 317 0.00% 0.00%
> system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 317 0.00% 0.00%
> system.ruby.Directory_Controller.B_Pm.CPUPrbResp 166 0.00% 0.00%
> system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 166 0.00% 0.00%
> system.ruby.Directory_Controller.B.CoreUnblock 1549 0.00% 0.00%
2998,3001c3042,3045
< system.ruby.LD.latency_hist_coalsr::mean 219.555556
< system.ruby.LD.latency_hist_coalsr::gmean 24.880500
< system.ruby.LD.latency_hist_coalsr::stdev 259.591078
< system.ruby.LD.latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 1 11.11% 66.67% | 1 11.11% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00%
---
> system.ruby.LD.latency_hist_coalsr::mean 133.666667
> system.ruby.LD.latency_hist_coalsr::gmean 19.860866
> system.ruby.LD.latency_hist_coalsr::stdev 158.801763
> system.ruby.LD.latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 1 11.11% 66.67% | 1 11.11% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3022,3025c3066,3069
< system.ruby.LD.miss_latency_hist_coalsr::mean 219.555556
< system.ruby.LD.miss_latency_hist_coalsr::gmean 24.880500
< system.ruby.LD.miss_latency_hist_coalsr::stdev 259.591078
< system.ruby.LD.miss_latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 1 11.11% 66.67% | 1 11.11% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00%
---
> system.ruby.LD.miss_latency_hist_coalsr::mean 133.666667
> system.ruby.LD.miss_latency_hist_coalsr::gmean 19.860866
> system.ruby.LD.miss_latency_hist_coalsr::stdev 158.801763
> system.ruby.LD.miss_latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 1 11.11% 66.67% | 1 11.11% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3035,3036c3079,3080
< system.ruby.ST.latency_hist_coalsr::bucket_size 32
< system.ruby.ST.latency_hist_coalsr::max_bucket 319
---
> system.ruby.ST.latency_hist_coalsr::bucket_size 64
> system.ruby.ST.latency_hist_coalsr::max_bucket 639
3038,3041c3082,3085
< system.ruby.ST.latency_hist_coalsr::mean 125.375000
< system.ruby.ST.latency_hist_coalsr::gmean 15.802815
< system.ruby.ST.latency_hist_coalsr::stdev 128.476133
< system.ruby.ST.latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 7 43.75% 93.75% | 1 6.25% 100.00% | 0 0.00% 100.00%
---
> system.ruby.ST.latency_hist_coalsr::mean 184.500000
> system.ruby.ST.latency_hist_coalsr::gmean 27.004823
> system.ruby.ST.latency_hist_coalsr::stdev 190.921974
> system.ruby.ST.latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 4 25.00% 75.00% | 4 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3058,3059c3102,3103
< system.ruby.ST.miss_latency_hist_coalsr::bucket_size 32
< system.ruby.ST.miss_latency_hist_coalsr::max_bucket 319
---
> system.ruby.ST.miss_latency_hist_coalsr::bucket_size 64
> system.ruby.ST.miss_latency_hist_coalsr::max_bucket 639
3061,3064c3105,3108
< system.ruby.ST.miss_latency_hist_coalsr::mean 125.375000
< system.ruby.ST.miss_latency_hist_coalsr::gmean 15.802815
< system.ruby.ST.miss_latency_hist_coalsr::stdev 128.476133
< system.ruby.ST.miss_latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 7 43.75% 93.75% | 1 6.25% 100.00% | 0 0.00% 100.00%
---
> system.ruby.ST.miss_latency_hist_coalsr::mean 184.500000
> system.ruby.ST.miss_latency_hist_coalsr::gmean 27.004823
> system.ruby.ST.miss_latency_hist_coalsr::stdev 190.921974
> system.ruby.ST.miss_latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 4 25.00% 75.00% | 4 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3069,3071c3113,3115
< system.ruby.ATOMIC.latency_hist_coalsr::mean 317.500000
< system.ruby.ATOMIC.latency_hist_coalsr::gmean 314.366029
< system.ruby.ATOMIC.latency_hist_coalsr::stdev 62.932504
---
> system.ruby.ATOMIC.latency_hist_coalsr::mean 295.500000
> system.ruby.ATOMIC.latency_hist_coalsr::gmean 293.237105
> system.ruby.ATOMIC.latency_hist_coalsr::stdev 51.618795
3077,3079c3121,3123
< system.ruby.ATOMIC.miss_latency_hist_coalsr::mean 317.500000
< system.ruby.ATOMIC.miss_latency_hist_coalsr::gmean 314.366029
< system.ruby.ATOMIC.miss_latency_hist_coalsr::stdev 62.932504
---
> system.ruby.ATOMIC.miss_latency_hist_coalsr::mean 295.500000
> system.ruby.ATOMIC.miss_latency_hist_coalsr::gmean 293.237105
> system.ruby.ATOMIC.miss_latency_hist_coalsr::stdev 51.618795
3181,3184c3225,3228
< system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean 478.666667
< system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 470.839796
< system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 101.159939
< system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 2 66.67% 100.00% | 0 0.00% 100.00%
---
> system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean 338.666667
> system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 338.633640
> system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 5.773503
> system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3189,3192c3233,3236
< system.ruby.TCP.miss_mach_latency_hist_coalsr::mean 1.538462
< system.ruby.TCP.miss_mach_latency_hist_coalsr::gmean 1.377009
< system.ruby.TCP.miss_mach_latency_hist_coalsr::stdev 0.877058
< system.ruby.TCP.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 8 61.54% 61.54% | 4 30.77% 92.31% | 0 0.00% 92.31% | 1 7.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
---
> system.ruby.TCP.miss_mach_latency_hist_coalsr::mean 2.153846
> system.ruby.TCP.miss_mach_latency_hist_coalsr::gmean 2.109532
> system.ruby.TCP.miss_mach_latency_hist_coalsr::stdev 0.554700
> system.ruby.TCP.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 12 92.31% 92.31% | 0 0.00% 92.31% | 1 7.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3197,3200c3241,3244
< system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 287.363636
< system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 279.637814
< system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 78.345737
< system.ruby.TCCdir.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 63.64% 63.64% | 2 18.18% 81.82% | 0 0.00% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
---
> system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 336.545455
> system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 330.845159
> system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 64.151950
> system.ruby.TCCdir.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 9.09% 9.09% | 2 18.18% 27.27% | 4 36.36% 63.64% | 4 36.36% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3227,3230c3271,3273
< system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 537
< system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 536.976722
< system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev 7.071068
< system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00%
---
> system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 342
> system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 342.000000
> system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3240,3241c3283,3284
< system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 64
< system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 639
---
> system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32
> system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319
3243,3246c3286,3289
< system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean 445
< system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 444.959549
< system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 8.485281
< system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
---
> system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean 253.500000
> system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 253.440328
> system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 7.778175
> system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00%
3266,3268c3309,3311
< system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::mean 1
< system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::gmean 1
< system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 8 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
---
> system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::mean 2
> system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::gmean 2
> system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 8 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3270,3271c3313,3314
< system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32
< system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319
---
> system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 64
> system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 639
3273,3276c3316,3319
< system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 249.750000
< system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 249.728954
< system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 3.494894
< system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 87.50% 87.50% | 1 12.50% 100.00% | 0 0.00% 100.00%
---
> system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 367
> system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 364.630235
> system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 44.510031
> system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 50.00% 50.00% | 4 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3281,3282c3324,3325
< system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 362
< system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 362.000000
---
> system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 332
> system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 332.000000
3289,3290c3332,3333
< system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::mean 273
< system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 273
---
> system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::mean 259
> system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 259.000000
3344,3351c3387,3394
< system.ruby.SQC_Controller.Fetch 86 0.00% 0.00%
< system.ruby.SQC_Controller.TCC_AckS 5 0.00% 0.00%
< system.ruby.SQC_Controller.I.Fetch 5 0.00% 0.00%
< system.ruby.SQC_Controller.S.Fetch 81 0.00% 0.00%
< system.ruby.SQC_Controller.I_S.TCC_AckS 5 0.00% 0.00%
< system.ruby.TCCdir_Controller.RdBlk 93 0.00% 0.00%
< system.ruby.TCCdir_Controller.RdBlkM 37 0.00% 0.00%
< system.ruby.TCCdir_Controller.RdBlkS 5 0.00% 0.00%
---
> system.ruby.SQC_Controller.Fetch 70 0.00% 0.00%
> system.ruby.SQC_Controller.TCC_AckS 3 0.00% 0.00%
> system.ruby.SQC_Controller.I.Fetch 3 0.00% 0.00%
> system.ruby.SQC_Controller.S.Fetch 67 0.00% 0.00%
> system.ruby.SQC_Controller.I_S.TCC_AckS 3 0.00% 0.00%
> system.ruby.TCCdir_Controller.RdBlk 54 0.00% 0.00%
> system.ruby.TCCdir_Controller.RdBlkM 34 0.00% 0.00%
> system.ruby.TCCdir_Controller.RdBlkS 3 0.00% 0.00%
3354c3397
< system.ruby.TCCdir_Controller.CoreUnblock 17 0.00% 0.00%
---
> system.ruby.TCCdir_Controller.CoreUnblock 15 0.00% 0.00%
3356c3399
< system.ruby.TCCdir_Controller.NB_AckS 7 0.00% 0.00%
---
> system.ruby.TCCdir_Controller.NB_AckS 5 0.00% 0.00%
3362c3405
< system.ruby.TCCdir_Controller.I.RdBlkS 5 0.00% 0.00%
---
> system.ruby.TCCdir_Controller.I.RdBlkS 3 0.00% 0.00%
3373c3416
< system.ruby.TCCdir_Controller.I_M.RdBlkM 22 0.00% 0.00%
---
> system.ruby.TCCdir_Controller.I_M.RdBlkM 20 0.00% 0.00%
3375c3418
< system.ruby.TCCdir_Controller.I_ES.RdBlk 79 0.00% 0.00%
---
> system.ruby.TCCdir_Controller.I_ES.RdBlk 41 0.00% 0.00%
3377c3420
< system.ruby.TCCdir_Controller.I_S.NB_AckS 5 0.00% 0.00%
---
> system.ruby.TCCdir_Controller.I_S.NB_AckS 3 0.00% 0.00%
3384,3386c3427,3429
< system.ruby.TCCdir_Controller.BBB_S.RdBlk 10 0.00% 0.00%
< system.ruby.TCCdir_Controller.BBB_S.CoreUnblock 7 0.00% 0.00%
< system.ruby.TCCdir_Controller.BBB_M.RdBlkM 5 0.00% 0.00%
---
> system.ruby.TCCdir_Controller.BBB_S.RdBlk 9 0.00% 0.00%
> system.ruby.TCCdir_Controller.BBB_S.CoreUnblock 5 0.00% 0.00%
> system.ruby.TCCdir_Controller.BBB_M.RdBlkM 4 0.00% 0.00%
3396c3439
< system.ruby.TCP_Controller.PrbInvData | 1 33.33% 33.33% | 2 66.67% 100.00%
---
> system.ruby.TCP_Controller.PrbInvData | 2 66.67% 66.67% | 1 33.33% 100.00%
3398c3441
< system.ruby.TCP_Controller.PrbShrData | 7 63.64% 63.64% | 4 36.36% 100.00%
---
> system.ruby.TCP_Controller.PrbShrData | 6 54.55% 54.55% | 5 45.45% 100.00%
3412c3455
< system.ruby.TCP_Controller.M.PrbInvData | 0 0.00% 0.00% | 1 100.00% 100.00%
---
> system.ruby.TCP_Controller.M.PrbInvData | 1 100.00% 100.00% | 0 0.00% 100.00%
3414c3457
< system.ruby.TCP_Controller.M.PrbShrData | 5 55.56% 55.56% | 4 44.44% 100.00%
---
> system.ruby.TCP_Controller.M.PrbShrData | 4 44.44% 44.44% | 5 55.56% 100.00%