7,11c7,11
< host_inst_rate 74039 # Simulator instruction rate (inst/s)
< host_op_rate 152254 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 733530611 # Simulator tick rate (ticks/s)
< host_mem_usage 1301780 # Number of bytes of host memory used
< host_seconds 0.90 # Real time elapsed on the host
---
> host_inst_rate 97803 # Simulator instruction rate (inst/s)
> host_op_rate 201121 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 968968514 # Simulator tick rate (ticks/s)
> host_mem_usage 1290208 # Number of bytes of host memory used
> host_seconds 0.68 # Real time elapsed on the host
90,91c90,91
< system.mem_ctrls.rdQLenPdf::5 3 # What read queue length does an incoming req see
< system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
---
> system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see
> system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see
195,196c195,196
< system.mem_ctrls.totQLat 15500500 # Total ticks spent queuing
< system.mem_ctrls.totMemAccLat 44581750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.mem_ctrls.totQLat 15500495 # Total ticks spent queuing
> system.mem_ctrls.totMemAccLat 44581745 # Total ticks spent from burst creation until serviced by the DRAM
296,301c296,301
< system.ruby.outstanding_req_hist_coalsr::samples 28
< system.ruby.outstanding_req_hist_coalsr::mean 1.642857
< system.ruby.outstanding_req_hist_coalsr::gmean 1.455771
< system.ruby.outstanding_req_hist_coalsr::stdev 0.911421
< system.ruby.outstanding_req_hist_coalsr | 0 0.00% 0.00% | 16 57.14% 57.14% | 8 28.57% 85.71% | 2 7.14% 92.86% | 2 7.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
< system.ruby.outstanding_req_hist_coalsr::total 28
---
> system.ruby.outstanding_req_hist_coalsr::samples 27
> system.ruby.outstanding_req_hist_coalsr::mean 1.629630
> system.ruby.outstanding_req_hist_coalsr::gmean 1.438746
> system.ruby.outstanding_req_hist_coalsr::stdev 0.926040
> system.ruby.outstanding_req_hist_coalsr | 0 0.00% 0.00% | 16 59.26% 59.26% | 7 25.93% 85.19% | 2 7.41% 92.59% | 2 7.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
> system.ruby.outstanding_req_hist_coalsr::total 27
305c305
< system.ruby.latency_hist_seqr::mean 4.784183
---
> system.ruby.latency_hist_seqr::mean 4.784165
307c307
< system.ruby.latency_hist_seqr::stdev 23.846744
---
> system.ruby.latency_hist_seqr::stdev 23.846473
312,317c312,317
< system.ruby.latency_hist_coalsr::samples 28
< system.ruby.latency_hist_coalsr::mean 136.285714
< system.ruby.latency_hist_coalsr::gmean 19.975449
< system.ruby.latency_hist_coalsr::stdev 139.699905
< system.ruby.latency_hist_coalsr | 14 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 10 35.71% 85.71% | 1 3.57% 89.29% | 3 10.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
< system.ruby.latency_hist_coalsr::total 28
---
> system.ruby.latency_hist_coalsr::samples 27
> system.ruby.latency_hist_coalsr::mean 141.296296
> system.ruby.latency_hist_coalsr::gmean 21.202698
> system.ruby.latency_hist_coalsr::stdev 140.217089
> system.ruby.latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 10 37.04% 85.19% | 1 3.70% 88.89% | 3 11.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
> system.ruby.latency_hist_coalsr::total 27
321,323c321,323
< system.ruby.hit_latency_hist_seqr::mean 208.449511
< system.ruby.hit_latency_hist_seqr::gmean 208.002927
< system.ruby.hit_latency_hist_seqr::stdev 15.847049
---
> system.ruby.hit_latency_hist_seqr::mean 208.448208
> system.ruby.hit_latency_hist_seqr::gmean 208.002202
> system.ruby.hit_latency_hist_seqr::stdev 15.833423
336,341c336,341
< system.ruby.miss_latency_hist_coalsr::samples 28
< system.ruby.miss_latency_hist_coalsr::mean 136.285714
< system.ruby.miss_latency_hist_coalsr::gmean 19.975449
< system.ruby.miss_latency_hist_coalsr::stdev 139.699905
< system.ruby.miss_latency_hist_coalsr | 14 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 10 35.71% 85.71% | 1 3.57% 89.29% | 3 10.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
< system.ruby.miss_latency_hist_coalsr::total 28
---
> system.ruby.miss_latency_hist_coalsr::samples 27
> system.ruby.miss_latency_hist_coalsr::mean 141.296296
> system.ruby.miss_latency_hist_coalsr::gmean 21.202698
> system.ruby.miss_latency_hist_coalsr::stdev 140.217089
> system.ruby.miss_latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 10 37.04% 85.19% | 1 3.70% 88.89% | 3 11.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
> system.ruby.miss_latency_hist_coalsr::total 27
391,394c391,394
< system.cpu0.num_idle_cycles 5227.003992 # Number of idle cycles
< system.cpu0.num_busy_cycles 1321681.996008 # Number of busy cycles
< system.cpu0.not_idle_fraction 0.996061 # Percentage of non-idle cycles
< system.cpu0.idle_fraction 0.003939 # Percentage of idle cycles
---
> system.cpu0.num_idle_cycles 5231.003992 # Number of idle cycles
> system.cpu0.num_busy_cycles 1321677.996008 # Number of busy cycles
> system.cpu0.not_idle_fraction 0.996058 # Percentage of non-idle cycles
> system.cpu0.idle_fraction 0.003942 # Percentage of idle cycles
435c435
< system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 297 # number of times the wf's instructions are blocked due to RAW dependencies
---
> system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 307 # number of times the wf's instructions are blocked due to RAW dependencies
627c627
< system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 273 # number of times the wf's instructions are blocked due to RAW dependencies
---
> system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 279 # number of times the wf's instructions are blocked due to RAW dependencies
819c819
< system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 272 # number of times the wf's instructions are blocked due to RAW dependencies
---
> system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 282 # number of times the wf's instructions are blocked due to RAW dependencies
1011c1011
< system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 256 # number of times the wf's instructions are blocked due to RAW dependencies
---
> system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 276 # number of times the wf's instructions are blocked due to RAW dependencies
1241,1242c1241,1242
< system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 3230 # number of cycles the CU issues nothing
< system.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued 128 # number of cycles the CU issued at least one instruction
---
> system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 3261 # number of cycles the CU issues nothing
> system.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued 99 # number of cycles the CU issued at least one instruction
1249,1257c1249,1257
< system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 780 # Number of cycles no instruction of specific type issued
< system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 367 # Number of cycles no instruction of specific type issued
< system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 384 # Number of cycles no instruction of specific type issued
< system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 327 # Number of cycles no instruction of specific type issued
< system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 414 # Number of cycles no instruction of specific type issued
< system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM 30 # Number of cycles no instruction of specific type issued
< system.cpu1.CUs0.ExecStage.spc::samples 3358 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs0.ExecStage.spc::mean 0.041989 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs0.ExecStage.spc::stdev 0.220406 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
---
> system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 769 # Number of cycles no instruction of specific type issued
> system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 357 # Number of cycles no instruction of specific type issued
> system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 375 # Number of cycles no instruction of specific type issued
> system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 332 # Number of cycles no instruction of specific type issued
> system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 398 # Number of cycles no instruction of specific type issued
> system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM 22 # Number of cycles no instruction of specific type issued
> system.cpu1.CUs0.ExecStage.spc::samples 3360 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs0.ExecStage.spc::mean 0.041964 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs0.ExecStage.spc::stdev 0.257708 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1259,1262c1259,1262
< system.cpu1.CUs0.ExecStage.spc::0 3230 96.19% 96.19% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs0.ExecStage.spc::1 116 3.45% 99.64% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs0.ExecStage.spc::2 11 0.33% 99.97% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs0.ExecStage.spc::3 1 0.03% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
---
> system.cpu1.CUs0.ExecStage.spc::0 3261 97.05% 97.05% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs0.ExecStage.spc::1 59 1.76% 98.81% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs0.ExecStage.spc::2 38 1.13% 99.94% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs0.ExecStage.spc::3 2 0.06% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1269,1273c1269,1273
< system.cpu1.CUs0.ExecStage.spc::total 3358 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 82 # number of CU transitions from active to idle
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 82 # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 39.280488 # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 158.161058 # duration of idle periods in cycles
---
> system.cpu1.CUs0.ExecStage.spc::total 3360 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 93 # number of CU transitions from active to idle
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 93 # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 34.967742 # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 149.478110 # duration of idle periods in cycles
1275,1291c1275,1291
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 62 75.61% 75.61% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 9 10.98% 86.59% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 1 1.22% 87.80% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 0 0.00% 87.80% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 2 2.44% 90.24% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.22% 91.46% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 91.46% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 91.46% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 91.46% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 91.46% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 91.46% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 91.46% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 91.46% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 91.46% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 91.46% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 91.46% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 7 8.54% 100.00% # duration of idle periods in cycles
---
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 74 79.57% 79.57% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 7 7.53% 87.10% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 1 1.08% 88.17% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 1 1.08% 89.25% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 2 2.15% 91.40% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.08% 92.47% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 92.47% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 92.47% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 92.47% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 92.47% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 92.47% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 92.47% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 92.47% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 92.47% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 92.47% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 92.47% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 7 7.53% 100.00% # duration of idle periods in cycles
1294c1294
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 82 # duration of idle periods in cycles
---
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 93 # duration of idle periods in cycles
1298,1299c1298,1299
< system.cpu1.CUs0.tlb_cycles -452460956000 # total number of cycles for all uncoalesced requests
< system.cpu1.CUs0.avg_translation_latency -588375755.526658 # Avg. translation latency for data translations
---
> system.cpu1.CUs0.tlb_cycles -452453001000 # total number of cycles for all uncoalesced requests
> system.cpu1.CUs0.avg_translation_latency -588365410.923277 # Avg. translation latency for data translations
1376c1376
< system.cpu1.CUs0.inst_exec_rate::stdev 229.391669 # Instruction Execution Rate: Number of executed vector instructions per cycle
---
> system.cpu1.CUs0.inst_exec_rate::stdev 229.706697 # Instruction Execution Rate: Number of executed vector instructions per cycle
1378,1385c1378,1385
< system.cpu1.CUs0.inst_exec_rate::0-1 1 0.71% 0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs0.inst_exec_rate::2-3 12 8.51% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs0.inst_exec_rate::4-5 51 36.17% 45.39% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs0.inst_exec_rate::6-7 32 22.70% 68.09% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs0.inst_exec_rate::8-9 2 1.42% 69.50% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs0.inst_exec_rate::10 2 1.42% 70.92% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs0.inst_exec_rate::overflows 41 29.08% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs0.inst_exec_rate::min_value 1 # Instruction Execution Rate: Number of executed vector instructions per cycle
---
> system.cpu1.CUs0.inst_exec_rate::0-1 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs0.inst_exec_rate::2-3 12 8.51% 8.51% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs0.inst_exec_rate::4-5 52 36.88% 45.39% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs0.inst_exec_rate::6-7 31 21.99% 67.38% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs0.inst_exec_rate::8-9 3 2.13% 69.50% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs0.inst_exec_rate::10 3 2.13% 71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs0.inst_exec_rate::overflows 40 28.37% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs0.inst_exec_rate::min_value 2 # Instruction Execution Rate: Number of executed vector instructions per cycle
1389,1391c1389,1391
< system.cpu1.CUs0.num_total_cycles 3358 # number of cycles the CU ran for
< system.cpu1.CUs0.vpc 2.015783 # Vector Operations per cycle (this CU only)
< system.cpu1.CUs0.ipc 0.041989 # Instructions per cycle (this CU only)
---
> system.cpu1.CUs0.num_total_cycles 3360 # number of cycles the CU ran for
> system.cpu1.CUs0.vpc 2.014583 # Vector Operations per cycle (this CU only)
> system.cpu1.CUs0.ipc 0.041964 # Instructions per cycle (this CU only)
1471c1471
< system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 381 # number of times the wf's instructions are blocked due to RAW dependencies
---
> system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 401 # number of times the wf's instructions are blocked due to RAW dependencies
1663c1663
< system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 356 # number of times the wf's instructions are blocked due to RAW dependencies
---
> system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 372 # number of times the wf's instructions are blocked due to RAW dependencies
1855c1855
< system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 356 # number of times the wf's instructions are blocked due to RAW dependencies
---
> system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 371 # number of times the wf's instructions are blocked due to RAW dependencies
2047c2047
< system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 339 # number of times the wf's instructions are blocked due to RAW dependencies
---
> system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 361 # number of times the wf's instructions are blocked due to RAW dependencies
2277,2278c2277,2278
< system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 3228 # number of cycles the CU issues nothing
< system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 130 # number of cycles the CU issued at least one instruction
---
> system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 3261 # number of cycles the CU issues nothing
> system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 99 # number of cycles the CU issued at least one instruction
2285c2285
< system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 778 # Number of cycles no instruction of specific type issued
---
> system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 777 # Number of cycles no instruction of specific type issued
2287,2293c2287,2293
< system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 447 # Number of cycles no instruction of specific type issued
< system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 411 # Number of cycles no instruction of specific type issued
< system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 417 # Number of cycles no instruction of specific type issued
< system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM 26 # Number of cycles no instruction of specific type issued
< system.cpu1.CUs1.ExecStage.spc::samples 3358 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs1.ExecStage.spc::mean 0.041989 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs1.ExecStage.spc::stdev 0.217686 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
---
> system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 444 # Number of cycles no instruction of specific type issued
> system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 416 # Number of cycles no instruction of specific type issued
> system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 404 # Number of cycles no instruction of specific type issued
> system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM 22 # Number of cycles no instruction of specific type issued
> system.cpu1.CUs1.ExecStage.spc::samples 3360 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs1.ExecStage.spc::mean 0.041964 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs1.ExecStage.spc::stdev 0.256550 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2295,2297c2295,2297
< system.cpu1.CUs1.ExecStage.spc::0 3228 96.13% 96.13% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs1.ExecStage.spc::1 120 3.57% 99.70% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs1.ExecStage.spc::2 9 0.27% 99.97% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
---
> system.cpu1.CUs1.ExecStage.spc::0 3261 97.05% 97.05% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs1.ExecStage.spc::1 58 1.73% 98.78% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs1.ExecStage.spc::2 40 1.19% 99.97% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2305,2309c2305,2309
< system.cpu1.CUs1.ExecStage.spc::total 3358 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 81 # number of CU transitions from active to idle
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 81 # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 38.617284 # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 158.076213 # duration of idle periods in cycles
---
> system.cpu1.CUs1.ExecStage.spc::total 3360 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 94 # number of CU transitions from active to idle
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 94 # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 33.585106 # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 147.747562 # duration of idle periods in cycles
2311,2327c2311,2327
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 60 74.07% 74.07% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 10 12.35% 86.42% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 86.42% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 2 2.47% 88.89% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 2 2.47% 91.36% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 0 0.00% 91.36% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 91.36% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 91.36% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 91.36% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 91.36% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 91.36% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 91.36% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 91.36% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 91.36% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 91.36% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 91.36% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 7 8.64% 100.00% # duration of idle periods in cycles
---
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 75 79.79% 79.79% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 8 8.51% 88.30% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 88.30% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 1 1.06% 89.36% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 2 2.13% 91.49% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 1 1.06% 92.55% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 92.55% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 92.55% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 92.55% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 92.55% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 92.55% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 92.55% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 92.55% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 92.55% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 92.55% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 92.55% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 7 7.45% 100.00% # duration of idle periods in cycles
2330c2330
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 81 # duration of idle periods in cycles
---
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 94 # duration of idle periods in cycles
2334,2335c2334,2335
< system.cpu1.CUs1.tlb_cycles -452466433000 # total number of cycles for all uncoalesced requests
< system.cpu1.CUs1.avg_translation_latency -588382877.763329 # Avg. translation latency for data translations
---
> system.cpu1.CUs1.tlb_cycles -452459838000 # total number of cycles for all uncoalesced requests
> system.cpu1.CUs1.avg_translation_latency -588374301.690507 # Avg. translation latency for data translations
2411,2412c2411,2412
< system.cpu1.CUs1.inst_exec_rate::mean 85.666667 # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs1.inst_exec_rate::stdev 230.212531 # Instruction Execution Rate: Number of executed vector instructions per cycle
---
> system.cpu1.CUs1.inst_exec_rate::mean 85.553191 # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs1.inst_exec_rate::stdev 230.829913 # Instruction Execution Rate: Number of executed vector instructions per cycle
2414,2415c2414,2415
< system.cpu1.CUs1.inst_exec_rate::0-1 1 0.71% 0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs1.inst_exec_rate::2-3 12 8.51% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle
---
> system.cpu1.CUs1.inst_exec_rate::0-1 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs1.inst_exec_rate::2-3 13 9.22% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle
2418,2421c2418,2421
< system.cpu1.CUs1.inst_exec_rate::8-9 4 2.84% 72.34% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs1.inst_exec_rate::10 1 0.71% 73.05% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs1.inst_exec_rate::overflows 38 26.95% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs1.inst_exec_rate::min_value 1 # Instruction Execution Rate: Number of executed vector instructions per cycle
---
> system.cpu1.CUs1.inst_exec_rate::8-9 6 4.26% 73.76% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs1.inst_exec_rate::10 0 0.00% 73.76% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs1.inst_exec_rate::overflows 37 26.24% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs1.inst_exec_rate::min_value 2 # Instruction Execution Rate: Number of executed vector instructions per cycle
2425,2427c2425,2427
< system.cpu1.CUs1.num_total_cycles 3358 # number of cycles the CU ran for
< system.cpu1.CUs1.vpc 2.013699 # Vector Operations per cycle (this CU only)
< system.cpu1.CUs1.ipc 0.041989 # Instructions per cycle (this CU only)
---
> system.cpu1.CUs1.num_total_cycles 3360 # number of cycles the CU ran for
> system.cpu1.CUs1.vpc 2.012500 # Vector Operations per cycle (this CU only)
> system.cpu1.CUs1.ipc 0.041964 # Instructions per cycle (this CU only)
2662c2662
< system.tcp_cntrl0.L1cache.num_data_array_reads 10 # number of data array reads
---
> system.tcp_cntrl0.L1cache.num_data_array_reads 9 # number of data array reads
2664c2664
< system.tcp_cntrl0.L1cache.num_tag_array_reads 27 # number of tag array reads
---
> system.tcp_cntrl0.L1cache.num_tag_array_reads 26 # number of tag array reads
2666d2665
< system.tcp_cntrl0.L1cache.num_tag_array_stalls 2 # number of stalls caused by tag array
2668c2667
< system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 3 # loads that hit in the TCP
---
> system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 2 # loads that hit in the TCP
2735c2734
< system.sqc_cntrl0.L1cache.num_data_array_stalls 44 # number of stalls caused by data array
---
> system.sqc_cntrl0.L1cache.num_data_array_stalls 47 # number of stalls caused by data array
2758,2761c2757,2760
< system.sqc_coalescer.coalesced_accesses 63 # Number of coalesced TLB accesses
< system.sqc_coalescer.queuing_cycles 100000 # Number of cycles spent in queue
< system.sqc_coalescer.local_queuing_cycles 100000 # Number of cycles spent in queue for all incoming reqs
< system.sqc_coalescer.local_latency 1162.790698 # Avg. latency over all incoming pkts
---
> system.sqc_coalescer.coalesced_accesses 60 # Number of coalesced TLB accesses
> system.sqc_coalescer.queuing_cycles 108000 # Number of cycles spent in queue
> system.sqc_coalescer.local_queuing_cycles 108000 # Number of cycles spent in queue for all incoming reqs
> system.sqc_coalescer.local_latency 1255.813953 # Avg. latency over all incoming pkts
2764,2765c2763,2764
< system.sqc_tlb.local_TLB_accesses 63 # Number of TLB accesses
< system.sqc_tlb.local_TLB_hits 62 # Number of TLB hits
---
> system.sqc_tlb.local_TLB_accesses 60 # Number of TLB accesses
> system.sqc_tlb.local_TLB_hits 59 # Number of TLB hits
2767c2766
< system.sqc_tlb.local_TLB_miss_rate 1.587302 # TLB miss rate
---
> system.sqc_tlb.local_TLB_miss_rate 1.666667 # TLB miss rate
2775,2776c2774,2775
< system.sqc_tlb.local_cycles 63001 # Number of cycles spent in queue for all incoming reqs
< system.sqc_tlb.local_latency 1000.015873 # Avg. latency over incoming coalesced reqs
---
> system.sqc_tlb.local_cycles 60001 # Number of cycles spent in queue for all incoming reqs
> system.sqc_tlb.local_latency 1000.016667 # Avg. latency over incoming coalesced reqs
2900,2901c2899,2900
< system.ruby.Directory_Controller.BS_M.MemData 29 0.00% 0.00%
< system.ruby.Directory_Controller.BM_M.MemData 12 0.00% 0.00%
---
> system.ruby.Directory_Controller.BS_M.MemData 30 0.00% 0.00%
> system.ruby.Directory_Controller.BM_M.MemData 11 0.00% 0.00%
2903,2908c2902,2907
< system.ruby.Directory_Controller.BS_PM.CPUPrbResp 29 0.00% 0.00%
< system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 29 0.00% 0.00%
< system.ruby.Directory_Controller.BS_PM.MemData 1010 0.00% 0.00%
< system.ruby.Directory_Controller.BM_PM.CPUPrbResp 12 0.00% 0.00%
< system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 12 0.00% 0.00%
< system.ruby.Directory_Controller.BM_PM.MemData 323 0.00% 0.00%
---
> system.ruby.Directory_Controller.BS_PM.CPUPrbResp 30 0.00% 0.00%
> system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 30 0.00% 0.00%
> system.ruby.Directory_Controller.BS_PM.MemData 1009 0.00% 0.00%
> system.ruby.Directory_Controller.BM_PM.CPUPrbResp 11 0.00% 0.00%
> system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 11 0.00% 0.00%
> system.ruby.Directory_Controller.BM_PM.MemData 324 0.00% 0.00%
2912,2915c2911,2914
< system.ruby.Directory_Controller.BS_Pm.CPUPrbResp 1010 0.00% 0.00%
< system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 1010 0.00% 0.00%
< system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 323 0.00% 0.00%
< system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 323 0.00% 0.00%
---
> system.ruby.Directory_Controller.BS_Pm.CPUPrbResp 1009 0.00% 0.00%
> system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 1009 0.00% 0.00%
> system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 324 0.00% 0.00%
> system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 324 0.00% 0.00%
2929,2934c2928,2933
< system.ruby.LD.latency_hist_coalsr::samples 10
< system.ruby.LD.latency_hist_coalsr::mean 119.100000
< system.ruby.LD.latency_hist_coalsr::gmean 16.830524
< system.ruby.LD.latency_hist_coalsr::stdev 153.079827
< system.ruby.LD.latency_hist_coalsr | 6 60.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 2 20.00% 80.00% | 0 0.00% 80.00% | 2 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
< system.ruby.LD.latency_hist_coalsr::total 10
---
> system.ruby.LD.latency_hist_coalsr::samples 9
> system.ruby.LD.latency_hist_coalsr::mean 133
> system.ruby.LD.latency_hist_coalsr::gmean 19.809210
> system.ruby.LD.latency_hist_coalsr::stdev 158.221364
> system.ruby.LD.latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 2 22.22% 77.78% | 0 0.00% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
> system.ruby.LD.latency_hist_coalsr::total 9
2953,2958c2952,2957
< system.ruby.LD.miss_latency_hist_coalsr::samples 10
< system.ruby.LD.miss_latency_hist_coalsr::mean 119.100000
< system.ruby.LD.miss_latency_hist_coalsr::gmean 16.830524
< system.ruby.LD.miss_latency_hist_coalsr::stdev 153.079827
< system.ruby.LD.miss_latency_hist_coalsr | 6 60.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 2 20.00% 80.00% | 0 0.00% 80.00% | 2 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
< system.ruby.LD.miss_latency_hist_coalsr::total 10
---
> system.ruby.LD.miss_latency_hist_coalsr::samples 9
> system.ruby.LD.miss_latency_hist_coalsr::mean 133
> system.ruby.LD.miss_latency_hist_coalsr::gmean 19.809210
> system.ruby.LD.miss_latency_hist_coalsr::stdev 158.221364
> system.ruby.LD.miss_latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 2 22.22% 77.78% | 0 0.00% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
> system.ruby.LD.miss_latency_hist_coalsr::total 9
2970,2972c2969,2971
< system.ruby.ST.latency_hist_coalsr::mean 125.375000
< system.ruby.ST.latency_hist_coalsr::gmean 15.803091
< system.ruby.ST.latency_hist_coalsr::stdev 128.466792
---
> system.ruby.ST.latency_hist_coalsr::mean 124.937500
> system.ruby.ST.latency_hist_coalsr::gmean 15.775436
> system.ruby.ST.latency_hist_coalsr::stdev 128.013264
2993,2995c2992,2994
< system.ruby.ST.miss_latency_hist_coalsr::mean 125.375000
< system.ruby.ST.miss_latency_hist_coalsr::gmean 15.803091
< system.ruby.ST.miss_latency_hist_coalsr::stdev 128.466792
---
> system.ruby.ST.miss_latency_hist_coalsr::mean 124.937500
> system.ruby.ST.miss_latency_hist_coalsr::gmean 15.775436
> system.ruby.ST.miss_latency_hist_coalsr::stdev 128.013264
3017c3016
< system.ruby.IFETCH.latency_hist_seqr::mean 4.462093
---
> system.ruby.IFETCH.latency_hist_seqr::mean 4.462070
3019c3018
< system.ruby.IFETCH.latency_hist_seqr::stdev 22.435279
---
> system.ruby.IFETCH.latency_hist_seqr::stdev 22.434900
3025,3027c3024,3026
< system.ruby.IFETCH.hit_latency_hist_seqr::mean 208.444874
< system.ruby.IFETCH.hit_latency_hist_seqr::gmean 207.968565
< system.ruby.IFETCH.hit_latency_hist_seqr::stdev 16.462617
---
> system.ruby.IFETCH.hit_latency_hist_seqr::mean 208.442940
> system.ruby.IFETCH.hit_latency_hist_seqr::gmean 207.967489
> system.ruby.IFETCH.hit_latency_hist_seqr::stdev 16.443135
3105,3107c3104,3106
< system.ruby.Directory.hit_mach_latency_hist_seqr::mean 208.449511
< system.ruby.Directory.hit_mach_latency_hist_seqr::gmean 208.002927
< system.ruby.Directory.hit_mach_latency_hist_seqr::stdev 15.847049
---
> system.ruby.Directory.hit_mach_latency_hist_seqr::mean 208.448208
> system.ruby.Directory.hit_mach_latency_hist_seqr::gmean 208.002202
> system.ruby.Directory.hit_mach_latency_hist_seqr::stdev 15.833423
3113,3115c3112,3114
< system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean 342
< system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 341.902506
< system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 10
---
> system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean 345.333333
> system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 345.301362
> system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 5.773503
3120,3125c3119,3124
< system.ruby.TCP.miss_mach_latency_hist_coalsr::samples 14
< system.ruby.TCP.miss_mach_latency_hist_coalsr::mean 1.714286
< system.ruby.TCP.miss_mach_latency_hist_coalsr::gmean 1.485994
< system.ruby.TCP.miss_mach_latency_hist_coalsr::stdev 1.069045
< system.ruby.TCP.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 8 57.14% 57.14% | 4 28.57% 85.71% | 0 0.00% 85.71% | 2 14.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
< system.ruby.TCP.miss_mach_latency_hist_coalsr::total 14
---
> system.ruby.TCP.miss_mach_latency_hist_coalsr::samples 13
> system.ruby.TCP.miss_mach_latency_hist_coalsr::mean 1.538462
> system.ruby.TCP.miss_mach_latency_hist_coalsr::gmean 1.377009
> system.ruby.TCP.miss_mach_latency_hist_coalsr::stdev 0.877058
> system.ruby.TCP.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 8 61.54% 61.54% | 4 30.77% 92.31% | 0 0.00% 92.31% | 1 7.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
> system.ruby.TCP.miss_mach_latency_hist_coalsr::total 13
3129,3131c3128,3130
< system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 251.454545
< system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 251.396753
< system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 5.733474
---
> system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 250.818182
> system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 250.757089
> system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 5.896070
3159,3161c3158,3159
< system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 337
< system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 336.962906
< system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev 7.071068
---
> system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 342
> system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 342.000000
3166,3171c3164,3169
< system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::samples 6
< system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::mean 2.666667
< system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::gmean 2.519842
< system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::stdev 1.032796
< system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 66.67% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
< system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::total 6
---
> system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::samples 5
> system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::mean 2.400000
> system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::gmean 2.297397
> system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::stdev 0.894427
> system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 80.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
> system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::total 5
3205,3207c3203,3205
< system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 249.750000
< system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 249.737699
< system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 2.659216
---
> system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 248.875000
> system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 248.864382
> system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 2.474874
3243,3245c3241,3243
< system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::mean 208.444874
< system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::gmean 207.968565
< system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::stdev 16.462617
---
> system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::mean 208.442940
> system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::gmean 207.967489
> system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::stdev 16.443135
3281c3279
< system.ruby.TCCdir_Controller.RdBlk 53 0.00% 0.00%
---
> system.ruby.TCCdir_Controller.RdBlk 54 0.00% 0.00%
3316c3314
< system.ruby.TCCdir_Controller.BBB_S.RdBlk 8 0.00% 0.00%
---
> system.ruby.TCCdir_Controller.BBB_S.RdBlk 9 0.00% 0.00%
3320,3321c3318,3319
< system.ruby.TCP_Controller.Load | 5 50.00% 50.00% | 5 50.00% 100.00%
< system.ruby.TCP_Controller.Load::total 10
---
> system.ruby.TCP_Controller.Load | 4 44.44% 44.44% | 5 55.56% 100.00%
> system.ruby.TCP_Controller.Load::total 9
3336,3337c3334,3335
< system.ruby.TCP_Controller.S.Load | 3 50.00% 50.00% | 3 50.00% 100.00%
< system.ruby.TCP_Controller.S.Load::total 6
---
> system.ruby.TCP_Controller.S.Load | 2 40.00% 40.00% | 3 60.00% 100.00%
> system.ruby.TCP_Controller.S.Load::total 5
< host_inst_rate 74039 # Simulator instruction rate (inst/s)
< host_op_rate 152254 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 733530611 # Simulator tick rate (ticks/s)
< host_mem_usage 1301780 # Number of bytes of host memory used
< host_seconds 0.90 # Real time elapsed on the host
---
> host_inst_rate 97803 # Simulator instruction rate (inst/s)
> host_op_rate 201121 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 968968514 # Simulator tick rate (ticks/s)
> host_mem_usage 1290208 # Number of bytes of host memory used
> host_seconds 0.68 # Real time elapsed on the host
90,91c90,91
< system.mem_ctrls.rdQLenPdf::5 3 # What read queue length does an incoming req see
< system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
---
> system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see
> system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see
195,196c195,196
< system.mem_ctrls.totQLat 15500500 # Total ticks spent queuing
< system.mem_ctrls.totMemAccLat 44581750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.mem_ctrls.totQLat 15500495 # Total ticks spent queuing
> system.mem_ctrls.totMemAccLat 44581745 # Total ticks spent from burst creation until serviced by the DRAM
296,301c296,301
< system.ruby.outstanding_req_hist_coalsr::samples 28
< system.ruby.outstanding_req_hist_coalsr::mean 1.642857
< system.ruby.outstanding_req_hist_coalsr::gmean 1.455771
< system.ruby.outstanding_req_hist_coalsr::stdev 0.911421
< system.ruby.outstanding_req_hist_coalsr | 0 0.00% 0.00% | 16 57.14% 57.14% | 8 28.57% 85.71% | 2 7.14% 92.86% | 2 7.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
< system.ruby.outstanding_req_hist_coalsr::total 28
---
> system.ruby.outstanding_req_hist_coalsr::samples 27
> system.ruby.outstanding_req_hist_coalsr::mean 1.629630
> system.ruby.outstanding_req_hist_coalsr::gmean 1.438746
> system.ruby.outstanding_req_hist_coalsr::stdev 0.926040
> system.ruby.outstanding_req_hist_coalsr | 0 0.00% 0.00% | 16 59.26% 59.26% | 7 25.93% 85.19% | 2 7.41% 92.59% | 2 7.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
> system.ruby.outstanding_req_hist_coalsr::total 27
305c305
< system.ruby.latency_hist_seqr::mean 4.784183
---
> system.ruby.latency_hist_seqr::mean 4.784165
307c307
< system.ruby.latency_hist_seqr::stdev 23.846744
---
> system.ruby.latency_hist_seqr::stdev 23.846473
312,317c312,317
< system.ruby.latency_hist_coalsr::samples 28
< system.ruby.latency_hist_coalsr::mean 136.285714
< system.ruby.latency_hist_coalsr::gmean 19.975449
< system.ruby.latency_hist_coalsr::stdev 139.699905
< system.ruby.latency_hist_coalsr | 14 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 10 35.71% 85.71% | 1 3.57% 89.29% | 3 10.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
< system.ruby.latency_hist_coalsr::total 28
---
> system.ruby.latency_hist_coalsr::samples 27
> system.ruby.latency_hist_coalsr::mean 141.296296
> system.ruby.latency_hist_coalsr::gmean 21.202698
> system.ruby.latency_hist_coalsr::stdev 140.217089
> system.ruby.latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 10 37.04% 85.19% | 1 3.70% 88.89% | 3 11.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
> system.ruby.latency_hist_coalsr::total 27
321,323c321,323
< system.ruby.hit_latency_hist_seqr::mean 208.449511
< system.ruby.hit_latency_hist_seqr::gmean 208.002927
< system.ruby.hit_latency_hist_seqr::stdev 15.847049
---
> system.ruby.hit_latency_hist_seqr::mean 208.448208
> system.ruby.hit_latency_hist_seqr::gmean 208.002202
> system.ruby.hit_latency_hist_seqr::stdev 15.833423
336,341c336,341
< system.ruby.miss_latency_hist_coalsr::samples 28
< system.ruby.miss_latency_hist_coalsr::mean 136.285714
< system.ruby.miss_latency_hist_coalsr::gmean 19.975449
< system.ruby.miss_latency_hist_coalsr::stdev 139.699905
< system.ruby.miss_latency_hist_coalsr | 14 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 10 35.71% 85.71% | 1 3.57% 89.29% | 3 10.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
< system.ruby.miss_latency_hist_coalsr::total 28
---
> system.ruby.miss_latency_hist_coalsr::samples 27
> system.ruby.miss_latency_hist_coalsr::mean 141.296296
> system.ruby.miss_latency_hist_coalsr::gmean 21.202698
> system.ruby.miss_latency_hist_coalsr::stdev 140.217089
> system.ruby.miss_latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 10 37.04% 85.19% | 1 3.70% 88.89% | 3 11.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
> system.ruby.miss_latency_hist_coalsr::total 27
391,394c391,394
< system.cpu0.num_idle_cycles 5227.003992 # Number of idle cycles
< system.cpu0.num_busy_cycles 1321681.996008 # Number of busy cycles
< system.cpu0.not_idle_fraction 0.996061 # Percentage of non-idle cycles
< system.cpu0.idle_fraction 0.003939 # Percentage of idle cycles
---
> system.cpu0.num_idle_cycles 5231.003992 # Number of idle cycles
> system.cpu0.num_busy_cycles 1321677.996008 # Number of busy cycles
> system.cpu0.not_idle_fraction 0.996058 # Percentage of non-idle cycles
> system.cpu0.idle_fraction 0.003942 # Percentage of idle cycles
435c435
< system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 297 # number of times the wf's instructions are blocked due to RAW dependencies
---
> system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 307 # number of times the wf's instructions are blocked due to RAW dependencies
627c627
< system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 273 # number of times the wf's instructions are blocked due to RAW dependencies
---
> system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 279 # number of times the wf's instructions are blocked due to RAW dependencies
819c819
< system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 272 # number of times the wf's instructions are blocked due to RAW dependencies
---
> system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 282 # number of times the wf's instructions are blocked due to RAW dependencies
1011c1011
< system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 256 # number of times the wf's instructions are blocked due to RAW dependencies
---
> system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 276 # number of times the wf's instructions are blocked due to RAW dependencies
1241,1242c1241,1242
< system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 3230 # number of cycles the CU issues nothing
< system.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued 128 # number of cycles the CU issued at least one instruction
---
> system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 3261 # number of cycles the CU issues nothing
> system.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued 99 # number of cycles the CU issued at least one instruction
1249,1257c1249,1257
< system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 780 # Number of cycles no instruction of specific type issued
< system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 367 # Number of cycles no instruction of specific type issued
< system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 384 # Number of cycles no instruction of specific type issued
< system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 327 # Number of cycles no instruction of specific type issued
< system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 414 # Number of cycles no instruction of specific type issued
< system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM 30 # Number of cycles no instruction of specific type issued
< system.cpu1.CUs0.ExecStage.spc::samples 3358 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs0.ExecStage.spc::mean 0.041989 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs0.ExecStage.spc::stdev 0.220406 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
---
> system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 769 # Number of cycles no instruction of specific type issued
> system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 357 # Number of cycles no instruction of specific type issued
> system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 375 # Number of cycles no instruction of specific type issued
> system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 332 # Number of cycles no instruction of specific type issued
> system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 398 # Number of cycles no instruction of specific type issued
> system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM 22 # Number of cycles no instruction of specific type issued
> system.cpu1.CUs0.ExecStage.spc::samples 3360 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs0.ExecStage.spc::mean 0.041964 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs0.ExecStage.spc::stdev 0.257708 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1259,1262c1259,1262
< system.cpu1.CUs0.ExecStage.spc::0 3230 96.19% 96.19% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs0.ExecStage.spc::1 116 3.45% 99.64% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs0.ExecStage.spc::2 11 0.33% 99.97% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs0.ExecStage.spc::3 1 0.03% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
---
> system.cpu1.CUs0.ExecStage.spc::0 3261 97.05% 97.05% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs0.ExecStage.spc::1 59 1.76% 98.81% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs0.ExecStage.spc::2 38 1.13% 99.94% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs0.ExecStage.spc::3 2 0.06% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1269,1273c1269,1273
< system.cpu1.CUs0.ExecStage.spc::total 3358 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 82 # number of CU transitions from active to idle
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 82 # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 39.280488 # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 158.161058 # duration of idle periods in cycles
---
> system.cpu1.CUs0.ExecStage.spc::total 3360 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 93 # number of CU transitions from active to idle
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 93 # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 34.967742 # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 149.478110 # duration of idle periods in cycles
1275,1291c1275,1291
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 62 75.61% 75.61% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 9 10.98% 86.59% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 1 1.22% 87.80% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 0 0.00% 87.80% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 2 2.44% 90.24% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.22% 91.46% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 91.46% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 91.46% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 91.46% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 91.46% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 91.46% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 91.46% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 91.46% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 91.46% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 91.46% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 91.46% # duration of idle periods in cycles
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 7 8.54% 100.00% # duration of idle periods in cycles
---
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 74 79.57% 79.57% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 7 7.53% 87.10% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 1 1.08% 88.17% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 1 1.08% 89.25% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 2 2.15% 91.40% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.08% 92.47% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 92.47% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 92.47% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 92.47% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 92.47% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 92.47% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 92.47% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 92.47% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 92.47% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 92.47% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 92.47% # duration of idle periods in cycles
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 7 7.53% 100.00% # duration of idle periods in cycles
1294c1294
< system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 82 # duration of idle periods in cycles
---
> system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 93 # duration of idle periods in cycles
1298,1299c1298,1299
< system.cpu1.CUs0.tlb_cycles -452460956000 # total number of cycles for all uncoalesced requests
< system.cpu1.CUs0.avg_translation_latency -588375755.526658 # Avg. translation latency for data translations
---
> system.cpu1.CUs0.tlb_cycles -452453001000 # total number of cycles for all uncoalesced requests
> system.cpu1.CUs0.avg_translation_latency -588365410.923277 # Avg. translation latency for data translations
1376c1376
< system.cpu1.CUs0.inst_exec_rate::stdev 229.391669 # Instruction Execution Rate: Number of executed vector instructions per cycle
---
> system.cpu1.CUs0.inst_exec_rate::stdev 229.706697 # Instruction Execution Rate: Number of executed vector instructions per cycle
1378,1385c1378,1385
< system.cpu1.CUs0.inst_exec_rate::0-1 1 0.71% 0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs0.inst_exec_rate::2-3 12 8.51% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs0.inst_exec_rate::4-5 51 36.17% 45.39% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs0.inst_exec_rate::6-7 32 22.70% 68.09% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs0.inst_exec_rate::8-9 2 1.42% 69.50% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs0.inst_exec_rate::10 2 1.42% 70.92% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs0.inst_exec_rate::overflows 41 29.08% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs0.inst_exec_rate::min_value 1 # Instruction Execution Rate: Number of executed vector instructions per cycle
---
> system.cpu1.CUs0.inst_exec_rate::0-1 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs0.inst_exec_rate::2-3 12 8.51% 8.51% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs0.inst_exec_rate::4-5 52 36.88% 45.39% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs0.inst_exec_rate::6-7 31 21.99% 67.38% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs0.inst_exec_rate::8-9 3 2.13% 69.50% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs0.inst_exec_rate::10 3 2.13% 71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs0.inst_exec_rate::overflows 40 28.37% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs0.inst_exec_rate::min_value 2 # Instruction Execution Rate: Number of executed vector instructions per cycle
1389,1391c1389,1391
< system.cpu1.CUs0.num_total_cycles 3358 # number of cycles the CU ran for
< system.cpu1.CUs0.vpc 2.015783 # Vector Operations per cycle (this CU only)
< system.cpu1.CUs0.ipc 0.041989 # Instructions per cycle (this CU only)
---
> system.cpu1.CUs0.num_total_cycles 3360 # number of cycles the CU ran for
> system.cpu1.CUs0.vpc 2.014583 # Vector Operations per cycle (this CU only)
> system.cpu1.CUs0.ipc 0.041964 # Instructions per cycle (this CU only)
1471c1471
< system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 381 # number of times the wf's instructions are blocked due to RAW dependencies
---
> system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 401 # number of times the wf's instructions are blocked due to RAW dependencies
1663c1663
< system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 356 # number of times the wf's instructions are blocked due to RAW dependencies
---
> system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 372 # number of times the wf's instructions are blocked due to RAW dependencies
1855c1855
< system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 356 # number of times the wf's instructions are blocked due to RAW dependencies
---
> system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 371 # number of times the wf's instructions are blocked due to RAW dependencies
2047c2047
< system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 339 # number of times the wf's instructions are blocked due to RAW dependencies
---
> system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 361 # number of times the wf's instructions are blocked due to RAW dependencies
2277,2278c2277,2278
< system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 3228 # number of cycles the CU issues nothing
< system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 130 # number of cycles the CU issued at least one instruction
---
> system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 3261 # number of cycles the CU issues nothing
> system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 99 # number of cycles the CU issued at least one instruction
2285c2285
< system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 778 # Number of cycles no instruction of specific type issued
---
> system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 777 # Number of cycles no instruction of specific type issued
2287,2293c2287,2293
< system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 447 # Number of cycles no instruction of specific type issued
< system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 411 # Number of cycles no instruction of specific type issued
< system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 417 # Number of cycles no instruction of specific type issued
< system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM 26 # Number of cycles no instruction of specific type issued
< system.cpu1.CUs1.ExecStage.spc::samples 3358 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs1.ExecStage.spc::mean 0.041989 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs1.ExecStage.spc::stdev 0.217686 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
---
> system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 444 # Number of cycles no instruction of specific type issued
> system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 416 # Number of cycles no instruction of specific type issued
> system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 404 # Number of cycles no instruction of specific type issued
> system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM 22 # Number of cycles no instruction of specific type issued
> system.cpu1.CUs1.ExecStage.spc::samples 3360 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs1.ExecStage.spc::mean 0.041964 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs1.ExecStage.spc::stdev 0.256550 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2295,2297c2295,2297
< system.cpu1.CUs1.ExecStage.spc::0 3228 96.13% 96.13% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs1.ExecStage.spc::1 120 3.57% 99.70% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs1.ExecStage.spc::2 9 0.27% 99.97% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
---
> system.cpu1.CUs1.ExecStage.spc::0 3261 97.05% 97.05% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs1.ExecStage.spc::1 58 1.73% 98.78% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs1.ExecStage.spc::2 40 1.19% 99.97% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2305,2309c2305,2309
< system.cpu1.CUs1.ExecStage.spc::total 3358 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
< system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 81 # number of CU transitions from active to idle
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 81 # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 38.617284 # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 158.076213 # duration of idle periods in cycles
---
> system.cpu1.CUs1.ExecStage.spc::total 3360 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
> system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 94 # number of CU transitions from active to idle
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 94 # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 33.585106 # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 147.747562 # duration of idle periods in cycles
2311,2327c2311,2327
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 60 74.07% 74.07% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 10 12.35% 86.42% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 86.42% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 2 2.47% 88.89% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 2 2.47% 91.36% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 0 0.00% 91.36% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 91.36% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 91.36% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 91.36% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 91.36% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 91.36% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 91.36% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 91.36% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 91.36% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 91.36% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 91.36% # duration of idle periods in cycles
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 7 8.64% 100.00% # duration of idle periods in cycles
---
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 75 79.79% 79.79% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 8 8.51% 88.30% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 88.30% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 1 1.06% 89.36% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 2 2.13% 91.49% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 1 1.06% 92.55% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 92.55% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 92.55% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 92.55% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 92.55% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 92.55% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 92.55% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 92.55% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 92.55% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 92.55% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 92.55% # duration of idle periods in cycles
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 7 7.45% 100.00% # duration of idle periods in cycles
2330c2330
< system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 81 # duration of idle periods in cycles
---
> system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 94 # duration of idle periods in cycles
2334,2335c2334,2335
< system.cpu1.CUs1.tlb_cycles -452466433000 # total number of cycles for all uncoalesced requests
< system.cpu1.CUs1.avg_translation_latency -588382877.763329 # Avg. translation latency for data translations
---
> system.cpu1.CUs1.tlb_cycles -452459838000 # total number of cycles for all uncoalesced requests
> system.cpu1.CUs1.avg_translation_latency -588374301.690507 # Avg. translation latency for data translations
2411,2412c2411,2412
< system.cpu1.CUs1.inst_exec_rate::mean 85.666667 # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs1.inst_exec_rate::stdev 230.212531 # Instruction Execution Rate: Number of executed vector instructions per cycle
---
> system.cpu1.CUs1.inst_exec_rate::mean 85.553191 # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs1.inst_exec_rate::stdev 230.829913 # Instruction Execution Rate: Number of executed vector instructions per cycle
2414,2415c2414,2415
< system.cpu1.CUs1.inst_exec_rate::0-1 1 0.71% 0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs1.inst_exec_rate::2-3 12 8.51% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle
---
> system.cpu1.CUs1.inst_exec_rate::0-1 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs1.inst_exec_rate::2-3 13 9.22% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle
2418,2421c2418,2421
< system.cpu1.CUs1.inst_exec_rate::8-9 4 2.84% 72.34% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs1.inst_exec_rate::10 1 0.71% 73.05% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs1.inst_exec_rate::overflows 38 26.95% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
< system.cpu1.CUs1.inst_exec_rate::min_value 1 # Instruction Execution Rate: Number of executed vector instructions per cycle
---
> system.cpu1.CUs1.inst_exec_rate::8-9 6 4.26% 73.76% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs1.inst_exec_rate::10 0 0.00% 73.76% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs1.inst_exec_rate::overflows 37 26.24% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
> system.cpu1.CUs1.inst_exec_rate::min_value 2 # Instruction Execution Rate: Number of executed vector instructions per cycle
2425,2427c2425,2427
< system.cpu1.CUs1.num_total_cycles 3358 # number of cycles the CU ran for
< system.cpu1.CUs1.vpc 2.013699 # Vector Operations per cycle (this CU only)
< system.cpu1.CUs1.ipc 0.041989 # Instructions per cycle (this CU only)
---
> system.cpu1.CUs1.num_total_cycles 3360 # number of cycles the CU ran for
> system.cpu1.CUs1.vpc 2.012500 # Vector Operations per cycle (this CU only)
> system.cpu1.CUs1.ipc 0.041964 # Instructions per cycle (this CU only)
2662c2662
< system.tcp_cntrl0.L1cache.num_data_array_reads 10 # number of data array reads
---
> system.tcp_cntrl0.L1cache.num_data_array_reads 9 # number of data array reads
2664c2664
< system.tcp_cntrl0.L1cache.num_tag_array_reads 27 # number of tag array reads
---
> system.tcp_cntrl0.L1cache.num_tag_array_reads 26 # number of tag array reads
2666d2665
< system.tcp_cntrl0.L1cache.num_tag_array_stalls 2 # number of stalls caused by tag array
2668c2667
< system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 3 # loads that hit in the TCP
---
> system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 2 # loads that hit in the TCP
2735c2734
< system.sqc_cntrl0.L1cache.num_data_array_stalls 44 # number of stalls caused by data array
---
> system.sqc_cntrl0.L1cache.num_data_array_stalls 47 # number of stalls caused by data array
2758,2761c2757,2760
< system.sqc_coalescer.coalesced_accesses 63 # Number of coalesced TLB accesses
< system.sqc_coalescer.queuing_cycles 100000 # Number of cycles spent in queue
< system.sqc_coalescer.local_queuing_cycles 100000 # Number of cycles spent in queue for all incoming reqs
< system.sqc_coalescer.local_latency 1162.790698 # Avg. latency over all incoming pkts
---
> system.sqc_coalescer.coalesced_accesses 60 # Number of coalesced TLB accesses
> system.sqc_coalescer.queuing_cycles 108000 # Number of cycles spent in queue
> system.sqc_coalescer.local_queuing_cycles 108000 # Number of cycles spent in queue for all incoming reqs
> system.sqc_coalescer.local_latency 1255.813953 # Avg. latency over all incoming pkts
2764,2765c2763,2764
< system.sqc_tlb.local_TLB_accesses 63 # Number of TLB accesses
< system.sqc_tlb.local_TLB_hits 62 # Number of TLB hits
---
> system.sqc_tlb.local_TLB_accesses 60 # Number of TLB accesses
> system.sqc_tlb.local_TLB_hits 59 # Number of TLB hits
2767c2766
< system.sqc_tlb.local_TLB_miss_rate 1.587302 # TLB miss rate
---
> system.sqc_tlb.local_TLB_miss_rate 1.666667 # TLB miss rate
2775,2776c2774,2775
< system.sqc_tlb.local_cycles 63001 # Number of cycles spent in queue for all incoming reqs
< system.sqc_tlb.local_latency 1000.015873 # Avg. latency over incoming coalesced reqs
---
> system.sqc_tlb.local_cycles 60001 # Number of cycles spent in queue for all incoming reqs
> system.sqc_tlb.local_latency 1000.016667 # Avg. latency over incoming coalesced reqs
2900,2901c2899,2900
< system.ruby.Directory_Controller.BS_M.MemData 29 0.00% 0.00%
< system.ruby.Directory_Controller.BM_M.MemData 12 0.00% 0.00%
---
> system.ruby.Directory_Controller.BS_M.MemData 30 0.00% 0.00%
> system.ruby.Directory_Controller.BM_M.MemData 11 0.00% 0.00%
2903,2908c2902,2907
< system.ruby.Directory_Controller.BS_PM.CPUPrbResp 29 0.00% 0.00%
< system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 29 0.00% 0.00%
< system.ruby.Directory_Controller.BS_PM.MemData 1010 0.00% 0.00%
< system.ruby.Directory_Controller.BM_PM.CPUPrbResp 12 0.00% 0.00%
< system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 12 0.00% 0.00%
< system.ruby.Directory_Controller.BM_PM.MemData 323 0.00% 0.00%
---
> system.ruby.Directory_Controller.BS_PM.CPUPrbResp 30 0.00% 0.00%
> system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 30 0.00% 0.00%
> system.ruby.Directory_Controller.BS_PM.MemData 1009 0.00% 0.00%
> system.ruby.Directory_Controller.BM_PM.CPUPrbResp 11 0.00% 0.00%
> system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 11 0.00% 0.00%
> system.ruby.Directory_Controller.BM_PM.MemData 324 0.00% 0.00%
2912,2915c2911,2914
< system.ruby.Directory_Controller.BS_Pm.CPUPrbResp 1010 0.00% 0.00%
< system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 1010 0.00% 0.00%
< system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 323 0.00% 0.00%
< system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 323 0.00% 0.00%
---
> system.ruby.Directory_Controller.BS_Pm.CPUPrbResp 1009 0.00% 0.00%
> system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 1009 0.00% 0.00%
> system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 324 0.00% 0.00%
> system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 324 0.00% 0.00%
2929,2934c2928,2933
< system.ruby.LD.latency_hist_coalsr::samples 10
< system.ruby.LD.latency_hist_coalsr::mean 119.100000
< system.ruby.LD.latency_hist_coalsr::gmean 16.830524
< system.ruby.LD.latency_hist_coalsr::stdev 153.079827
< system.ruby.LD.latency_hist_coalsr | 6 60.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 2 20.00% 80.00% | 0 0.00% 80.00% | 2 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
< system.ruby.LD.latency_hist_coalsr::total 10
---
> system.ruby.LD.latency_hist_coalsr::samples 9
> system.ruby.LD.latency_hist_coalsr::mean 133
> system.ruby.LD.latency_hist_coalsr::gmean 19.809210
> system.ruby.LD.latency_hist_coalsr::stdev 158.221364
> system.ruby.LD.latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 2 22.22% 77.78% | 0 0.00% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
> system.ruby.LD.latency_hist_coalsr::total 9
2953,2958c2952,2957
< system.ruby.LD.miss_latency_hist_coalsr::samples 10
< system.ruby.LD.miss_latency_hist_coalsr::mean 119.100000
< system.ruby.LD.miss_latency_hist_coalsr::gmean 16.830524
< system.ruby.LD.miss_latency_hist_coalsr::stdev 153.079827
< system.ruby.LD.miss_latency_hist_coalsr | 6 60.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 2 20.00% 80.00% | 0 0.00% 80.00% | 2 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
< system.ruby.LD.miss_latency_hist_coalsr::total 10
---
> system.ruby.LD.miss_latency_hist_coalsr::samples 9
> system.ruby.LD.miss_latency_hist_coalsr::mean 133
> system.ruby.LD.miss_latency_hist_coalsr::gmean 19.809210
> system.ruby.LD.miss_latency_hist_coalsr::stdev 158.221364
> system.ruby.LD.miss_latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 2 22.22% 77.78% | 0 0.00% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
> system.ruby.LD.miss_latency_hist_coalsr::total 9
2970,2972c2969,2971
< system.ruby.ST.latency_hist_coalsr::mean 125.375000
< system.ruby.ST.latency_hist_coalsr::gmean 15.803091
< system.ruby.ST.latency_hist_coalsr::stdev 128.466792
---
> system.ruby.ST.latency_hist_coalsr::mean 124.937500
> system.ruby.ST.latency_hist_coalsr::gmean 15.775436
> system.ruby.ST.latency_hist_coalsr::stdev 128.013264
2993,2995c2992,2994
< system.ruby.ST.miss_latency_hist_coalsr::mean 125.375000
< system.ruby.ST.miss_latency_hist_coalsr::gmean 15.803091
< system.ruby.ST.miss_latency_hist_coalsr::stdev 128.466792
---
> system.ruby.ST.miss_latency_hist_coalsr::mean 124.937500
> system.ruby.ST.miss_latency_hist_coalsr::gmean 15.775436
> system.ruby.ST.miss_latency_hist_coalsr::stdev 128.013264
3017c3016
< system.ruby.IFETCH.latency_hist_seqr::mean 4.462093
---
> system.ruby.IFETCH.latency_hist_seqr::mean 4.462070
3019c3018
< system.ruby.IFETCH.latency_hist_seqr::stdev 22.435279
---
> system.ruby.IFETCH.latency_hist_seqr::stdev 22.434900
3025,3027c3024,3026
< system.ruby.IFETCH.hit_latency_hist_seqr::mean 208.444874
< system.ruby.IFETCH.hit_latency_hist_seqr::gmean 207.968565
< system.ruby.IFETCH.hit_latency_hist_seqr::stdev 16.462617
---
> system.ruby.IFETCH.hit_latency_hist_seqr::mean 208.442940
> system.ruby.IFETCH.hit_latency_hist_seqr::gmean 207.967489
> system.ruby.IFETCH.hit_latency_hist_seqr::stdev 16.443135
3105,3107c3104,3106
< system.ruby.Directory.hit_mach_latency_hist_seqr::mean 208.449511
< system.ruby.Directory.hit_mach_latency_hist_seqr::gmean 208.002927
< system.ruby.Directory.hit_mach_latency_hist_seqr::stdev 15.847049
---
> system.ruby.Directory.hit_mach_latency_hist_seqr::mean 208.448208
> system.ruby.Directory.hit_mach_latency_hist_seqr::gmean 208.002202
> system.ruby.Directory.hit_mach_latency_hist_seqr::stdev 15.833423
3113,3115c3112,3114
< system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean 342
< system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 341.902506
< system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 10
---
> system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean 345.333333
> system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 345.301362
> system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 5.773503
3120,3125c3119,3124
< system.ruby.TCP.miss_mach_latency_hist_coalsr::samples 14
< system.ruby.TCP.miss_mach_latency_hist_coalsr::mean 1.714286
< system.ruby.TCP.miss_mach_latency_hist_coalsr::gmean 1.485994
< system.ruby.TCP.miss_mach_latency_hist_coalsr::stdev 1.069045
< system.ruby.TCP.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 8 57.14% 57.14% | 4 28.57% 85.71% | 0 0.00% 85.71% | 2 14.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
< system.ruby.TCP.miss_mach_latency_hist_coalsr::total 14
---
> system.ruby.TCP.miss_mach_latency_hist_coalsr::samples 13
> system.ruby.TCP.miss_mach_latency_hist_coalsr::mean 1.538462
> system.ruby.TCP.miss_mach_latency_hist_coalsr::gmean 1.377009
> system.ruby.TCP.miss_mach_latency_hist_coalsr::stdev 0.877058
> system.ruby.TCP.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 8 61.54% 61.54% | 4 30.77% 92.31% | 0 0.00% 92.31% | 1 7.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
> system.ruby.TCP.miss_mach_latency_hist_coalsr::total 13
3129,3131c3128,3130
< system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 251.454545
< system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 251.396753
< system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 5.733474
---
> system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 250.818182
> system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 250.757089
> system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 5.896070
3159,3161c3158,3159
< system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 337
< system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 336.962906
< system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev 7.071068
---
> system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 342
> system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 342.000000
3166,3171c3164,3169
< system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::samples 6
< system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::mean 2.666667
< system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::gmean 2.519842
< system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::stdev 1.032796
< system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 66.67% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
< system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::total 6
---
> system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::samples 5
> system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::mean 2.400000
> system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::gmean 2.297397
> system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::stdev 0.894427
> system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 80.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
> system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::total 5
3205,3207c3203,3205
< system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 249.750000
< system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 249.737699
< system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 2.659216
---
> system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 248.875000
> system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 248.864382
> system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 2.474874
3243,3245c3241,3243
< system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::mean 208.444874
< system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::gmean 207.968565
< system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::stdev 16.462617
---
> system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::mean 208.442940
> system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::gmean 207.967489
> system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::stdev 16.443135
3281c3279
< system.ruby.TCCdir_Controller.RdBlk 53 0.00% 0.00%
---
> system.ruby.TCCdir_Controller.RdBlk 54 0.00% 0.00%
3316c3314
< system.ruby.TCCdir_Controller.BBB_S.RdBlk 8 0.00% 0.00%
---
> system.ruby.TCCdir_Controller.BBB_S.RdBlk 9 0.00% 0.00%
3320,3321c3318,3319
< system.ruby.TCP_Controller.Load | 5 50.00% 50.00% | 5 50.00% 100.00%
< system.ruby.TCP_Controller.Load::total 10
---
> system.ruby.TCP_Controller.Load | 4 44.44% 44.44% | 5 55.56% 100.00%
> system.ruby.TCP_Controller.Load::total 9
3336,3337c3334,3335
< system.ruby.TCP_Controller.S.Load | 3 50.00% 50.00% | 3 50.00% 100.00%
< system.ruby.TCP_Controller.S.Load::total 6
---
> system.ruby.TCP_Controller.S.Load | 2 40.00% 40.00% | 3 60.00% 100.00%
> system.ruby.TCP_Controller.S.Load::total 5