Cross Reference: /gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU

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stats.txt (11680:b4d943429dc6)	stats.txt (11687:b3d5f0e9e258)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000668 # Number of seconds simulated 4sim_ticks 668137500 # Number of ticks simulated 5final_tick 668137500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000668 # Number of seconds simulated 4sim_ticks 668137500 # Number of ticks simulated 5final_tick 668137500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 112893 # Simulator instruction rate (inst/s) 8host_op_rate 232149 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1126339333 # Simulator tick rate (ticks/s) 10host_mem_usage 1312868 # Number of bytes of host memory used 11host_seconds 0.59 # Real time elapsed on the host	7host_inst_rate 245703 # Simulator instruction rate (inst/s) 8host_op_rate 505252 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2451366703 # Simulator tick rate (ticks/s) 10host_mem_usage 1323744 # Number of bytes of host memory used 11host_seconds 0.27 # Real time elapsed on the host
12sim_insts 66963 # Number of instructions simulated 13sim_ops 137705 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 17system.mem_ctrls.bytes_read::dir_cntrl0 99264 # Number of bytes read from this memory 18system.mem_ctrls.bytes_read::total 99264 # Number of bytes read from this memory 19system.mem_ctrls.num_reads::dir_cntrl0 1551 # Number of read requests responded to by this memory 20system.mem_ctrls.num_reads::total 1551 # Number of read requests responded to by this memory 21system.mem_ctrls.bw_read::dir_cntrl0 148568221 # Total read bandwidth from this memory (bytes/s) 22system.mem_ctrls.bw_read::total 148568221 # Total read bandwidth from this memory (bytes/s) 23system.mem_ctrls.bw_total::dir_cntrl0 148568221 # Total bandwidth to/from this memory (bytes/s) 24system.mem_ctrls.bw_total::total 148568221 # Total bandwidth to/from this memory (bytes/s) 25system.mem_ctrls.readReqs 1551 # Number of read requests accepted 26system.mem_ctrls.writeReqs 0 # Number of write requests accepted 27system.mem_ctrls.readBursts 1551 # Number of DRAM read bursts, including those serviced by the write queue 28system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 29system.mem_ctrls.bytesReadDRAM 99264 # Total number of bytes read from DRAM 30system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue 31system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM 32system.mem_ctrls.bytesReadSys 99264 # Total read bytes from the system interface side 33system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side 34system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 35system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 36system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 37system.mem_ctrls.perBankRdBursts::0 122 # Per bank write bursts 38system.mem_ctrls.perBankRdBursts::1 192 # Per bank write bursts 39system.mem_ctrls.perBankRdBursts::2 93 # Per bank write bursts 40system.mem_ctrls.perBankRdBursts::3 44 # Per bank write bursts 41system.mem_ctrls.perBankRdBursts::4 61 # Per bank write bursts 42system.mem_ctrls.perBankRdBursts::5 79 # Per bank write bursts 43system.mem_ctrls.perBankRdBursts::6 52 # Per bank write bursts 44system.mem_ctrls.perBankRdBursts::7 42 # Per bank write bursts 45system.mem_ctrls.perBankRdBursts::8 54 # Per bank write bursts 46system.mem_ctrls.perBankRdBursts::9 56 # Per bank write bursts 47system.mem_ctrls.perBankRdBursts::10 174 # Per bank write bursts 48system.mem_ctrls.perBankRdBursts::11 90 # Per bank write bursts 49system.mem_ctrls.perBankRdBursts::12 222 # Per bank write bursts 50system.mem_ctrls.perBankRdBursts::13 125 # Per bank write bursts 51system.mem_ctrls.perBankRdBursts::14 51 # Per bank write bursts 52system.mem_ctrls.perBankRdBursts::15 94 # Per bank write bursts 53system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts 54system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts 55system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts 56system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts 57system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts 58system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts 59system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts 60system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts 61system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts 62system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts 63system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts 64system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts 65system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts 66system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts 67system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts 68system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts 69system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry 70system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry 71system.mem_ctrls.totGap 667904000 # Total gap between requests 72system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) 73system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) 74system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) 75system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) 76system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) 77system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) 78system.mem_ctrls.readPktSize::6 1551 # Read request sizes (log2) 79system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) 80system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) 81system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) 82system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) 83system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) 84system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) 85system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) 86system.mem_ctrls.rdQLenPdf::0 1542 # What read queue length does an incoming req see 87system.mem_ctrls.rdQLenPdf::1 2 # What read queue length does an incoming req see 88system.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see 89system.mem_ctrls.rdQLenPdf::3 1 # What read queue length does an incoming req see 90system.mem_ctrls.rdQLenPdf::4 1 # What read queue length does an incoming req see 91system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see 92system.mem_ctrls.rdQLenPdf::6 2 # What read queue length does an incoming req see 93system.mem_ctrls.rdQLenPdf::7 1 # What read queue length does an incoming req see 94system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see 95system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see 96system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see 97system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see 98system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see 99system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see 100system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see 101system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see 102system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see 103system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see 104system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see 105system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see 106system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see 107system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see 108system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see 109system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see 110system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see 111system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see 112system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see 113system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see 114system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see 115system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see 116system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see 117system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see 118system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see 119system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see 120system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see 121system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see 122system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see 123system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see 124system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see 125system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see 126system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see 127system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see 128system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see 129system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see 130system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see 131system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see 132system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see 133system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see 134system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see 135system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see 136system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see 137system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see 138system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see 139system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see 140system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see 141system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see 142system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see 143system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see 144system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see 145system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see 146system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see 147system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see 148system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see 149system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see 150system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see 151system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see 152system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see 153system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see 154system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see 155system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see 156system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see 157system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see 158system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see 159system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see 160system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see 161system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see 162system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see 163system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see 164system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see 165system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see 166system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see 167system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see 168system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see 169system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see 170system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see 171system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see 172system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see 173system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see 174system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see 175system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see 176system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see 177system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see 178system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see 179system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see 180system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see 181system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see 182system.mem_ctrls.bytesPerActivate::samples 484 # Bytes accessed per row activation 183system.mem_ctrls.bytesPerActivate::mean 203.636364 # Bytes accessed per row activation 184system.mem_ctrls.bytesPerActivate::gmean 145.087483 # Bytes accessed per row activation 185system.mem_ctrls.bytesPerActivate::stdev 194.740960 # Bytes accessed per row activation 186system.mem_ctrls.bytesPerActivate::0-127 177 36.57% 36.57% # Bytes accessed per row activation 187system.mem_ctrls.bytesPerActivate::128-255 167 34.50% 71.07% # Bytes accessed per row activation 188system.mem_ctrls.bytesPerActivate::256-383 64 13.22% 84.30% # Bytes accessed per row activation 189system.mem_ctrls.bytesPerActivate::384-511 29 5.99% 90.29% # Bytes accessed per row activation 190system.mem_ctrls.bytesPerActivate::512-639 20 4.13% 94.42% # Bytes accessed per row activation 191system.mem_ctrls.bytesPerActivate::640-767 10 2.07% 96.49% # Bytes accessed per row activation 192system.mem_ctrls.bytesPerActivate::768-895 10 2.07% 98.55% # Bytes accessed per row activation 193system.mem_ctrls.bytesPerActivate::896-1023 2 0.41% 98.97% # Bytes accessed per row activation 194system.mem_ctrls.bytesPerActivate::1024-1151 5 1.03% 100.00% # Bytes accessed per row activation 195system.mem_ctrls.bytesPerActivate::total 484 # Bytes accessed per row activation 196system.mem_ctrls.totQLat 31097995 # Total ticks spent queuing 197system.mem_ctrls.totMemAccLat 60179245 # Total ticks spent from burst creation until serviced by the DRAM 198system.mem_ctrls.totBusLat 7755000 # Total ticks spent in databus transfers 199system.mem_ctrls.avgQLat 20050.29 # Average queueing delay per DRAM burst 200system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst 201system.mem_ctrls.avgMemAccLat 38800.29 # Average memory access latency per DRAM burst 202system.mem_ctrls.avgRdBW 148.57 # Average DRAM read bandwidth in MiByte/s 203system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 204system.mem_ctrls.avgRdBWSys 148.57 # Average system read bandwidth in MiByte/s 205system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 206system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 207system.mem_ctrls.busUtil 1.16 # Data bus utilization in percentage 208system.mem_ctrls.busUtilRead 1.16 # Data bus utilization in percentage for reads 209system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes 210system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing 211system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing 212system.mem_ctrls.readRowHits 1062 # Number of row buffer hits during reads 213system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes 214system.mem_ctrls.readRowHitRate 68.47 # Row buffer hit rate for reads 215system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes 216system.mem_ctrls.avgGap 430627.98 # Average gap between requests 217system.mem_ctrls.pageHitRate 68.47 # Row buffer hit rate, read and write combined 218system.mem_ctrls_0.actEnergy 1320900 # Energy for activate commands per rank (pJ) 219system.mem_ctrls_0.preEnergy 694485 # Energy for precharge commands per rank (pJ) 220system.mem_ctrls_0.readEnergy 4890900 # Energy for read commands per rank (pJ) 221system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) 222system.mem_ctrls_0.refreshEnergy 51629760.000000 # Energy for refresh commands per rank (pJ) 223system.mem_ctrls_0.actBackEnergy 18618480 # Energy for active background per rank (pJ) 224system.mem_ctrls_0.preBackEnergy 1670400 # Energy for precharge background per rank (pJ) 225system.mem_ctrls_0.actPowerDownEnergy 210199470 # Energy for active power-down per rank (pJ) 226system.mem_ctrls_0.prePowerDownEnergy 42511680 # Energy for precharge power-down per rank (pJ) 227system.mem_ctrls_0.selfRefreshEnergy 15622140 # Energy for self refresh per rank (pJ) 228system.mem_ctrls_0.totalEnergy 347158215 # Total energy per rank (pJ) 229system.mem_ctrls_0.averagePower 519.590975 # Core power per rank (mW) 230system.mem_ctrls_0.totalIdleTime 622801252 # Total Idle time Per DRAM Rank 231system.mem_ctrls_0.memoryStateTime::IDLE 2030000 # Time in different power states 232system.mem_ctrls_0.memoryStateTime::REF 21876000 # Time in different power states 233system.mem_ctrls_0.memoryStateTime::SREF 51287000 # Time in different power states 234system.mem_ctrls_0.memoryStateTime::PRE_PDN 110705750 # Time in different power states 235system.mem_ctrls_0.memoryStateTime::ACT 21255248 # Time in different power states 236system.mem_ctrls_0.memoryStateTime::ACT_PDN 460983502 # Time in different power states 237system.mem_ctrls_1.actEnergy 2170560 # Energy for activate commands per rank (pJ) 238system.mem_ctrls_1.preEnergy 1142295 # Energy for precharge commands per rank (pJ) 239system.mem_ctrls_1.readEnergy 6183240 # Energy for read commands per rank (pJ) 240system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) 241system.mem_ctrls_1.refreshEnergy 52244400.000000 # Energy for refresh commands per rank (pJ) 242system.mem_ctrls_1.actBackEnergy 21589320 # Energy for active background per rank (pJ) 243system.mem_ctrls_1.preBackEnergy 1299360 # Energy for precharge background per rank (pJ) 244system.mem_ctrls_1.actPowerDownEnergy 243172830 # Energy for active power-down per rank (pJ) 245system.mem_ctrls_1.prePowerDownEnergy 28283040 # Energy for precharge power-down per rank (pJ) 246system.mem_ctrls_1.selfRefreshEnergy 3067740 # Energy for self refresh per rank (pJ) 247system.mem_ctrls_1.totalEnergy 359152785 # Total energy per rank (pJ) 248system.mem_ctrls_1.averagePower 537.543223 # Core power per rank (mW) 249system.mem_ctrls_1.totalIdleTime 616852750 # Total Idle time Per DRAM Rank 250system.mem_ctrls_1.memoryStateTime::IDLE 980000 # Time in different power states 251system.mem_ctrls_1.memoryStateTime::REF 22106000 # Time in different power states 252system.mem_ctrls_1.memoryStateTime::SREF 10481250 # Time in different power states 253system.mem_ctrls_1.memoryStateTime::PRE_PDN 73643500 # Time in different power states 254system.mem_ctrls_1.memoryStateTime::ACT 27629000 # Time in different power states 255system.mem_ctrls_1.memoryStateTime::ACT_PDN 533297750 # Time in different power states 256system.ruby.clk_domain.clock 500 # Clock period in ticks 257system.ruby.phys_mem.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 258system.ruby.phys_mem.bytes_read::cpu0.inst 696760 # Number of bytes read from this memory 259system.ruby.phys_mem.bytes_read::cpu0.data 119832 # Number of bytes read from this memory 260system.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 3280 # Number of bytes read from this memory 261system.ruby.phys_mem.bytes_read::cpu1.CUs1.ComputeUnit 3280 # Number of bytes read from this memory 262system.ruby.phys_mem.bytes_read::total 823152 # Number of bytes read from this memory 263system.ruby.phys_mem.bytes_inst_read::cpu0.inst 696760 # Number of instructions bytes read from this memory 264system.ruby.phys_mem.bytes_inst_read::cpu1.CUs0.ComputeUnit 2000 # Number of instructions bytes read from this memory 265system.ruby.phys_mem.bytes_inst_read::cpu1.CUs1.ComputeUnit 2000 # Number of instructions bytes read from this memory 266system.ruby.phys_mem.bytes_inst_read::total 700760 # Number of instructions bytes read from this memory 267system.ruby.phys_mem.bytes_written::cpu0.data 72767 # Number of bytes written to this memory 268system.ruby.phys_mem.bytes_written::cpu1.CUs0.ComputeUnit 256 # Number of bytes written to this memory 269system.ruby.phys_mem.bytes_written::cpu1.CUs1.ComputeUnit 256 # Number of bytes written to this memory 270system.ruby.phys_mem.bytes_written::total 73279 # Number of bytes written to this memory 271system.ruby.phys_mem.num_reads::cpu0.inst 87095 # Number of read requests responded to by this memory 272system.ruby.phys_mem.num_reads::cpu0.data 16686 # Number of read requests responded to by this memory 273system.ruby.phys_mem.num_reads::cpu1.CUs0.ComputeUnit 555 # Number of read requests responded to by this memory 274system.ruby.phys_mem.num_reads::cpu1.CUs1.ComputeUnit 555 # Number of read requests responded to by this memory 275system.ruby.phys_mem.num_reads::total 104891 # Number of read requests responded to by this memory 276system.ruby.phys_mem.num_writes::cpu0.data 10422 # Number of write requests responded to by this memory 277system.ruby.phys_mem.num_writes::cpu1.CUs0.ComputeUnit 256 # Number of write requests responded to by this memory 278system.ruby.phys_mem.num_writes::cpu1.CUs1.ComputeUnit 256 # Number of write requests responded to by this memory 279system.ruby.phys_mem.num_writes::total 10934 # Number of write requests responded to by this memory 280system.ruby.phys_mem.bw_read::cpu0.inst 1042839236 # Total read bandwidth from this memory (bytes/s) 281system.ruby.phys_mem.bw_read::cpu0.data 179352304 # Total read bandwidth from this memory (bytes/s) 282system.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit 4909169 # Total read bandwidth from this memory (bytes/s) 283system.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit 4909169 # Total read bandwidth from this memory (bytes/s) 284system.ruby.phys_mem.bw_read::total 1232009878 # Total read bandwidth from this memory (bytes/s) 285system.ruby.phys_mem.bw_inst_read::cpu0.inst 1042839236 # Instruction read bandwidth from this memory (bytes/s) 286system.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit 2993396 # Instruction read bandwidth from this memory (bytes/s) 287system.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit 2993396 # Instruction read bandwidth from this memory (bytes/s) 288system.ruby.phys_mem.bw_inst_read::total 1048826028 # Instruction read bandwidth from this memory (bytes/s) 289system.ruby.phys_mem.bw_write::cpu0.data 108910217 # Write bandwidth from this memory (bytes/s) 290system.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit 383155 # Write bandwidth from this memory (bytes/s) 291system.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit 383155 # Write bandwidth from this memory (bytes/s) 292system.ruby.phys_mem.bw_write::total 109676526 # Write bandwidth from this memory (bytes/s) 293system.ruby.phys_mem.bw_total::cpu0.inst 1042839236 # Total bandwidth to/from this memory (bytes/s) 294system.ruby.phys_mem.bw_total::cpu0.data 288262521 # Total bandwidth to/from this memory (bytes/s) 295system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 5292324 # Total bandwidth to/from this memory (bytes/s) 296system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 5292324 # Total bandwidth to/from this memory (bytes/s) 297system.ruby.phys_mem.bw_total::total 1341686404 # Total bandwidth to/from this memory (bytes/s) 298system.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 299system.ruby.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 300system.ruby.outstanding_req_hist_seqr::bucket_size 1 301system.ruby.outstanding_req_hist_seqr::max_bucket 9 302system.ruby.outstanding_req_hist_seqr::samples 114203 303system.ruby.outstanding_req_hist_seqr::mean 1.000035 304system.ruby.outstanding_req_hist_seqr::gmean 1.000024 305system.ruby.outstanding_req_hist_seqr::stdev 0.005918 306system.ruby.outstanding_req_hist_seqr \| 0 0.00% 0.00% \| 114199 100.00% 100.00% \| 4 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 307system.ruby.outstanding_req_hist_seqr::total 114203 308system.ruby.outstanding_req_hist_coalsr::bucket_size 1 309system.ruby.outstanding_req_hist_coalsr::max_bucket 9 310system.ruby.outstanding_req_hist_coalsr::samples 27 311system.ruby.outstanding_req_hist_coalsr::mean 1.629630 312system.ruby.outstanding_req_hist_coalsr::gmean 1.438746 313system.ruby.outstanding_req_hist_coalsr::stdev 0.926040 314system.ruby.outstanding_req_hist_coalsr \| 0 0.00% 0.00% \| 16 59.26% 59.26% \| 7 25.93% 85.19% \| 2 7.41% 92.59% \| 2 7.41% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 315system.ruby.outstanding_req_hist_coalsr::total 27 316system.ruby.latency_hist_seqr::bucket_size 64 317system.ruby.latency_hist_seqr::max_bucket 639 318system.ruby.latency_hist_seqr::samples 114203 319system.ruby.latency_hist_seqr::mean 4.823332 320system.ruby.latency_hist_seqr::gmean 2.131609 321system.ruby.latency_hist_seqr::stdev 24.449444 322system.ruby.latency_hist_seqr \| 112668 98.66% 98.66% \| 0 0.00% 98.66% \| 0 0.00% 98.66% \| 1490 1.30% 99.96% \| 18 0.02% 99.98% \| 18 0.02% 99.99% \| 2 0.00% 99.99% \| 0 0.00% 99.99% \| 0 0.00% 99.99% \| 7 0.01% 100.00% 323system.ruby.latency_hist_seqr::total 114203 324system.ruby.latency_hist_coalsr::bucket_size 64 325system.ruby.latency_hist_coalsr::max_bucket 639 326system.ruby.latency_hist_coalsr::samples 27 327system.ruby.latency_hist_coalsr::mean 171 328system.ruby.latency_hist_coalsr::gmean 22.942606 329system.ruby.latency_hist_coalsr::stdev 184.818206 330system.ruby.latency_hist_coalsr \| 13 48.15% 48.15% \| 0 0.00% 48.15% \| 0 0.00% 48.15% \| 7 25.93% 74.07% \| 2 7.41% 81.48% \| 1 3.70% 85.19% \| 1 3.70% 88.89% \| 1 3.70% 92.59% \| 2 7.41% 100.00% \| 0 0.00% 100.00% 331system.ruby.latency_hist_coalsr::total 27 332system.ruby.hit_latency_hist_seqr::bucket_size 64 333system.ruby.hit_latency_hist_seqr::max_bucket 639 334system.ruby.hit_latency_hist_seqr::samples 1535 335system.ruby.hit_latency_hist_seqr::mean 211.362215 336system.ruby.hit_latency_hist_seqr::gmean 209.793806 337system.ruby.hit_latency_hist_seqr::stdev 34.965177 338system.ruby.hit_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 1490 97.07% 97.07% \| 18 1.17% 98.24% \| 18 1.17% 99.41% \| 2 0.13% 99.54% \| 0 0.00% 99.54% \| 0 0.00% 99.54% \| 7 0.46% 100.00% 339system.ruby.hit_latency_hist_seqr::total 1535 340system.ruby.miss_latency_hist_seqr::bucket_size 4 341system.ruby.miss_latency_hist_seqr::max_bucket 39 342system.ruby.miss_latency_hist_seqr::samples 112668 343system.ruby.miss_latency_hist_seqr::mean 2.009426 344system.ruby.miss_latency_hist_seqr::gmean 2.002413 345system.ruby.miss_latency_hist_seqr::stdev 0.411800 346system.ruby.miss_latency_hist_seqr \| 112609 99.95% 99.95% \| 0 0.00% 99.95% \| 0 0.00% 99.95% \| 0 0.00% 99.95% \| 0 0.00% 99.95% \| 59 0.05% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 347system.ruby.miss_latency_hist_seqr::total 112668 348system.ruby.miss_latency_hist_coalsr::bucket_size 64 349system.ruby.miss_latency_hist_coalsr::max_bucket 639 350system.ruby.miss_latency_hist_coalsr::samples 27 351system.ruby.miss_latency_hist_coalsr::mean 171 352system.ruby.miss_latency_hist_coalsr::gmean 22.942606 353system.ruby.miss_latency_hist_coalsr::stdev 184.818206 354system.ruby.miss_latency_hist_coalsr \| 13 48.15% 48.15% \| 0 0.00% 48.15% \| 0 0.00% 48.15% \| 7 25.93% 74.07% \| 2 7.41% 81.48% \| 1 3.70% 85.19% \| 1 3.70% 88.89% \| 1 3.70% 92.59% \| 2 7.41% 100.00% \| 0 0.00% 100.00% 355system.ruby.miss_latency_hist_coalsr::total 27 356system.ruby.L1Cache.incomplete_times_seqr 112609 357system.ruby.L2Cache.incomplete_times_seqr 59 358system.cp_cntrl0.L1D0cache.demand_hits 0 # Number of cache demand hits 359system.cp_cntrl0.L1D0cache.demand_misses 506 # Number of cache demand misses 360system.cp_cntrl0.L1D0cache.demand_accesses 506 # Number of cache demand accesses 361system.cp_cntrl0.L1D0cache.num_data_array_reads 16155 # number of data array reads 362system.cp_cntrl0.L1D0cache.num_data_array_writes 11985 # number of data array writes 363system.cp_cntrl0.L1D0cache.num_tag_array_reads 27132 # number of tag array reads 364system.cp_cntrl0.L1D0cache.num_tag_array_writes 1584 # number of tag array writes 365system.cp_cntrl0.L1D1cache.demand_hits 0 # Number of cache demand hits 366system.cp_cntrl0.L1D1cache.demand_misses 0 # Number of cache demand misses 367system.cp_cntrl0.L1D1cache.demand_accesses 0 # Number of cache demand accesses 368system.cp_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits 369system.cp_cntrl0.L1Icache.demand_misses 1088 # Number of cache demand misses 370system.cp_cntrl0.L1Icache.demand_accesses 1088 # Number of cache demand accesses 371system.cp_cntrl0.L1Icache.num_data_array_reads 86007 # number of data array reads 372system.cp_cntrl0.L1Icache.num_data_array_writes 54 # number of data array writes 373system.cp_cntrl0.L1Icache.num_tag_array_reads 87684 # number of tag array reads 374system.cp_cntrl0.L1Icache.num_tag_array_writes 54 # number of tag array writes 375system.cp_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits 376system.cp_cntrl0.L2cache.demand_misses 1535 # Number of cache demand misses 377system.cp_cntrl0.L2cache.demand_accesses 1535 # Number of cache demand accesses 378system.cp_cntrl0.L2cache.num_data_array_reads 120 # number of data array reads 379system.cp_cntrl0.L2cache.num_data_array_writes 11982 # number of data array writes 380system.cp_cntrl0.L2cache.num_tag_array_reads 12059 # number of tag array reads 381system.cp_cntrl0.L2cache.num_tag_array_writes 1649 # number of tag array writes 382system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 383system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 384system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 385system.cpu0.clk_domain.clock 500 # Clock period in ticks 386system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 387system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks 388system.cpu0.interrupts.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 389system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 390system.cpu0.workload.num_syscalls 21 # Number of system calls 391system.cpu0.numPwrStateTransitions 2 # Number of power state transitions 392system.cpu0.pwrStateClkGateDist::samples 1 # Distribution of time spent in the clock gated state 393system.cpu0.pwrStateClkGateDist::mean 2825501 # Distribution of time spent in the clock gated state 394system.cpu0.pwrStateClkGateDist::1000-5e+10 1 100.00% 100.00% # Distribution of time spent in the clock gated state 395system.cpu0.pwrStateClkGateDist::min_value 2825501 # Distribution of time spent in the clock gated state 396system.cpu0.pwrStateClkGateDist::max_value 2825501 # Distribution of time spent in the clock gated state 397system.cpu0.pwrStateClkGateDist::total 1 # Distribution of time spent in the clock gated state 398system.cpu0.pwrStateResidencyTicks::ON 665311999 # Cumulative time (in ticks) in various power states 399system.cpu0.pwrStateResidencyTicks::CLK_GATED 2825501 # Cumulative time (in ticks) in various power states 400system.cpu0.numCycles 1336275 # number of cpu cycles simulated 401system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 402system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 403system.cpu0.committedInsts 66963 # Number of instructions committed 404system.cpu0.committedOps 137705 # Number of ops (including micro ops) committed 405system.cpu0.num_int_alu_accesses 136380 # Number of integer alu accesses 406system.cpu0.num_fp_alu_accesses 1279 # Number of float alu accesses 407system.cpu0.num_func_calls 3196 # number of times a function call or return occured 408system.cpu0.num_conditional_control_insts 12151 # number of instructions that are conditional controls 409system.cpu0.num_int_insts 136380 # number of integer instructions 410system.cpu0.num_fp_insts 1279 # number of float instructions 411system.cpu0.num_int_register_reads 257490 # number of times the integer registers were read 412system.cpu0.num_int_register_writes 110039 # number of times the integer registers were written 413system.cpu0.num_fp_register_reads 1981 # number of times the floating registers were read 414system.cpu0.num_fp_register_writes 981 # number of times the floating registers were written 415system.cpu0.num_cc_register_reads 78262 # number of times the CC registers were read 416system.cpu0.num_cc_register_writes 42183 # number of times the CC registers were written 417system.cpu0.num_mem_refs 27198 # number of memory refs 418system.cpu0.num_load_insts 16684 # Number of load instructions 419system.cpu0.num_store_insts 10514 # Number of store instructions 420system.cpu0.num_idle_cycles 5651.003992 # Number of idle cycles 421system.cpu0.num_busy_cycles 1330623.996008 # Number of busy cycles 422system.cpu0.not_idle_fraction 0.995771 # Percentage of non-idle cycles 423system.cpu0.idle_fraction 0.004229 # Percentage of idle cycles 424system.cpu0.Branches 16199 # Number of branches fetched 425system.cpu0.op_class::No_OpClass 615 0.45% 0.45% # Class of executed instruction 426system.cpu0.op_class::IntAlu 108791 79.00% 79.45% # Class of executed instruction 427system.cpu0.op_class::IntMult 13 0.01% 79.46% # Class of executed instruction 428system.cpu0.op_class::IntDiv 138 0.10% 79.56% # Class of executed instruction 429system.cpu0.op_class::FloatAdd 950 0.69% 80.25% # Class of executed instruction 430system.cpu0.op_class::FloatCmp 0 0.00% 80.25% # Class of executed instruction 431system.cpu0.op_class::FloatCvt 0 0.00% 80.25% # Class of executed instruction 432system.cpu0.op_class::FloatMult 0 0.00% 80.25% # Class of executed instruction	12sim_insts 66963 # Number of instructions simulated 13sim_ops 137705 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 17system.mem_ctrls.bytes_read::dir_cntrl0 99264 # Number of bytes read from this memory 18system.mem_ctrls.bytes_read::total 99264 # Number of bytes read from this memory 19system.mem_ctrls.num_reads::dir_cntrl0 1551 # Number of read requests responded to by this memory 20system.mem_ctrls.num_reads::total 1551 # Number of read requests responded to by this memory 21system.mem_ctrls.bw_read::dir_cntrl0 148568221 # Total read bandwidth from this memory (bytes/s) 22system.mem_ctrls.bw_read::total 148568221 # Total read bandwidth from this memory (bytes/s) 23system.mem_ctrls.bw_total::dir_cntrl0 148568221 # Total bandwidth to/from this memory (bytes/s) 24system.mem_ctrls.bw_total::total 148568221 # Total bandwidth to/from this memory (bytes/s) 25system.mem_ctrls.readReqs 1551 # Number of read requests accepted 26system.mem_ctrls.writeReqs 0 # Number of write requests accepted 27system.mem_ctrls.readBursts 1551 # Number of DRAM read bursts, including those serviced by the write queue 28system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 29system.mem_ctrls.bytesReadDRAM 99264 # Total number of bytes read from DRAM 30system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue 31system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM 32system.mem_ctrls.bytesReadSys 99264 # Total read bytes from the system interface side 33system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side 34system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 35system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 36system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 37system.mem_ctrls.perBankRdBursts::0 122 # Per bank write bursts 38system.mem_ctrls.perBankRdBursts::1 192 # Per bank write bursts 39system.mem_ctrls.perBankRdBursts::2 93 # Per bank write bursts 40system.mem_ctrls.perBankRdBursts::3 44 # Per bank write bursts 41system.mem_ctrls.perBankRdBursts::4 61 # Per bank write bursts 42system.mem_ctrls.perBankRdBursts::5 79 # Per bank write bursts 43system.mem_ctrls.perBankRdBursts::6 52 # Per bank write bursts 44system.mem_ctrls.perBankRdBursts::7 42 # Per bank write bursts 45system.mem_ctrls.perBankRdBursts::8 54 # Per bank write bursts 46system.mem_ctrls.perBankRdBursts::9 56 # Per bank write bursts 47system.mem_ctrls.perBankRdBursts::10 174 # Per bank write bursts 48system.mem_ctrls.perBankRdBursts::11 90 # Per bank write bursts 49system.mem_ctrls.perBankRdBursts::12 222 # Per bank write bursts 50system.mem_ctrls.perBankRdBursts::13 125 # Per bank write bursts 51system.mem_ctrls.perBankRdBursts::14 51 # Per bank write bursts 52system.mem_ctrls.perBankRdBursts::15 94 # Per bank write bursts 53system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts 54system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts 55system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts 56system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts 57system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts 58system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts 59system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts 60system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts 61system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts 62system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts 63system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts 64system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts 65system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts 66system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts 67system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts 68system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts 69system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry 70system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry 71system.mem_ctrls.totGap 667904000 # Total gap between requests 72system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) 73system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) 74system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) 75system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) 76system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) 77system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) 78system.mem_ctrls.readPktSize::6 1551 # Read request sizes (log2) 79system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) 80system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) 81system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) 82system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) 83system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) 84system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) 85system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) 86system.mem_ctrls.rdQLenPdf::0 1542 # What read queue length does an incoming req see 87system.mem_ctrls.rdQLenPdf::1 2 # What read queue length does an incoming req see 88system.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see 89system.mem_ctrls.rdQLenPdf::3 1 # What read queue length does an incoming req see 90system.mem_ctrls.rdQLenPdf::4 1 # What read queue length does an incoming req see 91system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see 92system.mem_ctrls.rdQLenPdf::6 2 # What read queue length does an incoming req see 93system.mem_ctrls.rdQLenPdf::7 1 # What read queue length does an incoming req see 94system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see 95system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see 96system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see 97system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see 98system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see 99system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see 100system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see 101system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see 102system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see 103system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see 104system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see 105system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see 106system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see 107system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see 108system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see 109system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see 110system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see 111system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see 112system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see 113system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see 114system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see 115system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see 116system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see 117system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see 118system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see 119system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see 120system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see 121system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see 122system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see 123system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see 124system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see 125system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see 126system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see 127system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see 128system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see 129system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see 130system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see 131system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see 132system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see 133system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see 134system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see 135system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see 136system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see 137system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see 138system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see 139system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see 140system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see 141system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see 142system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see 143system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see 144system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see 145system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see 146system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see 147system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see 148system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see 149system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see 150system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see 151system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see 152system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see 153system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see 154system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see 155system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see 156system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see 157system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see 158system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see 159system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see 160system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see 161system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see 162system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see 163system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see 164system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see 165system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see 166system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see 167system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see 168system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see 169system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see 170system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see 171system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see 172system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see 173system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see 174system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see 175system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see 176system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see 177system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see 178system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see 179system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see 180system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see 181system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see 182system.mem_ctrls.bytesPerActivate::samples 484 # Bytes accessed per row activation 183system.mem_ctrls.bytesPerActivate::mean 203.636364 # Bytes accessed per row activation 184system.mem_ctrls.bytesPerActivate::gmean 145.087483 # Bytes accessed per row activation 185system.mem_ctrls.bytesPerActivate::stdev 194.740960 # Bytes accessed per row activation 186system.mem_ctrls.bytesPerActivate::0-127 177 36.57% 36.57% # Bytes accessed per row activation 187system.mem_ctrls.bytesPerActivate::128-255 167 34.50% 71.07% # Bytes accessed per row activation 188system.mem_ctrls.bytesPerActivate::256-383 64 13.22% 84.30% # Bytes accessed per row activation 189system.mem_ctrls.bytesPerActivate::384-511 29 5.99% 90.29% # Bytes accessed per row activation 190system.mem_ctrls.bytesPerActivate::512-639 20 4.13% 94.42% # Bytes accessed per row activation 191system.mem_ctrls.bytesPerActivate::640-767 10 2.07% 96.49% # Bytes accessed per row activation 192system.mem_ctrls.bytesPerActivate::768-895 10 2.07% 98.55% # Bytes accessed per row activation 193system.mem_ctrls.bytesPerActivate::896-1023 2 0.41% 98.97% # Bytes accessed per row activation 194system.mem_ctrls.bytesPerActivate::1024-1151 5 1.03% 100.00% # Bytes accessed per row activation 195system.mem_ctrls.bytesPerActivate::total 484 # Bytes accessed per row activation 196system.mem_ctrls.totQLat 31097995 # Total ticks spent queuing 197system.mem_ctrls.totMemAccLat 60179245 # Total ticks spent from burst creation until serviced by the DRAM 198system.mem_ctrls.totBusLat 7755000 # Total ticks spent in databus transfers 199system.mem_ctrls.avgQLat 20050.29 # Average queueing delay per DRAM burst 200system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst 201system.mem_ctrls.avgMemAccLat 38800.29 # Average memory access latency per DRAM burst 202system.mem_ctrls.avgRdBW 148.57 # Average DRAM read bandwidth in MiByte/s 203system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 204system.mem_ctrls.avgRdBWSys 148.57 # Average system read bandwidth in MiByte/s 205system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 206system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 207system.mem_ctrls.busUtil 1.16 # Data bus utilization in percentage 208system.mem_ctrls.busUtilRead 1.16 # Data bus utilization in percentage for reads 209system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes 210system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing 211system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing 212system.mem_ctrls.readRowHits 1062 # Number of row buffer hits during reads 213system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes 214system.mem_ctrls.readRowHitRate 68.47 # Row buffer hit rate for reads 215system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes 216system.mem_ctrls.avgGap 430627.98 # Average gap between requests 217system.mem_ctrls.pageHitRate 68.47 # Row buffer hit rate, read and write combined 218system.mem_ctrls_0.actEnergy 1320900 # Energy for activate commands per rank (pJ) 219system.mem_ctrls_0.preEnergy 694485 # Energy for precharge commands per rank (pJ) 220system.mem_ctrls_0.readEnergy 4890900 # Energy for read commands per rank (pJ) 221system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) 222system.mem_ctrls_0.refreshEnergy 51629760.000000 # Energy for refresh commands per rank (pJ) 223system.mem_ctrls_0.actBackEnergy 18618480 # Energy for active background per rank (pJ) 224system.mem_ctrls_0.preBackEnergy 1670400 # Energy for precharge background per rank (pJ) 225system.mem_ctrls_0.actPowerDownEnergy 210199470 # Energy for active power-down per rank (pJ) 226system.mem_ctrls_0.prePowerDownEnergy 42511680 # Energy for precharge power-down per rank (pJ) 227system.mem_ctrls_0.selfRefreshEnergy 15622140 # Energy for self refresh per rank (pJ) 228system.mem_ctrls_0.totalEnergy 347158215 # Total energy per rank (pJ) 229system.mem_ctrls_0.averagePower 519.590975 # Core power per rank (mW) 230system.mem_ctrls_0.totalIdleTime 622801252 # Total Idle time Per DRAM Rank 231system.mem_ctrls_0.memoryStateTime::IDLE 2030000 # Time in different power states 232system.mem_ctrls_0.memoryStateTime::REF 21876000 # Time in different power states 233system.mem_ctrls_0.memoryStateTime::SREF 51287000 # Time in different power states 234system.mem_ctrls_0.memoryStateTime::PRE_PDN 110705750 # Time in different power states 235system.mem_ctrls_0.memoryStateTime::ACT 21255248 # Time in different power states 236system.mem_ctrls_0.memoryStateTime::ACT_PDN 460983502 # Time in different power states 237system.mem_ctrls_1.actEnergy 2170560 # Energy for activate commands per rank (pJ) 238system.mem_ctrls_1.preEnergy 1142295 # Energy for precharge commands per rank (pJ) 239system.mem_ctrls_1.readEnergy 6183240 # Energy for read commands per rank (pJ) 240system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) 241system.mem_ctrls_1.refreshEnergy 52244400.000000 # Energy for refresh commands per rank (pJ) 242system.mem_ctrls_1.actBackEnergy 21589320 # Energy for active background per rank (pJ) 243system.mem_ctrls_1.preBackEnergy 1299360 # Energy for precharge background per rank (pJ) 244system.mem_ctrls_1.actPowerDownEnergy 243172830 # Energy for active power-down per rank (pJ) 245system.mem_ctrls_1.prePowerDownEnergy 28283040 # Energy for precharge power-down per rank (pJ) 246system.mem_ctrls_1.selfRefreshEnergy 3067740 # Energy for self refresh per rank (pJ) 247system.mem_ctrls_1.totalEnergy 359152785 # Total energy per rank (pJ) 248system.mem_ctrls_1.averagePower 537.543223 # Core power per rank (mW) 249system.mem_ctrls_1.totalIdleTime 616852750 # Total Idle time Per DRAM Rank 250system.mem_ctrls_1.memoryStateTime::IDLE 980000 # Time in different power states 251system.mem_ctrls_1.memoryStateTime::REF 22106000 # Time in different power states 252system.mem_ctrls_1.memoryStateTime::SREF 10481250 # Time in different power states 253system.mem_ctrls_1.memoryStateTime::PRE_PDN 73643500 # Time in different power states 254system.mem_ctrls_1.memoryStateTime::ACT 27629000 # Time in different power states 255system.mem_ctrls_1.memoryStateTime::ACT_PDN 533297750 # Time in different power states 256system.ruby.clk_domain.clock 500 # Clock period in ticks 257system.ruby.phys_mem.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 258system.ruby.phys_mem.bytes_read::cpu0.inst 696760 # Number of bytes read from this memory 259system.ruby.phys_mem.bytes_read::cpu0.data 119832 # Number of bytes read from this memory 260system.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 3280 # Number of bytes read from this memory 261system.ruby.phys_mem.bytes_read::cpu1.CUs1.ComputeUnit 3280 # Number of bytes read from this memory 262system.ruby.phys_mem.bytes_read::total 823152 # Number of bytes read from this memory 263system.ruby.phys_mem.bytes_inst_read::cpu0.inst 696760 # Number of instructions bytes read from this memory 264system.ruby.phys_mem.bytes_inst_read::cpu1.CUs0.ComputeUnit 2000 # Number of instructions bytes read from this memory 265system.ruby.phys_mem.bytes_inst_read::cpu1.CUs1.ComputeUnit 2000 # Number of instructions bytes read from this memory 266system.ruby.phys_mem.bytes_inst_read::total 700760 # Number of instructions bytes read from this memory 267system.ruby.phys_mem.bytes_written::cpu0.data 72767 # Number of bytes written to this memory 268system.ruby.phys_mem.bytes_written::cpu1.CUs0.ComputeUnit 256 # Number of bytes written to this memory 269system.ruby.phys_mem.bytes_written::cpu1.CUs1.ComputeUnit 256 # Number of bytes written to this memory 270system.ruby.phys_mem.bytes_written::total 73279 # Number of bytes written to this memory 271system.ruby.phys_mem.num_reads::cpu0.inst 87095 # Number of read requests responded to by this memory 272system.ruby.phys_mem.num_reads::cpu0.data 16686 # Number of read requests responded to by this memory 273system.ruby.phys_mem.num_reads::cpu1.CUs0.ComputeUnit 555 # Number of read requests responded to by this memory 274system.ruby.phys_mem.num_reads::cpu1.CUs1.ComputeUnit 555 # Number of read requests responded to by this memory 275system.ruby.phys_mem.num_reads::total 104891 # Number of read requests responded to by this memory 276system.ruby.phys_mem.num_writes::cpu0.data 10422 # Number of write requests responded to by this memory 277system.ruby.phys_mem.num_writes::cpu1.CUs0.ComputeUnit 256 # Number of write requests responded to by this memory 278system.ruby.phys_mem.num_writes::cpu1.CUs1.ComputeUnit 256 # Number of write requests responded to by this memory 279system.ruby.phys_mem.num_writes::total 10934 # Number of write requests responded to by this memory 280system.ruby.phys_mem.bw_read::cpu0.inst 1042839236 # Total read bandwidth from this memory (bytes/s) 281system.ruby.phys_mem.bw_read::cpu0.data 179352304 # Total read bandwidth from this memory (bytes/s) 282system.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit 4909169 # Total read bandwidth from this memory (bytes/s) 283system.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit 4909169 # Total read bandwidth from this memory (bytes/s) 284system.ruby.phys_mem.bw_read::total 1232009878 # Total read bandwidth from this memory (bytes/s) 285system.ruby.phys_mem.bw_inst_read::cpu0.inst 1042839236 # Instruction read bandwidth from this memory (bytes/s) 286system.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit 2993396 # Instruction read bandwidth from this memory (bytes/s) 287system.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit 2993396 # Instruction read bandwidth from this memory (bytes/s) 288system.ruby.phys_mem.bw_inst_read::total 1048826028 # Instruction read bandwidth from this memory (bytes/s) 289system.ruby.phys_mem.bw_write::cpu0.data 108910217 # Write bandwidth from this memory (bytes/s) 290system.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit 383155 # Write bandwidth from this memory (bytes/s) 291system.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit 383155 # Write bandwidth from this memory (bytes/s) 292system.ruby.phys_mem.bw_write::total 109676526 # Write bandwidth from this memory (bytes/s) 293system.ruby.phys_mem.bw_total::cpu0.inst 1042839236 # Total bandwidth to/from this memory (bytes/s) 294system.ruby.phys_mem.bw_total::cpu0.data 288262521 # Total bandwidth to/from this memory (bytes/s) 295system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 5292324 # Total bandwidth to/from this memory (bytes/s) 296system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 5292324 # Total bandwidth to/from this memory (bytes/s) 297system.ruby.phys_mem.bw_total::total 1341686404 # Total bandwidth to/from this memory (bytes/s) 298system.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 299system.ruby.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 300system.ruby.outstanding_req_hist_seqr::bucket_size 1 301system.ruby.outstanding_req_hist_seqr::max_bucket 9 302system.ruby.outstanding_req_hist_seqr::samples 114203 303system.ruby.outstanding_req_hist_seqr::mean 1.000035 304system.ruby.outstanding_req_hist_seqr::gmean 1.000024 305system.ruby.outstanding_req_hist_seqr::stdev 0.005918 306system.ruby.outstanding_req_hist_seqr \| 0 0.00% 0.00% \| 114199 100.00% 100.00% \| 4 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 307system.ruby.outstanding_req_hist_seqr::total 114203 308system.ruby.outstanding_req_hist_coalsr::bucket_size 1 309system.ruby.outstanding_req_hist_coalsr::max_bucket 9 310system.ruby.outstanding_req_hist_coalsr::samples 27 311system.ruby.outstanding_req_hist_coalsr::mean 1.629630 312system.ruby.outstanding_req_hist_coalsr::gmean 1.438746 313system.ruby.outstanding_req_hist_coalsr::stdev 0.926040 314system.ruby.outstanding_req_hist_coalsr \| 0 0.00% 0.00% \| 16 59.26% 59.26% \| 7 25.93% 85.19% \| 2 7.41% 92.59% \| 2 7.41% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 315system.ruby.outstanding_req_hist_coalsr::total 27 316system.ruby.latency_hist_seqr::bucket_size 64 317system.ruby.latency_hist_seqr::max_bucket 639 318system.ruby.latency_hist_seqr::samples 114203 319system.ruby.latency_hist_seqr::mean 4.823332 320system.ruby.latency_hist_seqr::gmean 2.131609 321system.ruby.latency_hist_seqr::stdev 24.449444 322system.ruby.latency_hist_seqr \| 112668 98.66% 98.66% \| 0 0.00% 98.66% \| 0 0.00% 98.66% \| 1490 1.30% 99.96% \| 18 0.02% 99.98% \| 18 0.02% 99.99% \| 2 0.00% 99.99% \| 0 0.00% 99.99% \| 0 0.00% 99.99% \| 7 0.01% 100.00% 323system.ruby.latency_hist_seqr::total 114203 324system.ruby.latency_hist_coalsr::bucket_size 64 325system.ruby.latency_hist_coalsr::max_bucket 639 326system.ruby.latency_hist_coalsr::samples 27 327system.ruby.latency_hist_coalsr::mean 171 328system.ruby.latency_hist_coalsr::gmean 22.942606 329system.ruby.latency_hist_coalsr::stdev 184.818206 330system.ruby.latency_hist_coalsr \| 13 48.15% 48.15% \| 0 0.00% 48.15% \| 0 0.00% 48.15% \| 7 25.93% 74.07% \| 2 7.41% 81.48% \| 1 3.70% 85.19% \| 1 3.70% 88.89% \| 1 3.70% 92.59% \| 2 7.41% 100.00% \| 0 0.00% 100.00% 331system.ruby.latency_hist_coalsr::total 27 332system.ruby.hit_latency_hist_seqr::bucket_size 64 333system.ruby.hit_latency_hist_seqr::max_bucket 639 334system.ruby.hit_latency_hist_seqr::samples 1535 335system.ruby.hit_latency_hist_seqr::mean 211.362215 336system.ruby.hit_latency_hist_seqr::gmean 209.793806 337system.ruby.hit_latency_hist_seqr::stdev 34.965177 338system.ruby.hit_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 1490 97.07% 97.07% \| 18 1.17% 98.24% \| 18 1.17% 99.41% \| 2 0.13% 99.54% \| 0 0.00% 99.54% \| 0 0.00% 99.54% \| 7 0.46% 100.00% 339system.ruby.hit_latency_hist_seqr::total 1535 340system.ruby.miss_latency_hist_seqr::bucket_size 4 341system.ruby.miss_latency_hist_seqr::max_bucket 39 342system.ruby.miss_latency_hist_seqr::samples 112668 343system.ruby.miss_latency_hist_seqr::mean 2.009426 344system.ruby.miss_latency_hist_seqr::gmean 2.002413 345system.ruby.miss_latency_hist_seqr::stdev 0.411800 346system.ruby.miss_latency_hist_seqr \| 112609 99.95% 99.95% \| 0 0.00% 99.95% \| 0 0.00% 99.95% \| 0 0.00% 99.95% \| 0 0.00% 99.95% \| 59 0.05% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 347system.ruby.miss_latency_hist_seqr::total 112668 348system.ruby.miss_latency_hist_coalsr::bucket_size 64 349system.ruby.miss_latency_hist_coalsr::max_bucket 639 350system.ruby.miss_latency_hist_coalsr::samples 27 351system.ruby.miss_latency_hist_coalsr::mean 171 352system.ruby.miss_latency_hist_coalsr::gmean 22.942606 353system.ruby.miss_latency_hist_coalsr::stdev 184.818206 354system.ruby.miss_latency_hist_coalsr \| 13 48.15% 48.15% \| 0 0.00% 48.15% \| 0 0.00% 48.15% \| 7 25.93% 74.07% \| 2 7.41% 81.48% \| 1 3.70% 85.19% \| 1 3.70% 88.89% \| 1 3.70% 92.59% \| 2 7.41% 100.00% \| 0 0.00% 100.00% 355system.ruby.miss_latency_hist_coalsr::total 27 356system.ruby.L1Cache.incomplete_times_seqr 112609 357system.ruby.L2Cache.incomplete_times_seqr 59 358system.cp_cntrl0.L1D0cache.demand_hits 0 # Number of cache demand hits 359system.cp_cntrl0.L1D0cache.demand_misses 506 # Number of cache demand misses 360system.cp_cntrl0.L1D0cache.demand_accesses 506 # Number of cache demand accesses 361system.cp_cntrl0.L1D0cache.num_data_array_reads 16155 # number of data array reads 362system.cp_cntrl0.L1D0cache.num_data_array_writes 11985 # number of data array writes 363system.cp_cntrl0.L1D0cache.num_tag_array_reads 27132 # number of tag array reads 364system.cp_cntrl0.L1D0cache.num_tag_array_writes 1584 # number of tag array writes 365system.cp_cntrl0.L1D1cache.demand_hits 0 # Number of cache demand hits 366system.cp_cntrl0.L1D1cache.demand_misses 0 # Number of cache demand misses 367system.cp_cntrl0.L1D1cache.demand_accesses 0 # Number of cache demand accesses 368system.cp_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits 369system.cp_cntrl0.L1Icache.demand_misses 1088 # Number of cache demand misses 370system.cp_cntrl0.L1Icache.demand_accesses 1088 # Number of cache demand accesses 371system.cp_cntrl0.L1Icache.num_data_array_reads 86007 # number of data array reads 372system.cp_cntrl0.L1Icache.num_data_array_writes 54 # number of data array writes 373system.cp_cntrl0.L1Icache.num_tag_array_reads 87684 # number of tag array reads 374system.cp_cntrl0.L1Icache.num_tag_array_writes 54 # number of tag array writes 375system.cp_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits 376system.cp_cntrl0.L2cache.demand_misses 1535 # Number of cache demand misses 377system.cp_cntrl0.L2cache.demand_accesses 1535 # Number of cache demand accesses 378system.cp_cntrl0.L2cache.num_data_array_reads 120 # number of data array reads 379system.cp_cntrl0.L2cache.num_data_array_writes 11982 # number of data array writes 380system.cp_cntrl0.L2cache.num_tag_array_reads 12059 # number of tag array reads 381system.cp_cntrl0.L2cache.num_tag_array_writes 1649 # number of tag array writes 382system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 383system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 384system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 385system.cpu0.clk_domain.clock 500 # Clock period in ticks 386system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 387system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks 388system.cpu0.interrupts.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 389system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 390system.cpu0.workload.num_syscalls 21 # Number of system calls 391system.cpu0.numPwrStateTransitions 2 # Number of power state transitions 392system.cpu0.pwrStateClkGateDist::samples 1 # Distribution of time spent in the clock gated state 393system.cpu0.pwrStateClkGateDist::mean 2825501 # Distribution of time spent in the clock gated state 394system.cpu0.pwrStateClkGateDist::1000-5e+10 1 100.00% 100.00% # Distribution of time spent in the clock gated state 395system.cpu0.pwrStateClkGateDist::min_value 2825501 # Distribution of time spent in the clock gated state 396system.cpu0.pwrStateClkGateDist::max_value 2825501 # Distribution of time spent in the clock gated state 397system.cpu0.pwrStateClkGateDist::total 1 # Distribution of time spent in the clock gated state 398system.cpu0.pwrStateResidencyTicks::ON 665311999 # Cumulative time (in ticks) in various power states 399system.cpu0.pwrStateResidencyTicks::CLK_GATED 2825501 # Cumulative time (in ticks) in various power states 400system.cpu0.numCycles 1336275 # number of cpu cycles simulated 401system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 402system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 403system.cpu0.committedInsts 66963 # Number of instructions committed 404system.cpu0.committedOps 137705 # Number of ops (including micro ops) committed 405system.cpu0.num_int_alu_accesses 136380 # Number of integer alu accesses 406system.cpu0.num_fp_alu_accesses 1279 # Number of float alu accesses 407system.cpu0.num_func_calls 3196 # number of times a function call or return occured 408system.cpu0.num_conditional_control_insts 12151 # number of instructions that are conditional controls 409system.cpu0.num_int_insts 136380 # number of integer instructions 410system.cpu0.num_fp_insts 1279 # number of float instructions 411system.cpu0.num_int_register_reads 257490 # number of times the integer registers were read 412system.cpu0.num_int_register_writes 110039 # number of times the integer registers were written 413system.cpu0.num_fp_register_reads 1981 # number of times the floating registers were read 414system.cpu0.num_fp_register_writes 981 # number of times the floating registers were written 415system.cpu0.num_cc_register_reads 78262 # number of times the CC registers were read 416system.cpu0.num_cc_register_writes 42183 # number of times the CC registers were written 417system.cpu0.num_mem_refs 27198 # number of memory refs 418system.cpu0.num_load_insts 16684 # Number of load instructions 419system.cpu0.num_store_insts 10514 # Number of store instructions 420system.cpu0.num_idle_cycles 5651.003992 # Number of idle cycles 421system.cpu0.num_busy_cycles 1330623.996008 # Number of busy cycles 422system.cpu0.not_idle_fraction 0.995771 # Percentage of non-idle cycles 423system.cpu0.idle_fraction 0.004229 # Percentage of idle cycles 424system.cpu0.Branches 16199 # Number of branches fetched 425system.cpu0.op_class::No_OpClass 615 0.45% 0.45% # Class of executed instruction 426system.cpu0.op_class::IntAlu 108791 79.00% 79.45% # Class of executed instruction 427system.cpu0.op_class::IntMult 13 0.01% 79.46% # Class of executed instruction 428system.cpu0.op_class::IntDiv 138 0.10% 79.56% # Class of executed instruction 429system.cpu0.op_class::FloatAdd 950 0.69% 80.25% # Class of executed instruction 430system.cpu0.op_class::FloatCmp 0 0.00% 80.25% # Class of executed instruction 431system.cpu0.op_class::FloatCvt 0 0.00% 80.25% # Class of executed instruction 432system.cpu0.op_class::FloatMult 0 0.00% 80.25% # Class of executed instruction
	433system.cpu0.op_class::FloatMultAcc 0 0.00% 80.25% # Class of executed instruction
433system.cpu0.op_class::FloatDiv 0 0.00% 80.25% # Class of executed instruction	434system.cpu0.op_class::FloatDiv 0 0.00% 80.25% # Class of executed instruction
	435system.cpu0.op_class::FloatMisc 0 0.00% 80.25% # Class of executed instruction
434system.cpu0.op_class::FloatSqrt 0 0.00% 80.25% # Class of executed instruction 435system.cpu0.op_class::SimdAdd 0 0.00% 80.25% # Class of executed instruction 436system.cpu0.op_class::SimdAddAcc 0 0.00% 80.25% # Class of executed instruction 437system.cpu0.op_class::SimdAlu 0 0.00% 80.25% # Class of executed instruction 438system.cpu0.op_class::SimdCmp 0 0.00% 80.25% # Class of executed instruction 439system.cpu0.op_class::SimdCvt 0 0.00% 80.25% # Class of executed instruction 440system.cpu0.op_class::SimdMisc 0 0.00% 80.25% # Class of executed instruction 441system.cpu0.op_class::SimdMult 0 0.00% 80.25% # Class of executed instruction 442system.cpu0.op_class::SimdMultAcc 0 0.00% 80.25% # Class of executed instruction 443system.cpu0.op_class::SimdShift 0 0.00% 80.25% # Class of executed instruction 444system.cpu0.op_class::SimdShiftAcc 0 0.00% 80.25% # Class of executed instruction 445system.cpu0.op_class::SimdSqrt 0 0.00% 80.25% # Class of executed instruction 446system.cpu0.op_class::SimdFloatAdd 0 0.00% 80.25% # Class of executed instruction 447system.cpu0.op_class::SimdFloatAlu 0 0.00% 80.25% # Class of executed instruction 448system.cpu0.op_class::SimdFloatCmp 0 0.00% 80.25% # Class of executed instruction 449system.cpu0.op_class::SimdFloatCvt 0 0.00% 80.25% # Class of executed instruction 450system.cpu0.op_class::SimdFloatDiv 0 0.00% 80.25% # Class of executed instruction 451system.cpu0.op_class::SimdFloatMisc 0 0.00% 80.25% # Class of executed instruction 452system.cpu0.op_class::SimdFloatMult 0 0.00% 80.25% # Class of executed instruction 453system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 80.25% # Class of executed instruction 454system.cpu0.op_class::SimdFloatSqrt 0 0.00% 80.25% # Class of executed instruction	436system.cpu0.op_class::FloatSqrt 0 0.00% 80.25% # Class of executed instruction 437system.cpu0.op_class::SimdAdd 0 0.00% 80.25% # Class of executed instruction 438system.cpu0.op_class::SimdAddAcc 0 0.00% 80.25% # Class of executed instruction 439system.cpu0.op_class::SimdAlu 0 0.00% 80.25% # Class of executed instruction 440system.cpu0.op_class::SimdCmp 0 0.00% 80.25% # Class of executed instruction 441system.cpu0.op_class::SimdCvt 0 0.00% 80.25% # Class of executed instruction 442system.cpu0.op_class::SimdMisc 0 0.00% 80.25% # Class of executed instruction 443system.cpu0.op_class::SimdMult 0 0.00% 80.25% # Class of executed instruction 444system.cpu0.op_class::SimdMultAcc 0 0.00% 80.25% # Class of executed instruction 445system.cpu0.op_class::SimdShift 0 0.00% 80.25% # Class of executed instruction 446system.cpu0.op_class::SimdShiftAcc 0 0.00% 80.25% # Class of executed instruction 447system.cpu0.op_class::SimdSqrt 0 0.00% 80.25% # Class of executed instruction 448system.cpu0.op_class::SimdFloatAdd 0 0.00% 80.25% # Class of executed instruction 449system.cpu0.op_class::SimdFloatAlu 0 0.00% 80.25% # Class of executed instruction 450system.cpu0.op_class::SimdFloatCmp 0 0.00% 80.25% # Class of executed instruction 451system.cpu0.op_class::SimdFloatCvt 0 0.00% 80.25% # Class of executed instruction 452system.cpu0.op_class::SimdFloatDiv 0 0.00% 80.25% # Class of executed instruction 453system.cpu0.op_class::SimdFloatMisc 0 0.00% 80.25% # Class of executed instruction 454system.cpu0.op_class::SimdFloatMult 0 0.00% 80.25% # Class of executed instruction 455system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 80.25% # Class of executed instruction 456system.cpu0.op_class::SimdFloatSqrt 0 0.00% 80.25% # Class of executed instruction
455system.cpu0.op_class::MemRead 16684 12.12% 92.36% # Class of executed instruction 456system.cpu0.op_class::MemWrite 10514 7.64% 100.00% # Class of executed instruction	457system.cpu0.op_class::MemRead 16382 11.90% 92.15% # Class of executed instruction 458system.cpu0.op_class::MemWrite 10514 7.64% 99.78% # Class of executed instruction 459system.cpu0.op_class::FloatMemRead 302 0.22% 100.00% # Class of executed instruction 460system.cpu0.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
457system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 458system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 459system.cpu0.op_class::total 137705 # Class of executed instruction 460system.cpu1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 461system.cpu1.clk_domain.clock 1000 # Clock period in ticks 462system.cpu1.CUs0.localDataStore.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 463system.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 464system.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 465system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 498 # number of times the wf's instructions are blocked due to RAW dependencies 466system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands 467system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands 468system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands 469system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 470system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands 471system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands 472system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 473system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 474system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 475system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 476system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::total 39 # number of executed instructions with N source register operands 477system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::samples 39 # number of executed instructions with N destination register operands 478system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::mean 0.589744 # number of executed instructions with N destination register operands 479system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::stdev 0.498310 # number of executed instructions with N destination register operands 480system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 481system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00% # number of executed instructions with N destination register operands 482system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 483system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 484system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 485system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 486system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::total 39 # number of executed instructions with N destination register operands 487system.cpu1.CUs0.wavefronts01.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 488system.cpu1.CUs0.wavefronts01.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 489system.cpu1.CUs0.wavefronts01.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 490system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 491system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 492system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 493system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 494system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 495system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 496system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 497system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 498system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 499system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 500system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 501system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 502system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 503system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 504system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 505system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 506system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 507system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 508system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 509system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 510system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 511system.cpu1.CUs0.wavefronts02.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 512system.cpu1.CUs0.wavefronts02.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 513system.cpu1.CUs0.wavefronts02.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 514system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 515system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 516system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 517system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 518system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 519system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 520system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 521system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 522system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 523system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 524system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 525system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 526system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 527system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 528system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 529system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 530system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 531system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 532system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 533system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 534system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 535system.cpu1.CUs0.wavefronts03.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 536system.cpu1.CUs0.wavefronts03.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 537system.cpu1.CUs0.wavefronts03.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 538system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 539system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 540system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 541system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 542system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 543system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 544system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 545system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 546system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 547system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 548system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 549system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 550system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 551system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 552system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 553system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 554system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 555system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 556system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 557system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 558system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 559system.cpu1.CUs0.wavefronts04.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 560system.cpu1.CUs0.wavefronts04.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 561system.cpu1.CUs0.wavefronts04.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 562system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 563system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 564system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 565system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 566system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 567system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 568system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 569system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 570system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 571system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 572system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 573system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 574system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 575system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 576system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 577system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 578system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 579system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 580system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 581system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 582system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 583system.cpu1.CUs0.wavefronts05.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 584system.cpu1.CUs0.wavefronts05.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 585system.cpu1.CUs0.wavefronts05.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 586system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 587system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 588system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 589system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 590system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 591system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 592system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 593system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 594system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 595system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 596system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 597system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 598system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 599system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 600system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 601system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 602system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 603system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 604system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 605system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 606system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 607system.cpu1.CUs0.wavefronts06.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 608system.cpu1.CUs0.wavefronts06.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 609system.cpu1.CUs0.wavefronts06.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 610system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 611system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 612system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 613system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 614system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 615system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 616system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 617system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 618system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 619system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 620system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 621system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 622system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 623system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 624system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 625system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 626system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 627system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 628system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 629system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 630system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 631system.cpu1.CUs0.wavefronts07.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 632system.cpu1.CUs0.wavefronts07.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 633system.cpu1.CUs0.wavefronts07.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 634system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 635system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 636system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 637system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 638system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 639system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 640system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 641system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 642system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 643system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 644system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 645system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 646system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 647system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 648system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 649system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 650system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 651system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 652system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 653system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 654system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 655system.cpu1.CUs0.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 656system.cpu1.CUs0.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 657system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 470 # number of times the wf's instructions are blocked due to RAW dependencies 658system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 659system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 660system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 661system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 662system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 663system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 664system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 665system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 666system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 667system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 668system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 669system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 670system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 671system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 672system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 673system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 674system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 675system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 676system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 677system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 678system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 679system.cpu1.CUs0.wavefronts09.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 680system.cpu1.CUs0.wavefronts09.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 681system.cpu1.CUs0.wavefronts09.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 682system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 683system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 684system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 685system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 686system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 687system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 688system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 689system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 690system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 691system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 692system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 693system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 694system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 695system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 696system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 697system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 698system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 699system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 700system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 701system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 702system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 703system.cpu1.CUs0.wavefronts10.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 704system.cpu1.CUs0.wavefronts10.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 705system.cpu1.CUs0.wavefronts10.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 706system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 707system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 708system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 709system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 710system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 711system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 712system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 713system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 714system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 715system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 716system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 717system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 718system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 719system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 720system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 721system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 722system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 723system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 724system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 725system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 726system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 727system.cpu1.CUs0.wavefronts11.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 728system.cpu1.CUs0.wavefronts11.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 729system.cpu1.CUs0.wavefronts11.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 730system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 731system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 732system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 733system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 734system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 735system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 736system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 737system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 738system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 739system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 740system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 741system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 742system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 743system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 744system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 745system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 746system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 747system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 748system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 749system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 750system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 751system.cpu1.CUs0.wavefronts12.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 752system.cpu1.CUs0.wavefronts12.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 753system.cpu1.CUs0.wavefronts12.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 754system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 755system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 756system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 757system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 758system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 759system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 760system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 761system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 762system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 763system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 764system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 765system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 766system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 767system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 768system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 769system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 770system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 771system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 772system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 773system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 774system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 775system.cpu1.CUs0.wavefronts13.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 776system.cpu1.CUs0.wavefronts13.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 777system.cpu1.CUs0.wavefronts13.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 778system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 779system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 780system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 781system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 782system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 783system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 784system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 785system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 786system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 787system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 788system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 789system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 790system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 791system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 792system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 793system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 794system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 795system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 796system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 797system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 798system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 799system.cpu1.CUs0.wavefronts14.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 800system.cpu1.CUs0.wavefronts14.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 801system.cpu1.CUs0.wavefronts14.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 802system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 803system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 804system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 805system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 806system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 807system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 808system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 809system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 810system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 811system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 812system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 813system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 814system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 815system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 816system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 817system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 818system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 819system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 820system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 821system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 822system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 823system.cpu1.CUs0.wavefronts15.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 824system.cpu1.CUs0.wavefronts15.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 825system.cpu1.CUs0.wavefronts15.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 826system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 827system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 828system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 829system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 830system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 831system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 832system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 833system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 834system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 835system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 836system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 837system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 838system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 839system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 840system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 841system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 842system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 843system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 844system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 845system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 846system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 847system.cpu1.CUs0.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 848system.cpu1.CUs0.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 849system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 473 # number of times the wf's instructions are blocked due to RAW dependencies 850system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 851system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 852system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 853system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 854system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 855system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 856system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 857system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 858system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 859system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 860system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 861system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 862system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 863system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 864system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 865system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 866system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 867system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 868system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 869system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 870system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 871system.cpu1.CUs0.wavefronts17.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 872system.cpu1.CUs0.wavefronts17.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 873system.cpu1.CUs0.wavefronts17.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 874system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 875system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 876system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 877system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 878system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 879system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 880system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 881system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 882system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 883system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 884system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 885system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 886system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 887system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 888system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 889system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 890system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 891system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 892system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 893system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 894system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 895system.cpu1.CUs0.wavefronts18.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 896system.cpu1.CUs0.wavefronts18.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 897system.cpu1.CUs0.wavefronts18.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 898system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 899system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 900system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 901system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 902system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 903system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 904system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 905system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 906system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 907system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 908system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 909system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 910system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 911system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 912system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 913system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 914system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 915system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 916system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 917system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 918system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 919system.cpu1.CUs0.wavefronts19.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 920system.cpu1.CUs0.wavefronts19.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 921system.cpu1.CUs0.wavefronts19.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 922system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 923system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 924system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 925system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 926system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 927system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 928system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 929system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 930system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 931system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 932system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 933system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 934system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 935system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 936system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 937system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 938system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 939system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 940system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 941system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 942system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 943system.cpu1.CUs0.wavefronts20.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 944system.cpu1.CUs0.wavefronts20.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 945system.cpu1.CUs0.wavefronts20.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 946system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 947system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 948system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 949system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 950system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 951system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 952system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 953system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 954system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 955system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 956system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 957system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 958system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 959system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 960system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 961system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 962system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 963system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 964system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 965system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 966system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 967system.cpu1.CUs0.wavefronts21.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 968system.cpu1.CUs0.wavefronts21.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 969system.cpu1.CUs0.wavefronts21.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 970system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 971system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 972system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 973system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 974system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 975system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 976system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 977system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 978system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 979system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 980system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 981system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 982system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 983system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 984system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 985system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 986system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 987system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 988system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 989system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 990system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 991system.cpu1.CUs0.wavefronts22.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 992system.cpu1.CUs0.wavefronts22.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 993system.cpu1.CUs0.wavefronts22.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 994system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 995system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 996system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 997system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 998system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 999system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1000system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1001system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1002system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1003system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1004system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1005system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1006system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1007system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1008system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1009system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1010system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1011system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1012system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1013system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1014system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1015system.cpu1.CUs0.wavefronts23.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1016system.cpu1.CUs0.wavefronts23.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1017system.cpu1.CUs0.wavefronts23.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1018system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1019system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1020system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1021system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1022system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1023system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1024system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1025system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1026system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1027system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1028system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1029system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1030system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1031system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1032system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1033system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1034system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1035system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1036system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1037system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1038system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1039system.cpu1.CUs0.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1040system.cpu1.CUs0.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1041system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 467 # number of times the wf's instructions are blocked due to RAW dependencies 1042system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 1043system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 1044system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 1045system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 1046system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 1047system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 1048system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 1049system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 1050system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1051system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 1052system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 1053system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 1054system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 1055system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 1056system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 1057system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 1058system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 1059system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 1060system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1061system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 1062system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 1063system.cpu1.CUs0.wavefronts25.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1064system.cpu1.CUs0.wavefronts25.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1065system.cpu1.CUs0.wavefronts25.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1066system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1067system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1068system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1069system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1070system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1071system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1072system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1073system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1074system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1075system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1076system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1077system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1078system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1079system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1080system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1081system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1082system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1083system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1084system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1085system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1086system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1087system.cpu1.CUs0.wavefronts26.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1088system.cpu1.CUs0.wavefronts26.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1089system.cpu1.CUs0.wavefronts26.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1090system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1091system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1092system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1093system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1094system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1095system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1096system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1097system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1098system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1099system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1100system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1101system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1102system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1103system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1104system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1105system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1106system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1107system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1108system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1109system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1110system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1111system.cpu1.CUs0.wavefronts27.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1112system.cpu1.CUs0.wavefronts27.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1113system.cpu1.CUs0.wavefronts27.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1114system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1115system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1116system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1117system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1118system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1119system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1120system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1121system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1122system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1123system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1124system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1125system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1126system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1127system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1128system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1129system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1130system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1131system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1132system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1133system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1134system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1135system.cpu1.CUs0.wavefronts28.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1136system.cpu1.CUs0.wavefronts28.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1137system.cpu1.CUs0.wavefronts28.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1138system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1139system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1140system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1141system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1142system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1143system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1144system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1145system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1146system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1147system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1148system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1149system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1150system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1151system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1152system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1153system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1154system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1155system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1156system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1157system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1158system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1159system.cpu1.CUs0.wavefronts29.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1160system.cpu1.CUs0.wavefronts29.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1161system.cpu1.CUs0.wavefronts29.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1162system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1163system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1164system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1165system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1166system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1167system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1168system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1169system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1170system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1171system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1172system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1173system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1174system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1175system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1176system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1177system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1178system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1179system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1180system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1181system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1182system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1183system.cpu1.CUs0.wavefronts30.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1184system.cpu1.CUs0.wavefronts30.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1185system.cpu1.CUs0.wavefronts30.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1186system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1187system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1188system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1189system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1190system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1191system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1192system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1193system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1194system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1195system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1196system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1197system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1198system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1199system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1200system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1201system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1202system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1203system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1204system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1205system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1206system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1207system.cpu1.CUs0.wavefronts31.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1208system.cpu1.CUs0.wavefronts31.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1209system.cpu1.CUs0.wavefronts31.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1210system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1211system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1212system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1213system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1214system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1215system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1216system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1217system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1218system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1219system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1220system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1221system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1222system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1223system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1224system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1225system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1226system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1227system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1228system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1229system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1230system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1231system.cpu1.CUs0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 1232system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it 1233system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it 1234system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it 1235system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 1236system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 1237system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it 1238system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it 1239system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it 1240system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it 1241system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it 1242system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it 1243system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1244system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1245system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1246system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1247system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1248system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1249system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1250system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1251system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1252system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1253system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1254system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1255system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1256system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1257system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1258system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1259system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1260system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1261system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1262system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1263system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1264system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1265system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1266system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1267system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1268system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1269system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it 1270system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it 1271system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it 1272system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 3471 # number of cycles the CU issues nothing 1273system.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued 99 # number of cycles the CU issued at least one instruction 1274system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued 1275system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued 1276system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued 1277system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued 1278system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued 1279system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued 1280system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 970 # Number of cycles no instruction of specific type issued 1281system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 548 # Number of cycles no instruction of specific type issued 1282system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 566 # Number of cycles no instruction of specific type issued 1283system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 523 # Number of cycles no instruction of specific type issued 1284system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 398 # Number of cycles no instruction of specific type issued 1285system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM 22 # Number of cycles no instruction of specific type issued 1286system.cpu1.CUs0.ExecStage.spc::samples 3570 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1287system.cpu1.CUs0.ExecStage.spc::mean 0.039496 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1288system.cpu1.CUs0.ExecStage.spc::stdev 0.250206 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1289system.cpu1.CUs0.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1290system.cpu1.CUs0.ExecStage.spc::0 3471 97.23% 97.23% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1291system.cpu1.CUs0.ExecStage.spc::1 59 1.65% 98.88% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1292system.cpu1.CUs0.ExecStage.spc::2 38 1.06% 99.94% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1293system.cpu1.CUs0.ExecStage.spc::3 2 0.06% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1294system.cpu1.CUs0.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1295system.cpu1.CUs0.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1296system.cpu1.CUs0.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1297system.cpu1.CUs0.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1298system.cpu1.CUs0.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1299system.cpu1.CUs0.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1300system.cpu1.CUs0.ExecStage.spc::total 3570 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1301system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 93 # number of CU transitions from active to idle 1302system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 93 # duration of idle periods in cycles 1303system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 37.225806 # duration of idle periods in cycles 1304system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 154.644552 # duration of idle periods in cycles 1305system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles 1306system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 74 79.57% 79.57% # duration of idle periods in cycles 1307system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 7 7.53% 87.10% # duration of idle periods in cycles 1308system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 1 1.08% 88.17% # duration of idle periods in cycles 1309system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 1 1.08% 89.25% # duration of idle periods in cycles 1310system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 2 2.15% 91.40% # duration of idle periods in cycles 1311system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.08% 92.47% # duration of idle periods in cycles 1312system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 92.47% # duration of idle periods in cycles 1313system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 92.47% # duration of idle periods in cycles 1314system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 92.47% # duration of idle periods in cycles 1315system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 92.47% # duration of idle periods in cycles 1316system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 92.47% # duration of idle periods in cycles 1317system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 92.47% # duration of idle periods in cycles 1318system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 92.47% # duration of idle periods in cycles 1319system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 92.47% # duration of idle periods in cycles 1320system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 92.47% # duration of idle periods in cycles 1321system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 92.47% # duration of idle periods in cycles 1322system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 7 7.53% 100.00% # duration of idle periods in cycles 1323system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles 1324system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::max_value 1291 # duration of idle periods in cycles 1325system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 93 # duration of idle periods in cycles 1326system.cpu1.CUs0.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF 1327system.cpu1.CUs0.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF 1328system.cpu1.CUs0.tlb_requests 769 # number of uncoalesced requests 1329system.cpu1.CUs0.tlb_cycles -455223738000 # total number of cycles for all uncoalesced requests 1330system.cpu1.CUs0.avg_translation_latency -591968449.934981 # Avg. translation latency for data translations 1331system.cpu1.CUs0.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB 1332system.cpu1.CUs0.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 1333system.cpu1.CUs0.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 1334system.cpu1.CUs0.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 1335system.cpu1.CUs0.lds_bank_access_cnt 54 # Total number of LDS bank accesses 1336system.cpu1.CUs0.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet 1337system.cpu1.CUs0.lds_bank_conflicts::mean 8 # Number of bank conflicts per LDS memory packet 1338system.cpu1.CUs0.lds_bank_conflicts::stdev 6.196773 # Number of bank conflicts per LDS memory packet 1339system.cpu1.CUs0.lds_bank_conflicts::underflows 0 0.00% 0.00% # Number of bank conflicts per LDS memory packet 1340system.cpu1.CUs0.lds_bank_conflicts::0-1 2 33.33% 33.33% # Number of bank conflicts per LDS memory packet 1341system.cpu1.CUs0.lds_bank_conflicts::2-3 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 1342system.cpu1.CUs0.lds_bank_conflicts::4-5 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 1343system.cpu1.CUs0.lds_bank_conflicts::6-7 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 1344system.cpu1.CUs0.lds_bank_conflicts::8-9 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 1345system.cpu1.CUs0.lds_bank_conflicts::10-11 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 1346system.cpu1.CUs0.lds_bank_conflicts::12-13 4 66.67% 100.00% # Number of bank conflicts per LDS memory packet 1347system.cpu1.CUs0.lds_bank_conflicts::14-15 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1348system.cpu1.CUs0.lds_bank_conflicts::16-17 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1349system.cpu1.CUs0.lds_bank_conflicts::18-19 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1350system.cpu1.CUs0.lds_bank_conflicts::20-21 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1351system.cpu1.CUs0.lds_bank_conflicts::22-23 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1352system.cpu1.CUs0.lds_bank_conflicts::24-25 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1353system.cpu1.CUs0.lds_bank_conflicts::26-27 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1354system.cpu1.CUs0.lds_bank_conflicts::28-29 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1355system.cpu1.CUs0.lds_bank_conflicts::30-31 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1356system.cpu1.CUs0.lds_bank_conflicts::32-33 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1357system.cpu1.CUs0.lds_bank_conflicts::34-35 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1358system.cpu1.CUs0.lds_bank_conflicts::36-37 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1359system.cpu1.CUs0.lds_bank_conflicts::38-39 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1360system.cpu1.CUs0.lds_bank_conflicts::40-41 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1361system.cpu1.CUs0.lds_bank_conflicts::42-43 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1362system.cpu1.CUs0.lds_bank_conflicts::44-45 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1363system.cpu1.CUs0.lds_bank_conflicts::46-47 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1364system.cpu1.CUs0.lds_bank_conflicts::48-49 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1365system.cpu1.CUs0.lds_bank_conflicts::50-51 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1366system.cpu1.CUs0.lds_bank_conflicts::52-53 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1367system.cpu1.CUs0.lds_bank_conflicts::54-55 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1368system.cpu1.CUs0.lds_bank_conflicts::56-57 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1369system.cpu1.CUs0.lds_bank_conflicts::58-59 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1370system.cpu1.CUs0.lds_bank_conflicts::60-61 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1371system.cpu1.CUs0.lds_bank_conflicts::62-63 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1372system.cpu1.CUs0.lds_bank_conflicts::64 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1373system.cpu1.CUs0.lds_bank_conflicts::overflows 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1374system.cpu1.CUs0.lds_bank_conflicts::min_value 0 # Number of bank conflicts per LDS memory packet 1375system.cpu1.CUs0.lds_bank_conflicts::max_value 12 # Number of bank conflicts per LDS memory packet 1376system.cpu1.CUs0.lds_bank_conflicts::total 6 # Number of bank conflicts per LDS memory packet 1377system.cpu1.CUs0.page_divergence_dist::samples 17 # pages touched per wf (over all mem. instr.) 1378system.cpu1.CUs0.page_divergence_dist::mean 1 # pages touched per wf (over all mem. instr.) 1379system.cpu1.CUs0.page_divergence_dist::stdev 0 # pages touched per wf (over all mem. instr.) 1380system.cpu1.CUs0.page_divergence_dist::underflows 0 0.00% 0.00% # pages touched per wf (over all mem. instr.) 1381system.cpu1.CUs0.page_divergence_dist::1-4 17 100.00% 100.00% # pages touched per wf (over all mem. instr.) 1382system.cpu1.CUs0.page_divergence_dist::5-8 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1383system.cpu1.CUs0.page_divergence_dist::9-12 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1384system.cpu1.CUs0.page_divergence_dist::13-16 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1385system.cpu1.CUs0.page_divergence_dist::17-20 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1386system.cpu1.CUs0.page_divergence_dist::21-24 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1387system.cpu1.CUs0.page_divergence_dist::25-28 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1388system.cpu1.CUs0.page_divergence_dist::29-32 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1389system.cpu1.CUs0.page_divergence_dist::33-36 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1390system.cpu1.CUs0.page_divergence_dist::37-40 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1391system.cpu1.CUs0.page_divergence_dist::41-44 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1392system.cpu1.CUs0.page_divergence_dist::45-48 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1393system.cpu1.CUs0.page_divergence_dist::49-52 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1394system.cpu1.CUs0.page_divergence_dist::53-56 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1395system.cpu1.CUs0.page_divergence_dist::57-60 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1396system.cpu1.CUs0.page_divergence_dist::61-64 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1397system.cpu1.CUs0.page_divergence_dist::overflows 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1398system.cpu1.CUs0.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.) 1399system.cpu1.CUs0.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.) 1400system.cpu1.CUs0.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.) 1401system.cpu1.CUs0.global_mem_instr_cnt 17 # dynamic global memory instructions count 1402system.cpu1.CUs0.local_mem_instr_cnt 6 # dynamic local memory intruction count 1403system.cpu1.CUs0.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity 1404system.cpu1.CUs0.num_instr_executed 141 # number of instructions executed 1405system.cpu1.CUs0.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle 1406system.cpu1.CUs0.inst_exec_rate::mean 92.127660 # Instruction Execution Rate: Number of executed vector instructions per cycle 1407system.cpu1.CUs0.inst_exec_rate::stdev 237.147810 # Instruction Execution Rate: Number of executed vector instructions per cycle 1408system.cpu1.CUs0.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 1409system.cpu1.CUs0.inst_exec_rate::0-1 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 1410system.cpu1.CUs0.inst_exec_rate::2-3 12 8.51% 8.51% # Instruction Execution Rate: Number of executed vector instructions per cycle 1411system.cpu1.CUs0.inst_exec_rate::4-5 52 36.88% 45.39% # Instruction Execution Rate: Number of executed vector instructions per cycle 1412system.cpu1.CUs0.inst_exec_rate::6-7 31 21.99% 67.38% # Instruction Execution Rate: Number of executed vector instructions per cycle 1413system.cpu1.CUs0.inst_exec_rate::8-9 3 2.13% 69.50% # Instruction Execution Rate: Number of executed vector instructions per cycle 1414system.cpu1.CUs0.inst_exec_rate::10 3 2.13% 71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle 1415system.cpu1.CUs0.inst_exec_rate::overflows 40 28.37% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 1416system.cpu1.CUs0.inst_exec_rate::min_value 2 # Instruction Execution Rate: Number of executed vector instructions per cycle 1417system.cpu1.CUs0.inst_exec_rate::max_value 1297 # Instruction Execution Rate: Number of executed vector instructions per cycle 1418system.cpu1.CUs0.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle 1419system.cpu1.CUs0.num_vec_ops_executed 6769 # number of vec ops executed (e.g. WF size/inst) 1420system.cpu1.CUs0.num_total_cycles 3570 # number of cycles the CU ran for 1421system.cpu1.CUs0.vpc 1.896078 # Vector Operations per cycle (this CU only) 1422system.cpu1.CUs0.ipc 0.039496 # Instructions per cycle (this CU only) 1423system.cpu1.CUs0.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) 1424system.cpu1.CUs0.warp_execution_dist::mean 48.007092 # number of lanes active per instruction (oval all instructions) 1425system.cpu1.CUs0.warp_execution_dist::stdev 23.719942 # number of lanes active per instruction (oval all instructions) 1426system.cpu1.CUs0.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions) 1427system.cpu1.CUs0.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions) 1428system.cpu1.CUs0.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) 1429system.cpu1.CUs0.warp_execution_dist::9-12 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) 1430system.cpu1.CUs0.warp_execution_dist::13-16 36 25.53% 29.08% # number of lanes active per instruction (oval all instructions) 1431system.cpu1.CUs0.warp_execution_dist::17-20 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 1432system.cpu1.CUs0.warp_execution_dist::21-24 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 1433system.cpu1.CUs0.warp_execution_dist::25-28 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 1434system.cpu1.CUs0.warp_execution_dist::29-32 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 1435system.cpu1.CUs0.warp_execution_dist::33-36 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 1436system.cpu1.CUs0.warp_execution_dist::37-40 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 1437system.cpu1.CUs0.warp_execution_dist::41-44 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 1438system.cpu1.CUs0.warp_execution_dist::45-48 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 1439system.cpu1.CUs0.warp_execution_dist::49-52 8 5.67% 34.75% # number of lanes active per instruction (oval all instructions) 1440system.cpu1.CUs0.warp_execution_dist::53-56 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) 1441system.cpu1.CUs0.warp_execution_dist::57-60 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) 1442system.cpu1.CUs0.warp_execution_dist::61-64 92 65.25% 100.00% # number of lanes active per instruction (oval all instructions) 1443system.cpu1.CUs0.warp_execution_dist::overflows 0 0.00% 100.00% # number of lanes active per instruction (oval all instructions) 1444system.cpu1.CUs0.warp_execution_dist::min_value 1 # number of lanes active per instruction (oval all instructions) 1445system.cpu1.CUs0.warp_execution_dist::max_value 64 # number of lanes active per instruction (oval all instructions) 1446system.cpu1.CUs0.warp_execution_dist::total 141 # number of lanes active per instruction (oval all instructions) 1447system.cpu1.CUs0.gmem_lanes_execution_dist::samples 18 # number of active lanes per global memory instruction 1448system.cpu1.CUs0.gmem_lanes_execution_dist::mean 37.833333 # number of active lanes per global memory instruction 1449system.cpu1.CUs0.gmem_lanes_execution_dist::stdev 27.064737 # number of active lanes per global memory instruction 1450system.cpu1.CUs0.gmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per global memory instruction 1451system.cpu1.CUs0.gmem_lanes_execution_dist::1-4 1 5.56% 5.56% # number of active lanes per global memory instruction 1452system.cpu1.CUs0.gmem_lanes_execution_dist::5-8 0 0.00% 5.56% # number of active lanes per global memory instruction 1453system.cpu1.CUs0.gmem_lanes_execution_dist::9-12 0 0.00% 5.56% # number of active lanes per global memory instruction 1454system.cpu1.CUs0.gmem_lanes_execution_dist::13-16 8 44.44% 50.00% # number of active lanes per global memory instruction 1455system.cpu1.CUs0.gmem_lanes_execution_dist::17-20 0 0.00% 50.00% # number of active lanes per global memory instruction 1456system.cpu1.CUs0.gmem_lanes_execution_dist::21-24 0 0.00% 50.00% # number of active lanes per global memory instruction 1457system.cpu1.CUs0.gmem_lanes_execution_dist::25-28 0 0.00% 50.00% # number of active lanes per global memory instruction 1458system.cpu1.CUs0.gmem_lanes_execution_dist::29-32 0 0.00% 50.00% # number of active lanes per global memory instruction 1459system.cpu1.CUs0.gmem_lanes_execution_dist::33-36 0 0.00% 50.00% # number of active lanes per global memory instruction 1460system.cpu1.CUs0.gmem_lanes_execution_dist::37-40 0 0.00% 50.00% # number of active lanes per global memory instruction 1461system.cpu1.CUs0.gmem_lanes_execution_dist::41-44 0 0.00% 50.00% # number of active lanes per global memory instruction 1462system.cpu1.CUs0.gmem_lanes_execution_dist::45-48 0 0.00% 50.00% # number of active lanes per global memory instruction 1463system.cpu1.CUs0.gmem_lanes_execution_dist::49-52 0 0.00% 50.00% # number of active lanes per global memory instruction 1464system.cpu1.CUs0.gmem_lanes_execution_dist::53-56 0 0.00% 50.00% # number of active lanes per global memory instruction 1465system.cpu1.CUs0.gmem_lanes_execution_dist::57-60 0 0.00% 50.00% # number of active lanes per global memory instruction 1466system.cpu1.CUs0.gmem_lanes_execution_dist::61-64 9 50.00% 100.00% # number of active lanes per global memory instruction 1467system.cpu1.CUs0.gmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per global memory instruction 1468system.cpu1.CUs0.gmem_lanes_execution_dist::min_value 1 # number of active lanes per global memory instruction 1469system.cpu1.CUs0.gmem_lanes_execution_dist::max_value 64 # number of active lanes per global memory instruction 1470system.cpu1.CUs0.gmem_lanes_execution_dist::total 18 # number of active lanes per global memory instruction 1471system.cpu1.CUs0.lmem_lanes_execution_dist::samples 6 # number of active lanes per local memory instruction 1472system.cpu1.CUs0.lmem_lanes_execution_dist::mean 19.500000 # number of active lanes per local memory instruction 1473system.cpu1.CUs0.lmem_lanes_execution_dist::stdev 22.322634 # number of active lanes per local memory instruction 1474system.cpu1.CUs0.lmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per local memory instruction 1475system.cpu1.CUs0.lmem_lanes_execution_dist::1-4 1 16.67% 16.67% # number of active lanes per local memory instruction 1476system.cpu1.CUs0.lmem_lanes_execution_dist::5-8 0 0.00% 16.67% # number of active lanes per local memory instruction 1477system.cpu1.CUs0.lmem_lanes_execution_dist::9-12 0 0.00% 16.67% # number of active lanes per local memory instruction 1478system.cpu1.CUs0.lmem_lanes_execution_dist::13-16 4 66.67% 83.33% # number of active lanes per local memory instruction 1479system.cpu1.CUs0.lmem_lanes_execution_dist::17-20 0 0.00% 83.33% # number of active lanes per local memory instruction 1480system.cpu1.CUs0.lmem_lanes_execution_dist::21-24 0 0.00% 83.33% # number of active lanes per local memory instruction 1481system.cpu1.CUs0.lmem_lanes_execution_dist::25-28 0 0.00% 83.33% # number of active lanes per local memory instruction 1482system.cpu1.CUs0.lmem_lanes_execution_dist::29-32 0 0.00% 83.33% # number of active lanes per local memory instruction 1483system.cpu1.CUs0.lmem_lanes_execution_dist::33-36 0 0.00% 83.33% # number of active lanes per local memory instruction 1484system.cpu1.CUs0.lmem_lanes_execution_dist::37-40 0 0.00% 83.33% # number of active lanes per local memory instruction 1485system.cpu1.CUs0.lmem_lanes_execution_dist::41-44 0 0.00% 83.33% # number of active lanes per local memory instruction 1486system.cpu1.CUs0.lmem_lanes_execution_dist::45-48 0 0.00% 83.33% # number of active lanes per local memory instruction 1487system.cpu1.CUs0.lmem_lanes_execution_dist::49-52 0 0.00% 83.33% # number of active lanes per local memory instruction 1488system.cpu1.CUs0.lmem_lanes_execution_dist::53-56 0 0.00% 83.33% # number of active lanes per local memory instruction 1489system.cpu1.CUs0.lmem_lanes_execution_dist::57-60 0 0.00% 83.33% # number of active lanes per local memory instruction 1490system.cpu1.CUs0.lmem_lanes_execution_dist::61-64 1 16.67% 100.00% # number of active lanes per local memory instruction 1491system.cpu1.CUs0.lmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per local memory instruction 1492system.cpu1.CUs0.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction 1493system.cpu1.CUs0.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction 1494system.cpu1.CUs0.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction 1495system.cpu1.CUs0.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed 1496system.cpu1.CUs0.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD 1497system.cpu1.CUs0.num_CAS_ops 0 # number of compare and swap operations 1498system.cpu1.CUs0.num_failed_CAS_ops 0 # number of compare and swap operations that failed 1499system.cpu1.CUs0.num_completed_wfs 4 # number of completed wavefronts 1500system.cpu1.CUs1.localDataStore.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 1501system.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1502system.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1503system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 591 # number of times the wf's instructions are blocked due to RAW dependencies 1504system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands 1505system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands 1506system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands 1507system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 1508system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands 1509system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands 1510system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 1511system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 1512system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1513system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 1514system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::total 39 # number of executed instructions with N source register operands 1515system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::samples 39 # number of executed instructions with N destination register operands 1516system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::mean 0.589744 # number of executed instructions with N destination register operands 1517system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::stdev 0.498310 # number of executed instructions with N destination register operands 1518system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 1519system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00% # number of executed instructions with N destination register operands 1520system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 1521system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 1522system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1523system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 1524system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::total 39 # number of executed instructions with N destination register operands 1525system.cpu1.CUs1.wavefronts01.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1526system.cpu1.CUs1.wavefronts01.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1527system.cpu1.CUs1.wavefronts01.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1528system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1529system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1530system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1531system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1532system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1533system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1534system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1535system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1536system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1537system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1538system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1539system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1540system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1541system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1542system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1543system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1544system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1545system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1546system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1547system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1548system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1549system.cpu1.CUs1.wavefronts02.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1550system.cpu1.CUs1.wavefronts02.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1551system.cpu1.CUs1.wavefronts02.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1552system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1553system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1554system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1555system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1556system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1557system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1558system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1559system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1560system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1561system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1562system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1563system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1564system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1565system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1566system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1567system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1568system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1569system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1570system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1571system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1572system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1573system.cpu1.CUs1.wavefronts03.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1574system.cpu1.CUs1.wavefronts03.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1575system.cpu1.CUs1.wavefronts03.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1576system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1577system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1578system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1579system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1580system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1581system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1582system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1583system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1584system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1585system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1586system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1587system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1588system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1589system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1590system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1591system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1592system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1593system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1594system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1595system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1596system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1597system.cpu1.CUs1.wavefronts04.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1598system.cpu1.CUs1.wavefronts04.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1599system.cpu1.CUs1.wavefronts04.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1600system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1601system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1602system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1603system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1604system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1605system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1606system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1607system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1608system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1609system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1610system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1611system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1612system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1613system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1614system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1615system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1616system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1617system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1618system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1619system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1620system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1621system.cpu1.CUs1.wavefronts05.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1622system.cpu1.CUs1.wavefronts05.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1623system.cpu1.CUs1.wavefronts05.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1624system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1625system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1626system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1627system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1628system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1629system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1630system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1631system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1632system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1633system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1634system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1635system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1636system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1637system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1638system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1639system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1640system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1641system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1642system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1643system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1644system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1645system.cpu1.CUs1.wavefronts06.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1646system.cpu1.CUs1.wavefronts06.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1647system.cpu1.CUs1.wavefronts06.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1648system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1649system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1650system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1651system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1652system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1653system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1654system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1655system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1656system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1657system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1658system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1659system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1660system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1661system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1662system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1663system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1664system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1665system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1666system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1667system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1668system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1669system.cpu1.CUs1.wavefronts07.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1670system.cpu1.CUs1.wavefronts07.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1671system.cpu1.CUs1.wavefronts07.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1672system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1673system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1674system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1675system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1676system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1677system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1678system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1679system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1680system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1681system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1682system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1683system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1684system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1685system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1686system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1687system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1688system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1689system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1690system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1691system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1692system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1693system.cpu1.CUs1.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1694system.cpu1.CUs1.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1695system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 562 # number of times the wf's instructions are blocked due to RAW dependencies 1696system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 1697system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 1698system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 1699system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 1700system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 1701system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 1702system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 1703system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 1704system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1705system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 1706system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 1707system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 1708system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 1709system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 1710system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 1711system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 1712system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 1713system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 1714system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1715system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 1716system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 1717system.cpu1.CUs1.wavefronts09.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1718system.cpu1.CUs1.wavefronts09.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1719system.cpu1.CUs1.wavefronts09.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1720system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1721system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1722system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1723system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1724system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1725system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1726system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1727system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1728system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1729system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1730system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1731system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1732system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1733system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1734system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1735system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1736system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1737system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1738system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1739system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1740system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1741system.cpu1.CUs1.wavefronts10.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1742system.cpu1.CUs1.wavefronts10.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1743system.cpu1.CUs1.wavefronts10.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1744system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1745system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1746system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1747system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1748system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1749system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1750system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1751system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1752system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1753system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1754system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1755system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1756system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1757system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1758system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1759system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1760system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1761system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1762system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1763system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1764system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1765system.cpu1.CUs1.wavefronts11.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1766system.cpu1.CUs1.wavefronts11.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1767system.cpu1.CUs1.wavefronts11.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1768system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1769system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1770system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1771system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1772system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1773system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1774system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1775system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1776system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1777system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1778system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1779system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1780system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1781system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1782system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1783system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1784system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1785system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1786system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1787system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1788system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1789system.cpu1.CUs1.wavefronts12.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1790system.cpu1.CUs1.wavefronts12.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1791system.cpu1.CUs1.wavefronts12.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1792system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1793system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1794system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1795system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1796system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1797system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1798system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1799system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1800system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1801system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1802system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1803system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1804system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1805system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1806system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1807system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1808system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1809system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1810system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1811system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1812system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1813system.cpu1.CUs1.wavefronts13.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1814system.cpu1.CUs1.wavefronts13.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1815system.cpu1.CUs1.wavefronts13.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1816system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1817system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1818system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1819system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1820system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1821system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1822system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1823system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1824system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1825system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1826system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1827system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1828system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1829system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1830system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1831system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1832system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1833system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1834system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1835system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1836system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1837system.cpu1.CUs1.wavefronts14.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1838system.cpu1.CUs1.wavefronts14.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1839system.cpu1.CUs1.wavefronts14.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1840system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1841system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1842system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1843system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1844system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1845system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1846system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1847system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1848system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1849system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1850system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1851system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1852system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1853system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1854system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1855system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1856system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1857system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1858system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1859system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1860system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1861system.cpu1.CUs1.wavefronts15.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1862system.cpu1.CUs1.wavefronts15.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1863system.cpu1.CUs1.wavefronts15.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1864system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1865system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1866system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1867system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1868system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1869system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1870system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1871system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1872system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1873system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1874system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1875system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1876system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1877system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1878system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1879system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1880system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1881system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1882system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1883system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1884system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1885system.cpu1.CUs1.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1886system.cpu1.CUs1.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1887system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 561 # number of times the wf's instructions are blocked due to RAW dependencies 1888system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 1889system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 1890system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 1891system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 1892system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 1893system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 1894system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 1895system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 1896system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1897system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 1898system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 1899system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 1900system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 1901system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 1902system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 1903system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 1904system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 1905system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 1906system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1907system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 1908system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 1909system.cpu1.CUs1.wavefronts17.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1910system.cpu1.CUs1.wavefronts17.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1911system.cpu1.CUs1.wavefronts17.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1912system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1913system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1914system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1915system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1916system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1917system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1918system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1919system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1920system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1921system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1922system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1923system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1924system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1925system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1926system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1927system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1928system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1929system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1930system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1931system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1932system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1933system.cpu1.CUs1.wavefronts18.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1934system.cpu1.CUs1.wavefronts18.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1935system.cpu1.CUs1.wavefronts18.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1936system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1937system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1938system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1939system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1940system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1941system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1942system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1943system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1944system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1945system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1946system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1947system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1948system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1949system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1950system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1951system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1952system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1953system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1954system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1955system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1956system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1957system.cpu1.CUs1.wavefronts19.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1958system.cpu1.CUs1.wavefronts19.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1959system.cpu1.CUs1.wavefronts19.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1960system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1961system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1962system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1963system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1964system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1965system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1966system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1967system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1968system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1969system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1970system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1971system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1972system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1973system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1974system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1975system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1976system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1977system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1978system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1979system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1980system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1981system.cpu1.CUs1.wavefronts20.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1982system.cpu1.CUs1.wavefronts20.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1983system.cpu1.CUs1.wavefronts20.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1984system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1985system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1986system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1987system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1988system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1989system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1990system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1991system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1992system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1993system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1994system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1995system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1996system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1997system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1998system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1999system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 2000system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 2001system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 2002system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2003system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 2004system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 2005system.cpu1.CUs1.wavefronts21.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 2006system.cpu1.CUs1.wavefronts21.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 2007system.cpu1.CUs1.wavefronts21.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 2008system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 2009system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 2010system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 2011system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 2012system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 2013system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 2014system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 2015system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 2016system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 2017system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 2018system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 2019system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 2020system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 2021system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 2022system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 2023system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 2024system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 2025system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 2026system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2027system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 2028system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 2029system.cpu1.CUs1.wavefronts22.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 2030system.cpu1.CUs1.wavefronts22.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 2031system.cpu1.CUs1.wavefronts22.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 2032system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 2033system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 2034system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 2035system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 2036system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 2037system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 2038system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 2039system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 2040system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 2041system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 2042system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 2043system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 2044system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 2045system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 2046system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 2047system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 2048system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 2049system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 2050system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2051system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 2052system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 2053system.cpu1.CUs1.wavefronts23.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 2054system.cpu1.CUs1.wavefronts23.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 2055system.cpu1.CUs1.wavefronts23.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 2056system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 2057system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 2058system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 2059system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 2060system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 2061system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 2062system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 2063system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 2064system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 2065system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 2066system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 2067system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 2068system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 2069system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 2070system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 2071system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 2072system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 2073system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 2074system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2075system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 2076system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 2077system.cpu1.CUs1.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 2078system.cpu1.CUs1.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 2079system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 551 # number of times the wf's instructions are blocked due to RAW dependencies 2080system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 2081system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 2082system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 2083system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 2084system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 2085system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 2086system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 2087system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 2088system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 2089system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 2090system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 2091system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 2092system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 2093system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 2094system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 2095system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 2096system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 2097system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 2098system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2099system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 2100system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 2101system.cpu1.CUs1.wavefronts25.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 2102system.cpu1.CUs1.wavefronts25.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 2103system.cpu1.CUs1.wavefronts25.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 2104system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 2105system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 2106system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 2107system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 2108system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 2109system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 2110system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 2111system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 2112system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 2113system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 2114system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 2115system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 2116system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 2117system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 2118system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 2119system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 2120system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 2121system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 2122system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2123system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 2124system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 2125system.cpu1.CUs1.wavefronts26.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 2126system.cpu1.CUs1.wavefronts26.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 2127system.cpu1.CUs1.wavefronts26.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 2128system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 2129system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 2130system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 2131system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 2132system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 2133system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 2134system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 2135system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 2136system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 2137system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 2138system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 2139system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 2140system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 2141system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 2142system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 2143system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 2144system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 2145system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 2146system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2147system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 2148system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 2149system.cpu1.CUs1.wavefronts27.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 2150system.cpu1.CUs1.wavefronts27.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 2151system.cpu1.CUs1.wavefronts27.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 2152system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 2153system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 2154system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 2155system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 2156system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 2157system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 2158system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 2159system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 2160system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 2161system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 2162system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 2163system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 2164system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 2165system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 2166system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 2167system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 2168system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 2169system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 2170system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2171system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 2172system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 2173system.cpu1.CUs1.wavefronts28.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 2174system.cpu1.CUs1.wavefronts28.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 2175system.cpu1.CUs1.wavefronts28.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 2176system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 2177system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 2178system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 2179system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 2180system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 2181system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 2182system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 2183system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 2184system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 2185system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 2186system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 2187system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 2188system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 2189system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 2190system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 2191system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 2192system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 2193system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 2194system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2195system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 2196system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 2197system.cpu1.CUs1.wavefronts29.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 2198system.cpu1.CUs1.wavefronts29.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 2199system.cpu1.CUs1.wavefronts29.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 2200system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 2201system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 2202system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 2203system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 2204system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 2205system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 2206system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 2207system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 2208system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 2209system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 2210system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 2211system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 2212system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 2213system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 2214system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 2215system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 2216system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 2217system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 2218system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2219system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 2220system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 2221system.cpu1.CUs1.wavefronts30.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 2222system.cpu1.CUs1.wavefronts30.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 2223system.cpu1.CUs1.wavefronts30.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 2224system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 2225system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 2226system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 2227system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 2228system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 2229system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 2230system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 2231system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 2232system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 2233system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 2234system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 2235system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 2236system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 2237system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 2238system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 2239system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 2240system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 2241system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 2242system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2243system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 2244system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 2245system.cpu1.CUs1.wavefronts31.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 2246system.cpu1.CUs1.wavefronts31.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 2247system.cpu1.CUs1.wavefronts31.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 2248system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 2249system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 2250system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 2251system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 2252system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 2253system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 2254system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 2255system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 2256system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 2257system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 2258system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 2259system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 2260system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 2261system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 2262system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 2263system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 2264system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 2265system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 2266system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2267system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 2268system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 2269system.cpu1.CUs1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2270system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it 2271system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it 2272system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it 2273system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 2274system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 2275system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it 2276system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it 2277system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it 2278system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it 2279system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it 2280system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it 2281system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2282system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2283system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2284system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2285system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2286system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2287system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2288system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2289system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2290system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2291system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2292system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2293system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2294system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2295system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2296system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2297system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2298system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2299system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2300system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2301system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2302system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2303system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2304system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2305system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2306system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2307system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it 2308system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it 2309system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it 2310system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 3471 # number of cycles the CU issues nothing 2311system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 99 # number of cycles the CU issued at least one instruction 2312system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued 2313system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued 2314system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued 2315system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued 2316system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued 2317system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued 2318system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 973 # Number of cycles no instruction of specific type issued 2319system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 662 # Number of cycles no instruction of specific type issued 2320system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 634 # Number of cycles no instruction of specific type issued 2321system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 606 # Number of cycles no instruction of specific type issued 2322system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 404 # Number of cycles no instruction of specific type issued 2323system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM 22 # Number of cycles no instruction of specific type issued 2324system.cpu1.CUs1.ExecStage.spc::samples 3570 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2325system.cpu1.CUs1.ExecStage.spc::mean 0.039496 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2326system.cpu1.CUs1.ExecStage.spc::stdev 0.249084 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2327system.cpu1.CUs1.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2328system.cpu1.CUs1.ExecStage.spc::0 3471 97.23% 97.23% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2329system.cpu1.CUs1.ExecStage.spc::1 58 1.62% 98.85% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2330system.cpu1.CUs1.ExecStage.spc::2 40 1.12% 99.97% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2331system.cpu1.CUs1.ExecStage.spc::3 1 0.03% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2332system.cpu1.CUs1.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2333system.cpu1.CUs1.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2334system.cpu1.CUs1.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2335system.cpu1.CUs1.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2336system.cpu1.CUs1.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2337system.cpu1.CUs1.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2338system.cpu1.CUs1.ExecStage.spc::total 3570 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2339system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 94 # number of CU transitions from active to idle 2340system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 94 # duration of idle periods in cycles 2341system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 35.776596 # duration of idle periods in cycles 2342system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 153.908027 # duration of idle periods in cycles 2343system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles 2344system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 75 79.79% 79.79% # duration of idle periods in cycles 2345system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 8 8.51% 88.30% # duration of idle periods in cycles 2346system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 88.30% # duration of idle periods in cycles 2347system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 1 1.06% 89.36% # duration of idle periods in cycles 2348system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 2 2.13% 91.49% # duration of idle periods in cycles 2349system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 1 1.06% 92.55% # duration of idle periods in cycles 2350system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 92.55% # duration of idle periods in cycles 2351system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 92.55% # duration of idle periods in cycles 2352system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 92.55% # duration of idle periods in cycles 2353system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 92.55% # duration of idle periods in cycles 2354system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 92.55% # duration of idle periods in cycles 2355system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 92.55% # duration of idle periods in cycles 2356system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 92.55% # duration of idle periods in cycles 2357system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 92.55% # duration of idle periods in cycles 2358system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 92.55% # duration of idle periods in cycles 2359system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 92.55% # duration of idle periods in cycles 2360system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 7 7.45% 100.00% # duration of idle periods in cycles 2361system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles 2362system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::max_value 1299 # duration of idle periods in cycles 2363system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 94 # duration of idle periods in cycles 2364system.cpu1.CUs1.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF 2365system.cpu1.CUs1.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF 2366system.cpu1.CUs1.tlb_requests 769 # number of uncoalesced requests 2367system.cpu1.CUs1.tlb_cycles -455230572000 # total number of cycles for all uncoalesced requests 2368system.cpu1.CUs1.avg_translation_latency -591977336.801040 # Avg. translation latency for data translations 2369system.cpu1.CUs1.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB 2370system.cpu1.CUs1.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 2371system.cpu1.CUs1.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 2372system.cpu1.CUs1.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 2373system.cpu1.CUs1.lds_bank_access_cnt 53 # Total number of LDS bank accesses 2374system.cpu1.CUs1.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet 2375system.cpu1.CUs1.lds_bank_conflicts::mean 7.833333 # Number of bank conflicts per LDS memory packet 2376system.cpu1.CUs1.lds_bank_conflicts::stdev 6.080022 # Number of bank conflicts per LDS memory packet 2377system.cpu1.CUs1.lds_bank_conflicts::underflows 0 0.00% 0.00% # Number of bank conflicts per LDS memory packet 2378system.cpu1.CUs1.lds_bank_conflicts::0-1 2 33.33% 33.33% # Number of bank conflicts per LDS memory packet 2379system.cpu1.CUs1.lds_bank_conflicts::2-3 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 2380system.cpu1.CUs1.lds_bank_conflicts::4-5 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 2381system.cpu1.CUs1.lds_bank_conflicts::6-7 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 2382system.cpu1.CUs1.lds_bank_conflicts::8-9 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 2383system.cpu1.CUs1.lds_bank_conflicts::10-11 1 16.67% 50.00% # Number of bank conflicts per LDS memory packet 2384system.cpu1.CUs1.lds_bank_conflicts::12-13 3 50.00% 100.00% # Number of bank conflicts per LDS memory packet 2385system.cpu1.CUs1.lds_bank_conflicts::14-15 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2386system.cpu1.CUs1.lds_bank_conflicts::16-17 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2387system.cpu1.CUs1.lds_bank_conflicts::18-19 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2388system.cpu1.CUs1.lds_bank_conflicts::20-21 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2389system.cpu1.CUs1.lds_bank_conflicts::22-23 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2390system.cpu1.CUs1.lds_bank_conflicts::24-25 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2391system.cpu1.CUs1.lds_bank_conflicts::26-27 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2392system.cpu1.CUs1.lds_bank_conflicts::28-29 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2393system.cpu1.CUs1.lds_bank_conflicts::30-31 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2394system.cpu1.CUs1.lds_bank_conflicts::32-33 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2395system.cpu1.CUs1.lds_bank_conflicts::34-35 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2396system.cpu1.CUs1.lds_bank_conflicts::36-37 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2397system.cpu1.CUs1.lds_bank_conflicts::38-39 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2398system.cpu1.CUs1.lds_bank_conflicts::40-41 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2399system.cpu1.CUs1.lds_bank_conflicts::42-43 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2400system.cpu1.CUs1.lds_bank_conflicts::44-45 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2401system.cpu1.CUs1.lds_bank_conflicts::46-47 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2402system.cpu1.CUs1.lds_bank_conflicts::48-49 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2403system.cpu1.CUs1.lds_bank_conflicts::50-51 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2404system.cpu1.CUs1.lds_bank_conflicts::52-53 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2405system.cpu1.CUs1.lds_bank_conflicts::54-55 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2406system.cpu1.CUs1.lds_bank_conflicts::56-57 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2407system.cpu1.CUs1.lds_bank_conflicts::58-59 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2408system.cpu1.CUs1.lds_bank_conflicts::60-61 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2409system.cpu1.CUs1.lds_bank_conflicts::62-63 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2410system.cpu1.CUs1.lds_bank_conflicts::64 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2411system.cpu1.CUs1.lds_bank_conflicts::overflows 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2412system.cpu1.CUs1.lds_bank_conflicts::min_value 0 # Number of bank conflicts per LDS memory packet 2413system.cpu1.CUs1.lds_bank_conflicts::max_value 12 # Number of bank conflicts per LDS memory packet 2414system.cpu1.CUs1.lds_bank_conflicts::total 6 # Number of bank conflicts per LDS memory packet 2415system.cpu1.CUs1.page_divergence_dist::samples 17 # pages touched per wf (over all mem. instr.) 2416system.cpu1.CUs1.page_divergence_dist::mean 1 # pages touched per wf (over all mem. instr.) 2417system.cpu1.CUs1.page_divergence_dist::stdev 0 # pages touched per wf (over all mem. instr.) 2418system.cpu1.CUs1.page_divergence_dist::underflows 0 0.00% 0.00% # pages touched per wf (over all mem. instr.) 2419system.cpu1.CUs1.page_divergence_dist::1-4 17 100.00% 100.00% # pages touched per wf (over all mem. instr.) 2420system.cpu1.CUs1.page_divergence_dist::5-8 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2421system.cpu1.CUs1.page_divergence_dist::9-12 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2422system.cpu1.CUs1.page_divergence_dist::13-16 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2423system.cpu1.CUs1.page_divergence_dist::17-20 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2424system.cpu1.CUs1.page_divergence_dist::21-24 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2425system.cpu1.CUs1.page_divergence_dist::25-28 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2426system.cpu1.CUs1.page_divergence_dist::29-32 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2427system.cpu1.CUs1.page_divergence_dist::33-36 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2428system.cpu1.CUs1.page_divergence_dist::37-40 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2429system.cpu1.CUs1.page_divergence_dist::41-44 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2430system.cpu1.CUs1.page_divergence_dist::45-48 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2431system.cpu1.CUs1.page_divergence_dist::49-52 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2432system.cpu1.CUs1.page_divergence_dist::53-56 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2433system.cpu1.CUs1.page_divergence_dist::57-60 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2434system.cpu1.CUs1.page_divergence_dist::61-64 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2435system.cpu1.CUs1.page_divergence_dist::overflows 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2436system.cpu1.CUs1.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.) 2437system.cpu1.CUs1.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.) 2438system.cpu1.CUs1.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.) 2439system.cpu1.CUs1.global_mem_instr_cnt 17 # dynamic global memory instructions count 2440system.cpu1.CUs1.local_mem_instr_cnt 6 # dynamic local memory intruction count 2441system.cpu1.CUs1.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity 2442system.cpu1.CUs1.num_instr_executed 141 # number of instructions executed 2443system.cpu1.CUs1.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle 2444system.cpu1.CUs1.inst_exec_rate::mean 91.269504 # Instruction Execution Rate: Number of executed vector instructions per cycle 2445system.cpu1.CUs1.inst_exec_rate::stdev 240.230451 # Instruction Execution Rate: Number of executed vector instructions per cycle 2446system.cpu1.CUs1.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 2447system.cpu1.CUs1.inst_exec_rate::0-1 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 2448system.cpu1.CUs1.inst_exec_rate::2-3 13 9.22% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle 2449system.cpu1.CUs1.inst_exec_rate::4-5 52 36.88% 46.10% # Instruction Execution Rate: Number of executed vector instructions per cycle 2450system.cpu1.CUs1.inst_exec_rate::6-7 33 23.40% 69.50% # Instruction Execution Rate: Number of executed vector instructions per cycle 2451system.cpu1.CUs1.inst_exec_rate::8-9 6 4.26% 73.76% # Instruction Execution Rate: Number of executed vector instructions per cycle 2452system.cpu1.CUs1.inst_exec_rate::10 0 0.00% 73.76% # Instruction Execution Rate: Number of executed vector instructions per cycle 2453system.cpu1.CUs1.inst_exec_rate::overflows 37 26.24% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 2454system.cpu1.CUs1.inst_exec_rate::min_value 2 # Instruction Execution Rate: Number of executed vector instructions per cycle 2455system.cpu1.CUs1.inst_exec_rate::max_value 1305 # Instruction Execution Rate: Number of executed vector instructions per cycle 2456system.cpu1.CUs1.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle 2457system.cpu1.CUs1.num_vec_ops_executed 6762 # number of vec ops executed (e.g. WF size/inst) 2458system.cpu1.CUs1.num_total_cycles 3570 # number of cycles the CU ran for 2459system.cpu1.CUs1.vpc 1.894118 # Vector Operations per cycle (this CU only) 2460system.cpu1.CUs1.ipc 0.039496 # Instructions per cycle (this CU only) 2461system.cpu1.CUs1.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) 2462system.cpu1.CUs1.warp_execution_dist::mean 47.957447 # number of lanes active per instruction (oval all instructions) 2463system.cpu1.CUs1.warp_execution_dist::stdev 23.818022 # number of lanes active per instruction (oval all instructions) 2464system.cpu1.CUs1.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions) 2465system.cpu1.CUs1.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions) 2466system.cpu1.CUs1.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) 2467system.cpu1.CUs1.warp_execution_dist::9-12 9 6.38% 9.93% # number of lanes active per instruction (oval all instructions) 2468system.cpu1.CUs1.warp_execution_dist::13-16 27 19.15% 29.08% # number of lanes active per instruction (oval all instructions) 2469system.cpu1.CUs1.warp_execution_dist::17-20 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 2470system.cpu1.CUs1.warp_execution_dist::21-24 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 2471system.cpu1.CUs1.warp_execution_dist::25-28 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 2472system.cpu1.CUs1.warp_execution_dist::29-32 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 2473system.cpu1.CUs1.warp_execution_dist::33-36 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 2474system.cpu1.CUs1.warp_execution_dist::37-40 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 2475system.cpu1.CUs1.warp_execution_dist::41-44 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 2476system.cpu1.CUs1.warp_execution_dist::45-48 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 2477system.cpu1.CUs1.warp_execution_dist::49-52 8 5.67% 34.75% # number of lanes active per instruction (oval all instructions) 2478system.cpu1.CUs1.warp_execution_dist::53-56 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) 2479system.cpu1.CUs1.warp_execution_dist::57-60 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) 2480system.cpu1.CUs1.warp_execution_dist::61-64 92 65.25% 100.00% # number of lanes active per instruction (oval all instructions) 2481system.cpu1.CUs1.warp_execution_dist::overflows 0 0.00% 100.00% # number of lanes active per instruction (oval all instructions) 2482system.cpu1.CUs1.warp_execution_dist::min_value 1 # number of lanes active per instruction (oval all instructions) 2483system.cpu1.CUs1.warp_execution_dist::max_value 64 # number of lanes active per instruction (oval all instructions) 2484system.cpu1.CUs1.warp_execution_dist::total 141 # number of lanes active per instruction (oval all instructions) 2485system.cpu1.CUs1.gmem_lanes_execution_dist::samples 18 # number of active lanes per global memory instruction 2486system.cpu1.CUs1.gmem_lanes_execution_dist::mean 37.722222 # number of active lanes per global memory instruction 2487system.cpu1.CUs1.gmem_lanes_execution_dist::stdev 27.174394 # number of active lanes per global memory instruction 2488system.cpu1.CUs1.gmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per global memory instruction 2489system.cpu1.CUs1.gmem_lanes_execution_dist::1-4 1 5.56% 5.56% # number of active lanes per global memory instruction 2490system.cpu1.CUs1.gmem_lanes_execution_dist::5-8 0 0.00% 5.56% # number of active lanes per global memory instruction 2491system.cpu1.CUs1.gmem_lanes_execution_dist::9-12 2 11.11% 16.67% # number of active lanes per global memory instruction 2492system.cpu1.CUs1.gmem_lanes_execution_dist::13-16 6 33.33% 50.00% # number of active lanes per global memory instruction 2493system.cpu1.CUs1.gmem_lanes_execution_dist::17-20 0 0.00% 50.00% # number of active lanes per global memory instruction 2494system.cpu1.CUs1.gmem_lanes_execution_dist::21-24 0 0.00% 50.00% # number of active lanes per global memory instruction 2495system.cpu1.CUs1.gmem_lanes_execution_dist::25-28 0 0.00% 50.00% # number of active lanes per global memory instruction 2496system.cpu1.CUs1.gmem_lanes_execution_dist::29-32 0 0.00% 50.00% # number of active lanes per global memory instruction 2497system.cpu1.CUs1.gmem_lanes_execution_dist::33-36 0 0.00% 50.00% # number of active lanes per global memory instruction 2498system.cpu1.CUs1.gmem_lanes_execution_dist::37-40 0 0.00% 50.00% # number of active lanes per global memory instruction 2499system.cpu1.CUs1.gmem_lanes_execution_dist::41-44 0 0.00% 50.00% # number of active lanes per global memory instruction 2500system.cpu1.CUs1.gmem_lanes_execution_dist::45-48 0 0.00% 50.00% # number of active lanes per global memory instruction 2501system.cpu1.CUs1.gmem_lanes_execution_dist::49-52 0 0.00% 50.00% # number of active lanes per global memory instruction 2502system.cpu1.CUs1.gmem_lanes_execution_dist::53-56 0 0.00% 50.00% # number of active lanes per global memory instruction 2503system.cpu1.CUs1.gmem_lanes_execution_dist::57-60 0 0.00% 50.00% # number of active lanes per global memory instruction 2504system.cpu1.CUs1.gmem_lanes_execution_dist::61-64 9 50.00% 100.00% # number of active lanes per global memory instruction 2505system.cpu1.CUs1.gmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per global memory instruction 2506system.cpu1.CUs1.gmem_lanes_execution_dist::min_value 1 # number of active lanes per global memory instruction 2507system.cpu1.CUs1.gmem_lanes_execution_dist::max_value 64 # number of active lanes per global memory instruction 2508system.cpu1.CUs1.gmem_lanes_execution_dist::total 18 # number of active lanes per global memory instruction 2509system.cpu1.CUs1.lmem_lanes_execution_dist::samples 6 # number of active lanes per local memory instruction 2510system.cpu1.CUs1.lmem_lanes_execution_dist::mean 19.333333 # number of active lanes per local memory instruction 2511system.cpu1.CUs1.lmem_lanes_execution_dist::stdev 22.384518 # number of active lanes per local memory instruction 2512system.cpu1.CUs1.lmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per local memory instruction 2513system.cpu1.CUs1.lmem_lanes_execution_dist::1-4 1 16.67% 16.67% # number of active lanes per local memory instruction 2514system.cpu1.CUs1.lmem_lanes_execution_dist::5-8 0 0.00% 16.67% # number of active lanes per local memory instruction 2515system.cpu1.CUs1.lmem_lanes_execution_dist::9-12 1 16.67% 33.33% # number of active lanes per local memory instruction 2516system.cpu1.CUs1.lmem_lanes_execution_dist::13-16 3 50.00% 83.33% # number of active lanes per local memory instruction 2517system.cpu1.CUs1.lmem_lanes_execution_dist::17-20 0 0.00% 83.33% # number of active lanes per local memory instruction 2518system.cpu1.CUs1.lmem_lanes_execution_dist::21-24 0 0.00% 83.33% # number of active lanes per local memory instruction 2519system.cpu1.CUs1.lmem_lanes_execution_dist::25-28 0 0.00% 83.33% # number of active lanes per local memory instruction 2520system.cpu1.CUs1.lmem_lanes_execution_dist::29-32 0 0.00% 83.33% # number of active lanes per local memory instruction 2521system.cpu1.CUs1.lmem_lanes_execution_dist::33-36 0 0.00% 83.33% # number of active lanes per local memory instruction 2522system.cpu1.CUs1.lmem_lanes_execution_dist::37-40 0 0.00% 83.33% # number of active lanes per local memory instruction 2523system.cpu1.CUs1.lmem_lanes_execution_dist::41-44 0 0.00% 83.33% # number of active lanes per local memory instruction 2524system.cpu1.CUs1.lmem_lanes_execution_dist::45-48 0 0.00% 83.33% # number of active lanes per local memory instruction 2525system.cpu1.CUs1.lmem_lanes_execution_dist::49-52 0 0.00% 83.33% # number of active lanes per local memory instruction 2526system.cpu1.CUs1.lmem_lanes_execution_dist::53-56 0 0.00% 83.33% # number of active lanes per local memory instruction 2527system.cpu1.CUs1.lmem_lanes_execution_dist::57-60 0 0.00% 83.33% # number of active lanes per local memory instruction 2528system.cpu1.CUs1.lmem_lanes_execution_dist::61-64 1 16.67% 100.00% # number of active lanes per local memory instruction 2529system.cpu1.CUs1.lmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per local memory instruction 2530system.cpu1.CUs1.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction 2531system.cpu1.CUs1.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction 2532system.cpu1.CUs1.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction 2533system.cpu1.CUs1.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed 2534system.cpu1.CUs1.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD 2535system.cpu1.CUs1.num_CAS_ops 0 # number of compare and swap operations 2536system.cpu1.CUs1.num_failed_CAS_ops 0 # number of compare and swap operations that failed 2537system.cpu1.CUs1.num_completed_wfs 4 # number of completed wavefronts 2538system.cpu1.CUs0.ldsBus.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2539system.cpu1.CUs1.ldsBus.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2540system.cpu2.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2541system.cpu2.num_kernel_launched 1 # number of kernel launched 2542system.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits 2543system.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses 2544system.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses 2545system.dir_cntrl0.L3CacheMemory.num_data_array_writes 1551 # number of data array writes 2546system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1551 # number of tag array reads 2547system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1551 # number of tag array writes 2548system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2549system.dispatcher_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2550system.dispatcher_coalescer.clk_domain.clock 1000 # Clock period in ticks 2551system.dispatcher_coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2552system.dispatcher_coalescer.uncoalesced_accesses 0 # Number of uncoalesced TLB accesses 2553system.dispatcher_coalescer.coalesced_accesses 0 # Number of coalesced TLB accesses 2554system.dispatcher_coalescer.queuing_cycles 0 # Number of cycles spent in queue 2555system.dispatcher_coalescer.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 2556system.dispatcher_coalescer.local_latency nan # Avg. latency over all incoming pkts 2557system.dispatcher_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2558system.dispatcher_tlb.clk_domain.clock 1000 # Clock period in ticks 2559system.dispatcher_tlb.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2560system.dispatcher_tlb.local_TLB_accesses 0 # Number of TLB accesses 2561system.dispatcher_tlb.local_TLB_hits 0 # Number of TLB hits 2562system.dispatcher_tlb.local_TLB_misses 0 # Number of TLB misses 2563system.dispatcher_tlb.local_TLB_miss_rate nan # TLB miss rate 2564system.dispatcher_tlb.global_TLB_accesses 0 # Number of TLB accesses 2565system.dispatcher_tlb.global_TLB_hits 0 # Number of TLB hits 2566system.dispatcher_tlb.global_TLB_misses 0 # Number of TLB misses 2567system.dispatcher_tlb.global_TLB_miss_rate nan # TLB miss rate 2568system.dispatcher_tlb.access_cycles 0 # Cycles spent accessing this TLB level 2569system.dispatcher_tlb.page_table_cycles 0 # Cycles spent accessing the page table 2570system.dispatcher_tlb.unique_pages 0 # Number of unique pages touched 2571system.dispatcher_tlb.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 2572system.dispatcher_tlb.local_latency nan # Avg. latency over incoming coalesced reqs 2573system.dispatcher_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 2574system.l1_coalescer0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2575system.l1_coalescer0.clk_domain.clock 1000 # Clock period in ticks 2576system.l1_coalescer0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2577system.l1_coalescer0.uncoalesced_accesses 778 # Number of uncoalesced TLB accesses 2578system.l1_coalescer0.coalesced_accesses 0 # Number of coalesced TLB accesses 2579system.l1_coalescer0.queuing_cycles 0 # Number of cycles spent in queue 2580system.l1_coalescer0.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 2581system.l1_coalescer0.local_latency 0 # Avg. latency over all incoming pkts 2582system.l1_coalescer1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2583system.l1_coalescer1.clk_domain.clock 1000 # Clock period in ticks 2584system.l1_coalescer1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2585system.l1_coalescer1.uncoalesced_accesses 769 # Number of uncoalesced TLB accesses 2586system.l1_coalescer1.coalesced_accesses 0 # Number of coalesced TLB accesses 2587system.l1_coalescer1.queuing_cycles 0 # Number of cycles spent in queue 2588system.l1_coalescer1.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 2589system.l1_coalescer1.local_latency 0 # Avg. latency over all incoming pkts 2590system.l1_tlb0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2591system.l1_tlb0.clk_domain.clock 1000 # Clock period in ticks 2592system.l1_tlb0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2593system.l1_tlb0.local_TLB_accesses 778 # Number of TLB accesses 2594system.l1_tlb0.local_TLB_hits 774 # Number of TLB hits 2595system.l1_tlb0.local_TLB_misses 4 # Number of TLB misses 2596system.l1_tlb0.local_TLB_miss_rate 0.514139 # TLB miss rate 2597system.l1_tlb0.global_TLB_accesses 778 # Number of TLB accesses 2598system.l1_tlb0.global_TLB_hits 774 # Number of TLB hits 2599system.l1_tlb0.global_TLB_misses 4 # Number of TLB misses 2600system.l1_tlb0.global_TLB_miss_rate 0.514139 # TLB miss rate 2601system.l1_tlb0.access_cycles 0 # Cycles spent accessing this TLB level 2602system.l1_tlb0.page_table_cycles 0 # Cycles spent accessing the page table 2603system.l1_tlb0.unique_pages 4 # Number of unique pages touched 2604system.l1_tlb0.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 2605system.l1_tlb0.local_latency 0 # Avg. latency over incoming coalesced reqs 2606system.l1_tlb0.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 2607system.l1_tlb1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2608system.l1_tlb1.clk_domain.clock 1000 # Clock period in ticks 2609system.l1_tlb1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2610system.l1_tlb1.local_TLB_accesses 769 # Number of TLB accesses 2611system.l1_tlb1.local_TLB_hits 766 # Number of TLB hits 2612system.l1_tlb1.local_TLB_misses 3 # Number of TLB misses 2613system.l1_tlb1.local_TLB_miss_rate 0.390117 # TLB miss rate 2614system.l1_tlb1.global_TLB_accesses 769 # Number of TLB accesses 2615system.l1_tlb1.global_TLB_hits 766 # Number of TLB hits 2616system.l1_tlb1.global_TLB_misses 3 # Number of TLB misses 2617system.l1_tlb1.global_TLB_miss_rate 0.390117 # TLB miss rate 2618system.l1_tlb1.access_cycles 0 # Cycles spent accessing this TLB level 2619system.l1_tlb1.page_table_cycles 0 # Cycles spent accessing the page table 2620system.l1_tlb1.unique_pages 3 # Number of unique pages touched 2621system.l1_tlb1.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 2622system.l1_tlb1.local_latency 0 # Avg. latency over incoming coalesced reqs 2623system.l1_tlb1.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 2624system.l2_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2625system.l2_coalescer.clk_domain.clock 1000 # Clock period in ticks 2626system.l2_coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2627system.l2_coalescer.uncoalesced_accesses 8 # Number of uncoalesced TLB accesses 2628system.l2_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses 2629system.l2_coalescer.queuing_cycles 8000 # Number of cycles spent in queue 2630system.l2_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs 2631system.l2_coalescer.local_latency 125 # Avg. latency over all incoming pkts 2632system.l2_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2633system.l2_tlb.clk_domain.clock 1000 # Clock period in ticks 2634system.l2_tlb.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2635system.l2_tlb.local_TLB_accesses 8 # Number of TLB accesses 2636system.l2_tlb.local_TLB_hits 3 # Number of TLB hits 2637system.l2_tlb.local_TLB_misses 5 # Number of TLB misses 2638system.l2_tlb.local_TLB_miss_rate 62.500000 # TLB miss rate 2639system.l2_tlb.global_TLB_accesses 15 # Number of TLB accesses 2640system.l2_tlb.global_TLB_hits 3 # Number of TLB hits 2641system.l2_tlb.global_TLB_misses 12 # Number of TLB misses 2642system.l2_tlb.global_TLB_miss_rate 80 # TLB miss rate 2643system.l2_tlb.access_cycles 552008 # Cycles spent accessing this TLB level 2644system.l2_tlb.page_table_cycles 0 # Cycles spent accessing the page table 2645system.l2_tlb.unique_pages 5 # Number of unique pages touched 2646system.l2_tlb.local_cycles 69001 # Number of cycles spent in queue for all incoming reqs 2647system.l2_tlb.local_latency 8625.125000 # Avg. latency over incoming coalesced reqs 2648system.l2_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 2649system.l3_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2650system.l3_coalescer.clk_domain.clock 1000 # Clock period in ticks 2651system.l3_coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2652system.l3_coalescer.uncoalesced_accesses 5 # Number of uncoalesced TLB accesses 2653system.l3_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses 2654system.l3_coalescer.queuing_cycles 8000 # Number of cycles spent in queue 2655system.l3_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs 2656system.l3_coalescer.local_latency 200 # Avg. latency over all incoming pkts 2657system.l3_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2658system.l3_tlb.clk_domain.clock 1000 # Clock period in ticks 2659system.l3_tlb.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2660system.l3_tlb.local_TLB_accesses 5 # Number of TLB accesses 2661system.l3_tlb.local_TLB_hits 0 # Number of TLB hits 2662system.l3_tlb.local_TLB_misses 5 # Number of TLB misses 2663system.l3_tlb.local_TLB_miss_rate 100 # TLB miss rate 2664system.l3_tlb.global_TLB_accesses 12 # Number of TLB accesses 2665system.l3_tlb.global_TLB_hits 0 # Number of TLB hits 2666system.l3_tlb.global_TLB_misses 12 # Number of TLB misses 2667system.l3_tlb.global_TLB_miss_rate 100 # TLB miss rate 2668system.l3_tlb.access_cycles 1200000 # Cycles spent accessing this TLB level 2669system.l3_tlb.page_table_cycles 6000000 # Cycles spent accessing the page table 2670system.l3_tlb.unique_pages 5 # Number of unique pages touched 2671system.l3_tlb.local_cycles 150000 # Number of cycles spent in queue for all incoming reqs 2672system.l3_tlb.local_latency 30000 # Avg. latency over incoming coalesced reqs 2673system.l3_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 2674system.piobus.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2675system.piobus.trans_dist::WriteReq 94 # Transaction distribution 2676system.piobus.trans_dist::WriteResp 94 # Transaction distribution 2677system.piobus.pkt_count_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 188 # Packet count per connected master and slave (bytes) 2678system.piobus.pkt_count::total 188 # Packet count per connected master and slave (bytes) 2679system.piobus.pkt_size_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 748 # Cumulative packet size per connected master and slave (bytes) 2680system.piobus.pkt_size::total 748 # Cumulative packet size per connected master and slave (bytes) 2681system.piobus.reqLayer0.occupancy 188000 # Layer occupancy (ticks) 2682system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2683system.piobus.respLayer0.occupancy 94000 # Layer occupancy (ticks) 2684system.piobus.respLayer0.utilization 0.0 # Layer utilization (%) 2685system.ruby.network.ext_links0.int_node.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2686system.ruby.network.ext_links0.int_node.percent_links_utilized 0.007896 2687system.ruby.network.ext_links0.int_node.msg_count.Control::0 1551 2688system.ruby.network.ext_links0.int_node.msg_count.Request_Control::0 1551 2689system.ruby.network.ext_links0.int_node.msg_count.Response_Data::2 1563 2690system.ruby.network.ext_links0.int_node.msg_count.Response_Control::2 1539 2691system.ruby.network.ext_links0.int_node.msg_count.Unblock_Control::4 1551 2692system.ruby.network.ext_links0.int_node.msg_bytes.Control::0 12408 2693system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0 12408 2694system.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2 112536 2695system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2 12312 2696system.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4 12408 2697system.ruby.network.ext_links1.int_node.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2698system.ruby.network.ext_links1.int_node.percent_links_utilized 0.009900 2699system.ruby.network.ext_links1.int_node.msg_count.Control::0 16 2700system.ruby.network.ext_links1.int_node.msg_count.Request_Control::0 1535 2701system.ruby.network.ext_links1.int_node.msg_count.Response_Data::2 1537 2702system.ruby.network.ext_links1.int_node.msg_count.Response_Control::2 14 2703system.ruby.network.ext_links1.int_node.msg_count.Unblock_Control::4 1535 2704system.ruby.network.ext_links1.int_node.msg_bytes.Control::0 128 2705system.ruby.network.ext_links1.int_node.msg_bytes.Request_Control::0 12280 2706system.ruby.network.ext_links1.int_node.msg_bytes.Response_Data::2 110664 2707system.ruby.network.ext_links1.int_node.msg_bytes.Response_Control::2 112 2708system.ruby.network.ext_links1.int_node.msg_bytes.Unblock_Control::4 12280 2709system.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits 2710system.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses 2711system.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses 2712system.tcp_cntrl0.L1cache.num_data_array_reads 9 # number of data array reads 2713system.tcp_cntrl0.L1cache.num_data_array_writes 11 # number of data array writes 2714system.tcp_cntrl0.L1cache.num_tag_array_reads 26 # number of tag array reads 2715system.tcp_cntrl0.L1cache.num_tag_array_writes 18 # number of tag array writes 2716system.tcp_cntrl0.L1cache.num_data_array_stalls 2 # number of stalls caused by data array 2717system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2718system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 2 # loads that hit in the TCP 2719system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers 2720system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 2721system.tcp_cntrl0.coalescer.gpu_ld_misses 2 # loads that miss in the GPU 2722system.tcp_cntrl0.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP 2723system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 1 # TCP to TCP store transfers 2724system.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 2725system.tcp_cntrl0.coalescer.gpu_st_misses 4 # stores that miss in the GPU 2726system.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 2727system.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 2728system.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 2729system.tcp_cntrl0.coalescer.cp_ld_misses 0 # loads that miss in the GPU 2730system.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 2731system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 2732system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 2733system.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU 2734system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2735system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2736system.ruby.network.ext_links2.int_node.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2737system.ruby.network.ext_links2.int_node.percent_links_utilized 0.000716 2738system.ruby.network.ext_links2.int_node.msg_count.Control::0 1535 2739system.ruby.network.ext_links2.int_node.msg_count.Control::1 14 2740system.ruby.network.ext_links2.int_node.msg_count.Request_Control::0 16 2741system.ruby.network.ext_links2.int_node.msg_count.Request_Control::1 19 2742system.ruby.network.ext_links2.int_node.msg_count.Response_Data::2 26 2743system.ruby.network.ext_links2.int_node.msg_count.Response_Data::3 33 2744system.ruby.network.ext_links2.int_node.msg_count.Response_Control::2 1525 2745system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::4 16 2746system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::5 19 2747system.ruby.network.ext_links2.int_node.msg_bytes.Control::0 12280 2748system.ruby.network.ext_links2.int_node.msg_bytes.Control::1 112 2749system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::0 128 2750system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::1 152 2751system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::2 1872 2752system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::3 2376 2753system.ruby.network.ext_links2.int_node.msg_bytes.Response_Control::2 12200 2754system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::4 128 2755system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::5 152 2756system.tcp_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits 2757system.tcp_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses 2758system.tcp_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses 2759system.tcp_cntrl1.L1cache.num_data_array_reads 7 # number of data array reads 2760system.tcp_cntrl1.L1cache.num_data_array_writes 11 # number of data array writes 2761system.tcp_cntrl1.L1cache.num_tag_array_reads 25 # number of tag array reads 2762system.tcp_cntrl1.L1cache.num_tag_array_writes 18 # number of tag array writes 2763system.tcp_cntrl1.L1cache.num_tag_array_stalls 2 # number of stalls caused by tag array 2764system.tcp_cntrl1.L1cache.num_data_array_stalls 2 # number of stalls caused by data array 2765system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2766system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 3 # loads that hit in the TCP 2767system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 2 # TCP to TCP load transfers 2768system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 2769system.tcp_cntrl1.coalescer.gpu_ld_misses 0 # loads that miss in the GPU 2770system.tcp_cntrl1.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP 2771system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers 2772system.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 2773system.tcp_cntrl1.coalescer.gpu_st_misses 5 # stores that miss in the GPU 2774system.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 2775system.tcp_cntrl1.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 2776system.tcp_cntrl1.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 2777system.tcp_cntrl1.coalescer.cp_ld_misses 0 # loads that miss in the GPU 2778system.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 2779system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 2780system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 2781system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU 2782system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2783system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2784system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits 2785system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses 2786system.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses 2787system.sqc_cntrl0.L1cache.num_data_array_reads 86 # number of data array reads 2788system.sqc_cntrl0.L1cache.num_data_array_writes 5 # number of data array writes 2789system.sqc_cntrl0.L1cache.num_tag_array_reads 86 # number of tag array reads 2790system.sqc_cntrl0.L1cache.num_tag_array_writes 5 # number of tag array writes 2791system.sqc_cntrl0.L1cache.num_data_array_stalls 47 # number of stalls caused by data array 2792system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2793system.sqc_cntrl0.sequencer.load_waiting_on_load 120 # Number of times a load aliased with a pending load 2794system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2795system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits 2796system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses 2797system.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses 2798system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2799system.tccdir_cntrl0.directory.demand_hits 0 # Number of cache demand hits 2800system.tccdir_cntrl0.directory.demand_misses 0 # Number of cache demand misses 2801system.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses 2802system.tccdir_cntrl0.directory.num_tag_array_reads 1554 # number of tag array reads 2803system.tccdir_cntrl0.directory.num_tag_array_writes 27 # number of tag array writes 2804system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2805system.ruby.network.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2806system.ruby.network.msg_count.Control 3116 2807system.ruby.network.msg_count.Request_Control 3121 2808system.ruby.network.msg_count.Response_Data 3159 2809system.ruby.network.msg_count.Response_Control 3078 2810system.ruby.network.msg_count.Unblock_Control 3121 2811system.ruby.network.msg_byte.Control 24928 2812system.ruby.network.msg_byte.Request_Control 24968 2813system.ruby.network.msg_byte.Response_Data 227448 2814system.ruby.network.msg_byte.Response_Control 24624 2815system.ruby.network.msg_byte.Unblock_Control 24968 2816system.sqc_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2817system.sqc_coalescer.clk_domain.clock 1000 # Clock period in ticks 2818system.sqc_coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2819system.sqc_coalescer.uncoalesced_accesses 86 # Number of uncoalesced TLB accesses 2820system.sqc_coalescer.coalesced_accesses 60 # Number of coalesced TLB accesses 2821system.sqc_coalescer.queuing_cycles 108000 # Number of cycles spent in queue 2822system.sqc_coalescer.local_queuing_cycles 108000 # Number of cycles spent in queue for all incoming reqs 2823system.sqc_coalescer.local_latency 1255.813953 # Avg. latency over all incoming pkts 2824system.sqc_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2825system.sqc_tlb.clk_domain.clock 1000 # Clock period in ticks 2826system.sqc_tlb.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2827system.sqc_tlb.local_TLB_accesses 60 # Number of TLB accesses 2828system.sqc_tlb.local_TLB_hits 59 # Number of TLB hits 2829system.sqc_tlb.local_TLB_misses 1 # Number of TLB misses 2830system.sqc_tlb.local_TLB_miss_rate 1.666667 # TLB miss rate 2831system.sqc_tlb.global_TLB_accesses 86 # Number of TLB accesses 2832system.sqc_tlb.global_TLB_hits 78 # Number of TLB hits 2833system.sqc_tlb.global_TLB_misses 8 # Number of TLB misses 2834system.sqc_tlb.global_TLB_miss_rate 9.302326 # TLB miss rate 2835system.sqc_tlb.access_cycles 86008 # Cycles spent accessing this TLB level 2836system.sqc_tlb.page_table_cycles 0 # Cycles spent accessing the page table 2837system.sqc_tlb.unique_pages 1 # Number of unique pages touched 2838system.sqc_tlb.local_cycles 60001 # Number of cycles spent in queue for all incoming reqs 2839system.sqc_tlb.local_latency 1000.016667 # Avg. latency over incoming coalesced reqs 2840system.sqc_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 2841system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2842system.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.005553 2843system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1551 2844system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Data::2 12 2845system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2 1539 2846system.ruby.network.ext_links0.int_node.throttle0.msg_count.Unblock_Control::4 1551 2847system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0 12408 2848system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Data::2 864 2849system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Control::2 12312 2850system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Unblock_Control::4 12408 2851system.ruby.network.ext_links0.int_node.throttle1.link_utilization 0.016173 2852system.ruby.network.ext_links0.int_node.throttle1.msg_count.Control::0 16 2853system.ruby.network.ext_links0.int_node.throttle1.msg_count.Response_Data::2 1535 2854system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Control::0 128 2855system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Response_Data::2 110520 2856system.ruby.network.ext_links0.int_node.throttle2.link_utilization 0.001963 2857system.ruby.network.ext_links0.int_node.throttle2.msg_count.Control::0 1535 2858system.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Data::2 16 2859system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Control::0 12280 2860system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Data::2 1152 2861system.ruby.network.ext_links1.int_node.throttle0.link_utilization 0.016173 2862system.ruby.network.ext_links1.int_node.throttle0.msg_count.Control::0 16 2863system.ruby.network.ext_links1.int_node.throttle0.msg_count.Response_Data::2 1535 2864system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Control::0 128 2865system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Response_Data::2 110520 2866system.ruby.network.ext_links1.int_node.throttle1.link_utilization 0.003627 2867system.ruby.network.ext_links1.int_node.throttle1.msg_count.Request_Control::0 1535 2868system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Data::2 2 2869system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Control::2 14 2870system.ruby.network.ext_links1.int_node.throttle1.msg_count.Unblock_Control::4 1535 2871system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Request_Control::0 12280 2872system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Data::2 144 2873system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Control::2 112 2874system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Unblock_Control::4 12280 2875system.ruby.network.ext_links2.int_node.throttle0.link_utilization 0.000083 2876system.ruby.network.ext_links2.int_node.throttle0.msg_count.Control::1 8 2877system.ruby.network.ext_links2.int_node.throttle0.msg_count.Response_Data::3 7 2878system.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Control::1 64 2879system.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Response_Data::3 504 2880system.ruby.network.ext_links2.int_node.throttle1.link_utilization 0.000081 2881system.ruby.network.ext_links2.int_node.throttle1.msg_count.Control::1 6 2882system.ruby.network.ext_links2.int_node.throttle1.msg_count.Response_Data::3 7 2883system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Control::1 48 2884system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Response_Data::3 504 2885system.ruby.network.ext_links2.int_node.throttle2.link_utilization 0 2886system.ruby.network.ext_links2.int_node.throttle3.link_utilization 0.002155 2887system.ruby.network.ext_links2.int_node.throttle3.msg_count.Control::0 1535 2888system.ruby.network.ext_links2.int_node.throttle3.msg_count.Request_Control::1 19 2889system.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::2 16 2890system.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::3 14 2891system.ruby.network.ext_links2.int_node.throttle3.msg_count.Unblock_Control::5 19 2892system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Control::0 12280 2893system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Request_Control::1 152 2894system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Response_Data::2 1152 2895system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Response_Data::3 1008 2896system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Unblock_Control::5 152 2897system.ruby.network.ext_links2.int_node.throttle4.link_utilization 0.000053 2898system.ruby.network.ext_links2.int_node.throttle4.msg_count.Response_Data::3 5 2899system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Response_Data::3 360 2900system.ruby.network.ext_links2.int_node.throttle5.link_utilization 0.001926 2901system.ruby.network.ext_links2.int_node.throttle5.msg_count.Request_Control::0 16 2902system.ruby.network.ext_links2.int_node.throttle5.msg_count.Response_Data::2 10 2903system.ruby.network.ext_links2.int_node.throttle5.msg_count.Response_Control::2 1525 2904system.ruby.network.ext_links2.int_node.throttle5.msg_count.Unblock_Control::4 16 2905system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Request_Control::0 128 2906system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Response_Data::2 720 2907system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Response_Control::2 12200 2908system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Unblock_Control::4 128 2909system.ruby.CorePair_Controller.C0_Load_L1miss 180 0.00% 0.00% 2910system.ruby.CorePair_Controller.C0_Load_L1hit 16155 0.00% 0.00% 2911system.ruby.CorePair_Controller.Ifetch0_L1hit 86007 0.00% 0.00% 2912system.ruby.CorePair_Controller.Ifetch0_L1miss 1088 0.00% 0.00% 2913system.ruby.CorePair_Controller.C0_Store_L1miss 325 0.00% 0.00% 2914system.ruby.CorePair_Controller.C0_Store_L1hit 10448 0.00% 0.00% 2915system.ruby.CorePair_Controller.NB_AckS 1043 0.00% 0.00% 2916system.ruby.CorePair_Controller.NB_AckM 326 0.00% 0.00% 2917system.ruby.CorePair_Controller.NB_AckE 166 0.00% 0.00% 2918system.ruby.CorePair_Controller.L1I_Repl 589 0.00% 0.00% 2919system.ruby.CorePair_Controller.L1D0_Repl 24 0.00% 0.00% 2920system.ruby.CorePair_Controller.L2_to_L1D0 5 0.00% 0.00% 2921system.ruby.CorePair_Controller.L2_to_L1I 54 0.00% 0.00% 2922system.ruby.CorePair_Controller.PrbInvData 9 0.00% 0.00% 2923system.ruby.CorePair_Controller.PrbShrData 7 0.00% 0.00% 2924system.ruby.CorePair_Controller.I.C0_Load_L1miss 175 0.00% 0.00% 2925system.ruby.CorePair_Controller.I.Ifetch0_L1miss 1034 0.00% 0.00% 2926system.ruby.CorePair_Controller.I.C0_Store_L1miss 325 0.00% 0.00% 2927system.ruby.CorePair_Controller.I.PrbInvData 8 0.00% 0.00% 2928system.ruby.CorePair_Controller.I.PrbShrData 5 0.00% 0.00% 2929system.ruby.CorePair_Controller.S.C0_Load_L1hit 635 0.00% 0.00% 2930system.ruby.CorePair_Controller.S.Ifetch0_L1hit 86007 0.00% 0.00% 2931system.ruby.CorePair_Controller.S.Ifetch0_L1miss 54 0.00% 0.00% 2932system.ruby.CorePair_Controller.S.L1I_Repl 589 0.00% 0.00% 2933system.ruby.CorePair_Controller.E0.C0_Load_L1miss 2 0.00% 0.00% 2934system.ruby.CorePair_Controller.E0.C0_Load_L1hit 2721 0.00% 0.00% 2935system.ruby.CorePair_Controller.E0.C0_Store_L1hit 46 0.00% 0.00% 2936system.ruby.CorePair_Controller.E0.L1D0_Repl 16 0.00% 0.00% 2937system.ruby.CorePair_Controller.E0.PrbShrData 1 0.00% 0.00% 2938system.ruby.CorePair_Controller.O.C0_Load_L1hit 3 0.00% 0.00% 2939system.ruby.CorePair_Controller.O.C0_Store_L1hit 1 0.00% 0.00% 2940system.ruby.CorePair_Controller.M0.C0_Load_L1miss 3 0.00% 0.00% 2941system.ruby.CorePair_Controller.M0.C0_Load_L1hit 12796 0.00% 0.00% 2942system.ruby.CorePair_Controller.M0.C0_Store_L1hit 10401 0.00% 0.00% 2943system.ruby.CorePair_Controller.M0.L1D0_Repl 8 0.00% 0.00% 2944system.ruby.CorePair_Controller.M0.PrbInvData 1 0.00% 0.00% 2945system.ruby.CorePair_Controller.M0.PrbShrData 1 0.00% 0.00% 2946system.ruby.CorePair_Controller.I_M0.NB_AckM 325 0.00% 0.00% 2947system.ruby.CorePair_Controller.I_E0S.NB_AckS 9 0.00% 0.00% 2948system.ruby.CorePair_Controller.I_E0S.NB_AckE 166 0.00% 0.00% 2949system.ruby.CorePair_Controller.Si_F0.L2_to_L1I 54 0.00% 0.00% 2950system.ruby.CorePair_Controller.O_M0.NB_AckM 1 0.00% 0.00% 2951system.ruby.CorePair_Controller.S0.NB_AckS 1034 0.00% 0.00% 2952system.ruby.CorePair_Controller.E0_F.L2_to_L1D0 2 0.00% 0.00% 2953system.ruby.CorePair_Controller.M0_F.L2_to_L1D0 3 0.00% 0.00% 2954system.ruby.Directory_Controller.RdBlkS 1039 0.00% 0.00% 2955system.ruby.Directory_Controller.RdBlkM 335 0.00% 0.00% 2956system.ruby.Directory_Controller.RdBlk 177 0.00% 0.00% 2957system.ruby.Directory_Controller.CPUPrbResp 1551 0.00% 0.00% 2958system.ruby.Directory_Controller.ProbeAcksComplete 1551 0.00% 0.00% 2959system.ruby.Directory_Controller.MemData 1551 0.00% 0.00% 2960system.ruby.Directory_Controller.CoreUnblock 1551 0.00% 0.00% 2961system.ruby.Directory_Controller.U.RdBlkS 1039 0.00% 0.00% 2962system.ruby.Directory_Controller.U.RdBlkM 335 0.00% 0.00% 2963system.ruby.Directory_Controller.U.RdBlk 177 0.00% 0.00% 2964system.ruby.Directory_Controller.BS_M.MemData 36 0.00% 0.00% 2965system.ruby.Directory_Controller.BM_M.MemData 13 0.00% 0.00% 2966system.ruby.Directory_Controller.B_M.MemData 12 0.00% 0.00% 2967system.ruby.Directory_Controller.BS_PM.CPUPrbResp 36 0.00% 0.00% 2968system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 36 0.00% 0.00% 2969system.ruby.Directory_Controller.BS_PM.MemData 1003 0.00% 0.00% 2970system.ruby.Directory_Controller.BM_PM.CPUPrbResp 14 0.00% 0.00% 2971system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 13 0.00% 0.00% 2972system.ruby.Directory_Controller.BM_PM.MemData 322 0.00% 0.00% 2973system.ruby.Directory_Controller.B_PM.CPUPrbResp 12 0.00% 0.00% 2974system.ruby.Directory_Controller.B_PM.ProbeAcksComplete 12 0.00% 0.00% 2975system.ruby.Directory_Controller.B_PM.MemData 165 0.00% 0.00% 2976system.ruby.Directory_Controller.BS_Pm.CPUPrbResp 1003 0.00% 0.00% 2977system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 1003 0.00% 0.00% 2978system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 321 0.00% 0.00% 2979system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 322 0.00% 0.00% 2980system.ruby.Directory_Controller.B_Pm.CPUPrbResp 165 0.00% 0.00% 2981system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 165 0.00% 0.00% 2982system.ruby.Directory_Controller.B.CoreUnblock 1551 0.00% 0.00% 2983system.ruby.LD.latency_hist_seqr::bucket_size 64 2984system.ruby.LD.latency_hist_seqr::max_bucket 639 2985system.ruby.LD.latency_hist_seqr::samples 16335 2986system.ruby.LD.latency_hist_seqr::mean 4.314539 2987system.ruby.LD.latency_hist_seqr::gmean 2.104196 2988system.ruby.LD.latency_hist_seqr::stdev 22.794494 2989system.ruby.LD.latency_hist_seqr \| 16160 98.93% 98.93% \| 0 0.00% 98.93% \| 0 0.00% 98.93% \| 166 1.02% 99.94% \| 6 0.04% 99.98% \| 1 0.01% 99.99% \| 0 0.00% 99.99% \| 0 0.00% 99.99% \| 0 0.00% 99.99% \| 2 0.01% 100.00% 2990system.ruby.LD.latency_hist_seqr::total 16335 2991system.ruby.LD.latency_hist_coalsr::bucket_size 64 2992system.ruby.LD.latency_hist_coalsr::max_bucket 639 2993system.ruby.LD.latency_hist_coalsr::samples 9 2994system.ruby.LD.latency_hist_coalsr::mean 219.555556 2995system.ruby.LD.latency_hist_coalsr::gmean 24.880500 2996system.ruby.LD.latency_hist_coalsr::stdev 259.591078 2997system.ruby.LD.latency_hist_coalsr \| 5 55.56% 55.56% \| 0 0.00% 55.56% \| 0 0.00% 55.56% \| 0 0.00% 55.56% \| 0 0.00% 55.56% \| 0 0.00% 55.56% \| 1 11.11% 66.67% \| 1 11.11% 77.78% \| 2 22.22% 100.00% \| 0 0.00% 100.00% 2998system.ruby.LD.latency_hist_coalsr::total 9 2999system.ruby.LD.hit_latency_hist_seqr::bucket_size 64 3000system.ruby.LD.hit_latency_hist_seqr::max_bucket 639 3001system.ruby.LD.hit_latency_hist_seqr::samples 175 3002system.ruby.LD.hit_latency_hist_seqr::mean 217.531429 3003system.ruby.LD.hit_latency_hist_seqr::gmean 214.409561 3004system.ruby.LD.hit_latency_hist_seqr::stdev 50.482703 3005system.ruby.LD.hit_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 166 94.86% 94.86% \| 6 3.43% 98.29% \| 1 0.57% 98.86% \| 0 0.00% 98.86% \| 0 0.00% 98.86% \| 0 0.00% 98.86% \| 2 1.14% 100.00% 3006system.ruby.LD.hit_latency_hist_seqr::total 175 3007system.ruby.LD.miss_latency_hist_seqr::bucket_size 4 3008system.ruby.LD.miss_latency_hist_seqr::max_bucket 39 3009system.ruby.LD.miss_latency_hist_seqr::samples 16160 3010system.ruby.LD.miss_latency_hist_seqr::mean 2.005569 3011system.ruby.LD.miss_latency_hist_seqr::gmean 2.001425 3012system.ruby.LD.miss_latency_hist_seqr::stdev 0.316580 3013system.ruby.LD.miss_latency_hist_seqr \| 16155 99.97% 99.97% \| 0 0.00% 99.97% \| 0 0.00% 99.97% \| 0 0.00% 99.97% \| 0 0.00% 99.97% \| 5 0.03% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3014system.ruby.LD.miss_latency_hist_seqr::total 16160 3015system.ruby.LD.miss_latency_hist_coalsr::bucket_size 64 3016system.ruby.LD.miss_latency_hist_coalsr::max_bucket 639 3017system.ruby.LD.miss_latency_hist_coalsr::samples 9 3018system.ruby.LD.miss_latency_hist_coalsr::mean 219.555556 3019system.ruby.LD.miss_latency_hist_coalsr::gmean 24.880500 3020system.ruby.LD.miss_latency_hist_coalsr::stdev 259.591078 3021system.ruby.LD.miss_latency_hist_coalsr \| 5 55.56% 55.56% \| 0 0.00% 55.56% \| 0 0.00% 55.56% \| 0 0.00% 55.56% \| 0 0.00% 55.56% \| 0 0.00% 55.56% \| 1 11.11% 66.67% \| 1 11.11% 77.78% \| 2 22.22% 100.00% \| 0 0.00% 100.00% 3022system.ruby.LD.miss_latency_hist_coalsr::total 9 3023system.ruby.ST.latency_hist_seqr::bucket_size 64 3024system.ruby.ST.latency_hist_seqr::max_bucket 639 3025system.ruby.ST.latency_hist_seqr::samples 10412 3026system.ruby.ST.latency_hist_seqr::mean 8.469939 3027system.ruby.ST.latency_hist_seqr::gmean 2.309412 3028system.ruby.ST.latency_hist_seqr::stdev 36.833690 3029system.ruby.ST.latency_hist_seqr \| 10090 96.91% 96.91% \| 0 0.00% 96.91% \| 0 0.00% 96.91% \| 314 3.02% 99.92% \| 1 0.01% 99.93% \| 5 0.05% 99.98% \| 0 0.00% 99.98% \| 0 0.00% 99.98% \| 0 0.00% 99.98% \| 2 0.02% 100.00% 3030system.ruby.ST.latency_hist_seqr::total 10412 3031system.ruby.ST.latency_hist_coalsr::bucket_size 32 3032system.ruby.ST.latency_hist_coalsr::max_bucket 319 3033system.ruby.ST.latency_hist_coalsr::samples 16 3034system.ruby.ST.latency_hist_coalsr::mean 125.375000 3035system.ruby.ST.latency_hist_coalsr::gmean 15.802815 3036system.ruby.ST.latency_hist_coalsr::stdev 128.476133 3037system.ruby.ST.latency_hist_coalsr \| 8 50.00% 50.00% \| 0 0.00% 50.00% \| 0 0.00% 50.00% \| 0 0.00% 50.00% \| 0 0.00% 50.00% \| 0 0.00% 50.00% \| 0 0.00% 50.00% \| 7 43.75% 93.75% \| 1 6.25% 100.00% \| 0 0.00% 100.00% 3038system.ruby.ST.latency_hist_coalsr::total 16 3039system.ruby.ST.hit_latency_hist_seqr::bucket_size 64 3040system.ruby.ST.hit_latency_hist_seqr::max_bucket 639 3041system.ruby.ST.hit_latency_hist_seqr::samples 322 3042system.ruby.ST.hit_latency_hist_seqr::mean 211.208075 3043system.ruby.ST.hit_latency_hist_seqr::gmean 209.444324 3044system.ruby.ST.hit_latency_hist_seqr::stdev 38.157121 3045system.ruby.ST.hit_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 314 97.52% 97.52% \| 1 0.31% 97.83% \| 5 1.55% 99.38% \| 0 0.00% 99.38% \| 0 0.00% 99.38% \| 0 0.00% 99.38% \| 2 0.62% 100.00% 3046system.ruby.ST.hit_latency_hist_seqr::total 322 3047system.ruby.ST.miss_latency_hist_seqr::bucket_size 1 3048system.ruby.ST.miss_latency_hist_seqr::max_bucket 9 3049system.ruby.ST.miss_latency_hist_seqr::samples 10090 3050system.ruby.ST.miss_latency_hist_seqr::mean 2 3051system.ruby.ST.miss_latency_hist_seqr::gmean 2.000000 3052system.ruby.ST.miss_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 10090 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3053system.ruby.ST.miss_latency_hist_seqr::total 10090 3054system.ruby.ST.miss_latency_hist_coalsr::bucket_size 32 3055system.ruby.ST.miss_latency_hist_coalsr::max_bucket 319 3056system.ruby.ST.miss_latency_hist_coalsr::samples 16 3057system.ruby.ST.miss_latency_hist_coalsr::mean 125.375000 3058system.ruby.ST.miss_latency_hist_coalsr::gmean 15.802815 3059system.ruby.ST.miss_latency_hist_coalsr::stdev 128.476133 3060system.ruby.ST.miss_latency_hist_coalsr \| 8 50.00% 50.00% \| 0 0.00% 50.00% \| 0 0.00% 50.00% \| 0 0.00% 50.00% \| 0 0.00% 50.00% \| 0 0.00% 50.00% \| 0 0.00% 50.00% \| 7 43.75% 93.75% \| 1 6.25% 100.00% \| 0 0.00% 100.00% 3061system.ruby.ST.miss_latency_hist_coalsr::total 16 3062system.ruby.ATOMIC.latency_hist_coalsr::bucket_size 64 3063system.ruby.ATOMIC.latency_hist_coalsr::max_bucket 639 3064system.ruby.ATOMIC.latency_hist_coalsr::samples 2 3065system.ruby.ATOMIC.latency_hist_coalsr::mean 317.500000 3066system.ruby.ATOMIC.latency_hist_coalsr::gmean 314.366029 3067system.ruby.ATOMIC.latency_hist_coalsr::stdev 62.932504 3068system.ruby.ATOMIC.latency_hist_coalsr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 1 50.00% 50.00% \| 1 50.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3069system.ruby.ATOMIC.latency_hist_coalsr::total 2 3070system.ruby.ATOMIC.miss_latency_hist_coalsr::bucket_size 64 3071system.ruby.ATOMIC.miss_latency_hist_coalsr::max_bucket 639 3072system.ruby.ATOMIC.miss_latency_hist_coalsr::samples 2 3073system.ruby.ATOMIC.miss_latency_hist_coalsr::mean 317.500000 3074system.ruby.ATOMIC.miss_latency_hist_coalsr::gmean 314.366029 3075system.ruby.ATOMIC.miss_latency_hist_coalsr::stdev 62.932504 3076system.ruby.ATOMIC.miss_latency_hist_coalsr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 1 50.00% 50.00% \| 1 50.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3077system.ruby.ATOMIC.miss_latency_hist_coalsr::total 2 3078system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 3079system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 3080system.ruby.IFETCH.latency_hist_seqr::samples 87095 3081system.ruby.IFETCH.latency_hist_seqr::mean 4.485148 3082system.ruby.IFETCH.latency_hist_seqr::gmean 2.116532 3083system.ruby.IFETCH.latency_hist_seqr::stdev 22.815865 3084system.ruby.IFETCH.latency_hist_seqr \| 86061 98.81% 98.81% \| 0 0.00% 98.81% \| 0 0.00% 98.81% \| 1006 1.16% 99.97% \| 11 0.01% 99.98% \| 12 0.01% 99.99% \| 2 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 3 0.00% 100.00% 3085system.ruby.IFETCH.latency_hist_seqr::total 87095 3086system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 64 3087system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 639 3088system.ruby.IFETCH.hit_latency_hist_seqr::samples 1034 3089system.ruby.IFETCH.hit_latency_hist_seqr::mean 210.386847 3090system.ruby.IFETCH.hit_latency_hist_seqr::gmean 209.145816 3091system.ruby.IFETCH.hit_latency_hist_seqr::stdev 30.434753 3092system.ruby.IFETCH.hit_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 1006 97.29% 97.29% \| 11 1.06% 98.36% \| 12 1.16% 99.52% \| 2 0.19% 99.71% \| 0 0.00% 99.71% \| 0 0.00% 99.71% \| 3 0.29% 100.00% 3093system.ruby.IFETCH.hit_latency_hist_seqr::total 1034 3094system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 4 3095system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 39 3096system.ruby.IFETCH.miss_latency_hist_seqr::samples 86061 3097system.ruby.IFETCH.miss_latency_hist_seqr::mean 2.011294 3098system.ruby.IFETCH.miss_latency_hist_seqr::gmean 2.002892 3099system.ruby.IFETCH.miss_latency_hist_seqr::stdev 0.450747 3100system.ruby.IFETCH.miss_latency_hist_seqr \| 86007 99.94% 99.94% \| 0 0.00% 99.94% \| 0 0.00% 99.94% \| 0 0.00% 99.94% \| 0 0.00% 99.94% \| 54 0.06% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3101system.ruby.IFETCH.miss_latency_hist_seqr::total 86061 3102system.ruby.RMW_Read.latency_hist_seqr::bucket_size 32 3103system.ruby.RMW_Read.latency_hist_seqr::max_bucket 319 3104system.ruby.RMW_Read.latency_hist_seqr::samples 341 3105system.ruby.RMW_Read.latency_hist_seqr::mean 4.392962 3106system.ruby.RMW_Read.latency_hist_seqr::gmean 2.111743 3107system.ruby.RMW_Read.latency_hist_seqr::stdev 21.996747 3108system.ruby.RMW_Read.latency_hist_seqr \| 337 98.83% 98.83% \| 0 0.00% 98.83% \| 0 0.00% 98.83% \| 0 0.00% 98.83% \| 0 0.00% 98.83% \| 0 0.00% 98.83% \| 4 1.17% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3109system.ruby.RMW_Read.latency_hist_seqr::total 341 3110system.ruby.RMW_Read.hit_latency_hist_seqr::bucket_size 32 3111system.ruby.RMW_Read.hit_latency_hist_seqr::max_bucket 319 3112system.ruby.RMW_Read.hit_latency_hist_seqr::samples 4 3113system.ruby.RMW_Read.hit_latency_hist_seqr::mean 206 3114system.ruby.RMW_Read.hit_latency_hist_seqr::gmean 206.000000 3115system.ruby.RMW_Read.hit_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 4 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3116system.ruby.RMW_Read.hit_latency_hist_seqr::total 4 3117system.ruby.RMW_Read.miss_latency_hist_seqr::bucket_size 1 3118system.ruby.RMW_Read.miss_latency_hist_seqr::max_bucket 9 3119system.ruby.RMW_Read.miss_latency_hist_seqr::samples 337 3120system.ruby.RMW_Read.miss_latency_hist_seqr::mean 2 3121system.ruby.RMW_Read.miss_latency_hist_seqr::gmean 2.000000 3122system.ruby.RMW_Read.miss_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 337 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3123system.ruby.RMW_Read.miss_latency_hist_seqr::total 337 3124system.ruby.Locked_RMW_Read.latency_hist_seqr::bucket_size 1 3125system.ruby.Locked_RMW_Read.latency_hist_seqr::max_bucket 9 3126system.ruby.Locked_RMW_Read.latency_hist_seqr::samples 10 3127system.ruby.Locked_RMW_Read.latency_hist_seqr::mean 2 3128system.ruby.Locked_RMW_Read.latency_hist_seqr::gmean 2 3129system.ruby.Locked_RMW_Read.latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 10 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3130system.ruby.Locked_RMW_Read.latency_hist_seqr::total 10 3131system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::bucket_size 1 3132system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::max_bucket 9 3133system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::samples 10 3134system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::mean 2 3135system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::gmean 2 3136system.ruby.Locked_RMW_Read.miss_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 10 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3137system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::total 10 3138system.ruby.Locked_RMW_Write.latency_hist_seqr::bucket_size 1 3139system.ruby.Locked_RMW_Write.latency_hist_seqr::max_bucket 9 3140system.ruby.Locked_RMW_Write.latency_hist_seqr::samples 10 3141system.ruby.Locked_RMW_Write.latency_hist_seqr::mean 2 3142system.ruby.Locked_RMW_Write.latency_hist_seqr::gmean 2 3143system.ruby.Locked_RMW_Write.latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 10 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3144system.ruby.Locked_RMW_Write.latency_hist_seqr::total 10 3145system.ruby.Locked_RMW_Write.miss_latency_hist_seqr::bucket_size 1 3146system.ruby.Locked_RMW_Write.miss_latency_hist_seqr::max_bucket 9 3147system.ruby.Locked_RMW_Write.miss_latency_hist_seqr::samples 10 3148system.ruby.Locked_RMW_Write.miss_latency_hist_seqr::mean 2 3149system.ruby.Locked_RMW_Write.miss_latency_hist_seqr::gmean 2 3150system.ruby.Locked_RMW_Write.miss_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 10 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3151system.ruby.Locked_RMW_Write.miss_latency_hist_seqr::total 10 3152system.ruby.L1Cache.miss_mach_latency_hist_seqr::bucket_size 1 3153system.ruby.L1Cache.miss_mach_latency_hist_seqr::max_bucket 9 3154system.ruby.L1Cache.miss_mach_latency_hist_seqr::samples 112609 3155system.ruby.L1Cache.miss_mach_latency_hist_seqr::mean 2 3156system.ruby.L1Cache.miss_mach_latency_hist_seqr::gmean 2.000000 3157system.ruby.L1Cache.miss_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 112609 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3158system.ruby.L1Cache.miss_mach_latency_hist_seqr::total 112609 3159system.ruby.L2Cache.miss_mach_latency_hist_seqr::bucket_size 4 3160system.ruby.L2Cache.miss_mach_latency_hist_seqr::max_bucket 39 3161system.ruby.L2Cache.miss_mach_latency_hist_seqr::samples 59 3162system.ruby.L2Cache.miss_mach_latency_hist_seqr::mean 20 3163system.ruby.L2Cache.miss_mach_latency_hist_seqr::gmean 20.000000 3164system.ruby.L2Cache.miss_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 59 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3165system.ruby.L2Cache.miss_mach_latency_hist_seqr::total 59 3166system.ruby.Directory.hit_mach_latency_hist_seqr::bucket_size 64 3167system.ruby.Directory.hit_mach_latency_hist_seqr::max_bucket 639 3168system.ruby.Directory.hit_mach_latency_hist_seqr::samples 1535 3169system.ruby.Directory.hit_mach_latency_hist_seqr::mean 211.362215 3170system.ruby.Directory.hit_mach_latency_hist_seqr::gmean 209.793806 3171system.ruby.Directory.hit_mach_latency_hist_seqr::stdev 34.965177 3172system.ruby.Directory.hit_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 1490 97.07% 97.07% \| 18 1.17% 98.24% \| 18 1.17% 99.41% \| 2 0.13% 99.54% \| 0 0.00% 99.54% \| 0 0.00% 99.54% \| 7 0.46% 100.00% 3173system.ruby.Directory.hit_mach_latency_hist_seqr::total 1535 3174system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::bucket_size 64 3175system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::max_bucket 639 3176system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::samples 3 3177system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean 478.666667 3178system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 470.839796 3179system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 101.159939 3180system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 1 33.33% 33.33% \| 0 0.00% 33.33% \| 0 0.00% 33.33% \| 2 66.67% 100.00% \| 0 0.00% 100.00% 3181system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::total 3 3182system.ruby.TCP.miss_mach_latency_hist_coalsr::bucket_size 1 3183system.ruby.TCP.miss_mach_latency_hist_coalsr::max_bucket 9 3184system.ruby.TCP.miss_mach_latency_hist_coalsr::samples 13 3185system.ruby.TCP.miss_mach_latency_hist_coalsr::mean 1.538462 3186system.ruby.TCP.miss_mach_latency_hist_coalsr::gmean 1.377009 3187system.ruby.TCP.miss_mach_latency_hist_coalsr::stdev 0.877058 3188system.ruby.TCP.miss_mach_latency_hist_coalsr \| 0 0.00% 0.00% \| 8 61.54% 61.54% \| 4 30.77% 92.31% \| 0 0.00% 92.31% \| 1 7.69% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3189system.ruby.TCP.miss_mach_latency_hist_coalsr::total 13 3190system.ruby.TCCdir.miss_mach_latency_hist_coalsr::bucket_size 64 3191system.ruby.TCCdir.miss_mach_latency_hist_coalsr::max_bucket 639 3192system.ruby.TCCdir.miss_mach_latency_hist_coalsr::samples 11 3193system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 287.363636 3194system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 279.637814 3195system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 78.345737 3196system.ruby.TCCdir.miss_mach_latency_hist_coalsr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 7 63.64% 63.64% \| 2 18.18% 81.82% \| 0 0.00% 81.82% \| 1 9.09% 90.91% \| 1 9.09% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3197system.ruby.TCCdir.miss_mach_latency_hist_coalsr::total 11 3198system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 3199system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 3200system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::samples 16155 3201system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 3202system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000 3203system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 16155 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3204system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::total 16155 3205system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::bucket_size 4 3206system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::max_bucket 39 3207system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::samples 5 3208system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::mean 20 3209system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::gmean 20.000000 3210system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 5 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3211system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::total 5 3212system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::bucket_size 64 3213system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::max_bucket 639 3214system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::samples 175 3215system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::mean 217.531429 3216system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::gmean 214.409561 3217system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::stdev 50.482703 3218system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 166 94.86% 94.86% \| 6 3.43% 98.29% \| 1 0.57% 98.86% \| 0 0.00% 98.86% \| 0 0.00% 98.86% \| 0 0.00% 98.86% \| 2 1.14% 100.00% 3219system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::total 175 3220system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64 3221system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639 3222system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 2 3223system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 537 3224system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 536.976722 3225system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev 7.071068 3226system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 2 100.00% 100.00% \| 0 0.00% 100.00% 3227system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 2 3228system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 3229system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 3230system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::samples 5 3231system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::mean 2.400000 3232system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::gmean 2.297397 3233system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::stdev 0.894427 3234system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 4 80.00% 80.00% \| 0 0.00% 80.00% \| 1 20.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3235system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::total 5 3236system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 64 3237system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 639 3238system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::samples 2 3239system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean 445 3240system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 444.959549 3241system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 8.485281 3242system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 1 50.00% 50.00% \| 1 50.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3243system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::total 2 3244system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 3245system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 3246system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::samples 10090 3247system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 3248system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000 3249system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 10090 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3250system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::total 10090 3251system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::bucket_size 64 3252system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::max_bucket 639 3253system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::samples 322 3254system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::mean 211.208075 3255system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::gmean 209.444324 3256system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::stdev 38.157121 3257system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 314 97.52% 97.52% \| 1 0.31% 97.83% \| 5 1.55% 99.38% \| 0 0.00% 99.38% \| 0 0.00% 99.38% \| 0 0.00% 99.38% \| 2 0.62% 100.00% 3258system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::total 322 3259system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 3260system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 3261system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::samples 8 3262system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::mean 1 3263system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::gmean 1 3264system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr \| 0 0.00% 0.00% \| 8 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3265system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::total 8 3266system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32 3267system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319 3268system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::samples 8 3269system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 249.750000 3270system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 249.728954 3271system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 3.494894 3272system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 7 87.50% 87.50% \| 1 12.50% 100.00% \| 0 0.00% 100.00% 3273system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::total 8 3274system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64 3275system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639 3276system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 1 3277system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 362 3278system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 362.000000 3279system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev nan 3280system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 1 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3281system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 1 3282system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32 3283system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319 3284system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::samples 1 3285system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::mean 273 3286system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 273 3287system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::stdev nan 3288system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 1 100.00% 100.00% \| 0 0.00% 100.00% 3289system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::total 1 3290system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 3291system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 3292system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::samples 86007 3293system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 3294system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000 3295system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 86007 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3296system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::total 86007 3297system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::bucket_size 4 3298system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::max_bucket 39 3299system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::samples 54 3300system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::mean 20 3301system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::gmean 20.000000 3302system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 54 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3303system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::total 54 3304system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::bucket_size 64 3305system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::max_bucket 639 3306system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::samples 1034 3307system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::mean 210.386847 3308system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::gmean 209.145816 3309system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::stdev 30.434753 3310system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 1006 97.29% 97.29% \| 11 1.06% 98.36% \| 12 1.16% 99.52% \| 2 0.19% 99.71% \| 0 0.00% 99.71% \| 0 0.00% 99.71% \| 3 0.29% 100.00% 3311system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::total 1034 3312system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 3313system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 3314system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::samples 337 3315system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 3316system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000 3317system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 337 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3318system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::total 337 3319system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::bucket_size 32 3320system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::max_bucket 319 3321system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::samples 4 3322system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::mean 206 3323system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::gmean 206.000000 3324system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 4 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3325system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::total 4 3326system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 3327system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 3328system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::samples 10 3329system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 3330system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2 3331system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 10 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3332system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::total 10 3333system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 3334system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 3335system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::samples 10 3336system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 3337system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2 3338system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 10 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3339system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::total 10 3340system.ruby.SQC_Controller.Fetch 86 0.00% 0.00% 3341system.ruby.SQC_Controller.TCC_AckS 5 0.00% 0.00% 3342system.ruby.SQC_Controller.I.Fetch 5 0.00% 0.00% 3343system.ruby.SQC_Controller.S.Fetch 81 0.00% 0.00% 3344system.ruby.SQC_Controller.I_S.TCC_AckS 5 0.00% 0.00% 3345system.ruby.TCCdir_Controller.RdBlk 93 0.00% 0.00% 3346system.ruby.TCCdir_Controller.RdBlkM 37 0.00% 0.00% 3347system.ruby.TCCdir_Controller.RdBlkS 5 0.00% 0.00% 3348system.ruby.TCCdir_Controller.CPUPrbResp 14 0.00% 0.00% 3349system.ruby.TCCdir_Controller.ProbeAcksComplete 13 0.00% 0.00% 3350system.ruby.TCCdir_Controller.CoreUnblock 17 0.00% 0.00% 3351system.ruby.TCCdir_Controller.LastCoreUnblock 2 0.00% 0.00% 3352system.ruby.TCCdir_Controller.NB_AckS 7 0.00% 0.00% 3353system.ruby.TCCdir_Controller.NB_AckM 9 0.00% 0.00% 3354system.ruby.TCCdir_Controller.PrbInvData 326 0.00% 0.00% 3355system.ruby.TCCdir_Controller.PrbShrData 1209 0.00% 0.00% 3356system.ruby.TCCdir_Controller.I.RdBlk 2 0.00% 0.00% 3357system.ruby.TCCdir_Controller.I.RdBlkM 9 0.00% 0.00% 3358system.ruby.TCCdir_Controller.I.RdBlkS 5 0.00% 0.00% 3359system.ruby.TCCdir_Controller.I.PrbInvData 325 0.00% 0.00% 3360system.ruby.TCCdir_Controller.I.PrbShrData 1200 0.00% 0.00% 3361system.ruby.TCCdir_Controller.S.RdBlk 2 0.00% 0.00% 3362system.ruby.TCCdir_Controller.S.PrbInvData 1 0.00% 0.00% 3363system.ruby.TCCdir_Controller.M.RdBlkM 1 0.00% 0.00% 3364system.ruby.TCCdir_Controller.M.PrbShrData 9 0.00% 0.00% 3365system.ruby.TCCdir_Controller.CP_I.CPUPrbResp 2 0.00% 0.00% 3366system.ruby.TCCdir_Controller.CP_I.ProbeAcksComplete 1 0.00% 0.00% 3367system.ruby.TCCdir_Controller.CP_O.CPUPrbResp 9 0.00% 0.00% 3368system.ruby.TCCdir_Controller.CP_O.ProbeAcksComplete 9 0.00% 0.00% 3369system.ruby.TCCdir_Controller.I_M.RdBlkM 22 0.00% 0.00% 3370system.ruby.TCCdir_Controller.I_M.NB_AckM 9 0.00% 0.00% 3371system.ruby.TCCdir_Controller.I_ES.RdBlk 79 0.00% 0.00% 3372system.ruby.TCCdir_Controller.I_ES.NB_AckS 2 0.00% 0.00% 3373system.ruby.TCCdir_Controller.I_S.NB_AckS 5 0.00% 0.00% 3374system.ruby.TCCdir_Controller.BBS_S.CPUPrbResp 2 0.00% 0.00% 3375system.ruby.TCCdir_Controller.BBS_S.ProbeAcksComplete 2 0.00% 0.00% 3376system.ruby.TCCdir_Controller.BBM_M.CPUPrbResp 1 0.00% 0.00% 3377system.ruby.TCCdir_Controller.BBM_M.ProbeAcksComplete 1 0.00% 0.00% 3378system.ruby.TCCdir_Controller.BB_M.CoreUnblock 1 0.00% 0.00% 3379system.ruby.TCCdir_Controller.BB_S.LastCoreUnblock 2 0.00% 0.00% 3380system.ruby.TCCdir_Controller.BBB_S.RdBlk 10 0.00% 0.00% 3381system.ruby.TCCdir_Controller.BBB_S.CoreUnblock 7 0.00% 0.00% 3382system.ruby.TCCdir_Controller.BBB_M.RdBlkM 5 0.00% 0.00% 3383system.ruby.TCCdir_Controller.BBB_M.CoreUnblock 9 0.00% 0.00% 3384system.ruby.TCP_Controller.Load \| 4 44.44% 44.44% \| 5 55.56% 100.00% 3385system.ruby.TCP_Controller.Load::total 9 3386system.ruby.TCP_Controller.Store \| 9 50.00% 50.00% \| 9 50.00% 100.00% 3387system.ruby.TCP_Controller.Store::total 18 3388system.ruby.TCP_Controller.TCC_AckS \| 2 50.00% 50.00% \| 2 50.00% 100.00% 3389system.ruby.TCP_Controller.TCC_AckS::total 4 3390system.ruby.TCP_Controller.TCC_AckM \| 5 50.00% 50.00% \| 5 50.00% 100.00% 3391system.ruby.TCP_Controller.TCC_AckM::total 10 3392system.ruby.TCP_Controller.PrbInvData \| 1 33.33% 33.33% \| 2 66.67% 100.00% 3393system.ruby.TCP_Controller.PrbInvData::total 3 3394system.ruby.TCP_Controller.PrbShrData \| 7 63.64% 63.64% \| 4 36.36% 100.00% 3395system.ruby.TCP_Controller.PrbShrData::total 11 3396system.ruby.TCP_Controller.I.Load \| 2 50.00% 50.00% \| 2 50.00% 100.00% 3397system.ruby.TCP_Controller.I.Load::total 4 3398system.ruby.TCP_Controller.I.Store \| 5 50.00% 50.00% \| 5 50.00% 100.00% 3399system.ruby.TCP_Controller.I.Store::total 10 3400system.ruby.TCP_Controller.S.Load \| 2 40.00% 40.00% \| 3 60.00% 100.00% 3401system.ruby.TCP_Controller.S.Load::total 5 3402system.ruby.TCP_Controller.S.PrbInvData \| 1 50.00% 50.00% \| 1 50.00% 100.00% 3403system.ruby.TCP_Controller.S.PrbInvData::total 2 3404system.ruby.TCP_Controller.S.PrbShrData \| 2 100.00% 100.00% \| 0 0.00% 100.00% 3405system.ruby.TCP_Controller.S.PrbShrData::total 2 3406system.ruby.TCP_Controller.M.Store \| 4 50.00% 50.00% \| 4 50.00% 100.00% 3407system.ruby.TCP_Controller.M.Store::total 8 3408system.ruby.TCP_Controller.M.PrbInvData \| 0 0.00% 0.00% \| 1 100.00% 100.00% 3409system.ruby.TCP_Controller.M.PrbInvData::total 1 3410system.ruby.TCP_Controller.M.PrbShrData \| 5 55.56% 55.56% \| 4 44.44% 100.00% 3411system.ruby.TCP_Controller.M.PrbShrData::total 9 3412system.ruby.TCP_Controller.I_M.TCC_AckM \| 5 50.00% 50.00% \| 5 50.00% 100.00% 3413system.ruby.TCP_Controller.I_M.TCC_AckM::total 10 3414system.ruby.TCP_Controller.I_ES.TCC_AckS \| 2 50.00% 50.00% \| 2 50.00% 100.00% 3415system.ruby.TCP_Controller.I_ES.TCC_AckS::total 4 3416 3417---------- End Simulation Statistics ----------	461system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 462system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 463system.cpu0.op_class::total 137705 # Class of executed instruction 464system.cpu1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 465system.cpu1.clk_domain.clock 1000 # Clock period in ticks 466system.cpu1.CUs0.localDataStore.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 467system.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 468system.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 469system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 498 # number of times the wf's instructions are blocked due to RAW dependencies 470system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands 471system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands 472system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands 473system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 474system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands 475system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands 476system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 477system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 478system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 479system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 480system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::total 39 # number of executed instructions with N source register operands 481system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::samples 39 # number of executed instructions with N destination register operands 482system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::mean 0.589744 # number of executed instructions with N destination register operands 483system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::stdev 0.498310 # number of executed instructions with N destination register operands 484system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 485system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00% # number of executed instructions with N destination register operands 486system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 487system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 488system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 489system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 490system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::total 39 # number of executed instructions with N destination register operands 491system.cpu1.CUs0.wavefronts01.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 492system.cpu1.CUs0.wavefronts01.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 493system.cpu1.CUs0.wavefronts01.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 494system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 495system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 496system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 497system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 498system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 499system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 500system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 501system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 502system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 503system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 504system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 505system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 506system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 507system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 508system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 509system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 510system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 511system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 512system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 513system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 514system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 515system.cpu1.CUs0.wavefronts02.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 516system.cpu1.CUs0.wavefronts02.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 517system.cpu1.CUs0.wavefronts02.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 518system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 519system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 520system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 521system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 522system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 523system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 524system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 525system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 526system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 527system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 528system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 529system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 530system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 531system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 532system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 533system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 534system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 535system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 536system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 537system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 538system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 539system.cpu1.CUs0.wavefronts03.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 540system.cpu1.CUs0.wavefronts03.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 541system.cpu1.CUs0.wavefronts03.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 542system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 543system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 544system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 545system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 546system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 547system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 548system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 549system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 550system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 551system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 552system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 553system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 554system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 555system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 556system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 557system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 558system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 559system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 560system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 561system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 562system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 563system.cpu1.CUs0.wavefronts04.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 564system.cpu1.CUs0.wavefronts04.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 565system.cpu1.CUs0.wavefronts04.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 566system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 567system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 568system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 569system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 570system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 571system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 572system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 573system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 574system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 575system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 576system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 577system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 578system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 579system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 580system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 581system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 582system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 583system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 584system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 585system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 586system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 587system.cpu1.CUs0.wavefronts05.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 588system.cpu1.CUs0.wavefronts05.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 589system.cpu1.CUs0.wavefronts05.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 590system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 591system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 592system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 593system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 594system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 595system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 596system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 597system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 598system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 599system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 600system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 601system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 602system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 603system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 604system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 605system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 606system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 607system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 608system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 609system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 610system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 611system.cpu1.CUs0.wavefronts06.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 612system.cpu1.CUs0.wavefronts06.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 613system.cpu1.CUs0.wavefronts06.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 614system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 615system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 616system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 617system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 618system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 619system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 620system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 621system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 622system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 623system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 624system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 625system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 626system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 627system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 628system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 629system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 630system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 631system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 632system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 633system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 634system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 635system.cpu1.CUs0.wavefronts07.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 636system.cpu1.CUs0.wavefronts07.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 637system.cpu1.CUs0.wavefronts07.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 638system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 639system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 640system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 641system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 642system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 643system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 644system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 645system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 646system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 647system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 648system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 649system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 650system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 651system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 652system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 653system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 654system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 655system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 656system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 657system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 658system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 659system.cpu1.CUs0.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 660system.cpu1.CUs0.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 661system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 470 # number of times the wf's instructions are blocked due to RAW dependencies 662system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 663system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 664system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 665system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 666system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 667system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 668system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 669system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 670system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 671system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 672system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 673system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 674system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 675system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 676system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 677system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 678system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 679system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 680system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 681system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 682system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 683system.cpu1.CUs0.wavefronts09.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 684system.cpu1.CUs0.wavefronts09.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 685system.cpu1.CUs0.wavefronts09.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 686system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 687system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 688system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 689system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 690system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 691system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 692system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 693system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 694system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 695system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 696system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 697system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 698system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 699system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 700system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 701system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 702system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 703system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 704system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 705system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 706system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 707system.cpu1.CUs0.wavefronts10.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 708system.cpu1.CUs0.wavefronts10.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 709system.cpu1.CUs0.wavefronts10.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 710system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 711system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 712system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 713system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 714system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 715system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 716system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 717system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 718system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 719system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 720system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 721system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 722system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 723system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 724system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 725system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 726system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 727system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 728system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 729system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 730system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 731system.cpu1.CUs0.wavefronts11.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 732system.cpu1.CUs0.wavefronts11.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 733system.cpu1.CUs0.wavefronts11.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 734system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 735system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 736system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 737system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 738system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 739system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 740system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 741system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 742system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 743system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 744system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 745system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 746system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 747system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 748system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 749system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 750system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 751system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 752system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 753system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 754system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 755system.cpu1.CUs0.wavefronts12.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 756system.cpu1.CUs0.wavefronts12.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 757system.cpu1.CUs0.wavefronts12.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 758system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 759system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 760system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 761system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 762system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 763system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 764system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 765system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 766system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 767system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 768system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 769system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 770system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 771system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 772system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 773system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 774system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 775system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 776system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 777system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 778system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 779system.cpu1.CUs0.wavefronts13.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 780system.cpu1.CUs0.wavefronts13.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 781system.cpu1.CUs0.wavefronts13.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 782system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 783system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 784system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 785system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 786system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 787system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 788system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 789system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 790system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 791system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 792system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 793system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 794system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 795system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 796system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 797system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 798system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 799system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 800system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 801system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 802system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 803system.cpu1.CUs0.wavefronts14.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 804system.cpu1.CUs0.wavefronts14.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 805system.cpu1.CUs0.wavefronts14.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 806system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 807system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 808system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 809system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 810system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 811system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 812system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 813system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 814system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 815system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 816system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 817system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 818system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 819system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 820system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 821system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 822system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 823system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 824system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 825system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 826system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 827system.cpu1.CUs0.wavefronts15.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 828system.cpu1.CUs0.wavefronts15.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 829system.cpu1.CUs0.wavefronts15.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 830system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 831system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 832system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 833system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 834system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 835system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 836system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 837system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 838system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 839system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 840system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 841system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 842system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 843system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 844system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 845system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 846system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 847system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 848system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 849system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 850system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 851system.cpu1.CUs0.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 852system.cpu1.CUs0.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 853system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 473 # number of times the wf's instructions are blocked due to RAW dependencies 854system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 855system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 856system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 857system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 858system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 859system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 860system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 861system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 862system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 863system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 864system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 865system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 866system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 867system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 868system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 869system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 870system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 871system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 872system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 873system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 874system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 875system.cpu1.CUs0.wavefronts17.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 876system.cpu1.CUs0.wavefronts17.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 877system.cpu1.CUs0.wavefronts17.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 878system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 879system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 880system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 881system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 882system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 883system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 884system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 885system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 886system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 887system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 888system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 889system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 890system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 891system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 892system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 893system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 894system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 895system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 896system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 897system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 898system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 899system.cpu1.CUs0.wavefronts18.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 900system.cpu1.CUs0.wavefronts18.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 901system.cpu1.CUs0.wavefronts18.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 902system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 903system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 904system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 905system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 906system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 907system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 908system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 909system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 910system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 911system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 912system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 913system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 914system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 915system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 916system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 917system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 918system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 919system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 920system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 921system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 922system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 923system.cpu1.CUs0.wavefronts19.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 924system.cpu1.CUs0.wavefronts19.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 925system.cpu1.CUs0.wavefronts19.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 926system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 927system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 928system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 929system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 930system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 931system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 932system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 933system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 934system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 935system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 936system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 937system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 938system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 939system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 940system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 941system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 942system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 943system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 944system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 945system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 946system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 947system.cpu1.CUs0.wavefronts20.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 948system.cpu1.CUs0.wavefronts20.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 949system.cpu1.CUs0.wavefronts20.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 950system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 951system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 952system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 953system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 954system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 955system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 956system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 957system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 958system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 959system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 960system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 961system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 962system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 963system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 964system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 965system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 966system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 967system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 968system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 969system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 970system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 971system.cpu1.CUs0.wavefronts21.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 972system.cpu1.CUs0.wavefronts21.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 973system.cpu1.CUs0.wavefronts21.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 974system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 975system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 976system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 977system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 978system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 979system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 980system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 981system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 982system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 983system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 984system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 985system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 986system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 987system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 988system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 989system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 990system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 991system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 992system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 993system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 994system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 995system.cpu1.CUs0.wavefronts22.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 996system.cpu1.CUs0.wavefronts22.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 997system.cpu1.CUs0.wavefronts22.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 998system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 999system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1000system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1001system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1002system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1003system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1004system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1005system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1006system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1007system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1008system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1009system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1010system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1011system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1012system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1013system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1014system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1015system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1016system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1017system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1018system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1019system.cpu1.CUs0.wavefronts23.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1020system.cpu1.CUs0.wavefronts23.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1021system.cpu1.CUs0.wavefronts23.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1022system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1023system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1024system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1025system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1026system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1027system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1028system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1029system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1030system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1031system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1032system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1033system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1034system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1035system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1036system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1037system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1038system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1039system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1040system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1041system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1042system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1043system.cpu1.CUs0.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1044system.cpu1.CUs0.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1045system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 467 # number of times the wf's instructions are blocked due to RAW dependencies 1046system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 1047system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 1048system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 1049system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 1050system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 1051system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 1052system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 1053system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 1054system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1055system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 1056system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 1057system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 1058system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 1059system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 1060system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 1061system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 1062system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 1063system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 1064system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1065system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 1066system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 1067system.cpu1.CUs0.wavefronts25.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1068system.cpu1.CUs0.wavefronts25.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1069system.cpu1.CUs0.wavefronts25.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1070system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1071system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1072system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1073system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1074system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1075system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1076system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1077system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1078system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1079system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1080system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1081system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1082system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1083system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1084system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1085system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1086system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1087system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1088system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1089system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1090system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1091system.cpu1.CUs0.wavefronts26.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1092system.cpu1.CUs0.wavefronts26.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1093system.cpu1.CUs0.wavefronts26.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1094system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1095system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1096system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1097system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1098system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1099system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1100system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1101system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1102system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1103system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1104system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1105system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1106system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1107system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1108system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1109system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1110system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1111system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1112system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1113system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1114system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1115system.cpu1.CUs0.wavefronts27.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1116system.cpu1.CUs0.wavefronts27.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1117system.cpu1.CUs0.wavefronts27.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1118system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1119system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1120system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1121system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1122system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1123system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1124system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1125system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1126system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1127system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1128system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1129system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1130system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1131system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1132system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1133system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1134system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1135system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1136system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1137system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1138system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1139system.cpu1.CUs0.wavefronts28.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1140system.cpu1.CUs0.wavefronts28.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1141system.cpu1.CUs0.wavefronts28.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1142system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1143system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1144system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1145system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1146system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1147system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1148system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1149system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1150system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1151system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1152system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1153system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1154system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1155system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1156system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1157system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1158system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1159system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1160system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1161system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1162system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1163system.cpu1.CUs0.wavefronts29.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1164system.cpu1.CUs0.wavefronts29.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1165system.cpu1.CUs0.wavefronts29.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1166system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1167system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1168system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1169system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1170system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1171system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1172system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1173system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1174system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1175system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1176system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1177system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1178system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1179system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1180system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1181system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1182system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1183system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1184system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1185system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1186system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1187system.cpu1.CUs0.wavefronts30.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1188system.cpu1.CUs0.wavefronts30.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1189system.cpu1.CUs0.wavefronts30.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1190system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1191system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1192system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1193system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1194system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1195system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1196system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1197system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1198system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1199system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1200system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1201system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1202system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1203system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1204system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1205system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1206system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1207system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1208system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1209system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1210system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1211system.cpu1.CUs0.wavefronts31.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1212system.cpu1.CUs0.wavefronts31.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1213system.cpu1.CUs0.wavefronts31.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1214system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1215system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1216system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1217system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1218system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1219system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1220system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1221system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1222system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1223system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1224system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1225system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1226system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1227system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1228system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1229system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1230system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1231system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1232system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1233system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1234system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1235system.cpu1.CUs0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 1236system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it 1237system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it 1238system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it 1239system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 1240system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 1241system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it 1242system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it 1243system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it 1244system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it 1245system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it 1246system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it 1247system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1248system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1249system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1250system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1251system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1252system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1253system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1254system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1255system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1256system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1257system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1258system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1259system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1260system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1261system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1262system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1263system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1264system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1265system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1266system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1267system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1268system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1269system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1270system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1271system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1272system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 1273system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it 1274system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it 1275system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it 1276system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 3471 # number of cycles the CU issues nothing 1277system.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued 99 # number of cycles the CU issued at least one instruction 1278system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued 1279system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued 1280system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued 1281system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued 1282system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued 1283system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued 1284system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 970 # Number of cycles no instruction of specific type issued 1285system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 548 # Number of cycles no instruction of specific type issued 1286system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 566 # Number of cycles no instruction of specific type issued 1287system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 523 # Number of cycles no instruction of specific type issued 1288system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 398 # Number of cycles no instruction of specific type issued 1289system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM 22 # Number of cycles no instruction of specific type issued 1290system.cpu1.CUs0.ExecStage.spc::samples 3570 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1291system.cpu1.CUs0.ExecStage.spc::mean 0.039496 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1292system.cpu1.CUs0.ExecStage.spc::stdev 0.250206 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1293system.cpu1.CUs0.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1294system.cpu1.CUs0.ExecStage.spc::0 3471 97.23% 97.23% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1295system.cpu1.CUs0.ExecStage.spc::1 59 1.65% 98.88% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1296system.cpu1.CUs0.ExecStage.spc::2 38 1.06% 99.94% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1297system.cpu1.CUs0.ExecStage.spc::3 2 0.06% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1298system.cpu1.CUs0.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1299system.cpu1.CUs0.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1300system.cpu1.CUs0.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1301system.cpu1.CUs0.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1302system.cpu1.CUs0.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1303system.cpu1.CUs0.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1304system.cpu1.CUs0.ExecStage.spc::total 3570 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 1305system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 93 # number of CU transitions from active to idle 1306system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 93 # duration of idle periods in cycles 1307system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 37.225806 # duration of idle periods in cycles 1308system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 154.644552 # duration of idle periods in cycles 1309system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles 1310system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 74 79.57% 79.57% # duration of idle periods in cycles 1311system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 7 7.53% 87.10% # duration of idle periods in cycles 1312system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 1 1.08% 88.17% # duration of idle periods in cycles 1313system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 1 1.08% 89.25% # duration of idle periods in cycles 1314system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 2 2.15% 91.40% # duration of idle periods in cycles 1315system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.08% 92.47% # duration of idle periods in cycles 1316system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 92.47% # duration of idle periods in cycles 1317system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 92.47% # duration of idle periods in cycles 1318system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 92.47% # duration of idle periods in cycles 1319system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 92.47% # duration of idle periods in cycles 1320system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 92.47% # duration of idle periods in cycles 1321system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 92.47% # duration of idle periods in cycles 1322system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 92.47% # duration of idle periods in cycles 1323system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 92.47% # duration of idle periods in cycles 1324system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 92.47% # duration of idle periods in cycles 1325system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 92.47% # duration of idle periods in cycles 1326system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 7 7.53% 100.00% # duration of idle periods in cycles 1327system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles 1328system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::max_value 1291 # duration of idle periods in cycles 1329system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 93 # duration of idle periods in cycles 1330system.cpu1.CUs0.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF 1331system.cpu1.CUs0.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF 1332system.cpu1.CUs0.tlb_requests 769 # number of uncoalesced requests 1333system.cpu1.CUs0.tlb_cycles -455223738000 # total number of cycles for all uncoalesced requests 1334system.cpu1.CUs0.avg_translation_latency -591968449.934981 # Avg. translation latency for data translations 1335system.cpu1.CUs0.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB 1336system.cpu1.CUs0.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 1337system.cpu1.CUs0.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 1338system.cpu1.CUs0.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 1339system.cpu1.CUs0.lds_bank_access_cnt 54 # Total number of LDS bank accesses 1340system.cpu1.CUs0.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet 1341system.cpu1.CUs0.lds_bank_conflicts::mean 8 # Number of bank conflicts per LDS memory packet 1342system.cpu1.CUs0.lds_bank_conflicts::stdev 6.196773 # Number of bank conflicts per LDS memory packet 1343system.cpu1.CUs0.lds_bank_conflicts::underflows 0 0.00% 0.00% # Number of bank conflicts per LDS memory packet 1344system.cpu1.CUs0.lds_bank_conflicts::0-1 2 33.33% 33.33% # Number of bank conflicts per LDS memory packet 1345system.cpu1.CUs0.lds_bank_conflicts::2-3 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 1346system.cpu1.CUs0.lds_bank_conflicts::4-5 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 1347system.cpu1.CUs0.lds_bank_conflicts::6-7 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 1348system.cpu1.CUs0.lds_bank_conflicts::8-9 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 1349system.cpu1.CUs0.lds_bank_conflicts::10-11 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 1350system.cpu1.CUs0.lds_bank_conflicts::12-13 4 66.67% 100.00% # Number of bank conflicts per LDS memory packet 1351system.cpu1.CUs0.lds_bank_conflicts::14-15 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1352system.cpu1.CUs0.lds_bank_conflicts::16-17 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1353system.cpu1.CUs0.lds_bank_conflicts::18-19 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1354system.cpu1.CUs0.lds_bank_conflicts::20-21 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1355system.cpu1.CUs0.lds_bank_conflicts::22-23 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1356system.cpu1.CUs0.lds_bank_conflicts::24-25 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1357system.cpu1.CUs0.lds_bank_conflicts::26-27 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1358system.cpu1.CUs0.lds_bank_conflicts::28-29 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1359system.cpu1.CUs0.lds_bank_conflicts::30-31 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1360system.cpu1.CUs0.lds_bank_conflicts::32-33 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1361system.cpu1.CUs0.lds_bank_conflicts::34-35 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1362system.cpu1.CUs0.lds_bank_conflicts::36-37 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1363system.cpu1.CUs0.lds_bank_conflicts::38-39 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1364system.cpu1.CUs0.lds_bank_conflicts::40-41 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1365system.cpu1.CUs0.lds_bank_conflicts::42-43 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1366system.cpu1.CUs0.lds_bank_conflicts::44-45 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1367system.cpu1.CUs0.lds_bank_conflicts::46-47 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1368system.cpu1.CUs0.lds_bank_conflicts::48-49 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1369system.cpu1.CUs0.lds_bank_conflicts::50-51 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1370system.cpu1.CUs0.lds_bank_conflicts::52-53 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1371system.cpu1.CUs0.lds_bank_conflicts::54-55 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1372system.cpu1.CUs0.lds_bank_conflicts::56-57 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1373system.cpu1.CUs0.lds_bank_conflicts::58-59 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1374system.cpu1.CUs0.lds_bank_conflicts::60-61 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1375system.cpu1.CUs0.lds_bank_conflicts::62-63 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1376system.cpu1.CUs0.lds_bank_conflicts::64 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1377system.cpu1.CUs0.lds_bank_conflicts::overflows 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 1378system.cpu1.CUs0.lds_bank_conflicts::min_value 0 # Number of bank conflicts per LDS memory packet 1379system.cpu1.CUs0.lds_bank_conflicts::max_value 12 # Number of bank conflicts per LDS memory packet 1380system.cpu1.CUs0.lds_bank_conflicts::total 6 # Number of bank conflicts per LDS memory packet 1381system.cpu1.CUs0.page_divergence_dist::samples 17 # pages touched per wf (over all mem. instr.) 1382system.cpu1.CUs0.page_divergence_dist::mean 1 # pages touched per wf (over all mem. instr.) 1383system.cpu1.CUs0.page_divergence_dist::stdev 0 # pages touched per wf (over all mem. instr.) 1384system.cpu1.CUs0.page_divergence_dist::underflows 0 0.00% 0.00% # pages touched per wf (over all mem. instr.) 1385system.cpu1.CUs0.page_divergence_dist::1-4 17 100.00% 100.00% # pages touched per wf (over all mem. instr.) 1386system.cpu1.CUs0.page_divergence_dist::5-8 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1387system.cpu1.CUs0.page_divergence_dist::9-12 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1388system.cpu1.CUs0.page_divergence_dist::13-16 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1389system.cpu1.CUs0.page_divergence_dist::17-20 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1390system.cpu1.CUs0.page_divergence_dist::21-24 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1391system.cpu1.CUs0.page_divergence_dist::25-28 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1392system.cpu1.CUs0.page_divergence_dist::29-32 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1393system.cpu1.CUs0.page_divergence_dist::33-36 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1394system.cpu1.CUs0.page_divergence_dist::37-40 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1395system.cpu1.CUs0.page_divergence_dist::41-44 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1396system.cpu1.CUs0.page_divergence_dist::45-48 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1397system.cpu1.CUs0.page_divergence_dist::49-52 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1398system.cpu1.CUs0.page_divergence_dist::53-56 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1399system.cpu1.CUs0.page_divergence_dist::57-60 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1400system.cpu1.CUs0.page_divergence_dist::61-64 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1401system.cpu1.CUs0.page_divergence_dist::overflows 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 1402system.cpu1.CUs0.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.) 1403system.cpu1.CUs0.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.) 1404system.cpu1.CUs0.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.) 1405system.cpu1.CUs0.global_mem_instr_cnt 17 # dynamic global memory instructions count 1406system.cpu1.CUs0.local_mem_instr_cnt 6 # dynamic local memory intruction count 1407system.cpu1.CUs0.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity 1408system.cpu1.CUs0.num_instr_executed 141 # number of instructions executed 1409system.cpu1.CUs0.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle 1410system.cpu1.CUs0.inst_exec_rate::mean 92.127660 # Instruction Execution Rate: Number of executed vector instructions per cycle 1411system.cpu1.CUs0.inst_exec_rate::stdev 237.147810 # Instruction Execution Rate: Number of executed vector instructions per cycle 1412system.cpu1.CUs0.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 1413system.cpu1.CUs0.inst_exec_rate::0-1 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 1414system.cpu1.CUs0.inst_exec_rate::2-3 12 8.51% 8.51% # Instruction Execution Rate: Number of executed vector instructions per cycle 1415system.cpu1.CUs0.inst_exec_rate::4-5 52 36.88% 45.39% # Instruction Execution Rate: Number of executed vector instructions per cycle 1416system.cpu1.CUs0.inst_exec_rate::6-7 31 21.99% 67.38% # Instruction Execution Rate: Number of executed vector instructions per cycle 1417system.cpu1.CUs0.inst_exec_rate::8-9 3 2.13% 69.50% # Instruction Execution Rate: Number of executed vector instructions per cycle 1418system.cpu1.CUs0.inst_exec_rate::10 3 2.13% 71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle 1419system.cpu1.CUs0.inst_exec_rate::overflows 40 28.37% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 1420system.cpu1.CUs0.inst_exec_rate::min_value 2 # Instruction Execution Rate: Number of executed vector instructions per cycle 1421system.cpu1.CUs0.inst_exec_rate::max_value 1297 # Instruction Execution Rate: Number of executed vector instructions per cycle 1422system.cpu1.CUs0.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle 1423system.cpu1.CUs0.num_vec_ops_executed 6769 # number of vec ops executed (e.g. WF size/inst) 1424system.cpu1.CUs0.num_total_cycles 3570 # number of cycles the CU ran for 1425system.cpu1.CUs0.vpc 1.896078 # Vector Operations per cycle (this CU only) 1426system.cpu1.CUs0.ipc 0.039496 # Instructions per cycle (this CU only) 1427system.cpu1.CUs0.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) 1428system.cpu1.CUs0.warp_execution_dist::mean 48.007092 # number of lanes active per instruction (oval all instructions) 1429system.cpu1.CUs0.warp_execution_dist::stdev 23.719942 # number of lanes active per instruction (oval all instructions) 1430system.cpu1.CUs0.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions) 1431system.cpu1.CUs0.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions) 1432system.cpu1.CUs0.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) 1433system.cpu1.CUs0.warp_execution_dist::9-12 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) 1434system.cpu1.CUs0.warp_execution_dist::13-16 36 25.53% 29.08% # number of lanes active per instruction (oval all instructions) 1435system.cpu1.CUs0.warp_execution_dist::17-20 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 1436system.cpu1.CUs0.warp_execution_dist::21-24 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 1437system.cpu1.CUs0.warp_execution_dist::25-28 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 1438system.cpu1.CUs0.warp_execution_dist::29-32 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 1439system.cpu1.CUs0.warp_execution_dist::33-36 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 1440system.cpu1.CUs0.warp_execution_dist::37-40 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 1441system.cpu1.CUs0.warp_execution_dist::41-44 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 1442system.cpu1.CUs0.warp_execution_dist::45-48 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 1443system.cpu1.CUs0.warp_execution_dist::49-52 8 5.67% 34.75% # number of lanes active per instruction (oval all instructions) 1444system.cpu1.CUs0.warp_execution_dist::53-56 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) 1445system.cpu1.CUs0.warp_execution_dist::57-60 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) 1446system.cpu1.CUs0.warp_execution_dist::61-64 92 65.25% 100.00% # number of lanes active per instruction (oval all instructions) 1447system.cpu1.CUs0.warp_execution_dist::overflows 0 0.00% 100.00% # number of lanes active per instruction (oval all instructions) 1448system.cpu1.CUs0.warp_execution_dist::min_value 1 # number of lanes active per instruction (oval all instructions) 1449system.cpu1.CUs0.warp_execution_dist::max_value 64 # number of lanes active per instruction (oval all instructions) 1450system.cpu1.CUs0.warp_execution_dist::total 141 # number of lanes active per instruction (oval all instructions) 1451system.cpu1.CUs0.gmem_lanes_execution_dist::samples 18 # number of active lanes per global memory instruction 1452system.cpu1.CUs0.gmem_lanes_execution_dist::mean 37.833333 # number of active lanes per global memory instruction 1453system.cpu1.CUs0.gmem_lanes_execution_dist::stdev 27.064737 # number of active lanes per global memory instruction 1454system.cpu1.CUs0.gmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per global memory instruction 1455system.cpu1.CUs0.gmem_lanes_execution_dist::1-4 1 5.56% 5.56% # number of active lanes per global memory instruction 1456system.cpu1.CUs0.gmem_lanes_execution_dist::5-8 0 0.00% 5.56% # number of active lanes per global memory instruction 1457system.cpu1.CUs0.gmem_lanes_execution_dist::9-12 0 0.00% 5.56% # number of active lanes per global memory instruction 1458system.cpu1.CUs0.gmem_lanes_execution_dist::13-16 8 44.44% 50.00% # number of active lanes per global memory instruction 1459system.cpu1.CUs0.gmem_lanes_execution_dist::17-20 0 0.00% 50.00% # number of active lanes per global memory instruction 1460system.cpu1.CUs0.gmem_lanes_execution_dist::21-24 0 0.00% 50.00% # number of active lanes per global memory instruction 1461system.cpu1.CUs0.gmem_lanes_execution_dist::25-28 0 0.00% 50.00% # number of active lanes per global memory instruction 1462system.cpu1.CUs0.gmem_lanes_execution_dist::29-32 0 0.00% 50.00% # number of active lanes per global memory instruction 1463system.cpu1.CUs0.gmem_lanes_execution_dist::33-36 0 0.00% 50.00% # number of active lanes per global memory instruction 1464system.cpu1.CUs0.gmem_lanes_execution_dist::37-40 0 0.00% 50.00% # number of active lanes per global memory instruction 1465system.cpu1.CUs0.gmem_lanes_execution_dist::41-44 0 0.00% 50.00% # number of active lanes per global memory instruction 1466system.cpu1.CUs0.gmem_lanes_execution_dist::45-48 0 0.00% 50.00% # number of active lanes per global memory instruction 1467system.cpu1.CUs0.gmem_lanes_execution_dist::49-52 0 0.00% 50.00% # number of active lanes per global memory instruction 1468system.cpu1.CUs0.gmem_lanes_execution_dist::53-56 0 0.00% 50.00% # number of active lanes per global memory instruction 1469system.cpu1.CUs0.gmem_lanes_execution_dist::57-60 0 0.00% 50.00% # number of active lanes per global memory instruction 1470system.cpu1.CUs0.gmem_lanes_execution_dist::61-64 9 50.00% 100.00% # number of active lanes per global memory instruction 1471system.cpu1.CUs0.gmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per global memory instruction 1472system.cpu1.CUs0.gmem_lanes_execution_dist::min_value 1 # number of active lanes per global memory instruction 1473system.cpu1.CUs0.gmem_lanes_execution_dist::max_value 64 # number of active lanes per global memory instruction 1474system.cpu1.CUs0.gmem_lanes_execution_dist::total 18 # number of active lanes per global memory instruction 1475system.cpu1.CUs0.lmem_lanes_execution_dist::samples 6 # number of active lanes per local memory instruction 1476system.cpu1.CUs0.lmem_lanes_execution_dist::mean 19.500000 # number of active lanes per local memory instruction 1477system.cpu1.CUs0.lmem_lanes_execution_dist::stdev 22.322634 # number of active lanes per local memory instruction 1478system.cpu1.CUs0.lmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per local memory instruction 1479system.cpu1.CUs0.lmem_lanes_execution_dist::1-4 1 16.67% 16.67% # number of active lanes per local memory instruction 1480system.cpu1.CUs0.lmem_lanes_execution_dist::5-8 0 0.00% 16.67% # number of active lanes per local memory instruction 1481system.cpu1.CUs0.lmem_lanes_execution_dist::9-12 0 0.00% 16.67% # number of active lanes per local memory instruction 1482system.cpu1.CUs0.lmem_lanes_execution_dist::13-16 4 66.67% 83.33% # number of active lanes per local memory instruction 1483system.cpu1.CUs0.lmem_lanes_execution_dist::17-20 0 0.00% 83.33% # number of active lanes per local memory instruction 1484system.cpu1.CUs0.lmem_lanes_execution_dist::21-24 0 0.00% 83.33% # number of active lanes per local memory instruction 1485system.cpu1.CUs0.lmem_lanes_execution_dist::25-28 0 0.00% 83.33% # number of active lanes per local memory instruction 1486system.cpu1.CUs0.lmem_lanes_execution_dist::29-32 0 0.00% 83.33% # number of active lanes per local memory instruction 1487system.cpu1.CUs0.lmem_lanes_execution_dist::33-36 0 0.00% 83.33% # number of active lanes per local memory instruction 1488system.cpu1.CUs0.lmem_lanes_execution_dist::37-40 0 0.00% 83.33% # number of active lanes per local memory instruction 1489system.cpu1.CUs0.lmem_lanes_execution_dist::41-44 0 0.00% 83.33% # number of active lanes per local memory instruction 1490system.cpu1.CUs0.lmem_lanes_execution_dist::45-48 0 0.00% 83.33% # number of active lanes per local memory instruction 1491system.cpu1.CUs0.lmem_lanes_execution_dist::49-52 0 0.00% 83.33% # number of active lanes per local memory instruction 1492system.cpu1.CUs0.lmem_lanes_execution_dist::53-56 0 0.00% 83.33% # number of active lanes per local memory instruction 1493system.cpu1.CUs0.lmem_lanes_execution_dist::57-60 0 0.00% 83.33% # number of active lanes per local memory instruction 1494system.cpu1.CUs0.lmem_lanes_execution_dist::61-64 1 16.67% 100.00% # number of active lanes per local memory instruction 1495system.cpu1.CUs0.lmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per local memory instruction 1496system.cpu1.CUs0.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction 1497system.cpu1.CUs0.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction 1498system.cpu1.CUs0.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction 1499system.cpu1.CUs0.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed 1500system.cpu1.CUs0.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD 1501system.cpu1.CUs0.num_CAS_ops 0 # number of compare and swap operations 1502system.cpu1.CUs0.num_failed_CAS_ops 0 # number of compare and swap operations that failed 1503system.cpu1.CUs0.num_completed_wfs 4 # number of completed wavefronts 1504system.cpu1.CUs1.localDataStore.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 1505system.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1506system.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1507system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 591 # number of times the wf's instructions are blocked due to RAW dependencies 1508system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands 1509system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands 1510system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands 1511system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 1512system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands 1513system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands 1514system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 1515system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 1516system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1517system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 1518system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::total 39 # number of executed instructions with N source register operands 1519system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::samples 39 # number of executed instructions with N destination register operands 1520system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::mean 0.589744 # number of executed instructions with N destination register operands 1521system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::stdev 0.498310 # number of executed instructions with N destination register operands 1522system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 1523system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00% # number of executed instructions with N destination register operands 1524system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 1525system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 1526system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1527system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 1528system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::total 39 # number of executed instructions with N destination register operands 1529system.cpu1.CUs1.wavefronts01.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1530system.cpu1.CUs1.wavefronts01.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1531system.cpu1.CUs1.wavefronts01.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1532system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1533system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1534system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1535system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1536system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1537system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1538system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1539system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1540system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1541system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1542system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1543system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1544system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1545system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1546system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1547system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1548system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1549system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1550system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1551system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1552system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1553system.cpu1.CUs1.wavefronts02.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1554system.cpu1.CUs1.wavefronts02.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1555system.cpu1.CUs1.wavefronts02.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1556system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1557system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1558system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1559system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1560system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1561system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1562system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1563system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1564system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1565system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1566system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1567system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1568system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1569system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1570system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1571system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1572system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1573system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1574system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1575system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1576system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1577system.cpu1.CUs1.wavefronts03.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1578system.cpu1.CUs1.wavefronts03.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1579system.cpu1.CUs1.wavefronts03.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1580system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1581system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1582system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1583system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1584system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1585system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1586system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1587system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1588system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1589system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1590system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1591system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1592system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1593system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1594system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1595system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1596system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1597system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1598system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1599system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1600system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1601system.cpu1.CUs1.wavefronts04.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1602system.cpu1.CUs1.wavefronts04.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1603system.cpu1.CUs1.wavefronts04.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1604system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1605system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1606system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1607system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1608system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1609system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1610system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1611system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1612system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1613system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1614system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1615system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1616system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1617system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1618system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1619system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1620system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1621system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1622system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1623system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1624system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1625system.cpu1.CUs1.wavefronts05.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1626system.cpu1.CUs1.wavefronts05.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1627system.cpu1.CUs1.wavefronts05.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1628system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1629system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1630system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1631system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1632system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1633system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1634system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1635system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1636system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1637system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1638system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1639system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1640system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1641system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1642system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1643system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1644system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1645system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1646system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1647system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1648system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1649system.cpu1.CUs1.wavefronts06.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1650system.cpu1.CUs1.wavefronts06.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1651system.cpu1.CUs1.wavefronts06.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1652system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1653system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1654system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1655system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1656system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1657system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1658system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1659system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1660system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1661system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1662system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1663system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1664system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1665system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1666system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1667system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1668system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1669system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1670system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1671system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1672system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1673system.cpu1.CUs1.wavefronts07.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1674system.cpu1.CUs1.wavefronts07.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1675system.cpu1.CUs1.wavefronts07.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1676system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1677system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1678system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1679system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1680system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1681system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1682system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1683system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1684system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1685system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1686system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1687system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1688system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1689system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1690system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1691system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1692system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1693system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1694system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1695system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1696system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1697system.cpu1.CUs1.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1698system.cpu1.CUs1.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1699system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 562 # number of times the wf's instructions are blocked due to RAW dependencies 1700system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 1701system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 1702system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 1703system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 1704system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 1705system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 1706system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 1707system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 1708system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1709system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 1710system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 1711system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 1712system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 1713system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 1714system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 1715system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 1716system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 1717system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 1718system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1719system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 1720system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 1721system.cpu1.CUs1.wavefronts09.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1722system.cpu1.CUs1.wavefronts09.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1723system.cpu1.CUs1.wavefronts09.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1724system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1725system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1726system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1727system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1728system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1729system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1730system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1731system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1732system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1733system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1734system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1735system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1736system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1737system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1738system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1739system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1740system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1741system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1742system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1743system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1744system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1745system.cpu1.CUs1.wavefronts10.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1746system.cpu1.CUs1.wavefronts10.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1747system.cpu1.CUs1.wavefronts10.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1748system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1749system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1750system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1751system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1752system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1753system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1754system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1755system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1756system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1757system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1758system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1759system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1760system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1761system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1762system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1763system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1764system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1765system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1766system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1767system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1768system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1769system.cpu1.CUs1.wavefronts11.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1770system.cpu1.CUs1.wavefronts11.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1771system.cpu1.CUs1.wavefronts11.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1772system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1773system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1774system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1775system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1776system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1777system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1778system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1779system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1780system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1781system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1782system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1783system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1784system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1785system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1786system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1787system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1788system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1789system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1790system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1791system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1792system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1793system.cpu1.CUs1.wavefronts12.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1794system.cpu1.CUs1.wavefronts12.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1795system.cpu1.CUs1.wavefronts12.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1796system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1797system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1798system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1799system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1800system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1801system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1802system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1803system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1804system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1805system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1806system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1807system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1808system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1809system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1810system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1811system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1812system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1813system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1814system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1815system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1816system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1817system.cpu1.CUs1.wavefronts13.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1818system.cpu1.CUs1.wavefronts13.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1819system.cpu1.CUs1.wavefronts13.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1820system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1821system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1822system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1823system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1824system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1825system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1826system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1827system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1828system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1829system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1830system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1831system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1832system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1833system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1834system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1835system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1836system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1837system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1838system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1839system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1840system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1841system.cpu1.CUs1.wavefronts14.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1842system.cpu1.CUs1.wavefronts14.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1843system.cpu1.CUs1.wavefronts14.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1844system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1845system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1846system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1847system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1848system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1849system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1850system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1851system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1852system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1853system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1854system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1855system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1856system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1857system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1858system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1859system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1860system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1861system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1862system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1863system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1864system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1865system.cpu1.CUs1.wavefronts15.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1866system.cpu1.CUs1.wavefronts15.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1867system.cpu1.CUs1.wavefronts15.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1868system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1869system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1870system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1871system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1872system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1873system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1874system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1875system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1876system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1877system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1878system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1879system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1880system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1881system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1882system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1883system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1884system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1885system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1886system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1887system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1888system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1889system.cpu1.CUs1.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1890system.cpu1.CUs1.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1891system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 561 # number of times the wf's instructions are blocked due to RAW dependencies 1892system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 1893system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 1894system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 1895system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 1896system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 1897system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 1898system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 1899system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 1900system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1901system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 1902system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 1903system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 1904system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 1905system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 1906system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 1907system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 1908system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 1909system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 1910system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1911system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 1912system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 1913system.cpu1.CUs1.wavefronts17.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1914system.cpu1.CUs1.wavefronts17.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1915system.cpu1.CUs1.wavefronts17.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1916system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1917system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1918system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1919system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1920system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1921system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1922system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1923system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1924system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1925system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1926system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1927system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1928system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1929system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1930system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1931system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1932system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1933system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1934system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1935system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1936system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1937system.cpu1.CUs1.wavefronts18.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1938system.cpu1.CUs1.wavefronts18.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1939system.cpu1.CUs1.wavefronts18.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1940system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1941system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1942system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1943system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1944system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1945system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1946system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1947system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1948system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1949system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1950system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1951system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1952system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1953system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1954system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1955system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1956system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1957system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1958system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1959system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1960system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1961system.cpu1.CUs1.wavefronts19.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1962system.cpu1.CUs1.wavefronts19.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1963system.cpu1.CUs1.wavefronts19.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1964system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1965system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1966system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1967system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1968system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1969system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1970system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1971system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1972system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1973system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1974system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1975system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 1976system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 1977system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 1978system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 1979system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 1980system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 1981system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 1982system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 1983system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 1984system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 1985system.cpu1.CUs1.wavefronts20.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 1986system.cpu1.CUs1.wavefronts20.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 1987system.cpu1.CUs1.wavefronts20.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 1988system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 1989system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 1990system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 1991system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 1992system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 1993system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 1994system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 1995system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 1996system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 1997system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 1998system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 1999system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 2000system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 2001system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 2002system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 2003system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 2004system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 2005system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 2006system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2007system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 2008system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 2009system.cpu1.CUs1.wavefronts21.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 2010system.cpu1.CUs1.wavefronts21.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 2011system.cpu1.CUs1.wavefronts21.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 2012system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 2013system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 2014system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 2015system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 2016system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 2017system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 2018system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 2019system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 2020system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 2021system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 2022system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 2023system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 2024system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 2025system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 2026system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 2027system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 2028system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 2029system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 2030system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2031system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 2032system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 2033system.cpu1.CUs1.wavefronts22.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 2034system.cpu1.CUs1.wavefronts22.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 2035system.cpu1.CUs1.wavefronts22.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 2036system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 2037system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 2038system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 2039system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 2040system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 2041system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 2042system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 2043system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 2044system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 2045system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 2046system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 2047system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 2048system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 2049system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 2050system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 2051system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 2052system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 2053system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 2054system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2055system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 2056system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 2057system.cpu1.CUs1.wavefronts23.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 2058system.cpu1.CUs1.wavefronts23.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 2059system.cpu1.CUs1.wavefronts23.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 2060system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 2061system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 2062system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 2063system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 2064system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 2065system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 2066system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 2067system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 2068system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 2069system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 2070system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 2071system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 2072system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 2073system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 2074system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 2075system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 2076system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 2077system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 2078system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2079system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 2080system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 2081system.cpu1.CUs1.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 2082system.cpu1.CUs1.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 2083system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 551 # number of times the wf's instructions are blocked due to RAW dependencies 2084system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 2085system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 2086system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 2087system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 2088system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 2089system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 2090system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 2091system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 2092system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 2093system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 2094system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 2095system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 2096system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 2097system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 2098system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 2099system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 2100system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 2101system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 2102system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2103system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 2104system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 2105system.cpu1.CUs1.wavefronts25.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 2106system.cpu1.CUs1.wavefronts25.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 2107system.cpu1.CUs1.wavefronts25.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 2108system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 2109system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 2110system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 2111system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 2112system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 2113system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 2114system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 2115system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 2116system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 2117system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 2118system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 2119system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 2120system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 2121system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 2122system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 2123system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 2124system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 2125system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 2126system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2127system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 2128system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 2129system.cpu1.CUs1.wavefronts26.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 2130system.cpu1.CUs1.wavefronts26.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 2131system.cpu1.CUs1.wavefronts26.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 2132system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 2133system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 2134system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 2135system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 2136system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 2137system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 2138system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 2139system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 2140system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 2141system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 2142system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 2143system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 2144system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 2145system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 2146system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 2147system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 2148system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 2149system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 2150system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2151system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 2152system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 2153system.cpu1.CUs1.wavefronts27.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 2154system.cpu1.CUs1.wavefronts27.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 2155system.cpu1.CUs1.wavefronts27.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 2156system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 2157system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 2158system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 2159system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 2160system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 2161system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 2162system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 2163system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 2164system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 2165system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 2166system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 2167system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 2168system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 2169system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 2170system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 2171system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 2172system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 2173system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 2174system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2175system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 2176system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 2177system.cpu1.CUs1.wavefronts28.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 2178system.cpu1.CUs1.wavefronts28.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 2179system.cpu1.CUs1.wavefronts28.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 2180system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 2181system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 2182system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 2183system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 2184system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 2185system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 2186system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 2187system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 2188system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 2189system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 2190system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 2191system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 2192system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 2193system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 2194system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 2195system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 2196system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 2197system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 2198system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2199system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 2200system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 2201system.cpu1.CUs1.wavefronts29.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 2202system.cpu1.CUs1.wavefronts29.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 2203system.cpu1.CUs1.wavefronts29.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 2204system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 2205system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 2206system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 2207system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 2208system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 2209system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 2210system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 2211system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 2212system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 2213system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 2214system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 2215system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 2216system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 2217system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 2218system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 2219system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 2220system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 2221system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 2222system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2223system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 2224system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 2225system.cpu1.CUs1.wavefronts30.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 2226system.cpu1.CUs1.wavefronts30.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 2227system.cpu1.CUs1.wavefronts30.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 2228system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 2229system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 2230system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 2231system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 2232system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 2233system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 2234system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 2235system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 2236system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 2237system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 2238system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 2239system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 2240system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 2241system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 2242system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 2243system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 2244system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 2245system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 2246system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2247system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 2248system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 2249system.cpu1.CUs1.wavefronts31.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 2250system.cpu1.CUs1.wavefronts31.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 2251system.cpu1.CUs1.wavefronts31.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 2252system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 2253system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 2254system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 2255system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 2256system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 2257system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 2258system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 2259system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 2260system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 2261system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 2262system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 2263system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 2264system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 2265system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 2266system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 2267system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 2268system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 2269system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 2270system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 2271system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 2272system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 2273system.cpu1.CUs1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2274system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it 2275system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it 2276system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it 2277system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 2278system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 2279system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it 2280system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it 2281system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it 2282system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it 2283system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it 2284system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it 2285system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2286system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2287system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2288system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2289system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2290system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2291system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2292system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2293system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2294system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2295system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2296system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2297system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2298system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2299system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2300system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2301system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2302system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2303system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2304system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2305system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2306system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2307system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2308system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2309system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2310system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 2311system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it 2312system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it 2313system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it 2314system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 3471 # number of cycles the CU issues nothing 2315system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 99 # number of cycles the CU issued at least one instruction 2316system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued 2317system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued 2318system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued 2319system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued 2320system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued 2321system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued 2322system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 973 # Number of cycles no instruction of specific type issued 2323system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 662 # Number of cycles no instruction of specific type issued 2324system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 634 # Number of cycles no instruction of specific type issued 2325system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 606 # Number of cycles no instruction of specific type issued 2326system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 404 # Number of cycles no instruction of specific type issued 2327system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM 22 # Number of cycles no instruction of specific type issued 2328system.cpu1.CUs1.ExecStage.spc::samples 3570 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2329system.cpu1.CUs1.ExecStage.spc::mean 0.039496 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2330system.cpu1.CUs1.ExecStage.spc::stdev 0.249084 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2331system.cpu1.CUs1.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2332system.cpu1.CUs1.ExecStage.spc::0 3471 97.23% 97.23% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2333system.cpu1.CUs1.ExecStage.spc::1 58 1.62% 98.85% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2334system.cpu1.CUs1.ExecStage.spc::2 40 1.12% 99.97% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2335system.cpu1.CUs1.ExecStage.spc::3 1 0.03% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2336system.cpu1.CUs1.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2337system.cpu1.CUs1.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2338system.cpu1.CUs1.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2339system.cpu1.CUs1.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2340system.cpu1.CUs1.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2341system.cpu1.CUs1.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2342system.cpu1.CUs1.ExecStage.spc::total 3570 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 2343system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 94 # number of CU transitions from active to idle 2344system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 94 # duration of idle periods in cycles 2345system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 35.776596 # duration of idle periods in cycles 2346system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 153.908027 # duration of idle periods in cycles 2347system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles 2348system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 75 79.79% 79.79% # duration of idle periods in cycles 2349system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 8 8.51% 88.30% # duration of idle periods in cycles 2350system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 88.30% # duration of idle periods in cycles 2351system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 1 1.06% 89.36% # duration of idle periods in cycles 2352system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 2 2.13% 91.49% # duration of idle periods in cycles 2353system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 1 1.06% 92.55% # duration of idle periods in cycles 2354system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 92.55% # duration of idle periods in cycles 2355system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 92.55% # duration of idle periods in cycles 2356system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 92.55% # duration of idle periods in cycles 2357system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 92.55% # duration of idle periods in cycles 2358system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 92.55% # duration of idle periods in cycles 2359system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 92.55% # duration of idle periods in cycles 2360system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 92.55% # duration of idle periods in cycles 2361system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 92.55% # duration of idle periods in cycles 2362system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 92.55% # duration of idle periods in cycles 2363system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 92.55% # duration of idle periods in cycles 2364system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 7 7.45% 100.00% # duration of idle periods in cycles 2365system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles 2366system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::max_value 1299 # duration of idle periods in cycles 2367system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 94 # duration of idle periods in cycles 2368system.cpu1.CUs1.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF 2369system.cpu1.CUs1.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF 2370system.cpu1.CUs1.tlb_requests 769 # number of uncoalesced requests 2371system.cpu1.CUs1.tlb_cycles -455230572000 # total number of cycles for all uncoalesced requests 2372system.cpu1.CUs1.avg_translation_latency -591977336.801040 # Avg. translation latency for data translations 2373system.cpu1.CUs1.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB 2374system.cpu1.CUs1.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 2375system.cpu1.CUs1.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 2376system.cpu1.CUs1.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 2377system.cpu1.CUs1.lds_bank_access_cnt 53 # Total number of LDS bank accesses 2378system.cpu1.CUs1.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet 2379system.cpu1.CUs1.lds_bank_conflicts::mean 7.833333 # Number of bank conflicts per LDS memory packet 2380system.cpu1.CUs1.lds_bank_conflicts::stdev 6.080022 # Number of bank conflicts per LDS memory packet 2381system.cpu1.CUs1.lds_bank_conflicts::underflows 0 0.00% 0.00% # Number of bank conflicts per LDS memory packet 2382system.cpu1.CUs1.lds_bank_conflicts::0-1 2 33.33% 33.33% # Number of bank conflicts per LDS memory packet 2383system.cpu1.CUs1.lds_bank_conflicts::2-3 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 2384system.cpu1.CUs1.lds_bank_conflicts::4-5 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 2385system.cpu1.CUs1.lds_bank_conflicts::6-7 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 2386system.cpu1.CUs1.lds_bank_conflicts::8-9 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 2387system.cpu1.CUs1.lds_bank_conflicts::10-11 1 16.67% 50.00% # Number of bank conflicts per LDS memory packet 2388system.cpu1.CUs1.lds_bank_conflicts::12-13 3 50.00% 100.00% # Number of bank conflicts per LDS memory packet 2389system.cpu1.CUs1.lds_bank_conflicts::14-15 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2390system.cpu1.CUs1.lds_bank_conflicts::16-17 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2391system.cpu1.CUs1.lds_bank_conflicts::18-19 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2392system.cpu1.CUs1.lds_bank_conflicts::20-21 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2393system.cpu1.CUs1.lds_bank_conflicts::22-23 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2394system.cpu1.CUs1.lds_bank_conflicts::24-25 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2395system.cpu1.CUs1.lds_bank_conflicts::26-27 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2396system.cpu1.CUs1.lds_bank_conflicts::28-29 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2397system.cpu1.CUs1.lds_bank_conflicts::30-31 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2398system.cpu1.CUs1.lds_bank_conflicts::32-33 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2399system.cpu1.CUs1.lds_bank_conflicts::34-35 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2400system.cpu1.CUs1.lds_bank_conflicts::36-37 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2401system.cpu1.CUs1.lds_bank_conflicts::38-39 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2402system.cpu1.CUs1.lds_bank_conflicts::40-41 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2403system.cpu1.CUs1.lds_bank_conflicts::42-43 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2404system.cpu1.CUs1.lds_bank_conflicts::44-45 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2405system.cpu1.CUs1.lds_bank_conflicts::46-47 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2406system.cpu1.CUs1.lds_bank_conflicts::48-49 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2407system.cpu1.CUs1.lds_bank_conflicts::50-51 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2408system.cpu1.CUs1.lds_bank_conflicts::52-53 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2409system.cpu1.CUs1.lds_bank_conflicts::54-55 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2410system.cpu1.CUs1.lds_bank_conflicts::56-57 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2411system.cpu1.CUs1.lds_bank_conflicts::58-59 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2412system.cpu1.CUs1.lds_bank_conflicts::60-61 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2413system.cpu1.CUs1.lds_bank_conflicts::62-63 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2414system.cpu1.CUs1.lds_bank_conflicts::64 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2415system.cpu1.CUs1.lds_bank_conflicts::overflows 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 2416system.cpu1.CUs1.lds_bank_conflicts::min_value 0 # Number of bank conflicts per LDS memory packet 2417system.cpu1.CUs1.lds_bank_conflicts::max_value 12 # Number of bank conflicts per LDS memory packet 2418system.cpu1.CUs1.lds_bank_conflicts::total 6 # Number of bank conflicts per LDS memory packet 2419system.cpu1.CUs1.page_divergence_dist::samples 17 # pages touched per wf (over all mem. instr.) 2420system.cpu1.CUs1.page_divergence_dist::mean 1 # pages touched per wf (over all mem. instr.) 2421system.cpu1.CUs1.page_divergence_dist::stdev 0 # pages touched per wf (over all mem. instr.) 2422system.cpu1.CUs1.page_divergence_dist::underflows 0 0.00% 0.00% # pages touched per wf (over all mem. instr.) 2423system.cpu1.CUs1.page_divergence_dist::1-4 17 100.00% 100.00% # pages touched per wf (over all mem. instr.) 2424system.cpu1.CUs1.page_divergence_dist::5-8 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2425system.cpu1.CUs1.page_divergence_dist::9-12 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2426system.cpu1.CUs1.page_divergence_dist::13-16 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2427system.cpu1.CUs1.page_divergence_dist::17-20 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2428system.cpu1.CUs1.page_divergence_dist::21-24 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2429system.cpu1.CUs1.page_divergence_dist::25-28 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2430system.cpu1.CUs1.page_divergence_dist::29-32 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2431system.cpu1.CUs1.page_divergence_dist::33-36 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2432system.cpu1.CUs1.page_divergence_dist::37-40 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2433system.cpu1.CUs1.page_divergence_dist::41-44 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2434system.cpu1.CUs1.page_divergence_dist::45-48 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2435system.cpu1.CUs1.page_divergence_dist::49-52 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2436system.cpu1.CUs1.page_divergence_dist::53-56 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2437system.cpu1.CUs1.page_divergence_dist::57-60 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2438system.cpu1.CUs1.page_divergence_dist::61-64 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2439system.cpu1.CUs1.page_divergence_dist::overflows 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 2440system.cpu1.CUs1.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.) 2441system.cpu1.CUs1.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.) 2442system.cpu1.CUs1.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.) 2443system.cpu1.CUs1.global_mem_instr_cnt 17 # dynamic global memory instructions count 2444system.cpu1.CUs1.local_mem_instr_cnt 6 # dynamic local memory intruction count 2445system.cpu1.CUs1.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity 2446system.cpu1.CUs1.num_instr_executed 141 # number of instructions executed 2447system.cpu1.CUs1.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle 2448system.cpu1.CUs1.inst_exec_rate::mean 91.269504 # Instruction Execution Rate: Number of executed vector instructions per cycle 2449system.cpu1.CUs1.inst_exec_rate::stdev 240.230451 # Instruction Execution Rate: Number of executed vector instructions per cycle 2450system.cpu1.CUs1.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 2451system.cpu1.CUs1.inst_exec_rate::0-1 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 2452system.cpu1.CUs1.inst_exec_rate::2-3 13 9.22% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle 2453system.cpu1.CUs1.inst_exec_rate::4-5 52 36.88% 46.10% # Instruction Execution Rate: Number of executed vector instructions per cycle 2454system.cpu1.CUs1.inst_exec_rate::6-7 33 23.40% 69.50% # Instruction Execution Rate: Number of executed vector instructions per cycle 2455system.cpu1.CUs1.inst_exec_rate::8-9 6 4.26% 73.76% # Instruction Execution Rate: Number of executed vector instructions per cycle 2456system.cpu1.CUs1.inst_exec_rate::10 0 0.00% 73.76% # Instruction Execution Rate: Number of executed vector instructions per cycle 2457system.cpu1.CUs1.inst_exec_rate::overflows 37 26.24% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 2458system.cpu1.CUs1.inst_exec_rate::min_value 2 # Instruction Execution Rate: Number of executed vector instructions per cycle 2459system.cpu1.CUs1.inst_exec_rate::max_value 1305 # Instruction Execution Rate: Number of executed vector instructions per cycle 2460system.cpu1.CUs1.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle 2461system.cpu1.CUs1.num_vec_ops_executed 6762 # number of vec ops executed (e.g. WF size/inst) 2462system.cpu1.CUs1.num_total_cycles 3570 # number of cycles the CU ran for 2463system.cpu1.CUs1.vpc 1.894118 # Vector Operations per cycle (this CU only) 2464system.cpu1.CUs1.ipc 0.039496 # Instructions per cycle (this CU only) 2465system.cpu1.CUs1.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) 2466system.cpu1.CUs1.warp_execution_dist::mean 47.957447 # number of lanes active per instruction (oval all instructions) 2467system.cpu1.CUs1.warp_execution_dist::stdev 23.818022 # number of lanes active per instruction (oval all instructions) 2468system.cpu1.CUs1.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions) 2469system.cpu1.CUs1.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions) 2470system.cpu1.CUs1.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) 2471system.cpu1.CUs1.warp_execution_dist::9-12 9 6.38% 9.93% # number of lanes active per instruction (oval all instructions) 2472system.cpu1.CUs1.warp_execution_dist::13-16 27 19.15% 29.08% # number of lanes active per instruction (oval all instructions) 2473system.cpu1.CUs1.warp_execution_dist::17-20 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 2474system.cpu1.CUs1.warp_execution_dist::21-24 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 2475system.cpu1.CUs1.warp_execution_dist::25-28 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 2476system.cpu1.CUs1.warp_execution_dist::29-32 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 2477system.cpu1.CUs1.warp_execution_dist::33-36 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 2478system.cpu1.CUs1.warp_execution_dist::37-40 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 2479system.cpu1.CUs1.warp_execution_dist::41-44 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 2480system.cpu1.CUs1.warp_execution_dist::45-48 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 2481system.cpu1.CUs1.warp_execution_dist::49-52 8 5.67% 34.75% # number of lanes active per instruction (oval all instructions) 2482system.cpu1.CUs1.warp_execution_dist::53-56 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) 2483system.cpu1.CUs1.warp_execution_dist::57-60 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) 2484system.cpu1.CUs1.warp_execution_dist::61-64 92 65.25% 100.00% # number of lanes active per instruction (oval all instructions) 2485system.cpu1.CUs1.warp_execution_dist::overflows 0 0.00% 100.00% # number of lanes active per instruction (oval all instructions) 2486system.cpu1.CUs1.warp_execution_dist::min_value 1 # number of lanes active per instruction (oval all instructions) 2487system.cpu1.CUs1.warp_execution_dist::max_value 64 # number of lanes active per instruction (oval all instructions) 2488system.cpu1.CUs1.warp_execution_dist::total 141 # number of lanes active per instruction (oval all instructions) 2489system.cpu1.CUs1.gmem_lanes_execution_dist::samples 18 # number of active lanes per global memory instruction 2490system.cpu1.CUs1.gmem_lanes_execution_dist::mean 37.722222 # number of active lanes per global memory instruction 2491system.cpu1.CUs1.gmem_lanes_execution_dist::stdev 27.174394 # number of active lanes per global memory instruction 2492system.cpu1.CUs1.gmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per global memory instruction 2493system.cpu1.CUs1.gmem_lanes_execution_dist::1-4 1 5.56% 5.56% # number of active lanes per global memory instruction 2494system.cpu1.CUs1.gmem_lanes_execution_dist::5-8 0 0.00% 5.56% # number of active lanes per global memory instruction 2495system.cpu1.CUs1.gmem_lanes_execution_dist::9-12 2 11.11% 16.67% # number of active lanes per global memory instruction 2496system.cpu1.CUs1.gmem_lanes_execution_dist::13-16 6 33.33% 50.00% # number of active lanes per global memory instruction 2497system.cpu1.CUs1.gmem_lanes_execution_dist::17-20 0 0.00% 50.00% # number of active lanes per global memory instruction 2498system.cpu1.CUs1.gmem_lanes_execution_dist::21-24 0 0.00% 50.00% # number of active lanes per global memory instruction 2499system.cpu1.CUs1.gmem_lanes_execution_dist::25-28 0 0.00% 50.00% # number of active lanes per global memory instruction 2500system.cpu1.CUs1.gmem_lanes_execution_dist::29-32 0 0.00% 50.00% # number of active lanes per global memory instruction 2501system.cpu1.CUs1.gmem_lanes_execution_dist::33-36 0 0.00% 50.00% # number of active lanes per global memory instruction 2502system.cpu1.CUs1.gmem_lanes_execution_dist::37-40 0 0.00% 50.00% # number of active lanes per global memory instruction 2503system.cpu1.CUs1.gmem_lanes_execution_dist::41-44 0 0.00% 50.00% # number of active lanes per global memory instruction 2504system.cpu1.CUs1.gmem_lanes_execution_dist::45-48 0 0.00% 50.00% # number of active lanes per global memory instruction 2505system.cpu1.CUs1.gmem_lanes_execution_dist::49-52 0 0.00% 50.00% # number of active lanes per global memory instruction 2506system.cpu1.CUs1.gmem_lanes_execution_dist::53-56 0 0.00% 50.00% # number of active lanes per global memory instruction 2507system.cpu1.CUs1.gmem_lanes_execution_dist::57-60 0 0.00% 50.00% # number of active lanes per global memory instruction 2508system.cpu1.CUs1.gmem_lanes_execution_dist::61-64 9 50.00% 100.00% # number of active lanes per global memory instruction 2509system.cpu1.CUs1.gmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per global memory instruction 2510system.cpu1.CUs1.gmem_lanes_execution_dist::min_value 1 # number of active lanes per global memory instruction 2511system.cpu1.CUs1.gmem_lanes_execution_dist::max_value 64 # number of active lanes per global memory instruction 2512system.cpu1.CUs1.gmem_lanes_execution_dist::total 18 # number of active lanes per global memory instruction 2513system.cpu1.CUs1.lmem_lanes_execution_dist::samples 6 # number of active lanes per local memory instruction 2514system.cpu1.CUs1.lmem_lanes_execution_dist::mean 19.333333 # number of active lanes per local memory instruction 2515system.cpu1.CUs1.lmem_lanes_execution_dist::stdev 22.384518 # number of active lanes per local memory instruction 2516system.cpu1.CUs1.lmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per local memory instruction 2517system.cpu1.CUs1.lmem_lanes_execution_dist::1-4 1 16.67% 16.67% # number of active lanes per local memory instruction 2518system.cpu1.CUs1.lmem_lanes_execution_dist::5-8 0 0.00% 16.67% # number of active lanes per local memory instruction 2519system.cpu1.CUs1.lmem_lanes_execution_dist::9-12 1 16.67% 33.33% # number of active lanes per local memory instruction 2520system.cpu1.CUs1.lmem_lanes_execution_dist::13-16 3 50.00% 83.33% # number of active lanes per local memory instruction 2521system.cpu1.CUs1.lmem_lanes_execution_dist::17-20 0 0.00% 83.33% # number of active lanes per local memory instruction 2522system.cpu1.CUs1.lmem_lanes_execution_dist::21-24 0 0.00% 83.33% # number of active lanes per local memory instruction 2523system.cpu1.CUs1.lmem_lanes_execution_dist::25-28 0 0.00% 83.33% # number of active lanes per local memory instruction 2524system.cpu1.CUs1.lmem_lanes_execution_dist::29-32 0 0.00% 83.33% # number of active lanes per local memory instruction 2525system.cpu1.CUs1.lmem_lanes_execution_dist::33-36 0 0.00% 83.33% # number of active lanes per local memory instruction 2526system.cpu1.CUs1.lmem_lanes_execution_dist::37-40 0 0.00% 83.33% # number of active lanes per local memory instruction 2527system.cpu1.CUs1.lmem_lanes_execution_dist::41-44 0 0.00% 83.33% # number of active lanes per local memory instruction 2528system.cpu1.CUs1.lmem_lanes_execution_dist::45-48 0 0.00% 83.33% # number of active lanes per local memory instruction 2529system.cpu1.CUs1.lmem_lanes_execution_dist::49-52 0 0.00% 83.33% # number of active lanes per local memory instruction 2530system.cpu1.CUs1.lmem_lanes_execution_dist::53-56 0 0.00% 83.33% # number of active lanes per local memory instruction 2531system.cpu1.CUs1.lmem_lanes_execution_dist::57-60 0 0.00% 83.33% # number of active lanes per local memory instruction 2532system.cpu1.CUs1.lmem_lanes_execution_dist::61-64 1 16.67% 100.00% # number of active lanes per local memory instruction 2533system.cpu1.CUs1.lmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per local memory instruction 2534system.cpu1.CUs1.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction 2535system.cpu1.CUs1.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction 2536system.cpu1.CUs1.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction 2537system.cpu1.CUs1.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed 2538system.cpu1.CUs1.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD 2539system.cpu1.CUs1.num_CAS_ops 0 # number of compare and swap operations 2540system.cpu1.CUs1.num_failed_CAS_ops 0 # number of compare and swap operations that failed 2541system.cpu1.CUs1.num_completed_wfs 4 # number of completed wavefronts 2542system.cpu1.CUs0.ldsBus.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2543system.cpu1.CUs1.ldsBus.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2544system.cpu2.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2545system.cpu2.num_kernel_launched 1 # number of kernel launched 2546system.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits 2547system.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses 2548system.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses 2549system.dir_cntrl0.L3CacheMemory.num_data_array_writes 1551 # number of data array writes 2550system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1551 # number of tag array reads 2551system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1551 # number of tag array writes 2552system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2553system.dispatcher_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2554system.dispatcher_coalescer.clk_domain.clock 1000 # Clock period in ticks 2555system.dispatcher_coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2556system.dispatcher_coalescer.uncoalesced_accesses 0 # Number of uncoalesced TLB accesses 2557system.dispatcher_coalescer.coalesced_accesses 0 # Number of coalesced TLB accesses 2558system.dispatcher_coalescer.queuing_cycles 0 # Number of cycles spent in queue 2559system.dispatcher_coalescer.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 2560system.dispatcher_coalescer.local_latency nan # Avg. latency over all incoming pkts 2561system.dispatcher_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2562system.dispatcher_tlb.clk_domain.clock 1000 # Clock period in ticks 2563system.dispatcher_tlb.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2564system.dispatcher_tlb.local_TLB_accesses 0 # Number of TLB accesses 2565system.dispatcher_tlb.local_TLB_hits 0 # Number of TLB hits 2566system.dispatcher_tlb.local_TLB_misses 0 # Number of TLB misses 2567system.dispatcher_tlb.local_TLB_miss_rate nan # TLB miss rate 2568system.dispatcher_tlb.global_TLB_accesses 0 # Number of TLB accesses 2569system.dispatcher_tlb.global_TLB_hits 0 # Number of TLB hits 2570system.dispatcher_tlb.global_TLB_misses 0 # Number of TLB misses 2571system.dispatcher_tlb.global_TLB_miss_rate nan # TLB miss rate 2572system.dispatcher_tlb.access_cycles 0 # Cycles spent accessing this TLB level 2573system.dispatcher_tlb.page_table_cycles 0 # Cycles spent accessing the page table 2574system.dispatcher_tlb.unique_pages 0 # Number of unique pages touched 2575system.dispatcher_tlb.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 2576system.dispatcher_tlb.local_latency nan # Avg. latency over incoming coalesced reqs 2577system.dispatcher_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 2578system.l1_coalescer0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2579system.l1_coalescer0.clk_domain.clock 1000 # Clock period in ticks 2580system.l1_coalescer0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2581system.l1_coalescer0.uncoalesced_accesses 778 # Number of uncoalesced TLB accesses 2582system.l1_coalescer0.coalesced_accesses 0 # Number of coalesced TLB accesses 2583system.l1_coalescer0.queuing_cycles 0 # Number of cycles spent in queue 2584system.l1_coalescer0.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 2585system.l1_coalescer0.local_latency 0 # Avg. latency over all incoming pkts 2586system.l1_coalescer1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2587system.l1_coalescer1.clk_domain.clock 1000 # Clock period in ticks 2588system.l1_coalescer1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2589system.l1_coalescer1.uncoalesced_accesses 769 # Number of uncoalesced TLB accesses 2590system.l1_coalescer1.coalesced_accesses 0 # Number of coalesced TLB accesses 2591system.l1_coalescer1.queuing_cycles 0 # Number of cycles spent in queue 2592system.l1_coalescer1.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 2593system.l1_coalescer1.local_latency 0 # Avg. latency over all incoming pkts 2594system.l1_tlb0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2595system.l1_tlb0.clk_domain.clock 1000 # Clock period in ticks 2596system.l1_tlb0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2597system.l1_tlb0.local_TLB_accesses 778 # Number of TLB accesses 2598system.l1_tlb0.local_TLB_hits 774 # Number of TLB hits 2599system.l1_tlb0.local_TLB_misses 4 # Number of TLB misses 2600system.l1_tlb0.local_TLB_miss_rate 0.514139 # TLB miss rate 2601system.l1_tlb0.global_TLB_accesses 778 # Number of TLB accesses 2602system.l1_tlb0.global_TLB_hits 774 # Number of TLB hits 2603system.l1_tlb0.global_TLB_misses 4 # Number of TLB misses 2604system.l1_tlb0.global_TLB_miss_rate 0.514139 # TLB miss rate 2605system.l1_tlb0.access_cycles 0 # Cycles spent accessing this TLB level 2606system.l1_tlb0.page_table_cycles 0 # Cycles spent accessing the page table 2607system.l1_tlb0.unique_pages 4 # Number of unique pages touched 2608system.l1_tlb0.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 2609system.l1_tlb0.local_latency 0 # Avg. latency over incoming coalesced reqs 2610system.l1_tlb0.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 2611system.l1_tlb1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2612system.l1_tlb1.clk_domain.clock 1000 # Clock period in ticks 2613system.l1_tlb1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2614system.l1_tlb1.local_TLB_accesses 769 # Number of TLB accesses 2615system.l1_tlb1.local_TLB_hits 766 # Number of TLB hits 2616system.l1_tlb1.local_TLB_misses 3 # Number of TLB misses 2617system.l1_tlb1.local_TLB_miss_rate 0.390117 # TLB miss rate 2618system.l1_tlb1.global_TLB_accesses 769 # Number of TLB accesses 2619system.l1_tlb1.global_TLB_hits 766 # Number of TLB hits 2620system.l1_tlb1.global_TLB_misses 3 # Number of TLB misses 2621system.l1_tlb1.global_TLB_miss_rate 0.390117 # TLB miss rate 2622system.l1_tlb1.access_cycles 0 # Cycles spent accessing this TLB level 2623system.l1_tlb1.page_table_cycles 0 # Cycles spent accessing the page table 2624system.l1_tlb1.unique_pages 3 # Number of unique pages touched 2625system.l1_tlb1.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 2626system.l1_tlb1.local_latency 0 # Avg. latency over incoming coalesced reqs 2627system.l1_tlb1.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 2628system.l2_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2629system.l2_coalescer.clk_domain.clock 1000 # Clock period in ticks 2630system.l2_coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2631system.l2_coalescer.uncoalesced_accesses 8 # Number of uncoalesced TLB accesses 2632system.l2_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses 2633system.l2_coalescer.queuing_cycles 8000 # Number of cycles spent in queue 2634system.l2_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs 2635system.l2_coalescer.local_latency 125 # Avg. latency over all incoming pkts 2636system.l2_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2637system.l2_tlb.clk_domain.clock 1000 # Clock period in ticks 2638system.l2_tlb.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2639system.l2_tlb.local_TLB_accesses 8 # Number of TLB accesses 2640system.l2_tlb.local_TLB_hits 3 # Number of TLB hits 2641system.l2_tlb.local_TLB_misses 5 # Number of TLB misses 2642system.l2_tlb.local_TLB_miss_rate 62.500000 # TLB miss rate 2643system.l2_tlb.global_TLB_accesses 15 # Number of TLB accesses 2644system.l2_tlb.global_TLB_hits 3 # Number of TLB hits 2645system.l2_tlb.global_TLB_misses 12 # Number of TLB misses 2646system.l2_tlb.global_TLB_miss_rate 80 # TLB miss rate 2647system.l2_tlb.access_cycles 552008 # Cycles spent accessing this TLB level 2648system.l2_tlb.page_table_cycles 0 # Cycles spent accessing the page table 2649system.l2_tlb.unique_pages 5 # Number of unique pages touched 2650system.l2_tlb.local_cycles 69001 # Number of cycles spent in queue for all incoming reqs 2651system.l2_tlb.local_latency 8625.125000 # Avg. latency over incoming coalesced reqs 2652system.l2_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 2653system.l3_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2654system.l3_coalescer.clk_domain.clock 1000 # Clock period in ticks 2655system.l3_coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2656system.l3_coalescer.uncoalesced_accesses 5 # Number of uncoalesced TLB accesses 2657system.l3_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses 2658system.l3_coalescer.queuing_cycles 8000 # Number of cycles spent in queue 2659system.l3_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs 2660system.l3_coalescer.local_latency 200 # Avg. latency over all incoming pkts 2661system.l3_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2662system.l3_tlb.clk_domain.clock 1000 # Clock period in ticks 2663system.l3_tlb.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2664system.l3_tlb.local_TLB_accesses 5 # Number of TLB accesses 2665system.l3_tlb.local_TLB_hits 0 # Number of TLB hits 2666system.l3_tlb.local_TLB_misses 5 # Number of TLB misses 2667system.l3_tlb.local_TLB_miss_rate 100 # TLB miss rate 2668system.l3_tlb.global_TLB_accesses 12 # Number of TLB accesses 2669system.l3_tlb.global_TLB_hits 0 # Number of TLB hits 2670system.l3_tlb.global_TLB_misses 12 # Number of TLB misses 2671system.l3_tlb.global_TLB_miss_rate 100 # TLB miss rate 2672system.l3_tlb.access_cycles 1200000 # Cycles spent accessing this TLB level 2673system.l3_tlb.page_table_cycles 6000000 # Cycles spent accessing the page table 2674system.l3_tlb.unique_pages 5 # Number of unique pages touched 2675system.l3_tlb.local_cycles 150000 # Number of cycles spent in queue for all incoming reqs 2676system.l3_tlb.local_latency 30000 # Avg. latency over incoming coalesced reqs 2677system.l3_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 2678system.piobus.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2679system.piobus.trans_dist::WriteReq 94 # Transaction distribution 2680system.piobus.trans_dist::WriteResp 94 # Transaction distribution 2681system.piobus.pkt_count_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 188 # Packet count per connected master and slave (bytes) 2682system.piobus.pkt_count::total 188 # Packet count per connected master and slave (bytes) 2683system.piobus.pkt_size_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 748 # Cumulative packet size per connected master and slave (bytes) 2684system.piobus.pkt_size::total 748 # Cumulative packet size per connected master and slave (bytes) 2685system.piobus.reqLayer0.occupancy 188000 # Layer occupancy (ticks) 2686system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2687system.piobus.respLayer0.occupancy 94000 # Layer occupancy (ticks) 2688system.piobus.respLayer0.utilization 0.0 # Layer utilization (%) 2689system.ruby.network.ext_links0.int_node.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2690system.ruby.network.ext_links0.int_node.percent_links_utilized 0.007896 2691system.ruby.network.ext_links0.int_node.msg_count.Control::0 1551 2692system.ruby.network.ext_links0.int_node.msg_count.Request_Control::0 1551 2693system.ruby.network.ext_links0.int_node.msg_count.Response_Data::2 1563 2694system.ruby.network.ext_links0.int_node.msg_count.Response_Control::2 1539 2695system.ruby.network.ext_links0.int_node.msg_count.Unblock_Control::4 1551 2696system.ruby.network.ext_links0.int_node.msg_bytes.Control::0 12408 2697system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0 12408 2698system.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2 112536 2699system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2 12312 2700system.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4 12408 2701system.ruby.network.ext_links1.int_node.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2702system.ruby.network.ext_links1.int_node.percent_links_utilized 0.009900 2703system.ruby.network.ext_links1.int_node.msg_count.Control::0 16 2704system.ruby.network.ext_links1.int_node.msg_count.Request_Control::0 1535 2705system.ruby.network.ext_links1.int_node.msg_count.Response_Data::2 1537 2706system.ruby.network.ext_links1.int_node.msg_count.Response_Control::2 14 2707system.ruby.network.ext_links1.int_node.msg_count.Unblock_Control::4 1535 2708system.ruby.network.ext_links1.int_node.msg_bytes.Control::0 128 2709system.ruby.network.ext_links1.int_node.msg_bytes.Request_Control::0 12280 2710system.ruby.network.ext_links1.int_node.msg_bytes.Response_Data::2 110664 2711system.ruby.network.ext_links1.int_node.msg_bytes.Response_Control::2 112 2712system.ruby.network.ext_links1.int_node.msg_bytes.Unblock_Control::4 12280 2713system.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits 2714system.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses 2715system.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses 2716system.tcp_cntrl0.L1cache.num_data_array_reads 9 # number of data array reads 2717system.tcp_cntrl0.L1cache.num_data_array_writes 11 # number of data array writes 2718system.tcp_cntrl0.L1cache.num_tag_array_reads 26 # number of tag array reads 2719system.tcp_cntrl0.L1cache.num_tag_array_writes 18 # number of tag array writes 2720system.tcp_cntrl0.L1cache.num_data_array_stalls 2 # number of stalls caused by data array 2721system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2722system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 2 # loads that hit in the TCP 2723system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers 2724system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 2725system.tcp_cntrl0.coalescer.gpu_ld_misses 2 # loads that miss in the GPU 2726system.tcp_cntrl0.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP 2727system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 1 # TCP to TCP store transfers 2728system.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 2729system.tcp_cntrl0.coalescer.gpu_st_misses 4 # stores that miss in the GPU 2730system.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 2731system.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 2732system.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 2733system.tcp_cntrl0.coalescer.cp_ld_misses 0 # loads that miss in the GPU 2734system.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 2735system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 2736system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 2737system.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU 2738system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2739system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2740system.ruby.network.ext_links2.int_node.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2741system.ruby.network.ext_links2.int_node.percent_links_utilized 0.000716 2742system.ruby.network.ext_links2.int_node.msg_count.Control::0 1535 2743system.ruby.network.ext_links2.int_node.msg_count.Control::1 14 2744system.ruby.network.ext_links2.int_node.msg_count.Request_Control::0 16 2745system.ruby.network.ext_links2.int_node.msg_count.Request_Control::1 19 2746system.ruby.network.ext_links2.int_node.msg_count.Response_Data::2 26 2747system.ruby.network.ext_links2.int_node.msg_count.Response_Data::3 33 2748system.ruby.network.ext_links2.int_node.msg_count.Response_Control::2 1525 2749system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::4 16 2750system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::5 19 2751system.ruby.network.ext_links2.int_node.msg_bytes.Control::0 12280 2752system.ruby.network.ext_links2.int_node.msg_bytes.Control::1 112 2753system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::0 128 2754system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::1 152 2755system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::2 1872 2756system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::3 2376 2757system.ruby.network.ext_links2.int_node.msg_bytes.Response_Control::2 12200 2758system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::4 128 2759system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::5 152 2760system.tcp_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits 2761system.tcp_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses 2762system.tcp_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses 2763system.tcp_cntrl1.L1cache.num_data_array_reads 7 # number of data array reads 2764system.tcp_cntrl1.L1cache.num_data_array_writes 11 # number of data array writes 2765system.tcp_cntrl1.L1cache.num_tag_array_reads 25 # number of tag array reads 2766system.tcp_cntrl1.L1cache.num_tag_array_writes 18 # number of tag array writes 2767system.tcp_cntrl1.L1cache.num_tag_array_stalls 2 # number of stalls caused by tag array 2768system.tcp_cntrl1.L1cache.num_data_array_stalls 2 # number of stalls caused by data array 2769system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2770system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 3 # loads that hit in the TCP 2771system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 2 # TCP to TCP load transfers 2772system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 2773system.tcp_cntrl1.coalescer.gpu_ld_misses 0 # loads that miss in the GPU 2774system.tcp_cntrl1.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP 2775system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers 2776system.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 2777system.tcp_cntrl1.coalescer.gpu_st_misses 5 # stores that miss in the GPU 2778system.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 2779system.tcp_cntrl1.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 2780system.tcp_cntrl1.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 2781system.tcp_cntrl1.coalescer.cp_ld_misses 0 # loads that miss in the GPU 2782system.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 2783system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 2784system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 2785system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU 2786system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2787system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2788system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits 2789system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses 2790system.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses 2791system.sqc_cntrl0.L1cache.num_data_array_reads 86 # number of data array reads 2792system.sqc_cntrl0.L1cache.num_data_array_writes 5 # number of data array writes 2793system.sqc_cntrl0.L1cache.num_tag_array_reads 86 # number of tag array reads 2794system.sqc_cntrl0.L1cache.num_tag_array_writes 5 # number of tag array writes 2795system.sqc_cntrl0.L1cache.num_data_array_stalls 47 # number of stalls caused by data array 2796system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2797system.sqc_cntrl0.sequencer.load_waiting_on_load 120 # Number of times a load aliased with a pending load 2798system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2799system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits 2800system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses 2801system.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses 2802system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2803system.tccdir_cntrl0.directory.demand_hits 0 # Number of cache demand hits 2804system.tccdir_cntrl0.directory.demand_misses 0 # Number of cache demand misses 2805system.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses 2806system.tccdir_cntrl0.directory.num_tag_array_reads 1554 # number of tag array reads 2807system.tccdir_cntrl0.directory.num_tag_array_writes 27 # number of tag array writes 2808system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2809system.ruby.network.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2810system.ruby.network.msg_count.Control 3116 2811system.ruby.network.msg_count.Request_Control 3121 2812system.ruby.network.msg_count.Response_Data 3159 2813system.ruby.network.msg_count.Response_Control 3078 2814system.ruby.network.msg_count.Unblock_Control 3121 2815system.ruby.network.msg_byte.Control 24928 2816system.ruby.network.msg_byte.Request_Control 24968 2817system.ruby.network.msg_byte.Response_Data 227448 2818system.ruby.network.msg_byte.Response_Control 24624 2819system.ruby.network.msg_byte.Unblock_Control 24968 2820system.sqc_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2821system.sqc_coalescer.clk_domain.clock 1000 # Clock period in ticks 2822system.sqc_coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2823system.sqc_coalescer.uncoalesced_accesses 86 # Number of uncoalesced TLB accesses 2824system.sqc_coalescer.coalesced_accesses 60 # Number of coalesced TLB accesses 2825system.sqc_coalescer.queuing_cycles 108000 # Number of cycles spent in queue 2826system.sqc_coalescer.local_queuing_cycles 108000 # Number of cycles spent in queue for all incoming reqs 2827system.sqc_coalescer.local_latency 1255.813953 # Avg. latency over all incoming pkts 2828system.sqc_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 2829system.sqc_tlb.clk_domain.clock 1000 # Clock period in ticks 2830system.sqc_tlb.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2831system.sqc_tlb.local_TLB_accesses 60 # Number of TLB accesses 2832system.sqc_tlb.local_TLB_hits 59 # Number of TLB hits 2833system.sqc_tlb.local_TLB_misses 1 # Number of TLB misses 2834system.sqc_tlb.local_TLB_miss_rate 1.666667 # TLB miss rate 2835system.sqc_tlb.global_TLB_accesses 86 # Number of TLB accesses 2836system.sqc_tlb.global_TLB_hits 78 # Number of TLB hits 2837system.sqc_tlb.global_TLB_misses 8 # Number of TLB misses 2838system.sqc_tlb.global_TLB_miss_rate 9.302326 # TLB miss rate 2839system.sqc_tlb.access_cycles 86008 # Cycles spent accessing this TLB level 2840system.sqc_tlb.page_table_cycles 0 # Cycles spent accessing the page table 2841system.sqc_tlb.unique_pages 1 # Number of unique pages touched 2842system.sqc_tlb.local_cycles 60001 # Number of cycles spent in queue for all incoming reqs 2843system.sqc_tlb.local_latency 1000.016667 # Avg. latency over incoming coalesced reqs 2844system.sqc_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 2845system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states 2846system.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.005553 2847system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1551 2848system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Data::2 12 2849system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2 1539 2850system.ruby.network.ext_links0.int_node.throttle0.msg_count.Unblock_Control::4 1551 2851system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0 12408 2852system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Data::2 864 2853system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Control::2 12312 2854system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Unblock_Control::4 12408 2855system.ruby.network.ext_links0.int_node.throttle1.link_utilization 0.016173 2856system.ruby.network.ext_links0.int_node.throttle1.msg_count.Control::0 16 2857system.ruby.network.ext_links0.int_node.throttle1.msg_count.Response_Data::2 1535 2858system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Control::0 128 2859system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Response_Data::2 110520 2860system.ruby.network.ext_links0.int_node.throttle2.link_utilization 0.001963 2861system.ruby.network.ext_links0.int_node.throttle2.msg_count.Control::0 1535 2862system.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Data::2 16 2863system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Control::0 12280 2864system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Data::2 1152 2865system.ruby.network.ext_links1.int_node.throttle0.link_utilization 0.016173 2866system.ruby.network.ext_links1.int_node.throttle0.msg_count.Control::0 16 2867system.ruby.network.ext_links1.int_node.throttle0.msg_count.Response_Data::2 1535 2868system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Control::0 128 2869system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Response_Data::2 110520 2870system.ruby.network.ext_links1.int_node.throttle1.link_utilization 0.003627 2871system.ruby.network.ext_links1.int_node.throttle1.msg_count.Request_Control::0 1535 2872system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Data::2 2 2873system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Control::2 14 2874system.ruby.network.ext_links1.int_node.throttle1.msg_count.Unblock_Control::4 1535 2875system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Request_Control::0 12280 2876system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Data::2 144 2877system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Control::2 112 2878system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Unblock_Control::4 12280 2879system.ruby.network.ext_links2.int_node.throttle0.link_utilization 0.000083 2880system.ruby.network.ext_links2.int_node.throttle0.msg_count.Control::1 8 2881system.ruby.network.ext_links2.int_node.throttle0.msg_count.Response_Data::3 7 2882system.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Control::1 64 2883system.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Response_Data::3 504 2884system.ruby.network.ext_links2.int_node.throttle1.link_utilization 0.000081 2885system.ruby.network.ext_links2.int_node.throttle1.msg_count.Control::1 6 2886system.ruby.network.ext_links2.int_node.throttle1.msg_count.Response_Data::3 7 2887system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Control::1 48 2888system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Response_Data::3 504 2889system.ruby.network.ext_links2.int_node.throttle2.link_utilization 0 2890system.ruby.network.ext_links2.int_node.throttle3.link_utilization 0.002155 2891system.ruby.network.ext_links2.int_node.throttle3.msg_count.Control::0 1535 2892system.ruby.network.ext_links2.int_node.throttle3.msg_count.Request_Control::1 19 2893system.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::2 16 2894system.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::3 14 2895system.ruby.network.ext_links2.int_node.throttle3.msg_count.Unblock_Control::5 19 2896system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Control::0 12280 2897system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Request_Control::1 152 2898system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Response_Data::2 1152 2899system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Response_Data::3 1008 2900system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Unblock_Control::5 152 2901system.ruby.network.ext_links2.int_node.throttle4.link_utilization 0.000053 2902system.ruby.network.ext_links2.int_node.throttle4.msg_count.Response_Data::3 5 2903system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Response_Data::3 360 2904system.ruby.network.ext_links2.int_node.throttle5.link_utilization 0.001926 2905system.ruby.network.ext_links2.int_node.throttle5.msg_count.Request_Control::0 16 2906system.ruby.network.ext_links2.int_node.throttle5.msg_count.Response_Data::2 10 2907system.ruby.network.ext_links2.int_node.throttle5.msg_count.Response_Control::2 1525 2908system.ruby.network.ext_links2.int_node.throttle5.msg_count.Unblock_Control::4 16 2909system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Request_Control::0 128 2910system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Response_Data::2 720 2911system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Response_Control::2 12200 2912system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Unblock_Control::4 128 2913system.ruby.CorePair_Controller.C0_Load_L1miss 180 0.00% 0.00% 2914system.ruby.CorePair_Controller.C0_Load_L1hit 16155 0.00% 0.00% 2915system.ruby.CorePair_Controller.Ifetch0_L1hit 86007 0.00% 0.00% 2916system.ruby.CorePair_Controller.Ifetch0_L1miss 1088 0.00% 0.00% 2917system.ruby.CorePair_Controller.C0_Store_L1miss 325 0.00% 0.00% 2918system.ruby.CorePair_Controller.C0_Store_L1hit 10448 0.00% 0.00% 2919system.ruby.CorePair_Controller.NB_AckS 1043 0.00% 0.00% 2920system.ruby.CorePair_Controller.NB_AckM 326 0.00% 0.00% 2921system.ruby.CorePair_Controller.NB_AckE 166 0.00% 0.00% 2922system.ruby.CorePair_Controller.L1I_Repl 589 0.00% 0.00% 2923system.ruby.CorePair_Controller.L1D0_Repl 24 0.00% 0.00% 2924system.ruby.CorePair_Controller.L2_to_L1D0 5 0.00% 0.00% 2925system.ruby.CorePair_Controller.L2_to_L1I 54 0.00% 0.00% 2926system.ruby.CorePair_Controller.PrbInvData 9 0.00% 0.00% 2927system.ruby.CorePair_Controller.PrbShrData 7 0.00% 0.00% 2928system.ruby.CorePair_Controller.I.C0_Load_L1miss 175 0.00% 0.00% 2929system.ruby.CorePair_Controller.I.Ifetch0_L1miss 1034 0.00% 0.00% 2930system.ruby.CorePair_Controller.I.C0_Store_L1miss 325 0.00% 0.00% 2931system.ruby.CorePair_Controller.I.PrbInvData 8 0.00% 0.00% 2932system.ruby.CorePair_Controller.I.PrbShrData 5 0.00% 0.00% 2933system.ruby.CorePair_Controller.S.C0_Load_L1hit 635 0.00% 0.00% 2934system.ruby.CorePair_Controller.S.Ifetch0_L1hit 86007 0.00% 0.00% 2935system.ruby.CorePair_Controller.S.Ifetch0_L1miss 54 0.00% 0.00% 2936system.ruby.CorePair_Controller.S.L1I_Repl 589 0.00% 0.00% 2937system.ruby.CorePair_Controller.E0.C0_Load_L1miss 2 0.00% 0.00% 2938system.ruby.CorePair_Controller.E0.C0_Load_L1hit 2721 0.00% 0.00% 2939system.ruby.CorePair_Controller.E0.C0_Store_L1hit 46 0.00% 0.00% 2940system.ruby.CorePair_Controller.E0.L1D0_Repl 16 0.00% 0.00% 2941system.ruby.CorePair_Controller.E0.PrbShrData 1 0.00% 0.00% 2942system.ruby.CorePair_Controller.O.C0_Load_L1hit 3 0.00% 0.00% 2943system.ruby.CorePair_Controller.O.C0_Store_L1hit 1 0.00% 0.00% 2944system.ruby.CorePair_Controller.M0.C0_Load_L1miss 3 0.00% 0.00% 2945system.ruby.CorePair_Controller.M0.C0_Load_L1hit 12796 0.00% 0.00% 2946system.ruby.CorePair_Controller.M0.C0_Store_L1hit 10401 0.00% 0.00% 2947system.ruby.CorePair_Controller.M0.L1D0_Repl 8 0.00% 0.00% 2948system.ruby.CorePair_Controller.M0.PrbInvData 1 0.00% 0.00% 2949system.ruby.CorePair_Controller.M0.PrbShrData 1 0.00% 0.00% 2950system.ruby.CorePair_Controller.I_M0.NB_AckM 325 0.00% 0.00% 2951system.ruby.CorePair_Controller.I_E0S.NB_AckS 9 0.00% 0.00% 2952system.ruby.CorePair_Controller.I_E0S.NB_AckE 166 0.00% 0.00% 2953system.ruby.CorePair_Controller.Si_F0.L2_to_L1I 54 0.00% 0.00% 2954system.ruby.CorePair_Controller.O_M0.NB_AckM 1 0.00% 0.00% 2955system.ruby.CorePair_Controller.S0.NB_AckS 1034 0.00% 0.00% 2956system.ruby.CorePair_Controller.E0_F.L2_to_L1D0 2 0.00% 0.00% 2957system.ruby.CorePair_Controller.M0_F.L2_to_L1D0 3 0.00% 0.00% 2958system.ruby.Directory_Controller.RdBlkS 1039 0.00% 0.00% 2959system.ruby.Directory_Controller.RdBlkM 335 0.00% 0.00% 2960system.ruby.Directory_Controller.RdBlk 177 0.00% 0.00% 2961system.ruby.Directory_Controller.CPUPrbResp 1551 0.00% 0.00% 2962system.ruby.Directory_Controller.ProbeAcksComplete 1551 0.00% 0.00% 2963system.ruby.Directory_Controller.MemData 1551 0.00% 0.00% 2964system.ruby.Directory_Controller.CoreUnblock 1551 0.00% 0.00% 2965system.ruby.Directory_Controller.U.RdBlkS 1039 0.00% 0.00% 2966system.ruby.Directory_Controller.U.RdBlkM 335 0.00% 0.00% 2967system.ruby.Directory_Controller.U.RdBlk 177 0.00% 0.00% 2968system.ruby.Directory_Controller.BS_M.MemData 36 0.00% 0.00% 2969system.ruby.Directory_Controller.BM_M.MemData 13 0.00% 0.00% 2970system.ruby.Directory_Controller.B_M.MemData 12 0.00% 0.00% 2971system.ruby.Directory_Controller.BS_PM.CPUPrbResp 36 0.00% 0.00% 2972system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 36 0.00% 0.00% 2973system.ruby.Directory_Controller.BS_PM.MemData 1003 0.00% 0.00% 2974system.ruby.Directory_Controller.BM_PM.CPUPrbResp 14 0.00% 0.00% 2975system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 13 0.00% 0.00% 2976system.ruby.Directory_Controller.BM_PM.MemData 322 0.00% 0.00% 2977system.ruby.Directory_Controller.B_PM.CPUPrbResp 12 0.00% 0.00% 2978system.ruby.Directory_Controller.B_PM.ProbeAcksComplete 12 0.00% 0.00% 2979system.ruby.Directory_Controller.B_PM.MemData 165 0.00% 0.00% 2980system.ruby.Directory_Controller.BS_Pm.CPUPrbResp 1003 0.00% 0.00% 2981system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 1003 0.00% 0.00% 2982system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 321 0.00% 0.00% 2983system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 322 0.00% 0.00% 2984system.ruby.Directory_Controller.B_Pm.CPUPrbResp 165 0.00% 0.00% 2985system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 165 0.00% 0.00% 2986system.ruby.Directory_Controller.B.CoreUnblock 1551 0.00% 0.00% 2987system.ruby.LD.latency_hist_seqr::bucket_size 64 2988system.ruby.LD.latency_hist_seqr::max_bucket 639 2989system.ruby.LD.latency_hist_seqr::samples 16335 2990system.ruby.LD.latency_hist_seqr::mean 4.314539 2991system.ruby.LD.latency_hist_seqr::gmean 2.104196 2992system.ruby.LD.latency_hist_seqr::stdev 22.794494 2993system.ruby.LD.latency_hist_seqr \| 16160 98.93% 98.93% \| 0 0.00% 98.93% \| 0 0.00% 98.93% \| 166 1.02% 99.94% \| 6 0.04% 99.98% \| 1 0.01% 99.99% \| 0 0.00% 99.99% \| 0 0.00% 99.99% \| 0 0.00% 99.99% \| 2 0.01% 100.00% 2994system.ruby.LD.latency_hist_seqr::total 16335 2995system.ruby.LD.latency_hist_coalsr::bucket_size 64 2996system.ruby.LD.latency_hist_coalsr::max_bucket 639 2997system.ruby.LD.latency_hist_coalsr::samples 9 2998system.ruby.LD.latency_hist_coalsr::mean 219.555556 2999system.ruby.LD.latency_hist_coalsr::gmean 24.880500 3000system.ruby.LD.latency_hist_coalsr::stdev 259.591078 3001system.ruby.LD.latency_hist_coalsr \| 5 55.56% 55.56% \| 0 0.00% 55.56% \| 0 0.00% 55.56% \| 0 0.00% 55.56% \| 0 0.00% 55.56% \| 0 0.00% 55.56% \| 1 11.11% 66.67% \| 1 11.11% 77.78% \| 2 22.22% 100.00% \| 0 0.00% 100.00% 3002system.ruby.LD.latency_hist_coalsr::total 9 3003system.ruby.LD.hit_latency_hist_seqr::bucket_size 64 3004system.ruby.LD.hit_latency_hist_seqr::max_bucket 639 3005system.ruby.LD.hit_latency_hist_seqr::samples 175 3006system.ruby.LD.hit_latency_hist_seqr::mean 217.531429 3007system.ruby.LD.hit_latency_hist_seqr::gmean 214.409561 3008system.ruby.LD.hit_latency_hist_seqr::stdev 50.482703 3009system.ruby.LD.hit_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 166 94.86% 94.86% \| 6 3.43% 98.29% \| 1 0.57% 98.86% \| 0 0.00% 98.86% \| 0 0.00% 98.86% \| 0 0.00% 98.86% \| 2 1.14% 100.00% 3010system.ruby.LD.hit_latency_hist_seqr::total 175 3011system.ruby.LD.miss_latency_hist_seqr::bucket_size 4 3012system.ruby.LD.miss_latency_hist_seqr::max_bucket 39 3013system.ruby.LD.miss_latency_hist_seqr::samples 16160 3014system.ruby.LD.miss_latency_hist_seqr::mean 2.005569 3015system.ruby.LD.miss_latency_hist_seqr::gmean 2.001425 3016system.ruby.LD.miss_latency_hist_seqr::stdev 0.316580 3017system.ruby.LD.miss_latency_hist_seqr \| 16155 99.97% 99.97% \| 0 0.00% 99.97% \| 0 0.00% 99.97% \| 0 0.00% 99.97% \| 0 0.00% 99.97% \| 5 0.03% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3018system.ruby.LD.miss_latency_hist_seqr::total 16160 3019system.ruby.LD.miss_latency_hist_coalsr::bucket_size 64 3020system.ruby.LD.miss_latency_hist_coalsr::max_bucket 639 3021system.ruby.LD.miss_latency_hist_coalsr::samples 9 3022system.ruby.LD.miss_latency_hist_coalsr::mean 219.555556 3023system.ruby.LD.miss_latency_hist_coalsr::gmean 24.880500 3024system.ruby.LD.miss_latency_hist_coalsr::stdev 259.591078 3025system.ruby.LD.miss_latency_hist_coalsr \| 5 55.56% 55.56% \| 0 0.00% 55.56% \| 0 0.00% 55.56% \| 0 0.00% 55.56% \| 0 0.00% 55.56% \| 0 0.00% 55.56% \| 1 11.11% 66.67% \| 1 11.11% 77.78% \| 2 22.22% 100.00% \| 0 0.00% 100.00% 3026system.ruby.LD.miss_latency_hist_coalsr::total 9 3027system.ruby.ST.latency_hist_seqr::bucket_size 64 3028system.ruby.ST.latency_hist_seqr::max_bucket 639 3029system.ruby.ST.latency_hist_seqr::samples 10412 3030system.ruby.ST.latency_hist_seqr::mean 8.469939 3031system.ruby.ST.latency_hist_seqr::gmean 2.309412 3032system.ruby.ST.latency_hist_seqr::stdev 36.833690 3033system.ruby.ST.latency_hist_seqr \| 10090 96.91% 96.91% \| 0 0.00% 96.91% \| 0 0.00% 96.91% \| 314 3.02% 99.92% \| 1 0.01% 99.93% \| 5 0.05% 99.98% \| 0 0.00% 99.98% \| 0 0.00% 99.98% \| 0 0.00% 99.98% \| 2 0.02% 100.00% 3034system.ruby.ST.latency_hist_seqr::total 10412 3035system.ruby.ST.latency_hist_coalsr::bucket_size 32 3036system.ruby.ST.latency_hist_coalsr::max_bucket 319 3037system.ruby.ST.latency_hist_coalsr::samples 16 3038system.ruby.ST.latency_hist_coalsr::mean 125.375000 3039system.ruby.ST.latency_hist_coalsr::gmean 15.802815 3040system.ruby.ST.latency_hist_coalsr::stdev 128.476133 3041system.ruby.ST.latency_hist_coalsr \| 8 50.00% 50.00% \| 0 0.00% 50.00% \| 0 0.00% 50.00% \| 0 0.00% 50.00% \| 0 0.00% 50.00% \| 0 0.00% 50.00% \| 0 0.00% 50.00% \| 7 43.75% 93.75% \| 1 6.25% 100.00% \| 0 0.00% 100.00% 3042system.ruby.ST.latency_hist_coalsr::total 16 3043system.ruby.ST.hit_latency_hist_seqr::bucket_size 64 3044system.ruby.ST.hit_latency_hist_seqr::max_bucket 639 3045system.ruby.ST.hit_latency_hist_seqr::samples 322 3046system.ruby.ST.hit_latency_hist_seqr::mean 211.208075 3047system.ruby.ST.hit_latency_hist_seqr::gmean 209.444324 3048system.ruby.ST.hit_latency_hist_seqr::stdev 38.157121 3049system.ruby.ST.hit_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 314 97.52% 97.52% \| 1 0.31% 97.83% \| 5 1.55% 99.38% \| 0 0.00% 99.38% \| 0 0.00% 99.38% \| 0 0.00% 99.38% \| 2 0.62% 100.00% 3050system.ruby.ST.hit_latency_hist_seqr::total 322 3051system.ruby.ST.miss_latency_hist_seqr::bucket_size 1 3052system.ruby.ST.miss_latency_hist_seqr::max_bucket 9 3053system.ruby.ST.miss_latency_hist_seqr::samples 10090 3054system.ruby.ST.miss_latency_hist_seqr::mean 2 3055system.ruby.ST.miss_latency_hist_seqr::gmean 2.000000 3056system.ruby.ST.miss_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 10090 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3057system.ruby.ST.miss_latency_hist_seqr::total 10090 3058system.ruby.ST.miss_latency_hist_coalsr::bucket_size 32 3059system.ruby.ST.miss_latency_hist_coalsr::max_bucket 319 3060system.ruby.ST.miss_latency_hist_coalsr::samples 16 3061system.ruby.ST.miss_latency_hist_coalsr::mean 125.375000 3062system.ruby.ST.miss_latency_hist_coalsr::gmean 15.802815 3063system.ruby.ST.miss_latency_hist_coalsr::stdev 128.476133 3064system.ruby.ST.miss_latency_hist_coalsr \| 8 50.00% 50.00% \| 0 0.00% 50.00% \| 0 0.00% 50.00% \| 0 0.00% 50.00% \| 0 0.00% 50.00% \| 0 0.00% 50.00% \| 0 0.00% 50.00% \| 7 43.75% 93.75% \| 1 6.25% 100.00% \| 0 0.00% 100.00% 3065system.ruby.ST.miss_latency_hist_coalsr::total 16 3066system.ruby.ATOMIC.latency_hist_coalsr::bucket_size 64 3067system.ruby.ATOMIC.latency_hist_coalsr::max_bucket 639 3068system.ruby.ATOMIC.latency_hist_coalsr::samples 2 3069system.ruby.ATOMIC.latency_hist_coalsr::mean 317.500000 3070system.ruby.ATOMIC.latency_hist_coalsr::gmean 314.366029 3071system.ruby.ATOMIC.latency_hist_coalsr::stdev 62.932504 3072system.ruby.ATOMIC.latency_hist_coalsr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 1 50.00% 50.00% \| 1 50.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3073system.ruby.ATOMIC.latency_hist_coalsr::total 2 3074system.ruby.ATOMIC.miss_latency_hist_coalsr::bucket_size 64 3075system.ruby.ATOMIC.miss_latency_hist_coalsr::max_bucket 639 3076system.ruby.ATOMIC.miss_latency_hist_coalsr::samples 2 3077system.ruby.ATOMIC.miss_latency_hist_coalsr::mean 317.500000 3078system.ruby.ATOMIC.miss_latency_hist_coalsr::gmean 314.366029 3079system.ruby.ATOMIC.miss_latency_hist_coalsr::stdev 62.932504 3080system.ruby.ATOMIC.miss_latency_hist_coalsr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 1 50.00% 50.00% \| 1 50.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3081system.ruby.ATOMIC.miss_latency_hist_coalsr::total 2 3082system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 3083system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 3084system.ruby.IFETCH.latency_hist_seqr::samples 87095 3085system.ruby.IFETCH.latency_hist_seqr::mean 4.485148 3086system.ruby.IFETCH.latency_hist_seqr::gmean 2.116532 3087system.ruby.IFETCH.latency_hist_seqr::stdev 22.815865 3088system.ruby.IFETCH.latency_hist_seqr \| 86061 98.81% 98.81% \| 0 0.00% 98.81% \| 0 0.00% 98.81% \| 1006 1.16% 99.97% \| 11 0.01% 99.98% \| 12 0.01% 99.99% \| 2 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 3 0.00% 100.00% 3089system.ruby.IFETCH.latency_hist_seqr::total 87095 3090system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 64 3091system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 639 3092system.ruby.IFETCH.hit_latency_hist_seqr::samples 1034 3093system.ruby.IFETCH.hit_latency_hist_seqr::mean 210.386847 3094system.ruby.IFETCH.hit_latency_hist_seqr::gmean 209.145816 3095system.ruby.IFETCH.hit_latency_hist_seqr::stdev 30.434753 3096system.ruby.IFETCH.hit_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 1006 97.29% 97.29% \| 11 1.06% 98.36% \| 12 1.16% 99.52% \| 2 0.19% 99.71% \| 0 0.00% 99.71% \| 0 0.00% 99.71% \| 3 0.29% 100.00% 3097system.ruby.IFETCH.hit_latency_hist_seqr::total 1034 3098system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 4 3099system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 39 3100system.ruby.IFETCH.miss_latency_hist_seqr::samples 86061 3101system.ruby.IFETCH.miss_latency_hist_seqr::mean 2.011294 3102system.ruby.IFETCH.miss_latency_hist_seqr::gmean 2.002892 3103system.ruby.IFETCH.miss_latency_hist_seqr::stdev 0.450747 3104system.ruby.IFETCH.miss_latency_hist_seqr \| 86007 99.94% 99.94% \| 0 0.00% 99.94% \| 0 0.00% 99.94% \| 0 0.00% 99.94% \| 0 0.00% 99.94% \| 54 0.06% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3105system.ruby.IFETCH.miss_latency_hist_seqr::total 86061 3106system.ruby.RMW_Read.latency_hist_seqr::bucket_size 32 3107system.ruby.RMW_Read.latency_hist_seqr::max_bucket 319 3108system.ruby.RMW_Read.latency_hist_seqr::samples 341 3109system.ruby.RMW_Read.latency_hist_seqr::mean 4.392962 3110system.ruby.RMW_Read.latency_hist_seqr::gmean 2.111743 3111system.ruby.RMW_Read.latency_hist_seqr::stdev 21.996747 3112system.ruby.RMW_Read.latency_hist_seqr \| 337 98.83% 98.83% \| 0 0.00% 98.83% \| 0 0.00% 98.83% \| 0 0.00% 98.83% \| 0 0.00% 98.83% \| 0 0.00% 98.83% \| 4 1.17% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3113system.ruby.RMW_Read.latency_hist_seqr::total 341 3114system.ruby.RMW_Read.hit_latency_hist_seqr::bucket_size 32 3115system.ruby.RMW_Read.hit_latency_hist_seqr::max_bucket 319 3116system.ruby.RMW_Read.hit_latency_hist_seqr::samples 4 3117system.ruby.RMW_Read.hit_latency_hist_seqr::mean 206 3118system.ruby.RMW_Read.hit_latency_hist_seqr::gmean 206.000000 3119system.ruby.RMW_Read.hit_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 4 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3120system.ruby.RMW_Read.hit_latency_hist_seqr::total 4 3121system.ruby.RMW_Read.miss_latency_hist_seqr::bucket_size 1 3122system.ruby.RMW_Read.miss_latency_hist_seqr::max_bucket 9 3123system.ruby.RMW_Read.miss_latency_hist_seqr::samples 337 3124system.ruby.RMW_Read.miss_latency_hist_seqr::mean 2 3125system.ruby.RMW_Read.miss_latency_hist_seqr::gmean 2.000000 3126system.ruby.RMW_Read.miss_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 337 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3127system.ruby.RMW_Read.miss_latency_hist_seqr::total 337 3128system.ruby.Locked_RMW_Read.latency_hist_seqr::bucket_size 1 3129system.ruby.Locked_RMW_Read.latency_hist_seqr::max_bucket 9 3130system.ruby.Locked_RMW_Read.latency_hist_seqr::samples 10 3131system.ruby.Locked_RMW_Read.latency_hist_seqr::mean 2 3132system.ruby.Locked_RMW_Read.latency_hist_seqr::gmean 2 3133system.ruby.Locked_RMW_Read.latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 10 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3134system.ruby.Locked_RMW_Read.latency_hist_seqr::total 10 3135system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::bucket_size 1 3136system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::max_bucket 9 3137system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::samples 10 3138system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::mean 2 3139system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::gmean 2 3140system.ruby.Locked_RMW_Read.miss_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 10 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3141system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::total 10 3142system.ruby.Locked_RMW_Write.latency_hist_seqr::bucket_size 1 3143system.ruby.Locked_RMW_Write.latency_hist_seqr::max_bucket 9 3144system.ruby.Locked_RMW_Write.latency_hist_seqr::samples 10 3145system.ruby.Locked_RMW_Write.latency_hist_seqr::mean 2 3146system.ruby.Locked_RMW_Write.latency_hist_seqr::gmean 2 3147system.ruby.Locked_RMW_Write.latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 10 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3148system.ruby.Locked_RMW_Write.latency_hist_seqr::total 10 3149system.ruby.Locked_RMW_Write.miss_latency_hist_seqr::bucket_size 1 3150system.ruby.Locked_RMW_Write.miss_latency_hist_seqr::max_bucket 9 3151system.ruby.Locked_RMW_Write.miss_latency_hist_seqr::samples 10 3152system.ruby.Locked_RMW_Write.miss_latency_hist_seqr::mean 2 3153system.ruby.Locked_RMW_Write.miss_latency_hist_seqr::gmean 2 3154system.ruby.Locked_RMW_Write.miss_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 10 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3155system.ruby.Locked_RMW_Write.miss_latency_hist_seqr::total 10 3156system.ruby.L1Cache.miss_mach_latency_hist_seqr::bucket_size 1 3157system.ruby.L1Cache.miss_mach_latency_hist_seqr::max_bucket 9 3158system.ruby.L1Cache.miss_mach_latency_hist_seqr::samples 112609 3159system.ruby.L1Cache.miss_mach_latency_hist_seqr::mean 2 3160system.ruby.L1Cache.miss_mach_latency_hist_seqr::gmean 2.000000 3161system.ruby.L1Cache.miss_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 112609 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3162system.ruby.L1Cache.miss_mach_latency_hist_seqr::total 112609 3163system.ruby.L2Cache.miss_mach_latency_hist_seqr::bucket_size 4 3164system.ruby.L2Cache.miss_mach_latency_hist_seqr::max_bucket 39 3165system.ruby.L2Cache.miss_mach_latency_hist_seqr::samples 59 3166system.ruby.L2Cache.miss_mach_latency_hist_seqr::mean 20 3167system.ruby.L2Cache.miss_mach_latency_hist_seqr::gmean 20.000000 3168system.ruby.L2Cache.miss_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 59 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3169system.ruby.L2Cache.miss_mach_latency_hist_seqr::total 59 3170system.ruby.Directory.hit_mach_latency_hist_seqr::bucket_size 64 3171system.ruby.Directory.hit_mach_latency_hist_seqr::max_bucket 639 3172system.ruby.Directory.hit_mach_latency_hist_seqr::samples 1535 3173system.ruby.Directory.hit_mach_latency_hist_seqr::mean 211.362215 3174system.ruby.Directory.hit_mach_latency_hist_seqr::gmean 209.793806 3175system.ruby.Directory.hit_mach_latency_hist_seqr::stdev 34.965177 3176system.ruby.Directory.hit_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 1490 97.07% 97.07% \| 18 1.17% 98.24% \| 18 1.17% 99.41% \| 2 0.13% 99.54% \| 0 0.00% 99.54% \| 0 0.00% 99.54% \| 7 0.46% 100.00% 3177system.ruby.Directory.hit_mach_latency_hist_seqr::total 1535 3178system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::bucket_size 64 3179system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::max_bucket 639 3180system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::samples 3 3181system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean 478.666667 3182system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 470.839796 3183system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 101.159939 3184system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 1 33.33% 33.33% \| 0 0.00% 33.33% \| 0 0.00% 33.33% \| 2 66.67% 100.00% \| 0 0.00% 100.00% 3185system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::total 3 3186system.ruby.TCP.miss_mach_latency_hist_coalsr::bucket_size 1 3187system.ruby.TCP.miss_mach_latency_hist_coalsr::max_bucket 9 3188system.ruby.TCP.miss_mach_latency_hist_coalsr::samples 13 3189system.ruby.TCP.miss_mach_latency_hist_coalsr::mean 1.538462 3190system.ruby.TCP.miss_mach_latency_hist_coalsr::gmean 1.377009 3191system.ruby.TCP.miss_mach_latency_hist_coalsr::stdev 0.877058 3192system.ruby.TCP.miss_mach_latency_hist_coalsr \| 0 0.00% 0.00% \| 8 61.54% 61.54% \| 4 30.77% 92.31% \| 0 0.00% 92.31% \| 1 7.69% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3193system.ruby.TCP.miss_mach_latency_hist_coalsr::total 13 3194system.ruby.TCCdir.miss_mach_latency_hist_coalsr::bucket_size 64 3195system.ruby.TCCdir.miss_mach_latency_hist_coalsr::max_bucket 639 3196system.ruby.TCCdir.miss_mach_latency_hist_coalsr::samples 11 3197system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 287.363636 3198system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 279.637814 3199system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 78.345737 3200system.ruby.TCCdir.miss_mach_latency_hist_coalsr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 7 63.64% 63.64% \| 2 18.18% 81.82% \| 0 0.00% 81.82% \| 1 9.09% 90.91% \| 1 9.09% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3201system.ruby.TCCdir.miss_mach_latency_hist_coalsr::total 11 3202system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 3203system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 3204system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::samples 16155 3205system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 3206system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000 3207system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 16155 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3208system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::total 16155 3209system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::bucket_size 4 3210system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::max_bucket 39 3211system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::samples 5 3212system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::mean 20 3213system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::gmean 20.000000 3214system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 5 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3215system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::total 5 3216system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::bucket_size 64 3217system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::max_bucket 639 3218system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::samples 175 3219system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::mean 217.531429 3220system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::gmean 214.409561 3221system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::stdev 50.482703 3222system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 166 94.86% 94.86% \| 6 3.43% 98.29% \| 1 0.57% 98.86% \| 0 0.00% 98.86% \| 0 0.00% 98.86% \| 0 0.00% 98.86% \| 2 1.14% 100.00% 3223system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::total 175 3224system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64 3225system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639 3226system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 2 3227system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 537 3228system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 536.976722 3229system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev 7.071068 3230system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 2 100.00% 100.00% \| 0 0.00% 100.00% 3231system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 2 3232system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 3233system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 3234system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::samples 5 3235system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::mean 2.400000 3236system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::gmean 2.297397 3237system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::stdev 0.894427 3238system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 4 80.00% 80.00% \| 0 0.00% 80.00% \| 1 20.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3239system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::total 5 3240system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 64 3241system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 639 3242system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::samples 2 3243system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean 445 3244system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 444.959549 3245system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 8.485281 3246system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 1 50.00% 50.00% \| 1 50.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3247system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::total 2 3248system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 3249system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 3250system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::samples 10090 3251system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 3252system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000 3253system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 10090 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3254system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::total 10090 3255system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::bucket_size 64 3256system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::max_bucket 639 3257system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::samples 322 3258system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::mean 211.208075 3259system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::gmean 209.444324 3260system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::stdev 38.157121 3261system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 314 97.52% 97.52% \| 1 0.31% 97.83% \| 5 1.55% 99.38% \| 0 0.00% 99.38% \| 0 0.00% 99.38% \| 0 0.00% 99.38% \| 2 0.62% 100.00% 3262system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::total 322 3263system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 3264system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 3265system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::samples 8 3266system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::mean 1 3267system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::gmean 1 3268system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr \| 0 0.00% 0.00% \| 8 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3269system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::total 8 3270system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32 3271system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319 3272system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::samples 8 3273system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 249.750000 3274system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 249.728954 3275system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 3.494894 3276system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 7 87.50% 87.50% \| 1 12.50% 100.00% \| 0 0.00% 100.00% 3277system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::total 8 3278system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64 3279system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639 3280system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 1 3281system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 362 3282system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 362.000000 3283system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev nan 3284system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 1 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3285system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 1 3286system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32 3287system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319 3288system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::samples 1 3289system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::mean 273 3290system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 273 3291system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::stdev nan 3292system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 1 100.00% 100.00% \| 0 0.00% 100.00% 3293system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::total 1 3294system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 3295system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 3296system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::samples 86007 3297system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 3298system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000 3299system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 86007 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3300system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::total 86007 3301system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::bucket_size 4 3302system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::max_bucket 39 3303system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::samples 54 3304system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::mean 20 3305system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::gmean 20.000000 3306system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 54 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3307system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::total 54 3308system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::bucket_size 64 3309system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::max_bucket 639 3310system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::samples 1034 3311system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::mean 210.386847 3312system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::gmean 209.145816 3313system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::stdev 30.434753 3314system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 1006 97.29% 97.29% \| 11 1.06% 98.36% \| 12 1.16% 99.52% \| 2 0.19% 99.71% \| 0 0.00% 99.71% \| 0 0.00% 99.71% \| 3 0.29% 100.00% 3315system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::total 1034 3316system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 3317system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 3318system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::samples 337 3319system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 3320system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000 3321system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 337 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3322system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::total 337 3323system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::bucket_size 32 3324system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::max_bucket 319 3325system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::samples 4 3326system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::mean 206 3327system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::gmean 206.000000 3328system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 4 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3329system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::total 4 3330system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 3331system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 3332system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::samples 10 3333system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 3334system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2 3335system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 10 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3336system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::total 10 3337system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 3338system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 3339system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::samples 10 3340system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 3341system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2 3342system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 10 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 3343system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::total 10 3344system.ruby.SQC_Controller.Fetch 86 0.00% 0.00% 3345system.ruby.SQC_Controller.TCC_AckS 5 0.00% 0.00% 3346system.ruby.SQC_Controller.I.Fetch 5 0.00% 0.00% 3347system.ruby.SQC_Controller.S.Fetch 81 0.00% 0.00% 3348system.ruby.SQC_Controller.I_S.TCC_AckS 5 0.00% 0.00% 3349system.ruby.TCCdir_Controller.RdBlk 93 0.00% 0.00% 3350system.ruby.TCCdir_Controller.RdBlkM 37 0.00% 0.00% 3351system.ruby.TCCdir_Controller.RdBlkS 5 0.00% 0.00% 3352system.ruby.TCCdir_Controller.CPUPrbResp 14 0.00% 0.00% 3353system.ruby.TCCdir_Controller.ProbeAcksComplete 13 0.00% 0.00% 3354system.ruby.TCCdir_Controller.CoreUnblock 17 0.00% 0.00% 3355system.ruby.TCCdir_Controller.LastCoreUnblock 2 0.00% 0.00% 3356system.ruby.TCCdir_Controller.NB_AckS 7 0.00% 0.00% 3357system.ruby.TCCdir_Controller.NB_AckM 9 0.00% 0.00% 3358system.ruby.TCCdir_Controller.PrbInvData 326 0.00% 0.00% 3359system.ruby.TCCdir_Controller.PrbShrData 1209 0.00% 0.00% 3360system.ruby.TCCdir_Controller.I.RdBlk 2 0.00% 0.00% 3361system.ruby.TCCdir_Controller.I.RdBlkM 9 0.00% 0.00% 3362system.ruby.TCCdir_Controller.I.RdBlkS 5 0.00% 0.00% 3363system.ruby.TCCdir_Controller.I.PrbInvData 325 0.00% 0.00% 3364system.ruby.TCCdir_Controller.I.PrbShrData 1200 0.00% 0.00% 3365system.ruby.TCCdir_Controller.S.RdBlk 2 0.00% 0.00% 3366system.ruby.TCCdir_Controller.S.PrbInvData 1 0.00% 0.00% 3367system.ruby.TCCdir_Controller.M.RdBlkM 1 0.00% 0.00% 3368system.ruby.TCCdir_Controller.M.PrbShrData 9 0.00% 0.00% 3369system.ruby.TCCdir_Controller.CP_I.CPUPrbResp 2 0.00% 0.00% 3370system.ruby.TCCdir_Controller.CP_I.ProbeAcksComplete 1 0.00% 0.00% 3371system.ruby.TCCdir_Controller.CP_O.CPUPrbResp 9 0.00% 0.00% 3372system.ruby.TCCdir_Controller.CP_O.ProbeAcksComplete 9 0.00% 0.00% 3373system.ruby.TCCdir_Controller.I_M.RdBlkM 22 0.00% 0.00% 3374system.ruby.TCCdir_Controller.I_M.NB_AckM 9 0.00% 0.00% 3375system.ruby.TCCdir_Controller.I_ES.RdBlk 79 0.00% 0.00% 3376system.ruby.TCCdir_Controller.I_ES.NB_AckS 2 0.00% 0.00% 3377system.ruby.TCCdir_Controller.I_S.NB_AckS 5 0.00% 0.00% 3378system.ruby.TCCdir_Controller.BBS_S.CPUPrbResp 2 0.00% 0.00% 3379system.ruby.TCCdir_Controller.BBS_S.ProbeAcksComplete 2 0.00% 0.00% 3380system.ruby.TCCdir_Controller.BBM_M.CPUPrbResp 1 0.00% 0.00% 3381system.ruby.TCCdir_Controller.BBM_M.ProbeAcksComplete 1 0.00% 0.00% 3382system.ruby.TCCdir_Controller.BB_M.CoreUnblock 1 0.00% 0.00% 3383system.ruby.TCCdir_Controller.BB_S.LastCoreUnblock 2 0.00% 0.00% 3384system.ruby.TCCdir_Controller.BBB_S.RdBlk 10 0.00% 0.00% 3385system.ruby.TCCdir_Controller.BBB_S.CoreUnblock 7 0.00% 0.00% 3386system.ruby.TCCdir_Controller.BBB_M.RdBlkM 5 0.00% 0.00% 3387system.ruby.TCCdir_Controller.BBB_M.CoreUnblock 9 0.00% 0.00% 3388system.ruby.TCP_Controller.Load \| 4 44.44% 44.44% \| 5 55.56% 100.00% 3389system.ruby.TCP_Controller.Load::total 9 3390system.ruby.TCP_Controller.Store \| 9 50.00% 50.00% \| 9 50.00% 100.00% 3391system.ruby.TCP_Controller.Store::total 18 3392system.ruby.TCP_Controller.TCC_AckS \| 2 50.00% 50.00% \| 2 50.00% 100.00% 3393system.ruby.TCP_Controller.TCC_AckS::total 4 3394system.ruby.TCP_Controller.TCC_AckM \| 5 50.00% 50.00% \| 5 50.00% 100.00% 3395system.ruby.TCP_Controller.TCC_AckM::total 10 3396system.ruby.TCP_Controller.PrbInvData \| 1 33.33% 33.33% \| 2 66.67% 100.00% 3397system.ruby.TCP_Controller.PrbInvData::total 3 3398system.ruby.TCP_Controller.PrbShrData \| 7 63.64% 63.64% \| 4 36.36% 100.00% 3399system.ruby.TCP_Controller.PrbShrData::total 11 3400system.ruby.TCP_Controller.I.Load \| 2 50.00% 50.00% \| 2 50.00% 100.00% 3401system.ruby.TCP_Controller.I.Load::total 4 3402system.ruby.TCP_Controller.I.Store \| 5 50.00% 50.00% \| 5 50.00% 100.00% 3403system.ruby.TCP_Controller.I.Store::total 10 3404system.ruby.TCP_Controller.S.Load \| 2 40.00% 40.00% \| 3 60.00% 100.00% 3405system.ruby.TCP_Controller.S.Load::total 5 3406system.ruby.TCP_Controller.S.PrbInvData \| 1 50.00% 50.00% \| 1 50.00% 100.00% 3407system.ruby.TCP_Controller.S.PrbInvData::total 2 3408system.ruby.TCP_Controller.S.PrbShrData \| 2 100.00% 100.00% \| 0 0.00% 100.00% 3409system.ruby.TCP_Controller.S.PrbShrData::total 2 3410system.ruby.TCP_Controller.M.Store \| 4 50.00% 50.00% \| 4 50.00% 100.00% 3411system.ruby.TCP_Controller.M.Store::total 8 3412system.ruby.TCP_Controller.M.PrbInvData \| 0 0.00% 0.00% \| 1 100.00% 100.00% 3413system.ruby.TCP_Controller.M.PrbInvData::total 1 3414system.ruby.TCP_Controller.M.PrbShrData \| 5 55.56% 55.56% \| 4 44.44% 100.00% 3415system.ruby.TCP_Controller.M.PrbShrData::total 9 3416system.ruby.TCP_Controller.I_M.TCC_AckM \| 5 50.00% 50.00% \| 5 50.00% 100.00% 3417system.ruby.TCP_Controller.I_M.TCC_AckM::total 10 3418system.ruby.TCP_Controller.I_ES.TCC_AckS \| 2 50.00% 50.00% \| 2 50.00% 100.00% 3419system.ruby.TCP_Controller.I_ES.TCC_AckS::total 4 3420 3421---------- End Simulation Statistics ----------