1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000663 # Number of seconds simulated
4sim_ticks 663454500 # Number of ticks simulated
5final_tick 663454500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 237471 # Simulator instruction rate (inst/s)
8host_op_rate 488329 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2352682974 # Simulator tick rate (ticks/s)
10host_mem_usage 1358064 # Number of bytes of host memory used
11host_seconds 0.28 # Real time elapsed on the host
12sim_insts 66963 # Number of instructions simulated
13sim_ops 137705 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
17system.mem_ctrls.bytes_read::dir_cntrl0 99264 # Number of bytes read from this memory
18system.mem_ctrls.bytes_read::total 99264 # Number of bytes read from this memory
19system.mem_ctrls.num_reads::dir_cntrl0 1551 # Number of read requests responded to by this memory
20system.mem_ctrls.num_reads::total 1551 # Number of read requests responded to by this memory
21system.mem_ctrls.bw_read::dir_cntrl0 149616892 # Total read bandwidth from this memory (bytes/s)
22system.mem_ctrls.bw_read::total 149616892 # Total read bandwidth from this memory (bytes/s)
23system.mem_ctrls.bw_total::dir_cntrl0 149616892 # Total bandwidth to/from this memory (bytes/s)
24system.mem_ctrls.bw_total::total 149616892 # Total bandwidth to/from this memory (bytes/s)
25system.mem_ctrls.readReqs 1551 # Number of read requests accepted
26system.mem_ctrls.writeReqs 0 # Number of write requests accepted
27system.mem_ctrls.readBursts 1551 # Number of DRAM read bursts, including those serviced by the write queue
28system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
29system.mem_ctrls.bytesReadDRAM 99264 # Total number of bytes read from DRAM
30system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue
31system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM
32system.mem_ctrls.bytesReadSys 99264 # Total read bytes from the system interface side

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63system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts
64system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
65system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
66system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts
67system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts
68system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
69system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
70system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
71system.mem_ctrls.totGap 663221000 # Total gap between requests
72system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
73system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
74system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
75system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
76system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
77system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
78system.mem_ctrls.readPktSize::6 1551 # Read request sizes (log2)
79system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
80system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
81system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
82system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
83system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
84system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
85system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2)
86system.mem_ctrls.rdQLenPdf::0 1542 # What read queue length does an incoming req see
87system.mem_ctrls.rdQLenPdf::1 2 # What read queue length does an incoming req see
88system.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see
89system.mem_ctrls.rdQLenPdf::3 1 # What read queue length does an incoming req see
90system.mem_ctrls.rdQLenPdf::4 2 # What read queue length does an incoming req see
91system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see
92system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see
93system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
94system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
95system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
96system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
97system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
98system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
99system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
100system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
101system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see

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174system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
175system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
176system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
177system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
178system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
179system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
180system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
181system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
182system.mem_ctrls.bytesPerActivate::samples 485 # Bytes accessed per row activation
183system.mem_ctrls.bytesPerActivate::mean 204.008247 # Bytes accessed per row activation
184system.mem_ctrls.bytesPerActivate::gmean 145.772769 # Bytes accessed per row activation
185system.mem_ctrls.bytesPerActivate::stdev 192.306659 # Bytes accessed per row activation
186system.mem_ctrls.bytesPerActivate::0-127 178 36.70% 36.70% # Bytes accessed per row activation
187system.mem_ctrls.bytesPerActivate::128-255 156 32.16% 68.87% # Bytes accessed per row activation
188system.mem_ctrls.bytesPerActivate::256-383 70 14.43% 83.30% # Bytes accessed per row activation
189system.mem_ctrls.bytesPerActivate::384-511 40 8.25% 91.55% # Bytes accessed per row activation
190system.mem_ctrls.bytesPerActivate::512-639 15 3.09% 94.64% # Bytes accessed per row activation
191system.mem_ctrls.bytesPerActivate::640-767 10 2.06% 96.70% # Bytes accessed per row activation
192system.mem_ctrls.bytesPerActivate::768-895 9 1.86% 98.56% # Bytes accessed per row activation
193system.mem_ctrls.bytesPerActivate::896-1023 2 0.41% 98.97% # Bytes accessed per row activation
194system.mem_ctrls.bytesPerActivate::1024-1151 5 1.03% 100.00% # Bytes accessed per row activation
195system.mem_ctrls.bytesPerActivate::total 485 # Bytes accessed per row activation
196system.mem_ctrls.totQLat 15500495 # Total ticks spent queuing
197system.mem_ctrls.totMemAccLat 44581745 # Total ticks spent from burst creation until serviced by the DRAM
198system.mem_ctrls.totBusLat 7755000 # Total ticks spent in databus transfers
199system.mem_ctrls.avgQLat 9993.87 # Average queueing delay per DRAM burst
200system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst
201system.mem_ctrls.avgMemAccLat 28743.87 # Average memory access latency per DRAM burst
202system.mem_ctrls.avgRdBW 149.62 # Average DRAM read bandwidth in MiByte/s
203system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
204system.mem_ctrls.avgRdBWSys 149.62 # Average system read bandwidth in MiByte/s
205system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
206system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
207system.mem_ctrls.busUtil 1.17 # Data bus utilization in percentage
208system.mem_ctrls.busUtilRead 1.17 # Data bus utilization in percentage for reads
209system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes
210system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
211system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing
212system.mem_ctrls.readRowHits 1062 # Number of row buffer hits during reads
213system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes
214system.mem_ctrls.readRowHitRate 68.47 # Row buffer hit rate for reads
215system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes
216system.mem_ctrls.avgGap 427608.64 # Average gap between requests
217system.mem_ctrls.pageHitRate 68.47 # Row buffer hit rate, read and write combined
218system.mem_ctrls_0.actEnergy 1391040 # Energy for activate commands per rank (pJ)
219system.mem_ctrls_0.preEnergy 759000 # Energy for precharge commands per rank (pJ)
220system.mem_ctrls_0.readEnergy 5335200 # Energy for read commands per rank (pJ)
221system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ)
222system.mem_ctrls_0.refreshEnergy 43227600 # Energy for refresh commands per rank (pJ)
223system.mem_ctrls_0.actBackEnergy 335485755 # Energy for active background per rank (pJ)
224system.mem_ctrls_0.preBackEnergy 102969000 # Energy for precharge background per rank (pJ)
225system.mem_ctrls_0.totalEnergy 489167595 # Total energy per rank (pJ)
226system.mem_ctrls_0.averagePower 738.822020 # Core power per rank (mW)
227system.mem_ctrls_0.memoryStateTime::IDLE 170399250 # Time in different power states
228system.mem_ctrls_0.memoryStateTime::REF 22100000 # Time in different power states
229system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
230system.mem_ctrls_0.memoryStateTime::ACT 470741750 # Time in different power states
231system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
232system.mem_ctrls_1.actEnergy 2275560 # Energy for activate commands per rank (pJ)
233system.mem_ctrls_1.preEnergy 1241625 # Energy for precharge commands per rank (pJ)
234system.mem_ctrls_1.readEnergy 6723600 # Energy for read commands per rank (pJ)
235system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ)
236system.mem_ctrls_1.refreshEnergy 43227600 # Energy for refresh commands per rank (pJ)
237system.mem_ctrls_1.actBackEnergy 371983995 # Energy for active background per rank (pJ)
238system.mem_ctrls_1.preBackEnergy 70953000 # Energy for precharge background per rank (pJ)
239system.mem_ctrls_1.totalEnergy 496405380 # Total energy per rank (pJ)
240system.mem_ctrls_1.averagePower 749.753724 # Core power per rank (mW)
241system.mem_ctrls_1.memoryStateTime::IDLE 115859750 # Time in different power states
242system.mem_ctrls_1.memoryStateTime::REF 22100000 # Time in different power states
243system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
244system.mem_ctrls_1.memoryStateTime::ACT 524145250 # Time in different power states
245system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
246system.ruby.clk_domain.clock 500 # Clock period in ticks
247system.ruby.phys_mem.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
248system.ruby.phys_mem.bytes_read::cpu0.inst 696760 # Number of bytes read from this memory
249system.ruby.phys_mem.bytes_read::cpu0.data 119832 # Number of bytes read from this memory
250system.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 3280 # Number of bytes read from this memory
251system.ruby.phys_mem.bytes_read::cpu1.CUs1.ComputeUnit 3280 # Number of bytes read from this memory
252system.ruby.phys_mem.bytes_read::total 823152 # Number of bytes read from this memory
253system.ruby.phys_mem.bytes_inst_read::cpu0.inst 696760 # Number of instructions bytes read from this memory
254system.ruby.phys_mem.bytes_inst_read::cpu1.CUs0.ComputeUnit 2000 # Number of instructions bytes read from this memory
255system.ruby.phys_mem.bytes_inst_read::cpu1.CUs1.ComputeUnit 2000 # Number of instructions bytes read from this memory

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262system.ruby.phys_mem.num_reads::cpu0.data 16686 # Number of read requests responded to by this memory
263system.ruby.phys_mem.num_reads::cpu1.CUs0.ComputeUnit 555 # Number of read requests responded to by this memory
264system.ruby.phys_mem.num_reads::cpu1.CUs1.ComputeUnit 555 # Number of read requests responded to by this memory
265system.ruby.phys_mem.num_reads::total 104891 # Number of read requests responded to by this memory
266system.ruby.phys_mem.num_writes::cpu0.data 10422 # Number of write requests responded to by this memory
267system.ruby.phys_mem.num_writes::cpu1.CUs0.ComputeUnit 256 # Number of write requests responded to by this memory
268system.ruby.phys_mem.num_writes::cpu1.CUs1.ComputeUnit 256 # Number of write requests responded to by this memory
269system.ruby.phys_mem.num_writes::total 10934 # Number of write requests responded to by this memory
270system.ruby.phys_mem.bw_read::cpu0.inst 1050200127 # Total read bandwidth from this memory (bytes/s)
271system.ruby.phys_mem.bw_read::cpu0.data 180618264 # Total read bandwidth from this memory (bytes/s)
272system.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit 4943821 # Total read bandwidth from this memory (bytes/s)
273system.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit 4943821 # Total read bandwidth from this memory (bytes/s)
274system.ruby.phys_mem.bw_read::total 1240706032 # Total read bandwidth from this memory (bytes/s)
275system.ruby.phys_mem.bw_inst_read::cpu0.inst 1050200127 # Instruction read bandwidth from this memory (bytes/s)
276system.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit 3014525 # Instruction read bandwidth from this memory (bytes/s)
277system.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit 3014525 # Instruction read bandwidth from this memory (bytes/s)
278system.ruby.phys_mem.bw_inst_read::total 1056229176 # Instruction read bandwidth from this memory (bytes/s)
279system.ruby.phys_mem.bw_write::cpu0.data 109678961 # Write bandwidth from this memory (bytes/s)
280system.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit 385859 # Write bandwidth from this memory (bytes/s)
281system.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit 385859 # Write bandwidth from this memory (bytes/s)
282system.ruby.phys_mem.bw_write::total 110450679 # Write bandwidth from this memory (bytes/s)
283system.ruby.phys_mem.bw_total::cpu0.inst 1050200127 # Total bandwidth to/from this memory (bytes/s)
284system.ruby.phys_mem.bw_total::cpu0.data 290297225 # Total bandwidth to/from this memory (bytes/s)
285system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 5329680 # Total bandwidth to/from this memory (bytes/s)
286system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 5329680 # Total bandwidth to/from this memory (bytes/s)
287system.ruby.phys_mem.bw_total::total 1351156711 # Total bandwidth to/from this memory (bytes/s)
288system.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
289system.ruby.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
290system.ruby.outstanding_req_hist_seqr::bucket_size 1
291system.ruby.outstanding_req_hist_seqr::max_bucket 9
292system.ruby.outstanding_req_hist_seqr::samples 114203
293system.ruby.outstanding_req_hist_seqr::mean 1.000035
294system.ruby.outstanding_req_hist_seqr::gmean 1.000024
295system.ruby.outstanding_req_hist_seqr::stdev 0.005918
296system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 114199 100.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
297system.ruby.outstanding_req_hist_seqr::total 114203
298system.ruby.outstanding_req_hist_coalsr::bucket_size 1
299system.ruby.outstanding_req_hist_coalsr::max_bucket 9
300system.ruby.outstanding_req_hist_coalsr::samples 27
301system.ruby.outstanding_req_hist_coalsr::mean 1.629630
302system.ruby.outstanding_req_hist_coalsr::gmean 1.438746
303system.ruby.outstanding_req_hist_coalsr::stdev 0.926040
304system.ruby.outstanding_req_hist_coalsr | 0 0.00% 0.00% | 16 59.26% 59.26% | 7 25.93% 85.19% | 2 7.41% 92.59% | 2 7.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
305system.ruby.outstanding_req_hist_coalsr::total 27
306system.ruby.latency_hist_seqr::bucket_size 64
307system.ruby.latency_hist_seqr::max_bucket 639
308system.ruby.latency_hist_seqr::samples 114203
309system.ruby.latency_hist_seqr::mean 4.784165
310system.ruby.latency_hist_seqr::gmean 2.131364
311system.ruby.latency_hist_seqr::stdev 23.846473
312system.ruby.latency_hist_seqr | 112668 98.66% 98.66% | 0 0.00% 98.66% | 0 0.00% 98.66% | 1506 1.32% 99.97% | 19 0.02% 99.99% | 10 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
313system.ruby.latency_hist_seqr::total 114203
314system.ruby.latency_hist_coalsr::bucket_size 64
315system.ruby.latency_hist_coalsr::max_bucket 639
316system.ruby.latency_hist_coalsr::samples 27
317system.ruby.latency_hist_coalsr::mean 141.296296
318system.ruby.latency_hist_coalsr::gmean 21.202698
319system.ruby.latency_hist_coalsr::stdev 140.217089
320system.ruby.latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 10 37.04% 85.19% | 1 3.70% 88.89% | 3 11.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
321system.ruby.latency_hist_coalsr::total 27
322system.ruby.hit_latency_hist_seqr::bucket_size 64
323system.ruby.hit_latency_hist_seqr::max_bucket 639
324system.ruby.hit_latency_hist_seqr::samples 1535
325system.ruby.hit_latency_hist_seqr::mean 208.448208
326system.ruby.hit_latency_hist_seqr::gmean 208.002202
327system.ruby.hit_latency_hist_seqr::stdev 15.833423
328system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1506 98.11% 98.11% | 19 1.24% 99.35% | 10 0.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
329system.ruby.hit_latency_hist_seqr::total 1535
330system.ruby.miss_latency_hist_seqr::bucket_size 4
331system.ruby.miss_latency_hist_seqr::max_bucket 39
332system.ruby.miss_latency_hist_seqr::samples 112668
333system.ruby.miss_latency_hist_seqr::mean 2.009426
334system.ruby.miss_latency_hist_seqr::gmean 2.002413
335system.ruby.miss_latency_hist_seqr::stdev 0.411800
336system.ruby.miss_latency_hist_seqr | 112609 99.95% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 59 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
337system.ruby.miss_latency_hist_seqr::total 112668
338system.ruby.miss_latency_hist_coalsr::bucket_size 64
339system.ruby.miss_latency_hist_coalsr::max_bucket 639
340system.ruby.miss_latency_hist_coalsr::samples 27
341system.ruby.miss_latency_hist_coalsr::mean 141.296296
342system.ruby.miss_latency_hist_coalsr::gmean 21.202698
343system.ruby.miss_latency_hist_coalsr::stdev 140.217089
344system.ruby.miss_latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 10 37.04% 85.19% | 1 3.70% 88.89% | 3 11.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
345system.ruby.miss_latency_hist_coalsr::total 27
346system.ruby.L1Cache.incomplete_times_seqr 112609
347system.ruby.L2Cache.incomplete_times_seqr 59
348system.cp_cntrl0.L1D0cache.demand_hits 0 # Number of cache demand hits
349system.cp_cntrl0.L1D0cache.demand_misses 506 # Number of cache demand misses
350system.cp_cntrl0.L1D0cache.demand_accesses 506 # Number of cache demand accesses
351system.cp_cntrl0.L1D0cache.num_data_array_reads 16155 # number of data array reads
352system.cp_cntrl0.L1D0cache.num_data_array_writes 11985 # number of data array writes

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364system.cp_cntrl0.L1Icache.num_tag_array_writes 54 # number of tag array writes
365system.cp_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits
366system.cp_cntrl0.L2cache.demand_misses 1535 # Number of cache demand misses
367system.cp_cntrl0.L2cache.demand_accesses 1535 # Number of cache demand accesses
368system.cp_cntrl0.L2cache.num_data_array_reads 120 # number of data array reads
369system.cp_cntrl0.L2cache.num_data_array_writes 11982 # number of data array writes
370system.cp_cntrl0.L2cache.num_tag_array_reads 12059 # number of tag array reads
371system.cp_cntrl0.L2cache.num_tag_array_writes 1649 # number of tag array writes
372system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
373system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
374system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
375system.cpu0.clk_domain.clock 500 # Clock period in ticks
376system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
377system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
378system.cpu0.interrupts.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
379system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
380system.cpu0.workload.num_syscalls 21 # Number of system calls
381system.cpu0.numPwrStateTransitions 2 # Number of power state transitions
382system.cpu0.pwrStateClkGateDist::samples 1 # Distribution of time spent in the clock gated state
383system.cpu0.pwrStateClkGateDist::mean 2615501 # Distribution of time spent in the clock gated state
384system.cpu0.pwrStateClkGateDist::1000-5e+10 1 100.00% 100.00% # Distribution of time spent in the clock gated state
385system.cpu0.pwrStateClkGateDist::min_value 2615501 # Distribution of time spent in the clock gated state
386system.cpu0.pwrStateClkGateDist::max_value 2615501 # Distribution of time spent in the clock gated state
387system.cpu0.pwrStateClkGateDist::total 1 # Distribution of time spent in the clock gated state
388system.cpu0.pwrStateResidencyTicks::ON 660838999 # Cumulative time (in ticks) in various power states
389system.cpu0.pwrStateResidencyTicks::CLK_GATED 2615501 # Cumulative time (in ticks) in various power states
390system.cpu0.numCycles 1326909 # number of cpu cycles simulated
391system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
392system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
393system.cpu0.committedInsts 66963 # Number of instructions committed
394system.cpu0.committedOps 137705 # Number of ops (including micro ops) committed
395system.cpu0.num_int_alu_accesses 136380 # Number of integer alu accesses
396system.cpu0.num_fp_alu_accesses 1279 # Number of float alu accesses
397system.cpu0.num_func_calls 3196 # number of times a function call or return occured
398system.cpu0.num_conditional_control_insts 12151 # number of instructions that are conditional controls
399system.cpu0.num_int_insts 136380 # number of integer instructions
400system.cpu0.num_fp_insts 1279 # number of float instructions
401system.cpu0.num_int_register_reads 257490 # number of times the integer registers were read
402system.cpu0.num_int_register_writes 110039 # number of times the integer registers were written
403system.cpu0.num_fp_register_reads 1981 # number of times the floating registers were read
404system.cpu0.num_fp_register_writes 981 # number of times the floating registers were written
405system.cpu0.num_cc_register_reads 78262 # number of times the CC registers were read
406system.cpu0.num_cc_register_writes 42183 # number of times the CC registers were written
407system.cpu0.num_mem_refs 27198 # number of memory refs
408system.cpu0.num_load_insts 16684 # Number of load instructions
409system.cpu0.num_store_insts 10514 # Number of store instructions
410system.cpu0.num_idle_cycles 5231.003992 # Number of idle cycles
411system.cpu0.num_busy_cycles 1321677.996008 # Number of busy cycles
412system.cpu0.not_idle_fraction 0.996058 # Percentage of non-idle cycles
413system.cpu0.idle_fraction 0.003942 # Percentage of idle cycles
414system.cpu0.Branches 16199 # Number of branches fetched
415system.cpu0.op_class::No_OpClass 615 0.45% 0.45% # Class of executed instruction
416system.cpu0.op_class::IntAlu 108791 79.00% 79.45% # Class of executed instruction
417system.cpu0.op_class::IntMult 13 0.01% 79.46% # Class of executed instruction
418system.cpu0.op_class::IntDiv 138 0.10% 79.56% # Class of executed instruction
419system.cpu0.op_class::FloatAdd 950 0.69% 80.25% # Class of executed instruction
420system.cpu0.op_class::FloatCmp 0 0.00% 80.25% # Class of executed instruction
421system.cpu0.op_class::FloatCvt 0 0.00% 80.25% # Class of executed instruction

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444system.cpu0.op_class::SimdFloatSqrt 0 0.00% 80.25% # Class of executed instruction
445system.cpu0.op_class::MemRead 16684 12.12% 92.36% # Class of executed instruction
446system.cpu0.op_class::MemWrite 10514 7.64% 100.00% # Class of executed instruction
447system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
448system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
449system.cpu0.op_class::total 137705 # Class of executed instruction
450system.cpu1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
451system.cpu1.clk_domain.clock 1000 # Clock period in ticks
452system.cpu1.CUs0.localDataStore.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
453system.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
454system.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
455system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 307 # number of times the wf's instructions are blocked due to RAW dependencies
456system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands
457system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands
458system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands
459system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
460system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands
461system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands
462system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
463system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands

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639system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
640system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
641system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
642system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
643system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
644system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
645system.cpu1.CUs0.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
646system.cpu1.CUs0.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
647system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 279 # number of times the wf's instructions are blocked due to RAW dependencies
648system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
649system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
650system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
651system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
652system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
653system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
654system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
655system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands

--- 175 unchanged lines hidden (view full) ---

831system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
832system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
833system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
834system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
835system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
836system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
837system.cpu1.CUs0.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
838system.cpu1.CUs0.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
839system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 282 # number of times the wf's instructions are blocked due to RAW dependencies
840system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
841system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
842system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
843system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
844system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
845system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
846system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
847system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands

--- 175 unchanged lines hidden (view full) ---

1023system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
1024system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
1025system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
1026system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
1027system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
1028system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
1029system.cpu1.CUs0.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
1030system.cpu1.CUs0.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
1031system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 276 # number of times the wf's instructions are blocked due to RAW dependencies
1032system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
1033system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
1034system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
1035system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
1036system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
1037system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
1038system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
1039system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands

--- 173 unchanged lines hidden (view full) ---

1213system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
1214system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
1215system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
1216system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
1217system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
1218system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
1219system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
1220system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
1221system.cpu1.CUs0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
1222system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it
1223system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it
1224system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it
1225system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it
1226system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it
1227system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it
1228system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it
1229system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it

--- 24 unchanged lines hidden (view full) ---

1254system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
1255system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
1256system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
1257system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
1258system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
1259system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it
1260system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it
1261system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it
1262system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 3261 # number of cycles the CU issues nothing
1263system.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued 99 # number of cycles the CU issued at least one instruction
1264system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued
1265system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued
1266system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued
1267system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued
1268system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued
1269system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued
1270system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 769 # Number of cycles no instruction of specific type issued
1271system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 357 # Number of cycles no instruction of specific type issued
1272system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 375 # Number of cycles no instruction of specific type issued
1273system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 332 # Number of cycles no instruction of specific type issued
1274system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 398 # Number of cycles no instruction of specific type issued
1275system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM 22 # Number of cycles no instruction of specific type issued
1276system.cpu1.CUs0.ExecStage.spc::samples 3360 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1277system.cpu1.CUs0.ExecStage.spc::mean 0.041964 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1278system.cpu1.CUs0.ExecStage.spc::stdev 0.257708 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1279system.cpu1.CUs0.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1280system.cpu1.CUs0.ExecStage.spc::0 3261 97.05% 97.05% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1281system.cpu1.CUs0.ExecStage.spc::1 59 1.76% 98.81% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1282system.cpu1.CUs0.ExecStage.spc::2 38 1.13% 99.94% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1283system.cpu1.CUs0.ExecStage.spc::3 2 0.06% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1284system.cpu1.CUs0.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1285system.cpu1.CUs0.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1286system.cpu1.CUs0.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1287system.cpu1.CUs0.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1288system.cpu1.CUs0.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1289system.cpu1.CUs0.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1290system.cpu1.CUs0.ExecStage.spc::total 3360 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
1291system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 93 # number of CU transitions from active to idle
1292system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 93 # duration of idle periods in cycles
1293system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 34.967742 # duration of idle periods in cycles
1294system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 149.478110 # duration of idle periods in cycles
1295system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles
1296system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 74 79.57% 79.57% # duration of idle periods in cycles
1297system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 7 7.53% 87.10% # duration of idle periods in cycles
1298system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 1 1.08% 88.17% # duration of idle periods in cycles
1299system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 1 1.08% 89.25% # duration of idle periods in cycles
1300system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 2 2.15% 91.40% # duration of idle periods in cycles
1301system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.08% 92.47% # duration of idle periods in cycles
1302system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 92.47% # duration of idle periods in cycles
1303system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 92.47% # duration of idle periods in cycles
1304system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 92.47% # duration of idle periods in cycles
1305system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 92.47% # duration of idle periods in cycles
1306system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 92.47% # duration of idle periods in cycles
1307system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 92.47% # duration of idle periods in cycles
1308system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 92.47% # duration of idle periods in cycles
1309system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 92.47% # duration of idle periods in cycles
1310system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 92.47% # duration of idle periods in cycles
1311system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 92.47% # duration of idle periods in cycles
1312system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 7 7.53% 100.00% # duration of idle periods in cycles
1313system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles
1314system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::max_value 1285 # duration of idle periods in cycles
1315system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 93 # duration of idle periods in cycles
1316system.cpu1.CUs0.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF
1317system.cpu1.CUs0.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF
1318system.cpu1.CUs0.tlb_requests 769 # number of uncoalesced requests
1319system.cpu1.CUs0.tlb_cycles -452453001000 # total number of cycles for all uncoalesced requests
1320system.cpu1.CUs0.avg_translation_latency -588365410.923277 # Avg. translation latency for data translations
1321system.cpu1.CUs0.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB
1322system.cpu1.CUs0.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
1323system.cpu1.CUs0.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
1324system.cpu1.CUs0.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
1325system.cpu1.CUs0.lds_bank_access_cnt 54 # Total number of LDS bank accesses
1326system.cpu1.CUs0.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet
1327system.cpu1.CUs0.lds_bank_conflicts::mean 8 # Number of bank conflicts per LDS memory packet
1328system.cpu1.CUs0.lds_bank_conflicts::stdev 6.196773 # Number of bank conflicts per LDS memory packet

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1388system.cpu1.CUs0.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.)
1389system.cpu1.CUs0.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.)
1390system.cpu1.CUs0.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.)
1391system.cpu1.CUs0.global_mem_instr_cnt 17 # dynamic global memory instructions count
1392system.cpu1.CUs0.local_mem_instr_cnt 6 # dynamic local memory intruction count
1393system.cpu1.CUs0.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity
1394system.cpu1.CUs0.num_instr_executed 141 # number of instructions executed
1395system.cpu1.CUs0.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle
1396system.cpu1.CUs0.inst_exec_rate::mean 86.382979 # Instruction Execution Rate: Number of executed vector instructions per cycle
1397system.cpu1.CUs0.inst_exec_rate::stdev 229.706697 # Instruction Execution Rate: Number of executed vector instructions per cycle
1398system.cpu1.CUs0.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
1399system.cpu1.CUs0.inst_exec_rate::0-1 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
1400system.cpu1.CUs0.inst_exec_rate::2-3 12 8.51% 8.51% # Instruction Execution Rate: Number of executed vector instructions per cycle
1401system.cpu1.CUs0.inst_exec_rate::4-5 52 36.88% 45.39% # Instruction Execution Rate: Number of executed vector instructions per cycle
1402system.cpu1.CUs0.inst_exec_rate::6-7 31 21.99% 67.38% # Instruction Execution Rate: Number of executed vector instructions per cycle
1403system.cpu1.CUs0.inst_exec_rate::8-9 3 2.13% 69.50% # Instruction Execution Rate: Number of executed vector instructions per cycle
1404system.cpu1.CUs0.inst_exec_rate::10 3 2.13% 71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle
1405system.cpu1.CUs0.inst_exec_rate::overflows 40 28.37% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
1406system.cpu1.CUs0.inst_exec_rate::min_value 2 # Instruction Execution Rate: Number of executed vector instructions per cycle
1407system.cpu1.CUs0.inst_exec_rate::max_value 1291 # Instruction Execution Rate: Number of executed vector instructions per cycle
1408system.cpu1.CUs0.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle
1409system.cpu1.CUs0.num_vec_ops_executed 6769 # number of vec ops executed (e.g. VSZ/inst)
1410system.cpu1.CUs0.num_total_cycles 3360 # number of cycles the CU ran for
1411system.cpu1.CUs0.vpc 2.014583 # Vector Operations per cycle (this CU only)
1412system.cpu1.CUs0.ipc 0.041964 # Instructions per cycle (this CU only)
1413system.cpu1.CUs0.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions)
1414system.cpu1.CUs0.warp_execution_dist::mean 48.007092 # number of lanes active per instruction (oval all instructions)
1415system.cpu1.CUs0.warp_execution_dist::stdev 23.719942 # number of lanes active per instruction (oval all instructions)
1416system.cpu1.CUs0.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions)
1417system.cpu1.CUs0.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions)
1418system.cpu1.CUs0.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions)
1419system.cpu1.CUs0.warp_execution_dist::9-12 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions)
1420system.cpu1.CUs0.warp_execution_dist::13-16 36 25.53% 29.08% # number of lanes active per instruction (oval all instructions)

--- 61 unchanged lines hidden (view full) ---

1482system.cpu1.CUs0.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction
1483system.cpu1.CUs0.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction
1484system.cpu1.CUs0.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction
1485system.cpu1.CUs0.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed
1486system.cpu1.CUs0.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD
1487system.cpu1.CUs0.num_CAS_ops 0 # number of compare and swap operations
1488system.cpu1.CUs0.num_failed_CAS_ops 0 # number of compare and swap operations that failed
1489system.cpu1.CUs0.num_completed_wfs 4 # number of completed wavefronts
1490system.cpu1.CUs1.localDataStore.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
1491system.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
1492system.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
1493system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 401 # number of times the wf's instructions are blocked due to RAW dependencies
1494system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands
1495system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands
1496system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands
1497system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
1498system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands
1499system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands
1500system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
1501system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands

--- 175 unchanged lines hidden (view full) ---

1677system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
1678system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
1679system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
1680system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
1681system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
1682system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
1683system.cpu1.CUs1.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
1684system.cpu1.CUs1.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
1685system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 372 # number of times the wf's instructions are blocked due to RAW dependencies
1686system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
1687system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
1688system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
1689system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
1690system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
1691system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
1692system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
1693system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands

--- 175 unchanged lines hidden (view full) ---

1869system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
1870system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
1871system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
1872system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
1873system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
1874system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
1875system.cpu1.CUs1.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
1876system.cpu1.CUs1.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
1877system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 371 # number of times the wf's instructions are blocked due to RAW dependencies
1878system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
1879system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
1880system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
1881system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
1882system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
1883system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
1884system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
1885system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands

--- 175 unchanged lines hidden (view full) ---

2061system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
2062system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
2063system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
2064system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
2065system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
2066system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
2067system.cpu1.CUs1.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
2068system.cpu1.CUs1.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
2069system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 361 # number of times the wf's instructions are blocked due to RAW dependencies
2070system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
2071system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
2072system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
2073system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
2074system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
2075system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
2076system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
2077system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands

--- 173 unchanged lines hidden (view full) ---

2251system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
2252system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
2253system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
2254system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
2255system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
2256system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
2257system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
2258system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
2259system.cpu1.CUs1.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2260system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it
2261system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it
2262system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it
2263system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it
2264system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it
2265system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it
2266system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it
2267system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it

--- 24 unchanged lines hidden (view full) ---

2292system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
2293system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
2294system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
2295system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
2296system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
2297system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it
2298system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it
2299system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it
2300system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 3261 # number of cycles the CU issues nothing
2301system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 99 # number of cycles the CU issued at least one instruction
2302system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued
2303system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued
2304system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued
2305system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued
2306system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued
2307system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued
2308system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 777 # Number of cycles no instruction of specific type issued
2309system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 472 # Number of cycles no instruction of specific type issued
2310system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 444 # Number of cycles no instruction of specific type issued
2311system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 416 # Number of cycles no instruction of specific type issued
2312system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 404 # Number of cycles no instruction of specific type issued
2313system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM 22 # Number of cycles no instruction of specific type issued
2314system.cpu1.CUs1.ExecStage.spc::samples 3360 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2315system.cpu1.CUs1.ExecStage.spc::mean 0.041964 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2316system.cpu1.CUs1.ExecStage.spc::stdev 0.256550 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2317system.cpu1.CUs1.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2318system.cpu1.CUs1.ExecStage.spc::0 3261 97.05% 97.05% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2319system.cpu1.CUs1.ExecStage.spc::1 58 1.73% 98.78% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2320system.cpu1.CUs1.ExecStage.spc::2 40 1.19% 99.97% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2321system.cpu1.CUs1.ExecStage.spc::3 1 0.03% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2322system.cpu1.CUs1.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2323system.cpu1.CUs1.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2324system.cpu1.CUs1.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2325system.cpu1.CUs1.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2326system.cpu1.CUs1.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2327system.cpu1.CUs1.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2328system.cpu1.CUs1.ExecStage.spc::total 3360 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
2329system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 94 # number of CU transitions from active to idle
2330system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 94 # duration of idle periods in cycles
2331system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 33.585106 # duration of idle periods in cycles
2332system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 147.747562 # duration of idle periods in cycles
2333system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles
2334system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 75 79.79% 79.79% # duration of idle periods in cycles
2335system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 8 8.51% 88.30% # duration of idle periods in cycles
2336system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 88.30% # duration of idle periods in cycles
2337system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 1 1.06% 89.36% # duration of idle periods in cycles
2338system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 2 2.13% 91.49% # duration of idle periods in cycles
2339system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 1 1.06% 92.55% # duration of idle periods in cycles
2340system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 92.55% # duration of idle periods in cycles
2341system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 92.55% # duration of idle periods in cycles
2342system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 92.55% # duration of idle periods in cycles
2343system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 92.55% # duration of idle periods in cycles
2344system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 92.55% # duration of idle periods in cycles
2345system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 92.55% # duration of idle periods in cycles
2346system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 92.55% # duration of idle periods in cycles
2347system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 92.55% # duration of idle periods in cycles
2348system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 92.55% # duration of idle periods in cycles
2349system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 92.55% # duration of idle periods in cycles
2350system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 7 7.45% 100.00% # duration of idle periods in cycles
2351system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles
2352system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::max_value 1293 # duration of idle periods in cycles
2353system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 94 # duration of idle periods in cycles
2354system.cpu1.CUs1.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF
2355system.cpu1.CUs1.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF
2356system.cpu1.CUs1.tlb_requests 769 # number of uncoalesced requests
2357system.cpu1.CUs1.tlb_cycles -452459838000 # total number of cycles for all uncoalesced requests
2358system.cpu1.CUs1.avg_translation_latency -588374301.690507 # Avg. translation latency for data translations
2359system.cpu1.CUs1.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB
2360system.cpu1.CUs1.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
2361system.cpu1.CUs1.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
2362system.cpu1.CUs1.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
2363system.cpu1.CUs1.lds_bank_access_cnt 53 # Total number of LDS bank accesses
2364system.cpu1.CUs1.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet
2365system.cpu1.CUs1.lds_bank_conflicts::mean 7.833333 # Number of bank conflicts per LDS memory packet
2366system.cpu1.CUs1.lds_bank_conflicts::stdev 6.080022 # Number of bank conflicts per LDS memory packet

--- 59 unchanged lines hidden (view full) ---

2426system.cpu1.CUs1.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.)
2427system.cpu1.CUs1.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.)
2428system.cpu1.CUs1.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.)
2429system.cpu1.CUs1.global_mem_instr_cnt 17 # dynamic global memory instructions count
2430system.cpu1.CUs1.local_mem_instr_cnt 6 # dynamic local memory intruction count
2431system.cpu1.CUs1.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity
2432system.cpu1.CUs1.num_instr_executed 141 # number of instructions executed
2433system.cpu1.CUs1.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle
2434system.cpu1.CUs1.inst_exec_rate::mean 85.553191 # Instruction Execution Rate: Number of executed vector instructions per cycle
2435system.cpu1.CUs1.inst_exec_rate::stdev 230.829913 # Instruction Execution Rate: Number of executed vector instructions per cycle
2436system.cpu1.CUs1.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
2437system.cpu1.CUs1.inst_exec_rate::0-1 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
2438system.cpu1.CUs1.inst_exec_rate::2-3 13 9.22% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle
2439system.cpu1.CUs1.inst_exec_rate::4-5 52 36.88% 46.10% # Instruction Execution Rate: Number of executed vector instructions per cycle
2440system.cpu1.CUs1.inst_exec_rate::6-7 33 23.40% 69.50% # Instruction Execution Rate: Number of executed vector instructions per cycle
2441system.cpu1.CUs1.inst_exec_rate::8-9 6 4.26% 73.76% # Instruction Execution Rate: Number of executed vector instructions per cycle
2442system.cpu1.CUs1.inst_exec_rate::10 0 0.00% 73.76% # Instruction Execution Rate: Number of executed vector instructions per cycle
2443system.cpu1.CUs1.inst_exec_rate::overflows 37 26.24% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
2444system.cpu1.CUs1.inst_exec_rate::min_value 2 # Instruction Execution Rate: Number of executed vector instructions per cycle
2445system.cpu1.CUs1.inst_exec_rate::max_value 1299 # Instruction Execution Rate: Number of executed vector instructions per cycle
2446system.cpu1.CUs1.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle
2447system.cpu1.CUs1.num_vec_ops_executed 6762 # number of vec ops executed (e.g. VSZ/inst)
2448system.cpu1.CUs1.num_total_cycles 3360 # number of cycles the CU ran for
2449system.cpu1.CUs1.vpc 2.012500 # Vector Operations per cycle (this CU only)
2450system.cpu1.CUs1.ipc 0.041964 # Instructions per cycle (this CU only)
2451system.cpu1.CUs1.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions)
2452system.cpu1.CUs1.warp_execution_dist::mean 47.957447 # number of lanes active per instruction (oval all instructions)
2453system.cpu1.CUs1.warp_execution_dist::stdev 23.818022 # number of lanes active per instruction (oval all instructions)
2454system.cpu1.CUs1.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions)
2455system.cpu1.CUs1.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions)
2456system.cpu1.CUs1.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions)
2457system.cpu1.CUs1.warp_execution_dist::9-12 9 6.38% 9.93% # number of lanes active per instruction (oval all instructions)
2458system.cpu1.CUs1.warp_execution_dist::13-16 27 19.15% 29.08% # number of lanes active per instruction (oval all instructions)

--- 61 unchanged lines hidden (view full) ---

2520system.cpu1.CUs1.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction
2521system.cpu1.CUs1.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction
2522system.cpu1.CUs1.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction
2523system.cpu1.CUs1.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed
2524system.cpu1.CUs1.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD
2525system.cpu1.CUs1.num_CAS_ops 0 # number of compare and swap operations
2526system.cpu1.CUs1.num_failed_CAS_ops 0 # number of compare and swap operations that failed
2527system.cpu1.CUs1.num_completed_wfs 4 # number of completed wavefronts
2528system.cpu1.CUs0.ldsBus.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2529system.cpu1.CUs1.ldsBus.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2530system.cpu2.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2531system.cpu2.num_kernel_launched 1 # number of kernel launched
2532system.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits
2533system.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses
2534system.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses
2535system.dir_cntrl0.L3CacheMemory.num_data_array_writes 1551 # number of data array writes
2536system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1551 # number of tag array reads
2537system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1551 # number of tag array writes
2538system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2539system.dispatcher_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
2540system.dispatcher_coalescer.clk_domain.clock 1000 # Clock period in ticks
2541system.dispatcher_coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2542system.dispatcher_coalescer.uncoalesced_accesses 0 # Number of uncoalesced TLB accesses
2543system.dispatcher_coalescer.coalesced_accesses 0 # Number of coalesced TLB accesses
2544system.dispatcher_coalescer.queuing_cycles 0 # Number of cycles spent in queue
2545system.dispatcher_coalescer.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs
2546system.dispatcher_coalescer.local_latency nan # Avg. latency over all incoming pkts
2547system.dispatcher_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
2548system.dispatcher_tlb.clk_domain.clock 1000 # Clock period in ticks
2549system.dispatcher_tlb.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2550system.dispatcher_tlb.local_TLB_accesses 0 # Number of TLB accesses
2551system.dispatcher_tlb.local_TLB_hits 0 # Number of TLB hits
2552system.dispatcher_tlb.local_TLB_misses 0 # Number of TLB misses
2553system.dispatcher_tlb.local_TLB_miss_rate nan # TLB miss rate
2554system.dispatcher_tlb.global_TLB_accesses 0 # Number of TLB accesses
2555system.dispatcher_tlb.global_TLB_hits 0 # Number of TLB hits
2556system.dispatcher_tlb.global_TLB_misses 0 # Number of TLB misses
2557system.dispatcher_tlb.global_TLB_miss_rate nan # TLB miss rate
2558system.dispatcher_tlb.access_cycles 0 # Cycles spent accessing this TLB level
2559system.dispatcher_tlb.page_table_cycles 0 # Cycles spent accessing the page table
2560system.dispatcher_tlb.unique_pages 0 # Number of unique pages touched
2561system.dispatcher_tlb.local_cycles 0 # Number of cycles spent in queue for all incoming reqs
2562system.dispatcher_tlb.local_latency nan # Avg. latency over incoming coalesced reqs
2563system.dispatcher_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
2564system.l1_coalescer0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
2565system.l1_coalescer0.clk_domain.clock 1000 # Clock period in ticks
2566system.l1_coalescer0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2567system.l1_coalescer0.uncoalesced_accesses 778 # Number of uncoalesced TLB accesses
2568system.l1_coalescer0.coalesced_accesses 0 # Number of coalesced TLB accesses
2569system.l1_coalescer0.queuing_cycles 0 # Number of cycles spent in queue
2570system.l1_coalescer0.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs
2571system.l1_coalescer0.local_latency 0 # Avg. latency over all incoming pkts
2572system.l1_coalescer1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
2573system.l1_coalescer1.clk_domain.clock 1000 # Clock period in ticks
2574system.l1_coalescer1.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2575system.l1_coalescer1.uncoalesced_accesses 769 # Number of uncoalesced TLB accesses
2576system.l1_coalescer1.coalesced_accesses 0 # Number of coalesced TLB accesses
2577system.l1_coalescer1.queuing_cycles 0 # Number of cycles spent in queue
2578system.l1_coalescer1.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs
2579system.l1_coalescer1.local_latency 0 # Avg. latency over all incoming pkts
2580system.l1_tlb0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
2581system.l1_tlb0.clk_domain.clock 1000 # Clock period in ticks
2582system.l1_tlb0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2583system.l1_tlb0.local_TLB_accesses 778 # Number of TLB accesses
2584system.l1_tlb0.local_TLB_hits 774 # Number of TLB hits
2585system.l1_tlb0.local_TLB_misses 4 # Number of TLB misses
2586system.l1_tlb0.local_TLB_miss_rate 0.514139 # TLB miss rate
2587system.l1_tlb0.global_TLB_accesses 778 # Number of TLB accesses
2588system.l1_tlb0.global_TLB_hits 774 # Number of TLB hits
2589system.l1_tlb0.global_TLB_misses 4 # Number of TLB misses
2590system.l1_tlb0.global_TLB_miss_rate 0.514139 # TLB miss rate
2591system.l1_tlb0.access_cycles 0 # Cycles spent accessing this TLB level
2592system.l1_tlb0.page_table_cycles 0 # Cycles spent accessing the page table
2593system.l1_tlb0.unique_pages 4 # Number of unique pages touched
2594system.l1_tlb0.local_cycles 0 # Number of cycles spent in queue for all incoming reqs
2595system.l1_tlb0.local_latency 0 # Avg. latency over incoming coalesced reqs
2596system.l1_tlb0.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
2597system.l1_tlb1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
2598system.l1_tlb1.clk_domain.clock 1000 # Clock period in ticks
2599system.l1_tlb1.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2600system.l1_tlb1.local_TLB_accesses 769 # Number of TLB accesses
2601system.l1_tlb1.local_TLB_hits 766 # Number of TLB hits
2602system.l1_tlb1.local_TLB_misses 3 # Number of TLB misses
2603system.l1_tlb1.local_TLB_miss_rate 0.390117 # TLB miss rate
2604system.l1_tlb1.global_TLB_accesses 769 # Number of TLB accesses
2605system.l1_tlb1.global_TLB_hits 766 # Number of TLB hits
2606system.l1_tlb1.global_TLB_misses 3 # Number of TLB misses
2607system.l1_tlb1.global_TLB_miss_rate 0.390117 # TLB miss rate
2608system.l1_tlb1.access_cycles 0 # Cycles spent accessing this TLB level
2609system.l1_tlb1.page_table_cycles 0 # Cycles spent accessing the page table
2610system.l1_tlb1.unique_pages 3 # Number of unique pages touched
2611system.l1_tlb1.local_cycles 0 # Number of cycles spent in queue for all incoming reqs
2612system.l1_tlb1.local_latency 0 # Avg. latency over incoming coalesced reqs
2613system.l1_tlb1.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
2614system.l2_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
2615system.l2_coalescer.clk_domain.clock 1000 # Clock period in ticks
2616system.l2_coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2617system.l2_coalescer.uncoalesced_accesses 8 # Number of uncoalesced TLB accesses
2618system.l2_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses
2619system.l2_coalescer.queuing_cycles 8000 # Number of cycles spent in queue
2620system.l2_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs
2621system.l2_coalescer.local_latency 125 # Avg. latency over all incoming pkts
2622system.l2_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
2623system.l2_tlb.clk_domain.clock 1000 # Clock period in ticks
2624system.l2_tlb.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2625system.l2_tlb.local_TLB_accesses 8 # Number of TLB accesses
2626system.l2_tlb.local_TLB_hits 3 # Number of TLB hits
2627system.l2_tlb.local_TLB_misses 5 # Number of TLB misses
2628system.l2_tlb.local_TLB_miss_rate 62.500000 # TLB miss rate
2629system.l2_tlb.global_TLB_accesses 15 # Number of TLB accesses
2630system.l2_tlb.global_TLB_hits 3 # Number of TLB hits
2631system.l2_tlb.global_TLB_misses 12 # Number of TLB misses
2632system.l2_tlb.global_TLB_miss_rate 80 # TLB miss rate
2633system.l2_tlb.access_cycles 552008 # Cycles spent accessing this TLB level
2634system.l2_tlb.page_table_cycles 0 # Cycles spent accessing the page table
2635system.l2_tlb.unique_pages 5 # Number of unique pages touched
2636system.l2_tlb.local_cycles 69001 # Number of cycles spent in queue for all incoming reqs
2637system.l2_tlb.local_latency 8625.125000 # Avg. latency over incoming coalesced reqs
2638system.l2_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
2639system.l3_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
2640system.l3_coalescer.clk_domain.clock 1000 # Clock period in ticks
2641system.l3_coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2642system.l3_coalescer.uncoalesced_accesses 5 # Number of uncoalesced TLB accesses
2643system.l3_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses
2644system.l3_coalescer.queuing_cycles 8000 # Number of cycles spent in queue
2645system.l3_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs
2646system.l3_coalescer.local_latency 200 # Avg. latency over all incoming pkts
2647system.l3_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
2648system.l3_tlb.clk_domain.clock 1000 # Clock period in ticks
2649system.l3_tlb.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2650system.l3_tlb.local_TLB_accesses 5 # Number of TLB accesses
2651system.l3_tlb.local_TLB_hits 0 # Number of TLB hits
2652system.l3_tlb.local_TLB_misses 5 # Number of TLB misses
2653system.l3_tlb.local_TLB_miss_rate 100 # TLB miss rate
2654system.l3_tlb.global_TLB_accesses 12 # Number of TLB accesses
2655system.l3_tlb.global_TLB_hits 0 # Number of TLB hits
2656system.l3_tlb.global_TLB_misses 12 # Number of TLB misses
2657system.l3_tlb.global_TLB_miss_rate 100 # TLB miss rate
2658system.l3_tlb.access_cycles 1200000 # Cycles spent accessing this TLB level
2659system.l3_tlb.page_table_cycles 6000000 # Cycles spent accessing the page table
2660system.l3_tlb.unique_pages 5 # Number of unique pages touched
2661system.l3_tlb.local_cycles 150000 # Number of cycles spent in queue for all incoming reqs
2662system.l3_tlb.local_latency 30000 # Avg. latency over incoming coalesced reqs
2663system.l3_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
2664system.piobus.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2665system.piobus.trans_dist::WriteReq 94 # Transaction distribution
2666system.piobus.trans_dist::WriteResp 94 # Transaction distribution
2667system.piobus.pkt_count_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 188 # Packet count per connected master and slave (bytes)
2668system.piobus.pkt_count::total 188 # Packet count per connected master and slave (bytes)
2669system.piobus.pkt_size_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 748 # Cumulative packet size per connected master and slave (bytes)
2670system.piobus.pkt_size::total 748 # Cumulative packet size per connected master and slave (bytes)
2671system.piobus.reqLayer0.occupancy 188000 # Layer occupancy (ticks)
2672system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2673system.piobus.respLayer0.occupancy 94000 # Layer occupancy (ticks)
2674system.piobus.respLayer0.utilization 0.0 # Layer utilization (%)
2675system.ruby.network.ext_links0.int_node.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2676system.ruby.network.ext_links0.int_node.percent_links_utilized 0.007952
2677system.ruby.network.ext_links0.int_node.msg_count.Control::0 1551
2678system.ruby.network.ext_links0.int_node.msg_count.Request_Control::0 1551
2679system.ruby.network.ext_links0.int_node.msg_count.Response_Data::2 1563
2680system.ruby.network.ext_links0.int_node.msg_count.Response_Control::2 1539
2681system.ruby.network.ext_links0.int_node.msg_count.Unblock_Control::4 1551
2682system.ruby.network.ext_links0.int_node.msg_bytes.Control::0 12408
2683system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0 12408
2684system.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2 112536
2685system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2 12312
2686system.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4 12408
2687system.ruby.network.ext_links1.int_node.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2688system.ruby.network.ext_links1.int_node.percent_links_utilized 0.009970
2689system.ruby.network.ext_links1.int_node.msg_count.Control::0 16
2690system.ruby.network.ext_links1.int_node.msg_count.Request_Control::0 1535
2691system.ruby.network.ext_links1.int_node.msg_count.Response_Data::2 1537
2692system.ruby.network.ext_links1.int_node.msg_count.Response_Control::2 14
2693system.ruby.network.ext_links1.int_node.msg_count.Unblock_Control::4 1535
2694system.ruby.network.ext_links1.int_node.msg_bytes.Control::0 128
2695system.ruby.network.ext_links1.int_node.msg_bytes.Request_Control::0 12280
2696system.ruby.network.ext_links1.int_node.msg_bytes.Response_Data::2 110664
2697system.ruby.network.ext_links1.int_node.msg_bytes.Response_Control::2 112
2698system.ruby.network.ext_links1.int_node.msg_bytes.Unblock_Control::4 12280
2699system.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits
2700system.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses
2701system.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses
2702system.tcp_cntrl0.L1cache.num_data_array_reads 9 # number of data array reads
2703system.tcp_cntrl0.L1cache.num_data_array_writes 11 # number of data array writes
2704system.tcp_cntrl0.L1cache.num_tag_array_reads 26 # number of tag array reads
2705system.tcp_cntrl0.L1cache.num_tag_array_writes 18 # number of tag array writes
2706system.tcp_cntrl0.L1cache.num_data_array_stalls 2 # number of stalls caused by data array
2707system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2708system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 2 # loads that hit in the TCP
2709system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers
2710system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
2711system.tcp_cntrl0.coalescer.gpu_ld_misses 2 # loads that miss in the GPU
2712system.tcp_cntrl0.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP
2713system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 1 # TCP to TCP store transfers
2714system.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC
2715system.tcp_cntrl0.coalescer.gpu_st_misses 4 # stores that miss in the GPU
2716system.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP
2717system.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers
2718system.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC
2719system.tcp_cntrl0.coalescer.cp_ld_misses 0 # loads that miss in the GPU
2720system.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP
2721system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
2722system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
2723system.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU
2724system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2725system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2726system.ruby.network.ext_links2.int_node.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2727system.ruby.network.ext_links2.int_node.percent_links_utilized 0.000721
2728system.ruby.network.ext_links2.int_node.msg_count.Control::0 1535
2729system.ruby.network.ext_links2.int_node.msg_count.Control::1 14
2730system.ruby.network.ext_links2.int_node.msg_count.Request_Control::0 16
2731system.ruby.network.ext_links2.int_node.msg_count.Request_Control::1 19
2732system.ruby.network.ext_links2.int_node.msg_count.Response_Data::2 26
2733system.ruby.network.ext_links2.int_node.msg_count.Response_Data::3 33
2734system.ruby.network.ext_links2.int_node.msg_count.Response_Control::2 1525
2735system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::4 16

--- 11 unchanged lines hidden (view full) ---

2747system.tcp_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses
2748system.tcp_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses
2749system.tcp_cntrl1.L1cache.num_data_array_reads 7 # number of data array reads
2750system.tcp_cntrl1.L1cache.num_data_array_writes 11 # number of data array writes
2751system.tcp_cntrl1.L1cache.num_tag_array_reads 25 # number of tag array reads
2752system.tcp_cntrl1.L1cache.num_tag_array_writes 18 # number of tag array writes
2753system.tcp_cntrl1.L1cache.num_tag_array_stalls 2 # number of stalls caused by tag array
2754system.tcp_cntrl1.L1cache.num_data_array_stalls 2 # number of stalls caused by data array
2755system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2756system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 3 # loads that hit in the TCP
2757system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 2 # TCP to TCP load transfers
2758system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
2759system.tcp_cntrl1.coalescer.gpu_ld_misses 0 # loads that miss in the GPU
2760system.tcp_cntrl1.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP
2761system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers
2762system.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC
2763system.tcp_cntrl1.coalescer.gpu_st_misses 5 # stores that miss in the GPU
2764system.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP
2765system.tcp_cntrl1.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers
2766system.tcp_cntrl1.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC
2767system.tcp_cntrl1.coalescer.cp_ld_misses 0 # loads that miss in the GPU
2768system.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP
2769system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
2770system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
2771system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU
2772system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2773system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2774system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits
2775system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses
2776system.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses
2777system.sqc_cntrl0.L1cache.num_data_array_reads 86 # number of data array reads
2778system.sqc_cntrl0.L1cache.num_data_array_writes 5 # number of data array writes
2779system.sqc_cntrl0.L1cache.num_tag_array_reads 86 # number of tag array reads
2780system.sqc_cntrl0.L1cache.num_tag_array_writes 5 # number of tag array writes
2781system.sqc_cntrl0.L1cache.num_data_array_stalls 47 # number of stalls caused by data array
2782system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2783system.sqc_cntrl0.sequencer.load_waiting_on_load 120 # Number of times a load aliased with a pending load
2784system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2785system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits
2786system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses
2787system.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses
2788system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2789system.tccdir_cntrl0.directory.demand_hits 0 # Number of cache demand hits
2790system.tccdir_cntrl0.directory.demand_misses 0 # Number of cache demand misses
2791system.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses
2792system.tccdir_cntrl0.directory.num_tag_array_reads 1554 # number of tag array reads
2793system.tccdir_cntrl0.directory.num_tag_array_writes 27 # number of tag array writes
2794system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2795system.ruby.network.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2796system.ruby.network.msg_count.Control 3116
2797system.ruby.network.msg_count.Request_Control 3121
2798system.ruby.network.msg_count.Response_Data 3159
2799system.ruby.network.msg_count.Response_Control 3078
2800system.ruby.network.msg_count.Unblock_Control 3121
2801system.ruby.network.msg_byte.Control 24928
2802system.ruby.network.msg_byte.Request_Control 24968
2803system.ruby.network.msg_byte.Response_Data 227448
2804system.ruby.network.msg_byte.Response_Control 24624
2805system.ruby.network.msg_byte.Unblock_Control 24968
2806system.sqc_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
2807system.sqc_coalescer.clk_domain.clock 1000 # Clock period in ticks
2808system.sqc_coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2809system.sqc_coalescer.uncoalesced_accesses 86 # Number of uncoalesced TLB accesses
2810system.sqc_coalescer.coalesced_accesses 60 # Number of coalesced TLB accesses
2811system.sqc_coalescer.queuing_cycles 108000 # Number of cycles spent in queue
2812system.sqc_coalescer.local_queuing_cycles 108000 # Number of cycles spent in queue for all incoming reqs
2813system.sqc_coalescer.local_latency 1255.813953 # Avg. latency over all incoming pkts
2814system.sqc_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
2815system.sqc_tlb.clk_domain.clock 1000 # Clock period in ticks
2816system.sqc_tlb.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2817system.sqc_tlb.local_TLB_accesses 60 # Number of TLB accesses
2818system.sqc_tlb.local_TLB_hits 59 # Number of TLB hits
2819system.sqc_tlb.local_TLB_misses 1 # Number of TLB misses
2820system.sqc_tlb.local_TLB_miss_rate 1.666667 # TLB miss rate
2821system.sqc_tlb.global_TLB_accesses 86 # Number of TLB accesses
2822system.sqc_tlb.global_TLB_hits 78 # Number of TLB hits
2823system.sqc_tlb.global_TLB_misses 8 # Number of TLB misses
2824system.sqc_tlb.global_TLB_miss_rate 9.302326 # TLB miss rate
2825system.sqc_tlb.access_cycles 86008 # Cycles spent accessing this TLB level
2826system.sqc_tlb.page_table_cycles 0 # Cycles spent accessing the page table
2827system.sqc_tlb.unique_pages 1 # Number of unique pages touched
2828system.sqc_tlb.local_cycles 60001 # Number of cycles spent in queue for all incoming reqs
2829system.sqc_tlb.local_latency 1000.016667 # Avg. latency over incoming coalesced reqs
2830system.sqc_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
2831system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
2832system.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.005592
2833system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1551
2834system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Data::2 12
2835system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2 1539
2836system.ruby.network.ext_links0.int_node.throttle0.msg_count.Unblock_Control::4 1551
2837system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0 12408
2838system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Data::2 864
2839system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Control::2 12312
2840system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Unblock_Control::4 12408
2841system.ruby.network.ext_links0.int_node.throttle1.link_utilization 0.016287
2842system.ruby.network.ext_links0.int_node.throttle1.msg_count.Control::0 16
2843system.ruby.network.ext_links0.int_node.throttle1.msg_count.Response_Data::2 1535
2844system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Control::0 128
2845system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Response_Data::2 110520
2846system.ruby.network.ext_links0.int_node.throttle2.link_utilization 0.001977
2847system.ruby.network.ext_links0.int_node.throttle2.msg_count.Control::0 1535
2848system.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Data::2 16
2849system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Control::0 12280
2850system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Data::2 1152
2851system.ruby.network.ext_links1.int_node.throttle0.link_utilization 0.016287
2852system.ruby.network.ext_links1.int_node.throttle0.msg_count.Control::0 16
2853system.ruby.network.ext_links1.int_node.throttle0.msg_count.Response_Data::2 1535
2854system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Control::0 128
2855system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Response_Data::2 110520
2856system.ruby.network.ext_links1.int_node.throttle1.link_utilization 0.003653
2857system.ruby.network.ext_links1.int_node.throttle1.msg_count.Request_Control::0 1535
2858system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Data::2 2
2859system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Control::2 14
2860system.ruby.network.ext_links1.int_node.throttle1.msg_count.Unblock_Control::4 1535
2861system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Request_Control::0 12280
2862system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Data::2 144
2863system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Control::2 112
2864system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Unblock_Control::4 12280
2865system.ruby.network.ext_links2.int_node.throttle0.link_utilization 0.000084
2866system.ruby.network.ext_links2.int_node.throttle0.msg_count.Control::1 8
2867system.ruby.network.ext_links2.int_node.throttle0.msg_count.Response_Data::3 7
2868system.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Control::1 64
2869system.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Response_Data::3 504
2870system.ruby.network.ext_links2.int_node.throttle1.link_utilization 0.000081
2871system.ruby.network.ext_links2.int_node.throttle1.msg_count.Control::1 6
2872system.ruby.network.ext_links2.int_node.throttle1.msg_count.Response_Data::3 7
2873system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Control::1 48
2874system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Response_Data::3 504
2875system.ruby.network.ext_links2.int_node.throttle2.link_utilization 0
2876system.ruby.network.ext_links2.int_node.throttle3.link_utilization 0.002170
2877system.ruby.network.ext_links2.int_node.throttle3.msg_count.Control::0 1535
2878system.ruby.network.ext_links2.int_node.throttle3.msg_count.Request_Control::1 19
2879system.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::2 16
2880system.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::3 14
2881system.ruby.network.ext_links2.int_node.throttle3.msg_count.Unblock_Control::5 19
2882system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Control::0 12280
2883system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Request_Control::1 152
2884system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Response_Data::2 1152
2885system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Response_Data::3 1008
2886system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Unblock_Control::5 152
2887system.ruby.network.ext_links2.int_node.throttle4.link_utilization 0.000053
2888system.ruby.network.ext_links2.int_node.throttle4.msg_count.Response_Data::3 5
2889system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Response_Data::3 360
2890system.ruby.network.ext_links2.int_node.throttle5.link_utilization 0.001939
2891system.ruby.network.ext_links2.int_node.throttle5.msg_count.Request_Control::0 16
2892system.ruby.network.ext_links2.int_node.throttle5.msg_count.Response_Data::2 10
2893system.ruby.network.ext_links2.int_node.throttle5.msg_count.Response_Control::2 1525
2894system.ruby.network.ext_links2.int_node.throttle5.msg_count.Unblock_Control::4 16
2895system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Request_Control::0 128
2896system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Response_Data::2 720
2897system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Response_Control::2 12200
2898system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Unblock_Control::4 128

--- 47 unchanged lines hidden (view full) ---

2946system.ruby.Directory_Controller.RdBlk 177 0.00% 0.00%
2947system.ruby.Directory_Controller.CPUPrbResp 1551 0.00% 0.00%
2948system.ruby.Directory_Controller.ProbeAcksComplete 1551 0.00% 0.00%
2949system.ruby.Directory_Controller.MemData 1551 0.00% 0.00%
2950system.ruby.Directory_Controller.CoreUnblock 1551 0.00% 0.00%
2951system.ruby.Directory_Controller.U.RdBlkS 1039 0.00% 0.00%
2952system.ruby.Directory_Controller.U.RdBlkM 335 0.00% 0.00%
2953system.ruby.Directory_Controller.U.RdBlk 177 0.00% 0.00%
2954system.ruby.Directory_Controller.BS_M.MemData 30 0.00% 0.00%
2955system.ruby.Directory_Controller.BM_M.MemData 11 0.00% 0.00%
2956system.ruby.Directory_Controller.B_M.MemData 1 0.00% 0.00%
2957system.ruby.Directory_Controller.BS_PM.CPUPrbResp 30 0.00% 0.00%
2958system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 30 0.00% 0.00%
2959system.ruby.Directory_Controller.BS_PM.MemData 1009 0.00% 0.00%
2960system.ruby.Directory_Controller.BM_PM.CPUPrbResp 11 0.00% 0.00%
2961system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 11 0.00% 0.00%
2962system.ruby.Directory_Controller.BM_PM.MemData 324 0.00% 0.00%
2963system.ruby.Directory_Controller.B_PM.CPUPrbResp 1 0.00% 0.00%
2964system.ruby.Directory_Controller.B_PM.ProbeAcksComplete 1 0.00% 0.00%
2965system.ruby.Directory_Controller.B_PM.MemData 176 0.00% 0.00%
2966system.ruby.Directory_Controller.BS_Pm.CPUPrbResp 1009 0.00% 0.00%
2967system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 1009 0.00% 0.00%
2968system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 324 0.00% 0.00%
2969system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 324 0.00% 0.00%
2970system.ruby.Directory_Controller.B_Pm.CPUPrbResp 176 0.00% 0.00%
2971system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 176 0.00% 0.00%
2972system.ruby.Directory_Controller.B.CoreUnblock 1551 0.00% 0.00%
2973system.ruby.LD.latency_hist_seqr::bucket_size 32
2974system.ruby.LD.latency_hist_seqr::max_bucket 319
2975system.ruby.LD.latency_hist_seqr::samples 16335
2976system.ruby.LD.latency_hist_seqr::mean 4.217447
2977system.ruby.LD.latency_hist_seqr::gmean 2.103537
2978system.ruby.LD.latency_hist_seqr::stdev 21.286370
2979system.ruby.LD.latency_hist_seqr | 16160 98.93% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 166 1.02% 99.94% | 9 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
2980system.ruby.LD.latency_hist_seqr::total 16335
2981system.ruby.LD.latency_hist_coalsr::bucket_size 64
2982system.ruby.LD.latency_hist_coalsr::max_bucket 639
2983system.ruby.LD.latency_hist_coalsr::samples 9
2984system.ruby.LD.latency_hist_coalsr::mean 133
2985system.ruby.LD.latency_hist_coalsr::gmean 19.809210
2986system.ruby.LD.latency_hist_coalsr::stdev 158.221364
2987system.ruby.LD.latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 2 22.22% 77.78% | 0 0.00% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
2988system.ruby.LD.latency_hist_coalsr::total 9
2989system.ruby.LD.hit_latency_hist_seqr::bucket_size 32
2990system.ruby.LD.hit_latency_hist_seqr::max_bucket 319
2991system.ruby.LD.hit_latency_hist_seqr::samples 175
2992system.ruby.LD.hit_latency_hist_seqr::mean 208.468571
2993system.ruby.LD.hit_latency_hist_seqr::gmean 208.231054
2994system.ruby.LD.hit_latency_hist_seqr::stdev 10.632194
2995system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 166 94.86% 94.86% | 9 5.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
2996system.ruby.LD.hit_latency_hist_seqr::total 175
2997system.ruby.LD.miss_latency_hist_seqr::bucket_size 4
2998system.ruby.LD.miss_latency_hist_seqr::max_bucket 39
2999system.ruby.LD.miss_latency_hist_seqr::samples 16160
3000system.ruby.LD.miss_latency_hist_seqr::mean 2.005569
3001system.ruby.LD.miss_latency_hist_seqr::gmean 2.001425
3002system.ruby.LD.miss_latency_hist_seqr::stdev 0.316580
3003system.ruby.LD.miss_latency_hist_seqr | 16155 99.97% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 5 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3004system.ruby.LD.miss_latency_hist_seqr::total 16160
3005system.ruby.LD.miss_latency_hist_coalsr::bucket_size 64
3006system.ruby.LD.miss_latency_hist_coalsr::max_bucket 639
3007system.ruby.LD.miss_latency_hist_coalsr::samples 9
3008system.ruby.LD.miss_latency_hist_coalsr::mean 133
3009system.ruby.LD.miss_latency_hist_coalsr::gmean 19.809210
3010system.ruby.LD.miss_latency_hist_coalsr::stdev 158.221364
3011system.ruby.LD.miss_latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 2 22.22% 77.78% | 0 0.00% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3012system.ruby.LD.miss_latency_hist_coalsr::total 9
3013system.ruby.ST.latency_hist_seqr::bucket_size 64
3014system.ruby.ST.latency_hist_seqr::max_bucket 639
3015system.ruby.ST.latency_hist_seqr::samples 10412
3016system.ruby.ST.latency_hist_seqr::mean 8.385709
3017system.ruby.ST.latency_hist_seqr::gmean 2.308923
3018system.ruby.ST.latency_hist_seqr::stdev 35.862445
3019system.ruby.ST.latency_hist_seqr | 10090 96.91% 96.91% | 0 0.00% 96.91% | 0 0.00% 96.91% | 316 3.03% 99.94% | 3 0.03% 99.97% | 3 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3020system.ruby.ST.latency_hist_seqr::total 10412
3021system.ruby.ST.latency_hist_coalsr::bucket_size 32
3022system.ruby.ST.latency_hist_coalsr::max_bucket 319
3023system.ruby.ST.latency_hist_coalsr::samples 16
3024system.ruby.ST.latency_hist_coalsr::mean 124.937500
3025system.ruby.ST.latency_hist_coalsr::gmean 15.775436
3026system.ruby.ST.latency_hist_coalsr::stdev 128.013264
3027system.ruby.ST.latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 8 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3028system.ruby.ST.latency_hist_coalsr::total 16
3029system.ruby.ST.hit_latency_hist_seqr::bucket_size 64
3030system.ruby.ST.hit_latency_hist_seqr::max_bucket 639
3031system.ruby.ST.hit_latency_hist_seqr::samples 322
3032system.ruby.ST.hit_latency_hist_seqr::mean 208.484472
3033system.ruby.ST.hit_latency_hist_seqr::gmean 208.014366
3034system.ruby.ST.hit_latency_hist_seqr::stdev 16.327683
3035system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 316 98.14% 98.14% | 3 0.93% 99.07% | 3 0.93% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3036system.ruby.ST.hit_latency_hist_seqr::total 322
3037system.ruby.ST.miss_latency_hist_seqr::bucket_size 1
3038system.ruby.ST.miss_latency_hist_seqr::max_bucket 9
3039system.ruby.ST.miss_latency_hist_seqr::samples 10090
3040system.ruby.ST.miss_latency_hist_seqr::mean 2
3041system.ruby.ST.miss_latency_hist_seqr::gmean 2.000000
3042system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10090 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3043system.ruby.ST.miss_latency_hist_seqr::total 10090
3044system.ruby.ST.miss_latency_hist_coalsr::bucket_size 32
3045system.ruby.ST.miss_latency_hist_coalsr::max_bucket 319
3046system.ruby.ST.miss_latency_hist_coalsr::samples 16
3047system.ruby.ST.miss_latency_hist_coalsr::mean 124.937500
3048system.ruby.ST.miss_latency_hist_coalsr::gmean 15.775436
3049system.ruby.ST.miss_latency_hist_coalsr::stdev 128.013264
3050system.ruby.ST.miss_latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 8 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3051system.ruby.ST.miss_latency_hist_coalsr::total 16
3052system.ruby.ATOMIC.latency_hist_coalsr::bucket_size 64
3053system.ruby.ATOMIC.latency_hist_coalsr::max_bucket 639
3054system.ruby.ATOMIC.latency_hist_coalsr::samples 2
3055system.ruby.ATOMIC.latency_hist_coalsr::mean 309.500000
3056system.ruby.ATOMIC.latency_hist_coalsr::gmean 306.568100
3057system.ruby.ATOMIC.latency_hist_coalsr::stdev 60.104076
3058system.ruby.ATOMIC.latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3059system.ruby.ATOMIC.latency_hist_coalsr::total 2
3060system.ruby.ATOMIC.miss_latency_hist_coalsr::bucket_size 64
3061system.ruby.ATOMIC.miss_latency_hist_coalsr::max_bucket 639
3062system.ruby.ATOMIC.miss_latency_hist_coalsr::samples 2
3063system.ruby.ATOMIC.miss_latency_hist_coalsr::mean 309.500000
3064system.ruby.ATOMIC.miss_latency_hist_coalsr::gmean 306.568100
3065system.ruby.ATOMIC.miss_latency_hist_coalsr::stdev 60.104076
3066system.ruby.ATOMIC.miss_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3067system.ruby.ATOMIC.miss_latency_hist_coalsr::total 2
3068system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
3069system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
3070system.ruby.IFETCH.latency_hist_seqr::samples 87095
3071system.ruby.IFETCH.latency_hist_seqr::mean 4.462070
3072system.ruby.IFETCH.latency_hist_seqr::gmean 2.116390
3073system.ruby.IFETCH.latency_hist_seqr::stdev 22.434900
3074system.ruby.IFETCH.latency_hist_seqr | 86061 98.81% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1011 1.16% 99.97% | 16 0.02% 99.99% | 7 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3075system.ruby.IFETCH.latency_hist_seqr::total 87095
3076system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 64
3077system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 639
3078system.ruby.IFETCH.hit_latency_hist_seqr::samples 1034
3079system.ruby.IFETCH.hit_latency_hist_seqr::mean 208.442940
3080system.ruby.IFETCH.hit_latency_hist_seqr::gmean 207.967489
3081system.ruby.IFETCH.hit_latency_hist_seqr::stdev 16.443135
3082system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1011 97.78% 97.78% | 16 1.55% 99.32% | 7 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3083system.ruby.IFETCH.hit_latency_hist_seqr::total 1034
3084system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 4
3085system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 39
3086system.ruby.IFETCH.miss_latency_hist_seqr::samples 86061
3087system.ruby.IFETCH.miss_latency_hist_seqr::mean 2.011294
3088system.ruby.IFETCH.miss_latency_hist_seqr::gmean 2.002892
3089system.ruby.IFETCH.miss_latency_hist_seqr::stdev 0.450747
3090system.ruby.IFETCH.miss_latency_hist_seqr | 86007 99.94% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 54 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%

--- 60 unchanged lines hidden (view full) ---

3151system.ruby.L2Cache.miss_mach_latency_hist_seqr::samples 59
3152system.ruby.L2Cache.miss_mach_latency_hist_seqr::mean 20
3153system.ruby.L2Cache.miss_mach_latency_hist_seqr::gmean 20.000000
3154system.ruby.L2Cache.miss_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 59 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3155system.ruby.L2Cache.miss_mach_latency_hist_seqr::total 59
3156system.ruby.Directory.hit_mach_latency_hist_seqr::bucket_size 64
3157system.ruby.Directory.hit_mach_latency_hist_seqr::max_bucket 639
3158system.ruby.Directory.hit_mach_latency_hist_seqr::samples 1535
3159system.ruby.Directory.hit_mach_latency_hist_seqr::mean 208.448208
3160system.ruby.Directory.hit_mach_latency_hist_seqr::gmean 208.002202
3161system.ruby.Directory.hit_mach_latency_hist_seqr::stdev 15.833423
3162system.ruby.Directory.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1506 98.11% 98.11% | 19 1.24% 99.35% | 10 0.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3163system.ruby.Directory.hit_mach_latency_hist_seqr::total 1535
3164system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::bucket_size 64
3165system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::max_bucket 639
3166system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::samples 3
3167system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean 345.333333
3168system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 345.301362
3169system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 5.773503
3170system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3171system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::total 3
3172system.ruby.TCP.miss_mach_latency_hist_coalsr::bucket_size 1
3173system.ruby.TCP.miss_mach_latency_hist_coalsr::max_bucket 9
3174system.ruby.TCP.miss_mach_latency_hist_coalsr::samples 13
3175system.ruby.TCP.miss_mach_latency_hist_coalsr::mean 1.538462
3176system.ruby.TCP.miss_mach_latency_hist_coalsr::gmean 1.377009
3177system.ruby.TCP.miss_mach_latency_hist_coalsr::stdev 0.877058
3178system.ruby.TCP.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 8 61.54% 61.54% | 4 30.77% 92.31% | 0 0.00% 92.31% | 1 7.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3179system.ruby.TCP.miss_mach_latency_hist_coalsr::total 13
3180system.ruby.TCCdir.miss_mach_latency_hist_coalsr::bucket_size 32
3181system.ruby.TCCdir.miss_mach_latency_hist_coalsr::max_bucket 319
3182system.ruby.TCCdir.miss_mach_latency_hist_coalsr::samples 11
3183system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 250.818182
3184system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 250.757089
3185system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 5.896070
3186system.ruby.TCCdir.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 90.91% 90.91% | 1 9.09% 100.00% | 0 0.00% 100.00%
3187system.ruby.TCCdir.miss_mach_latency_hist_coalsr::total 11
3188system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1
3189system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9
3190system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::samples 16155
3191system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::mean 2
3192system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000
3193system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 16155 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3194system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::total 16155
3195system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::bucket_size 4
3196system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::max_bucket 39
3197system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::samples 5
3198system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::mean 20
3199system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::gmean 20.000000
3200system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3201system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::total 5
3202system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::bucket_size 32
3203system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::max_bucket 319
3204system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::samples 175
3205system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::mean 208.468571
3206system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::gmean 208.231054
3207system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::stdev 10.632194
3208system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 166 94.86% 94.86% | 9 5.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3209system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::total 175
3210system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64
3211system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639
3212system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 2
3213system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 342
3214system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 342.000000
3215system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3216system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 2
3217system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1
3218system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9
3219system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::samples 5
3220system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::mean 2.400000
3221system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::gmean 2.297397
3222system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::stdev 0.894427
3223system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 80.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3224system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::total 5
3225system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32
3226system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319
3227system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::samples 2
3228system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean 250.500000
3229system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 250.487525
3230system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 3.535534
3231system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3232system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::total 2
3233system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1
3234system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9
3235system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::samples 10090
3236system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::mean 2
3237system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000
3238system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10090 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3239system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::total 10090
3240system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::bucket_size 64
3241system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::max_bucket 639
3242system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::samples 322
3243system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::mean 208.484472
3244system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::gmean 208.014366
3245system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::stdev 16.327683
3246system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 316 98.14% 98.14% | 3 0.93% 99.07% | 3 0.93% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3247system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::total 322
3248system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1
3249system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9
3250system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::samples 8
3251system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::mean 1
3252system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::gmean 1
3253system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 8 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3254system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::total 8
3255system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32
3256system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319
3257system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::samples 8
3258system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 248.875000
3259system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 248.864382
3260system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 2.474874
3261system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 8 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3262system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::total 8
3263system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64
3264system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639
3265system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 1
3266system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 352
3267system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 352.000000
3268system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev nan
3269system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3270system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 1
3271system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32
3272system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319
3273system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::samples 1
3274system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::mean 267
3275system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 267.000000
3276system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::stdev nan
3277system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00%
3278system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::total 1
3279system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1
3280system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9
3281system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::samples 86007
3282system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::mean 2
3283system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000

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3288system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::samples 54
3289system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::mean 20
3290system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::gmean 20.000000
3291system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 54 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3292system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::total 54
3293system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::bucket_size 64
3294system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::max_bucket 639
3295system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::samples 1034
3296system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::mean 208.442940
3297system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::gmean 207.967489
3298system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::stdev 16.443135
3299system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1011 97.78% 97.78% | 16 1.55% 99.32% | 7 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3300system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::total 1034
3301system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1
3302system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9
3303system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::samples 337
3304system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::mean 2
3305system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000
3306system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3307system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::total 337

--- 18 unchanged lines hidden (view full) ---

3326system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2
3327system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
3328system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::total 10
3329system.ruby.SQC_Controller.Fetch 86 0.00% 0.00%
3330system.ruby.SQC_Controller.TCC_AckS 5 0.00% 0.00%
3331system.ruby.SQC_Controller.I.Fetch 5 0.00% 0.00%
3332system.ruby.SQC_Controller.S.Fetch 81 0.00% 0.00%
3333system.ruby.SQC_Controller.I_S.TCC_AckS 5 0.00% 0.00%
3334system.ruby.TCCdir_Controller.RdBlk 54 0.00% 0.00%
3335system.ruby.TCCdir_Controller.RdBlkM 36 0.00% 0.00%
3336system.ruby.TCCdir_Controller.RdBlkS 5 0.00% 0.00%
3337system.ruby.TCCdir_Controller.CPUPrbResp 14 0.00% 0.00%
3338system.ruby.TCCdir_Controller.ProbeAcksComplete 13 0.00% 0.00%
3339system.ruby.TCCdir_Controller.CoreUnblock 17 0.00% 0.00%
3340system.ruby.TCCdir_Controller.LastCoreUnblock 2 0.00% 0.00%
3341system.ruby.TCCdir_Controller.NB_AckS 7 0.00% 0.00%
3342system.ruby.TCCdir_Controller.NB_AckM 9 0.00% 0.00%
3343system.ruby.TCCdir_Controller.PrbInvData 326 0.00% 0.00%

--- 8 unchanged lines hidden (view full) ---

3352system.ruby.TCCdir_Controller.M.RdBlkM 1 0.00% 0.00%
3353system.ruby.TCCdir_Controller.M.PrbShrData 9 0.00% 0.00%
3354system.ruby.TCCdir_Controller.CP_I.CPUPrbResp 2 0.00% 0.00%
3355system.ruby.TCCdir_Controller.CP_I.ProbeAcksComplete 1 0.00% 0.00%
3356system.ruby.TCCdir_Controller.CP_O.CPUPrbResp 9 0.00% 0.00%
3357system.ruby.TCCdir_Controller.CP_O.ProbeAcksComplete 9 0.00% 0.00%
3358system.ruby.TCCdir_Controller.I_M.RdBlkM 22 0.00% 0.00%
3359system.ruby.TCCdir_Controller.I_M.NB_AckM 9 0.00% 0.00%
3360system.ruby.TCCdir_Controller.I_ES.RdBlk 41 0.00% 0.00%
3361system.ruby.TCCdir_Controller.I_ES.NB_AckS 2 0.00% 0.00%
3362system.ruby.TCCdir_Controller.I_S.NB_AckS 5 0.00% 0.00%
3363system.ruby.TCCdir_Controller.BBS_S.CPUPrbResp 2 0.00% 0.00%
3364system.ruby.TCCdir_Controller.BBS_S.ProbeAcksComplete 2 0.00% 0.00%
3365system.ruby.TCCdir_Controller.BBM_M.CPUPrbResp 1 0.00% 0.00%
3366system.ruby.TCCdir_Controller.BBM_M.ProbeAcksComplete 1 0.00% 0.00%
3367system.ruby.TCCdir_Controller.BB_M.CoreUnblock 1 0.00% 0.00%
3368system.ruby.TCCdir_Controller.BB_S.LastCoreUnblock 2 0.00% 0.00%
3369system.ruby.TCCdir_Controller.BBB_S.RdBlk 9 0.00% 0.00%
3370system.ruby.TCCdir_Controller.BBB_S.CoreUnblock 7 0.00% 0.00%
3371system.ruby.TCCdir_Controller.BBB_M.RdBlkM 4 0.00% 0.00%
3372system.ruby.TCCdir_Controller.BBB_M.CoreUnblock 9 0.00% 0.00%
3373system.ruby.TCP_Controller.Load | 4 44.44% 44.44% | 5 55.56% 100.00%
3374system.ruby.TCP_Controller.Load::total 9
3375system.ruby.TCP_Controller.Store | 9 50.00% 50.00% | 9 50.00% 100.00%
3376system.ruby.TCP_Controller.Store::total 18
3377system.ruby.TCP_Controller.TCC_AckS | 2 50.00% 50.00% | 2 50.00% 100.00%
3378system.ruby.TCP_Controller.TCC_AckS::total 4
3379system.ruby.TCP_Controller.TCC_AckM | 5 50.00% 50.00% | 5 50.00% 100.00%

--- 27 unchanged lines hidden ---