| stats.txt (11606:6b749761c398) | stats.txt (11680:b4d943429dc6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000056 # Number of seconds simulated 4sim_ticks 56435000 # Number of ticks simulated 5final_tick 56435000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000059 # Number of seconds simulated 4sim_ticks 58513000 # Number of ticks simulated 5final_tick 58513000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 125605 # Simulator instruction rate (inst/s) 8host_op_rate 226732 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1240265940 # Simulator tick rate (ticks/s) 10host_mem_usage 656384 # Number of bytes of host memory used 11host_seconds 0.05 # Real time elapsed on the host | 7host_inst_rate 325988 # Simulator instruction rate (inst/s) 8host_op_rate 588251 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3335289412 # Simulator tick rate (ticks/s) 10host_mem_usage 654560 # Number of bytes of host memory used 11host_seconds 0.02 # Real time elapsed on the host |
| 12sim_insts 5712 # Number of instructions simulated 13sim_ops 10314 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 5712 # Number of instructions simulated 13sim_ops 10314 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states | 16system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states |
| 17system.mem_ctrl.bytes_read::cpu.inst 14656 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::cpu.data 8640 # Number of bytes read from this memory 19system.mem_ctrl.bytes_read::total 23296 # Number of bytes read from this memory 20system.mem_ctrl.bytes_inst_read::cpu.inst 14656 # Number of instructions bytes read from this memory 21system.mem_ctrl.bytes_inst_read::total 14656 # Number of instructions bytes read from this memory 22system.mem_ctrl.num_reads::cpu.inst 229 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::cpu.data 135 # Number of read requests responded to by this memory 24system.mem_ctrl.num_reads::total 364 # Number of read requests responded to by this memory | 17system.mem_ctrl.bytes_read::cpu.inst 14656 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::cpu.data 8640 # Number of bytes read from this memory 19system.mem_ctrl.bytes_read::total 23296 # Number of bytes read from this memory 20system.mem_ctrl.bytes_inst_read::cpu.inst 14656 # Number of instructions bytes read from this memory 21system.mem_ctrl.bytes_inst_read::total 14656 # Number of instructions bytes read from this memory 22system.mem_ctrl.num_reads::cpu.inst 229 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::cpu.data 135 # Number of read requests responded to by this memory 24system.mem_ctrl.num_reads::total 364 # Number of read requests responded to by this memory |
| 25system.mem_ctrl.bw_read::cpu.inst 259696997 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrl.bw_read::cpu.data 153096483 # Total read bandwidth from this memory (bytes/s) 27system.mem_ctrl.bw_read::total 412793479 # Total read bandwidth from this memory (bytes/s) 28system.mem_ctrl.bw_inst_read::cpu.inst 259696997 # Instruction read bandwidth from this memory (bytes/s) 29system.mem_ctrl.bw_inst_read::total 259696997 # Instruction read bandwidth from this memory (bytes/s) 30system.mem_ctrl.bw_total::cpu.inst 259696997 # Total bandwidth to/from this memory (bytes/s) 31system.mem_ctrl.bw_total::cpu.data 153096483 # Total bandwidth to/from this memory (bytes/s) 32system.mem_ctrl.bw_total::total 412793479 # Total bandwidth to/from this memory (bytes/s) | 25system.mem_ctrl.bw_read::cpu.inst 250474254 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrl.bw_read::cpu.data 147659494 # Total read bandwidth from this memory (bytes/s) 27system.mem_ctrl.bw_read::total 398133748 # Total read bandwidth from this memory (bytes/s) 28system.mem_ctrl.bw_inst_read::cpu.inst 250474254 # Instruction read bandwidth from this memory (bytes/s) 29system.mem_ctrl.bw_inst_read::total 250474254 # Instruction read bandwidth from this memory (bytes/s) 30system.mem_ctrl.bw_total::cpu.inst 250474254 # Total bandwidth to/from this memory (bytes/s) 31system.mem_ctrl.bw_total::cpu.data 147659494 # Total bandwidth to/from this memory (bytes/s) 32system.mem_ctrl.bw_total::total 398133748 # Total bandwidth to/from this memory (bytes/s) |
| 33system.mem_ctrl.readReqs 364 # Number of read requests accepted 34system.mem_ctrl.writeReqs 0 # Number of write requests accepted 35system.mem_ctrl.readBursts 364 # Number of DRAM read bursts, including those serviced by the write queue 36system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.mem_ctrl.bytesReadDRAM 23296 # Total number of bytes read from DRAM 38system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM 40system.mem_ctrl.bytesReadSys 23296 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts 72system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts 73system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts 74system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts 75system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts 76system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts 77system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry 78system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry | 33system.mem_ctrl.readReqs 364 # Number of read requests accepted 34system.mem_ctrl.writeReqs 0 # Number of write requests accepted 35system.mem_ctrl.readBursts 364 # Number of DRAM read bursts, including those serviced by the write queue 36system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.mem_ctrl.bytesReadDRAM 23296 # Total number of bytes read from DRAM 38system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM 40system.mem_ctrl.bytesReadSys 23296 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts 72system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts 73system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts 74system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts 75system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts 76system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts 77system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry 78system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry |
| 79system.mem_ctrl.totGap 56304000 # Total gap between requests | 79system.mem_ctrl.totGap 58376000 # Total gap between requests |
| 80system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) 81system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) 82system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) 83system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) 84system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) 85system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) 86system.mem_ctrl.readPktSize::6 364 # Read request sizes (log2) 87system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) --- 94 unchanged lines hidden (view full) --- 182system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see | 80system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) 81system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) 82system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) 83system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) 84system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) 85system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) 86system.mem_ctrl.readPktSize::6 364 # Read request sizes (log2) 87system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) --- 94 unchanged lines hidden (view full) --- 182system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 190system.mem_ctrl.bytesPerActivate::samples 117 # Bytes accessed per row activation 191system.mem_ctrl.bytesPerActivate::mean 193.094017 # Bytes accessed per row activation 192system.mem_ctrl.bytesPerActivate::gmean 128.926887 # Bytes accessed per row activation 193system.mem_ctrl.bytesPerActivate::stdev 215.889898 # Bytes accessed per row activation 194system.mem_ctrl.bytesPerActivate::0-127 57 48.72% 48.72% # Bytes accessed per row activation 195system.mem_ctrl.bytesPerActivate::128-255 28 23.93% 72.65% # Bytes accessed per row activation 196system.mem_ctrl.bytesPerActivate::256-383 16 13.68% 86.32% # Bytes accessed per row activation 197system.mem_ctrl.bytesPerActivate::384-511 6 5.13% 91.45% # Bytes accessed per row activation 198system.mem_ctrl.bytesPerActivate::512-639 2 1.71% 93.16% # Bytes accessed per row activation 199system.mem_ctrl.bytesPerActivate::640-767 2 1.71% 94.87% # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::768-895 3 2.56% 97.44% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::1024-1151 3 2.56% 100.00% # Bytes accessed per row activation 202system.mem_ctrl.bytesPerActivate::total 117 # Bytes accessed per row activation 203system.mem_ctrl.totQLat 3777750 # Total ticks spent queuing 204system.mem_ctrl.totMemAccLat 10602750 # Total ticks spent from burst creation until serviced by the DRAM | 190system.mem_ctrl.bytesPerActivate::samples 108 # Bytes accessed per row activation 191system.mem_ctrl.bytesPerActivate::mean 199.703704 # Bytes accessed per row activation 192system.mem_ctrl.bytesPerActivate::gmean 135.091179 # Bytes accessed per row activation 193system.mem_ctrl.bytesPerActivate::stdev 199.282229 # Bytes accessed per row activation 194system.mem_ctrl.bytesPerActivate::0-127 52 48.15% 48.15% # Bytes accessed per row activation 195system.mem_ctrl.bytesPerActivate::128-255 21 19.44% 67.59% # Bytes accessed per row activation 196system.mem_ctrl.bytesPerActivate::256-383 15 13.89% 81.48% # Bytes accessed per row activation 197system.mem_ctrl.bytesPerActivate::384-511 8 7.41% 88.89% # Bytes accessed per row activation 198system.mem_ctrl.bytesPerActivate::512-639 7 6.48% 95.37% # Bytes accessed per row activation 199system.mem_ctrl.bytesPerActivate::640-767 2 1.85% 97.22% # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::768-895 1 0.93% 98.15% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::896-1023 1 0.93% 99.07% # Bytes accessed per row activation 202system.mem_ctrl.bytesPerActivate::1024-1151 1 0.93% 100.00% # Bytes accessed per row activation 203system.mem_ctrl.bytesPerActivate::total 108 # Bytes accessed per row activation 204system.mem_ctrl.totQLat 5858750 # Total ticks spent queuing 205system.mem_ctrl.totMemAccLat 12683750 # Total ticks spent from burst creation until serviced by the DRAM |
| 205system.mem_ctrl.totBusLat 1820000 # Total ticks spent in databus transfers | 206system.mem_ctrl.totBusLat 1820000 # Total ticks spent in databus transfers |
| 206system.mem_ctrl.avgQLat 10378.43 # Average queueing delay per DRAM burst | 207system.mem_ctrl.avgQLat 16095.47 # Average queueing delay per DRAM burst |
| 207system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst | 208system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 208system.mem_ctrl.avgMemAccLat 29128.43 # Average memory access latency per DRAM burst 209system.mem_ctrl.avgRdBW 412.79 # Average DRAM read bandwidth in MiByte/s | 209system.mem_ctrl.avgMemAccLat 34845.47 # Average memory access latency per DRAM burst 210system.mem_ctrl.avgRdBW 398.13 # Average DRAM read bandwidth in MiByte/s |
| 210system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 211system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 211system.mem_ctrl.avgRdBWSys 412.79 # Average system read bandwidth in MiByte/s | 212system.mem_ctrl.avgRdBWSys 398.13 # Average system read bandwidth in MiByte/s |
| 212system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 213system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 214system.mem_ctrl.busUtil 3.22 # Data bus utilization in percentage 215system.mem_ctrl.busUtilRead 3.22 # Data bus utilization in percentage for reads | 215system.mem_ctrl.busUtil 3.11 # Data bus utilization in percentage 216system.mem_ctrl.busUtilRead 3.11 # Data bus utilization in percentage for reads |
| 216system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing 218system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing | 217system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing 219system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 219system.mem_ctrl.readRowHits 241 # Number of row buffer hits during reads | 220system.mem_ctrl.readRowHits 248 # Number of row buffer hits during reads |
| 220system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes | 221system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes |
| 221system.mem_ctrl.readRowHitRate 66.21 # Row buffer hit rate for reads | 222system.mem_ctrl.readRowHitRate 68.13 # Row buffer hit rate for reads |
| 222system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes | 223system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes |
| 223system.mem_ctrl.avgGap 154681.32 # Average gap between requests 224system.mem_ctrl.pageHitRate 66.21 # Row buffer hit rate, read and write combined 225system.mem_ctrl_0.actEnergy 309960 # Energy for activate commands per rank (pJ) 226system.mem_ctrl_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) 227system.mem_ctrl_0.readEnergy 1201200 # Energy for read commands per rank (pJ) | 224system.mem_ctrl.avgGap 160373.63 # Average gap between requests 225system.mem_ctrl.pageHitRate 68.13 # Row buffer hit rate, read and write combined 226system.mem_ctrl_0.actEnergy 292740 # Energy for activate commands per rank (pJ) 227system.mem_ctrl_0.preEnergy 136620 # Energy for precharge commands per rank (pJ) 228system.mem_ctrl_0.readEnergy 1170960 # Energy for read commands per rank (pJ) |
| 228system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) | 229system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 229system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) 230system.mem_ctrl_0.actBackEnergy 32277105 # Energy for active background per rank (pJ) 231system.mem_ctrl_0.preBackEnergy 4545000 # Energy for precharge background per rank (pJ) 232system.mem_ctrl_0.totalEnergy 42062310 # Total energy per rank (pJ) 233system.mem_ctrl_0.averagePower 768.068476 # Core power per rank (mW) 234system.mem_ctrl_0.memoryStateTime::IDLE 7392500 # Time in different power states | 230system.mem_ctrl_0.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) 231system.mem_ctrl_0.actBackEnergy 2975970 # Energy for active background per rank (pJ) 232system.mem_ctrl_0.preBackEnergy 96960 # Energy for precharge background per rank (pJ) 233system.mem_ctrl_0.actPowerDownEnergy 20164320 # Energy for active power-down per rank (pJ) 234system.mem_ctrl_0.prePowerDownEnergy 2885760 # Energy for precharge power-down per rank (pJ) 235system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 236system.mem_ctrl_0.totalEnergy 32025810 # Total energy per rank (pJ) 237system.mem_ctrl_0.averagePower 547.321100 # Core power per rank (mW) 238system.mem_ctrl_0.totalIdleTime 51467750 # Total Idle time Per DRAM Rank 239system.mem_ctrl_0.memoryStateTime::IDLE 59000 # Time in different power states |
| 235system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states | 240system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states |
| 236system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states 237system.mem_ctrl_0.memoryStateTime::ACT 45565000 # Time in different power states 238system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.mem_ctrl_1.actEnergy 574560 # Energy for activate commands per rank (pJ) 240system.mem_ctrl_1.preEnergy 313500 # Energy for precharge commands per rank (pJ) 241system.mem_ctrl_1.readEnergy 1552200 # Energy for read commands per rank (pJ) | 241system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states 242system.mem_ctrl_0.memoryStateTime::PRE_PDN 7513000 # Time in different power states 243system.mem_ctrl_0.memoryStateTime::ACT 4902000 # Time in different power states 244system.mem_ctrl_0.memoryStateTime::ACT_PDN 44219000 # Time in different power states 245system.mem_ctrl_1.actEnergy 535500 # Energy for activate commands per rank (pJ) 246system.mem_ctrl_1.preEnergy 273240 # Energy for precharge commands per rank (pJ) 247system.mem_ctrl_1.readEnergy 1428000 # Energy for read commands per rank (pJ) |
| 242system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) | 248system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 243system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) 244system.mem_ctrl_1.actBackEnergy 36915480 # Energy for active background per rank (pJ) 245system.mem_ctrl_1.preBackEnergy 476250 # Energy for precharge background per rank (pJ) 246system.mem_ctrl_1.totalEnergy 43391910 # Total energy per rank (pJ) 247system.mem_ctrl_1.averagePower 792.347310 # Core power per rank (mW) 248system.mem_ctrl_1.memoryStateTime::IDLE 2122500 # Time in different power states | 249system.mem_ctrl_1.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) 250system.mem_ctrl_1.actBackEnergy 3735210 # Energy for active background per rank (pJ) 251system.mem_ctrl_1.preBackEnergy 150720 # Energy for precharge background per rank (pJ) 252system.mem_ctrl_1.actPowerDownEnergy 22328040 # Energy for active power-down per rank (pJ) 253system.mem_ctrl_1.prePowerDownEnergy 370560 # Energy for precharge power-down per rank (pJ) 254system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 255system.mem_ctrl_1.totalEnergy 33123750 # Total energy per rank (pJ) 256system.mem_ctrl_1.averagePower 566.084895 # Core power per rank (mW) 257system.mem_ctrl_1.totalIdleTime 49870500 # Total Idle time Per DRAM Rank 258system.mem_ctrl_1.memoryStateTime::IDLE 184000 # Time in different power states |
| 249system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states | 259system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states |
| 250system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.mem_ctrl_1.memoryStateTime::ACT 52384500 # Time in different power states 252system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states 254system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states | 260system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states 261system.mem_ctrl_1.memoryStateTime::PRE_PDN 965000 # Time in different power states 262system.mem_ctrl_1.memoryStateTime::ACT 6563000 # Time in different power states 263system.mem_ctrl_1.memoryStateTime::ACT_PDN 48981000 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states 265system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states |
| 255system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks | 266system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks |
| 256system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states 257system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states | 267system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states 268system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states |
| 258system.cpu.workload.num_syscalls 11 # Number of system calls | 269system.cpu.workload.num_syscalls 11 # Number of system calls |
| 259system.cpu.pwrStateResidencyTicks::ON 56435000 # Cumulative time (in ticks) in various power states 260system.cpu.numCycles 56435 # number of cpu cycles simulated | 270system.cpu.pwrStateResidencyTicks::ON 58513000 # Cumulative time (in ticks) in various power states 271system.cpu.numCycles 58513 # number of cpu cycles simulated |
| 261system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 262system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 263system.cpu.committedInsts 5712 # Number of instructions committed 264system.cpu.committedOps 10314 # Number of ops (including micro ops) committed 265system.cpu.num_int_alu_accesses 10205 # Number of integer alu accesses 266system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 267system.cpu.num_func_calls 221 # number of times a function call or return occured 268system.cpu.num_conditional_control_insts 986 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 273system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 274system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 275system.cpu.num_cc_register_reads 7020 # number of times the CC registers were read 276system.cpu.num_cc_register_writes 3825 # number of times the CC registers were written 277system.cpu.num_mem_refs 2025 # number of memory refs 278system.cpu.num_load_insts 1084 # Number of load instructions 279system.cpu.num_store_insts 941 # Number of store instructions 280system.cpu.num_idle_cycles 0.001000 # Number of idle cycles | 272system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 273system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 274system.cpu.committedInsts 5712 # Number of instructions committed 275system.cpu.committedOps 10314 # Number of ops (including micro ops) committed 276system.cpu.num_int_alu_accesses 10205 # Number of integer alu accesses 277system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 278system.cpu.num_func_calls 221 # number of times a function call or return occured 279system.cpu.num_conditional_control_insts 986 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 284system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 285system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 286system.cpu.num_cc_register_reads 7020 # number of times the CC registers were read 287system.cpu.num_cc_register_writes 3825 # number of times the CC registers were written 288system.cpu.num_mem_refs 2025 # number of memory refs 289system.cpu.num_load_insts 1084 # Number of load instructions 290system.cpu.num_store_insts 941 # Number of store instructions 291system.cpu.num_idle_cycles 0.001000 # Number of idle cycles |
| 281system.cpu.num_busy_cycles 56434.999000 # Number of busy cycles | 292system.cpu.num_busy_cycles 58512.999000 # Number of busy cycles |
| 282system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 283system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 284system.cpu.Branches 1306 # Number of branches fetched 285system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction 286system.cpu.op_class::IntAlu 8275 80.23% 80.24% # Class of executed instruction 287system.cpu.op_class::IntMult 6 0.06% 80.30% # Class of executed instruction 288system.cpu.op_class::IntDiv 7 0.07% 80.37% # Class of executed instruction 289system.cpu.op_class::FloatAdd 0 0.00% 80.37% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 312system.cpu.op_class::SimdFloatMult 0 0.00% 80.37% # Class of executed instruction 313system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37% # Class of executed instruction 314system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37% # Class of executed instruction 315system.cpu.op_class::MemRead 1084 10.51% 90.88% # Class of executed instruction 316system.cpu.op_class::MemWrite 941 9.12% 100.00% # Class of executed instruction 317system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 318system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 319system.cpu.op_class::total 10314 # Class of executed instruction | 293system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 294system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 295system.cpu.Branches 1306 # Number of branches fetched 296system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction 297system.cpu.op_class::IntAlu 8275 80.23% 80.24% # Class of executed instruction 298system.cpu.op_class::IntMult 6 0.06% 80.30% # Class of executed instruction 299system.cpu.op_class::IntDiv 7 0.07% 80.37% # Class of executed instruction 300system.cpu.op_class::FloatAdd 0 0.00% 80.37% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 323system.cpu.op_class::SimdFloatMult 0 0.00% 80.37% # Class of executed instruction 324system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37% # Class of executed instruction 325system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37% # Class of executed instruction 326system.cpu.op_class::MemRead 1084 10.51% 90.88% # Class of executed instruction 327system.cpu.op_class::MemWrite 941 9.12% 100.00% # Class of executed instruction 328system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 329system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 330system.cpu.op_class::total 10314 # Class of executed instruction |
| 320system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states | 331system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states |
| 321system.cpu.dcache.tags.replacements 0 # number of replacements | 332system.cpu.dcache.tags.replacements 0 # number of replacements |
| 322system.cpu.dcache.tags.tagsinuse 81.661133 # Cycle average of tags in use | 333system.cpu.dcache.tags.tagsinuse 81.299644 # Cycle average of tags in use |
| 323system.cpu.dcache.tags.total_refs 1890 # Total number of references to valid blocks. 324system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. 325system.cpu.dcache.tags.avg_refs 14 # Average number of references to valid blocks. 326system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 334system.cpu.dcache.tags.total_refs 1890 # Total number of references to valid blocks. 335system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. 336system.cpu.dcache.tags.avg_refs 14 # Average number of references to valid blocks. 337system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 327system.cpu.dcache.tags.occ_blocks::cpu.data 81.661133 # Average occupied blocks per requestor 328system.cpu.dcache.tags.occ_percent::cpu.data 0.079747 # Average percentage of cache occupancy 329system.cpu.dcache.tags.occ_percent::total 0.079747 # Average percentage of cache occupancy | 338system.cpu.dcache.tags.occ_blocks::cpu.data 81.299644 # Average occupied blocks per requestor 339system.cpu.dcache.tags.occ_percent::cpu.data 0.079394 # Average percentage of cache occupancy 340system.cpu.dcache.tags.occ_percent::total 0.079394 # Average percentage of cache occupancy |
| 330system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id 331system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id 332system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id 333system.cpu.dcache.tags.occ_task_id_percent::1024 0.131836 # Percentage of cache occupancy per task id 334system.cpu.dcache.tags.tag_accesses 4185 # Number of tag accesses 335system.cpu.dcache.tags.data_accesses 4185 # Number of data accesses | 341system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id 342system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id 343system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id 344system.cpu.dcache.tags.occ_task_id_percent::1024 0.131836 # Percentage of cache occupancy per task id 345system.cpu.dcache.tags.tag_accesses 4185 # Number of tag accesses 346system.cpu.dcache.tags.data_accesses 4185 # Number of data accesses |
| 336system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states | 347system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states |
| 337system.cpu.dcache.ReadReq_hits::cpu.data 1028 # number of ReadReq hits 338system.cpu.dcache.ReadReq_hits::total 1028 # number of ReadReq hits 339system.cpu.dcache.WriteReq_hits::cpu.data 862 # number of WriteReq hits 340system.cpu.dcache.WriteReq_hits::total 862 # number of WriteReq hits 341system.cpu.dcache.demand_hits::cpu.data 1890 # number of demand (read+write) hits 342system.cpu.dcache.demand_hits::total 1890 # number of demand (read+write) hits 343system.cpu.dcache.overall_hits::cpu.data 1890 # number of overall hits 344system.cpu.dcache.overall_hits::total 1890 # number of overall hits 345system.cpu.dcache.ReadReq_misses::cpu.data 56 # number of ReadReq misses 346system.cpu.dcache.ReadReq_misses::total 56 # number of ReadReq misses 347system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses 348system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses 349system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses 350system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses 351system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses 352system.cpu.dcache.overall_misses::total 135 # number of overall misses | 348system.cpu.dcache.ReadReq_hits::cpu.data 1028 # number of ReadReq hits 349system.cpu.dcache.ReadReq_hits::total 1028 # number of ReadReq hits 350system.cpu.dcache.WriteReq_hits::cpu.data 862 # number of WriteReq hits 351system.cpu.dcache.WriteReq_hits::total 862 # number of WriteReq hits 352system.cpu.dcache.demand_hits::cpu.data 1890 # number of demand (read+write) hits 353system.cpu.dcache.demand_hits::total 1890 # number of demand (read+write) hits 354system.cpu.dcache.overall_hits::cpu.data 1890 # number of overall hits 355system.cpu.dcache.overall_hits::total 1890 # number of overall hits 356system.cpu.dcache.ReadReq_misses::cpu.data 56 # number of ReadReq misses 357system.cpu.dcache.ReadReq_misses::total 56 # number of ReadReq misses 358system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses 359system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses 360system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses 361system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses 362system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses 363system.cpu.dcache.overall_misses::total 135 # number of overall misses |
| 353system.cpu.dcache.ReadReq_miss_latency::cpu.data 6076000 # number of ReadReq miss cycles 354system.cpu.dcache.ReadReq_miss_latency::total 6076000 # number of ReadReq miss cycles 355system.cpu.dcache.WriteReq_miss_latency::cpu.data 8376000 # number of WriteReq miss cycles 356system.cpu.dcache.WriteReq_miss_latency::total 8376000 # number of WriteReq miss cycles 357system.cpu.dcache.demand_miss_latency::cpu.data 14452000 # number of demand (read+write) miss cycles 358system.cpu.dcache.demand_miss_latency::total 14452000 # number of demand (read+write) miss cycles 359system.cpu.dcache.overall_miss_latency::cpu.data 14452000 # number of overall miss cycles 360system.cpu.dcache.overall_miss_latency::total 14452000 # number of overall miss cycles | 364system.cpu.dcache.ReadReq_miss_latency::cpu.data 6406000 # number of ReadReq miss cycles 365system.cpu.dcache.ReadReq_miss_latency::total 6406000 # number of ReadReq miss cycles 366system.cpu.dcache.WriteReq_miss_latency::cpu.data 8602000 # number of WriteReq miss cycles 367system.cpu.dcache.WriteReq_miss_latency::total 8602000 # number of WriteReq miss cycles 368system.cpu.dcache.demand_miss_latency::cpu.data 15008000 # number of demand (read+write) miss cycles 369system.cpu.dcache.demand_miss_latency::total 15008000 # number of demand (read+write) miss cycles 370system.cpu.dcache.overall_miss_latency::cpu.data 15008000 # number of overall miss cycles 371system.cpu.dcache.overall_miss_latency::total 15008000 # number of overall miss cycles |
| 361system.cpu.dcache.ReadReq_accesses::cpu.data 1084 # number of ReadReq accesses(hits+misses) 362system.cpu.dcache.ReadReq_accesses::total 1084 # number of ReadReq accesses(hits+misses) 363system.cpu.dcache.WriteReq_accesses::cpu.data 941 # number of WriteReq accesses(hits+misses) 364system.cpu.dcache.WriteReq_accesses::total 941 # number of WriteReq accesses(hits+misses) 365system.cpu.dcache.demand_accesses::cpu.data 2025 # number of demand (read+write) accesses 366system.cpu.dcache.demand_accesses::total 2025 # number of demand (read+write) accesses 367system.cpu.dcache.overall_accesses::cpu.data 2025 # number of overall (read+write) accesses 368system.cpu.dcache.overall_accesses::total 2025 # number of overall (read+write) accesses 369system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.051661 # miss rate for ReadReq accesses 370system.cpu.dcache.ReadReq_miss_rate::total 0.051661 # miss rate for ReadReq accesses 371system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083953 # miss rate for WriteReq accesses 372system.cpu.dcache.WriteReq_miss_rate::total 0.083953 # miss rate for WriteReq accesses 373system.cpu.dcache.demand_miss_rate::cpu.data 0.066667 # miss rate for demand accesses 374system.cpu.dcache.demand_miss_rate::total 0.066667 # miss rate for demand accesses 375system.cpu.dcache.overall_miss_rate::cpu.data 0.066667 # miss rate for overall accesses 376system.cpu.dcache.overall_miss_rate::total 0.066667 # miss rate for overall accesses | 372system.cpu.dcache.ReadReq_accesses::cpu.data 1084 # number of ReadReq accesses(hits+misses) 373system.cpu.dcache.ReadReq_accesses::total 1084 # number of ReadReq accesses(hits+misses) 374system.cpu.dcache.WriteReq_accesses::cpu.data 941 # number of WriteReq accesses(hits+misses) 375system.cpu.dcache.WriteReq_accesses::total 941 # number of WriteReq accesses(hits+misses) 376system.cpu.dcache.demand_accesses::cpu.data 2025 # number of demand (read+write) accesses 377system.cpu.dcache.demand_accesses::total 2025 # number of demand (read+write) accesses 378system.cpu.dcache.overall_accesses::cpu.data 2025 # number of overall (read+write) accesses 379system.cpu.dcache.overall_accesses::total 2025 # number of overall (read+write) accesses 380system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.051661 # miss rate for ReadReq accesses 381system.cpu.dcache.ReadReq_miss_rate::total 0.051661 # miss rate for ReadReq accesses 382system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083953 # miss rate for WriteReq accesses 383system.cpu.dcache.WriteReq_miss_rate::total 0.083953 # miss rate for WriteReq accesses 384system.cpu.dcache.demand_miss_rate::cpu.data 0.066667 # miss rate for demand accesses 385system.cpu.dcache.demand_miss_rate::total 0.066667 # miss rate for demand accesses 386system.cpu.dcache.overall_miss_rate::cpu.data 0.066667 # miss rate for overall accesses 387system.cpu.dcache.overall_miss_rate::total 0.066667 # miss rate for overall accesses |
| 377system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 108500 # average ReadReq miss latency 378system.cpu.dcache.ReadReq_avg_miss_latency::total 108500 # average ReadReq miss latency 379system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 106025.316456 # average WriteReq miss latency 380system.cpu.dcache.WriteReq_avg_miss_latency::total 106025.316456 # average WriteReq miss latency 381system.cpu.dcache.demand_avg_miss_latency::cpu.data 107051.851852 # average overall miss latency 382system.cpu.dcache.demand_avg_miss_latency::total 107051.851852 # average overall miss latency 383system.cpu.dcache.overall_avg_miss_latency::cpu.data 107051.851852 # average overall miss latency 384system.cpu.dcache.overall_avg_miss_latency::total 107051.851852 # average overall miss latency | 388system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 114392.857143 # average ReadReq miss latency 389system.cpu.dcache.ReadReq_avg_miss_latency::total 114392.857143 # average ReadReq miss latency 390system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108886.075949 # average WriteReq miss latency 391system.cpu.dcache.WriteReq_avg_miss_latency::total 108886.075949 # average WriteReq miss latency 392system.cpu.dcache.demand_avg_miss_latency::cpu.data 111170.370370 # average overall miss latency 393system.cpu.dcache.demand_avg_miss_latency::total 111170.370370 # average overall miss latency 394system.cpu.dcache.overall_avg_miss_latency::cpu.data 111170.370370 # average overall miss latency 395system.cpu.dcache.overall_avg_miss_latency::total 111170.370370 # average overall miss latency |
| 385system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 386system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 387system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 388system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 389system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 390system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 391system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses 392system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses 393system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses 394system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses 395system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses 396system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses 397system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses 398system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses | 396system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 397system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 398system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 399system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 400system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 401system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 402system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses 403system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses 404system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses 405system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses 406system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses 407system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses 408system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses 409system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses |
| 399system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5964000 # number of ReadReq MSHR miss cycles 400system.cpu.dcache.ReadReq_mshr_miss_latency::total 5964000 # number of ReadReq MSHR miss cycles 401system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8218000 # number of WriteReq MSHR miss cycles 402system.cpu.dcache.WriteReq_mshr_miss_latency::total 8218000 # number of WriteReq MSHR miss cycles 403system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14182000 # number of demand (read+write) MSHR miss cycles 404system.cpu.dcache.demand_mshr_miss_latency::total 14182000 # number of demand (read+write) MSHR miss cycles 405system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14182000 # number of overall MSHR miss cycles 406system.cpu.dcache.overall_mshr_miss_latency::total 14182000 # number of overall MSHR miss cycles | 410system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6294000 # number of ReadReq MSHR miss cycles 411system.cpu.dcache.ReadReq_mshr_miss_latency::total 6294000 # number of ReadReq MSHR miss cycles 412system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8444000 # number of WriteReq MSHR miss cycles 413system.cpu.dcache.WriteReq_mshr_miss_latency::total 8444000 # number of WriteReq MSHR miss cycles 414system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14738000 # number of demand (read+write) MSHR miss cycles 415system.cpu.dcache.demand_mshr_miss_latency::total 14738000 # number of demand (read+write) MSHR miss cycles 416system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14738000 # number of overall MSHR miss cycles 417system.cpu.dcache.overall_mshr_miss_latency::total 14738000 # number of overall MSHR miss cycles |
| 407system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051661 # mshr miss rate for ReadReq accesses 408system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051661 # mshr miss rate for ReadReq accesses 409system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083953 # mshr miss rate for WriteReq accesses 410system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083953 # mshr miss rate for WriteReq accesses 411system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066667 # mshr miss rate for demand accesses 412system.cpu.dcache.demand_mshr_miss_rate::total 0.066667 # mshr miss rate for demand accesses 413system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066667 # mshr miss rate for overall accesses 414system.cpu.dcache.overall_mshr_miss_rate::total 0.066667 # mshr miss rate for overall accesses | 418system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051661 # mshr miss rate for ReadReq accesses 419system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051661 # mshr miss rate for ReadReq accesses 420system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083953 # mshr miss rate for WriteReq accesses 421system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083953 # mshr miss rate for WriteReq accesses 422system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066667 # mshr miss rate for demand accesses 423system.cpu.dcache.demand_mshr_miss_rate::total 0.066667 # mshr miss rate for demand accesses 424system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066667 # mshr miss rate for overall accesses 425system.cpu.dcache.overall_mshr_miss_rate::total 0.066667 # mshr miss rate for overall accesses |
| 415system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 106500 # average ReadReq mshr miss latency 416system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 106500 # average ReadReq mshr miss latency 417system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 104025.316456 # average WriteReq mshr miss latency 418system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 104025.316456 # average WriteReq mshr miss latency 419system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 105051.851852 # average overall mshr miss latency 420system.cpu.dcache.demand_avg_mshr_miss_latency::total 105051.851852 # average overall mshr miss latency 421system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 105051.851852 # average overall mshr miss latency 422system.cpu.dcache.overall_avg_mshr_miss_latency::total 105051.851852 # average overall mshr miss latency 423system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states | 426system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 112392.857143 # average ReadReq mshr miss latency 427system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 112392.857143 # average ReadReq mshr miss latency 428system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106886.075949 # average WriteReq mshr miss latency 429system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106886.075949 # average WriteReq mshr miss latency 430system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 109170.370370 # average overall mshr miss latency 431system.cpu.dcache.demand_avg_mshr_miss_latency::total 109170.370370 # average overall mshr miss latency 432system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 109170.370370 # average overall mshr miss latency 433system.cpu.dcache.overall_avg_mshr_miss_latency::total 109170.370370 # average overall mshr miss latency 434system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states |
| 424system.cpu.icache.tags.replacements 58 # number of replacements | 435system.cpu.icache.tags.replacements 58 # number of replacements |
| 425system.cpu.icache.tags.tagsinuse 91.248553 # Cycle average of tags in use | 436system.cpu.icache.tags.tagsinuse 90.704136 # Cycle average of tags in use |
| 426system.cpu.icache.tags.total_refs 7048 # Total number of references to valid blocks. 427system.cpu.icache.tags.sampled_refs 235 # Sample count of references to valid blocks. 428system.cpu.icache.tags.avg_refs 29.991489 # Average number of references to valid blocks. 429system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 437system.cpu.icache.tags.total_refs 7048 # Total number of references to valid blocks. 438system.cpu.icache.tags.sampled_refs 235 # Sample count of references to valid blocks. 439system.cpu.icache.tags.avg_refs 29.991489 # Average number of references to valid blocks. 440system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 430system.cpu.icache.tags.occ_blocks::cpu.inst 91.248553 # Average occupied blocks per requestor 431system.cpu.icache.tags.occ_percent::cpu.inst 0.356440 # Average percentage of cache occupancy 432system.cpu.icache.tags.occ_percent::total 0.356440 # Average percentage of cache occupancy | 441system.cpu.icache.tags.occ_blocks::cpu.inst 90.704136 # Average occupied blocks per requestor 442system.cpu.icache.tags.occ_percent::cpu.inst 0.354313 # Average percentage of cache occupancy 443system.cpu.icache.tags.occ_percent::total 0.354313 # Average percentage of cache occupancy |
| 433system.cpu.icache.tags.occ_task_id_blocks::1024 177 # Occupied blocks per task id 434system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id 435system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id 436system.cpu.icache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id 437system.cpu.icache.tags.tag_accesses 14801 # Number of tag accesses 438system.cpu.icache.tags.data_accesses 14801 # Number of data accesses | 444system.cpu.icache.tags.occ_task_id_blocks::1024 177 # Occupied blocks per task id 445system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id 446system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id 447system.cpu.icache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id 448system.cpu.icache.tags.tag_accesses 14801 # Number of tag accesses 449system.cpu.icache.tags.data_accesses 14801 # Number of data accesses |
| 439system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states | 450system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states |
| 440system.cpu.icache.ReadReq_hits::cpu.inst 7048 # number of ReadReq hits 441system.cpu.icache.ReadReq_hits::total 7048 # number of ReadReq hits 442system.cpu.icache.demand_hits::cpu.inst 7048 # number of demand (read+write) hits 443system.cpu.icache.demand_hits::total 7048 # number of demand (read+write) hits 444system.cpu.icache.overall_hits::cpu.inst 7048 # number of overall hits 445system.cpu.icache.overall_hits::total 7048 # number of overall hits 446system.cpu.icache.ReadReq_misses::cpu.inst 235 # number of ReadReq misses 447system.cpu.icache.ReadReq_misses::total 235 # number of ReadReq misses 448system.cpu.icache.demand_misses::cpu.inst 235 # number of demand (read+write) misses 449system.cpu.icache.demand_misses::total 235 # number of demand (read+write) misses 450system.cpu.icache.overall_misses::cpu.inst 235 # number of overall misses 451system.cpu.icache.overall_misses::total 235 # number of overall misses | 451system.cpu.icache.ReadReq_hits::cpu.inst 7048 # number of ReadReq hits 452system.cpu.icache.ReadReq_hits::total 7048 # number of ReadReq hits 453system.cpu.icache.demand_hits::cpu.inst 7048 # number of demand (read+write) hits 454system.cpu.icache.demand_hits::total 7048 # number of demand (read+write) hits 455system.cpu.icache.overall_hits::cpu.inst 7048 # number of overall hits 456system.cpu.icache.overall_hits::total 7048 # number of overall hits 457system.cpu.icache.ReadReq_misses::cpu.inst 235 # number of ReadReq misses 458system.cpu.icache.ReadReq_misses::total 235 # number of ReadReq misses 459system.cpu.icache.demand_misses::cpu.inst 235 # number of demand (read+write) misses 460system.cpu.icache.demand_misses::total 235 # number of demand (read+write) misses 461system.cpu.icache.overall_misses::cpu.inst 235 # number of overall misses 462system.cpu.icache.overall_misses::total 235 # number of overall misses |
| 452system.cpu.icache.ReadReq_miss_latency::cpu.inst 24107000 # number of ReadReq miss cycles 453system.cpu.icache.ReadReq_miss_latency::total 24107000 # number of ReadReq miss cycles 454system.cpu.icache.demand_miss_latency::cpu.inst 24107000 # number of demand (read+write) miss cycles 455system.cpu.icache.demand_miss_latency::total 24107000 # number of demand (read+write) miss cycles 456system.cpu.icache.overall_miss_latency::cpu.inst 24107000 # number of overall miss cycles 457system.cpu.icache.overall_miss_latency::total 24107000 # number of overall miss cycles | 463system.cpu.icache.ReadReq_miss_latency::cpu.inst 25629000 # number of ReadReq miss cycles 464system.cpu.icache.ReadReq_miss_latency::total 25629000 # number of ReadReq miss cycles 465system.cpu.icache.demand_miss_latency::cpu.inst 25629000 # number of demand (read+write) miss cycles 466system.cpu.icache.demand_miss_latency::total 25629000 # number of demand (read+write) miss cycles 467system.cpu.icache.overall_miss_latency::cpu.inst 25629000 # number of overall miss cycles 468system.cpu.icache.overall_miss_latency::total 25629000 # number of overall miss cycles |
| 458system.cpu.icache.ReadReq_accesses::cpu.inst 7283 # number of ReadReq accesses(hits+misses) 459system.cpu.icache.ReadReq_accesses::total 7283 # number of ReadReq accesses(hits+misses) 460system.cpu.icache.demand_accesses::cpu.inst 7283 # number of demand (read+write) accesses 461system.cpu.icache.demand_accesses::total 7283 # number of demand (read+write) accesses 462system.cpu.icache.overall_accesses::cpu.inst 7283 # number of overall (read+write) accesses 463system.cpu.icache.overall_accesses::total 7283 # number of overall (read+write) accesses 464system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.032267 # miss rate for ReadReq accesses 465system.cpu.icache.ReadReq_miss_rate::total 0.032267 # miss rate for ReadReq accesses 466system.cpu.icache.demand_miss_rate::cpu.inst 0.032267 # miss rate for demand accesses 467system.cpu.icache.demand_miss_rate::total 0.032267 # miss rate for demand accesses 468system.cpu.icache.overall_miss_rate::cpu.inst 0.032267 # miss rate for overall accesses 469system.cpu.icache.overall_miss_rate::total 0.032267 # miss rate for overall accesses | 469system.cpu.icache.ReadReq_accesses::cpu.inst 7283 # number of ReadReq accesses(hits+misses) 470system.cpu.icache.ReadReq_accesses::total 7283 # number of ReadReq accesses(hits+misses) 471system.cpu.icache.demand_accesses::cpu.inst 7283 # number of demand (read+write) accesses 472system.cpu.icache.demand_accesses::total 7283 # number of demand (read+write) accesses 473system.cpu.icache.overall_accesses::cpu.inst 7283 # number of overall (read+write) accesses 474system.cpu.icache.overall_accesses::total 7283 # number of overall (read+write) accesses 475system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.032267 # miss rate for ReadReq accesses 476system.cpu.icache.ReadReq_miss_rate::total 0.032267 # miss rate for ReadReq accesses 477system.cpu.icache.demand_miss_rate::cpu.inst 0.032267 # miss rate for demand accesses 478system.cpu.icache.demand_miss_rate::total 0.032267 # miss rate for demand accesses 479system.cpu.icache.overall_miss_rate::cpu.inst 0.032267 # miss rate for overall accesses 480system.cpu.icache.overall_miss_rate::total 0.032267 # miss rate for overall accesses |
| 470system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 102582.978723 # average ReadReq miss latency 471system.cpu.icache.ReadReq_avg_miss_latency::total 102582.978723 # average ReadReq miss latency 472system.cpu.icache.demand_avg_miss_latency::cpu.inst 102582.978723 # average overall miss latency 473system.cpu.icache.demand_avg_miss_latency::total 102582.978723 # average overall miss latency 474system.cpu.icache.overall_avg_miss_latency::cpu.inst 102582.978723 # average overall miss latency 475system.cpu.icache.overall_avg_miss_latency::total 102582.978723 # average overall miss latency | 481system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 109059.574468 # average ReadReq miss latency 482system.cpu.icache.ReadReq_avg_miss_latency::total 109059.574468 # average ReadReq miss latency 483system.cpu.icache.demand_avg_miss_latency::cpu.inst 109059.574468 # average overall miss latency 484system.cpu.icache.demand_avg_miss_latency::total 109059.574468 # average overall miss latency 485system.cpu.icache.overall_avg_miss_latency::cpu.inst 109059.574468 # average overall miss latency 486system.cpu.icache.overall_avg_miss_latency::total 109059.574468 # average overall miss latency |
| 476system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 477system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 478system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 479system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 480system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 481system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 482system.cpu.icache.ReadReq_mshr_misses::cpu.inst 235 # number of ReadReq MSHR misses 483system.cpu.icache.ReadReq_mshr_misses::total 235 # number of ReadReq MSHR misses 484system.cpu.icache.demand_mshr_misses::cpu.inst 235 # number of demand (read+write) MSHR misses 485system.cpu.icache.demand_mshr_misses::total 235 # number of demand (read+write) MSHR misses 486system.cpu.icache.overall_mshr_misses::cpu.inst 235 # number of overall MSHR misses 487system.cpu.icache.overall_mshr_misses::total 235 # number of overall MSHR misses | 487system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 488system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 489system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 490system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 491system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 492system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 493system.cpu.icache.ReadReq_mshr_misses::cpu.inst 235 # number of ReadReq MSHR misses 494system.cpu.icache.ReadReq_mshr_misses::total 235 # number of ReadReq MSHR misses 495system.cpu.icache.demand_mshr_misses::cpu.inst 235 # number of demand (read+write) MSHR misses 496system.cpu.icache.demand_mshr_misses::total 235 # number of demand (read+write) MSHR misses 497system.cpu.icache.overall_mshr_misses::cpu.inst 235 # number of overall MSHR misses 498system.cpu.icache.overall_mshr_misses::total 235 # number of overall MSHR misses |
| 488system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23637000 # number of ReadReq MSHR miss cycles 489system.cpu.icache.ReadReq_mshr_miss_latency::total 23637000 # number of ReadReq MSHR miss cycles 490system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23637000 # number of demand (read+write) MSHR miss cycles 491system.cpu.icache.demand_mshr_miss_latency::total 23637000 # number of demand (read+write) MSHR miss cycles 492system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23637000 # number of overall MSHR miss cycles 493system.cpu.icache.overall_mshr_miss_latency::total 23637000 # number of overall MSHR miss cycles | 499system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25159000 # number of ReadReq MSHR miss cycles 500system.cpu.icache.ReadReq_mshr_miss_latency::total 25159000 # number of ReadReq MSHR miss cycles 501system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25159000 # number of demand (read+write) MSHR miss cycles 502system.cpu.icache.demand_mshr_miss_latency::total 25159000 # number of demand (read+write) MSHR miss cycles 503system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25159000 # number of overall MSHR miss cycles 504system.cpu.icache.overall_mshr_miss_latency::total 25159000 # number of overall MSHR miss cycles |
| 494system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for ReadReq accesses 495system.cpu.icache.ReadReq_mshr_miss_rate::total 0.032267 # mshr miss rate for ReadReq accesses 496system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for demand accesses 497system.cpu.icache.demand_mshr_miss_rate::total 0.032267 # mshr miss rate for demand accesses 498system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for overall accesses 499system.cpu.icache.overall_mshr_miss_rate::total 0.032267 # mshr miss rate for overall accesses | 505system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for ReadReq accesses 506system.cpu.icache.ReadReq_mshr_miss_rate::total 0.032267 # mshr miss rate for ReadReq accesses 507system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for demand accesses 508system.cpu.icache.demand_mshr_miss_rate::total 0.032267 # mshr miss rate for demand accesses 509system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for overall accesses 510system.cpu.icache.overall_mshr_miss_rate::total 0.032267 # mshr miss rate for overall accesses |
| 500system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 100582.978723 # average ReadReq mshr miss latency 501system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 100582.978723 # average ReadReq mshr miss latency 502system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 100582.978723 # average overall mshr miss latency 503system.cpu.icache.demand_avg_mshr_miss_latency::total 100582.978723 # average overall mshr miss latency 504system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 100582.978723 # average overall mshr miss latency 505system.cpu.icache.overall_avg_mshr_miss_latency::total 100582.978723 # average overall mshr miss latency | 511system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 107059.574468 # average ReadReq mshr miss latency 512system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 107059.574468 # average ReadReq mshr miss latency 513system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 107059.574468 # average overall mshr miss latency 514system.cpu.icache.demand_avg_mshr_miss_latency::total 107059.574468 # average overall mshr miss latency 515system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 107059.574468 # average overall mshr miss latency 516system.cpu.icache.overall_avg_mshr_miss_latency::total 107059.574468 # average overall mshr miss latency |
| 506system.l2bus.snoop_filter.tot_requests 428 # Total number of requests made to the snoop filter. 507system.l2bus.snoop_filter.hit_single_requests 59 # Number of requests hitting in the snoop filter with a single holder of the requested data. 508system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 509system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 510system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 511system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 517system.l2bus.snoop_filter.tot_requests 428 # Total number of requests made to the snoop filter. 518system.l2bus.snoop_filter.hit_single_requests 59 # Number of requests hitting in the snoop filter with a single holder of the requested data. 519system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 520system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 521system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 522system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 512system.l2bus.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states | 523system.l2bus.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states |
| 513system.l2bus.trans_dist::ReadResp 291 # Transaction distribution 514system.l2bus.trans_dist::CleanEvict 58 # Transaction distribution 515system.l2bus.trans_dist::ReadExReq 79 # Transaction distribution 516system.l2bus.trans_dist::ReadExResp 79 # Transaction distribution 517system.l2bus.trans_dist::ReadSharedReq 291 # Transaction distribution 518system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 528 # Packet count per connected master and slave (bytes) 519system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) 520system.l2bus.pkt_count::total 798 # Packet count per connected master and slave (bytes) --- 9 unchanged lines hidden (view full) --- 530system.l2bus.snoop_fanout::0 369 99.73% 99.73% # Request fanout histogram 531system.l2bus.snoop_fanout::1 1 0.27% 100.00% # Request fanout histogram 532system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 533system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 534system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram 535system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 536system.l2bus.snoop_fanout::total 370 # Request fanout histogram 537system.l2bus.reqLayer0.occupancy 428000 # Layer occupancy (ticks) | 524system.l2bus.trans_dist::ReadResp 291 # Transaction distribution 525system.l2bus.trans_dist::CleanEvict 58 # Transaction distribution 526system.l2bus.trans_dist::ReadExReq 79 # Transaction distribution 527system.l2bus.trans_dist::ReadExResp 79 # Transaction distribution 528system.l2bus.trans_dist::ReadSharedReq 291 # Transaction distribution 529system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 528 # Packet count per connected master and slave (bytes) 530system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) 531system.l2bus.pkt_count::total 798 # Packet count per connected master and slave (bytes) --- 9 unchanged lines hidden (view full) --- 541system.l2bus.snoop_fanout::0 369 99.73% 99.73% # Request fanout histogram 542system.l2bus.snoop_fanout::1 1 0.27% 100.00% # Request fanout histogram 543system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 544system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 545system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram 546system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 547system.l2bus.snoop_fanout::total 370 # Request fanout histogram 548system.l2bus.reqLayer0.occupancy 428000 # Layer occupancy (ticks) |
| 538system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) | 549system.l2bus.reqLayer0.utilization 0.7 # Layer utilization (%) |
| 539system.l2bus.respLayer0.occupancy 705000 # Layer occupancy (ticks) 540system.l2bus.respLayer0.utilization 1.2 # Layer utilization (%) 541system.l2bus.respLayer1.occupancy 405000 # Layer occupancy (ticks) 542system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) | 550system.l2bus.respLayer0.occupancy 705000 # Layer occupancy (ticks) 551system.l2bus.respLayer0.utilization 1.2 # Layer utilization (%) 552system.l2bus.respLayer1.occupancy 405000 # Layer occupancy (ticks) 553system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) |
| 543system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states | 554system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states |
| 544system.l2cache.tags.replacements 0 # number of replacements | 555system.l2cache.tags.replacements 0 # number of replacements |
| 545system.l2cache.tags.tagsinuse 188.623694 # Cycle average of tags in use | 556system.l2cache.tags.tagsinuse 187.541609 # Cycle average of tags in use |
| 546system.l2cache.tags.total_refs 64 # Total number of references to valid blocks. 547system.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks. 548system.l2cache.tags.avg_refs 0.175824 # Average number of references to valid blocks. 549system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 557system.l2cache.tags.total_refs 64 # Total number of references to valid blocks. 558system.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks. 559system.l2cache.tags.avg_refs 0.175824 # Average number of references to valid blocks. 560system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 550system.l2cache.tags.occ_blocks::cpu.inst 106.912326 # Average occupied blocks per requestor 551system.l2cache.tags.occ_blocks::cpu.data 81.711368 # Average occupied blocks per requestor 552system.l2cache.tags.occ_percent::cpu.inst 0.026102 # Average percentage of cache occupancy 553system.l2cache.tags.occ_percent::cpu.data 0.019949 # Average percentage of cache occupancy 554system.l2cache.tags.occ_percent::total 0.046051 # Average percentage of cache occupancy | 561system.l2cache.tags.occ_blocks::cpu.inst 106.193515 # Average occupied blocks per requestor 562system.l2cache.tags.occ_blocks::cpu.data 81.348095 # Average occupied blocks per requestor 563system.l2cache.tags.occ_percent::cpu.inst 0.025926 # Average percentage of cache occupancy 564system.l2cache.tags.occ_percent::cpu.data 0.019860 # Average percentage of cache occupancy 565system.l2cache.tags.occ_percent::total 0.045787 # Average percentage of cache occupancy |
| 555system.l2cache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id 556system.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 557system.l2cache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id 558system.l2cache.tags.occ_task_id_percent::1024 0.088867 # Percentage of cache occupancy per task id 559system.l2cache.tags.tag_accesses 3788 # Number of tag accesses 560system.l2cache.tags.data_accesses 3788 # Number of data accesses | 566system.l2cache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id 567system.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 568system.l2cache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id 569system.l2cache.tags.occ_task_id_percent::1024 0.088867 # Percentage of cache occupancy per task id 570system.l2cache.tags.tag_accesses 3788 # Number of tag accesses 571system.l2cache.tags.data_accesses 3788 # Number of data accesses |
| 561system.l2cache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states | 572system.l2cache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states |
| 562system.l2cache.ReadSharedReq_hits::cpu.inst 6 # number of ReadSharedReq hits 563system.l2cache.ReadSharedReq_hits::total 6 # number of ReadSharedReq hits 564system.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits 565system.l2cache.demand_hits::total 6 # number of demand (read+write) hits 566system.l2cache.overall_hits::cpu.inst 6 # number of overall hits 567system.l2cache.overall_hits::total 6 # number of overall hits 568system.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses 569system.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses 570system.l2cache.ReadSharedReq_misses::cpu.inst 229 # number of ReadSharedReq misses 571system.l2cache.ReadSharedReq_misses::cpu.data 56 # number of ReadSharedReq misses 572system.l2cache.ReadSharedReq_misses::total 285 # number of ReadSharedReq misses 573system.l2cache.demand_misses::cpu.inst 229 # number of demand (read+write) misses 574system.l2cache.demand_misses::cpu.data 135 # number of demand (read+write) misses 575system.l2cache.demand_misses::total 364 # number of demand (read+write) misses 576system.l2cache.overall_misses::cpu.inst 229 # number of overall misses 577system.l2cache.overall_misses::cpu.data 135 # number of overall misses 578system.l2cache.overall_misses::total 364 # number of overall misses | 573system.l2cache.ReadSharedReq_hits::cpu.inst 6 # number of ReadSharedReq hits 574system.l2cache.ReadSharedReq_hits::total 6 # number of ReadSharedReq hits 575system.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits 576system.l2cache.demand_hits::total 6 # number of demand (read+write) hits 577system.l2cache.overall_hits::cpu.inst 6 # number of overall hits 578system.l2cache.overall_hits::total 6 # number of overall hits 579system.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses 580system.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses 581system.l2cache.ReadSharedReq_misses::cpu.inst 229 # number of ReadSharedReq misses 582system.l2cache.ReadSharedReq_misses::cpu.data 56 # number of ReadSharedReq misses 583system.l2cache.ReadSharedReq_misses::total 285 # number of ReadSharedReq misses 584system.l2cache.demand_misses::cpu.inst 229 # number of demand (read+write) misses 585system.l2cache.demand_misses::cpu.data 135 # number of demand (read+write) misses 586system.l2cache.demand_misses::total 364 # number of demand (read+write) misses 587system.l2cache.overall_misses::cpu.inst 229 # number of overall misses 588system.l2cache.overall_misses::cpu.data 135 # number of overall misses 589system.l2cache.overall_misses::total 364 # number of overall misses |
| 579system.l2cache.ReadExReq_miss_latency::cpu.data 7981000 # number of ReadExReq miss cycles 580system.l2cache.ReadExReq_miss_latency::total 7981000 # number of ReadExReq miss cycles 581system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22804000 # number of ReadSharedReq miss cycles 582system.l2cache.ReadSharedReq_miss_latency::cpu.data 5796000 # number of ReadSharedReq miss cycles 583system.l2cache.ReadSharedReq_miss_latency::total 28600000 # number of ReadSharedReq miss cycles 584system.l2cache.demand_miss_latency::cpu.inst 22804000 # number of demand (read+write) miss cycles 585system.l2cache.demand_miss_latency::cpu.data 13777000 # number of demand (read+write) miss cycles 586system.l2cache.demand_miss_latency::total 36581000 # number of demand (read+write) miss cycles 587system.l2cache.overall_miss_latency::cpu.inst 22804000 # number of overall miss cycles 588system.l2cache.overall_miss_latency::cpu.data 13777000 # number of overall miss cycles 589system.l2cache.overall_miss_latency::total 36581000 # number of overall miss cycles | 590system.l2cache.ReadExReq_miss_latency::cpu.data 8207000 # number of ReadExReq miss cycles 591system.l2cache.ReadExReq_miss_latency::total 8207000 # number of ReadExReq miss cycles 592system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24326000 # number of ReadSharedReq miss cycles 593system.l2cache.ReadSharedReq_miss_latency::cpu.data 6126000 # number of ReadSharedReq miss cycles 594system.l2cache.ReadSharedReq_miss_latency::total 30452000 # number of ReadSharedReq miss cycles 595system.l2cache.demand_miss_latency::cpu.inst 24326000 # number of demand (read+write) miss cycles 596system.l2cache.demand_miss_latency::cpu.data 14333000 # number of demand (read+write) miss cycles 597system.l2cache.demand_miss_latency::total 38659000 # number of demand (read+write) miss cycles 598system.l2cache.overall_miss_latency::cpu.inst 24326000 # number of overall miss cycles 599system.l2cache.overall_miss_latency::cpu.data 14333000 # number of overall miss cycles 600system.l2cache.overall_miss_latency::total 38659000 # number of overall miss cycles |
| 590system.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) 591system.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) 592system.l2cache.ReadSharedReq_accesses::cpu.inst 235 # number of ReadSharedReq accesses(hits+misses) 593system.l2cache.ReadSharedReq_accesses::cpu.data 56 # number of ReadSharedReq accesses(hits+misses) 594system.l2cache.ReadSharedReq_accesses::total 291 # number of ReadSharedReq accesses(hits+misses) 595system.l2cache.demand_accesses::cpu.inst 235 # number of demand (read+write) accesses 596system.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses 597system.l2cache.demand_accesses::total 370 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 604system.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 605system.l2cache.ReadSharedReq_miss_rate::total 0.979381 # miss rate for ReadSharedReq accesses 606system.l2cache.demand_miss_rate::cpu.inst 0.974468 # miss rate for demand accesses 607system.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 608system.l2cache.demand_miss_rate::total 0.983784 # miss rate for demand accesses 609system.l2cache.overall_miss_rate::cpu.inst 0.974468 # miss rate for overall accesses 610system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 611system.l2cache.overall_miss_rate::total 0.983784 # miss rate for overall accesses | 601system.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) 602system.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) 603system.l2cache.ReadSharedReq_accesses::cpu.inst 235 # number of ReadSharedReq accesses(hits+misses) 604system.l2cache.ReadSharedReq_accesses::cpu.data 56 # number of ReadSharedReq accesses(hits+misses) 605system.l2cache.ReadSharedReq_accesses::total 291 # number of ReadSharedReq accesses(hits+misses) 606system.l2cache.demand_accesses::cpu.inst 235 # number of demand (read+write) accesses 607system.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses 608system.l2cache.demand_accesses::total 370 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 615system.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 616system.l2cache.ReadSharedReq_miss_rate::total 0.979381 # miss rate for ReadSharedReq accesses 617system.l2cache.demand_miss_rate::cpu.inst 0.974468 # miss rate for demand accesses 618system.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 619system.l2cache.demand_miss_rate::total 0.983784 # miss rate for demand accesses 620system.l2cache.overall_miss_rate::cpu.inst 0.974468 # miss rate for overall accesses 621system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 622system.l2cache.overall_miss_rate::total 0.983784 # miss rate for overall accesses |
| 612system.l2cache.ReadExReq_avg_miss_latency::cpu.data 101025.316456 # average ReadExReq miss latency 613system.l2cache.ReadExReq_avg_miss_latency::total 101025.316456 # average ReadExReq miss latency 614system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 99580.786026 # average ReadSharedReq miss latency 615system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103500 # average ReadSharedReq miss latency 616system.l2cache.ReadSharedReq_avg_miss_latency::total 100350.877193 # average ReadSharedReq miss latency 617system.l2cache.demand_avg_miss_latency::cpu.inst 99580.786026 # average overall miss latency 618system.l2cache.demand_avg_miss_latency::cpu.data 102051.851852 # average overall miss latency 619system.l2cache.demand_avg_miss_latency::total 100497.252747 # average overall miss latency 620system.l2cache.overall_avg_miss_latency::cpu.inst 99580.786026 # average overall miss latency 621system.l2cache.overall_avg_miss_latency::cpu.data 102051.851852 # average overall miss latency 622system.l2cache.overall_avg_miss_latency::total 100497.252747 # average overall miss latency | 623system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103886.075949 # average ReadExReq miss latency 624system.l2cache.ReadExReq_avg_miss_latency::total 103886.075949 # average ReadExReq miss latency 625system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 106227.074236 # average ReadSharedReq miss latency 626system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 109392.857143 # average ReadSharedReq miss latency 627system.l2cache.ReadSharedReq_avg_miss_latency::total 106849.122807 # average ReadSharedReq miss latency 628system.l2cache.demand_avg_miss_latency::cpu.inst 106227.074236 # average overall miss latency 629system.l2cache.demand_avg_miss_latency::cpu.data 106170.370370 # average overall miss latency 630system.l2cache.demand_avg_miss_latency::total 106206.043956 # average overall miss latency 631system.l2cache.overall_avg_miss_latency::cpu.inst 106227.074236 # average overall miss latency 632system.l2cache.overall_avg_miss_latency::cpu.data 106170.370370 # average overall miss latency 633system.l2cache.overall_avg_miss_latency::total 106206.043956 # average overall miss latency |
| 623system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 624system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 625system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 626system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 627system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 628system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 629system.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses 630system.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses 631system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 229 # number of ReadSharedReq MSHR misses 632system.l2cache.ReadSharedReq_mshr_misses::cpu.data 56 # number of ReadSharedReq MSHR misses 633system.l2cache.ReadSharedReq_mshr_misses::total 285 # number of ReadSharedReq MSHR misses 634system.l2cache.demand_mshr_misses::cpu.inst 229 # number of demand (read+write) MSHR misses 635system.l2cache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses 636system.l2cache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses 637system.l2cache.overall_mshr_misses::cpu.inst 229 # number of overall MSHR misses 638system.l2cache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses 639system.l2cache.overall_mshr_misses::total 364 # number of overall MSHR misses | 634system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 635system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 636system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 637system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 638system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 639system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 640system.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses 641system.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses 642system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 229 # number of ReadSharedReq MSHR misses 643system.l2cache.ReadSharedReq_mshr_misses::cpu.data 56 # number of ReadSharedReq MSHR misses 644system.l2cache.ReadSharedReq_mshr_misses::total 285 # number of ReadSharedReq MSHR misses 645system.l2cache.demand_mshr_misses::cpu.inst 229 # number of demand (read+write) MSHR misses 646system.l2cache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses 647system.l2cache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses 648system.l2cache.overall_mshr_misses::cpu.inst 229 # number of overall MSHR misses 649system.l2cache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses 650system.l2cache.overall_mshr_misses::total 364 # number of overall MSHR misses |
| 640system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6401000 # number of ReadExReq MSHR miss cycles 641system.l2cache.ReadExReq_mshr_miss_latency::total 6401000 # number of ReadExReq MSHR miss cycles 642system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 18224000 # number of ReadSharedReq MSHR miss cycles 643system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4676000 # number of ReadSharedReq MSHR miss cycles 644system.l2cache.ReadSharedReq_mshr_miss_latency::total 22900000 # number of ReadSharedReq MSHR miss cycles 645system.l2cache.demand_mshr_miss_latency::cpu.inst 18224000 # number of demand (read+write) MSHR miss cycles 646system.l2cache.demand_mshr_miss_latency::cpu.data 11077000 # number of demand (read+write) MSHR miss cycles 647system.l2cache.demand_mshr_miss_latency::total 29301000 # number of demand (read+write) MSHR miss cycles 648system.l2cache.overall_mshr_miss_latency::cpu.inst 18224000 # number of overall MSHR miss cycles 649system.l2cache.overall_mshr_miss_latency::cpu.data 11077000 # number of overall MSHR miss cycles 650system.l2cache.overall_mshr_miss_latency::total 29301000 # number of overall MSHR miss cycles | 651system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6627000 # number of ReadExReq MSHR miss cycles 652system.l2cache.ReadExReq_mshr_miss_latency::total 6627000 # number of ReadExReq MSHR miss cycles 653system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19746000 # number of ReadSharedReq MSHR miss cycles 654system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5006000 # number of ReadSharedReq MSHR miss cycles 655system.l2cache.ReadSharedReq_mshr_miss_latency::total 24752000 # number of ReadSharedReq MSHR miss cycles 656system.l2cache.demand_mshr_miss_latency::cpu.inst 19746000 # number of demand (read+write) MSHR miss cycles 657system.l2cache.demand_mshr_miss_latency::cpu.data 11633000 # number of demand (read+write) MSHR miss cycles 658system.l2cache.demand_mshr_miss_latency::total 31379000 # number of demand (read+write) MSHR miss cycles 659system.l2cache.overall_mshr_miss_latency::cpu.inst 19746000 # number of overall MSHR miss cycles 660system.l2cache.overall_mshr_miss_latency::cpu.data 11633000 # number of overall MSHR miss cycles 661system.l2cache.overall_mshr_miss_latency::total 31379000 # number of overall MSHR miss cycles |
| 651system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 652system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 653system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for ReadSharedReq accesses 654system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 655system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.979381 # mshr miss rate for ReadSharedReq accesses 656system.l2cache.demand_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for demand accesses 657system.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 658system.l2cache.demand_mshr_miss_rate::total 0.983784 # mshr miss rate for demand accesses 659system.l2cache.overall_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for overall accesses 660system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 661system.l2cache.overall_mshr_miss_rate::total 0.983784 # mshr miss rate for overall accesses | 662system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 663system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 664system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for ReadSharedReq accesses 665system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 666system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.979381 # mshr miss rate for ReadSharedReq accesses 667system.l2cache.demand_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for demand accesses 668system.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 669system.l2cache.demand_mshr_miss_rate::total 0.983784 # mshr miss rate for demand accesses 670system.l2cache.overall_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for overall accesses 671system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 672system.l2cache.overall_mshr_miss_rate::total 0.983784 # mshr miss rate for overall accesses |
| 662system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81025.316456 # average ReadExReq mshr miss latency 663system.l2cache.ReadExReq_avg_mshr_miss_latency::total 81025.316456 # average ReadExReq mshr miss latency 664system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 79580.786026 # average ReadSharedReq mshr miss latency 665system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83500 # average ReadSharedReq mshr miss latency 666system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80350.877193 # average ReadSharedReq mshr miss latency 667system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79580.786026 # average overall mshr miss latency 668system.l2cache.demand_avg_mshr_miss_latency::cpu.data 82051.851852 # average overall mshr miss latency 669system.l2cache.demand_avg_mshr_miss_latency::total 80497.252747 # average overall mshr miss latency 670system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79580.786026 # average overall mshr miss latency 671system.l2cache.overall_avg_mshr_miss_latency::cpu.data 82051.851852 # average overall mshr miss latency 672system.l2cache.overall_avg_mshr_miss_latency::total 80497.252747 # average overall mshr miss latency | 673system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83886.075949 # average ReadExReq mshr miss latency 674system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83886.075949 # average ReadExReq mshr miss latency 675system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 86227.074236 # average ReadSharedReq mshr miss latency 676system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89392.857143 # average ReadSharedReq mshr miss latency 677system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 86849.122807 # average ReadSharedReq mshr miss latency 678system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 86227.074236 # average overall mshr miss latency 679system.l2cache.demand_avg_mshr_miss_latency::cpu.data 86170.370370 # average overall mshr miss latency 680system.l2cache.demand_avg_mshr_miss_latency::total 86206.043956 # average overall mshr miss latency 681system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 86227.074236 # average overall mshr miss latency 682system.l2cache.overall_avg_mshr_miss_latency::cpu.data 86170.370370 # average overall mshr miss latency 683system.l2cache.overall_avg_mshr_miss_latency::total 86206.043956 # average overall mshr miss latency |
| 673system.membus.snoop_filter.tot_requests 364 # Total number of requests made to the snoop filter. 674system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 675system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 676system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 677system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 678system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 684system.membus.snoop_filter.tot_requests 364 # Total number of requests made to the snoop filter. 685system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 686system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 687system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 688system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 689system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 679system.membus.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states | 690system.membus.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states |
| 680system.membus.trans_dist::ReadResp 285 # Transaction distribution 681system.membus.trans_dist::ReadExReq 79 # Transaction distribution 682system.membus.trans_dist::ReadExResp 79 # Transaction distribution 683system.membus.trans_dist::ReadSharedReq 285 # Transaction distribution 684system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 728 # Packet count per connected master and slave (bytes) 685system.membus.pkt_count_system.l2cache.mem_side::total 728 # Packet count per connected master and slave (bytes) 686system.membus.pkt_count::total 728 # Packet count per connected master and slave (bytes) 687system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 23296 # Cumulative packet size per connected master and slave (bytes) --- 8 unchanged lines hidden (view full) --- 696system.membus.snoop_fanout::0 364 100.00% 100.00% # Request fanout histogram 697system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 698system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 699system.membus.snoop_fanout::min_value 0 # Request fanout histogram 700system.membus.snoop_fanout::max_value 0 # Request fanout histogram 701system.membus.snoop_fanout::total 364 # Request fanout histogram 702system.membus.reqLayer2.occupancy 364000 # Layer occupancy (ticks) 703system.membus.reqLayer2.utilization 0.6 # Layer utilization (%) | 691system.membus.trans_dist::ReadResp 285 # Transaction distribution 692system.membus.trans_dist::ReadExReq 79 # Transaction distribution 693system.membus.trans_dist::ReadExResp 79 # Transaction distribution 694system.membus.trans_dist::ReadSharedReq 285 # Transaction distribution 695system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 728 # Packet count per connected master and slave (bytes) 696system.membus.pkt_count_system.l2cache.mem_side::total 728 # Packet count per connected master and slave (bytes) 697system.membus.pkt_count::total 728 # Packet count per connected master and slave (bytes) 698system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 23296 # Cumulative packet size per connected master and slave (bytes) --- 8 unchanged lines hidden (view full) --- 707system.membus.snoop_fanout::0 364 100.00% 100.00% # Request fanout histogram 708system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 709system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 710system.membus.snoop_fanout::min_value 0 # Request fanout histogram 711system.membus.snoop_fanout::max_value 0 # Request fanout histogram 712system.membus.snoop_fanout::total 364 # Request fanout histogram 713system.membus.reqLayer2.occupancy 364000 # Layer occupancy (ticks) 714system.membus.reqLayer2.utilization 0.6 # Layer utilization (%) |
| 704system.membus.respLayer0.occupancy 1954250 # Layer occupancy (ticks) 705system.membus.respLayer0.utilization 3.5 # Layer utilization (%) | 715system.membus.respLayer0.occupancy 1951250 # Layer occupancy (ticks) 716system.membus.respLayer0.utilization 3.3 # Layer utilization (%) |
| 706 707---------- End Simulation Statistics ---------- | 717 718---------- End Simulation Statistics ---------- |