| stats.txt (11502:e273e86a873d) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000056 # Number of seconds simulated 4sim_ticks 55844000 # Number of ticks simulated 5final_tick 55844000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000056 # Number of seconds simulated 4sim_ticks 55844000 # Number of ticks simulated 5final_tick 55844000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 299396 # Simulator instruction rate (inst/s) 8host_op_rate 540174 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2922543083 # Simulator tick rate (ticks/s) 10host_mem_usage 651308 # Number of bytes of host memory used | 7host_inst_rate 304150 # Simulator instruction rate (inst/s) 8host_op_rate 548931 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2970813002 # Simulator tick rate (ticks/s) 10host_mem_usage 696756 # Number of bytes of host memory used |
| 11host_seconds 0.02 # Real time elapsed on the host 12sim_insts 5712 # Number of instructions simulated 13sim_ops 10314 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 11host_seconds 0.02 # Real time elapsed on the host 12sim_insts 5712 # Number of instructions simulated 13sim_ops 10314 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states |
|
| 16system.mem_ctrl.bytes_read::cpu.inst 14656 # Number of bytes read from this memory 17system.mem_ctrl.bytes_read::cpu.data 8640 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::total 23296 # Number of bytes read from this memory 19system.mem_ctrl.bytes_inst_read::cpu.inst 14656 # Number of instructions bytes read from this memory 20system.mem_ctrl.bytes_inst_read::total 14656 # Number of instructions bytes read from this memory 21system.mem_ctrl.num_reads::cpu.inst 229 # Number of read requests responded to by this memory 22system.mem_ctrl.num_reads::cpu.data 135 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::total 364 # Number of read requests responded to by this memory --- 221 unchanged lines hidden (view full) --- 245system.mem_ctrl_1.preBackEnergy 1265250 # Energy for precharge background per rank (pJ) 246system.mem_ctrl_1.totalEnergy 43269765 # Total energy per rank (pJ) 247system.mem_ctrl_1.averagePower 790.116911 # Core power per rank (mW) 248system.mem_ctrl_1.memoryStateTime::IDLE 2847000 # Time in different power states 249system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states 250system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.mem_ctrl_1.memoryStateTime::ACT 51070000 # Time in different power states 252system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.mem_ctrl.bytes_read::cpu.inst 14656 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::cpu.data 8640 # Number of bytes read from this memory 19system.mem_ctrl.bytes_read::total 23296 # Number of bytes read from this memory 20system.mem_ctrl.bytes_inst_read::cpu.inst 14656 # Number of instructions bytes read from this memory 21system.mem_ctrl.bytes_inst_read::total 14656 # Number of instructions bytes read from this memory 22system.mem_ctrl.num_reads::cpu.inst 229 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::cpu.data 135 # Number of read requests responded to by this memory 24system.mem_ctrl.num_reads::total 364 # Number of read requests responded to by this memory --- 221 unchanged lines hidden (view full) --- 246system.mem_ctrl_1.preBackEnergy 1265250 # Energy for precharge background per rank (pJ) 247system.mem_ctrl_1.totalEnergy 43269765 # Total energy per rank (pJ) 248system.mem_ctrl_1.averagePower 790.116911 # Core power per rank (mW) 249system.mem_ctrl_1.memoryStateTime::IDLE 2847000 # Time in different power states 250system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states 251system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states 252system.mem_ctrl_1.memoryStateTime::ACT 51070000 # Time in different power states 253system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 254system.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states 255system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states |
|
| 253system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks | 256system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks |
| 257system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states 258system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states |
|
| 254system.cpu.workload.num_syscalls 11 # Number of system calls | 259system.cpu.workload.num_syscalls 11 # Number of system calls |
| 260system.cpu.pwrStateResidencyTicks::ON 55844000 # Cumulative time (in ticks) in various power states |
|
| 255system.cpu.numCycles 55844 # number of cpu cycles simulated 256system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 257system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 258system.cpu.committedInsts 5712 # Number of instructions committed 259system.cpu.committedOps 10314 # Number of ops (including micro ops) committed 260system.cpu.num_int_alu_accesses 10205 # Number of integer alu accesses 261system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 262system.cpu.num_func_calls 221 # number of times a function call or return occured --- 44 unchanged lines hidden (view full) --- 307system.cpu.op_class::SimdFloatMult 0 0.00% 80.37% # Class of executed instruction 308system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37% # Class of executed instruction 309system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37% # Class of executed instruction 310system.cpu.op_class::MemRead 1084 10.51% 90.88% # Class of executed instruction 311system.cpu.op_class::MemWrite 941 9.12% 100.00% # Class of executed instruction 312system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 313system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 314system.cpu.op_class::total 10314 # Class of executed instruction | 261system.cpu.numCycles 55844 # number of cpu cycles simulated 262system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 263system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 264system.cpu.committedInsts 5712 # Number of instructions committed 265system.cpu.committedOps 10314 # Number of ops (including micro ops) committed 266system.cpu.num_int_alu_accesses 10205 # Number of integer alu accesses 267system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 268system.cpu.num_func_calls 221 # number of times a function call or return occured --- 44 unchanged lines hidden (view full) --- 313system.cpu.op_class::SimdFloatMult 0 0.00% 80.37% # Class of executed instruction 314system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37% # Class of executed instruction 315system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37% # Class of executed instruction 316system.cpu.op_class::MemRead 1084 10.51% 90.88% # Class of executed instruction 317system.cpu.op_class::MemWrite 941 9.12% 100.00% # Class of executed instruction 318system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 319system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 320system.cpu.op_class::total 10314 # Class of executed instruction |
| 321system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states |
|
| 315system.cpu.dcache.tags.replacements 0 # number of replacements 316system.cpu.dcache.tags.tagsinuse 81.671640 # Cycle average of tags in use 317system.cpu.dcache.tags.total_refs 1890 # Total number of references to valid blocks. 318system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. 319system.cpu.dcache.tags.avg_refs 14 # Average number of references to valid blocks. 320system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 321system.cpu.dcache.tags.occ_blocks::cpu.data 81.671640 # Average occupied blocks per requestor 322system.cpu.dcache.tags.occ_percent::cpu.data 0.079757 # Average percentage of cache occupancy 323system.cpu.dcache.tags.occ_percent::total 0.079757 # Average percentage of cache occupancy 324system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id 325system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id 326system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id 327system.cpu.dcache.tags.occ_task_id_percent::1024 0.131836 # Percentage of cache occupancy per task id 328system.cpu.dcache.tags.tag_accesses 4185 # Number of tag accesses 329system.cpu.dcache.tags.data_accesses 4185 # Number of data accesses | 322system.cpu.dcache.tags.replacements 0 # number of replacements 323system.cpu.dcache.tags.tagsinuse 81.671640 # Cycle average of tags in use 324system.cpu.dcache.tags.total_refs 1890 # Total number of references to valid blocks. 325system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. 326system.cpu.dcache.tags.avg_refs 14 # Average number of references to valid blocks. 327system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 328system.cpu.dcache.tags.occ_blocks::cpu.data 81.671640 # Average occupied blocks per requestor 329system.cpu.dcache.tags.occ_percent::cpu.data 0.079757 # Average percentage of cache occupancy 330system.cpu.dcache.tags.occ_percent::total 0.079757 # Average percentage of cache occupancy 331system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id 332system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id 333system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id 334system.cpu.dcache.tags.occ_task_id_percent::1024 0.131836 # Percentage of cache occupancy per task id 335system.cpu.dcache.tags.tag_accesses 4185 # Number of tag accesses 336system.cpu.dcache.tags.data_accesses 4185 # Number of data accesses |
| 337system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states |
|
| 330system.cpu.dcache.ReadReq_hits::cpu.data 1028 # number of ReadReq hits 331system.cpu.dcache.ReadReq_hits::total 1028 # number of ReadReq hits 332system.cpu.dcache.WriteReq_hits::cpu.data 862 # number of WriteReq hits 333system.cpu.dcache.WriteReq_hits::total 862 # number of WriteReq hits 334system.cpu.dcache.demand_hits::cpu.data 1890 # number of demand (read+write) hits 335system.cpu.dcache.demand_hits::total 1890 # number of demand (read+write) hits 336system.cpu.dcache.overall_hits::cpu.data 1890 # number of overall hits 337system.cpu.dcache.overall_hits::total 1890 # number of overall hits --- 70 unchanged lines hidden (view full) --- 408system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 105250 # average ReadReq mshr miss latency 409system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 105250 # average ReadReq mshr miss latency 410system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102556.962025 # average WriteReq mshr miss latency 411system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102556.962025 # average WriteReq mshr miss latency 412system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency 413system.cpu.dcache.demand_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency 414system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency 415system.cpu.dcache.overall_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency | 338system.cpu.dcache.ReadReq_hits::cpu.data 1028 # number of ReadReq hits 339system.cpu.dcache.ReadReq_hits::total 1028 # number of ReadReq hits 340system.cpu.dcache.WriteReq_hits::cpu.data 862 # number of WriteReq hits 341system.cpu.dcache.WriteReq_hits::total 862 # number of WriteReq hits 342system.cpu.dcache.demand_hits::cpu.data 1890 # number of demand (read+write) hits 343system.cpu.dcache.demand_hits::total 1890 # number of demand (read+write) hits 344system.cpu.dcache.overall_hits::cpu.data 1890 # number of overall hits 345system.cpu.dcache.overall_hits::total 1890 # number of overall hits --- 70 unchanged lines hidden (view full) --- 416system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 105250 # average ReadReq mshr miss latency 417system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 105250 # average ReadReq mshr miss latency 418system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102556.962025 # average WriteReq mshr miss latency 419system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102556.962025 # average WriteReq mshr miss latency 420system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency 421system.cpu.dcache.demand_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency 422system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency 423system.cpu.dcache.overall_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency |
| 424system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states |
|
| 416system.cpu.icache.tags.replacements 58 # number of replacements 417system.cpu.icache.tags.tagsinuse 91.239705 # Cycle average of tags in use 418system.cpu.icache.tags.total_refs 7048 # Total number of references to valid blocks. 419system.cpu.icache.tags.sampled_refs 235 # Sample count of references to valid blocks. 420system.cpu.icache.tags.avg_refs 29.991489 # Average number of references to valid blocks. 421system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 422system.cpu.icache.tags.occ_blocks::cpu.inst 91.239705 # Average occupied blocks per requestor 423system.cpu.icache.tags.occ_percent::cpu.inst 0.356405 # Average percentage of cache occupancy 424system.cpu.icache.tags.occ_percent::total 0.356405 # Average percentage of cache occupancy 425system.cpu.icache.tags.occ_task_id_blocks::1024 177 # Occupied blocks per task id 426system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 427system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id 428system.cpu.icache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id 429system.cpu.icache.tags.tag_accesses 14801 # Number of tag accesses 430system.cpu.icache.tags.data_accesses 14801 # Number of data accesses | 425system.cpu.icache.tags.replacements 58 # number of replacements 426system.cpu.icache.tags.tagsinuse 91.239705 # Cycle average of tags in use 427system.cpu.icache.tags.total_refs 7048 # Total number of references to valid blocks. 428system.cpu.icache.tags.sampled_refs 235 # Sample count of references to valid blocks. 429system.cpu.icache.tags.avg_refs 29.991489 # Average number of references to valid blocks. 430system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 431system.cpu.icache.tags.occ_blocks::cpu.inst 91.239705 # Average occupied blocks per requestor 432system.cpu.icache.tags.occ_percent::cpu.inst 0.356405 # Average percentage of cache occupancy 433system.cpu.icache.tags.occ_percent::total 0.356405 # Average percentage of cache occupancy 434system.cpu.icache.tags.occ_task_id_blocks::1024 177 # Occupied blocks per task id 435system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 436system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id 437system.cpu.icache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id 438system.cpu.icache.tags.tag_accesses 14801 # Number of tag accesses 439system.cpu.icache.tags.data_accesses 14801 # Number of data accesses |
| 440system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states |
|
| 431system.cpu.icache.ReadReq_hits::cpu.inst 7048 # number of ReadReq hits 432system.cpu.icache.ReadReq_hits::total 7048 # number of ReadReq hits 433system.cpu.icache.demand_hits::cpu.inst 7048 # number of demand (read+write) hits 434system.cpu.icache.demand_hits::total 7048 # number of demand (read+write) hits 435system.cpu.icache.overall_hits::cpu.inst 7048 # number of overall hits 436system.cpu.icache.overall_hits::total 7048 # number of overall hits 437system.cpu.icache.ReadReq_misses::cpu.inst 235 # number of ReadReq misses 438system.cpu.icache.ReadReq_misses::total 235 # number of ReadReq misses --- 56 unchanged lines hidden (view full) --- 495system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency 496system.cpu.icache.overall_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency 497system.l2bus.snoop_filter.tot_requests 428 # Total number of requests made to the snoop filter. 498system.l2bus.snoop_filter.hit_single_requests 59 # Number of requests hitting in the snoop filter with a single holder of the requested data. 499system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 500system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 501system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 502system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 441system.cpu.icache.ReadReq_hits::cpu.inst 7048 # number of ReadReq hits 442system.cpu.icache.ReadReq_hits::total 7048 # number of ReadReq hits 443system.cpu.icache.demand_hits::cpu.inst 7048 # number of demand (read+write) hits 444system.cpu.icache.demand_hits::total 7048 # number of demand (read+write) hits 445system.cpu.icache.overall_hits::cpu.inst 7048 # number of overall hits 446system.cpu.icache.overall_hits::total 7048 # number of overall hits 447system.cpu.icache.ReadReq_misses::cpu.inst 235 # number of ReadReq misses 448system.cpu.icache.ReadReq_misses::total 235 # number of ReadReq misses --- 56 unchanged lines hidden (view full) --- 505system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency 506system.cpu.icache.overall_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency 507system.l2bus.snoop_filter.tot_requests 428 # Total number of requests made to the snoop filter. 508system.l2bus.snoop_filter.hit_single_requests 59 # Number of requests hitting in the snoop filter with a single holder of the requested data. 509system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 510system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 511system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 512system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 513system.l2bus.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states |
|
| 503system.l2bus.trans_dist::ReadResp 291 # Transaction distribution 504system.l2bus.trans_dist::CleanEvict 58 # Transaction distribution 505system.l2bus.trans_dist::ReadExReq 79 # Transaction distribution 506system.l2bus.trans_dist::ReadExResp 79 # Transaction distribution 507system.l2bus.trans_dist::ReadSharedReq 291 # Transaction distribution 508system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 528 # Packet count per connected master and slave (bytes) 509system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) 510system.l2bus.pkt_count::total 798 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 524system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 525system.l2bus.snoop_fanout::total 370 # Request fanout histogram 526system.l2bus.reqLayer0.occupancy 428000 # Layer occupancy (ticks) 527system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) 528system.l2bus.respLayer0.occupancy 705000 # Layer occupancy (ticks) 529system.l2bus.respLayer0.utilization 1.3 # Layer utilization (%) 530system.l2bus.respLayer1.occupancy 405000 # Layer occupancy (ticks) 531system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) | 514system.l2bus.trans_dist::ReadResp 291 # Transaction distribution 515system.l2bus.trans_dist::CleanEvict 58 # Transaction distribution 516system.l2bus.trans_dist::ReadExReq 79 # Transaction distribution 517system.l2bus.trans_dist::ReadExResp 79 # Transaction distribution 518system.l2bus.trans_dist::ReadSharedReq 291 # Transaction distribution 519system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 528 # Packet count per connected master and slave (bytes) 520system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) 521system.l2bus.pkt_count::total 798 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 535system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 536system.l2bus.snoop_fanout::total 370 # Request fanout histogram 537system.l2bus.reqLayer0.occupancy 428000 # Layer occupancy (ticks) 538system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) 539system.l2bus.respLayer0.occupancy 705000 # Layer occupancy (ticks) 540system.l2bus.respLayer0.utilization 1.3 # Layer utilization (%) 541system.l2bus.respLayer1.occupancy 405000 # Layer occupancy (ticks) 542system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) |
| 543system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states |
|
| 532system.l2cache.tags.replacements 0 # number of replacements 533system.l2cache.tags.tagsinuse 135.848259 # Cycle average of tags in use 534system.l2cache.tags.total_refs 64 # Total number of references to valid blocks. 535system.l2cache.tags.sampled_refs 285 # Sample count of references to valid blocks. 536system.l2cache.tags.avg_refs 0.224561 # Average number of references to valid blocks. 537system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 538system.l2cache.tags.occ_blocks::cpu.inst 106.898398 # Average occupied blocks per requestor 539system.l2cache.tags.occ_blocks::cpu.data 28.949861 # Average occupied blocks per requestor 540system.l2cache.tags.occ_percent::cpu.inst 0.026098 # Average percentage of cache occupancy 541system.l2cache.tags.occ_percent::cpu.data 0.007068 # Average percentage of cache occupancy 542system.l2cache.tags.occ_percent::total 0.033166 # Average percentage of cache occupancy 543system.l2cache.tags.occ_task_id_blocks::1024 285 # Occupied blocks per task id 544system.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 545system.l2cache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id 546system.l2cache.tags.occ_task_id_percent::1024 0.069580 # Percentage of cache occupancy per task id 547system.l2cache.tags.tag_accesses 3788 # Number of tag accesses 548system.l2cache.tags.data_accesses 3788 # Number of data accesses | 544system.l2cache.tags.replacements 0 # number of replacements 545system.l2cache.tags.tagsinuse 135.848259 # Cycle average of tags in use 546system.l2cache.tags.total_refs 64 # Total number of references to valid blocks. 547system.l2cache.tags.sampled_refs 285 # Sample count of references to valid blocks. 548system.l2cache.tags.avg_refs 0.224561 # Average number of references to valid blocks. 549system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 550system.l2cache.tags.occ_blocks::cpu.inst 106.898398 # Average occupied blocks per requestor 551system.l2cache.tags.occ_blocks::cpu.data 28.949861 # Average occupied blocks per requestor 552system.l2cache.tags.occ_percent::cpu.inst 0.026098 # Average percentage of cache occupancy 553system.l2cache.tags.occ_percent::cpu.data 0.007068 # Average percentage of cache occupancy 554system.l2cache.tags.occ_percent::total 0.033166 # Average percentage of cache occupancy 555system.l2cache.tags.occ_task_id_blocks::1024 285 # Occupied blocks per task id 556system.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 557system.l2cache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id 558system.l2cache.tags.occ_task_id_percent::1024 0.069580 # Percentage of cache occupancy per task id 559system.l2cache.tags.tag_accesses 3788 # Number of tag accesses 560system.l2cache.tags.data_accesses 3788 # Number of data accesses |
| 561system.l2cache.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states |
|
| 549system.l2cache.ReadSharedReq_hits::cpu.inst 6 # number of ReadSharedReq hits 550system.l2cache.ReadSharedReq_hits::total 6 # number of ReadSharedReq hits 551system.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits 552system.l2cache.demand_hits::total 6 # number of demand (read+write) hits 553system.l2cache.overall_hits::cpu.inst 6 # number of overall hits 554system.l2cache.overall_hits::total 6 # number of overall hits 555system.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses 556system.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses --- 95 unchanged lines hidden (view full) --- 652system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82250 # average ReadSharedReq mshr miss latency 653system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78684.210526 # average ReadSharedReq mshr miss latency 654system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency 655system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency 656system.l2cache.demand_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency 657system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency 658system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency 659system.l2cache.overall_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency | 562system.l2cache.ReadSharedReq_hits::cpu.inst 6 # number of ReadSharedReq hits 563system.l2cache.ReadSharedReq_hits::total 6 # number of ReadSharedReq hits 564system.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits 565system.l2cache.demand_hits::total 6 # number of demand (read+write) hits 566system.l2cache.overall_hits::cpu.inst 6 # number of overall hits 567system.l2cache.overall_hits::total 6 # number of overall hits 568system.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses 569system.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses --- 95 unchanged lines hidden (view full) --- 665system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82250 # average ReadSharedReq mshr miss latency 666system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78684.210526 # average ReadSharedReq mshr miss latency 667system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency 668system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency 669system.l2cache.demand_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency 670system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency 671system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency 672system.l2cache.overall_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency |
| 673system.membus.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states |
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| 660system.membus.trans_dist::ReadResp 285 # Transaction distribution 661system.membus.trans_dist::ReadExReq 79 # Transaction distribution 662system.membus.trans_dist::ReadExResp 79 # Transaction distribution 663system.membus.trans_dist::ReadSharedReq 285 # Transaction distribution 664system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 728 # Packet count per connected master and slave (bytes) 665system.membus.pkt_count_system.l2cache.mem_side::total 728 # Packet count per connected master and slave (bytes) 666system.membus.pkt_count::total 728 # Packet count per connected master and slave (bytes) 667system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 23296 # Cumulative packet size per connected master and slave (bytes) --- 19 unchanged lines hidden --- | 674system.membus.trans_dist::ReadResp 285 # Transaction distribution 675system.membus.trans_dist::ReadExReq 79 # Transaction distribution 676system.membus.trans_dist::ReadExResp 79 # Transaction distribution 677system.membus.trans_dist::ReadSharedReq 285 # Transaction distribution 678system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 728 # Packet count per connected master and slave (bytes) 679system.membus.pkt_count_system.l2cache.mem_side::total 728 # Packet count per connected master and slave (bytes) 680system.membus.pkt_count::total 728 # Packet count per connected master and slave (bytes) 681system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 23296 # Cumulative packet size per connected master and slave (bytes) --- 19 unchanged lines hidden --- |