| stats.txt (11312:3d7a85d71bd1) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000056 # Number of seconds simulated 4sim_ticks 55844000 # Number of ticks simulated 5final_tick 55844000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000056 # Number of seconds simulated 4sim_ticks 55844000 # Number of ticks simulated 5final_tick 55844000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 84620 # Simulator instruction rate (inst/s) 8host_op_rate 152747 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 826790083 # Simulator tick rate (ticks/s) 10host_mem_usage 634592 # Number of bytes of host memory used 11host_seconds 0.07 # Real time elapsed on the host | 7host_inst_rate 250477 # Simulator instruction rate (inst/s) 8host_op_rate 451948 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2445398371 # Simulator tick rate (ticks/s) 10host_mem_usage 655164 # Number of bytes of host memory used 11host_seconds 0.02 # Real time elapsed on the host |
| 12sim_insts 5712 # Number of instructions simulated 13sim_ops 10314 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.mem_ctrl.bytes_read::cpu.inst 14656 # Number of bytes read from this memory 17system.mem_ctrl.bytes_read::cpu.data 8640 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::total 23296 # Number of bytes read from this memory 19system.mem_ctrl.bytes_inst_read::cpu.inst 14656 # Number of instructions bytes read from this memory --- 356 unchanged lines hidden (view full) --- 376system.cpu.dcache.overall_avg_miss_latency::cpu.data 105674.074074 # average overall miss latency 377system.cpu.dcache.overall_avg_miss_latency::total 105674.074074 # average overall miss latency 378system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 379system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 380system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 381system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 382system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 383system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 5712 # Number of instructions simulated 13sim_ops 10314 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.mem_ctrl.bytes_read::cpu.inst 14656 # Number of bytes read from this memory 17system.mem_ctrl.bytes_read::cpu.data 8640 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::total 23296 # Number of bytes read from this memory 19system.mem_ctrl.bytes_inst_read::cpu.inst 14656 # Number of instructions bytes read from this memory --- 356 unchanged lines hidden (view full) --- 376system.cpu.dcache.overall_avg_miss_latency::cpu.data 105674.074074 # average overall miss latency 377system.cpu.dcache.overall_avg_miss_latency::total 105674.074074 # average overall miss latency 378system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 379system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 380system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 381system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 382system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 383system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 384system.cpu.dcache.fast_writes 0 # number of fast writes performed 385system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 386system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses 387system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses 388system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses 389system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses 390system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses 391system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses 392system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses 393system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses --- 16 unchanged lines hidden (view full) --- 410system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 105250 # average ReadReq mshr miss latency 411system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 105250 # average ReadReq mshr miss latency 412system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102556.962025 # average WriteReq mshr miss latency 413system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102556.962025 # average WriteReq mshr miss latency 414system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency 415system.cpu.dcache.demand_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency 416system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency 417system.cpu.dcache.overall_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency | 384system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses 385system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses 386system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses 387system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses 388system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses 389system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses 390system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses 391system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses --- 16 unchanged lines hidden (view full) --- 408system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 105250 # average ReadReq mshr miss latency 409system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 105250 # average ReadReq mshr miss latency 410system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102556.962025 # average WriteReq mshr miss latency 411system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102556.962025 # average WriteReq mshr miss latency 412system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency 413system.cpu.dcache.demand_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency 414system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency 415system.cpu.dcache.overall_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency |
| 418system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 419system.cpu.icache.tags.replacements 58 # number of replacements 420system.cpu.icache.tags.tagsinuse 91.239705 # Cycle average of tags in use 421system.cpu.icache.tags.total_refs 7048 # Total number of references to valid blocks. 422system.cpu.icache.tags.sampled_refs 235 # Sample count of references to valid blocks. 423system.cpu.icache.tags.avg_refs 29.991489 # Average number of references to valid blocks. 424system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 425system.cpu.icache.tags.occ_blocks::cpu.inst 91.239705 # Average occupied blocks per requestor 426system.cpu.icache.tags.occ_percent::cpu.inst 0.356405 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 468system.cpu.icache.overall_avg_miss_latency::cpu.inst 100859.574468 # average overall miss latency 469system.cpu.icache.overall_avg_miss_latency::total 100859.574468 # average overall miss latency 470system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 471system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 472system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 473system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 474system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 475system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 416system.cpu.icache.tags.replacements 58 # number of replacements 417system.cpu.icache.tags.tagsinuse 91.239705 # Cycle average of tags in use 418system.cpu.icache.tags.total_refs 7048 # Total number of references to valid blocks. 419system.cpu.icache.tags.sampled_refs 235 # Sample count of references to valid blocks. 420system.cpu.icache.tags.avg_refs 29.991489 # Average number of references to valid blocks. 421system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 422system.cpu.icache.tags.occ_blocks::cpu.inst 91.239705 # Average occupied blocks per requestor 423system.cpu.icache.tags.occ_percent::cpu.inst 0.356405 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 465system.cpu.icache.overall_avg_miss_latency::cpu.inst 100859.574468 # average overall miss latency 466system.cpu.icache.overall_avg_miss_latency::total 100859.574468 # average overall miss latency 467system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 468system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 469system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 470system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 471system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 472system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 476system.cpu.icache.fast_writes 0 # number of fast writes performed 477system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 478system.cpu.icache.ReadReq_mshr_misses::cpu.inst 235 # number of ReadReq MSHR misses 479system.cpu.icache.ReadReq_mshr_misses::total 235 # number of ReadReq MSHR misses 480system.cpu.icache.demand_mshr_misses::cpu.inst 235 # number of demand (read+write) MSHR misses 481system.cpu.icache.demand_mshr_misses::total 235 # number of demand (read+write) MSHR misses 482system.cpu.icache.overall_mshr_misses::cpu.inst 235 # number of overall MSHR misses 483system.cpu.icache.overall_mshr_misses::total 235 # number of overall MSHR misses 484system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23232000 # number of ReadReq MSHR miss cycles 485system.cpu.icache.ReadReq_mshr_miss_latency::total 23232000 # number of ReadReq MSHR miss cycles --- 8 unchanged lines hidden (view full) --- 494system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for overall accesses 495system.cpu.icache.overall_mshr_miss_rate::total 0.032267 # mshr miss rate for overall accesses 496system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98859.574468 # average ReadReq mshr miss latency 497system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98859.574468 # average ReadReq mshr miss latency 498system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency 499system.cpu.icache.demand_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency 500system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency 501system.cpu.icache.overall_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency | 473system.cpu.icache.ReadReq_mshr_misses::cpu.inst 235 # number of ReadReq MSHR misses 474system.cpu.icache.ReadReq_mshr_misses::total 235 # number of ReadReq MSHR misses 475system.cpu.icache.demand_mshr_misses::cpu.inst 235 # number of demand (read+write) MSHR misses 476system.cpu.icache.demand_mshr_misses::total 235 # number of demand (read+write) MSHR misses 477system.cpu.icache.overall_mshr_misses::cpu.inst 235 # number of overall MSHR misses 478system.cpu.icache.overall_mshr_misses::total 235 # number of overall MSHR misses 479system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23232000 # number of ReadReq MSHR miss cycles 480system.cpu.icache.ReadReq_mshr_miss_latency::total 23232000 # number of ReadReq MSHR miss cycles --- 8 unchanged lines hidden (view full) --- 489system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for overall accesses 490system.cpu.icache.overall_mshr_miss_rate::total 0.032267 # mshr miss rate for overall accesses 491system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98859.574468 # average ReadReq mshr miss latency 492system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98859.574468 # average ReadReq mshr miss latency 493system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency 494system.cpu.icache.demand_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency 495system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency 496system.cpu.icache.overall_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency |
| 502system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 503system.l2bus.snoop_filter.tot_requests 428 # Total number of requests made to the snoop filter. 504system.l2bus.snoop_filter.hit_single_requests 59 # Number of requests hitting in the snoop filter with a single holder of the requested data. 505system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 506system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 507system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 508system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 509system.l2bus.trans_dist::ReadResp 291 # Transaction distribution 510system.l2bus.trans_dist::CleanEvict 58 # Transaction distribution --- 103 unchanged lines hidden (view full) --- 614system.l2cache.overall_avg_miss_latency::cpu.data 100674.074074 # average overall miss latency 615system.l2cache.overall_avg_miss_latency::total 98873.626374 # average overall miss latency 616system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 617system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 618system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 619system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 620system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 621system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 497system.l2bus.snoop_filter.tot_requests 428 # Total number of requests made to the snoop filter. 498system.l2bus.snoop_filter.hit_single_requests 59 # Number of requests hitting in the snoop filter with a single holder of the requested data. 499system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 500system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 501system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 502system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 503system.l2bus.trans_dist::ReadResp 291 # Transaction distribution 504system.l2bus.trans_dist::CleanEvict 58 # Transaction distribution --- 103 unchanged lines hidden (view full) --- 608system.l2cache.overall_avg_miss_latency::cpu.data 100674.074074 # average overall miss latency 609system.l2cache.overall_avg_miss_latency::total 98873.626374 # average overall miss latency 610system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 611system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 612system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 613system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 614system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 615system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 622system.l2cache.fast_writes 0 # number of fast writes performed 623system.l2cache.cache_copies 0 # number of cache copies performed | |
| 624system.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses 625system.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses 626system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 229 # number of ReadSharedReq MSHR misses 627system.l2cache.ReadSharedReq_mshr_misses::cpu.data 56 # number of ReadSharedReq MSHR misses 628system.l2cache.ReadSharedReq_mshr_misses::total 285 # number of ReadSharedReq MSHR misses 629system.l2cache.demand_mshr_misses::cpu.inst 229 # number of demand (read+write) MSHR misses 630system.l2cache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses 631system.l2cache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses --- 28 unchanged lines hidden (view full) --- 660system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82250 # average ReadSharedReq mshr miss latency 661system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78684.210526 # average ReadSharedReq mshr miss latency 662system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency 663system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency 664system.l2cache.demand_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency 665system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency 666system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency 667system.l2cache.overall_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency | 616system.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses 617system.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses 618system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 229 # number of ReadSharedReq MSHR misses 619system.l2cache.ReadSharedReq_mshr_misses::cpu.data 56 # number of ReadSharedReq MSHR misses 620system.l2cache.ReadSharedReq_mshr_misses::total 285 # number of ReadSharedReq MSHR misses 621system.l2cache.demand_mshr_misses::cpu.inst 229 # number of demand (read+write) MSHR misses 622system.l2cache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses 623system.l2cache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses --- 28 unchanged lines hidden (view full) --- 652system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82250 # average ReadSharedReq mshr miss latency 653system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78684.210526 # average ReadSharedReq mshr miss latency 654system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency 655system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency 656system.l2cache.demand_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency 657system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency 658system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency 659system.l2cache.overall_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency |
| 668system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 669system.membus.trans_dist::ReadResp 285 # Transaction distribution 670system.membus.trans_dist::ReadExReq 79 # Transaction distribution 671system.membus.trans_dist::ReadExResp 79 # Transaction distribution 672system.membus.trans_dist::ReadSharedReq 285 # Transaction distribution 673system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 728 # Packet count per connected master and slave (bytes) 674system.membus.pkt_count_system.l2cache.mem_side::total 728 # Packet count per connected master and slave (bytes) 675system.membus.pkt_count::total 728 # Packet count per connected master and slave (bytes) 676system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 23296 # Cumulative packet size per connected master and slave (bytes) --- 19 unchanged lines hidden --- | 660system.membus.trans_dist::ReadResp 285 # Transaction distribution 661system.membus.trans_dist::ReadExReq 79 # Transaction distribution 662system.membus.trans_dist::ReadExResp 79 # Transaction distribution 663system.membus.trans_dist::ReadSharedReq 285 # Transaction distribution 664system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 728 # Packet count per connected master and slave (bytes) 665system.membus.pkt_count_system.l2cache.mem_side::total 728 # Packet count per connected master and slave (bytes) 666system.membus.pkt_count::total 728 # Packet count per connected master and slave (bytes) 667system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 23296 # Cumulative packet size per connected master and slave (bytes) --- 19 unchanged lines hidden --- |