| stats.txt (11106:878dd30741c4) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000056 # Number of seconds simulated 4sim_ticks 55844000 # Number of ticks simulated 5final_tick 55844000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000056 # Number of seconds simulated 4sim_ticks 55844000 # Number of ticks simulated 5final_tick 55844000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 212931 # Simulator instruction rate (inst/s) 8host_op_rate 384017 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2076955895 # Simulator tick rate (ticks/s) 10host_mem_usage 693340 # Number of bytes of host memory used 11host_seconds 0.03 # Real time elapsed on the host | 7host_inst_rate 284010 # Simulator instruction rate (inst/s) 8host_op_rate 512497 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2773065846 # Simulator tick rate (ticks/s) 10host_mem_usage 698700 # Number of bytes of host memory used 11host_seconds 0.02 # Real time elapsed on the host |
| 12sim_insts 5712 # Number of instructions simulated 13sim_ops 10314 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.mem_ctrl.bytes_read::cpu.inst 14656 # Number of bytes read from this memory 17system.mem_ctrl.bytes_read::cpu.data 8640 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::total 23296 # Number of bytes read from this memory 19system.mem_ctrl.bytes_inst_read::cpu.inst 14656 # Number of instructions bytes read from this memory --- 175 unchanged lines hidden (view full) --- 195system.mem_ctrl.bytesPerActivate::256-383 16 13.91% 86.09% # Bytes accessed per row activation 196system.mem_ctrl.bytesPerActivate::384-511 6 5.22% 91.30% # Bytes accessed per row activation 197system.mem_ctrl.bytesPerActivate::512-639 2 1.74% 93.04% # Bytes accessed per row activation 198system.mem_ctrl.bytesPerActivate::640-767 2 1.74% 94.78% # Bytes accessed per row activation 199system.mem_ctrl.bytesPerActivate::768-895 2 1.74% 96.52% # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::896-1023 1 0.87% 97.39% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::1024-1151 3 2.61% 100.00% # Bytes accessed per row activation 202system.mem_ctrl.bytesPerActivate::total 115 # Bytes accessed per row activation | 12sim_insts 5712 # Number of instructions simulated 13sim_ops 10314 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.mem_ctrl.bytes_read::cpu.inst 14656 # Number of bytes read from this memory 17system.mem_ctrl.bytes_read::cpu.data 8640 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::total 23296 # Number of bytes read from this memory 19system.mem_ctrl.bytes_inst_read::cpu.inst 14656 # Number of instructions bytes read from this memory --- 175 unchanged lines hidden (view full) --- 195system.mem_ctrl.bytesPerActivate::256-383 16 13.91% 86.09% # Bytes accessed per row activation 196system.mem_ctrl.bytesPerActivate::384-511 6 5.22% 91.30% # Bytes accessed per row activation 197system.mem_ctrl.bytesPerActivate::512-639 2 1.74% 93.04% # Bytes accessed per row activation 198system.mem_ctrl.bytesPerActivate::640-767 2 1.74% 94.78% # Bytes accessed per row activation 199system.mem_ctrl.bytesPerActivate::768-895 2 1.74% 96.52% # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::896-1023 1 0.87% 97.39% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::1024-1151 3 2.61% 100.00% # Bytes accessed per row activation 202system.mem_ctrl.bytesPerActivate::total 115 # Bytes accessed per row activation |
| 203system.mem_ctrl.totQLat 3554250 # Total ticks spent queuing 204system.mem_ctrl.totMemAccLat 10379250 # Total ticks spent from burst creation until serviced by the DRAM | 203system.mem_ctrl.totQLat 3552250 # Total ticks spent queuing 204system.mem_ctrl.totMemAccLat 10377250 # Total ticks spent from burst creation until serviced by the DRAM |
| 205system.mem_ctrl.totBusLat 1820000 # Total ticks spent in databus transfers | 205system.mem_ctrl.totBusLat 1820000 # Total ticks spent in databus transfers |
| 206system.mem_ctrl.avgQLat 9764.42 # Average queueing delay per DRAM burst | 206system.mem_ctrl.avgQLat 9758.93 # Average queueing delay per DRAM burst |
| 207system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 208system.mem_ctrl.avgMemAccLat 28514.42 # Average memory access latency per DRAM burst | 208system.mem_ctrl.avgMemAccLat 28508.93 # Average memory access latency per DRAM burst |
| 209system.mem_ctrl.avgRdBW 417.16 # Average DRAM read bandwidth in MiByte/s 210system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.mem_ctrl.avgRdBWSys 417.16 # Average system read bandwidth in MiByte/s 212system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.mem_ctrl.busUtil 3.26 # Data bus utilization in percentage 215system.mem_ctrl.busUtilRead 3.26 # Data bus utilization in percentage for reads 216system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 91 unchanged lines hidden (view full) --- 308system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37% # Class of executed instruction 309system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37% # Class of executed instruction 310system.cpu.op_class::MemRead 1084 10.51% 90.88% # Class of executed instruction 311system.cpu.op_class::MemWrite 941 9.12% 100.00% # Class of executed instruction 312system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 313system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 314system.cpu.op_class::total 10314 # Class of executed instruction 315system.cpu.dcache.tags.replacements 0 # number of replacements | 209system.mem_ctrl.avgRdBW 417.16 # Average DRAM read bandwidth in MiByte/s 210system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.mem_ctrl.avgRdBWSys 417.16 # Average system read bandwidth in MiByte/s 212system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.mem_ctrl.busUtil 3.26 # Data bus utilization in percentage 215system.mem_ctrl.busUtilRead 3.26 # Data bus utilization in percentage for reads 216system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 91 unchanged lines hidden (view full) --- 308system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37% # Class of executed instruction 309system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37% # Class of executed instruction 310system.cpu.op_class::MemRead 1084 10.51% 90.88% # Class of executed instruction 311system.cpu.op_class::MemWrite 941 9.12% 100.00% # Class of executed instruction 312system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 313system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 314system.cpu.op_class::total 10314 # Class of executed instruction 315system.cpu.dcache.tags.replacements 0 # number of replacements |
| 316system.cpu.dcache.tags.tagsinuse 81.671962 # Cycle average of tags in use | 316system.cpu.dcache.tags.tagsinuse 81.671640 # Cycle average of tags in use |
| 317system.cpu.dcache.tags.total_refs 1890 # Total number of references to valid blocks. 318system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. 319system.cpu.dcache.tags.avg_refs 14 # Average number of references to valid blocks. 320system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 317system.cpu.dcache.tags.total_refs 1890 # Total number of references to valid blocks. 318system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. 319system.cpu.dcache.tags.avg_refs 14 # Average number of references to valid blocks. 320system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 321system.cpu.dcache.tags.occ_blocks::cpu.data 81.671962 # Average occupied blocks per requestor 322system.cpu.dcache.tags.occ_percent::cpu.data 0.079758 # Average percentage of cache occupancy 323system.cpu.dcache.tags.occ_percent::total 0.079758 # Average percentage of cache occupancy | 321system.cpu.dcache.tags.occ_blocks::cpu.data 81.671640 # Average occupied blocks per requestor 322system.cpu.dcache.tags.occ_percent::cpu.data 0.079757 # Average percentage of cache occupancy 323system.cpu.dcache.tags.occ_percent::total 0.079757 # Average percentage of cache occupancy |
| 324system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id 325system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id 326system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id 327system.cpu.dcache.tags.occ_task_id_percent::1024 0.131836 # Percentage of cache occupancy per task id 328system.cpu.dcache.tags.tag_accesses 4185 # Number of tag accesses 329system.cpu.dcache.tags.data_accesses 4185 # Number of data accesses 330system.cpu.dcache.ReadReq_hits::cpu.data 1028 # number of ReadReq hits 331system.cpu.dcache.ReadReq_hits::total 1028 # number of ReadReq hits --- 80 unchanged lines hidden (view full) --- 412system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102556.962025 # average WriteReq mshr miss latency 413system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102556.962025 # average WriteReq mshr miss latency 414system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency 415system.cpu.dcache.demand_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency 416system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency 417system.cpu.dcache.overall_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency 418system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 419system.cpu.icache.tags.replacements 58 # number of replacements | 324system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id 325system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id 326system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id 327system.cpu.dcache.tags.occ_task_id_percent::1024 0.131836 # Percentage of cache occupancy per task id 328system.cpu.dcache.tags.tag_accesses 4185 # Number of tag accesses 329system.cpu.dcache.tags.data_accesses 4185 # Number of data accesses 330system.cpu.dcache.ReadReq_hits::cpu.data 1028 # number of ReadReq hits 331system.cpu.dcache.ReadReq_hits::total 1028 # number of ReadReq hits --- 80 unchanged lines hidden (view full) --- 412system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102556.962025 # average WriteReq mshr miss latency 413system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102556.962025 # average WriteReq mshr miss latency 414system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency 415system.cpu.dcache.demand_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency 416system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency 417system.cpu.dcache.overall_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency 418system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 419system.cpu.icache.tags.replacements 58 # number of replacements |
| 420system.cpu.icache.tags.tagsinuse 91.240171 # Cycle average of tags in use | 420system.cpu.icache.tags.tagsinuse 91.239705 # Cycle average of tags in use |
| 421system.cpu.icache.tags.total_refs 7048 # Total number of references to valid blocks. 422system.cpu.icache.tags.sampled_refs 235 # Sample count of references to valid blocks. 423system.cpu.icache.tags.avg_refs 29.991489 # Average number of references to valid blocks. 424system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 421system.cpu.icache.tags.total_refs 7048 # Total number of references to valid blocks. 422system.cpu.icache.tags.sampled_refs 235 # Sample count of references to valid blocks. 423system.cpu.icache.tags.avg_refs 29.991489 # Average number of references to valid blocks. 424system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 425system.cpu.icache.tags.occ_blocks::cpu.inst 91.240171 # Average occupied blocks per requestor 426system.cpu.icache.tags.occ_percent::cpu.inst 0.356407 # Average percentage of cache occupancy 427system.cpu.icache.tags.occ_percent::total 0.356407 # Average percentage of cache occupancy | 425system.cpu.icache.tags.occ_blocks::cpu.inst 91.239705 # Average occupied blocks per requestor 426system.cpu.icache.tags.occ_percent::cpu.inst 0.356405 # Average percentage of cache occupancy 427system.cpu.icache.tags.occ_percent::total 0.356405 # Average percentage of cache occupancy |
| 428system.cpu.icache.tags.occ_task_id_blocks::1024 177 # Occupied blocks per task id 429system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 430system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id 431system.cpu.icache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id 432system.cpu.icache.tags.tag_accesses 14801 # Number of tag accesses 433system.cpu.icache.tags.data_accesses 14801 # Number of data accesses 434system.cpu.icache.ReadReq_hits::cpu.inst 7048 # number of ReadReq hits 435system.cpu.icache.ReadReq_hits::total 7048 # number of ReadReq hits --- 59 unchanged lines hidden (view full) --- 495system.cpu.icache.overall_mshr_miss_rate::total 0.032267 # mshr miss rate for overall accesses 496system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98859.574468 # average ReadReq mshr miss latency 497system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98859.574468 # average ReadReq mshr miss latency 498system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency 499system.cpu.icache.demand_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency 500system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency 501system.cpu.icache.overall_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency 502system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 428system.cpu.icache.tags.occ_task_id_blocks::1024 177 # Occupied blocks per task id 429system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 430system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id 431system.cpu.icache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id 432system.cpu.icache.tags.tag_accesses 14801 # Number of tag accesses 433system.cpu.icache.tags.data_accesses 14801 # Number of data accesses 434system.cpu.icache.ReadReq_hits::cpu.inst 7048 # number of ReadReq hits 435system.cpu.icache.ReadReq_hits::total 7048 # number of ReadReq hits --- 59 unchanged lines hidden (view full) --- 495system.cpu.icache.overall_mshr_miss_rate::total 0.032267 # mshr miss rate for overall accesses 496system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98859.574468 # average ReadReq mshr miss latency 497system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98859.574468 # average ReadReq mshr miss latency 498system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency 499system.cpu.icache.demand_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency 500system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency 501system.cpu.icache.overall_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency 502system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 503system.l2bus.snoop_filter.tot_requests 428 # Total number of requests made to the snoop filter. 504system.l2bus.snoop_filter.hit_single_requests 59 # Number of requests hitting in the snoop filter with a single holder of the requested data. 505system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 506system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 507system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 508system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
|
| 503system.l2bus.trans_dist::ReadResp 291 # Transaction distribution 504system.l2bus.trans_dist::CleanEvict 58 # Transaction distribution 505system.l2bus.trans_dist::ReadExReq 79 # Transaction distribution 506system.l2bus.trans_dist::ReadExResp 79 # Transaction distribution 507system.l2bus.trans_dist::ReadSharedReq 291 # Transaction distribution 508system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 528 # Packet count per connected master and slave (bytes) 509system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) 510system.l2bus.pkt_count::total 798 # Packet count per connected master and slave (bytes) 511system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 15040 # Cumulative packet size per connected master and slave (bytes) 512system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) 513system.l2bus.pkt_size::total 23680 # Cumulative packet size per connected master and slave (bytes) 514system.l2bus.snoops 0 # Total snoops (count) 515system.l2bus.snoop_fanout::samples 428 # Request fanout histogram | 509system.l2bus.trans_dist::ReadResp 291 # Transaction distribution 510system.l2bus.trans_dist::CleanEvict 58 # Transaction distribution 511system.l2bus.trans_dist::ReadExReq 79 # Transaction distribution 512system.l2bus.trans_dist::ReadExResp 79 # Transaction distribution 513system.l2bus.trans_dist::ReadSharedReq 291 # Transaction distribution 514system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 528 # Packet count per connected master and slave (bytes) 515system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) 516system.l2bus.pkt_count::total 798 # Packet count per connected master and slave (bytes) 517system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 15040 # Cumulative packet size per connected master and slave (bytes) 518system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) 519system.l2bus.pkt_size::total 23680 # Cumulative packet size per connected master and slave (bytes) 520system.l2bus.snoops 0 # Total snoops (count) 521system.l2bus.snoop_fanout::samples 428 # Request fanout histogram |
| 516system.l2bus.snoop_fanout::mean 1 # Request fanout histogram 517system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram | 522system.l2bus.snoop_fanout::mean 0.002336 # Request fanout histogram 523system.l2bus.snoop_fanout::stdev 0.048337 # Request fanout histogram |
| 518system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 524system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 519system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 520system.l2bus.snoop_fanout::1 428 100.00% 100.00% # Request fanout histogram | 525system.l2bus.snoop_fanout::0 427 99.77% 99.77% # Request fanout histogram 526system.l2bus.snoop_fanout::1 1 0.23% 100.00% # Request fanout histogram |
| 521system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 522system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 527system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 528system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 523system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram | 529system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram |
| 524system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 525system.l2bus.snoop_fanout::total 428 # Request fanout histogram 526system.l2bus.reqLayer0.occupancy 428000 # Layer occupancy (ticks) 527system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) 528system.l2bus.respLayer0.occupancy 705000 # Layer occupancy (ticks) 529system.l2bus.respLayer0.utilization 1.3 # Layer utilization (%) 530system.l2bus.respLayer1.occupancy 405000 # Layer occupancy (ticks) 531system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) 532system.l2cache.tags.replacements 0 # number of replacements | 530system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 531system.l2bus.snoop_fanout::total 428 # Request fanout histogram 532system.l2bus.reqLayer0.occupancy 428000 # Layer occupancy (ticks) 533system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) 534system.l2bus.respLayer0.occupancy 705000 # Layer occupancy (ticks) 535system.l2bus.respLayer0.utilization 1.3 # Layer utilization (%) 536system.l2bus.respLayer1.occupancy 405000 # Layer occupancy (ticks) 537system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) 538system.l2cache.tags.replacements 0 # number of replacements |
| 533system.l2cache.tags.tagsinuse 135.849297 # Cycle average of tags in use | 539system.l2cache.tags.tagsinuse 135.848259 # Cycle average of tags in use |
| 534system.l2cache.tags.total_refs 64 # Total number of references to valid blocks. 535system.l2cache.tags.sampled_refs 285 # Sample count of references to valid blocks. 536system.l2cache.tags.avg_refs 0.224561 # Average number of references to valid blocks. 537system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 540system.l2cache.tags.total_refs 64 # Total number of references to valid blocks. 541system.l2cache.tags.sampled_refs 285 # Sample count of references to valid blocks. 542system.l2cache.tags.avg_refs 0.224561 # Average number of references to valid blocks. 543system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 538system.l2cache.tags.occ_blocks::cpu.inst 106.899114 # Average occupied blocks per requestor 539system.l2cache.tags.occ_blocks::cpu.data 28.950183 # Average occupied blocks per requestor | 544system.l2cache.tags.occ_blocks::cpu.inst 106.898398 # Average occupied blocks per requestor 545system.l2cache.tags.occ_blocks::cpu.data 28.949861 # Average occupied blocks per requestor |
| 540system.l2cache.tags.occ_percent::cpu.inst 0.026098 # Average percentage of cache occupancy 541system.l2cache.tags.occ_percent::cpu.data 0.007068 # Average percentage of cache occupancy 542system.l2cache.tags.occ_percent::total 0.033166 # Average percentage of cache occupancy 543system.l2cache.tags.occ_task_id_blocks::1024 285 # Occupied blocks per task id 544system.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 545system.l2cache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id 546system.l2cache.tags.occ_task_id_percent::1024 0.069580 # Percentage of cache occupancy per task id 547system.l2cache.tags.tag_accesses 3788 # Number of tag accesses --- 12 unchanged lines hidden (view full) --- 560system.l2cache.demand_misses::cpu.inst 229 # number of demand (read+write) misses 561system.l2cache.demand_misses::cpu.data 135 # number of demand (read+write) misses 562system.l2cache.demand_misses::total 364 # number of demand (read+write) misses 563system.l2cache.overall_misses::cpu.inst 229 # number of overall misses 564system.l2cache.overall_misses::cpu.data 135 # number of overall misses 565system.l2cache.overall_misses::total 364 # number of overall misses 566system.l2cache.ReadExReq_miss_latency::cpu.data 7865000 # number of ReadExReq miss cycles 567system.l2cache.ReadExReq_miss_latency::total 7865000 # number of ReadExReq miss cycles | 546system.l2cache.tags.occ_percent::cpu.inst 0.026098 # Average percentage of cache occupancy 547system.l2cache.tags.occ_percent::cpu.data 0.007068 # Average percentage of cache occupancy 548system.l2cache.tags.occ_percent::total 0.033166 # Average percentage of cache occupancy 549system.l2cache.tags.occ_task_id_blocks::1024 285 # Occupied blocks per task id 550system.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 551system.l2cache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id 552system.l2cache.tags.occ_task_id_percent::1024 0.069580 # Percentage of cache occupancy per task id 553system.l2cache.tags.tag_accesses 3788 # Number of tag accesses --- 12 unchanged lines hidden (view full) --- 566system.l2cache.demand_misses::cpu.inst 229 # number of demand (read+write) misses 567system.l2cache.demand_misses::cpu.data 135 # number of demand (read+write) misses 568system.l2cache.demand_misses::total 364 # number of demand (read+write) misses 569system.l2cache.overall_misses::cpu.inst 229 # number of overall misses 570system.l2cache.overall_misses::cpu.data 135 # number of overall misses 571system.l2cache.overall_misses::total 364 # number of overall misses 572system.l2cache.ReadExReq_miss_latency::cpu.data 7865000 # number of ReadExReq miss cycles 573system.l2cache.ReadExReq_miss_latency::total 7865000 # number of ReadExReq miss cycles |
| 568system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22401000 # number of ReadSharedReq miss cycles | 574system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22399000 # number of ReadSharedReq miss cycles |
| 569system.l2cache.ReadSharedReq_miss_latency::cpu.data 5726000 # number of ReadSharedReq miss cycles | 575system.l2cache.ReadSharedReq_miss_latency::cpu.data 5726000 # number of ReadSharedReq miss cycles |
| 570system.l2cache.ReadSharedReq_miss_latency::total 28127000 # number of ReadSharedReq miss cycles 571system.l2cache.demand_miss_latency::cpu.inst 22401000 # number of demand (read+write) miss cycles | 576system.l2cache.ReadSharedReq_miss_latency::total 28125000 # number of ReadSharedReq miss cycles 577system.l2cache.demand_miss_latency::cpu.inst 22399000 # number of demand (read+write) miss cycles |
| 572system.l2cache.demand_miss_latency::cpu.data 13591000 # number of demand (read+write) miss cycles | 578system.l2cache.demand_miss_latency::cpu.data 13591000 # number of demand (read+write) miss cycles |
| 573system.l2cache.demand_miss_latency::total 35992000 # number of demand (read+write) miss cycles 574system.l2cache.overall_miss_latency::cpu.inst 22401000 # number of overall miss cycles | 579system.l2cache.demand_miss_latency::total 35990000 # number of demand (read+write) miss cycles 580system.l2cache.overall_miss_latency::cpu.inst 22399000 # number of overall miss cycles |
| 575system.l2cache.overall_miss_latency::cpu.data 13591000 # number of overall miss cycles | 581system.l2cache.overall_miss_latency::cpu.data 13591000 # number of overall miss cycles |
| 576system.l2cache.overall_miss_latency::total 35992000 # number of overall miss cycles | 582system.l2cache.overall_miss_latency::total 35990000 # number of overall miss cycles |
| 577system.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) 578system.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) 579system.l2cache.ReadSharedReq_accesses::cpu.inst 235 # number of ReadSharedReq accesses(hits+misses) 580system.l2cache.ReadSharedReq_accesses::cpu.data 56 # number of ReadSharedReq accesses(hits+misses) 581system.l2cache.ReadSharedReq_accesses::total 291 # number of ReadSharedReq accesses(hits+misses) 582system.l2cache.demand_accesses::cpu.inst 235 # number of demand (read+write) accesses 583system.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses 584system.l2cache.demand_accesses::total 370 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 593system.l2cache.demand_miss_rate::cpu.inst 0.974468 # miss rate for demand accesses 594system.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 595system.l2cache.demand_miss_rate::total 0.983784 # miss rate for demand accesses 596system.l2cache.overall_miss_rate::cpu.inst 0.974468 # miss rate for overall accesses 597system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 598system.l2cache.overall_miss_rate::total 0.983784 # miss rate for overall accesses 599system.l2cache.ReadExReq_avg_miss_latency::cpu.data 99556.962025 # average ReadExReq miss latency 600system.l2cache.ReadExReq_avg_miss_latency::total 99556.962025 # average ReadExReq miss latency | 583system.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) 584system.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) 585system.l2cache.ReadSharedReq_accesses::cpu.inst 235 # number of ReadSharedReq accesses(hits+misses) 586system.l2cache.ReadSharedReq_accesses::cpu.data 56 # number of ReadSharedReq accesses(hits+misses) 587system.l2cache.ReadSharedReq_accesses::total 291 # number of ReadSharedReq accesses(hits+misses) 588system.l2cache.demand_accesses::cpu.inst 235 # number of demand (read+write) accesses 589system.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses 590system.l2cache.demand_accesses::total 370 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 599system.l2cache.demand_miss_rate::cpu.inst 0.974468 # miss rate for demand accesses 600system.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 601system.l2cache.demand_miss_rate::total 0.983784 # miss rate for demand accesses 602system.l2cache.overall_miss_rate::cpu.inst 0.974468 # miss rate for overall accesses 603system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 604system.l2cache.overall_miss_rate::total 0.983784 # miss rate for overall accesses 605system.l2cache.ReadExReq_avg_miss_latency::cpu.data 99556.962025 # average ReadExReq miss latency 606system.l2cache.ReadExReq_avg_miss_latency::total 99556.962025 # average ReadExReq miss latency |
| 601system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97820.960699 # average ReadSharedReq miss latency | 607system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97812.227074 # average ReadSharedReq miss latency |
| 602system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102250 # average ReadSharedReq miss latency | 608system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102250 # average ReadSharedReq miss latency |
| 603system.l2cache.ReadSharedReq_avg_miss_latency::total 98691.228070 # average ReadSharedReq miss latency 604system.l2cache.demand_avg_miss_latency::cpu.inst 97820.960699 # average overall miss latency | 609system.l2cache.ReadSharedReq_avg_miss_latency::total 98684.210526 # average ReadSharedReq miss latency 610system.l2cache.demand_avg_miss_latency::cpu.inst 97812.227074 # average overall miss latency |
| 605system.l2cache.demand_avg_miss_latency::cpu.data 100674.074074 # average overall miss latency | 611system.l2cache.demand_avg_miss_latency::cpu.data 100674.074074 # average overall miss latency |
| 606system.l2cache.demand_avg_miss_latency::total 98879.120879 # average overall miss latency 607system.l2cache.overall_avg_miss_latency::cpu.inst 97820.960699 # average overall miss latency | 612system.l2cache.demand_avg_miss_latency::total 98873.626374 # average overall miss latency 613system.l2cache.overall_avg_miss_latency::cpu.inst 97812.227074 # average overall miss latency |
| 608system.l2cache.overall_avg_miss_latency::cpu.data 100674.074074 # average overall miss latency | 614system.l2cache.overall_avg_miss_latency::cpu.data 100674.074074 # average overall miss latency |
| 609system.l2cache.overall_avg_miss_latency::total 98879.120879 # average overall miss latency | 615system.l2cache.overall_avg_miss_latency::total 98873.626374 # average overall miss latency |
| 610system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 611system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 612system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 613system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 614system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 615system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 616system.l2cache.fast_writes 0 # number of fast writes performed 617system.l2cache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 623system.l2cache.demand_mshr_misses::cpu.inst 229 # number of demand (read+write) MSHR misses 624system.l2cache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses 625system.l2cache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses 626system.l2cache.overall_mshr_misses::cpu.inst 229 # number of overall MSHR misses 627system.l2cache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses 628system.l2cache.overall_mshr_misses::total 364 # number of overall MSHR misses 629system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6285000 # number of ReadExReq MSHR miss cycles 630system.l2cache.ReadExReq_mshr_miss_latency::total 6285000 # number of ReadExReq MSHR miss cycles | 616system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 617system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 618system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 619system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 620system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 621system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 622system.l2cache.fast_writes 0 # number of fast writes performed 623system.l2cache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 629system.l2cache.demand_mshr_misses::cpu.inst 229 # number of demand (read+write) MSHR misses 630system.l2cache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses 631system.l2cache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses 632system.l2cache.overall_mshr_misses::cpu.inst 229 # number of overall MSHR misses 633system.l2cache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses 634system.l2cache.overall_mshr_misses::total 364 # number of overall MSHR misses 635system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6285000 # number of ReadExReq MSHR miss cycles 636system.l2cache.ReadExReq_mshr_miss_latency::total 6285000 # number of ReadExReq MSHR miss cycles |
| 631system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17821000 # number of ReadSharedReq MSHR miss cycles | 637system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17819000 # number of ReadSharedReq MSHR miss cycles |
| 632system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4606000 # number of ReadSharedReq MSHR miss cycles | 638system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4606000 # number of ReadSharedReq MSHR miss cycles |
| 633system.l2cache.ReadSharedReq_mshr_miss_latency::total 22427000 # number of ReadSharedReq MSHR miss cycles 634system.l2cache.demand_mshr_miss_latency::cpu.inst 17821000 # number of demand (read+write) MSHR miss cycles | 639system.l2cache.ReadSharedReq_mshr_miss_latency::total 22425000 # number of ReadSharedReq MSHR miss cycles 640system.l2cache.demand_mshr_miss_latency::cpu.inst 17819000 # number of demand (read+write) MSHR miss cycles |
| 635system.l2cache.demand_mshr_miss_latency::cpu.data 10891000 # number of demand (read+write) MSHR miss cycles | 641system.l2cache.demand_mshr_miss_latency::cpu.data 10891000 # number of demand (read+write) MSHR miss cycles |
| 636system.l2cache.demand_mshr_miss_latency::total 28712000 # number of demand (read+write) MSHR miss cycles 637system.l2cache.overall_mshr_miss_latency::cpu.inst 17821000 # number of overall MSHR miss cycles | 642system.l2cache.demand_mshr_miss_latency::total 28710000 # number of demand (read+write) MSHR miss cycles 643system.l2cache.overall_mshr_miss_latency::cpu.inst 17819000 # number of overall MSHR miss cycles |
| 638system.l2cache.overall_mshr_miss_latency::cpu.data 10891000 # number of overall MSHR miss cycles | 644system.l2cache.overall_mshr_miss_latency::cpu.data 10891000 # number of overall MSHR miss cycles |
| 639system.l2cache.overall_mshr_miss_latency::total 28712000 # number of overall MSHR miss cycles | 645system.l2cache.overall_mshr_miss_latency::total 28710000 # number of overall MSHR miss cycles |
| 640system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 641system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 642system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for ReadSharedReq accesses 643system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 644system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.979381 # mshr miss rate for ReadSharedReq accesses 645system.l2cache.demand_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for demand accesses 646system.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 647system.l2cache.demand_mshr_miss_rate::total 0.983784 # mshr miss rate for demand accesses 648system.l2cache.overall_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for overall accesses 649system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 650system.l2cache.overall_mshr_miss_rate::total 0.983784 # mshr miss rate for overall accesses 651system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79556.962025 # average ReadExReq mshr miss latency 652system.l2cache.ReadExReq_avg_mshr_miss_latency::total 79556.962025 # average ReadExReq mshr miss latency | 646system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 647system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 648system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for ReadSharedReq accesses 649system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 650system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.979381 # mshr miss rate for ReadSharedReq accesses 651system.l2cache.demand_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for demand accesses 652system.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 653system.l2cache.demand_mshr_miss_rate::total 0.983784 # mshr miss rate for demand accesses 654system.l2cache.overall_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for overall accesses 655system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 656system.l2cache.overall_mshr_miss_rate::total 0.983784 # mshr miss rate for overall accesses 657system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79556.962025 # average ReadExReq mshr miss latency 658system.l2cache.ReadExReq_avg_mshr_miss_latency::total 79556.962025 # average ReadExReq mshr miss latency |
| 653system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77820.960699 # average ReadSharedReq mshr miss latency | 659system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77812.227074 # average ReadSharedReq mshr miss latency |
| 654system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82250 # average ReadSharedReq mshr miss latency | 660system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82250 # average ReadSharedReq mshr miss latency |
| 655system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78691.228070 # average ReadSharedReq mshr miss latency 656system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77820.960699 # average overall mshr miss latency | 661system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78684.210526 # average ReadSharedReq mshr miss latency 662system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency |
| 657system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency | 663system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency |
| 658system.l2cache.demand_avg_mshr_miss_latency::total 78879.120879 # average overall mshr miss latency 659system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77820.960699 # average overall mshr miss latency | 664system.l2cache.demand_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency 665system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency |
| 660system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency | 666system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency |
| 661system.l2cache.overall_avg_mshr_miss_latency::total 78879.120879 # average overall mshr miss latency | 667system.l2cache.overall_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency |
| 662system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 663system.membus.trans_dist::ReadResp 285 # Transaction distribution 664system.membus.trans_dist::ReadExReq 79 # Transaction distribution 665system.membus.trans_dist::ReadExResp 79 # Transaction distribution 666system.membus.trans_dist::ReadSharedReq 285 # Transaction distribution 667system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 728 # Packet count per connected master and slave (bytes) 668system.membus.pkt_count_system.l2cache.mem_side::total 728 # Packet count per connected master and slave (bytes) 669system.membus.pkt_count::total 728 # Packet count per connected master and slave (bytes) --- 20 unchanged lines hidden --- | 668system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 669system.membus.trans_dist::ReadResp 285 # Transaction distribution 670system.membus.trans_dist::ReadExReq 79 # Transaction distribution 671system.membus.trans_dist::ReadExResp 79 # Transaction distribution 672system.membus.trans_dist::ReadSharedReq 285 # Transaction distribution 673system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 728 # Packet count per connected master and slave (bytes) 674system.membus.pkt_count_system.l2cache.mem_side::total 728 # Packet count per connected master and slave (bytes) 675system.membus.pkt_count::total 728 # Packet count per connected master and slave (bytes) --- 20 unchanged lines hidden --- |