3,5c3,5
< sim_seconds 0.000056 # Number of seconds simulated
< sim_ticks 56435000 # Number of ticks simulated
< final_tick 56435000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000059 # Number of seconds simulated
> sim_ticks 58513000 # Number of ticks simulated
> final_tick 58513000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 125605 # Simulator instruction rate (inst/s)
< host_op_rate 226732 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1240265940 # Simulator tick rate (ticks/s)
< host_mem_usage 656384 # Number of bytes of host memory used
< host_seconds 0.05 # Real time elapsed on the host
---
> host_inst_rate 325988 # Simulator instruction rate (inst/s)
> host_op_rate 588251 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 3335289412 # Simulator tick rate (ticks/s)
> host_mem_usage 654560 # Number of bytes of host memory used
> host_seconds 0.02 # Real time elapsed on the host
16c16
< system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
---
> system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.mem_ctrl.bw_read::cpu.inst 259696997 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::cpu.data 153096483 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::total 412793479 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::cpu.inst 259696997 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::total 259696997 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.inst 259696997 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.data 153096483 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::total 412793479 # Total bandwidth to/from this memory (bytes/s)
---
> system.mem_ctrl.bw_read::cpu.inst 250474254 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::cpu.data 147659494 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::total 398133748 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::cpu.inst 250474254 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::total 250474254 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.inst 250474254 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.data 147659494 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::total 398133748 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.mem_ctrl.totGap 56304000 # Total gap between requests
---
> system.mem_ctrl.totGap 58376000 # Total gap between requests
190,204c190,205
< system.mem_ctrl.bytesPerActivate::samples 117 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::mean 193.094017 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::gmean 128.926887 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::stdev 215.889898 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::0-127 57 48.72% 48.72% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::128-255 28 23.93% 72.65% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::256-383 16 13.68% 86.32% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::384-511 6 5.13% 91.45% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::512-639 2 1.71% 93.16% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::640-767 2 1.71% 94.87% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::768-895 3 2.56% 97.44% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::1024-1151 3 2.56% 100.00% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::total 117 # Bytes accessed per row activation
< system.mem_ctrl.totQLat 3777750 # Total ticks spent queuing
< system.mem_ctrl.totMemAccLat 10602750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.mem_ctrl.bytesPerActivate::samples 108 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::mean 199.703704 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::gmean 135.091179 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::stdev 199.282229 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::0-127 52 48.15% 48.15% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::128-255 21 19.44% 67.59% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::256-383 15 13.89% 81.48% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::384-511 8 7.41% 88.89% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::512-639 7 6.48% 95.37% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::640-767 2 1.85% 97.22% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::768-895 1 0.93% 98.15% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::896-1023 1 0.93% 99.07% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::1024-1151 1 0.93% 100.00% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::total 108 # Bytes accessed per row activation
> system.mem_ctrl.totQLat 5858750 # Total ticks spent queuing
> system.mem_ctrl.totMemAccLat 12683750 # Total ticks spent from burst creation until serviced by the DRAM
206c207
< system.mem_ctrl.avgQLat 10378.43 # Average queueing delay per DRAM burst
---
> system.mem_ctrl.avgQLat 16095.47 # Average queueing delay per DRAM burst
208,209c209,210
< system.mem_ctrl.avgMemAccLat 29128.43 # Average memory access latency per DRAM burst
< system.mem_ctrl.avgRdBW 412.79 # Average DRAM read bandwidth in MiByte/s
---
> system.mem_ctrl.avgMemAccLat 34845.47 # Average memory access latency per DRAM burst
> system.mem_ctrl.avgRdBW 398.13 # Average DRAM read bandwidth in MiByte/s
211c212
< system.mem_ctrl.avgRdBWSys 412.79 # Average system read bandwidth in MiByte/s
---
> system.mem_ctrl.avgRdBWSys 398.13 # Average system read bandwidth in MiByte/s
214,215c215,216
< system.mem_ctrl.busUtil 3.22 # Data bus utilization in percentage
< system.mem_ctrl.busUtilRead 3.22 # Data bus utilization in percentage for reads
---
> system.mem_ctrl.busUtil 3.11 # Data bus utilization in percentage
> system.mem_ctrl.busUtilRead 3.11 # Data bus utilization in percentage for reads
219c220
< system.mem_ctrl.readRowHits 241 # Number of row buffer hits during reads
---
> system.mem_ctrl.readRowHits 248 # Number of row buffer hits during reads
221c222
< system.mem_ctrl.readRowHitRate 66.21 # Row buffer hit rate for reads
---
> system.mem_ctrl.readRowHitRate 68.13 # Row buffer hit rate for reads
223,227c224,228
< system.mem_ctrl.avgGap 154681.32 # Average gap between requests
< system.mem_ctrl.pageHitRate 66.21 # Row buffer hit rate, read and write combined
< system.mem_ctrl_0.actEnergy 309960 # Energy for activate commands per rank (pJ)
< system.mem_ctrl_0.preEnergy 169125 # Energy for precharge commands per rank (pJ)
< system.mem_ctrl_0.readEnergy 1201200 # Energy for read commands per rank (pJ)
---
> system.mem_ctrl.avgGap 160373.63 # Average gap between requests
> system.mem_ctrl.pageHitRate 68.13 # Row buffer hit rate, read and write combined
> system.mem_ctrl_0.actEnergy 292740 # Energy for activate commands per rank (pJ)
> system.mem_ctrl_0.preEnergy 136620 # Energy for precharge commands per rank (pJ)
> system.mem_ctrl_0.readEnergy 1170960 # Energy for read commands per rank (pJ)
229,234c230,239
< system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ)
< system.mem_ctrl_0.actBackEnergy 32277105 # Energy for active background per rank (pJ)
< system.mem_ctrl_0.preBackEnergy 4545000 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_0.totalEnergy 42062310 # Total energy per rank (pJ)
< system.mem_ctrl_0.averagePower 768.068476 # Core power per rank (mW)
< system.mem_ctrl_0.memoryStateTime::IDLE 7392500 # Time in different power states
---
> system.mem_ctrl_0.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ)
> system.mem_ctrl_0.actBackEnergy 2975970 # Energy for active background per rank (pJ)
> system.mem_ctrl_0.preBackEnergy 96960 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_0.actPowerDownEnergy 20164320 # Energy for active power-down per rank (pJ)
> system.mem_ctrl_0.prePowerDownEnergy 2885760 # Energy for precharge power-down per rank (pJ)
> system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
> system.mem_ctrl_0.totalEnergy 32025810 # Total energy per rank (pJ)
> system.mem_ctrl_0.averagePower 547.321100 # Core power per rank (mW)
> system.mem_ctrl_0.totalIdleTime 51467750 # Total Idle time Per DRAM Rank
> system.mem_ctrl_0.memoryStateTime::IDLE 59000 # Time in different power states
236,241c241,247
< system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.mem_ctrl_0.memoryStateTime::ACT 45565000 # Time in different power states
< system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.mem_ctrl_1.actEnergy 574560 # Energy for activate commands per rank (pJ)
< system.mem_ctrl_1.preEnergy 313500 # Energy for precharge commands per rank (pJ)
< system.mem_ctrl_1.readEnergy 1552200 # Energy for read commands per rank (pJ)
---
> system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::PRE_PDN 7513000 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::ACT 4902000 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::ACT_PDN 44219000 # Time in different power states
> system.mem_ctrl_1.actEnergy 535500 # Energy for activate commands per rank (pJ)
> system.mem_ctrl_1.preEnergy 273240 # Energy for precharge commands per rank (pJ)
> system.mem_ctrl_1.readEnergy 1428000 # Energy for read commands per rank (pJ)
243,248c249,258
< system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ)
< system.mem_ctrl_1.actBackEnergy 36915480 # Energy for active background per rank (pJ)
< system.mem_ctrl_1.preBackEnergy 476250 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_1.totalEnergy 43391910 # Total energy per rank (pJ)
< system.mem_ctrl_1.averagePower 792.347310 # Core power per rank (mW)
< system.mem_ctrl_1.memoryStateTime::IDLE 2122500 # Time in different power states
---
> system.mem_ctrl_1.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ)
> system.mem_ctrl_1.actBackEnergy 3735210 # Energy for active background per rank (pJ)
> system.mem_ctrl_1.preBackEnergy 150720 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_1.actPowerDownEnergy 22328040 # Energy for active power-down per rank (pJ)
> system.mem_ctrl_1.prePowerDownEnergy 370560 # Energy for precharge power-down per rank (pJ)
> system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
> system.mem_ctrl_1.totalEnergy 33123750 # Total energy per rank (pJ)
> system.mem_ctrl_1.averagePower 566.084895 # Core power per rank (mW)
> system.mem_ctrl_1.totalIdleTime 49870500 # Total Idle time Per DRAM Rank
> system.mem_ctrl_1.memoryStateTime::IDLE 184000 # Time in different power states
250,254c260,265
< system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.mem_ctrl_1.memoryStateTime::ACT 52384500 # Time in different power states
< system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
---
> system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::PRE_PDN 965000 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::ACT 6563000 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::ACT_PDN 48981000 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states
256,257c267,268
< system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
---
> system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states
259,260c270,271
< system.cpu.pwrStateResidencyTicks::ON 56435000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 56435 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 58513000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 58513 # number of cpu cycles simulated
281c292
< system.cpu.num_busy_cycles 56434.999000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 58512.999000 # Number of busy cycles
320c331
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states
322c333
< system.cpu.dcache.tags.tagsinuse 81.661133 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 81.299644 # Cycle average of tags in use
327,329c338,340
< system.cpu.dcache.tags.occ_blocks::cpu.data 81.661133 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.079747 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.079747 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 81.299644 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.079394 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.079394 # Average percentage of cache occupancy
336c347
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states
353,360c364,371
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 6076000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 6076000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 8376000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 8376000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 14452000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 14452000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 14452000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 14452000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 6406000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 6406000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 8602000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 8602000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 15008000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 15008000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 15008000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 15008000 # number of overall miss cycles
377,384c388,395
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 108500 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 108500 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 106025.316456 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 106025.316456 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 107051.851852 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 107051.851852 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 107051.851852 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 107051.851852 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 114392.857143 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 114392.857143 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108886.075949 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 108886.075949 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 111170.370370 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 111170.370370 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 111170.370370 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 111170.370370 # average overall miss latency
399,406c410,417
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5964000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5964000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8218000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 8218000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14182000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 14182000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14182000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 14182000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6294000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6294000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8444000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 8444000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14738000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 14738000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14738000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 14738000 # number of overall MSHR miss cycles
415,423c426,434
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 106500 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 106500 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 104025.316456 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 104025.316456 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 105051.851852 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 105051.851852 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 105051.851852 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 105051.851852 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 112392.857143 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 112392.857143 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106886.075949 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106886.075949 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 109170.370370 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 109170.370370 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 109170.370370 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 109170.370370 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states
425c436
< system.cpu.icache.tags.tagsinuse 91.248553 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 90.704136 # Cycle average of tags in use
430,432c441,443
< system.cpu.icache.tags.occ_blocks::cpu.inst 91.248553 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.356440 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.356440 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 90.704136 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.354313 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.354313 # Average percentage of cache occupancy
439c450
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states
452,457c463,468
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 24107000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 24107000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 24107000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 24107000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 24107000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 24107000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 25629000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 25629000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 25629000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 25629000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 25629000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 25629000 # number of overall miss cycles
470,475c481,486
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 102582.978723 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 102582.978723 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 102582.978723 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 102582.978723 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 102582.978723 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 102582.978723 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 109059.574468 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 109059.574468 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 109059.574468 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 109059.574468 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 109059.574468 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 109059.574468 # average overall miss latency
488,493c499,504
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23637000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 23637000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23637000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 23637000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23637000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 23637000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25159000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 25159000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25159000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 25159000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25159000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 25159000 # number of overall MSHR miss cycles
500,505c511,516
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 100582.978723 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 100582.978723 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 100582.978723 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 100582.978723 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 100582.978723 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 100582.978723 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 107059.574468 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 107059.574468 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 107059.574468 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 107059.574468 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 107059.574468 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 107059.574468 # average overall mshr miss latency
512c523
< system.l2bus.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
---
> system.l2bus.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states
538c549
< system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%)
---
> system.l2bus.reqLayer0.utilization 0.7 # Layer utilization (%)
543c554
< system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states
545c556
< system.l2cache.tags.tagsinuse 188.623694 # Cycle average of tags in use
---
> system.l2cache.tags.tagsinuse 187.541609 # Cycle average of tags in use
550,554c561,565
< system.l2cache.tags.occ_blocks::cpu.inst 106.912326 # Average occupied blocks per requestor
< system.l2cache.tags.occ_blocks::cpu.data 81.711368 # Average occupied blocks per requestor
< system.l2cache.tags.occ_percent::cpu.inst 0.026102 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::cpu.data 0.019949 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::total 0.046051 # Average percentage of cache occupancy
---
> system.l2cache.tags.occ_blocks::cpu.inst 106.193515 # Average occupied blocks per requestor
> system.l2cache.tags.occ_blocks::cpu.data 81.348095 # Average occupied blocks per requestor
> system.l2cache.tags.occ_percent::cpu.inst 0.025926 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::cpu.data 0.019860 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::total 0.045787 # Average percentage of cache occupancy
561c572
< system.l2cache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states
579,589c590,600
< system.l2cache.ReadExReq_miss_latency::cpu.data 7981000 # number of ReadExReq miss cycles
< system.l2cache.ReadExReq_miss_latency::total 7981000 # number of ReadExReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22804000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.data 5796000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::total 28600000 # number of ReadSharedReq miss cycles
< system.l2cache.demand_miss_latency::cpu.inst 22804000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::cpu.data 13777000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::total 36581000 # number of demand (read+write) miss cycles
< system.l2cache.overall_miss_latency::cpu.inst 22804000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::cpu.data 13777000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::total 36581000 # number of overall miss cycles
---
> system.l2cache.ReadExReq_miss_latency::cpu.data 8207000 # number of ReadExReq miss cycles
> system.l2cache.ReadExReq_miss_latency::total 8207000 # number of ReadExReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24326000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.data 6126000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::total 30452000 # number of ReadSharedReq miss cycles
> system.l2cache.demand_miss_latency::cpu.inst 24326000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::cpu.data 14333000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::total 38659000 # number of demand (read+write) miss cycles
> system.l2cache.overall_miss_latency::cpu.inst 24326000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::cpu.data 14333000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::total 38659000 # number of overall miss cycles
612,622c623,633
< system.l2cache.ReadExReq_avg_miss_latency::cpu.data 101025.316456 # average ReadExReq miss latency
< system.l2cache.ReadExReq_avg_miss_latency::total 101025.316456 # average ReadExReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 99580.786026 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103500 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::total 100350.877193 # average ReadSharedReq miss latency
< system.l2cache.demand_avg_miss_latency::cpu.inst 99580.786026 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::cpu.data 102051.851852 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::total 100497.252747 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.inst 99580.786026 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.data 102051.851852 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::total 100497.252747 # average overall miss latency
---
> system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103886.075949 # average ReadExReq miss latency
> system.l2cache.ReadExReq_avg_miss_latency::total 103886.075949 # average ReadExReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 106227.074236 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 109392.857143 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::total 106849.122807 # average ReadSharedReq miss latency
> system.l2cache.demand_avg_miss_latency::cpu.inst 106227.074236 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::cpu.data 106170.370370 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::total 106206.043956 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.inst 106227.074236 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.data 106170.370370 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::total 106206.043956 # average overall miss latency
640,650c651,661
< system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6401000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadExReq_mshr_miss_latency::total 6401000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 18224000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4676000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::total 22900000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.inst 18224000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.data 11077000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::total 29301000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.inst 18224000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.data 11077000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::total 29301000 # number of overall MSHR miss cycles
---
> system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6627000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadExReq_mshr_miss_latency::total 6627000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19746000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5006000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::total 24752000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.inst 19746000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.data 11633000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::total 31379000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.inst 19746000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.data 11633000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::total 31379000 # number of overall MSHR miss cycles
662,672c673,683
< system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81025.316456 # average ReadExReq mshr miss latency
< system.l2cache.ReadExReq_avg_mshr_miss_latency::total 81025.316456 # average ReadExReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 79580.786026 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83500 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80350.877193 # average ReadSharedReq mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79580.786026 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.data 82051.851852 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::total 80497.252747 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79580.786026 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.data 82051.851852 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::total 80497.252747 # average overall mshr miss latency
---
> system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83886.075949 # average ReadExReq mshr miss latency
> system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83886.075949 # average ReadExReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 86227.074236 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89392.857143 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 86849.122807 # average ReadSharedReq mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 86227.074236 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.data 86170.370370 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::total 86206.043956 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 86227.074236 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.data 86170.370370 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::total 86206.043956 # average overall mshr miss latency
679c690
< system.membus.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states
704,705c715,716
< system.membus.respLayer0.occupancy 1954250 # Layer occupancy (ticks)
< system.membus.respLayer0.utilization 3.5 # Layer utilization (%)
---
> system.membus.respLayer0.occupancy 1951250 # Layer occupancy (ticks)
> system.membus.respLayer0.utilization 3.3 # Layer utilization (%)
< sim_seconds 0.000056 # Number of seconds simulated
< sim_ticks 56435000 # Number of ticks simulated
< final_tick 56435000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000059 # Number of seconds simulated
> sim_ticks 58513000 # Number of ticks simulated
> final_tick 58513000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 125605 # Simulator instruction rate (inst/s)
< host_op_rate 226732 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1240265940 # Simulator tick rate (ticks/s)
< host_mem_usage 656384 # Number of bytes of host memory used
< host_seconds 0.05 # Real time elapsed on the host
---
> host_inst_rate 325988 # Simulator instruction rate (inst/s)
> host_op_rate 588251 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 3335289412 # Simulator tick rate (ticks/s)
> host_mem_usage 654560 # Number of bytes of host memory used
> host_seconds 0.02 # Real time elapsed on the host
16c16
< system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
---
> system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.mem_ctrl.bw_read::cpu.inst 259696997 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::cpu.data 153096483 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::total 412793479 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::cpu.inst 259696997 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::total 259696997 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.inst 259696997 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.data 153096483 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::total 412793479 # Total bandwidth to/from this memory (bytes/s)
---
> system.mem_ctrl.bw_read::cpu.inst 250474254 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::cpu.data 147659494 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::total 398133748 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::cpu.inst 250474254 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::total 250474254 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.inst 250474254 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.data 147659494 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::total 398133748 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.mem_ctrl.totGap 56304000 # Total gap between requests
---
> system.mem_ctrl.totGap 58376000 # Total gap between requests
190,204c190,205
< system.mem_ctrl.bytesPerActivate::samples 117 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::mean 193.094017 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::gmean 128.926887 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::stdev 215.889898 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::0-127 57 48.72% 48.72% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::128-255 28 23.93% 72.65% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::256-383 16 13.68% 86.32% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::384-511 6 5.13% 91.45% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::512-639 2 1.71% 93.16% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::640-767 2 1.71% 94.87% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::768-895 3 2.56% 97.44% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::1024-1151 3 2.56% 100.00% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::total 117 # Bytes accessed per row activation
< system.mem_ctrl.totQLat 3777750 # Total ticks spent queuing
< system.mem_ctrl.totMemAccLat 10602750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.mem_ctrl.bytesPerActivate::samples 108 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::mean 199.703704 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::gmean 135.091179 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::stdev 199.282229 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::0-127 52 48.15% 48.15% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::128-255 21 19.44% 67.59% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::256-383 15 13.89% 81.48% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::384-511 8 7.41% 88.89% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::512-639 7 6.48% 95.37% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::640-767 2 1.85% 97.22% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::768-895 1 0.93% 98.15% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::896-1023 1 0.93% 99.07% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::1024-1151 1 0.93% 100.00% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::total 108 # Bytes accessed per row activation
> system.mem_ctrl.totQLat 5858750 # Total ticks spent queuing
> system.mem_ctrl.totMemAccLat 12683750 # Total ticks spent from burst creation until serviced by the DRAM
206c207
< system.mem_ctrl.avgQLat 10378.43 # Average queueing delay per DRAM burst
---
> system.mem_ctrl.avgQLat 16095.47 # Average queueing delay per DRAM burst
208,209c209,210
< system.mem_ctrl.avgMemAccLat 29128.43 # Average memory access latency per DRAM burst
< system.mem_ctrl.avgRdBW 412.79 # Average DRAM read bandwidth in MiByte/s
---
> system.mem_ctrl.avgMemAccLat 34845.47 # Average memory access latency per DRAM burst
> system.mem_ctrl.avgRdBW 398.13 # Average DRAM read bandwidth in MiByte/s
211c212
< system.mem_ctrl.avgRdBWSys 412.79 # Average system read bandwidth in MiByte/s
---
> system.mem_ctrl.avgRdBWSys 398.13 # Average system read bandwidth in MiByte/s
214,215c215,216
< system.mem_ctrl.busUtil 3.22 # Data bus utilization in percentage
< system.mem_ctrl.busUtilRead 3.22 # Data bus utilization in percentage for reads
---
> system.mem_ctrl.busUtil 3.11 # Data bus utilization in percentage
> system.mem_ctrl.busUtilRead 3.11 # Data bus utilization in percentage for reads
219c220
< system.mem_ctrl.readRowHits 241 # Number of row buffer hits during reads
---
> system.mem_ctrl.readRowHits 248 # Number of row buffer hits during reads
221c222
< system.mem_ctrl.readRowHitRate 66.21 # Row buffer hit rate for reads
---
> system.mem_ctrl.readRowHitRate 68.13 # Row buffer hit rate for reads
223,227c224,228
< system.mem_ctrl.avgGap 154681.32 # Average gap between requests
< system.mem_ctrl.pageHitRate 66.21 # Row buffer hit rate, read and write combined
< system.mem_ctrl_0.actEnergy 309960 # Energy for activate commands per rank (pJ)
< system.mem_ctrl_0.preEnergy 169125 # Energy for precharge commands per rank (pJ)
< system.mem_ctrl_0.readEnergy 1201200 # Energy for read commands per rank (pJ)
---
> system.mem_ctrl.avgGap 160373.63 # Average gap between requests
> system.mem_ctrl.pageHitRate 68.13 # Row buffer hit rate, read and write combined
> system.mem_ctrl_0.actEnergy 292740 # Energy for activate commands per rank (pJ)
> system.mem_ctrl_0.preEnergy 136620 # Energy for precharge commands per rank (pJ)
> system.mem_ctrl_0.readEnergy 1170960 # Energy for read commands per rank (pJ)
229,234c230,239
< system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ)
< system.mem_ctrl_0.actBackEnergy 32277105 # Energy for active background per rank (pJ)
< system.mem_ctrl_0.preBackEnergy 4545000 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_0.totalEnergy 42062310 # Total energy per rank (pJ)
< system.mem_ctrl_0.averagePower 768.068476 # Core power per rank (mW)
< system.mem_ctrl_0.memoryStateTime::IDLE 7392500 # Time in different power states
---
> system.mem_ctrl_0.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ)
> system.mem_ctrl_0.actBackEnergy 2975970 # Energy for active background per rank (pJ)
> system.mem_ctrl_0.preBackEnergy 96960 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_0.actPowerDownEnergy 20164320 # Energy for active power-down per rank (pJ)
> system.mem_ctrl_0.prePowerDownEnergy 2885760 # Energy for precharge power-down per rank (pJ)
> system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
> system.mem_ctrl_0.totalEnergy 32025810 # Total energy per rank (pJ)
> system.mem_ctrl_0.averagePower 547.321100 # Core power per rank (mW)
> system.mem_ctrl_0.totalIdleTime 51467750 # Total Idle time Per DRAM Rank
> system.mem_ctrl_0.memoryStateTime::IDLE 59000 # Time in different power states
236,241c241,247
< system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.mem_ctrl_0.memoryStateTime::ACT 45565000 # Time in different power states
< system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.mem_ctrl_1.actEnergy 574560 # Energy for activate commands per rank (pJ)
< system.mem_ctrl_1.preEnergy 313500 # Energy for precharge commands per rank (pJ)
< system.mem_ctrl_1.readEnergy 1552200 # Energy for read commands per rank (pJ)
---
> system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::PRE_PDN 7513000 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::ACT 4902000 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::ACT_PDN 44219000 # Time in different power states
> system.mem_ctrl_1.actEnergy 535500 # Energy for activate commands per rank (pJ)
> system.mem_ctrl_1.preEnergy 273240 # Energy for precharge commands per rank (pJ)
> system.mem_ctrl_1.readEnergy 1428000 # Energy for read commands per rank (pJ)
243,248c249,258
< system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ)
< system.mem_ctrl_1.actBackEnergy 36915480 # Energy for active background per rank (pJ)
< system.mem_ctrl_1.preBackEnergy 476250 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_1.totalEnergy 43391910 # Total energy per rank (pJ)
< system.mem_ctrl_1.averagePower 792.347310 # Core power per rank (mW)
< system.mem_ctrl_1.memoryStateTime::IDLE 2122500 # Time in different power states
---
> system.mem_ctrl_1.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ)
> system.mem_ctrl_1.actBackEnergy 3735210 # Energy for active background per rank (pJ)
> system.mem_ctrl_1.preBackEnergy 150720 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_1.actPowerDownEnergy 22328040 # Energy for active power-down per rank (pJ)
> system.mem_ctrl_1.prePowerDownEnergy 370560 # Energy for precharge power-down per rank (pJ)
> system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
> system.mem_ctrl_1.totalEnergy 33123750 # Total energy per rank (pJ)
> system.mem_ctrl_1.averagePower 566.084895 # Core power per rank (mW)
> system.mem_ctrl_1.totalIdleTime 49870500 # Total Idle time Per DRAM Rank
> system.mem_ctrl_1.memoryStateTime::IDLE 184000 # Time in different power states
250,254c260,265
< system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.mem_ctrl_1.memoryStateTime::ACT 52384500 # Time in different power states
< system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
---
> system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::PRE_PDN 965000 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::ACT 6563000 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::ACT_PDN 48981000 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states
256,257c267,268
< system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
---
> system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states
259,260c270,271
< system.cpu.pwrStateResidencyTicks::ON 56435000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 56435 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 58513000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 58513 # number of cpu cycles simulated
281c292
< system.cpu.num_busy_cycles 56434.999000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 58512.999000 # Number of busy cycles
320c331
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states
322c333
< system.cpu.dcache.tags.tagsinuse 81.661133 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 81.299644 # Cycle average of tags in use
327,329c338,340
< system.cpu.dcache.tags.occ_blocks::cpu.data 81.661133 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.079747 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.079747 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 81.299644 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.079394 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.079394 # Average percentage of cache occupancy
336c347
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states
353,360c364,371
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 6076000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 6076000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 8376000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 8376000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 14452000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 14452000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 14452000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 14452000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 6406000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 6406000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 8602000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 8602000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 15008000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 15008000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 15008000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 15008000 # number of overall miss cycles
377,384c388,395
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 108500 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 108500 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 106025.316456 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 106025.316456 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 107051.851852 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 107051.851852 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 107051.851852 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 107051.851852 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 114392.857143 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 114392.857143 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108886.075949 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 108886.075949 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 111170.370370 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 111170.370370 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 111170.370370 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 111170.370370 # average overall miss latency
399,406c410,417
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5964000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5964000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8218000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 8218000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14182000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 14182000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14182000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 14182000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6294000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6294000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8444000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 8444000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14738000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 14738000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14738000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 14738000 # number of overall MSHR miss cycles
415,423c426,434
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 106500 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 106500 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 104025.316456 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 104025.316456 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 105051.851852 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 105051.851852 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 105051.851852 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 105051.851852 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 112392.857143 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 112392.857143 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106886.075949 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106886.075949 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 109170.370370 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 109170.370370 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 109170.370370 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 109170.370370 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states
425c436
< system.cpu.icache.tags.tagsinuse 91.248553 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 90.704136 # Cycle average of tags in use
430,432c441,443
< system.cpu.icache.tags.occ_blocks::cpu.inst 91.248553 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.356440 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.356440 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 90.704136 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.354313 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.354313 # Average percentage of cache occupancy
439c450
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states
452,457c463,468
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 24107000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 24107000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 24107000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 24107000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 24107000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 24107000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 25629000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 25629000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 25629000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 25629000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 25629000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 25629000 # number of overall miss cycles
470,475c481,486
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 102582.978723 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 102582.978723 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 102582.978723 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 102582.978723 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 102582.978723 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 102582.978723 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 109059.574468 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 109059.574468 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 109059.574468 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 109059.574468 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 109059.574468 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 109059.574468 # average overall miss latency
488,493c499,504
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23637000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 23637000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23637000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 23637000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23637000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 23637000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25159000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 25159000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25159000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 25159000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25159000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 25159000 # number of overall MSHR miss cycles
500,505c511,516
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 100582.978723 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 100582.978723 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 100582.978723 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 100582.978723 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 100582.978723 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 100582.978723 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 107059.574468 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 107059.574468 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 107059.574468 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 107059.574468 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 107059.574468 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 107059.574468 # average overall mshr miss latency
512c523
< system.l2bus.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
---
> system.l2bus.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states
538c549
< system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%)
---
> system.l2bus.reqLayer0.utilization 0.7 # Layer utilization (%)
543c554
< system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states
545c556
< system.l2cache.tags.tagsinuse 188.623694 # Cycle average of tags in use
---
> system.l2cache.tags.tagsinuse 187.541609 # Cycle average of tags in use
550,554c561,565
< system.l2cache.tags.occ_blocks::cpu.inst 106.912326 # Average occupied blocks per requestor
< system.l2cache.tags.occ_blocks::cpu.data 81.711368 # Average occupied blocks per requestor
< system.l2cache.tags.occ_percent::cpu.inst 0.026102 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::cpu.data 0.019949 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::total 0.046051 # Average percentage of cache occupancy
---
> system.l2cache.tags.occ_blocks::cpu.inst 106.193515 # Average occupied blocks per requestor
> system.l2cache.tags.occ_blocks::cpu.data 81.348095 # Average occupied blocks per requestor
> system.l2cache.tags.occ_percent::cpu.inst 0.025926 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::cpu.data 0.019860 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::total 0.045787 # Average percentage of cache occupancy
561c572
< system.l2cache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states
579,589c590,600
< system.l2cache.ReadExReq_miss_latency::cpu.data 7981000 # number of ReadExReq miss cycles
< system.l2cache.ReadExReq_miss_latency::total 7981000 # number of ReadExReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22804000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.data 5796000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::total 28600000 # number of ReadSharedReq miss cycles
< system.l2cache.demand_miss_latency::cpu.inst 22804000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::cpu.data 13777000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::total 36581000 # number of demand (read+write) miss cycles
< system.l2cache.overall_miss_latency::cpu.inst 22804000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::cpu.data 13777000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::total 36581000 # number of overall miss cycles
---
> system.l2cache.ReadExReq_miss_latency::cpu.data 8207000 # number of ReadExReq miss cycles
> system.l2cache.ReadExReq_miss_latency::total 8207000 # number of ReadExReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24326000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.data 6126000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::total 30452000 # number of ReadSharedReq miss cycles
> system.l2cache.demand_miss_latency::cpu.inst 24326000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::cpu.data 14333000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::total 38659000 # number of demand (read+write) miss cycles
> system.l2cache.overall_miss_latency::cpu.inst 24326000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::cpu.data 14333000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::total 38659000 # number of overall miss cycles
612,622c623,633
< system.l2cache.ReadExReq_avg_miss_latency::cpu.data 101025.316456 # average ReadExReq miss latency
< system.l2cache.ReadExReq_avg_miss_latency::total 101025.316456 # average ReadExReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 99580.786026 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103500 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::total 100350.877193 # average ReadSharedReq miss latency
< system.l2cache.demand_avg_miss_latency::cpu.inst 99580.786026 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::cpu.data 102051.851852 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::total 100497.252747 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.inst 99580.786026 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.data 102051.851852 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::total 100497.252747 # average overall miss latency
---
> system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103886.075949 # average ReadExReq miss latency
> system.l2cache.ReadExReq_avg_miss_latency::total 103886.075949 # average ReadExReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 106227.074236 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 109392.857143 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::total 106849.122807 # average ReadSharedReq miss latency
> system.l2cache.demand_avg_miss_latency::cpu.inst 106227.074236 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::cpu.data 106170.370370 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::total 106206.043956 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.inst 106227.074236 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.data 106170.370370 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::total 106206.043956 # average overall miss latency
640,650c651,661
< system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6401000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadExReq_mshr_miss_latency::total 6401000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 18224000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4676000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::total 22900000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.inst 18224000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.data 11077000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::total 29301000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.inst 18224000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.data 11077000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::total 29301000 # number of overall MSHR miss cycles
---
> system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6627000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadExReq_mshr_miss_latency::total 6627000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19746000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5006000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::total 24752000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.inst 19746000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.data 11633000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::total 31379000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.inst 19746000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.data 11633000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::total 31379000 # number of overall MSHR miss cycles
662,672c673,683
< system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81025.316456 # average ReadExReq mshr miss latency
< system.l2cache.ReadExReq_avg_mshr_miss_latency::total 81025.316456 # average ReadExReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 79580.786026 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83500 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80350.877193 # average ReadSharedReq mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79580.786026 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.data 82051.851852 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::total 80497.252747 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79580.786026 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.data 82051.851852 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::total 80497.252747 # average overall mshr miss latency
---
> system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83886.075949 # average ReadExReq mshr miss latency
> system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83886.075949 # average ReadExReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 86227.074236 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89392.857143 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 86849.122807 # average ReadSharedReq mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 86227.074236 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.data 86170.370370 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::total 86206.043956 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 86227.074236 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.data 86170.370370 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::total 86206.043956 # average overall mshr miss latency
679c690
< system.membus.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states
704,705c715,716
< system.membus.respLayer0.occupancy 1954250 # Layer occupancy (ticks)
< system.membus.respLayer0.utilization 3.5 # Layer utilization (%)
---
> system.membus.respLayer0.occupancy 1951250 # Layer occupancy (ticks)
> system.membus.respLayer0.utilization 3.3 # Layer utilization (%)