4,5c4,5
< sim_ticks 55844000 # Number of ticks simulated
< final_tick 55844000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 56435000 # Number of ticks simulated
> final_tick 56435000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 197644 # Simulator instruction rate (inst/s)
< host_op_rate 356622 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1929610808 # Simulator tick rate (ticks/s)
< host_mem_usage 652268 # Number of bytes of host memory used
< host_seconds 0.03 # Real time elapsed on the host
---
> host_inst_rate 125605 # Simulator instruction rate (inst/s)
> host_op_rate 226732 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1240265940 # Simulator tick rate (ticks/s)
> host_mem_usage 656384 # Number of bytes of host memory used
> host_seconds 0.05 # Real time elapsed on the host
16c16
< system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
---
> system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.mem_ctrl.bw_read::cpu.inst 262445384 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::cpu.data 154716711 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::total 417162094 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::cpu.inst 262445384 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::total 262445384 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.inst 262445384 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.data 154716711 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::total 417162094 # Total bandwidth to/from this memory (bytes/s)
---
> system.mem_ctrl.bw_read::cpu.inst 259696997 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::cpu.data 153096483 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::total 412793479 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::cpu.inst 259696997 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::total 259696997 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.inst 259696997 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.data 153096483 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::total 412793479 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.mem_ctrl.totGap 55714000 # Total gap between requests
---
> system.mem_ctrl.totGap 56304000 # Total gap between requests
190,205c190,204
< system.mem_ctrl.bytesPerActivate::samples 115 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::mean 199.234783 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::gmean 135.588464 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::stdev 217.243914 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::0-127 49 42.61% 42.61% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::128-255 34 29.57% 72.17% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::256-383 16 13.91% 86.09% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::384-511 6 5.22% 91.30% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::512-639 2 1.74% 93.04% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::640-767 2 1.74% 94.78% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::768-895 2 1.74% 96.52% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::896-1023 1 0.87% 97.39% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::1024-1151 3 2.61% 100.00% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::total 115 # Bytes accessed per row activation
< system.mem_ctrl.totQLat 3552250 # Total ticks spent queuing
< system.mem_ctrl.totMemAccLat 10377250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.mem_ctrl.bytesPerActivate::samples 117 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::mean 193.094017 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::gmean 128.926887 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::stdev 215.889898 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::0-127 57 48.72% 48.72% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::128-255 28 23.93% 72.65% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::256-383 16 13.68% 86.32% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::384-511 6 5.13% 91.45% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::512-639 2 1.71% 93.16% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::640-767 2 1.71% 94.87% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::768-895 3 2.56% 97.44% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::1024-1151 3 2.56% 100.00% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::total 117 # Bytes accessed per row activation
> system.mem_ctrl.totQLat 3777750 # Total ticks spent queuing
> system.mem_ctrl.totMemAccLat 10602750 # Total ticks spent from burst creation until serviced by the DRAM
207c206
< system.mem_ctrl.avgQLat 9758.93 # Average queueing delay per DRAM burst
---
> system.mem_ctrl.avgQLat 10378.43 # Average queueing delay per DRAM burst
209,210c208,209
< system.mem_ctrl.avgMemAccLat 28508.93 # Average memory access latency per DRAM burst
< system.mem_ctrl.avgRdBW 417.16 # Average DRAM read bandwidth in MiByte/s
---
> system.mem_ctrl.avgMemAccLat 29128.43 # Average memory access latency per DRAM burst
> system.mem_ctrl.avgRdBW 412.79 # Average DRAM read bandwidth in MiByte/s
212c211
< system.mem_ctrl.avgRdBWSys 417.16 # Average system read bandwidth in MiByte/s
---
> system.mem_ctrl.avgRdBWSys 412.79 # Average system read bandwidth in MiByte/s
215,216c214,215
< system.mem_ctrl.busUtil 3.26 # Data bus utilization in percentage
< system.mem_ctrl.busUtilRead 3.26 # Data bus utilization in percentage for reads
---
> system.mem_ctrl.busUtil 3.22 # Data bus utilization in percentage
> system.mem_ctrl.busUtilRead 3.22 # Data bus utilization in percentage for reads
220c219
< system.mem_ctrl.readRowHits 244 # Number of row buffer hits during reads
---
> system.mem_ctrl.readRowHits 241 # Number of row buffer hits during reads
222c221
< system.mem_ctrl.readRowHitRate 67.03 # Row buffer hit rate for reads
---
> system.mem_ctrl.readRowHitRate 66.21 # Row buffer hit rate for reads
224,228c223,227
< system.mem_ctrl.avgGap 153060.44 # Average gap between requests
< system.mem_ctrl.pageHitRate 67.03 # Row buffer hit rate, read and write combined
< system.mem_ctrl_0.actEnergy 302400 # Energy for activate commands per rank (pJ)
< system.mem_ctrl_0.preEnergy 165000 # Energy for precharge commands per rank (pJ)
< system.mem_ctrl_0.readEnergy 1240200 # Energy for read commands per rank (pJ)
---
> system.mem_ctrl.avgGap 154681.32 # Average gap between requests
> system.mem_ctrl.pageHitRate 66.21 # Row buffer hit rate, read and write combined
> system.mem_ctrl_0.actEnergy 309960 # Energy for activate commands per rank (pJ)
> system.mem_ctrl_0.preEnergy 169125 # Energy for precharge commands per rank (pJ)
> system.mem_ctrl_0.readEnergy 1201200 # Energy for read commands per rank (pJ)
231,235c230,234
< system.mem_ctrl_0.actBackEnergy 32401080 # Energy for active background per rank (pJ)
< system.mem_ctrl_0.preBackEnergy 4436250 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_0.totalEnergy 42104850 # Total energy per rank (pJ)
< system.mem_ctrl_0.averagePower 768.845267 # Core power per rank (mW)
< system.mem_ctrl_0.memoryStateTime::IDLE 7212250 # Time in different power states
---
> system.mem_ctrl_0.actBackEnergy 32277105 # Energy for active background per rank (pJ)
> system.mem_ctrl_0.preBackEnergy 4545000 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_0.totalEnergy 42062310 # Total energy per rank (pJ)
> system.mem_ctrl_0.averagePower 768.068476 # Core power per rank (mW)
> system.mem_ctrl_0.memoryStateTime::IDLE 7392500 # Time in different power states
238c237
< system.mem_ctrl_0.memoryStateTime::ACT 45745250 # Time in different power states
---
> system.mem_ctrl_0.memoryStateTime::ACT 45565000 # Time in different power states
240,241c239,240
< system.mem_ctrl_1.actEnergy 567000 # Energy for activate commands per rank (pJ)
< system.mem_ctrl_1.preEnergy 309375 # Energy for precharge commands per rank (pJ)
---
> system.mem_ctrl_1.actEnergy 574560 # Energy for activate commands per rank (pJ)
> system.mem_ctrl_1.preEnergy 313500 # Energy for precharge commands per rank (pJ)
245,249c244,248
< system.mem_ctrl_1.actBackEnergy 36016020 # Energy for active background per rank (pJ)
< system.mem_ctrl_1.preBackEnergy 1265250 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_1.totalEnergy 43269765 # Total energy per rank (pJ)
< system.mem_ctrl_1.averagePower 790.116911 # Core power per rank (mW)
< system.mem_ctrl_1.memoryStateTime::IDLE 2847000 # Time in different power states
---
> system.mem_ctrl_1.actBackEnergy 36915480 # Energy for active background per rank (pJ)
> system.mem_ctrl_1.preBackEnergy 476250 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_1.totalEnergy 43391910 # Total energy per rank (pJ)
> system.mem_ctrl_1.averagePower 792.347310 # Core power per rank (mW)
> system.mem_ctrl_1.memoryStateTime::IDLE 2122500 # Time in different power states
252c251
< system.mem_ctrl_1.memoryStateTime::ACT 51070000 # Time in different power states
---
> system.mem_ctrl_1.memoryStateTime::ACT 52384500 # Time in different power states
254,255c253,254
< system.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
---
> system.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
257,258c256,257
< system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
---
> system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
260,261c259,260
< system.cpu.pwrStateResidencyTicks::ON 55844000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 55844 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 56435000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 56435 # number of cpu cycles simulated
282c281
< system.cpu.num_busy_cycles 55843.999000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 56434.999000 # Number of busy cycles
321c320
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
323c322
< system.cpu.dcache.tags.tagsinuse 81.671640 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 81.661133 # Cycle average of tags in use
328,330c327,329
< system.cpu.dcache.tags.occ_blocks::cpu.data 81.671640 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.079757 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.079757 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 81.661133 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.079747 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.079747 # Average percentage of cache occupancy
337c336
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
354,361c353,360
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 6006000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 6006000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 8260000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 8260000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 14266000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 14266000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 14266000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 14266000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 6076000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 6076000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 8376000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 8376000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 14452000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 14452000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 14452000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 14452000 # number of overall miss cycles
378,385c377,384
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 107250 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 107250 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 104556.962025 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 104556.962025 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 105674.074074 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 105674.074074 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 105674.074074 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 105674.074074 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 108500 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 108500 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 106025.316456 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 106025.316456 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 107051.851852 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 107051.851852 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 107051.851852 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 107051.851852 # average overall miss latency
400,407c399,406
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5894000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5894000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8102000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 8102000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13996000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 13996000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13996000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 13996000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5964000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5964000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8218000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 8218000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14182000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 14182000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14182000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 14182000 # number of overall MSHR miss cycles
416,424c415,423
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 105250 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 105250 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102556.962025 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102556.962025 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 106500 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 106500 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 104025.316456 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 104025.316456 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 105051.851852 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 105051.851852 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 105051.851852 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 105051.851852 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
426c425
< system.cpu.icache.tags.tagsinuse 91.239705 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 91.248553 # Cycle average of tags in use
431,433c430,432
< system.cpu.icache.tags.occ_blocks::cpu.inst 91.239705 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.356405 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.356405 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 91.248553 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.356440 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.356440 # Average percentage of cache occupancy
435,436c434,435
< system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id
440c439
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
453,458c452,457
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 23702000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 23702000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 23702000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 23702000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 23702000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 23702000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 24107000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 24107000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 24107000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 24107000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 24107000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 24107000 # number of overall miss cycles
471,476c470,475
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100859.574468 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 100859.574468 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 100859.574468 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 100859.574468 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 100859.574468 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 100859.574468 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 102582.978723 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 102582.978723 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 102582.978723 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 102582.978723 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 102582.978723 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 102582.978723 # average overall miss latency
489,494c488,493
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23232000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 23232000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23232000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 23232000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23232000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 23232000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23637000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 23637000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23637000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 23637000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23637000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 23637000 # number of overall MSHR miss cycles
501,506c500,505
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98859.574468 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98859.574468 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 100582.978723 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 100582.978723 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 100582.978723 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 100582.978723 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 100582.978723 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 100582.978723 # average overall mshr miss latency
513c512
< system.l2bus.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
---
> system.l2bus.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
541c540
< system.l2bus.respLayer0.utilization 1.3 # Layer utilization (%)
---
> system.l2bus.respLayer0.utilization 1.2 # Layer utilization (%)
544c543
< system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
546c545
< system.l2cache.tags.tagsinuse 135.848259 # Cycle average of tags in use
---
> system.l2cache.tags.tagsinuse 188.623694 # Cycle average of tags in use
548,549c547,548
< system.l2cache.tags.sampled_refs 285 # Sample count of references to valid blocks.
< system.l2cache.tags.avg_refs 0.224561 # Average number of references to valid blocks.
---
> system.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks.
> system.l2cache.tags.avg_refs 0.175824 # Average number of references to valid blocks.
551,559c550,558
< system.l2cache.tags.occ_blocks::cpu.inst 106.898398 # Average occupied blocks per requestor
< system.l2cache.tags.occ_blocks::cpu.data 28.949861 # Average occupied blocks per requestor
< system.l2cache.tags.occ_percent::cpu.inst 0.026098 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::cpu.data 0.007068 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::total 0.033166 # Average percentage of cache occupancy
< system.l2cache.tags.occ_task_id_blocks::1024 285 # Occupied blocks per task id
< system.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
< system.l2cache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id
< system.l2cache.tags.occ_task_id_percent::1024 0.069580 # Percentage of cache occupancy per task id
---
> system.l2cache.tags.occ_blocks::cpu.inst 106.912326 # Average occupied blocks per requestor
> system.l2cache.tags.occ_blocks::cpu.data 81.711368 # Average occupied blocks per requestor
> system.l2cache.tags.occ_percent::cpu.inst 0.026102 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::cpu.data 0.019949 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::total 0.046051 # Average percentage of cache occupancy
> system.l2cache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id
> system.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
> system.l2cache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id
> system.l2cache.tags.occ_task_id_percent::1024 0.088867 # Percentage of cache occupancy per task id
562c561
< system.l2cache.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
580,590c579,589
< system.l2cache.ReadExReq_miss_latency::cpu.data 7865000 # number of ReadExReq miss cycles
< system.l2cache.ReadExReq_miss_latency::total 7865000 # number of ReadExReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22399000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.data 5726000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::total 28125000 # number of ReadSharedReq miss cycles
< system.l2cache.demand_miss_latency::cpu.inst 22399000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::cpu.data 13591000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::total 35990000 # number of demand (read+write) miss cycles
< system.l2cache.overall_miss_latency::cpu.inst 22399000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::cpu.data 13591000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::total 35990000 # number of overall miss cycles
---
> system.l2cache.ReadExReq_miss_latency::cpu.data 7981000 # number of ReadExReq miss cycles
> system.l2cache.ReadExReq_miss_latency::total 7981000 # number of ReadExReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22804000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.data 5796000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::total 28600000 # number of ReadSharedReq miss cycles
> system.l2cache.demand_miss_latency::cpu.inst 22804000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::cpu.data 13777000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::total 36581000 # number of demand (read+write) miss cycles
> system.l2cache.overall_miss_latency::cpu.inst 22804000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::cpu.data 13777000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::total 36581000 # number of overall miss cycles
613,623c612,622
< system.l2cache.ReadExReq_avg_miss_latency::cpu.data 99556.962025 # average ReadExReq miss latency
< system.l2cache.ReadExReq_avg_miss_latency::total 99556.962025 # average ReadExReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97812.227074 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102250 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::total 98684.210526 # average ReadSharedReq miss latency
< system.l2cache.demand_avg_miss_latency::cpu.inst 97812.227074 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::cpu.data 100674.074074 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::total 98873.626374 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.inst 97812.227074 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.data 100674.074074 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::total 98873.626374 # average overall miss latency
---
> system.l2cache.ReadExReq_avg_miss_latency::cpu.data 101025.316456 # average ReadExReq miss latency
> system.l2cache.ReadExReq_avg_miss_latency::total 101025.316456 # average ReadExReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 99580.786026 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103500 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::total 100350.877193 # average ReadSharedReq miss latency
> system.l2cache.demand_avg_miss_latency::cpu.inst 99580.786026 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::cpu.data 102051.851852 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::total 100497.252747 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.inst 99580.786026 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.data 102051.851852 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::total 100497.252747 # average overall miss latency
641,651c640,650
< system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6285000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadExReq_mshr_miss_latency::total 6285000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17819000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4606000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::total 22425000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.inst 17819000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.data 10891000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::total 28710000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.inst 17819000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.data 10891000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::total 28710000 # number of overall MSHR miss cycles
---
> system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6401000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadExReq_mshr_miss_latency::total 6401000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 18224000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4676000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::total 22900000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.inst 18224000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.data 11077000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::total 29301000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.inst 18224000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.data 11077000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::total 29301000 # number of overall MSHR miss cycles
663,674c662,679
< system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79556.962025 # average ReadExReq mshr miss latency
< system.l2cache.ReadExReq_avg_mshr_miss_latency::total 79556.962025 # average ReadExReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77812.227074 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82250 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78684.210526 # average ReadSharedReq mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency
< system.membus.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81025.316456 # average ReadExReq mshr miss latency
> system.l2cache.ReadExReq_avg_mshr_miss_latency::total 81025.316456 # average ReadExReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 79580.786026 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83500 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80350.877193 # average ReadSharedReq mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79580.786026 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.data 82051.851852 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::total 80497.252747 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79580.786026 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.data 82051.851852 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::total 80497.252747 # average overall mshr miss latency
> system.membus.snoop_filter.tot_requests 364 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
698,699c703,704
< system.membus.reqLayer2.utilization 0.7 # Layer utilization (%)
< system.membus.respLayer0.occupancy 1952750 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.utilization 0.6 # Layer utilization (%)
> system.membus.respLayer0.occupancy 1954250 # Layer occupancy (ticks)
< sim_ticks 55844000 # Number of ticks simulated
< final_tick 55844000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 56435000 # Number of ticks simulated
> final_tick 56435000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 197644 # Simulator instruction rate (inst/s)
< host_op_rate 356622 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1929610808 # Simulator tick rate (ticks/s)
< host_mem_usage 652268 # Number of bytes of host memory used
< host_seconds 0.03 # Real time elapsed on the host
---
> host_inst_rate 125605 # Simulator instruction rate (inst/s)
> host_op_rate 226732 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1240265940 # Simulator tick rate (ticks/s)
> host_mem_usage 656384 # Number of bytes of host memory used
> host_seconds 0.05 # Real time elapsed on the host
16c16
< system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
---
> system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.mem_ctrl.bw_read::cpu.inst 262445384 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::cpu.data 154716711 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::total 417162094 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::cpu.inst 262445384 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::total 262445384 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.inst 262445384 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.data 154716711 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::total 417162094 # Total bandwidth to/from this memory (bytes/s)
---
> system.mem_ctrl.bw_read::cpu.inst 259696997 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::cpu.data 153096483 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::total 412793479 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::cpu.inst 259696997 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::total 259696997 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.inst 259696997 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.data 153096483 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::total 412793479 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.mem_ctrl.totGap 55714000 # Total gap between requests
---
> system.mem_ctrl.totGap 56304000 # Total gap between requests
190,205c190,204
< system.mem_ctrl.bytesPerActivate::samples 115 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::mean 199.234783 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::gmean 135.588464 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::stdev 217.243914 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::0-127 49 42.61% 42.61% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::128-255 34 29.57% 72.17% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::256-383 16 13.91% 86.09% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::384-511 6 5.22% 91.30% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::512-639 2 1.74% 93.04% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::640-767 2 1.74% 94.78% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::768-895 2 1.74% 96.52% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::896-1023 1 0.87% 97.39% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::1024-1151 3 2.61% 100.00% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::total 115 # Bytes accessed per row activation
< system.mem_ctrl.totQLat 3552250 # Total ticks spent queuing
< system.mem_ctrl.totMemAccLat 10377250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.mem_ctrl.bytesPerActivate::samples 117 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::mean 193.094017 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::gmean 128.926887 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::stdev 215.889898 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::0-127 57 48.72% 48.72% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::128-255 28 23.93% 72.65% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::256-383 16 13.68% 86.32% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::384-511 6 5.13% 91.45% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::512-639 2 1.71% 93.16% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::640-767 2 1.71% 94.87% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::768-895 3 2.56% 97.44% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::1024-1151 3 2.56% 100.00% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::total 117 # Bytes accessed per row activation
> system.mem_ctrl.totQLat 3777750 # Total ticks spent queuing
> system.mem_ctrl.totMemAccLat 10602750 # Total ticks spent from burst creation until serviced by the DRAM
207c206
< system.mem_ctrl.avgQLat 9758.93 # Average queueing delay per DRAM burst
---
> system.mem_ctrl.avgQLat 10378.43 # Average queueing delay per DRAM burst
209,210c208,209
< system.mem_ctrl.avgMemAccLat 28508.93 # Average memory access latency per DRAM burst
< system.mem_ctrl.avgRdBW 417.16 # Average DRAM read bandwidth in MiByte/s
---
> system.mem_ctrl.avgMemAccLat 29128.43 # Average memory access latency per DRAM burst
> system.mem_ctrl.avgRdBW 412.79 # Average DRAM read bandwidth in MiByte/s
212c211
< system.mem_ctrl.avgRdBWSys 417.16 # Average system read bandwidth in MiByte/s
---
> system.mem_ctrl.avgRdBWSys 412.79 # Average system read bandwidth in MiByte/s
215,216c214,215
< system.mem_ctrl.busUtil 3.26 # Data bus utilization in percentage
< system.mem_ctrl.busUtilRead 3.26 # Data bus utilization in percentage for reads
---
> system.mem_ctrl.busUtil 3.22 # Data bus utilization in percentage
> system.mem_ctrl.busUtilRead 3.22 # Data bus utilization in percentage for reads
220c219
< system.mem_ctrl.readRowHits 244 # Number of row buffer hits during reads
---
> system.mem_ctrl.readRowHits 241 # Number of row buffer hits during reads
222c221
< system.mem_ctrl.readRowHitRate 67.03 # Row buffer hit rate for reads
---
> system.mem_ctrl.readRowHitRate 66.21 # Row buffer hit rate for reads
224,228c223,227
< system.mem_ctrl.avgGap 153060.44 # Average gap between requests
< system.mem_ctrl.pageHitRate 67.03 # Row buffer hit rate, read and write combined
< system.mem_ctrl_0.actEnergy 302400 # Energy for activate commands per rank (pJ)
< system.mem_ctrl_0.preEnergy 165000 # Energy for precharge commands per rank (pJ)
< system.mem_ctrl_0.readEnergy 1240200 # Energy for read commands per rank (pJ)
---
> system.mem_ctrl.avgGap 154681.32 # Average gap between requests
> system.mem_ctrl.pageHitRate 66.21 # Row buffer hit rate, read and write combined
> system.mem_ctrl_0.actEnergy 309960 # Energy for activate commands per rank (pJ)
> system.mem_ctrl_0.preEnergy 169125 # Energy for precharge commands per rank (pJ)
> system.mem_ctrl_0.readEnergy 1201200 # Energy for read commands per rank (pJ)
231,235c230,234
< system.mem_ctrl_0.actBackEnergy 32401080 # Energy for active background per rank (pJ)
< system.mem_ctrl_0.preBackEnergy 4436250 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_0.totalEnergy 42104850 # Total energy per rank (pJ)
< system.mem_ctrl_0.averagePower 768.845267 # Core power per rank (mW)
< system.mem_ctrl_0.memoryStateTime::IDLE 7212250 # Time in different power states
---
> system.mem_ctrl_0.actBackEnergy 32277105 # Energy for active background per rank (pJ)
> system.mem_ctrl_0.preBackEnergy 4545000 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_0.totalEnergy 42062310 # Total energy per rank (pJ)
> system.mem_ctrl_0.averagePower 768.068476 # Core power per rank (mW)
> system.mem_ctrl_0.memoryStateTime::IDLE 7392500 # Time in different power states
238c237
< system.mem_ctrl_0.memoryStateTime::ACT 45745250 # Time in different power states
---
> system.mem_ctrl_0.memoryStateTime::ACT 45565000 # Time in different power states
240,241c239,240
< system.mem_ctrl_1.actEnergy 567000 # Energy for activate commands per rank (pJ)
< system.mem_ctrl_1.preEnergy 309375 # Energy for precharge commands per rank (pJ)
---
> system.mem_ctrl_1.actEnergy 574560 # Energy for activate commands per rank (pJ)
> system.mem_ctrl_1.preEnergy 313500 # Energy for precharge commands per rank (pJ)
245,249c244,248
< system.mem_ctrl_1.actBackEnergy 36016020 # Energy for active background per rank (pJ)
< system.mem_ctrl_1.preBackEnergy 1265250 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_1.totalEnergy 43269765 # Total energy per rank (pJ)
< system.mem_ctrl_1.averagePower 790.116911 # Core power per rank (mW)
< system.mem_ctrl_1.memoryStateTime::IDLE 2847000 # Time in different power states
---
> system.mem_ctrl_1.actBackEnergy 36915480 # Energy for active background per rank (pJ)
> system.mem_ctrl_1.preBackEnergy 476250 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_1.totalEnergy 43391910 # Total energy per rank (pJ)
> system.mem_ctrl_1.averagePower 792.347310 # Core power per rank (mW)
> system.mem_ctrl_1.memoryStateTime::IDLE 2122500 # Time in different power states
252c251
< system.mem_ctrl_1.memoryStateTime::ACT 51070000 # Time in different power states
---
> system.mem_ctrl_1.memoryStateTime::ACT 52384500 # Time in different power states
254,255c253,254
< system.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
---
> system.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
257,258c256,257
< system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
---
> system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
260,261c259,260
< system.cpu.pwrStateResidencyTicks::ON 55844000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 55844 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 56435000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 56435 # number of cpu cycles simulated
282c281
< system.cpu.num_busy_cycles 55843.999000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 56434.999000 # Number of busy cycles
321c320
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
323c322
< system.cpu.dcache.tags.tagsinuse 81.671640 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 81.661133 # Cycle average of tags in use
328,330c327,329
< system.cpu.dcache.tags.occ_blocks::cpu.data 81.671640 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.079757 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.079757 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 81.661133 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.079747 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.079747 # Average percentage of cache occupancy
337c336
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
354,361c353,360
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 6006000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 6006000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 8260000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 8260000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 14266000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 14266000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 14266000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 14266000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 6076000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 6076000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 8376000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 8376000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 14452000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 14452000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 14452000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 14452000 # number of overall miss cycles
378,385c377,384
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 107250 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 107250 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 104556.962025 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 104556.962025 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 105674.074074 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 105674.074074 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 105674.074074 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 105674.074074 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 108500 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 108500 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 106025.316456 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 106025.316456 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 107051.851852 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 107051.851852 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 107051.851852 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 107051.851852 # average overall miss latency
400,407c399,406
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5894000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5894000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8102000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 8102000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13996000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 13996000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13996000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 13996000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5964000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5964000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8218000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 8218000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14182000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 14182000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14182000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 14182000 # number of overall MSHR miss cycles
416,424c415,423
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 105250 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 105250 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102556.962025 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102556.962025 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 106500 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 106500 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 104025.316456 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 104025.316456 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 105051.851852 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 105051.851852 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 105051.851852 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 105051.851852 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
426c425
< system.cpu.icache.tags.tagsinuse 91.239705 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 91.248553 # Cycle average of tags in use
431,433c430,432
< system.cpu.icache.tags.occ_blocks::cpu.inst 91.239705 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.356405 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.356405 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 91.248553 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.356440 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.356440 # Average percentage of cache occupancy
435,436c434,435
< system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id
440c439
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
453,458c452,457
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 23702000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 23702000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 23702000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 23702000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 23702000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 23702000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 24107000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 24107000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 24107000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 24107000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 24107000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 24107000 # number of overall miss cycles
471,476c470,475
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100859.574468 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 100859.574468 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 100859.574468 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 100859.574468 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 100859.574468 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 100859.574468 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 102582.978723 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 102582.978723 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 102582.978723 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 102582.978723 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 102582.978723 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 102582.978723 # average overall miss latency
489,494c488,493
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23232000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 23232000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23232000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 23232000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23232000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 23232000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23637000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 23637000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23637000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 23637000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23637000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 23637000 # number of overall MSHR miss cycles
501,506c500,505
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98859.574468 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98859.574468 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 100582.978723 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 100582.978723 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 100582.978723 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 100582.978723 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 100582.978723 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 100582.978723 # average overall mshr miss latency
513c512
< system.l2bus.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
---
> system.l2bus.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
541c540
< system.l2bus.respLayer0.utilization 1.3 # Layer utilization (%)
---
> system.l2bus.respLayer0.utilization 1.2 # Layer utilization (%)
544c543
< system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
546c545
< system.l2cache.tags.tagsinuse 135.848259 # Cycle average of tags in use
---
> system.l2cache.tags.tagsinuse 188.623694 # Cycle average of tags in use
548,549c547,548
< system.l2cache.tags.sampled_refs 285 # Sample count of references to valid blocks.
< system.l2cache.tags.avg_refs 0.224561 # Average number of references to valid blocks.
---
> system.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks.
> system.l2cache.tags.avg_refs 0.175824 # Average number of references to valid blocks.
551,559c550,558
< system.l2cache.tags.occ_blocks::cpu.inst 106.898398 # Average occupied blocks per requestor
< system.l2cache.tags.occ_blocks::cpu.data 28.949861 # Average occupied blocks per requestor
< system.l2cache.tags.occ_percent::cpu.inst 0.026098 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::cpu.data 0.007068 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::total 0.033166 # Average percentage of cache occupancy
< system.l2cache.tags.occ_task_id_blocks::1024 285 # Occupied blocks per task id
< system.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
< system.l2cache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id
< system.l2cache.tags.occ_task_id_percent::1024 0.069580 # Percentage of cache occupancy per task id
---
> system.l2cache.tags.occ_blocks::cpu.inst 106.912326 # Average occupied blocks per requestor
> system.l2cache.tags.occ_blocks::cpu.data 81.711368 # Average occupied blocks per requestor
> system.l2cache.tags.occ_percent::cpu.inst 0.026102 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::cpu.data 0.019949 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::total 0.046051 # Average percentage of cache occupancy
> system.l2cache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id
> system.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
> system.l2cache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id
> system.l2cache.tags.occ_task_id_percent::1024 0.088867 # Percentage of cache occupancy per task id
562c561
< system.l2cache.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
580,590c579,589
< system.l2cache.ReadExReq_miss_latency::cpu.data 7865000 # number of ReadExReq miss cycles
< system.l2cache.ReadExReq_miss_latency::total 7865000 # number of ReadExReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22399000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.data 5726000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::total 28125000 # number of ReadSharedReq miss cycles
< system.l2cache.demand_miss_latency::cpu.inst 22399000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::cpu.data 13591000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::total 35990000 # number of demand (read+write) miss cycles
< system.l2cache.overall_miss_latency::cpu.inst 22399000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::cpu.data 13591000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::total 35990000 # number of overall miss cycles
---
> system.l2cache.ReadExReq_miss_latency::cpu.data 7981000 # number of ReadExReq miss cycles
> system.l2cache.ReadExReq_miss_latency::total 7981000 # number of ReadExReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22804000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.data 5796000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::total 28600000 # number of ReadSharedReq miss cycles
> system.l2cache.demand_miss_latency::cpu.inst 22804000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::cpu.data 13777000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::total 36581000 # number of demand (read+write) miss cycles
> system.l2cache.overall_miss_latency::cpu.inst 22804000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::cpu.data 13777000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::total 36581000 # number of overall miss cycles
613,623c612,622
< system.l2cache.ReadExReq_avg_miss_latency::cpu.data 99556.962025 # average ReadExReq miss latency
< system.l2cache.ReadExReq_avg_miss_latency::total 99556.962025 # average ReadExReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97812.227074 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102250 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::total 98684.210526 # average ReadSharedReq miss latency
< system.l2cache.demand_avg_miss_latency::cpu.inst 97812.227074 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::cpu.data 100674.074074 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::total 98873.626374 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.inst 97812.227074 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.data 100674.074074 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::total 98873.626374 # average overall miss latency
---
> system.l2cache.ReadExReq_avg_miss_latency::cpu.data 101025.316456 # average ReadExReq miss latency
> system.l2cache.ReadExReq_avg_miss_latency::total 101025.316456 # average ReadExReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 99580.786026 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103500 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::total 100350.877193 # average ReadSharedReq miss latency
> system.l2cache.demand_avg_miss_latency::cpu.inst 99580.786026 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::cpu.data 102051.851852 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::total 100497.252747 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.inst 99580.786026 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.data 102051.851852 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::total 100497.252747 # average overall miss latency
641,651c640,650
< system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6285000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadExReq_mshr_miss_latency::total 6285000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17819000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4606000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::total 22425000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.inst 17819000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.data 10891000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::total 28710000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.inst 17819000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.data 10891000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::total 28710000 # number of overall MSHR miss cycles
---
> system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6401000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadExReq_mshr_miss_latency::total 6401000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 18224000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4676000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::total 22900000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.inst 18224000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.data 11077000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::total 29301000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.inst 18224000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.data 11077000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::total 29301000 # number of overall MSHR miss cycles
663,674c662,679
< system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79556.962025 # average ReadExReq mshr miss latency
< system.l2cache.ReadExReq_avg_mshr_miss_latency::total 79556.962025 # average ReadExReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77812.227074 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82250 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78684.210526 # average ReadSharedReq mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency
< system.membus.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81025.316456 # average ReadExReq mshr miss latency
> system.l2cache.ReadExReq_avg_mshr_miss_latency::total 81025.316456 # average ReadExReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 79580.786026 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83500 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80350.877193 # average ReadSharedReq mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79580.786026 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.data 82051.851852 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::total 80497.252747 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79580.786026 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.data 82051.851852 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::total 80497.252747 # average overall mshr miss latency
> system.membus.snoop_filter.tot_requests 364 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states
698,699c703,704
< system.membus.reqLayer2.utilization 0.7 # Layer utilization (%)
< system.membus.respLayer0.occupancy 1952750 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.utilization 0.6 # Layer utilization (%)
> system.membus.respLayer0.occupancy 1954250 # Layer occupancy (ticks)