| config.ini (11570:4aac82f10951) | config.ini (11680:b4d943429dc6) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 9 unchanged lines hidden (view full) --- 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 9 unchanged lines hidden (view full) --- 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing |
| 26mem_ranges=0:536870911 | 26mem_ranges=0:536870911:0:0:0:0 |
| 27memories=system.mem_ctrl 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null --- 66 unchanged lines hidden (view full) --- 101type=DerivedClockDomain 102clk_divider=16 103clk_domain=system.clk_domain 104eventq_index=0 105 106[system.cpu.dcache] 107type=Cache 108children=tags | 27memories=system.mem_ctrl 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null --- 66 unchanged lines hidden (view full) --- 101type=DerivedClockDomain 102clk_divider=16 103clk_domain=system.clk_domain 104eventq_index=0 105 106[system.cpu.dcache] 107type=Cache 108children=tags |
| 109addr_ranges=0:18446744073709551615 | 109addr_ranges=0:18446744073709551615:0:0:0:0 |
| 110assoc=2 111clk_domain=system.clk_domain 112clusivity=mostly_incl 113default_p_state=UNDEFINED 114demand_mshr_reserve=1 115eventq_index=0 116hit_latency=2 117is_read_only=false --- 48 unchanged lines hidden (view full) --- 166p_state_clk_gate_max=1000000000000 167p_state_clk_gate_min=1000 168power_model=Null 169system=system 170 171[system.cpu.icache] 172type=Cache 173children=tags | 110assoc=2 111clk_domain=system.clk_domain 112clusivity=mostly_incl 113default_p_state=UNDEFINED 114demand_mshr_reserve=1 115eventq_index=0 116hit_latency=2 117is_read_only=false --- 48 unchanged lines hidden (view full) --- 166p_state_clk_gate_max=1000000000000 167p_state_clk_gate_min=1000 168power_model=Null 169system=system 170 171[system.cpu.icache] 172type=Cache 173children=tags |
| 174addr_ranges=0:18446744073709551615 | 174addr_ranges=0:18446744073709551615:0:0:0:0 |
| 175assoc=2 176clk_domain=system.clk_domain 177clusivity=mostly_incl 178default_p_state=UNDEFINED 179demand_mshr_reserve=1 180eventq_index=0 181hit_latency=2 182is_read_only=false --- 133 unchanged lines hidden (view full) --- 316eventq_index=0 317lookup_latency=0 318max_capacity=8388608 319system=system 320 321[system.l2cache] 322type=Cache 323children=tags | 175assoc=2 176clk_domain=system.clk_domain 177clusivity=mostly_incl 178default_p_state=UNDEFINED 179demand_mshr_reserve=1 180eventq_index=0 181hit_latency=2 182is_read_only=false --- 133 unchanged lines hidden (view full) --- 316eventq_index=0 317lookup_latency=0 318max_capacity=8388608 319system=system 320 321[system.l2cache] 322type=Cache 323children=tags |
| 324addr_ranges=0:18446744073709551615 | 324addr_ranges=0:18446744073709551615:0:0:0:0 |
| 325assoc=8 326clk_domain=system.clk_domain 327clusivity=mostly_incl 328default_p_state=UNDEFINED 329demand_mshr_reserve=1 330eventq_index=0 331hit_latency=20 332is_read_only=false --- 28 unchanged lines hidden (view full) --- 361p_state_clk_gate_max=1000000000000 362p_state_clk_gate_min=1000 363power_model=Null 364sequential_access=false 365size=262144 366 367[system.mem_ctrl] 368type=DRAMCtrl | 325assoc=8 326clk_domain=system.clk_domain 327clusivity=mostly_incl 328default_p_state=UNDEFINED 329demand_mshr_reserve=1 330eventq_index=0 331hit_latency=20 332is_read_only=false --- 28 unchanged lines hidden (view full) --- 361p_state_clk_gate_max=1000000000000 362p_state_clk_gate_min=1000 363power_model=Null 364sequential_access=false 365size=262144 366 367[system.mem_ctrl] 368type=DRAMCtrl |
| 369IDD0=0.075000 | 369IDD0=0.055000 |
| 370IDD02=0.000000 | 370IDD02=0.000000 |
| 371IDD2N=0.050000 | 371IDD2N=0.032000 |
| 372IDD2N2=0.000000 373IDD2P0=0.000000 374IDD2P02=0.000000 | 372IDD2N2=0.000000 373IDD2P0=0.000000 374IDD2P02=0.000000 |
| 375IDD2P1=0.000000 | 375IDD2P1=0.032000 |
| 376IDD2P12=0.000000 | 376IDD2P12=0.000000 |
| 377IDD3N=0.057000 | 377IDD3N=0.038000 |
| 378IDD3N2=0.000000 379IDD3P0=0.000000 380IDD3P02=0.000000 | 378IDD3N2=0.000000 379IDD3P0=0.000000 380IDD3P02=0.000000 |
| 381IDD3P1=0.000000 | 381IDD3P1=0.038000 |
| 382IDD3P12=0.000000 | 382IDD3P12=0.000000 |
| 383IDD4R=0.187000 | 383IDD4R=0.157000 |
| 384IDD4R2=0.000000 | 384IDD4R2=0.000000 |
| 385IDD4W=0.165000 | 385IDD4W=0.125000 |
| 386IDD4W2=0.000000 | 386IDD4W2=0.000000 |
| 387IDD5=0.220000 | 387IDD5=0.235000 |
| 388IDD52=0.000000 | 388IDD52=0.000000 |
| 389IDD6=0.000000 | 389IDD6=0.020000 |
| 390IDD62=0.000000 391VDD=1.500000 392VDD2=0.000000 393activation_limit=4 394addr_mapping=RoRaBaCoCh 395bank_groups_per_rank=0 396banks_per_rank=8 397burst_length=8 398channels=1 399clk_domain=system.clk_domain 400conf_table_reported=true 401default_p_state=UNDEFINED 402device_bus_width=8 403device_rowbuffer_size=1024 404device_size=536870912 405devices_per_rank=8 406dll=true 407eventq_index=0 408in_addr_map=true | 390IDD62=0.000000 391VDD=1.500000 392VDD2=0.000000 393activation_limit=4 394addr_mapping=RoRaBaCoCh 395bank_groups_per_rank=0 396banks_per_rank=8 397burst_length=8 398channels=1 399clk_domain=system.clk_domain 400conf_table_reported=true 401default_p_state=UNDEFINED 402device_bus_width=8 403device_rowbuffer_size=1024 404device_size=536870912 405devices_per_rank=8 406dll=true 407eventq_index=0 408in_addr_map=true |
| 409kvm_map=true |
|
| 409max_accesses_per_row=16 410mem_sched_policy=frfcfs 411min_writes_per_switch=16 412null=false 413p_state_clk_gate_bins=20 414p_state_clk_gate_max=1000000000000 415p_state_clk_gate_min=1000 416page_policy=open_adaptive 417power_model=Null | 410max_accesses_per_row=16 411mem_sched_policy=frfcfs 412min_writes_per_switch=16 413null=false 414p_state_clk_gate_bins=20 415p_state_clk_gate_max=1000000000000 416p_state_clk_gate_min=1000 417page_policy=open_adaptive 418power_model=Null |
| 418range=0:536870911 | 419range=0:536870911:0:0:0:0 |
| 419ranks_per_channel=2 420read_buffer_size=32 421static_backend_latency=10000 422static_frontend_latency=10000 423tBURST=5000 424tCCD_L=0 425tCK=1250 426tCL=13750 --- 5 unchanged lines hidden (view full) --- 432tRP=13750 433tRRD=6000 434tRRD_L=0 435tRTP=7500 436tRTW=2500 437tWR=15000 438tWTR=7500 439tXAW=30000 | 420ranks_per_channel=2 421read_buffer_size=32 422static_backend_latency=10000 423static_frontend_latency=10000 424tBURST=5000 425tCCD_L=0 426tCK=1250 427tCL=13750 --- 5 unchanged lines hidden (view full) --- 433tRP=13750 434tRRD=6000 435tRRD_L=0 436tRTP=7500 437tRTW=2500 438tWR=15000 439tWTR=7500 440tXAW=30000 |
| 440tXP=0 | 441tXP=6000 |
| 441tXPDLL=0 | 442tXPDLL=0 |
| 442tXS=0 | 443tXS=270000 |
| 443tXSDLL=0 444write_buffer_size=64 445write_high_thresh_perc=85 446write_low_thresh_perc=50 447port=system.membus.master[2] 448 449[system.membus] 450type=CoherentXBar | 444tXSDLL=0 445write_buffer_size=64 446write_high_thresh_perc=85 447write_low_thresh_perc=50 448port=system.membus.master[2] 449 450[system.membus] 451type=CoherentXBar |
| 452children=snoop_filter |
|
| 451clk_domain=system.clk_domain 452default_p_state=UNDEFINED 453eventq_index=0 454forward_latency=4 455frontend_latency=3 456p_state_clk_gate_bins=20 457p_state_clk_gate_max=1000000000000 458p_state_clk_gate_min=1000 459point_of_coherency=true 460power_model=Null 461response_latency=2 | 453clk_domain=system.clk_domain 454default_p_state=UNDEFINED 455eventq_index=0 456forward_latency=4 457frontend_latency=3 458p_state_clk_gate_bins=20 459p_state_clk_gate_max=1000000000000 460p_state_clk_gate_min=1000 461point_of_coherency=true 462power_model=Null 463response_latency=2 |
| 462snoop_filter=Null | 464snoop_filter=system.membus.snoop_filter |
| 463snoop_response_latency=4 464system=system 465use_default_range=false 466width=16 467master=system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.mem_ctrl.port 468slave=system.l2cache.mem_side system.cpu.interrupts.int_master system.system_port 469 | 465snoop_response_latency=4 466system=system 467use_default_range=false 468width=16 469master=system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.mem_ctrl.port 470slave=system.l2cache.mem_side system.cpu.interrupts.int_master system.system_port 471 |
| 472[system.membus.snoop_filter] 473type=SnoopFilter 474eventq_index=0 475lookup_latency=1 476max_capacity=8388608 477system=system 478 |
|