1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

--- 9 unchanged lines hidden (view full) ---

18eventq_index=0
19exit_on_work_items=false
20init_param=0
21kernel=
22kernel_addr_check=true
23load_addr_mask=1099511627775
24load_offset=0
25mem_mode=timing
26mem_ranges=0:536870911
27memories=system.mem_ctrl
28mmap_using_noreserve=false
29multi_thread=false
30num_work_ids=16
31p_state_clk_gate_bins=20
32p_state_clk_gate_max=1000000000000
33p_state_clk_gate_min=1000
34power_model=Null

--- 159 unchanged lines hidden (view full) ---

194domains=
195enable=false
196eventq_index=0
197sys_clk_domain=system.clk_domain
198transition_latency=100000000
199
200[system.mem_ctrl]
201type=DRAMCtrl
202IDD0=0.075000
203IDD02=0.000000
204IDD2N=0.050000
205IDD2N2=0.000000
206IDD2P0=0.000000
207IDD2P02=0.000000
208IDD2P1=0.000000
209IDD2P12=0.000000
210IDD3N=0.057000
211IDD3N2=0.000000
212IDD3P0=0.000000
213IDD3P02=0.000000
214IDD3P1=0.000000
215IDD3P12=0.000000
216IDD4R=0.187000
217IDD4R2=0.000000
218IDD4W=0.165000
219IDD4W2=0.000000
220IDD5=0.220000
221IDD52=0.000000
222IDD6=0.000000
223IDD62=0.000000
224VDD=1.500000
225VDD2=0.000000
226activation_limit=4
227addr_mapping=RoRaBaCoCh
228bank_groups_per_rank=0
229banks_per_rank=8
230burst_length=8
231channels=1
232clk_domain=system.clk_domain
233conf_table_reported=true
234default_p_state=UNDEFINED
235device_bus_width=8
236device_rowbuffer_size=1024
237device_size=536870912
238devices_per_rank=8
239dll=true
240eventq_index=0
241in_addr_map=true
242max_accesses_per_row=16
243mem_sched_policy=frfcfs
244min_writes_per_switch=16
245null=false
246p_state_clk_gate_bins=20
247p_state_clk_gate_max=1000000000000
248p_state_clk_gate_min=1000
249page_policy=open_adaptive
250power_model=Null
251range=0:536870911
252ranks_per_channel=2
253read_buffer_size=32
254static_backend_latency=10000
255static_frontend_latency=10000
256tBURST=5000
257tCCD_L=0
258tCK=1250
259tCL=13750

--- 5 unchanged lines hidden (view full) ---

265tRP=13750
266tRRD=6000
267tRRD_L=0
268tRTP=7500
269tRTW=2500
270tWR=15000
271tWTR=7500
272tXAW=30000
273tXP=0
274tXPDLL=0
275tXS=0
276tXSDLL=0
277write_buffer_size=64
278write_high_thresh_perc=85
279write_low_thresh_perc=50
280port=system.membus.master[2]
281
282[system.membus]
283type=CoherentXBar
284clk_domain=system.clk_domain
285default_p_state=UNDEFINED
286eventq_index=0
287forward_latency=4
288frontend_latency=3
289p_state_clk_gate_bins=20
290p_state_clk_gate_max=1000000000000
291p_state_clk_gate_min=1000
292point_of_coherency=true
293power_model=Null
294response_latency=2
295snoop_filter=Null
296snoop_response_latency=4
297system=system
298use_default_range=false
299width=16
300master=system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.mem_ctrl.port
301slave=system.cpu.icache_port system.cpu.dcache_port system.cpu.interrupts.int_master system.system_port
302