| stats.txt (11606:6b749761c398) | stats.txt (11680:b4d943429dc6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000054 # Number of seconds simulated 4sim_ticks 53605000 # Number of ticks simulated 5final_tick 53605000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000057 # Number of seconds simulated 4sim_ticks 56511000 # Number of ticks simulated 5final_tick 56511000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 205629 # Simulator instruction rate (inst/s) 8host_op_rate 205519 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1984690430 # Simulator tick rate (ticks/s) 10host_mem_usage 637752 # Number of bytes of host memory used 11host_seconds 0.03 # Real time elapsed on the host | 7host_inst_rate 292382 # Simulator instruction rate (inst/s) 8host_op_rate 292023 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2971184542 # Simulator tick rate (ticks/s) 10host_mem_usage 636424 # Number of bytes of host memory used 11host_seconds 0.02 # Real time elapsed on the host |
| 12sim_insts 5548 # Number of instructions simulated 13sim_ops 5548 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 5548 # Number of instructions simulated 13sim_ops 5548 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states | 16system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states |
| 17system.mem_ctrl.bytes_read::cpu.inst 16448 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory 19system.mem_ctrl.bytes_read::total 25216 # Number of bytes read from this memory 20system.mem_ctrl.bytes_inst_read::cpu.inst 16448 # Number of instructions bytes read from this memory 21system.mem_ctrl.bytes_inst_read::total 16448 # Number of instructions bytes read from this memory 22system.mem_ctrl.num_reads::cpu.inst 257 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory 24system.mem_ctrl.num_reads::total 394 # Number of read requests responded to by this memory | 17system.mem_ctrl.bytes_read::cpu.inst 16448 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory 19system.mem_ctrl.bytes_read::total 25216 # Number of bytes read from this memory 20system.mem_ctrl.bytes_inst_read::cpu.inst 16448 # Number of instructions bytes read from this memory 21system.mem_ctrl.bytes_inst_read::total 16448 # Number of instructions bytes read from this memory 22system.mem_ctrl.num_reads::cpu.inst 257 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory 24system.mem_ctrl.num_reads::total 394 # Number of read requests responded to by this memory |
| 25system.mem_ctrl.bw_read::cpu.inst 306837049 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrl.bw_read::cpu.data 163566831 # Total read bandwidth from this memory (bytes/s) 27system.mem_ctrl.bw_read::total 470403880 # Total read bandwidth from this memory (bytes/s) 28system.mem_ctrl.bw_inst_read::cpu.inst 306837049 # Instruction read bandwidth from this memory (bytes/s) 29system.mem_ctrl.bw_inst_read::total 306837049 # Instruction read bandwidth from this memory (bytes/s) 30system.mem_ctrl.bw_total::cpu.inst 306837049 # Total bandwidth to/from this memory (bytes/s) 31system.mem_ctrl.bw_total::cpu.data 163566831 # Total bandwidth to/from this memory (bytes/s) 32system.mem_ctrl.bw_total::total 470403880 # Total bandwidth to/from this memory (bytes/s) | 25system.mem_ctrl.bw_read::cpu.inst 291058378 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrl.bw_read::cpu.data 155155633 # Total read bandwidth from this memory (bytes/s) 27system.mem_ctrl.bw_read::total 446214011 # Total read bandwidth from this memory (bytes/s) 28system.mem_ctrl.bw_inst_read::cpu.inst 291058378 # Instruction read bandwidth from this memory (bytes/s) 29system.mem_ctrl.bw_inst_read::total 291058378 # Instruction read bandwidth from this memory (bytes/s) 30system.mem_ctrl.bw_total::cpu.inst 291058378 # Total bandwidth to/from this memory (bytes/s) 31system.mem_ctrl.bw_total::cpu.data 155155633 # Total bandwidth to/from this memory (bytes/s) 32system.mem_ctrl.bw_total::total 446214011 # Total bandwidth to/from this memory (bytes/s) |
| 33system.mem_ctrl.readReqs 394 # Number of read requests accepted 34system.mem_ctrl.writeReqs 0 # Number of write requests accepted 35system.mem_ctrl.readBursts 394 # Number of DRAM read bursts, including those serviced by the write queue 36system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.mem_ctrl.bytesReadDRAM 25216 # Total number of bytes read from DRAM 38system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM 40system.mem_ctrl.bytesReadSys 25216 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts 72system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts 73system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts 74system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts 75system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts 76system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts 77system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry 78system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry | 33system.mem_ctrl.readReqs 394 # Number of read requests accepted 34system.mem_ctrl.writeReqs 0 # Number of write requests accepted 35system.mem_ctrl.readBursts 394 # Number of DRAM read bursts, including those serviced by the write queue 36system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.mem_ctrl.bytesReadDRAM 25216 # Total number of bytes read from DRAM 38system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM 40system.mem_ctrl.bytesReadSys 25216 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts 72system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts 73system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts 74system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts 75system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts 76system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts 77system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry 78system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry |
| 79system.mem_ctrl.totGap 53508000 # Total gap between requests | 79system.mem_ctrl.totGap 56394000 # Total gap between requests |
| 80system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) 81system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) 82system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) 83system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) 84system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) 85system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) 86system.mem_ctrl.readPktSize::6 394 # Read request sizes (log2) 87system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) --- 94 unchanged lines hidden (view full) --- 182system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see | 80system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) 81system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) 82system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) 83system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) 84system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) 85system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) 86system.mem_ctrl.readPktSize::6 394 # Read request sizes (log2) 87system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) --- 94 unchanged lines hidden (view full) --- 182system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 190system.mem_ctrl.bytesPerActivate::samples 92 # Bytes accessed per row activation 191system.mem_ctrl.bytesPerActivate::mean 246.260870 # Bytes accessed per row activation 192system.mem_ctrl.bytesPerActivate::gmean 176.635417 # Bytes accessed per row activation 193system.mem_ctrl.bytesPerActivate::stdev 203.037423 # Bytes accessed per row activation 194system.mem_ctrl.bytesPerActivate::64-127 28 30.43% 30.43% # Bytes accessed per row activation 195system.mem_ctrl.bytesPerActivate::128-191 15 16.30% 46.74% # Bytes accessed per row activation 196system.mem_ctrl.bytesPerActivate::192-255 11 11.96% 58.70% # Bytes accessed per row activation 197system.mem_ctrl.bytesPerActivate::256-319 8 8.70% 67.39% # Bytes accessed per row activation 198system.mem_ctrl.bytesPerActivate::320-383 6 6.52% 73.91% # Bytes accessed per row activation 199system.mem_ctrl.bytesPerActivate::384-447 7 7.61% 81.52% # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::448-511 3 3.26% 84.78% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::512-575 3 3.26% 88.04% # Bytes accessed per row activation 202system.mem_ctrl.bytesPerActivate::576-639 6 6.52% 94.57% # Bytes accessed per row activation 203system.mem_ctrl.bytesPerActivate::640-703 2 2.17% 96.74% # Bytes accessed per row activation 204system.mem_ctrl.bytesPerActivate::768-831 1 1.09% 97.83% # Bytes accessed per row activation 205system.mem_ctrl.bytesPerActivate::896-959 2 2.17% 100.00% # Bytes accessed per row activation 206system.mem_ctrl.bytesPerActivate::total 92 # Bytes accessed per row activation 207system.mem_ctrl.totQLat 2887500 # Total ticks spent queuing 208system.mem_ctrl.totMemAccLat 10275000 # Total ticks spent from burst creation until serviced by the DRAM | 190system.mem_ctrl.bytesPerActivate::samples 98 # Bytes accessed per row activation 191system.mem_ctrl.bytesPerActivate::mean 248.816327 # Bytes accessed per row activation 192system.mem_ctrl.bytesPerActivate::gmean 183.748429 # Bytes accessed per row activation 193system.mem_ctrl.bytesPerActivate::stdev 196.431638 # Bytes accessed per row activation 194system.mem_ctrl.bytesPerActivate::0-127 26 26.53% 26.53% # Bytes accessed per row activation 195system.mem_ctrl.bytesPerActivate::128-255 31 31.63% 58.16% # Bytes accessed per row activation 196system.mem_ctrl.bytesPerActivate::256-383 15 15.31% 73.47% # Bytes accessed per row activation 197system.mem_ctrl.bytesPerActivate::384-511 13 13.27% 86.73% # Bytes accessed per row activation 198system.mem_ctrl.bytesPerActivate::512-639 9 9.18% 95.92% # Bytes accessed per row activation 199system.mem_ctrl.bytesPerActivate::640-767 2 2.04% 97.96% # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::896-1023 1 1.02% 98.98% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::1024-1151 1 1.02% 100.00% # Bytes accessed per row activation 202system.mem_ctrl.bytesPerActivate::total 98 # Bytes accessed per row activation 203system.mem_ctrl.totQLat 5793000 # Total ticks spent queuing 204system.mem_ctrl.totMemAccLat 13180500 # Total ticks spent from burst creation until serviced by the DRAM |
| 209system.mem_ctrl.totBusLat 1970000 # Total ticks spent in databus transfers | 205system.mem_ctrl.totBusLat 1970000 # Total ticks spent in databus transfers |
| 210system.mem_ctrl.avgQLat 7328.68 # Average queueing delay per DRAM burst | 206system.mem_ctrl.avgQLat 14703.05 # Average queueing delay per DRAM burst |
| 211system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 212system.mem_ctrl.avgMemAccLat 26078.68 # Average memory access latency per DRAM burst 213system.mem_ctrl.avgRdBW 470.40 # Average DRAM read bandwidth in MiByte/s | 208system.mem_ctrl.avgMemAccLat 33453.05 # Average memory access latency per DRAM burst 209system.mem_ctrl.avgRdBW 446.21 # Average DRAM read bandwidth in MiByte/s |
| 214system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 210system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 215system.mem_ctrl.avgRdBWSys 470.40 # Average system read bandwidth in MiByte/s | 211system.mem_ctrl.avgRdBWSys 446.21 # Average system read bandwidth in MiByte/s |
| 216system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 217system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 212system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 218system.mem_ctrl.busUtil 3.68 # Data bus utilization in percentage 219system.mem_ctrl.busUtilRead 3.68 # Data bus utilization in percentage for reads | 214system.mem_ctrl.busUtil 3.49 # Data bus utilization in percentage 215system.mem_ctrl.busUtilRead 3.49 # Data bus utilization in percentage for reads |
| 220system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes 221system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing 222system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing | 216system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing 218system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 223system.mem_ctrl.readRowHits 296 # Number of row buffer hits during reads | 219system.mem_ctrl.readRowHits 292 # Number of row buffer hits during reads |
| 224system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes | 220system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes |
| 225system.mem_ctrl.readRowHitRate 75.13 # Row buffer hit rate for reads | 221system.mem_ctrl.readRowHitRate 74.11 # Row buffer hit rate for reads |
| 226system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes | 222system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes |
| 227system.mem_ctrl.avgGap 135807.11 # Average gap between requests 228system.mem_ctrl.pageHitRate 75.13 # Row buffer hit rate, read and write combined 229system.mem_ctrl_0.actEnergy 378000 # Energy for activate commands per rank (pJ) 230system.mem_ctrl_0.preEnergy 206250 # Energy for precharge commands per rank (pJ) 231system.mem_ctrl_0.readEnergy 1614600 # Energy for read commands per rank (pJ) | 223system.mem_ctrl.avgGap 143131.98 # Average gap between requests 224system.mem_ctrl.pageHitRate 74.11 # Row buffer hit rate, read and write combined 225system.mem_ctrl_0.actEnergy 421260 # Energy for activate commands per rank (pJ) 226system.mem_ctrl_0.preEnergy 216315 # Energy for precharge commands per rank (pJ) 227system.mem_ctrl_0.readEnergy 1756440 # Energy for read commands per rank (pJ) |
| 232system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) | 228system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 233system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) 234system.mem_ctrl_0.actBackEnergy 30461940 # Energy for active background per rank (pJ) 235system.mem_ctrl_0.preBackEnergy 1478250 # Energy for precharge background per rank (pJ) 236system.mem_ctrl_0.totalEnergy 37190400 # Total energy per rank (pJ) 237system.mem_ctrl_0.averagePower 791.306152 # Core power per rank (mW) 238system.mem_ctrl_0.memoryStateTime::IDLE 2310750 # Time in different power states 239system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states 240system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states 241system.mem_ctrl_0.memoryStateTime::ACT 43141000 # Time in different power states 242system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states 243system.mem_ctrl_1.actEnergy 272160 # Energy for activate commands per rank (pJ) 244system.mem_ctrl_1.preEnergy 148500 # Energy for precharge commands per rank (pJ) 245system.mem_ctrl_1.readEnergy 1053000 # Energy for read commands per rank (pJ) | 229system.mem_ctrl_0.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) 230system.mem_ctrl_0.actBackEnergy 4075500 # Energy for active background per rank (pJ) 231system.mem_ctrl_0.preBackEnergy 122880 # Energy for precharge background per rank (pJ) 232system.mem_ctrl_0.actPowerDownEnergy 21123630 # Energy for active power-down per rank (pJ) 233system.mem_ctrl_0.prePowerDownEnergy 357120 # Energy for precharge power-down per rank (pJ) 234system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 235system.mem_ctrl_0.totalEnergy 32375625 # Total energy per rank (pJ) 236system.mem_ctrl_0.averagePower 572.905837 # Core power per rank (mW) 237system.mem_ctrl_0.totalIdleTime 47002000 # Total Idle time Per DRAM Rank 238system.mem_ctrl_0.memoryStateTime::IDLE 71000 # Time in different power states 239system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states 240system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states 241system.mem_ctrl_0.memoryStateTime::PRE_PDN 929250 # Time in different power states 242system.mem_ctrl_0.memoryStateTime::ACT 7357750 # Time in different power states 243system.mem_ctrl_0.memoryStateTime::ACT_PDN 46333000 # Time in different power states 244system.mem_ctrl_1.actEnergy 307020 # Energy for activate commands per rank (pJ) 245system.mem_ctrl_1.preEnergy 155595 # Energy for precharge commands per rank (pJ) 246system.mem_ctrl_1.readEnergy 1056720 # Energy for read commands per rank (pJ) |
| 246system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) | 247system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 247system.mem_ctrl_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) 248system.mem_ctrl_1.actBackEnergy 29252115 # Energy for active background per rank (pJ) 249system.mem_ctrl_1.preBackEnergy 2526750 # Energy for precharge background per rank (pJ) 250system.mem_ctrl_1.totalEnergy 36303885 # Total energy per rank (pJ) 251system.mem_ctrl_1.averagePower 772.793039 # Core power per rank (mW) 252system.mem_ctrl_1.memoryStateTime::IDLE 5312750 # Time in different power states 253system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states 254system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states 255system.mem_ctrl_1.memoryStateTime::ACT 41373250 # Time in different power states 256system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states 257system.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states | 248system.mem_ctrl_1.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) 249system.mem_ctrl_1.actBackEnergy 2785590 # Energy for active background per rank (pJ) 250system.mem_ctrl_1.preBackEnergy 293760 # Energy for precharge background per rank (pJ) 251system.mem_ctrl_1.actPowerDownEnergy 20523420 # Energy for active power-down per rank (pJ) 252system.mem_ctrl_1.prePowerDownEnergy 1777920 # Energy for precharge power-down per rank (pJ) 253system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 254system.mem_ctrl_1.totalEnergy 31202505 # Total energy per rank (pJ) 255system.mem_ctrl_1.averagePower 552.146785 # Core power per rank (mW) 256system.mem_ctrl_1.totalIdleTime 49582750 # Total Idle time Per DRAM Rank 257system.mem_ctrl_1.memoryStateTime::IDLE 557000 # Time in different power states 258system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states 259system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states 260system.mem_ctrl_1.memoryStateTime::PRE_PDN 4629500 # Time in different power states 261system.mem_ctrl_1.memoryStateTime::ACT 4495750 # Time in different power states 262system.mem_ctrl_1.memoryStateTime::ACT_PDN 45008750 # Time in different power states 263system.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states |
| 258system.cpu.workload.num_syscalls 11 # Number of system calls | 264system.cpu.workload.num_syscalls 11 # Number of system calls |
| 259system.cpu.pwrStateResidencyTicks::ON 53605000 # Cumulative time (in ticks) in various power states 260system.cpu.numCycles 53605 # number of cpu cycles simulated | 265system.cpu.pwrStateResidencyTicks::ON 56511000 # Cumulative time (in ticks) in various power states 266system.cpu.numCycles 56511 # number of cpu cycles simulated |
| 261system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 262system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 263system.cpu.committedInsts 5548 # Number of instructions committed 264system.cpu.committedOps 5548 # Number of ops (including micro ops) committed 265system.cpu.num_int_alu_accesses 4660 # Number of integer alu accesses 266system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 267system.cpu.num_func_calls 146 # number of times a function call or return occured 268system.cpu.num_conditional_control_insts 835 # number of instructions that are conditional controls 269system.cpu.num_int_insts 4660 # number of integer instructions 270system.cpu.num_fp_insts 0 # number of float instructions 271system.cpu.num_int_register_reads 10977 # number of times the integer registers were read 272system.cpu.num_int_register_writes 5062 # number of times the integer registers were written 273system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 274system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 275system.cpu.num_mem_refs 1404 # number of memory refs 276system.cpu.num_load_insts 726 # Number of load instructions 277system.cpu.num_store_insts 678 # Number of store instructions 278system.cpu.num_idle_cycles 0.001000 # Number of idle cycles | 267system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 268system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 269system.cpu.committedInsts 5548 # Number of instructions committed 270system.cpu.committedOps 5548 # Number of ops (including micro ops) committed 271system.cpu.num_int_alu_accesses 4660 # Number of integer alu accesses 272system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 273system.cpu.num_func_calls 146 # number of times a function call or return occured 274system.cpu.num_conditional_control_insts 835 # number of instructions that are conditional controls 275system.cpu.num_int_insts 4660 # number of integer instructions 276system.cpu.num_fp_insts 0 # number of float instructions 277system.cpu.num_int_register_reads 10977 # number of times the integer registers were read 278system.cpu.num_int_register_writes 5062 # number of times the integer registers were written 279system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 280system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 281system.cpu.num_mem_refs 1404 # number of memory refs 282system.cpu.num_load_insts 726 # Number of load instructions 283system.cpu.num_store_insts 678 # Number of store instructions 284system.cpu.num_idle_cycles 0.001000 # Number of idle cycles |
| 279system.cpu.num_busy_cycles 53604.999000 # Number of busy cycles | 285system.cpu.num_busy_cycles 56510.999000 # Number of busy cycles |
| 280system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 281system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 282system.cpu.Branches 1187 # Number of branches fetched 283system.cpu.op_class::No_OpClass 173 3.09% 3.09% # Class of executed instruction 284system.cpu.op_class::IntAlu 4014 71.79% 74.89% # Class of executed instruction 285system.cpu.op_class::IntMult 0 0.00% 74.89% # Class of executed instruction 286system.cpu.op_class::IntDiv 0 0.00% 74.89% # Class of executed instruction 287system.cpu.op_class::FloatAdd 0 0.00% 74.89% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 310system.cpu.op_class::SimdFloatMult 0 0.00% 74.89% # Class of executed instruction 311system.cpu.op_class::SimdFloatMultAcc 0 0.00% 74.89% # Class of executed instruction 312system.cpu.op_class::SimdFloatSqrt 0 0.00% 74.89% # Class of executed instruction 313system.cpu.op_class::MemRead 726 12.99% 87.87% # Class of executed instruction 314system.cpu.op_class::MemWrite 678 12.13% 100.00% # Class of executed instruction 315system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 316system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 317system.cpu.op_class::total 5591 # Class of executed instruction | 286system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 287system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 288system.cpu.Branches 1187 # Number of branches fetched 289system.cpu.op_class::No_OpClass 173 3.09% 3.09% # Class of executed instruction 290system.cpu.op_class::IntAlu 4014 71.79% 74.89% # Class of executed instruction 291system.cpu.op_class::IntMult 0 0.00% 74.89% # Class of executed instruction 292system.cpu.op_class::IntDiv 0 0.00% 74.89% # Class of executed instruction 293system.cpu.op_class::FloatAdd 0 0.00% 74.89% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 316system.cpu.op_class::SimdFloatMult 0 0.00% 74.89% # Class of executed instruction 317system.cpu.op_class::SimdFloatMultAcc 0 0.00% 74.89% # Class of executed instruction 318system.cpu.op_class::SimdFloatSqrt 0 0.00% 74.89% # Class of executed instruction 319system.cpu.op_class::MemRead 726 12.99% 87.87% # Class of executed instruction 320system.cpu.op_class::MemWrite 678 12.13% 100.00% # Class of executed instruction 321system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 322system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 323system.cpu.op_class::total 5591 # Class of executed instruction |
| 318system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states | 324system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states |
| 319system.cpu.dcache.tags.replacements 0 # number of replacements | 325system.cpu.dcache.tags.replacements 0 # number of replacements |
| 320system.cpu.dcache.tags.tagsinuse 83.787726 # Cycle average of tags in use | 326system.cpu.dcache.tags.tagsinuse 83.847801 # Cycle average of tags in use |
| 321system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. 322system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. 323system.cpu.dcache.tags.avg_refs 9.079710 # Average number of references to valid blocks. 324system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 327system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. 328system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. 329system.cpu.dcache.tags.avg_refs 9.079710 # Average number of references to valid blocks. 330system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 325system.cpu.dcache.tags.occ_blocks::cpu.data 83.787726 # Average occupied blocks per requestor 326system.cpu.dcache.tags.occ_percent::cpu.data 0.081824 # Average percentage of cache occupancy 327system.cpu.dcache.tags.occ_percent::total 0.081824 # Average percentage of cache occupancy | 331system.cpu.dcache.tags.occ_blocks::cpu.data 83.847801 # Average occupied blocks per requestor 332system.cpu.dcache.tags.occ_percent::cpu.data 0.081883 # Average percentage of cache occupancy 333system.cpu.dcache.tags.occ_percent::total 0.081883 # Average percentage of cache occupancy |
| 328system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id 329system.cpu.dcache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id 330system.cpu.dcache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id 331system.cpu.dcache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id 332system.cpu.dcache.tags.tag_accesses 2920 # Number of tag accesses 333system.cpu.dcache.tags.data_accesses 2920 # Number of data accesses | 334system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id 335system.cpu.dcache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id 336system.cpu.dcache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id 337system.cpu.dcache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id 338system.cpu.dcache.tags.tag_accesses 2920 # Number of tag accesses 339system.cpu.dcache.tags.data_accesses 2920 # Number of data accesses |
| 334system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states | 340system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states |
| 335system.cpu.dcache.ReadReq_hits::cpu.data 662 # number of ReadReq hits 336system.cpu.dcache.ReadReq_hits::total 662 # number of ReadReq hits 337system.cpu.dcache.WriteReq_hits::cpu.data 591 # number of WriteReq hits 338system.cpu.dcache.WriteReq_hits::total 591 # number of WriteReq hits 339system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits 340system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits 341system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits 342system.cpu.dcache.overall_hits::total 1253 # number of overall hits 343system.cpu.dcache.ReadReq_misses::cpu.data 56 # number of ReadReq misses 344system.cpu.dcache.ReadReq_misses::total 56 # number of ReadReq misses 345system.cpu.dcache.WriteReq_misses::cpu.data 82 # number of WriteReq misses 346system.cpu.dcache.WriteReq_misses::total 82 # number of WriteReq misses 347system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses 348system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses 349system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses 350system.cpu.dcache.overall_misses::total 138 # number of overall misses | 341system.cpu.dcache.ReadReq_hits::cpu.data 662 # number of ReadReq hits 342system.cpu.dcache.ReadReq_hits::total 662 # number of ReadReq hits 343system.cpu.dcache.WriteReq_hits::cpu.data 591 # number of WriteReq hits 344system.cpu.dcache.WriteReq_hits::total 591 # number of WriteReq hits 345system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits 346system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits 347system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits 348system.cpu.dcache.overall_hits::total 1253 # number of overall hits 349system.cpu.dcache.ReadReq_misses::cpu.data 56 # number of ReadReq misses 350system.cpu.dcache.ReadReq_misses::total 56 # number of ReadReq misses 351system.cpu.dcache.WriteReq_misses::cpu.data 82 # number of WriteReq misses 352system.cpu.dcache.WriteReq_misses::total 82 # number of WriteReq misses 353system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses 354system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses 355system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses 356system.cpu.dcache.overall_misses::total 138 # number of overall misses |
| 351system.cpu.dcache.ReadReq_miss_latency::cpu.data 5756000 # number of ReadReq miss cycles 352system.cpu.dcache.ReadReq_miss_latency::total 5756000 # number of ReadReq miss cycles 353system.cpu.dcache.WriteReq_miss_latency::cpu.data 8522000 # number of WriteReq miss cycles 354system.cpu.dcache.WriteReq_miss_latency::total 8522000 # number of WriteReq miss cycles 355system.cpu.dcache.demand_miss_latency::cpu.data 14278000 # number of demand (read+write) miss cycles 356system.cpu.dcache.demand_miss_latency::total 14278000 # number of demand (read+write) miss cycles 357system.cpu.dcache.overall_miss_latency::cpu.data 14278000 # number of overall miss cycles 358system.cpu.dcache.overall_miss_latency::total 14278000 # number of overall miss cycles | 357system.cpu.dcache.ReadReq_miss_latency::cpu.data 6576000 # number of ReadReq miss cycles 358system.cpu.dcache.ReadReq_miss_latency::total 6576000 # number of ReadReq miss cycles 359system.cpu.dcache.WriteReq_miss_latency::cpu.data 8937000 # number of WriteReq miss cycles 360system.cpu.dcache.WriteReq_miss_latency::total 8937000 # number of WriteReq miss cycles 361system.cpu.dcache.demand_miss_latency::cpu.data 15513000 # number of demand (read+write) miss cycles 362system.cpu.dcache.demand_miss_latency::total 15513000 # number of demand (read+write) miss cycles 363system.cpu.dcache.overall_miss_latency::cpu.data 15513000 # number of overall miss cycles 364system.cpu.dcache.overall_miss_latency::total 15513000 # number of overall miss cycles |
| 359system.cpu.dcache.ReadReq_accesses::cpu.data 718 # number of ReadReq accesses(hits+misses) 360system.cpu.dcache.ReadReq_accesses::total 718 # number of ReadReq accesses(hits+misses) 361system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) 362system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) 363system.cpu.dcache.demand_accesses::cpu.data 1391 # number of demand (read+write) accesses 364system.cpu.dcache.demand_accesses::total 1391 # number of demand (read+write) accesses 365system.cpu.dcache.overall_accesses::cpu.data 1391 # number of overall (read+write) accesses 366system.cpu.dcache.overall_accesses::total 1391 # number of overall (read+write) accesses 367system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.077994 # miss rate for ReadReq accesses 368system.cpu.dcache.ReadReq_miss_rate::total 0.077994 # miss rate for ReadReq accesses 369system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.121842 # miss rate for WriteReq accesses 370system.cpu.dcache.WriteReq_miss_rate::total 0.121842 # miss rate for WriteReq accesses 371system.cpu.dcache.demand_miss_rate::cpu.data 0.099209 # miss rate for demand accesses 372system.cpu.dcache.demand_miss_rate::total 0.099209 # miss rate for demand accesses 373system.cpu.dcache.overall_miss_rate::cpu.data 0.099209 # miss rate for overall accesses 374system.cpu.dcache.overall_miss_rate::total 0.099209 # miss rate for overall accesses | 365system.cpu.dcache.ReadReq_accesses::cpu.data 718 # number of ReadReq accesses(hits+misses) 366system.cpu.dcache.ReadReq_accesses::total 718 # number of ReadReq accesses(hits+misses) 367system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) 368system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) 369system.cpu.dcache.demand_accesses::cpu.data 1391 # number of demand (read+write) accesses 370system.cpu.dcache.demand_accesses::total 1391 # number of demand (read+write) accesses 371system.cpu.dcache.overall_accesses::cpu.data 1391 # number of overall (read+write) accesses 372system.cpu.dcache.overall_accesses::total 1391 # number of overall (read+write) accesses 373system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.077994 # miss rate for ReadReq accesses 374system.cpu.dcache.ReadReq_miss_rate::total 0.077994 # miss rate for ReadReq accesses 375system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.121842 # miss rate for WriteReq accesses 376system.cpu.dcache.WriteReq_miss_rate::total 0.121842 # miss rate for WriteReq accesses 377system.cpu.dcache.demand_miss_rate::cpu.data 0.099209 # miss rate for demand accesses 378system.cpu.dcache.demand_miss_rate::total 0.099209 # miss rate for demand accesses 379system.cpu.dcache.overall_miss_rate::cpu.data 0.099209 # miss rate for overall accesses 380system.cpu.dcache.overall_miss_rate::total 0.099209 # miss rate for overall accesses |
| 375system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102785.714286 # average ReadReq miss latency 376system.cpu.dcache.ReadReq_avg_miss_latency::total 102785.714286 # average ReadReq miss latency 377system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 103926.829268 # average WriteReq miss latency 378system.cpu.dcache.WriteReq_avg_miss_latency::total 103926.829268 # average WriteReq miss latency 379system.cpu.dcache.demand_avg_miss_latency::cpu.data 103463.768116 # average overall miss latency 380system.cpu.dcache.demand_avg_miss_latency::total 103463.768116 # average overall miss latency 381system.cpu.dcache.overall_avg_miss_latency::cpu.data 103463.768116 # average overall miss latency 382system.cpu.dcache.overall_avg_miss_latency::total 103463.768116 # average overall miss latency | 381system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 117428.571429 # average ReadReq miss latency 382system.cpu.dcache.ReadReq_avg_miss_latency::total 117428.571429 # average ReadReq miss latency 383system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108987.804878 # average WriteReq miss latency 384system.cpu.dcache.WriteReq_avg_miss_latency::total 108987.804878 # average WriteReq miss latency 385system.cpu.dcache.demand_avg_miss_latency::cpu.data 112413.043478 # average overall miss latency 386system.cpu.dcache.demand_avg_miss_latency::total 112413.043478 # average overall miss latency 387system.cpu.dcache.overall_avg_miss_latency::cpu.data 112413.043478 # average overall miss latency 388system.cpu.dcache.overall_avg_miss_latency::total 112413.043478 # average overall miss latency |
| 383system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 384system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 385system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 386system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 387system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 388system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 389system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses 390system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses 391system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82 # number of WriteReq MSHR misses 392system.cpu.dcache.WriteReq_mshr_misses::total 82 # number of WriteReq MSHR misses 393system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 394system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses 395system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses 396system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses | 389system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 390system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 391system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 392system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 393system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 394system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 395system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses 396system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses 397system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82 # number of WriteReq MSHR misses 398system.cpu.dcache.WriteReq_mshr_misses::total 82 # number of WriteReq MSHR misses 399system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 400system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses 401system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses 402system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses |
| 397system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5644000 # number of ReadReq MSHR miss cycles 398system.cpu.dcache.ReadReq_mshr_miss_latency::total 5644000 # number of ReadReq MSHR miss cycles 399system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8358000 # number of WriteReq MSHR miss cycles 400system.cpu.dcache.WriteReq_mshr_miss_latency::total 8358000 # number of WriteReq MSHR miss cycles 401system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14002000 # number of demand (read+write) MSHR miss cycles 402system.cpu.dcache.demand_mshr_miss_latency::total 14002000 # number of demand (read+write) MSHR miss cycles 403system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14002000 # number of overall MSHR miss cycles 404system.cpu.dcache.overall_mshr_miss_latency::total 14002000 # number of overall MSHR miss cycles | 403system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6464000 # number of ReadReq MSHR miss cycles 404system.cpu.dcache.ReadReq_mshr_miss_latency::total 6464000 # number of ReadReq MSHR miss cycles 405system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8773000 # number of WriteReq MSHR miss cycles 406system.cpu.dcache.WriteReq_mshr_miss_latency::total 8773000 # number of WriteReq MSHR miss cycles 407system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15237000 # number of demand (read+write) MSHR miss cycles 408system.cpu.dcache.demand_mshr_miss_latency::total 15237000 # number of demand (read+write) MSHR miss cycles 409system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15237000 # number of overall MSHR miss cycles 410system.cpu.dcache.overall_mshr_miss_latency::total 15237000 # number of overall MSHR miss cycles |
| 405system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.077994 # mshr miss rate for ReadReq accesses 406system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.077994 # mshr miss rate for ReadReq accesses 407system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.121842 # mshr miss rate for WriteReq accesses 408system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.121842 # mshr miss rate for WriteReq accesses 409system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.099209 # mshr miss rate for demand accesses 410system.cpu.dcache.demand_mshr_miss_rate::total 0.099209 # mshr miss rate for demand accesses 411system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.099209 # mshr miss rate for overall accesses 412system.cpu.dcache.overall_mshr_miss_rate::total 0.099209 # mshr miss rate for overall accesses | 411system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.077994 # mshr miss rate for ReadReq accesses 412system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.077994 # mshr miss rate for ReadReq accesses 413system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.121842 # mshr miss rate for WriteReq accesses 414system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.121842 # mshr miss rate for WriteReq accesses 415system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.099209 # mshr miss rate for demand accesses 416system.cpu.dcache.demand_mshr_miss_rate::total 0.099209 # mshr miss rate for demand accesses 417system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.099209 # mshr miss rate for overall accesses 418system.cpu.dcache.overall_mshr_miss_rate::total 0.099209 # mshr miss rate for overall accesses |
| 413system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100785.714286 # average ReadReq mshr miss latency 414system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100785.714286 # average ReadReq mshr miss latency 415system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 101926.829268 # average WriteReq mshr miss latency 416system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 101926.829268 # average WriteReq mshr miss latency 417system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101463.768116 # average overall mshr miss latency 418system.cpu.dcache.demand_avg_mshr_miss_latency::total 101463.768116 # average overall mshr miss latency 419system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101463.768116 # average overall mshr miss latency 420system.cpu.dcache.overall_avg_mshr_miss_latency::total 101463.768116 # average overall mshr miss latency 421system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states | 419system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115428.571429 # average ReadReq mshr miss latency 420system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115428.571429 # average ReadReq mshr miss latency 421system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106987.804878 # average WriteReq mshr miss latency 422system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106987.804878 # average WriteReq mshr miss latency 423system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 110413.043478 # average overall mshr miss latency 424system.cpu.dcache.demand_avg_mshr_miss_latency::total 110413.043478 # average overall mshr miss latency 425system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 110413.043478 # average overall mshr miss latency 426system.cpu.dcache.overall_avg_mshr_miss_latency::total 110413.043478 # average overall mshr miss latency 427system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states |
| 422system.cpu.icache.tags.replacements 71 # number of replacements | 428system.cpu.icache.tags.replacements 71 # number of replacements |
| 423system.cpu.icache.tags.tagsinuse 98.163046 # Cycle average of tags in use | 429system.cpu.icache.tags.tagsinuse 98.324434 # Cycle average of tags in use |
| 424system.cpu.icache.tags.total_refs 5333 # Total number of references to valid blocks. 425system.cpu.icache.tags.sampled_refs 259 # Sample count of references to valid blocks. 426system.cpu.icache.tags.avg_refs 20.590734 # Average number of references to valid blocks. 427system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 430system.cpu.icache.tags.total_refs 5333 # Total number of references to valid blocks. 431system.cpu.icache.tags.sampled_refs 259 # Sample count of references to valid blocks. 432system.cpu.icache.tags.avg_refs 20.590734 # Average number of references to valid blocks. 433system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 428system.cpu.icache.tags.occ_blocks::cpu.inst 98.163046 # Average occupied blocks per requestor 429system.cpu.icache.tags.occ_percent::cpu.inst 0.383449 # Average percentage of cache occupancy 430system.cpu.icache.tags.occ_percent::total 0.383449 # Average percentage of cache occupancy | 434system.cpu.icache.tags.occ_blocks::cpu.inst 98.324434 # Average occupied blocks per requestor 435system.cpu.icache.tags.occ_percent::cpu.inst 0.384080 # Average percentage of cache occupancy 436system.cpu.icache.tags.occ_percent::total 0.384080 # Average percentage of cache occupancy |
| 431system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id | 437system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id |
| 432system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id 433system.cpu.icache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id | 438system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 439system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id |
| 434system.cpu.icache.tags.occ_task_id_percent::1024 0.734375 # Percentage of cache occupancy per task id 435system.cpu.icache.tags.tag_accesses 11443 # Number of tag accesses 436system.cpu.icache.tags.data_accesses 11443 # Number of data accesses | 440system.cpu.icache.tags.occ_task_id_percent::1024 0.734375 # Percentage of cache occupancy per task id 441system.cpu.icache.tags.tag_accesses 11443 # Number of tag accesses 442system.cpu.icache.tags.data_accesses 11443 # Number of data accesses |
| 437system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states | 443system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states |
| 438system.cpu.icache.ReadReq_hits::cpu.inst 5333 # number of ReadReq hits 439system.cpu.icache.ReadReq_hits::total 5333 # number of ReadReq hits 440system.cpu.icache.demand_hits::cpu.inst 5333 # number of demand (read+write) hits 441system.cpu.icache.demand_hits::total 5333 # number of demand (read+write) hits 442system.cpu.icache.overall_hits::cpu.inst 5333 # number of overall hits 443system.cpu.icache.overall_hits::total 5333 # number of overall hits 444system.cpu.icache.ReadReq_misses::cpu.inst 259 # number of ReadReq misses 445system.cpu.icache.ReadReq_misses::total 259 # number of ReadReq misses 446system.cpu.icache.demand_misses::cpu.inst 259 # number of demand (read+write) misses 447system.cpu.icache.demand_misses::total 259 # number of demand (read+write) misses 448system.cpu.icache.overall_misses::cpu.inst 259 # number of overall misses 449system.cpu.icache.overall_misses::total 259 # number of overall misses | 444system.cpu.icache.ReadReq_hits::cpu.inst 5333 # number of ReadReq hits 445system.cpu.icache.ReadReq_hits::total 5333 # number of ReadReq hits 446system.cpu.icache.demand_hits::cpu.inst 5333 # number of demand (read+write) hits 447system.cpu.icache.demand_hits::total 5333 # number of demand (read+write) hits 448system.cpu.icache.overall_hits::cpu.inst 5333 # number of overall hits 449system.cpu.icache.overall_hits::total 5333 # number of overall hits 450system.cpu.icache.ReadReq_misses::cpu.inst 259 # number of ReadReq misses 451system.cpu.icache.ReadReq_misses::total 259 # number of ReadReq misses 452system.cpu.icache.demand_misses::cpu.inst 259 # number of demand (read+write) misses 453system.cpu.icache.demand_misses::total 259 # number of demand (read+write) misses 454system.cpu.icache.overall_misses::cpu.inst 259 # number of overall misses 455system.cpu.icache.overall_misses::total 259 # number of overall misses |
| 450system.cpu.icache.ReadReq_miss_latency::cpu.inst 26157000 # number of ReadReq miss cycles 451system.cpu.icache.ReadReq_miss_latency::total 26157000 # number of ReadReq miss cycles 452system.cpu.icache.demand_miss_latency::cpu.inst 26157000 # number of demand (read+write) miss cycles 453system.cpu.icache.demand_miss_latency::total 26157000 # number of demand (read+write) miss cycles 454system.cpu.icache.overall_miss_latency::cpu.inst 26157000 # number of overall miss cycles 455system.cpu.icache.overall_miss_latency::total 26157000 # number of overall miss cycles | 456system.cpu.icache.ReadReq_miss_latency::cpu.inst 27828000 # number of ReadReq miss cycles 457system.cpu.icache.ReadReq_miss_latency::total 27828000 # number of ReadReq miss cycles 458system.cpu.icache.demand_miss_latency::cpu.inst 27828000 # number of demand (read+write) miss cycles 459system.cpu.icache.demand_miss_latency::total 27828000 # number of demand (read+write) miss cycles 460system.cpu.icache.overall_miss_latency::cpu.inst 27828000 # number of overall miss cycles 461system.cpu.icache.overall_miss_latency::total 27828000 # number of overall miss cycles |
| 456system.cpu.icache.ReadReq_accesses::cpu.inst 5592 # number of ReadReq accesses(hits+misses) 457system.cpu.icache.ReadReq_accesses::total 5592 # number of ReadReq accesses(hits+misses) 458system.cpu.icache.demand_accesses::cpu.inst 5592 # number of demand (read+write) accesses 459system.cpu.icache.demand_accesses::total 5592 # number of demand (read+write) accesses 460system.cpu.icache.overall_accesses::cpu.inst 5592 # number of overall (read+write) accesses 461system.cpu.icache.overall_accesses::total 5592 # number of overall (read+write) accesses 462system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.046316 # miss rate for ReadReq accesses 463system.cpu.icache.ReadReq_miss_rate::total 0.046316 # miss rate for ReadReq accesses 464system.cpu.icache.demand_miss_rate::cpu.inst 0.046316 # miss rate for demand accesses 465system.cpu.icache.demand_miss_rate::total 0.046316 # miss rate for demand accesses 466system.cpu.icache.overall_miss_rate::cpu.inst 0.046316 # miss rate for overall accesses 467system.cpu.icache.overall_miss_rate::total 0.046316 # miss rate for overall accesses | 462system.cpu.icache.ReadReq_accesses::cpu.inst 5592 # number of ReadReq accesses(hits+misses) 463system.cpu.icache.ReadReq_accesses::total 5592 # number of ReadReq accesses(hits+misses) 464system.cpu.icache.demand_accesses::cpu.inst 5592 # number of demand (read+write) accesses 465system.cpu.icache.demand_accesses::total 5592 # number of demand (read+write) accesses 466system.cpu.icache.overall_accesses::cpu.inst 5592 # number of overall (read+write) accesses 467system.cpu.icache.overall_accesses::total 5592 # number of overall (read+write) accesses 468system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.046316 # miss rate for ReadReq accesses 469system.cpu.icache.ReadReq_miss_rate::total 0.046316 # miss rate for ReadReq accesses 470system.cpu.icache.demand_miss_rate::cpu.inst 0.046316 # miss rate for demand accesses 471system.cpu.icache.demand_miss_rate::total 0.046316 # miss rate for demand accesses 472system.cpu.icache.overall_miss_rate::cpu.inst 0.046316 # miss rate for overall accesses 473system.cpu.icache.overall_miss_rate::total 0.046316 # miss rate for overall accesses |
| 468system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100992.277992 # average ReadReq miss latency 469system.cpu.icache.ReadReq_avg_miss_latency::total 100992.277992 # average ReadReq miss latency 470system.cpu.icache.demand_avg_miss_latency::cpu.inst 100992.277992 # average overall miss latency 471system.cpu.icache.demand_avg_miss_latency::total 100992.277992 # average overall miss latency 472system.cpu.icache.overall_avg_miss_latency::cpu.inst 100992.277992 # average overall miss latency 473system.cpu.icache.overall_avg_miss_latency::total 100992.277992 # average overall miss latency | 474system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 107444.015444 # average ReadReq miss latency 475system.cpu.icache.ReadReq_avg_miss_latency::total 107444.015444 # average ReadReq miss latency 476system.cpu.icache.demand_avg_miss_latency::cpu.inst 107444.015444 # average overall miss latency 477system.cpu.icache.demand_avg_miss_latency::total 107444.015444 # average overall miss latency 478system.cpu.icache.overall_avg_miss_latency::cpu.inst 107444.015444 # average overall miss latency 479system.cpu.icache.overall_avg_miss_latency::total 107444.015444 # average overall miss latency |
| 474system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 475system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 476system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 477system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 478system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 479system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 480system.cpu.icache.ReadReq_mshr_misses::cpu.inst 259 # number of ReadReq MSHR misses 481system.cpu.icache.ReadReq_mshr_misses::total 259 # number of ReadReq MSHR misses 482system.cpu.icache.demand_mshr_misses::cpu.inst 259 # number of demand (read+write) MSHR misses 483system.cpu.icache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses 484system.cpu.icache.overall_mshr_misses::cpu.inst 259 # number of overall MSHR misses 485system.cpu.icache.overall_mshr_misses::total 259 # number of overall MSHR misses | 480system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 481system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 482system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 483system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 484system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 485system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 486system.cpu.icache.ReadReq_mshr_misses::cpu.inst 259 # number of ReadReq MSHR misses 487system.cpu.icache.ReadReq_mshr_misses::total 259 # number of ReadReq MSHR misses 488system.cpu.icache.demand_mshr_misses::cpu.inst 259 # number of demand (read+write) MSHR misses 489system.cpu.icache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses 490system.cpu.icache.overall_mshr_misses::cpu.inst 259 # number of overall MSHR misses 491system.cpu.icache.overall_mshr_misses::total 259 # number of overall MSHR misses |
| 486system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25639000 # number of ReadReq MSHR miss cycles 487system.cpu.icache.ReadReq_mshr_miss_latency::total 25639000 # number of ReadReq MSHR miss cycles 488system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25639000 # number of demand (read+write) MSHR miss cycles 489system.cpu.icache.demand_mshr_miss_latency::total 25639000 # number of demand (read+write) MSHR miss cycles 490system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25639000 # number of overall MSHR miss cycles 491system.cpu.icache.overall_mshr_miss_latency::total 25639000 # number of overall MSHR miss cycles | 492system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27310000 # number of ReadReq MSHR miss cycles 493system.cpu.icache.ReadReq_mshr_miss_latency::total 27310000 # number of ReadReq MSHR miss cycles 494system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27310000 # number of demand (read+write) MSHR miss cycles 495system.cpu.icache.demand_mshr_miss_latency::total 27310000 # number of demand (read+write) MSHR miss cycles 496system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27310000 # number of overall MSHR miss cycles 497system.cpu.icache.overall_mshr_miss_latency::total 27310000 # number of overall MSHR miss cycles |
| 492system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for ReadReq accesses 493system.cpu.icache.ReadReq_mshr_miss_rate::total 0.046316 # mshr miss rate for ReadReq accesses 494system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for demand accesses 495system.cpu.icache.demand_mshr_miss_rate::total 0.046316 # mshr miss rate for demand accesses 496system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for overall accesses 497system.cpu.icache.overall_mshr_miss_rate::total 0.046316 # mshr miss rate for overall accesses | 498system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for ReadReq accesses 499system.cpu.icache.ReadReq_mshr_miss_rate::total 0.046316 # mshr miss rate for ReadReq accesses 500system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for demand accesses 501system.cpu.icache.demand_mshr_miss_rate::total 0.046316 # mshr miss rate for demand accesses 502system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for overall accesses 503system.cpu.icache.overall_mshr_miss_rate::total 0.046316 # mshr miss rate for overall accesses |
| 498system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98992.277992 # average ReadReq mshr miss latency 499system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98992.277992 # average ReadReq mshr miss latency 500system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98992.277992 # average overall mshr miss latency 501system.cpu.icache.demand_avg_mshr_miss_latency::total 98992.277992 # average overall mshr miss latency 502system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98992.277992 # average overall mshr miss latency 503system.cpu.icache.overall_avg_mshr_miss_latency::total 98992.277992 # average overall mshr miss latency | 504system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 105444.015444 # average ReadReq mshr miss latency 505system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 105444.015444 # average ReadReq mshr miss latency 506system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 105444.015444 # average overall mshr miss latency 507system.cpu.icache.demand_avg_mshr_miss_latency::total 105444.015444 # average overall mshr miss latency 508system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 105444.015444 # average overall mshr miss latency 509system.cpu.icache.overall_avg_mshr_miss_latency::total 105444.015444 # average overall mshr miss latency |
| 504system.l2bus.snoop_filter.tot_requests 468 # Total number of requests made to the snoop filter. 505system.l2bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. 506system.l2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 507system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 508system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 509system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 510system.l2bus.snoop_filter.tot_requests 468 # Total number of requests made to the snoop filter. 511system.l2bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. 512system.l2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 513system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 514system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 515system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 510system.l2bus.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states | 516system.l2bus.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states |
| 511system.l2bus.trans_dist::ReadResp 315 # Transaction distribution 512system.l2bus.trans_dist::CleanEvict 71 # Transaction distribution 513system.l2bus.trans_dist::ReadExReq 82 # Transaction distribution 514system.l2bus.trans_dist::ReadExResp 82 # Transaction distribution 515system.l2bus.trans_dist::ReadSharedReq 315 # Transaction distribution 516system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 589 # Packet count per connected master and slave (bytes) 517system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) 518system.l2bus.pkt_count::total 865 # Packet count per connected master and slave (bytes) --- 9 unchanged lines hidden (view full) --- 528system.l2bus.snoop_fanout::0 394 99.24% 99.24% # Request fanout histogram 529system.l2bus.snoop_fanout::1 3 0.76% 100.00% # Request fanout histogram 530system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 531system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 532system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram 533system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 534system.l2bus.snoop_fanout::total 397 # Request fanout histogram 535system.l2bus.reqLayer0.occupancy 468000 # Layer occupancy (ticks) | 517system.l2bus.trans_dist::ReadResp 315 # Transaction distribution 518system.l2bus.trans_dist::CleanEvict 71 # Transaction distribution 519system.l2bus.trans_dist::ReadExReq 82 # Transaction distribution 520system.l2bus.trans_dist::ReadExResp 82 # Transaction distribution 521system.l2bus.trans_dist::ReadSharedReq 315 # Transaction distribution 522system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 589 # Packet count per connected master and slave (bytes) 523system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) 524system.l2bus.pkt_count::total 865 # Packet count per connected master and slave (bytes) --- 9 unchanged lines hidden (view full) --- 534system.l2bus.snoop_fanout::0 394 99.24% 99.24% # Request fanout histogram 535system.l2bus.snoop_fanout::1 3 0.76% 100.00% # Request fanout histogram 536system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 537system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 538system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram 539system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 540system.l2bus.snoop_fanout::total 397 # Request fanout histogram 541system.l2bus.reqLayer0.occupancy 468000 # Layer occupancy (ticks) |
| 536system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) | 542system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) |
| 537system.l2bus.respLayer0.occupancy 777000 # Layer occupancy (ticks) 538system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) 539system.l2bus.respLayer1.occupancy 414000 # Layer occupancy (ticks) | 543system.l2bus.respLayer0.occupancy 777000 # Layer occupancy (ticks) 544system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) 545system.l2bus.respLayer1.occupancy 414000 # Layer occupancy (ticks) |
| 540system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) 541system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states | 546system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) 547system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states |
| 542system.l2cache.tags.replacements 0 # number of replacements | 548system.l2cache.tags.replacements 0 # number of replacements |
| 543system.l2cache.tags.tagsinuse 200.697345 # Cycle average of tags in use | 549system.l2cache.tags.tagsinuse 201.052259 # Cycle average of tags in use |
| 544system.l2cache.tags.total_refs 73 # Total number of references to valid blocks. 545system.l2cache.tags.sampled_refs 394 # Sample count of references to valid blocks. 546system.l2cache.tags.avg_refs 0.185279 # Average number of references to valid blocks. 547system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 550system.l2cache.tags.total_refs 73 # Total number of references to valid blocks. 551system.l2cache.tags.sampled_refs 394 # Sample count of references to valid blocks. 552system.l2cache.tags.avg_refs 0.185279 # Average number of references to valid blocks. 553system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 548system.l2cache.tags.occ_blocks::cpu.inst 117.835895 # Average occupied blocks per requestor 549system.l2cache.tags.occ_blocks::cpu.data 82.861451 # Average occupied blocks per requestor 550system.l2cache.tags.occ_percent::cpu.inst 0.028769 # Average percentage of cache occupancy 551system.l2cache.tags.occ_percent::cpu.data 0.020230 # Average percentage of cache occupancy 552system.l2cache.tags.occ_percent::total 0.048998 # Average percentage of cache occupancy | 554system.l2cache.tags.occ_blocks::cpu.inst 118.133782 # Average occupied blocks per requestor 555system.l2cache.tags.occ_blocks::cpu.data 82.918477 # Average occupied blocks per requestor 556system.l2cache.tags.occ_percent::cpu.inst 0.028841 # Average percentage of cache occupancy 557system.l2cache.tags.occ_percent::cpu.data 0.020244 # Average percentage of cache occupancy 558system.l2cache.tags.occ_percent::total 0.049085 # Average percentage of cache occupancy |
| 553system.l2cache.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id | 559system.l2cache.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id |
| 554system.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 555system.l2cache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id | 560system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 561system.l2cache.tags.age_task_id_blocks_1024::1 332 # Occupied blocks per task id |
| 556system.l2cache.tags.occ_task_id_percent::1024 0.096191 # Percentage of cache occupancy per task id 557system.l2cache.tags.tag_accesses 4130 # Number of tag accesses 558system.l2cache.tags.data_accesses 4130 # Number of data accesses | 562system.l2cache.tags.occ_task_id_percent::1024 0.096191 # Percentage of cache occupancy per task id 563system.l2cache.tags.tag_accesses 4130 # Number of tag accesses 564system.l2cache.tags.data_accesses 4130 # Number of data accesses |
| 559system.l2cache.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states | 565system.l2cache.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states |
| 560system.l2cache.ReadSharedReq_hits::cpu.inst 2 # number of ReadSharedReq hits 561system.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits 562system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits 563system.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 564system.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 565system.l2cache.demand_hits::total 3 # number of demand (read+write) hits 566system.l2cache.overall_hits::cpu.inst 2 # number of overall hits 567system.l2cache.overall_hits::cpu.data 1 # number of overall hits --- 4 unchanged lines hidden (view full) --- 572system.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses 573system.l2cache.ReadSharedReq_misses::total 312 # number of ReadSharedReq misses 574system.l2cache.demand_misses::cpu.inst 257 # number of demand (read+write) misses 575system.l2cache.demand_misses::cpu.data 137 # number of demand (read+write) misses 576system.l2cache.demand_misses::total 394 # number of demand (read+write) misses 577system.l2cache.overall_misses::cpu.inst 257 # number of overall misses 578system.l2cache.overall_misses::cpu.data 137 # number of overall misses 579system.l2cache.overall_misses::total 394 # number of overall misses | 566system.l2cache.ReadSharedReq_hits::cpu.inst 2 # number of ReadSharedReq hits 567system.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits 568system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits 569system.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 570system.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 571system.l2cache.demand_hits::total 3 # number of demand (read+write) hits 572system.l2cache.overall_hits::cpu.inst 2 # number of overall hits 573system.l2cache.overall_hits::cpu.data 1 # number of overall hits --- 4 unchanged lines hidden (view full) --- 578system.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses 579system.l2cache.ReadSharedReq_misses::total 312 # number of ReadSharedReq misses 580system.l2cache.demand_misses::cpu.inst 257 # number of demand (read+write) misses 581system.l2cache.demand_misses::cpu.data 137 # number of demand (read+write) misses 582system.l2cache.demand_misses::total 394 # number of demand (read+write) misses 583system.l2cache.overall_misses::cpu.inst 257 # number of overall misses 584system.l2cache.overall_misses::cpu.data 137 # number of overall misses 585system.l2cache.overall_misses::total 394 # number of overall misses |
| 580system.l2cache.ReadExReq_miss_latency::cpu.data 8112000 # number of ReadExReq miss cycles 581system.l2cache.ReadExReq_miss_latency::total 8112000 # number of ReadExReq miss cycles 582system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24816000 # number of ReadSharedReq miss cycles 583system.l2cache.ReadSharedReq_miss_latency::cpu.data 5453000 # number of ReadSharedReq miss cycles 584system.l2cache.ReadSharedReq_miss_latency::total 30269000 # number of ReadSharedReq miss cycles 585system.l2cache.demand_miss_latency::cpu.inst 24816000 # number of demand (read+write) miss cycles 586system.l2cache.demand_miss_latency::cpu.data 13565000 # number of demand (read+write) miss cycles 587system.l2cache.demand_miss_latency::total 38381000 # number of demand (read+write) miss cycles 588system.l2cache.overall_miss_latency::cpu.inst 24816000 # number of overall miss cycles 589system.l2cache.overall_miss_latency::cpu.data 13565000 # number of overall miss cycles 590system.l2cache.overall_miss_latency::total 38381000 # number of overall miss cycles | 586system.l2cache.ReadExReq_miss_latency::cpu.data 8527000 # number of ReadExReq miss cycles 587system.l2cache.ReadExReq_miss_latency::total 8527000 # number of ReadExReq miss cycles 588system.l2cache.ReadSharedReq_miss_latency::cpu.inst 26487000 # number of ReadSharedReq miss cycles 589system.l2cache.ReadSharedReq_miss_latency::cpu.data 6273000 # number of ReadSharedReq miss cycles 590system.l2cache.ReadSharedReq_miss_latency::total 32760000 # number of ReadSharedReq miss cycles 591system.l2cache.demand_miss_latency::cpu.inst 26487000 # number of demand (read+write) miss cycles 592system.l2cache.demand_miss_latency::cpu.data 14800000 # number of demand (read+write) miss cycles 593system.l2cache.demand_miss_latency::total 41287000 # number of demand (read+write) miss cycles 594system.l2cache.overall_miss_latency::cpu.inst 26487000 # number of overall miss cycles 595system.l2cache.overall_miss_latency::cpu.data 14800000 # number of overall miss cycles 596system.l2cache.overall_miss_latency::total 41287000 # number of overall miss cycles |
| 591system.l2cache.ReadExReq_accesses::cpu.data 82 # number of ReadExReq accesses(hits+misses) 592system.l2cache.ReadExReq_accesses::total 82 # number of ReadExReq accesses(hits+misses) 593system.l2cache.ReadSharedReq_accesses::cpu.inst 259 # number of ReadSharedReq accesses(hits+misses) 594system.l2cache.ReadSharedReq_accesses::cpu.data 56 # number of ReadSharedReq accesses(hits+misses) 595system.l2cache.ReadSharedReq_accesses::total 315 # number of ReadSharedReq accesses(hits+misses) 596system.l2cache.demand_accesses::cpu.inst 259 # number of demand (read+write) accesses 597system.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses 598system.l2cache.demand_accesses::total 397 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 605system.l2cache.ReadSharedReq_miss_rate::cpu.data 0.982143 # miss rate for ReadSharedReq accesses 606system.l2cache.ReadSharedReq_miss_rate::total 0.990476 # miss rate for ReadSharedReq accesses 607system.l2cache.demand_miss_rate::cpu.inst 0.992278 # miss rate for demand accesses 608system.l2cache.demand_miss_rate::cpu.data 0.992754 # miss rate for demand accesses 609system.l2cache.demand_miss_rate::total 0.992443 # miss rate for demand accesses 610system.l2cache.overall_miss_rate::cpu.inst 0.992278 # miss rate for overall accesses 611system.l2cache.overall_miss_rate::cpu.data 0.992754 # miss rate for overall accesses 612system.l2cache.overall_miss_rate::total 0.992443 # miss rate for overall accesses | 597system.l2cache.ReadExReq_accesses::cpu.data 82 # number of ReadExReq accesses(hits+misses) 598system.l2cache.ReadExReq_accesses::total 82 # number of ReadExReq accesses(hits+misses) 599system.l2cache.ReadSharedReq_accesses::cpu.inst 259 # number of ReadSharedReq accesses(hits+misses) 600system.l2cache.ReadSharedReq_accesses::cpu.data 56 # number of ReadSharedReq accesses(hits+misses) 601system.l2cache.ReadSharedReq_accesses::total 315 # number of ReadSharedReq accesses(hits+misses) 602system.l2cache.demand_accesses::cpu.inst 259 # number of demand (read+write) accesses 603system.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses 604system.l2cache.demand_accesses::total 397 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 611system.l2cache.ReadSharedReq_miss_rate::cpu.data 0.982143 # miss rate for ReadSharedReq accesses 612system.l2cache.ReadSharedReq_miss_rate::total 0.990476 # miss rate for ReadSharedReq accesses 613system.l2cache.demand_miss_rate::cpu.inst 0.992278 # miss rate for demand accesses 614system.l2cache.demand_miss_rate::cpu.data 0.992754 # miss rate for demand accesses 615system.l2cache.demand_miss_rate::total 0.992443 # miss rate for demand accesses 616system.l2cache.overall_miss_rate::cpu.inst 0.992278 # miss rate for overall accesses 617system.l2cache.overall_miss_rate::cpu.data 0.992754 # miss rate for overall accesses 618system.l2cache.overall_miss_rate::total 0.992443 # miss rate for overall accesses |
| 613system.l2cache.ReadExReq_avg_miss_latency::cpu.data 98926.829268 # average ReadExReq miss latency 614system.l2cache.ReadExReq_avg_miss_latency::total 98926.829268 # average ReadExReq miss latency 615system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96560.311284 # average ReadSharedReq miss latency 616system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99145.454545 # average ReadSharedReq miss latency 617system.l2cache.ReadSharedReq_avg_miss_latency::total 97016.025641 # average ReadSharedReq miss latency 618system.l2cache.demand_avg_miss_latency::cpu.inst 96560.311284 # average overall miss latency 619system.l2cache.demand_avg_miss_latency::cpu.data 99014.598540 # average overall miss latency 620system.l2cache.demand_avg_miss_latency::total 97413.705584 # average overall miss latency 621system.l2cache.overall_avg_miss_latency::cpu.inst 96560.311284 # average overall miss latency 622system.l2cache.overall_avg_miss_latency::cpu.data 99014.598540 # average overall miss latency 623system.l2cache.overall_avg_miss_latency::total 97413.705584 # average overall miss latency | 619system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103987.804878 # average ReadExReq miss latency 620system.l2cache.ReadExReq_avg_miss_latency::total 103987.804878 # average ReadExReq miss latency 621system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 103062.256809 # average ReadSharedReq miss latency 622system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 114054.545455 # average ReadSharedReq miss latency 623system.l2cache.ReadSharedReq_avg_miss_latency::total 105000 # average ReadSharedReq miss latency 624system.l2cache.demand_avg_miss_latency::cpu.inst 103062.256809 # average overall miss latency 625system.l2cache.demand_avg_miss_latency::cpu.data 108029.197080 # average overall miss latency 626system.l2cache.demand_avg_miss_latency::total 104789.340102 # average overall miss latency 627system.l2cache.overall_avg_miss_latency::cpu.inst 103062.256809 # average overall miss latency 628system.l2cache.overall_avg_miss_latency::cpu.data 108029.197080 # average overall miss latency 629system.l2cache.overall_avg_miss_latency::total 104789.340102 # average overall miss latency |
| 624system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 625system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 626system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 627system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 628system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 629system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 630system.l2cache.ReadExReq_mshr_misses::cpu.data 82 # number of ReadExReq MSHR misses 631system.l2cache.ReadExReq_mshr_misses::total 82 # number of ReadExReq MSHR misses 632system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 257 # number of ReadSharedReq MSHR misses 633system.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses 634system.l2cache.ReadSharedReq_mshr_misses::total 312 # number of ReadSharedReq MSHR misses 635system.l2cache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses 636system.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses 637system.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses 638system.l2cache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses 639system.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses 640system.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses | 630system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 631system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 632system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 633system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 634system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 635system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 636system.l2cache.ReadExReq_mshr_misses::cpu.data 82 # number of ReadExReq MSHR misses 637system.l2cache.ReadExReq_mshr_misses::total 82 # number of ReadExReq MSHR misses 638system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 257 # number of ReadSharedReq MSHR misses 639system.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses 640system.l2cache.ReadSharedReq_mshr_misses::total 312 # number of ReadSharedReq MSHR misses 641system.l2cache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses 642system.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses 643system.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses 644system.l2cache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses 645system.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses 646system.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses |
| 641system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6472000 # number of ReadExReq MSHR miss cycles 642system.l2cache.ReadExReq_mshr_miss_latency::total 6472000 # number of ReadExReq MSHR miss cycles 643system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19676000 # number of ReadSharedReq MSHR miss cycles 644system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4353000 # number of ReadSharedReq MSHR miss cycles 645system.l2cache.ReadSharedReq_mshr_miss_latency::total 24029000 # number of ReadSharedReq MSHR miss cycles 646system.l2cache.demand_mshr_miss_latency::cpu.inst 19676000 # number of demand (read+write) MSHR miss cycles 647system.l2cache.demand_mshr_miss_latency::cpu.data 10825000 # number of demand (read+write) MSHR miss cycles 648system.l2cache.demand_mshr_miss_latency::total 30501000 # number of demand (read+write) MSHR miss cycles 649system.l2cache.overall_mshr_miss_latency::cpu.inst 19676000 # number of overall MSHR miss cycles 650system.l2cache.overall_mshr_miss_latency::cpu.data 10825000 # number of overall MSHR miss cycles 651system.l2cache.overall_mshr_miss_latency::total 30501000 # number of overall MSHR miss cycles | 647system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6887000 # number of ReadExReq MSHR miss cycles 648system.l2cache.ReadExReq_mshr_miss_latency::total 6887000 # number of ReadExReq MSHR miss cycles 649system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 21347000 # number of ReadSharedReq MSHR miss cycles 650system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5173000 # number of ReadSharedReq MSHR miss cycles 651system.l2cache.ReadSharedReq_mshr_miss_latency::total 26520000 # number of ReadSharedReq MSHR miss cycles 652system.l2cache.demand_mshr_miss_latency::cpu.inst 21347000 # number of demand (read+write) MSHR miss cycles 653system.l2cache.demand_mshr_miss_latency::cpu.data 12060000 # number of demand (read+write) MSHR miss cycles 654system.l2cache.demand_mshr_miss_latency::total 33407000 # number of demand (read+write) MSHR miss cycles 655system.l2cache.overall_mshr_miss_latency::cpu.inst 21347000 # number of overall MSHR miss cycles 656system.l2cache.overall_mshr_miss_latency::cpu.data 12060000 # number of overall MSHR miss cycles 657system.l2cache.overall_mshr_miss_latency::total 33407000 # number of overall MSHR miss cycles |
| 652system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 653system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 654system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for ReadSharedReq accesses 655system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.982143 # mshr miss rate for ReadSharedReq accesses 656system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.990476 # mshr miss rate for ReadSharedReq accesses 657system.l2cache.demand_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for demand accesses 658system.l2cache.demand_mshr_miss_rate::cpu.data 0.992754 # mshr miss rate for demand accesses 659system.l2cache.demand_mshr_miss_rate::total 0.992443 # mshr miss rate for demand accesses 660system.l2cache.overall_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for overall accesses 661system.l2cache.overall_mshr_miss_rate::cpu.data 0.992754 # mshr miss rate for overall accesses 662system.l2cache.overall_mshr_miss_rate::total 0.992443 # mshr miss rate for overall accesses | 658system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 659system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 660system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for ReadSharedReq accesses 661system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.982143 # mshr miss rate for ReadSharedReq accesses 662system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.990476 # mshr miss rate for ReadSharedReq accesses 663system.l2cache.demand_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for demand accesses 664system.l2cache.demand_mshr_miss_rate::cpu.data 0.992754 # mshr miss rate for demand accesses 665system.l2cache.demand_mshr_miss_rate::total 0.992443 # mshr miss rate for demand accesses 666system.l2cache.overall_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for overall accesses 667system.l2cache.overall_mshr_miss_rate::cpu.data 0.992754 # mshr miss rate for overall accesses 668system.l2cache.overall_mshr_miss_rate::total 0.992443 # mshr miss rate for overall accesses |
| 663system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.829268 # average ReadExReq mshr miss latency 664system.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.829268 # average ReadExReq mshr miss latency 665system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76560.311284 # average ReadSharedReq mshr miss latency 666system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79145.454545 # average ReadSharedReq mshr miss latency 667system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77016.025641 # average ReadSharedReq mshr miss latency 668system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76560.311284 # average overall mshr miss latency 669system.l2cache.demand_avg_mshr_miss_latency::cpu.data 79014.598540 # average overall mshr miss latency 670system.l2cache.demand_avg_mshr_miss_latency::total 77413.705584 # average overall mshr miss latency 671system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76560.311284 # average overall mshr miss latency 672system.l2cache.overall_avg_mshr_miss_latency::cpu.data 79014.598540 # average overall mshr miss latency 673system.l2cache.overall_avg_mshr_miss_latency::total 77413.705584 # average overall mshr miss latency | 669system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83987.804878 # average ReadExReq mshr miss latency 670system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83987.804878 # average ReadExReq mshr miss latency 671system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 83062.256809 # average ReadSharedReq mshr miss latency 672system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 94054.545455 # average ReadSharedReq mshr miss latency 673system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 85000 # average ReadSharedReq mshr miss latency 674system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83062.256809 # average overall mshr miss latency 675system.l2cache.demand_avg_mshr_miss_latency::cpu.data 88029.197080 # average overall mshr miss latency 676system.l2cache.demand_avg_mshr_miss_latency::total 84789.340102 # average overall mshr miss latency 677system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83062.256809 # average overall mshr miss latency 678system.l2cache.overall_avg_mshr_miss_latency::cpu.data 88029.197080 # average overall mshr miss latency 679system.l2cache.overall_avg_mshr_miss_latency::total 84789.340102 # average overall mshr miss latency |
| 674system.membus.snoop_filter.tot_requests 394 # Total number of requests made to the snoop filter. 675system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 676system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 677system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 678system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 679system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 680system.membus.snoop_filter.tot_requests 394 # Total number of requests made to the snoop filter. 681system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 682system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 683system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 684system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 685system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 680system.membus.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states | 686system.membus.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states |
| 681system.membus.trans_dist::ReadResp 312 # Transaction distribution 682system.membus.trans_dist::ReadExReq 82 # Transaction distribution 683system.membus.trans_dist::ReadExResp 82 # Transaction distribution 684system.membus.trans_dist::ReadSharedReq 312 # Transaction distribution 685system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 788 # Packet count per connected master and slave (bytes) 686system.membus.pkt_count::total 788 # Packet count per connected master and slave (bytes) 687system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 25216 # Cumulative packet size per connected master and slave (bytes) 688system.membus.pkt_size::total 25216 # Cumulative packet size per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 695system.membus.snoop_fanout::0 394 100.00% 100.00% # Request fanout histogram 696system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 697system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 698system.membus.snoop_fanout::min_value 0 # Request fanout histogram 699system.membus.snoop_fanout::max_value 0 # Request fanout histogram 700system.membus.snoop_fanout::total 394 # Request fanout histogram 701system.membus.reqLayer0.occupancy 394000 # Layer occupancy (ticks) 702system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) | 687system.membus.trans_dist::ReadResp 312 # Transaction distribution 688system.membus.trans_dist::ReadExReq 82 # Transaction distribution 689system.membus.trans_dist::ReadExResp 82 # Transaction distribution 690system.membus.trans_dist::ReadSharedReq 312 # Transaction distribution 691system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 788 # Packet count per connected master and slave (bytes) 692system.membus.pkt_count::total 788 # Packet count per connected master and slave (bytes) 693system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 25216 # Cumulative packet size per connected master and slave (bytes) 694system.membus.pkt_size::total 25216 # Cumulative packet size per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 701system.membus.snoop_fanout::0 394 100.00% 100.00% # Request fanout histogram 702system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 703system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 704system.membus.snoop_fanout::min_value 0 # Request fanout histogram 705system.membus.snoop_fanout::max_value 0 # Request fanout histogram 706system.membus.snoop_fanout::total 394 # Request fanout histogram 707system.membus.reqLayer0.occupancy 394000 # Layer occupancy (ticks) 708system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) |
| 703system.membus.respLayer0.occupancy 2102000 # Layer occupancy (ticks) 704system.membus.respLayer0.utilization 3.9 # Layer utilization (%) | 709system.membus.respLayer0.occupancy 2102500 # Layer occupancy (ticks) 710system.membus.respLayer0.utilization 3.7 # Layer utilization (%) |
| 705 706---------- End Simulation Statistics ---------- | 711 712---------- End Simulation Statistics ---------- |