| stats.txt (11570:4aac82f10951) | stats.txt (11606:6b749761c398) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000053 # Number of seconds simulated 4sim_ticks 53334000 # Number of ticks simulated 5final_tick 53334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000054 # Number of seconds simulated 4sim_ticks 53605000 # Number of ticks simulated 5final_tick 53605000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 532040 # Simulator instruction rate (inst/s) 8host_op_rate 531414 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5103257870 # Simulator tick rate (ticks/s) 10host_mem_usage 634140 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host | 7host_inst_rate 205629 # Simulator instruction rate (inst/s) 8host_op_rate 205519 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1984690430 # Simulator tick rate (ticks/s) 10host_mem_usage 637752 # Number of bytes of host memory used 11host_seconds 0.03 # Real time elapsed on the host |
| 12sim_insts 5548 # Number of instructions simulated 13sim_ops 5548 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 5548 # Number of instructions simulated 13sim_ops 5548 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states | 16system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states |
| 17system.mem_ctrl.bytes_read::cpu.inst 16448 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory 19system.mem_ctrl.bytes_read::total 25216 # Number of bytes read from this memory 20system.mem_ctrl.bytes_inst_read::cpu.inst 16448 # Number of instructions bytes read from this memory 21system.mem_ctrl.bytes_inst_read::total 16448 # Number of instructions bytes read from this memory 22system.mem_ctrl.num_reads::cpu.inst 257 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory 24system.mem_ctrl.num_reads::total 394 # Number of read requests responded to by this memory | 17system.mem_ctrl.bytes_read::cpu.inst 16448 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory 19system.mem_ctrl.bytes_read::total 25216 # Number of bytes read from this memory 20system.mem_ctrl.bytes_inst_read::cpu.inst 16448 # Number of instructions bytes read from this memory 21system.mem_ctrl.bytes_inst_read::total 16448 # Number of instructions bytes read from this memory 22system.mem_ctrl.num_reads::cpu.inst 257 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory 24system.mem_ctrl.num_reads::total 394 # Number of read requests responded to by this memory |
| 25system.mem_ctrl.bw_read::cpu.inst 308396145 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrl.bw_read::cpu.data 164397945 # Total read bandwidth from this memory (bytes/s) 27system.mem_ctrl.bw_read::total 472794090 # Total read bandwidth from this memory (bytes/s) 28system.mem_ctrl.bw_inst_read::cpu.inst 308396145 # Instruction read bandwidth from this memory (bytes/s) 29system.mem_ctrl.bw_inst_read::total 308396145 # Instruction read bandwidth from this memory (bytes/s) 30system.mem_ctrl.bw_total::cpu.inst 308396145 # Total bandwidth to/from this memory (bytes/s) 31system.mem_ctrl.bw_total::cpu.data 164397945 # Total bandwidth to/from this memory (bytes/s) 32system.mem_ctrl.bw_total::total 472794090 # Total bandwidth to/from this memory (bytes/s) | 25system.mem_ctrl.bw_read::cpu.inst 306837049 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrl.bw_read::cpu.data 163566831 # Total read bandwidth from this memory (bytes/s) 27system.mem_ctrl.bw_read::total 470403880 # Total read bandwidth from this memory (bytes/s) 28system.mem_ctrl.bw_inst_read::cpu.inst 306837049 # Instruction read bandwidth from this memory (bytes/s) 29system.mem_ctrl.bw_inst_read::total 306837049 # Instruction read bandwidth from this memory (bytes/s) 30system.mem_ctrl.bw_total::cpu.inst 306837049 # Total bandwidth to/from this memory (bytes/s) 31system.mem_ctrl.bw_total::cpu.data 163566831 # Total bandwidth to/from this memory (bytes/s) 32system.mem_ctrl.bw_total::total 470403880 # Total bandwidth to/from this memory (bytes/s) |
| 33system.mem_ctrl.readReqs 394 # Number of read requests accepted 34system.mem_ctrl.writeReqs 0 # Number of write requests accepted 35system.mem_ctrl.readBursts 394 # Number of DRAM read bursts, including those serviced by the write queue 36system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.mem_ctrl.bytesReadDRAM 25216 # Total number of bytes read from DRAM 38system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM 40system.mem_ctrl.bytesReadSys 25216 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts 72system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts 73system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts 74system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts 75system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts 76system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts 77system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry 78system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry | 33system.mem_ctrl.readReqs 394 # Number of read requests accepted 34system.mem_ctrl.writeReqs 0 # Number of write requests accepted 35system.mem_ctrl.readBursts 394 # Number of DRAM read bursts, including those serviced by the write queue 36system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.mem_ctrl.bytesReadDRAM 25216 # Total number of bytes read from DRAM 38system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM 40system.mem_ctrl.bytesReadSys 25216 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts 72system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts 73system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts 74system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts 75system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts 76system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts 77system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry 78system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry |
| 79system.mem_ctrl.totGap 53238000 # Total gap between requests | 79system.mem_ctrl.totGap 53508000 # Total gap between requests |
| 80system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) 81system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) 82system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) 83system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) 84system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) 85system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) 86system.mem_ctrl.readPktSize::6 394 # Read request sizes (log2) 87system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) --- 94 unchanged lines hidden (view full) --- 182system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see | 80system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) 81system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) 82system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) 83system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) 84system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) 85system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) 86system.mem_ctrl.readPktSize::6 394 # Read request sizes (log2) 87system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) --- 94 unchanged lines hidden (view full) --- 182system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 190system.mem_ctrl.bytesPerActivate::samples 93 # Bytes accessed per row activation 191system.mem_ctrl.bytesPerActivate::mean 243.612903 # Bytes accessed per row activation 192system.mem_ctrl.bytesPerActivate::gmean 174.394567 # Bytes accessed per row activation 193system.mem_ctrl.bytesPerActivate::stdev 202.881901 # Bytes accessed per row activation 194system.mem_ctrl.bytesPerActivate::64-127 29 31.18% 31.18% # Bytes accessed per row activation 195system.mem_ctrl.bytesPerActivate::128-191 15 16.13% 47.31% # Bytes accessed per row activation 196system.mem_ctrl.bytesPerActivate::192-255 11 11.83% 59.14% # Bytes accessed per row activation 197system.mem_ctrl.bytesPerActivate::256-319 8 8.60% 67.74% # Bytes accessed per row activation 198system.mem_ctrl.bytesPerActivate::320-383 6 6.45% 74.19% # Bytes accessed per row activation 199system.mem_ctrl.bytesPerActivate::384-447 8 8.60% 82.80% # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::448-511 2 2.15% 84.95% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::512-575 3 3.23% 88.17% # Bytes accessed per row activation 202system.mem_ctrl.bytesPerActivate::576-639 6 6.45% 94.62% # Bytes accessed per row activation 203system.mem_ctrl.bytesPerActivate::640-703 2 2.15% 96.77% # Bytes accessed per row activation 204system.mem_ctrl.bytesPerActivate::704-767 1 1.08% 97.85% # Bytes accessed per row activation 205system.mem_ctrl.bytesPerActivate::896-959 1 1.08% 98.92% # Bytes accessed per row activation 206system.mem_ctrl.bytesPerActivate::960-1023 1 1.08% 100.00% # Bytes accessed per row activation 207system.mem_ctrl.bytesPerActivate::total 93 # Bytes accessed per row activation 208system.mem_ctrl.totQLat 3010250 # Total ticks spent queuing 209system.mem_ctrl.totMemAccLat 10397750 # Total ticks spent from burst creation until serviced by the DRAM | 190system.mem_ctrl.bytesPerActivate::samples 92 # Bytes accessed per row activation 191system.mem_ctrl.bytesPerActivate::mean 246.260870 # Bytes accessed per row activation 192system.mem_ctrl.bytesPerActivate::gmean 176.635417 # Bytes accessed per row activation 193system.mem_ctrl.bytesPerActivate::stdev 203.037423 # Bytes accessed per row activation 194system.mem_ctrl.bytesPerActivate::64-127 28 30.43% 30.43% # Bytes accessed per row activation 195system.mem_ctrl.bytesPerActivate::128-191 15 16.30% 46.74% # Bytes accessed per row activation 196system.mem_ctrl.bytesPerActivate::192-255 11 11.96% 58.70% # Bytes accessed per row activation 197system.mem_ctrl.bytesPerActivate::256-319 8 8.70% 67.39% # Bytes accessed per row activation 198system.mem_ctrl.bytesPerActivate::320-383 6 6.52% 73.91% # Bytes accessed per row activation 199system.mem_ctrl.bytesPerActivate::384-447 7 7.61% 81.52% # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::448-511 3 3.26% 84.78% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::512-575 3 3.26% 88.04% # Bytes accessed per row activation 202system.mem_ctrl.bytesPerActivate::576-639 6 6.52% 94.57% # Bytes accessed per row activation 203system.mem_ctrl.bytesPerActivate::640-703 2 2.17% 96.74% # Bytes accessed per row activation 204system.mem_ctrl.bytesPerActivate::768-831 1 1.09% 97.83% # Bytes accessed per row activation 205system.mem_ctrl.bytesPerActivate::896-959 2 2.17% 100.00% # Bytes accessed per row activation 206system.mem_ctrl.bytesPerActivate::total 92 # Bytes accessed per row activation 207system.mem_ctrl.totQLat 2887500 # Total ticks spent queuing 208system.mem_ctrl.totMemAccLat 10275000 # Total ticks spent from burst creation until serviced by the DRAM |
| 210system.mem_ctrl.totBusLat 1970000 # Total ticks spent in databus transfers | 209system.mem_ctrl.totBusLat 1970000 # Total ticks spent in databus transfers |
| 211system.mem_ctrl.avgQLat 7640.23 # Average queueing delay per DRAM burst | 210system.mem_ctrl.avgQLat 7328.68 # Average queueing delay per DRAM burst |
| 212system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst | 211system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 213system.mem_ctrl.avgMemAccLat 26390.23 # Average memory access latency per DRAM burst 214system.mem_ctrl.avgRdBW 472.79 # Average DRAM read bandwidth in MiByte/s | 212system.mem_ctrl.avgMemAccLat 26078.68 # Average memory access latency per DRAM burst 213system.mem_ctrl.avgRdBW 470.40 # Average DRAM read bandwidth in MiByte/s |
| 215system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 214system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 216system.mem_ctrl.avgRdBWSys 472.79 # Average system read bandwidth in MiByte/s | 215system.mem_ctrl.avgRdBWSys 470.40 # Average system read bandwidth in MiByte/s |
| 217system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 218system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 216system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 217system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 219system.mem_ctrl.busUtil 3.69 # Data bus utilization in percentage 220system.mem_ctrl.busUtilRead 3.69 # Data bus utilization in percentage for reads | 218system.mem_ctrl.busUtil 3.68 # Data bus utilization in percentage 219system.mem_ctrl.busUtilRead 3.68 # Data bus utilization in percentage for reads |
| 221system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes 222system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing 223system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing | 220system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes 221system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing 222system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 224system.mem_ctrl.readRowHits 295 # Number of row buffer hits during reads | 223system.mem_ctrl.readRowHits 296 # Number of row buffer hits during reads |
| 225system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes | 224system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes |
| 226system.mem_ctrl.readRowHitRate 74.87 # Row buffer hit rate for reads | 225system.mem_ctrl.readRowHitRate 75.13 # Row buffer hit rate for reads |
| 227system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes | 226system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes |
| 228system.mem_ctrl.avgGap 135121.83 # Average gap between requests 229system.mem_ctrl.pageHitRate 74.87 # Row buffer hit rate, read and write combined 230system.mem_ctrl_0.actEnergy 385560 # Energy for activate commands per rank (pJ) 231system.mem_ctrl_0.preEnergy 210375 # Energy for precharge commands per rank (pJ) 232system.mem_ctrl_0.readEnergy 1622400 # Energy for read commands per rank (pJ) | 227system.mem_ctrl.avgGap 135807.11 # Average gap between requests 228system.mem_ctrl.pageHitRate 75.13 # Row buffer hit rate, read and write combined 229system.mem_ctrl_0.actEnergy 378000 # Energy for activate commands per rank (pJ) 230system.mem_ctrl_0.preEnergy 206250 # Energy for precharge commands per rank (pJ) 231system.mem_ctrl_0.readEnergy 1614600 # Energy for read commands per rank (pJ) |
| 233system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) 234system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) | 232system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) 233system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) |
| 235system.mem_ctrl_0.actBackEnergy 30540600 # Energy for active background per rank (pJ) 236system.mem_ctrl_0.preBackEnergy 1396500 # Energy for precharge background per rank (pJ) 237system.mem_ctrl_0.totalEnergy 37206795 # Total energy per rank (pJ) 238system.mem_ctrl_0.averagePower 792.013091 # Core power per rank (mW) 239system.mem_ctrl_0.memoryStateTime::IDLE 2174750 # Time in different power states | 234system.mem_ctrl_0.actBackEnergy 30461940 # Energy for active background per rank (pJ) 235system.mem_ctrl_0.preBackEnergy 1478250 # Energy for precharge background per rank (pJ) 236system.mem_ctrl_0.totalEnergy 37190400 # Total energy per rank (pJ) 237system.mem_ctrl_0.averagePower 791.306152 # Core power per rank (mW) 238system.mem_ctrl_0.memoryStateTime::IDLE 2310750 # Time in different power states |
| 240system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states 241system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 239system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states 240system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 242system.mem_ctrl_0.memoryStateTime::ACT 43256500 # Time in different power states | 241system.mem_ctrl_0.memoryStateTime::ACT 43141000 # Time in different power states |
| 243system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 242system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 244system.mem_ctrl_1.actEnergy 279720 # Energy for activate commands per rank (pJ) 245system.mem_ctrl_1.preEnergy 152625 # Energy for precharge commands per rank (pJ) | 243system.mem_ctrl_1.actEnergy 272160 # Energy for activate commands per rank (pJ) 244system.mem_ctrl_1.preEnergy 148500 # Energy for precharge commands per rank (pJ) |
| 246system.mem_ctrl_1.readEnergy 1053000 # Energy for read commands per rank (pJ) 247system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) 248system.mem_ctrl_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) | 245system.mem_ctrl_1.readEnergy 1053000 # Energy for read commands per rank (pJ) 246system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) 247system.mem_ctrl_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) |
| 249system.mem_ctrl_1.actBackEnergy 29447910 # Energy for active background per rank (pJ) 250system.mem_ctrl_1.preBackEnergy 2355000 # Energy for precharge background per rank (pJ) 251system.mem_ctrl_1.totalEnergy 36339615 # Total energy per rank (pJ) 252system.mem_ctrl_1.averagePower 773.553616 # Core power per rank (mW) 253system.mem_ctrl_1.memoryStateTime::IDLE 4798500 # Time in different power states | 248system.mem_ctrl_1.actBackEnergy 29252115 # Energy for active background per rank (pJ) 249system.mem_ctrl_1.preBackEnergy 2526750 # Energy for precharge background per rank (pJ) 250system.mem_ctrl_1.totalEnergy 36303885 # Total energy per rank (pJ) 251system.mem_ctrl_1.averagePower 772.793039 # Core power per rank (mW) 252system.mem_ctrl_1.memoryStateTime::IDLE 5312750 # Time in different power states |
| 254system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states 255system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 253system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states 254system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 256system.mem_ctrl_1.memoryStateTime::ACT 41660500 # Time in different power states | 255system.mem_ctrl_1.memoryStateTime::ACT 41373250 # Time in different power states |
| 257system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 256system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 258system.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states | 257system.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states |
| 259system.cpu.workload.num_syscalls 11 # Number of system calls | 258system.cpu.workload.num_syscalls 11 # Number of system calls |
| 260system.cpu.pwrStateResidencyTicks::ON 53334000 # Cumulative time (in ticks) in various power states 261system.cpu.numCycles 53334 # number of cpu cycles simulated | 259system.cpu.pwrStateResidencyTicks::ON 53605000 # Cumulative time (in ticks) in various power states 260system.cpu.numCycles 53605 # number of cpu cycles simulated |
| 262system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 263system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 264system.cpu.committedInsts 5548 # Number of instructions committed 265system.cpu.committedOps 5548 # Number of ops (including micro ops) committed 266system.cpu.num_int_alu_accesses 4660 # Number of integer alu accesses 267system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 268system.cpu.num_func_calls 146 # number of times a function call or return occured 269system.cpu.num_conditional_control_insts 835 # number of instructions that are conditional controls 270system.cpu.num_int_insts 4660 # number of integer instructions 271system.cpu.num_fp_insts 0 # number of float instructions 272system.cpu.num_int_register_reads 10977 # number of times the integer registers were read 273system.cpu.num_int_register_writes 5062 # number of times the integer registers were written 274system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 275system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 276system.cpu.num_mem_refs 1404 # number of memory refs 277system.cpu.num_load_insts 726 # Number of load instructions 278system.cpu.num_store_insts 678 # Number of store instructions 279system.cpu.num_idle_cycles 0.001000 # Number of idle cycles | 261system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 262system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 263system.cpu.committedInsts 5548 # Number of instructions committed 264system.cpu.committedOps 5548 # Number of ops (including micro ops) committed 265system.cpu.num_int_alu_accesses 4660 # Number of integer alu accesses 266system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 267system.cpu.num_func_calls 146 # number of times a function call or return occured 268system.cpu.num_conditional_control_insts 835 # number of instructions that are conditional controls 269system.cpu.num_int_insts 4660 # number of integer instructions 270system.cpu.num_fp_insts 0 # number of float instructions 271system.cpu.num_int_register_reads 10977 # number of times the integer registers were read 272system.cpu.num_int_register_writes 5062 # number of times the integer registers were written 273system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 274system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 275system.cpu.num_mem_refs 1404 # number of memory refs 276system.cpu.num_load_insts 726 # Number of load instructions 277system.cpu.num_store_insts 678 # Number of store instructions 278system.cpu.num_idle_cycles 0.001000 # Number of idle cycles |
| 280system.cpu.num_busy_cycles 53333.999000 # Number of busy cycles | 279system.cpu.num_busy_cycles 53604.999000 # Number of busy cycles |
| 281system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 282system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 283system.cpu.Branches 1187 # Number of branches fetched 284system.cpu.op_class::No_OpClass 173 3.09% 3.09% # Class of executed instruction 285system.cpu.op_class::IntAlu 4014 71.79% 74.89% # Class of executed instruction 286system.cpu.op_class::IntMult 0 0.00% 74.89% # Class of executed instruction 287system.cpu.op_class::IntDiv 0 0.00% 74.89% # Class of executed instruction 288system.cpu.op_class::FloatAdd 0 0.00% 74.89% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 311system.cpu.op_class::SimdFloatMult 0 0.00% 74.89% # Class of executed instruction 312system.cpu.op_class::SimdFloatMultAcc 0 0.00% 74.89% # Class of executed instruction 313system.cpu.op_class::SimdFloatSqrt 0 0.00% 74.89% # Class of executed instruction 314system.cpu.op_class::MemRead 726 12.99% 87.87% # Class of executed instruction 315system.cpu.op_class::MemWrite 678 12.13% 100.00% # Class of executed instruction 316system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 317system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 318system.cpu.op_class::total 5591 # Class of executed instruction | 280system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 281system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 282system.cpu.Branches 1187 # Number of branches fetched 283system.cpu.op_class::No_OpClass 173 3.09% 3.09% # Class of executed instruction 284system.cpu.op_class::IntAlu 4014 71.79% 74.89% # Class of executed instruction 285system.cpu.op_class::IntMult 0 0.00% 74.89% # Class of executed instruction 286system.cpu.op_class::IntDiv 0 0.00% 74.89% # Class of executed instruction 287system.cpu.op_class::FloatAdd 0 0.00% 74.89% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 310system.cpu.op_class::SimdFloatMult 0 0.00% 74.89% # Class of executed instruction 311system.cpu.op_class::SimdFloatMultAcc 0 0.00% 74.89% # Class of executed instruction 312system.cpu.op_class::SimdFloatSqrt 0 0.00% 74.89% # Class of executed instruction 313system.cpu.op_class::MemRead 726 12.99% 87.87% # Class of executed instruction 314system.cpu.op_class::MemWrite 678 12.13% 100.00% # Class of executed instruction 315system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 316system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 317system.cpu.op_class::total 5591 # Class of executed instruction |
| 319system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states | 318system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states |
| 320system.cpu.dcache.tags.replacements 0 # number of replacements | 319system.cpu.dcache.tags.replacements 0 # number of replacements |
| 321system.cpu.dcache.tags.tagsinuse 83.743129 # Cycle average of tags in use | 320system.cpu.dcache.tags.tagsinuse 83.787726 # Cycle average of tags in use |
| 322system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. 323system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. 324system.cpu.dcache.tags.avg_refs 9.079710 # Average number of references to valid blocks. 325system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 321system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. 322system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. 323system.cpu.dcache.tags.avg_refs 9.079710 # Average number of references to valid blocks. 324system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 326system.cpu.dcache.tags.occ_blocks::cpu.data 83.743129 # Average occupied blocks per requestor 327system.cpu.dcache.tags.occ_percent::cpu.data 0.081780 # Average percentage of cache occupancy 328system.cpu.dcache.tags.occ_percent::total 0.081780 # Average percentage of cache occupancy | 325system.cpu.dcache.tags.occ_blocks::cpu.data 83.787726 # Average occupied blocks per requestor 326system.cpu.dcache.tags.occ_percent::cpu.data 0.081824 # Average percentage of cache occupancy 327system.cpu.dcache.tags.occ_percent::total 0.081824 # Average percentage of cache occupancy |
| 329system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id 330system.cpu.dcache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id 331system.cpu.dcache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id 332system.cpu.dcache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id 333system.cpu.dcache.tags.tag_accesses 2920 # Number of tag accesses 334system.cpu.dcache.tags.data_accesses 2920 # Number of data accesses | 328system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id 329system.cpu.dcache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id 330system.cpu.dcache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id 331system.cpu.dcache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id 332system.cpu.dcache.tags.tag_accesses 2920 # Number of tag accesses 333system.cpu.dcache.tags.data_accesses 2920 # Number of data accesses |
| 335system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states | 334system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states |
| 336system.cpu.dcache.ReadReq_hits::cpu.data 662 # number of ReadReq hits 337system.cpu.dcache.ReadReq_hits::total 662 # number of ReadReq hits 338system.cpu.dcache.WriteReq_hits::cpu.data 591 # number of WriteReq hits 339system.cpu.dcache.WriteReq_hits::total 591 # number of WriteReq hits 340system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits 341system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits 342system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits 343system.cpu.dcache.overall_hits::total 1253 # number of overall hits 344system.cpu.dcache.ReadReq_misses::cpu.data 56 # number of ReadReq misses 345system.cpu.dcache.ReadReq_misses::total 56 # number of ReadReq misses 346system.cpu.dcache.WriteReq_misses::cpu.data 82 # number of WriteReq misses 347system.cpu.dcache.WriteReq_misses::total 82 # number of WriteReq misses 348system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses 349system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses 350system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses 351system.cpu.dcache.overall_misses::total 138 # number of overall misses | 335system.cpu.dcache.ReadReq_hits::cpu.data 662 # number of ReadReq hits 336system.cpu.dcache.ReadReq_hits::total 662 # number of ReadReq hits 337system.cpu.dcache.WriteReq_hits::cpu.data 591 # number of WriteReq hits 338system.cpu.dcache.WriteReq_hits::total 591 # number of WriteReq hits 339system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits 340system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits 341system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits 342system.cpu.dcache.overall_hits::total 1253 # number of overall hits 343system.cpu.dcache.ReadReq_misses::cpu.data 56 # number of ReadReq misses 344system.cpu.dcache.ReadReq_misses::total 56 # number of ReadReq misses 345system.cpu.dcache.WriteReq_misses::cpu.data 82 # number of WriteReq misses 346system.cpu.dcache.WriteReq_misses::total 82 # number of WriteReq misses 347system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses 348system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses 349system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses 350system.cpu.dcache.overall_misses::total 138 # number of overall misses |
| 352system.cpu.dcache.ReadReq_miss_latency::cpu.data 5534000 # number of ReadReq miss cycles 353system.cpu.dcache.ReadReq_miss_latency::total 5534000 # number of ReadReq miss cycles 354system.cpu.dcache.WriteReq_miss_latency::cpu.data 8431000 # number of WriteReq miss cycles 355system.cpu.dcache.WriteReq_miss_latency::total 8431000 # number of WriteReq miss cycles 356system.cpu.dcache.demand_miss_latency::cpu.data 13965000 # number of demand (read+write) miss cycles 357system.cpu.dcache.demand_miss_latency::total 13965000 # number of demand (read+write) miss cycles 358system.cpu.dcache.overall_miss_latency::cpu.data 13965000 # number of overall miss cycles 359system.cpu.dcache.overall_miss_latency::total 13965000 # number of overall miss cycles | 351system.cpu.dcache.ReadReq_miss_latency::cpu.data 5756000 # number of ReadReq miss cycles 352system.cpu.dcache.ReadReq_miss_latency::total 5756000 # number of ReadReq miss cycles 353system.cpu.dcache.WriteReq_miss_latency::cpu.data 8522000 # number of WriteReq miss cycles 354system.cpu.dcache.WriteReq_miss_latency::total 8522000 # number of WriteReq miss cycles 355system.cpu.dcache.demand_miss_latency::cpu.data 14278000 # number of demand (read+write) miss cycles 356system.cpu.dcache.demand_miss_latency::total 14278000 # number of demand (read+write) miss cycles 357system.cpu.dcache.overall_miss_latency::cpu.data 14278000 # number of overall miss cycles 358system.cpu.dcache.overall_miss_latency::total 14278000 # number of overall miss cycles |
| 360system.cpu.dcache.ReadReq_accesses::cpu.data 718 # number of ReadReq accesses(hits+misses) 361system.cpu.dcache.ReadReq_accesses::total 718 # number of ReadReq accesses(hits+misses) 362system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) 363system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) 364system.cpu.dcache.demand_accesses::cpu.data 1391 # number of demand (read+write) accesses 365system.cpu.dcache.demand_accesses::total 1391 # number of demand (read+write) accesses 366system.cpu.dcache.overall_accesses::cpu.data 1391 # number of overall (read+write) accesses 367system.cpu.dcache.overall_accesses::total 1391 # number of overall (read+write) accesses 368system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.077994 # miss rate for ReadReq accesses 369system.cpu.dcache.ReadReq_miss_rate::total 0.077994 # miss rate for ReadReq accesses 370system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.121842 # miss rate for WriteReq accesses 371system.cpu.dcache.WriteReq_miss_rate::total 0.121842 # miss rate for WriteReq accesses 372system.cpu.dcache.demand_miss_rate::cpu.data 0.099209 # miss rate for demand accesses 373system.cpu.dcache.demand_miss_rate::total 0.099209 # miss rate for demand accesses 374system.cpu.dcache.overall_miss_rate::cpu.data 0.099209 # miss rate for overall accesses 375system.cpu.dcache.overall_miss_rate::total 0.099209 # miss rate for overall accesses | 359system.cpu.dcache.ReadReq_accesses::cpu.data 718 # number of ReadReq accesses(hits+misses) 360system.cpu.dcache.ReadReq_accesses::total 718 # number of ReadReq accesses(hits+misses) 361system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) 362system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) 363system.cpu.dcache.demand_accesses::cpu.data 1391 # number of demand (read+write) accesses 364system.cpu.dcache.demand_accesses::total 1391 # number of demand (read+write) accesses 365system.cpu.dcache.overall_accesses::cpu.data 1391 # number of overall (read+write) accesses 366system.cpu.dcache.overall_accesses::total 1391 # number of overall (read+write) accesses 367system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.077994 # miss rate for ReadReq accesses 368system.cpu.dcache.ReadReq_miss_rate::total 0.077994 # miss rate for ReadReq accesses 369system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.121842 # miss rate for WriteReq accesses 370system.cpu.dcache.WriteReq_miss_rate::total 0.121842 # miss rate for WriteReq accesses 371system.cpu.dcache.demand_miss_rate::cpu.data 0.099209 # miss rate for demand accesses 372system.cpu.dcache.demand_miss_rate::total 0.099209 # miss rate for demand accesses 373system.cpu.dcache.overall_miss_rate::cpu.data 0.099209 # miss rate for overall accesses 374system.cpu.dcache.overall_miss_rate::total 0.099209 # miss rate for overall accesses |
| 376system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 98821.428571 # average ReadReq miss latency 377system.cpu.dcache.ReadReq_avg_miss_latency::total 98821.428571 # average ReadReq miss latency 378system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102817.073171 # average WriteReq miss latency 379system.cpu.dcache.WriteReq_avg_miss_latency::total 102817.073171 # average WriteReq miss latency 380system.cpu.dcache.demand_avg_miss_latency::cpu.data 101195.652174 # average overall miss latency 381system.cpu.dcache.demand_avg_miss_latency::total 101195.652174 # average overall miss latency 382system.cpu.dcache.overall_avg_miss_latency::cpu.data 101195.652174 # average overall miss latency 383system.cpu.dcache.overall_avg_miss_latency::total 101195.652174 # average overall miss latency | 375system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102785.714286 # average ReadReq miss latency 376system.cpu.dcache.ReadReq_avg_miss_latency::total 102785.714286 # average ReadReq miss latency 377system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 103926.829268 # average WriteReq miss latency 378system.cpu.dcache.WriteReq_avg_miss_latency::total 103926.829268 # average WriteReq miss latency 379system.cpu.dcache.demand_avg_miss_latency::cpu.data 103463.768116 # average overall miss latency 380system.cpu.dcache.demand_avg_miss_latency::total 103463.768116 # average overall miss latency 381system.cpu.dcache.overall_avg_miss_latency::cpu.data 103463.768116 # average overall miss latency 382system.cpu.dcache.overall_avg_miss_latency::total 103463.768116 # average overall miss latency |
| 384system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 385system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 386system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 387system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 388system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 389system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 390system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses 391system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses 392system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82 # number of WriteReq MSHR misses 393system.cpu.dcache.WriteReq_mshr_misses::total 82 # number of WriteReq MSHR misses 394system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 395system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses 396system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses 397system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses | 383system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 384system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 385system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 386system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 387system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 388system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 389system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses 390system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses 391system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82 # number of WriteReq MSHR misses 392system.cpu.dcache.WriteReq_mshr_misses::total 82 # number of WriteReq MSHR misses 393system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 394system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses 395system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses 396system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses |
| 398system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5422000 # number of ReadReq MSHR miss cycles 399system.cpu.dcache.ReadReq_mshr_miss_latency::total 5422000 # number of ReadReq MSHR miss cycles 400system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8267000 # number of WriteReq MSHR miss cycles 401system.cpu.dcache.WriteReq_mshr_miss_latency::total 8267000 # number of WriteReq MSHR miss cycles 402system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13689000 # number of demand (read+write) MSHR miss cycles 403system.cpu.dcache.demand_mshr_miss_latency::total 13689000 # number of demand (read+write) MSHR miss cycles 404system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13689000 # number of overall MSHR miss cycles 405system.cpu.dcache.overall_mshr_miss_latency::total 13689000 # number of overall MSHR miss cycles | 397system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5644000 # number of ReadReq MSHR miss cycles 398system.cpu.dcache.ReadReq_mshr_miss_latency::total 5644000 # number of ReadReq MSHR miss cycles 399system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8358000 # number of WriteReq MSHR miss cycles 400system.cpu.dcache.WriteReq_mshr_miss_latency::total 8358000 # number of WriteReq MSHR miss cycles 401system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14002000 # number of demand (read+write) MSHR miss cycles 402system.cpu.dcache.demand_mshr_miss_latency::total 14002000 # number of demand (read+write) MSHR miss cycles 403system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14002000 # number of overall MSHR miss cycles 404system.cpu.dcache.overall_mshr_miss_latency::total 14002000 # number of overall MSHR miss cycles |
| 406system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.077994 # mshr miss rate for ReadReq accesses 407system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.077994 # mshr miss rate for ReadReq accesses 408system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.121842 # mshr miss rate for WriteReq accesses 409system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.121842 # mshr miss rate for WriteReq accesses 410system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.099209 # mshr miss rate for demand accesses 411system.cpu.dcache.demand_mshr_miss_rate::total 0.099209 # mshr miss rate for demand accesses 412system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.099209 # mshr miss rate for overall accesses 413system.cpu.dcache.overall_mshr_miss_rate::total 0.099209 # mshr miss rate for overall accesses | 405system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.077994 # mshr miss rate for ReadReq accesses 406system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.077994 # mshr miss rate for ReadReq accesses 407system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.121842 # mshr miss rate for WriteReq accesses 408system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.121842 # mshr miss rate for WriteReq accesses 409system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.099209 # mshr miss rate for demand accesses 410system.cpu.dcache.demand_mshr_miss_rate::total 0.099209 # mshr miss rate for demand accesses 411system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.099209 # mshr miss rate for overall accesses 412system.cpu.dcache.overall_mshr_miss_rate::total 0.099209 # mshr miss rate for overall accesses |
| 414system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 96821.428571 # average ReadReq mshr miss latency 415system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 96821.428571 # average ReadReq mshr miss latency 416system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100817.073171 # average WriteReq mshr miss latency 417system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100817.073171 # average WriteReq mshr miss latency 418system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency 419system.cpu.dcache.demand_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency 420system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency 421system.cpu.dcache.overall_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency 422system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states | 413system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100785.714286 # average ReadReq mshr miss latency 414system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100785.714286 # average ReadReq mshr miss latency 415system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 101926.829268 # average WriteReq mshr miss latency 416system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 101926.829268 # average WriteReq mshr miss latency 417system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101463.768116 # average overall mshr miss latency 418system.cpu.dcache.demand_avg_mshr_miss_latency::total 101463.768116 # average overall mshr miss latency 419system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101463.768116 # average overall mshr miss latency 420system.cpu.dcache.overall_avg_mshr_miss_latency::total 101463.768116 # average overall mshr miss latency 421system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states |
| 423system.cpu.icache.tags.replacements 71 # number of replacements | 422system.cpu.icache.tags.replacements 71 # number of replacements |
| 424system.cpu.icache.tags.tagsinuse 98.062907 # Cycle average of tags in use | 423system.cpu.icache.tags.tagsinuse 98.163046 # Cycle average of tags in use |
| 425system.cpu.icache.tags.total_refs 5333 # Total number of references to valid blocks. 426system.cpu.icache.tags.sampled_refs 259 # Sample count of references to valid blocks. 427system.cpu.icache.tags.avg_refs 20.590734 # Average number of references to valid blocks. 428system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 424system.cpu.icache.tags.total_refs 5333 # Total number of references to valid blocks. 425system.cpu.icache.tags.sampled_refs 259 # Sample count of references to valid blocks. 426system.cpu.icache.tags.avg_refs 20.590734 # Average number of references to valid blocks. 427system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 429system.cpu.icache.tags.occ_blocks::cpu.inst 98.062907 # Average occupied blocks per requestor 430system.cpu.icache.tags.occ_percent::cpu.inst 0.383058 # Average percentage of cache occupancy 431system.cpu.icache.tags.occ_percent::total 0.383058 # Average percentage of cache occupancy | 428system.cpu.icache.tags.occ_blocks::cpu.inst 98.163046 # Average occupied blocks per requestor 429system.cpu.icache.tags.occ_percent::cpu.inst 0.383449 # Average percentage of cache occupancy 430system.cpu.icache.tags.occ_percent::total 0.383449 # Average percentage of cache occupancy |
| 432system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id | 431system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id |
| 433system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id 434system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id | 432system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id 433system.cpu.icache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id |
| 435system.cpu.icache.tags.occ_task_id_percent::1024 0.734375 # Percentage of cache occupancy per task id 436system.cpu.icache.tags.tag_accesses 11443 # Number of tag accesses 437system.cpu.icache.tags.data_accesses 11443 # Number of data accesses | 434system.cpu.icache.tags.occ_task_id_percent::1024 0.734375 # Percentage of cache occupancy per task id 435system.cpu.icache.tags.tag_accesses 11443 # Number of tag accesses 436system.cpu.icache.tags.data_accesses 11443 # Number of data accesses |
| 438system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states | 437system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states |
| 439system.cpu.icache.ReadReq_hits::cpu.inst 5333 # number of ReadReq hits 440system.cpu.icache.ReadReq_hits::total 5333 # number of ReadReq hits 441system.cpu.icache.demand_hits::cpu.inst 5333 # number of demand (read+write) hits 442system.cpu.icache.demand_hits::total 5333 # number of demand (read+write) hits 443system.cpu.icache.overall_hits::cpu.inst 5333 # number of overall hits 444system.cpu.icache.overall_hits::total 5333 # number of overall hits 445system.cpu.icache.ReadReq_misses::cpu.inst 259 # number of ReadReq misses 446system.cpu.icache.ReadReq_misses::total 259 # number of ReadReq misses 447system.cpu.icache.demand_misses::cpu.inst 259 # number of demand (read+write) misses 448system.cpu.icache.demand_misses::total 259 # number of demand (read+write) misses 449system.cpu.icache.overall_misses::cpu.inst 259 # number of overall misses 450system.cpu.icache.overall_misses::total 259 # number of overall misses | 438system.cpu.icache.ReadReq_hits::cpu.inst 5333 # number of ReadReq hits 439system.cpu.icache.ReadReq_hits::total 5333 # number of ReadReq hits 440system.cpu.icache.demand_hits::cpu.inst 5333 # number of demand (read+write) hits 441system.cpu.icache.demand_hits::total 5333 # number of demand (read+write) hits 442system.cpu.icache.overall_hits::cpu.inst 5333 # number of overall hits 443system.cpu.icache.overall_hits::total 5333 # number of overall hits 444system.cpu.icache.ReadReq_misses::cpu.inst 259 # number of ReadReq misses 445system.cpu.icache.ReadReq_misses::total 259 # number of ReadReq misses 446system.cpu.icache.demand_misses::cpu.inst 259 # number of demand (read+write) misses 447system.cpu.icache.demand_misses::total 259 # number of demand (read+write) misses 448system.cpu.icache.overall_misses::cpu.inst 259 # number of overall misses 449system.cpu.icache.overall_misses::total 259 # number of overall misses |
| 451system.cpu.icache.ReadReq_miss_latency::cpu.inst 26199000 # number of ReadReq miss cycles 452system.cpu.icache.ReadReq_miss_latency::total 26199000 # number of ReadReq miss cycles 453system.cpu.icache.demand_miss_latency::cpu.inst 26199000 # number of demand (read+write) miss cycles 454system.cpu.icache.demand_miss_latency::total 26199000 # number of demand (read+write) miss cycles 455system.cpu.icache.overall_miss_latency::cpu.inst 26199000 # number of overall miss cycles 456system.cpu.icache.overall_miss_latency::total 26199000 # number of overall miss cycles | 450system.cpu.icache.ReadReq_miss_latency::cpu.inst 26157000 # number of ReadReq miss cycles 451system.cpu.icache.ReadReq_miss_latency::total 26157000 # number of ReadReq miss cycles 452system.cpu.icache.demand_miss_latency::cpu.inst 26157000 # number of demand (read+write) miss cycles 453system.cpu.icache.demand_miss_latency::total 26157000 # number of demand (read+write) miss cycles 454system.cpu.icache.overall_miss_latency::cpu.inst 26157000 # number of overall miss cycles 455system.cpu.icache.overall_miss_latency::total 26157000 # number of overall miss cycles |
| 457system.cpu.icache.ReadReq_accesses::cpu.inst 5592 # number of ReadReq accesses(hits+misses) 458system.cpu.icache.ReadReq_accesses::total 5592 # number of ReadReq accesses(hits+misses) 459system.cpu.icache.demand_accesses::cpu.inst 5592 # number of demand (read+write) accesses 460system.cpu.icache.demand_accesses::total 5592 # number of demand (read+write) accesses 461system.cpu.icache.overall_accesses::cpu.inst 5592 # number of overall (read+write) accesses 462system.cpu.icache.overall_accesses::total 5592 # number of overall (read+write) accesses 463system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.046316 # miss rate for ReadReq accesses 464system.cpu.icache.ReadReq_miss_rate::total 0.046316 # miss rate for ReadReq accesses 465system.cpu.icache.demand_miss_rate::cpu.inst 0.046316 # miss rate for demand accesses 466system.cpu.icache.demand_miss_rate::total 0.046316 # miss rate for demand accesses 467system.cpu.icache.overall_miss_rate::cpu.inst 0.046316 # miss rate for overall accesses 468system.cpu.icache.overall_miss_rate::total 0.046316 # miss rate for overall accesses | 456system.cpu.icache.ReadReq_accesses::cpu.inst 5592 # number of ReadReq accesses(hits+misses) 457system.cpu.icache.ReadReq_accesses::total 5592 # number of ReadReq accesses(hits+misses) 458system.cpu.icache.demand_accesses::cpu.inst 5592 # number of demand (read+write) accesses 459system.cpu.icache.demand_accesses::total 5592 # number of demand (read+write) accesses 460system.cpu.icache.overall_accesses::cpu.inst 5592 # number of overall (read+write) accesses 461system.cpu.icache.overall_accesses::total 5592 # number of overall (read+write) accesses 462system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.046316 # miss rate for ReadReq accesses 463system.cpu.icache.ReadReq_miss_rate::total 0.046316 # miss rate for ReadReq accesses 464system.cpu.icache.demand_miss_rate::cpu.inst 0.046316 # miss rate for demand accesses 465system.cpu.icache.demand_miss_rate::total 0.046316 # miss rate for demand accesses 466system.cpu.icache.overall_miss_rate::cpu.inst 0.046316 # miss rate for overall accesses 467system.cpu.icache.overall_miss_rate::total 0.046316 # miss rate for overall accesses |
| 469system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101154.440154 # average ReadReq miss latency 470system.cpu.icache.ReadReq_avg_miss_latency::total 101154.440154 # average ReadReq miss latency 471system.cpu.icache.demand_avg_miss_latency::cpu.inst 101154.440154 # average overall miss latency 472system.cpu.icache.demand_avg_miss_latency::total 101154.440154 # average overall miss latency 473system.cpu.icache.overall_avg_miss_latency::cpu.inst 101154.440154 # average overall miss latency 474system.cpu.icache.overall_avg_miss_latency::total 101154.440154 # average overall miss latency | 468system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100992.277992 # average ReadReq miss latency 469system.cpu.icache.ReadReq_avg_miss_latency::total 100992.277992 # average ReadReq miss latency 470system.cpu.icache.demand_avg_miss_latency::cpu.inst 100992.277992 # average overall miss latency 471system.cpu.icache.demand_avg_miss_latency::total 100992.277992 # average overall miss latency 472system.cpu.icache.overall_avg_miss_latency::cpu.inst 100992.277992 # average overall miss latency 473system.cpu.icache.overall_avg_miss_latency::total 100992.277992 # average overall miss latency |
| 475system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 476system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 477system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 478system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 479system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 480system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 481system.cpu.icache.ReadReq_mshr_misses::cpu.inst 259 # number of ReadReq MSHR misses 482system.cpu.icache.ReadReq_mshr_misses::total 259 # number of ReadReq MSHR misses 483system.cpu.icache.demand_mshr_misses::cpu.inst 259 # number of demand (read+write) MSHR misses 484system.cpu.icache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses 485system.cpu.icache.overall_mshr_misses::cpu.inst 259 # number of overall MSHR misses 486system.cpu.icache.overall_mshr_misses::total 259 # number of overall MSHR misses | 474system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 475system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 476system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 477system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 478system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 479system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 480system.cpu.icache.ReadReq_mshr_misses::cpu.inst 259 # number of ReadReq MSHR misses 481system.cpu.icache.ReadReq_mshr_misses::total 259 # number of ReadReq MSHR misses 482system.cpu.icache.demand_mshr_misses::cpu.inst 259 # number of demand (read+write) MSHR misses 483system.cpu.icache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses 484system.cpu.icache.overall_mshr_misses::cpu.inst 259 # number of overall MSHR misses 485system.cpu.icache.overall_mshr_misses::total 259 # number of overall MSHR misses |
| 487system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25681000 # number of ReadReq MSHR miss cycles 488system.cpu.icache.ReadReq_mshr_miss_latency::total 25681000 # number of ReadReq MSHR miss cycles 489system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25681000 # number of demand (read+write) MSHR miss cycles 490system.cpu.icache.demand_mshr_miss_latency::total 25681000 # number of demand (read+write) MSHR miss cycles 491system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25681000 # number of overall MSHR miss cycles 492system.cpu.icache.overall_mshr_miss_latency::total 25681000 # number of overall MSHR miss cycles | 486system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25639000 # number of ReadReq MSHR miss cycles 487system.cpu.icache.ReadReq_mshr_miss_latency::total 25639000 # number of ReadReq MSHR miss cycles 488system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25639000 # number of demand (read+write) MSHR miss cycles 489system.cpu.icache.demand_mshr_miss_latency::total 25639000 # number of demand (read+write) MSHR miss cycles 490system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25639000 # number of overall MSHR miss cycles 491system.cpu.icache.overall_mshr_miss_latency::total 25639000 # number of overall MSHR miss cycles |
| 493system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for ReadReq accesses 494system.cpu.icache.ReadReq_mshr_miss_rate::total 0.046316 # mshr miss rate for ReadReq accesses 495system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for demand accesses 496system.cpu.icache.demand_mshr_miss_rate::total 0.046316 # mshr miss rate for demand accesses 497system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for overall accesses 498system.cpu.icache.overall_mshr_miss_rate::total 0.046316 # mshr miss rate for overall accesses | 492system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for ReadReq accesses 493system.cpu.icache.ReadReq_mshr_miss_rate::total 0.046316 # mshr miss rate for ReadReq accesses 494system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for demand accesses 495system.cpu.icache.demand_mshr_miss_rate::total 0.046316 # mshr miss rate for demand accesses 496system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for overall accesses 497system.cpu.icache.overall_mshr_miss_rate::total 0.046316 # mshr miss rate for overall accesses |
| 499system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99154.440154 # average ReadReq mshr miss latency 500system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99154.440154 # average ReadReq mshr miss latency 501system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency 502system.cpu.icache.demand_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency 503system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency 504system.cpu.icache.overall_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency | 498system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98992.277992 # average ReadReq mshr miss latency 499system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98992.277992 # average ReadReq mshr miss latency 500system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98992.277992 # average overall mshr miss latency 501system.cpu.icache.demand_avg_mshr_miss_latency::total 98992.277992 # average overall mshr miss latency 502system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98992.277992 # average overall mshr miss latency 503system.cpu.icache.overall_avg_mshr_miss_latency::total 98992.277992 # average overall mshr miss latency |
| 505system.l2bus.snoop_filter.tot_requests 468 # Total number of requests made to the snoop filter. 506system.l2bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. 507system.l2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 508system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 509system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 510system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 504system.l2bus.snoop_filter.tot_requests 468 # Total number of requests made to the snoop filter. 505system.l2bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. 506system.l2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 507system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 508system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 509system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 511system.l2bus.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states | 510system.l2bus.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states |
| 512system.l2bus.trans_dist::ReadResp 315 # Transaction distribution 513system.l2bus.trans_dist::CleanEvict 71 # Transaction distribution 514system.l2bus.trans_dist::ReadExReq 82 # Transaction distribution 515system.l2bus.trans_dist::ReadExResp 82 # Transaction distribution 516system.l2bus.trans_dist::ReadSharedReq 315 # Transaction distribution 517system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 589 # Packet count per connected master and slave (bytes) 518system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) 519system.l2bus.pkt_count::total 865 # Packet count per connected master and slave (bytes) --- 11 unchanged lines hidden (view full) --- 531system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 532system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 533system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram 534system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 535system.l2bus.snoop_fanout::total 397 # Request fanout histogram 536system.l2bus.reqLayer0.occupancy 468000 # Layer occupancy (ticks) 537system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) 538system.l2bus.respLayer0.occupancy 777000 # Layer occupancy (ticks) | 511system.l2bus.trans_dist::ReadResp 315 # Transaction distribution 512system.l2bus.trans_dist::CleanEvict 71 # Transaction distribution 513system.l2bus.trans_dist::ReadExReq 82 # Transaction distribution 514system.l2bus.trans_dist::ReadExResp 82 # Transaction distribution 515system.l2bus.trans_dist::ReadSharedReq 315 # Transaction distribution 516system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 589 # Packet count per connected master and slave (bytes) 517system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) 518system.l2bus.pkt_count::total 865 # Packet count per connected master and slave (bytes) --- 11 unchanged lines hidden (view full) --- 530system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 531system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 532system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram 533system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 534system.l2bus.snoop_fanout::total 397 # Request fanout histogram 535system.l2bus.reqLayer0.occupancy 468000 # Layer occupancy (ticks) 536system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) 537system.l2bus.respLayer0.occupancy 777000 # Layer occupancy (ticks) |
| 539system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) | 538system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) |
| 540system.l2bus.respLayer1.occupancy 414000 # Layer occupancy (ticks) 541system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) | 539system.l2bus.respLayer1.occupancy 414000 # Layer occupancy (ticks) 540system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) |
| 542system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states | 541system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states |
| 543system.l2cache.tags.replacements 0 # number of replacements | 542system.l2cache.tags.replacements 0 # number of replacements |
| 544system.l2cache.tags.tagsinuse 144.000978 # Cycle average of tags in use | 543system.l2cache.tags.tagsinuse 200.697345 # Cycle average of tags in use |
| 545system.l2cache.tags.total_refs 73 # Total number of references to valid blocks. | 544system.l2cache.tags.total_refs 73 # Total number of references to valid blocks. |
| 546system.l2cache.tags.sampled_refs 312 # Sample count of references to valid blocks. 547system.l2cache.tags.avg_refs 0.233974 # Average number of references to valid blocks. | 545system.l2cache.tags.sampled_refs 394 # Sample count of references to valid blocks. 546system.l2cache.tags.avg_refs 0.185279 # Average number of references to valid blocks. |
| 548system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 547system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 549system.l2cache.tags.occ_blocks::cpu.inst 117.700213 # Average occupied blocks per requestor 550system.l2cache.tags.occ_blocks::cpu.data 26.300766 # Average occupied blocks per requestor 551system.l2cache.tags.occ_percent::cpu.inst 0.028735 # Average percentage of cache occupancy 552system.l2cache.tags.occ_percent::cpu.data 0.006421 # Average percentage of cache occupancy 553system.l2cache.tags.occ_percent::total 0.035156 # Average percentage of cache occupancy 554system.l2cache.tags.occ_task_id_blocks::1024 312 # Occupied blocks per task id | 548system.l2cache.tags.occ_blocks::cpu.inst 117.835895 # Average occupied blocks per requestor 549system.l2cache.tags.occ_blocks::cpu.data 82.861451 # Average occupied blocks per requestor 550system.l2cache.tags.occ_percent::cpu.inst 0.028769 # Average percentage of cache occupancy 551system.l2cache.tags.occ_percent::cpu.data 0.020230 # Average percentage of cache occupancy 552system.l2cache.tags.occ_percent::total 0.048998 # Average percentage of cache occupancy 553system.l2cache.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id |
| 555system.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id | 554system.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id |
| 556system.l2cache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id 557system.l2cache.tags.occ_task_id_percent::1024 0.076172 # Percentage of cache occupancy per task id | 555system.l2cache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id 556system.l2cache.tags.occ_task_id_percent::1024 0.096191 # Percentage of cache occupancy per task id |
| 558system.l2cache.tags.tag_accesses 4130 # Number of tag accesses 559system.l2cache.tags.data_accesses 4130 # Number of data accesses | 557system.l2cache.tags.tag_accesses 4130 # Number of tag accesses 558system.l2cache.tags.data_accesses 4130 # Number of data accesses |
| 560system.l2cache.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states | 559system.l2cache.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states |
| 561system.l2cache.ReadSharedReq_hits::cpu.inst 2 # number of ReadSharedReq hits 562system.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits 563system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits 564system.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 565system.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 566system.l2cache.demand_hits::total 3 # number of demand (read+write) hits 567system.l2cache.overall_hits::cpu.inst 2 # number of overall hits 568system.l2cache.overall_hits::cpu.data 1 # number of overall hits --- 4 unchanged lines hidden (view full) --- 573system.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses 574system.l2cache.ReadSharedReq_misses::total 312 # number of ReadSharedReq misses 575system.l2cache.demand_misses::cpu.inst 257 # number of demand (read+write) misses 576system.l2cache.demand_misses::cpu.data 137 # number of demand (read+write) misses 577system.l2cache.demand_misses::total 394 # number of demand (read+write) misses 578system.l2cache.overall_misses::cpu.inst 257 # number of overall misses 579system.l2cache.overall_misses::cpu.data 137 # number of overall misses 580system.l2cache.overall_misses::total 394 # number of overall misses | 560system.l2cache.ReadSharedReq_hits::cpu.inst 2 # number of ReadSharedReq hits 561system.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits 562system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits 563system.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 564system.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 565system.l2cache.demand_hits::total 3 # number of demand (read+write) hits 566system.l2cache.overall_hits::cpu.inst 2 # number of overall hits 567system.l2cache.overall_hits::cpu.data 1 # number of overall hits --- 4 unchanged lines hidden (view full) --- 572system.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses 573system.l2cache.ReadSharedReq_misses::total 312 # number of ReadSharedReq misses 574system.l2cache.demand_misses::cpu.inst 257 # number of demand (read+write) misses 575system.l2cache.demand_misses::cpu.data 137 # number of demand (read+write) misses 576system.l2cache.demand_misses::total 394 # number of demand (read+write) misses 577system.l2cache.overall_misses::cpu.inst 257 # number of overall misses 578system.l2cache.overall_misses::cpu.data 137 # number of overall misses 579system.l2cache.overall_misses::total 394 # number of overall misses |
| 581system.l2cache.ReadExReq_miss_latency::cpu.data 8021000 # number of ReadExReq miss cycles 582system.l2cache.ReadExReq_miss_latency::total 8021000 # number of ReadExReq miss cycles 583system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24858000 # number of ReadSharedReq miss cycles 584system.l2cache.ReadSharedReq_miss_latency::cpu.data 5231000 # number of ReadSharedReq miss cycles 585system.l2cache.ReadSharedReq_miss_latency::total 30089000 # number of ReadSharedReq miss cycles 586system.l2cache.demand_miss_latency::cpu.inst 24858000 # number of demand (read+write) miss cycles 587system.l2cache.demand_miss_latency::cpu.data 13252000 # number of demand (read+write) miss cycles 588system.l2cache.demand_miss_latency::total 38110000 # number of demand (read+write) miss cycles 589system.l2cache.overall_miss_latency::cpu.inst 24858000 # number of overall miss cycles 590system.l2cache.overall_miss_latency::cpu.data 13252000 # number of overall miss cycles 591system.l2cache.overall_miss_latency::total 38110000 # number of overall miss cycles | 580system.l2cache.ReadExReq_miss_latency::cpu.data 8112000 # number of ReadExReq miss cycles 581system.l2cache.ReadExReq_miss_latency::total 8112000 # number of ReadExReq miss cycles 582system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24816000 # number of ReadSharedReq miss cycles 583system.l2cache.ReadSharedReq_miss_latency::cpu.data 5453000 # number of ReadSharedReq miss cycles 584system.l2cache.ReadSharedReq_miss_latency::total 30269000 # number of ReadSharedReq miss cycles 585system.l2cache.demand_miss_latency::cpu.inst 24816000 # number of demand (read+write) miss cycles 586system.l2cache.demand_miss_latency::cpu.data 13565000 # number of demand (read+write) miss cycles 587system.l2cache.demand_miss_latency::total 38381000 # number of demand (read+write) miss cycles 588system.l2cache.overall_miss_latency::cpu.inst 24816000 # number of overall miss cycles 589system.l2cache.overall_miss_latency::cpu.data 13565000 # number of overall miss cycles 590system.l2cache.overall_miss_latency::total 38381000 # number of overall miss cycles |
| 592system.l2cache.ReadExReq_accesses::cpu.data 82 # number of ReadExReq accesses(hits+misses) 593system.l2cache.ReadExReq_accesses::total 82 # number of ReadExReq accesses(hits+misses) 594system.l2cache.ReadSharedReq_accesses::cpu.inst 259 # number of ReadSharedReq accesses(hits+misses) 595system.l2cache.ReadSharedReq_accesses::cpu.data 56 # number of ReadSharedReq accesses(hits+misses) 596system.l2cache.ReadSharedReq_accesses::total 315 # number of ReadSharedReq accesses(hits+misses) 597system.l2cache.demand_accesses::cpu.inst 259 # number of demand (read+write) accesses 598system.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses 599system.l2cache.demand_accesses::total 397 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 606system.l2cache.ReadSharedReq_miss_rate::cpu.data 0.982143 # miss rate for ReadSharedReq accesses 607system.l2cache.ReadSharedReq_miss_rate::total 0.990476 # miss rate for ReadSharedReq accesses 608system.l2cache.demand_miss_rate::cpu.inst 0.992278 # miss rate for demand accesses 609system.l2cache.demand_miss_rate::cpu.data 0.992754 # miss rate for demand accesses 610system.l2cache.demand_miss_rate::total 0.992443 # miss rate for demand accesses 611system.l2cache.overall_miss_rate::cpu.inst 0.992278 # miss rate for overall accesses 612system.l2cache.overall_miss_rate::cpu.data 0.992754 # miss rate for overall accesses 613system.l2cache.overall_miss_rate::total 0.992443 # miss rate for overall accesses | 591system.l2cache.ReadExReq_accesses::cpu.data 82 # number of ReadExReq accesses(hits+misses) 592system.l2cache.ReadExReq_accesses::total 82 # number of ReadExReq accesses(hits+misses) 593system.l2cache.ReadSharedReq_accesses::cpu.inst 259 # number of ReadSharedReq accesses(hits+misses) 594system.l2cache.ReadSharedReq_accesses::cpu.data 56 # number of ReadSharedReq accesses(hits+misses) 595system.l2cache.ReadSharedReq_accesses::total 315 # number of ReadSharedReq accesses(hits+misses) 596system.l2cache.demand_accesses::cpu.inst 259 # number of demand (read+write) accesses 597system.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses 598system.l2cache.demand_accesses::total 397 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 605system.l2cache.ReadSharedReq_miss_rate::cpu.data 0.982143 # miss rate for ReadSharedReq accesses 606system.l2cache.ReadSharedReq_miss_rate::total 0.990476 # miss rate for ReadSharedReq accesses 607system.l2cache.demand_miss_rate::cpu.inst 0.992278 # miss rate for demand accesses 608system.l2cache.demand_miss_rate::cpu.data 0.992754 # miss rate for demand accesses 609system.l2cache.demand_miss_rate::total 0.992443 # miss rate for demand accesses 610system.l2cache.overall_miss_rate::cpu.inst 0.992278 # miss rate for overall accesses 611system.l2cache.overall_miss_rate::cpu.data 0.992754 # miss rate for overall accesses 612system.l2cache.overall_miss_rate::total 0.992443 # miss rate for overall accesses |
| 614system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97817.073171 # average ReadExReq miss latency 615system.l2cache.ReadExReq_avg_miss_latency::total 97817.073171 # average ReadExReq miss latency 616system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96723.735409 # average ReadSharedReq miss latency 617system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95109.090909 # average ReadSharedReq miss latency 618system.l2cache.ReadSharedReq_avg_miss_latency::total 96439.102564 # average ReadSharedReq miss latency 619system.l2cache.demand_avg_miss_latency::cpu.inst 96723.735409 # average overall miss latency 620system.l2cache.demand_avg_miss_latency::cpu.data 96729.927007 # average overall miss latency 621system.l2cache.demand_avg_miss_latency::total 96725.888325 # average overall miss latency 622system.l2cache.overall_avg_miss_latency::cpu.inst 96723.735409 # average overall miss latency 623system.l2cache.overall_avg_miss_latency::cpu.data 96729.927007 # average overall miss latency 624system.l2cache.overall_avg_miss_latency::total 96725.888325 # average overall miss latency | 613system.l2cache.ReadExReq_avg_miss_latency::cpu.data 98926.829268 # average ReadExReq miss latency 614system.l2cache.ReadExReq_avg_miss_latency::total 98926.829268 # average ReadExReq miss latency 615system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96560.311284 # average ReadSharedReq miss latency 616system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99145.454545 # average ReadSharedReq miss latency 617system.l2cache.ReadSharedReq_avg_miss_latency::total 97016.025641 # average ReadSharedReq miss latency 618system.l2cache.demand_avg_miss_latency::cpu.inst 96560.311284 # average overall miss latency 619system.l2cache.demand_avg_miss_latency::cpu.data 99014.598540 # average overall miss latency 620system.l2cache.demand_avg_miss_latency::total 97413.705584 # average overall miss latency 621system.l2cache.overall_avg_miss_latency::cpu.inst 96560.311284 # average overall miss latency 622system.l2cache.overall_avg_miss_latency::cpu.data 99014.598540 # average overall miss latency 623system.l2cache.overall_avg_miss_latency::total 97413.705584 # average overall miss latency |
| 625system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 626system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 627system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 628system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 629system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 630system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 631system.l2cache.ReadExReq_mshr_misses::cpu.data 82 # number of ReadExReq MSHR misses 632system.l2cache.ReadExReq_mshr_misses::total 82 # number of ReadExReq MSHR misses 633system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 257 # number of ReadSharedReq MSHR misses 634system.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses 635system.l2cache.ReadSharedReq_mshr_misses::total 312 # number of ReadSharedReq MSHR misses 636system.l2cache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses 637system.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses 638system.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses 639system.l2cache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses 640system.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses 641system.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses | 624system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 625system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 626system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 627system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 628system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 629system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 630system.l2cache.ReadExReq_mshr_misses::cpu.data 82 # number of ReadExReq MSHR misses 631system.l2cache.ReadExReq_mshr_misses::total 82 # number of ReadExReq MSHR misses 632system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 257 # number of ReadSharedReq MSHR misses 633system.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses 634system.l2cache.ReadSharedReq_mshr_misses::total 312 # number of ReadSharedReq MSHR misses 635system.l2cache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses 636system.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses 637system.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses 638system.l2cache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses 639system.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses 640system.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses |
| 642system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6381000 # number of ReadExReq MSHR miss cycles 643system.l2cache.ReadExReq_mshr_miss_latency::total 6381000 # number of ReadExReq MSHR miss cycles 644system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19718000 # number of ReadSharedReq MSHR miss cycles 645system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4131000 # number of ReadSharedReq MSHR miss cycles 646system.l2cache.ReadSharedReq_mshr_miss_latency::total 23849000 # number of ReadSharedReq MSHR miss cycles 647system.l2cache.demand_mshr_miss_latency::cpu.inst 19718000 # number of demand (read+write) MSHR miss cycles 648system.l2cache.demand_mshr_miss_latency::cpu.data 10512000 # number of demand (read+write) MSHR miss cycles 649system.l2cache.demand_mshr_miss_latency::total 30230000 # number of demand (read+write) MSHR miss cycles 650system.l2cache.overall_mshr_miss_latency::cpu.inst 19718000 # number of overall MSHR miss cycles 651system.l2cache.overall_mshr_miss_latency::cpu.data 10512000 # number of overall MSHR miss cycles 652system.l2cache.overall_mshr_miss_latency::total 30230000 # number of overall MSHR miss cycles | 641system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6472000 # number of ReadExReq MSHR miss cycles 642system.l2cache.ReadExReq_mshr_miss_latency::total 6472000 # number of ReadExReq MSHR miss cycles 643system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19676000 # number of ReadSharedReq MSHR miss cycles 644system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4353000 # number of ReadSharedReq MSHR miss cycles 645system.l2cache.ReadSharedReq_mshr_miss_latency::total 24029000 # number of ReadSharedReq MSHR miss cycles 646system.l2cache.demand_mshr_miss_latency::cpu.inst 19676000 # number of demand (read+write) MSHR miss cycles 647system.l2cache.demand_mshr_miss_latency::cpu.data 10825000 # number of demand (read+write) MSHR miss cycles 648system.l2cache.demand_mshr_miss_latency::total 30501000 # number of demand (read+write) MSHR miss cycles 649system.l2cache.overall_mshr_miss_latency::cpu.inst 19676000 # number of overall MSHR miss cycles 650system.l2cache.overall_mshr_miss_latency::cpu.data 10825000 # number of overall MSHR miss cycles 651system.l2cache.overall_mshr_miss_latency::total 30501000 # number of overall MSHR miss cycles |
| 653system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 654system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 655system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for ReadSharedReq accesses 656system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.982143 # mshr miss rate for ReadSharedReq accesses 657system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.990476 # mshr miss rate for ReadSharedReq accesses 658system.l2cache.demand_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for demand accesses 659system.l2cache.demand_mshr_miss_rate::cpu.data 0.992754 # mshr miss rate for demand accesses 660system.l2cache.demand_mshr_miss_rate::total 0.992443 # mshr miss rate for demand accesses 661system.l2cache.overall_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for overall accesses 662system.l2cache.overall_mshr_miss_rate::cpu.data 0.992754 # mshr miss rate for overall accesses 663system.l2cache.overall_mshr_miss_rate::total 0.992443 # mshr miss rate for overall accesses | 652system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 653system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 654system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for ReadSharedReq accesses 655system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.982143 # mshr miss rate for ReadSharedReq accesses 656system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.990476 # mshr miss rate for ReadSharedReq accesses 657system.l2cache.demand_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for demand accesses 658system.l2cache.demand_mshr_miss_rate::cpu.data 0.992754 # mshr miss rate for demand accesses 659system.l2cache.demand_mshr_miss_rate::total 0.992443 # mshr miss rate for demand accesses 660system.l2cache.overall_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for overall accesses 661system.l2cache.overall_mshr_miss_rate::cpu.data 0.992754 # mshr miss rate for overall accesses 662system.l2cache.overall_mshr_miss_rate::total 0.992443 # mshr miss rate for overall accesses |
| 664system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77817.073171 # average ReadExReq mshr miss latency 665system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77817.073171 # average ReadExReq mshr miss latency 666system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76723.735409 # average ReadSharedReq mshr miss latency 667system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75109.090909 # average ReadSharedReq mshr miss latency 668system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76439.102564 # average ReadSharedReq mshr miss latency 669system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency 670system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency 671system.l2cache.demand_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency 672system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency 673system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency 674system.l2cache.overall_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency 675system.membus.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states | 663system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.829268 # average ReadExReq mshr miss latency 664system.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.829268 # average ReadExReq mshr miss latency 665system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76560.311284 # average ReadSharedReq mshr miss latency 666system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79145.454545 # average ReadSharedReq mshr miss latency 667system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77016.025641 # average ReadSharedReq mshr miss latency 668system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76560.311284 # average overall mshr miss latency 669system.l2cache.demand_avg_mshr_miss_latency::cpu.data 79014.598540 # average overall mshr miss latency 670system.l2cache.demand_avg_mshr_miss_latency::total 77413.705584 # average overall mshr miss latency 671system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76560.311284 # average overall mshr miss latency 672system.l2cache.overall_avg_mshr_miss_latency::cpu.data 79014.598540 # average overall mshr miss latency 673system.l2cache.overall_avg_mshr_miss_latency::total 77413.705584 # average overall mshr miss latency 674system.membus.snoop_filter.tot_requests 394 # Total number of requests made to the snoop filter. 675system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 676system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 677system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 678system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 679system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 680system.membus.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states |
| 676system.membus.trans_dist::ReadResp 312 # Transaction distribution 677system.membus.trans_dist::ReadExReq 82 # Transaction distribution 678system.membus.trans_dist::ReadExResp 82 # Transaction distribution 679system.membus.trans_dist::ReadSharedReq 312 # Transaction distribution 680system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 788 # Packet count per connected master and slave (bytes) 681system.membus.pkt_count::total 788 # Packet count per connected master and slave (bytes) 682system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 25216 # Cumulative packet size per connected master and slave (bytes) 683system.membus.pkt_size::total 25216 # Cumulative packet size per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 690system.membus.snoop_fanout::0 394 100.00% 100.00% # Request fanout histogram 691system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 692system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 693system.membus.snoop_fanout::min_value 0 # Request fanout histogram 694system.membus.snoop_fanout::max_value 0 # Request fanout histogram 695system.membus.snoop_fanout::total 394 # Request fanout histogram 696system.membus.reqLayer0.occupancy 394000 # Layer occupancy (ticks) 697system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) | 681system.membus.trans_dist::ReadResp 312 # Transaction distribution 682system.membus.trans_dist::ReadExReq 82 # Transaction distribution 683system.membus.trans_dist::ReadExResp 82 # Transaction distribution 684system.membus.trans_dist::ReadSharedReq 312 # Transaction distribution 685system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 788 # Packet count per connected master and slave (bytes) 686system.membus.pkt_count::total 788 # Packet count per connected master and slave (bytes) 687system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 25216 # Cumulative packet size per connected master and slave (bytes) 688system.membus.pkt_size::total 25216 # Cumulative packet size per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 695system.membus.snoop_fanout::0 394 100.00% 100.00% # Request fanout histogram 696system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 697system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 698system.membus.snoop_fanout::min_value 0 # Request fanout histogram 699system.membus.snoop_fanout::max_value 0 # Request fanout histogram 700system.membus.snoop_fanout::total 394 # Request fanout histogram 701system.membus.reqLayer0.occupancy 394000 # Layer occupancy (ticks) 702system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) |
| 698system.membus.respLayer0.occupancy 2102250 # Layer occupancy (ticks) | 703system.membus.respLayer0.occupancy 2102000 # Layer occupancy (ticks) |
| 699system.membus.respLayer0.utilization 3.9 # Layer utilization (%) 700 701---------- End Simulation Statistics ---------- | 704system.membus.respLayer0.utilization 3.9 # Layer utilization (%) 705 706---------- End Simulation Statistics ---------- |