| stats.txt (11502:e273e86a873d) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000053 # Number of seconds simulated 4sim_ticks 53334000 # Number of ticks simulated 5final_tick 53334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000053 # Number of seconds simulated 4sim_ticks 53334000 # Number of ticks simulated 5final_tick 53334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 429905 # Simulator instruction rate (inst/s) 8host_op_rate 429380 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4122052129 # Simulator tick rate (ticks/s) 10host_mem_usage 633208 # Number of bytes of host memory used | 7host_inst_rate 483647 # Simulator instruction rate (inst/s) 8host_op_rate 483274 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4642649843 # Simulator tick rate (ticks/s) 10host_mem_usage 677372 # Number of bytes of host memory used |
| 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 5548 # Number of instructions simulated 13sim_ops 5548 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 5548 # Number of instructions simulated 13sim_ops 5548 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states |
|
| 16system.mem_ctrl.bytes_read::cpu.inst 16448 # Number of bytes read from this memory 17system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::total 25216 # Number of bytes read from this memory 19system.mem_ctrl.bytes_inst_read::cpu.inst 16448 # Number of instructions bytes read from this memory 20system.mem_ctrl.bytes_inst_read::total 16448 # Number of instructions bytes read from this memory 21system.mem_ctrl.num_reads::cpu.inst 257 # Number of read requests responded to by this memory 22system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::total 394 # Number of read requests responded to by this memory --- 225 unchanged lines hidden (view full) --- 249system.mem_ctrl_1.preBackEnergy 2355000 # Energy for precharge background per rank (pJ) 250system.mem_ctrl_1.totalEnergy 36339615 # Total energy per rank (pJ) 251system.mem_ctrl_1.averagePower 773.553616 # Core power per rank (mW) 252system.mem_ctrl_1.memoryStateTime::IDLE 4798500 # Time in different power states 253system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states 254system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states 255system.mem_ctrl_1.memoryStateTime::ACT 41660500 # Time in different power states 256system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.mem_ctrl.bytes_read::cpu.inst 16448 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory 19system.mem_ctrl.bytes_read::total 25216 # Number of bytes read from this memory 20system.mem_ctrl.bytes_inst_read::cpu.inst 16448 # Number of instructions bytes read from this memory 21system.mem_ctrl.bytes_inst_read::total 16448 # Number of instructions bytes read from this memory 22system.mem_ctrl.num_reads::cpu.inst 257 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory 24system.mem_ctrl.num_reads::total 394 # Number of read requests responded to by this memory --- 225 unchanged lines hidden (view full) --- 250system.mem_ctrl_1.preBackEnergy 2355000 # Energy for precharge background per rank (pJ) 251system.mem_ctrl_1.totalEnergy 36339615 # Total energy per rank (pJ) 252system.mem_ctrl_1.averagePower 773.553616 # Core power per rank (mW) 253system.mem_ctrl_1.memoryStateTime::IDLE 4798500 # Time in different power states 254system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states 255system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states 256system.mem_ctrl_1.memoryStateTime::ACT 41660500 # Time in different power states 257system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 258system.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states |
|
| 257system.cpu.workload.num_syscalls 11 # Number of system calls | 259system.cpu.workload.num_syscalls 11 # Number of system calls |
| 260system.cpu.pwrStateResidencyTicks::ON 53334000 # Cumulative time (in ticks) in various power states |
|
| 258system.cpu.numCycles 53334 # number of cpu cycles simulated 259system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 260system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 261system.cpu.committedInsts 5548 # Number of instructions committed 262system.cpu.committedOps 5548 # Number of ops (including micro ops) committed 263system.cpu.num_int_alu_accesses 4660 # Number of integer alu accesses 264system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 265system.cpu.num_func_calls 146 # number of times a function call or return occured --- 42 unchanged lines hidden (view full) --- 308system.cpu.op_class::SimdFloatMult 0 0.00% 74.89% # Class of executed instruction 309system.cpu.op_class::SimdFloatMultAcc 0 0.00% 74.89% # Class of executed instruction 310system.cpu.op_class::SimdFloatSqrt 0 0.00% 74.89% # Class of executed instruction 311system.cpu.op_class::MemRead 726 12.99% 87.87% # Class of executed instruction 312system.cpu.op_class::MemWrite 678 12.13% 100.00% # Class of executed instruction 313system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 314system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 315system.cpu.op_class::total 5591 # Class of executed instruction | 261system.cpu.numCycles 53334 # number of cpu cycles simulated 262system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 263system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 264system.cpu.committedInsts 5548 # Number of instructions committed 265system.cpu.committedOps 5548 # Number of ops (including micro ops) committed 266system.cpu.num_int_alu_accesses 4660 # Number of integer alu accesses 267system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 268system.cpu.num_func_calls 146 # number of times a function call or return occured --- 42 unchanged lines hidden (view full) --- 311system.cpu.op_class::SimdFloatMult 0 0.00% 74.89% # Class of executed instruction 312system.cpu.op_class::SimdFloatMultAcc 0 0.00% 74.89% # Class of executed instruction 313system.cpu.op_class::SimdFloatSqrt 0 0.00% 74.89% # Class of executed instruction 314system.cpu.op_class::MemRead 726 12.99% 87.87% # Class of executed instruction 315system.cpu.op_class::MemWrite 678 12.13% 100.00% # Class of executed instruction 316system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 317system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 318system.cpu.op_class::total 5591 # Class of executed instruction |
| 319system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states |
|
| 316system.cpu.dcache.tags.replacements 0 # number of replacements 317system.cpu.dcache.tags.tagsinuse 83.743129 # Cycle average of tags in use 318system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. 319system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. 320system.cpu.dcache.tags.avg_refs 9.079710 # Average number of references to valid blocks. 321system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 322system.cpu.dcache.tags.occ_blocks::cpu.data 83.743129 # Average occupied blocks per requestor 323system.cpu.dcache.tags.occ_percent::cpu.data 0.081780 # Average percentage of cache occupancy 324system.cpu.dcache.tags.occ_percent::total 0.081780 # Average percentage of cache occupancy 325system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id 326system.cpu.dcache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id 327system.cpu.dcache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id 328system.cpu.dcache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id 329system.cpu.dcache.tags.tag_accesses 2920 # Number of tag accesses 330system.cpu.dcache.tags.data_accesses 2920 # Number of data accesses | 320system.cpu.dcache.tags.replacements 0 # number of replacements 321system.cpu.dcache.tags.tagsinuse 83.743129 # Cycle average of tags in use 322system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. 323system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. 324system.cpu.dcache.tags.avg_refs 9.079710 # Average number of references to valid blocks. 325system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 326system.cpu.dcache.tags.occ_blocks::cpu.data 83.743129 # Average occupied blocks per requestor 327system.cpu.dcache.tags.occ_percent::cpu.data 0.081780 # Average percentage of cache occupancy 328system.cpu.dcache.tags.occ_percent::total 0.081780 # Average percentage of cache occupancy 329system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id 330system.cpu.dcache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id 331system.cpu.dcache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id 332system.cpu.dcache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id 333system.cpu.dcache.tags.tag_accesses 2920 # Number of tag accesses 334system.cpu.dcache.tags.data_accesses 2920 # Number of data accesses |
| 335system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states |
|
| 331system.cpu.dcache.ReadReq_hits::cpu.data 662 # number of ReadReq hits 332system.cpu.dcache.ReadReq_hits::total 662 # number of ReadReq hits 333system.cpu.dcache.WriteReq_hits::cpu.data 591 # number of WriteReq hits 334system.cpu.dcache.WriteReq_hits::total 591 # number of WriteReq hits 335system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits 336system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits 337system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits 338system.cpu.dcache.overall_hits::total 1253 # number of overall hits --- 70 unchanged lines hidden (view full) --- 409system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 96821.428571 # average ReadReq mshr miss latency 410system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 96821.428571 # average ReadReq mshr miss latency 411system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100817.073171 # average WriteReq mshr miss latency 412system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100817.073171 # average WriteReq mshr miss latency 413system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency 414system.cpu.dcache.demand_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency 415system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency 416system.cpu.dcache.overall_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency | 336system.cpu.dcache.ReadReq_hits::cpu.data 662 # number of ReadReq hits 337system.cpu.dcache.ReadReq_hits::total 662 # number of ReadReq hits 338system.cpu.dcache.WriteReq_hits::cpu.data 591 # number of WriteReq hits 339system.cpu.dcache.WriteReq_hits::total 591 # number of WriteReq hits 340system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits 341system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits 342system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits 343system.cpu.dcache.overall_hits::total 1253 # number of overall hits --- 70 unchanged lines hidden (view full) --- 414system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 96821.428571 # average ReadReq mshr miss latency 415system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 96821.428571 # average ReadReq mshr miss latency 416system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100817.073171 # average WriteReq mshr miss latency 417system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100817.073171 # average WriteReq mshr miss latency 418system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency 419system.cpu.dcache.demand_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency 420system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency 421system.cpu.dcache.overall_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency |
| 422system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states |
|
| 417system.cpu.icache.tags.replacements 71 # number of replacements 418system.cpu.icache.tags.tagsinuse 98.062907 # Cycle average of tags in use 419system.cpu.icache.tags.total_refs 5333 # Total number of references to valid blocks. 420system.cpu.icache.tags.sampled_refs 259 # Sample count of references to valid blocks. 421system.cpu.icache.tags.avg_refs 20.590734 # Average number of references to valid blocks. 422system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 423system.cpu.icache.tags.occ_blocks::cpu.inst 98.062907 # Average occupied blocks per requestor 424system.cpu.icache.tags.occ_percent::cpu.inst 0.383058 # Average percentage of cache occupancy 425system.cpu.icache.tags.occ_percent::total 0.383058 # Average percentage of cache occupancy 426system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id 427system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id 428system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id 429system.cpu.icache.tags.occ_task_id_percent::1024 0.734375 # Percentage of cache occupancy per task id 430system.cpu.icache.tags.tag_accesses 11443 # Number of tag accesses 431system.cpu.icache.tags.data_accesses 11443 # Number of data accesses | 423system.cpu.icache.tags.replacements 71 # number of replacements 424system.cpu.icache.tags.tagsinuse 98.062907 # Cycle average of tags in use 425system.cpu.icache.tags.total_refs 5333 # Total number of references to valid blocks. 426system.cpu.icache.tags.sampled_refs 259 # Sample count of references to valid blocks. 427system.cpu.icache.tags.avg_refs 20.590734 # Average number of references to valid blocks. 428system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 429system.cpu.icache.tags.occ_blocks::cpu.inst 98.062907 # Average occupied blocks per requestor 430system.cpu.icache.tags.occ_percent::cpu.inst 0.383058 # Average percentage of cache occupancy 431system.cpu.icache.tags.occ_percent::total 0.383058 # Average percentage of cache occupancy 432system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id 433system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id 434system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id 435system.cpu.icache.tags.occ_task_id_percent::1024 0.734375 # Percentage of cache occupancy per task id 436system.cpu.icache.tags.tag_accesses 11443 # Number of tag accesses 437system.cpu.icache.tags.data_accesses 11443 # Number of data accesses |
| 438system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states |
|
| 432system.cpu.icache.ReadReq_hits::cpu.inst 5333 # number of ReadReq hits 433system.cpu.icache.ReadReq_hits::total 5333 # number of ReadReq hits 434system.cpu.icache.demand_hits::cpu.inst 5333 # number of demand (read+write) hits 435system.cpu.icache.demand_hits::total 5333 # number of demand (read+write) hits 436system.cpu.icache.overall_hits::cpu.inst 5333 # number of overall hits 437system.cpu.icache.overall_hits::total 5333 # number of overall hits 438system.cpu.icache.ReadReq_misses::cpu.inst 259 # number of ReadReq misses 439system.cpu.icache.ReadReq_misses::total 259 # number of ReadReq misses --- 56 unchanged lines hidden (view full) --- 496system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency 497system.cpu.icache.overall_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency 498system.l2bus.snoop_filter.tot_requests 468 # Total number of requests made to the snoop filter. 499system.l2bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. 500system.l2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 501system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 502system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 503system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 439system.cpu.icache.ReadReq_hits::cpu.inst 5333 # number of ReadReq hits 440system.cpu.icache.ReadReq_hits::total 5333 # number of ReadReq hits 441system.cpu.icache.demand_hits::cpu.inst 5333 # number of demand (read+write) hits 442system.cpu.icache.demand_hits::total 5333 # number of demand (read+write) hits 443system.cpu.icache.overall_hits::cpu.inst 5333 # number of overall hits 444system.cpu.icache.overall_hits::total 5333 # number of overall hits 445system.cpu.icache.ReadReq_misses::cpu.inst 259 # number of ReadReq misses 446system.cpu.icache.ReadReq_misses::total 259 # number of ReadReq misses --- 56 unchanged lines hidden (view full) --- 503system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency 504system.cpu.icache.overall_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency 505system.l2bus.snoop_filter.tot_requests 468 # Total number of requests made to the snoop filter. 506system.l2bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. 507system.l2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 508system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 509system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 510system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 511system.l2bus.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states |
|
| 504system.l2bus.trans_dist::ReadResp 315 # Transaction distribution 505system.l2bus.trans_dist::CleanEvict 71 # Transaction distribution 506system.l2bus.trans_dist::ReadExReq 82 # Transaction distribution 507system.l2bus.trans_dist::ReadExResp 82 # Transaction distribution 508system.l2bus.trans_dist::ReadSharedReq 315 # Transaction distribution 509system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 589 # Packet count per connected master and slave (bytes) 510system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) 511system.l2bus.pkt_count::total 865 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 525system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 526system.l2bus.snoop_fanout::total 397 # Request fanout histogram 527system.l2bus.reqLayer0.occupancy 468000 # Layer occupancy (ticks) 528system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) 529system.l2bus.respLayer0.occupancy 777000 # Layer occupancy (ticks) 530system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) 531system.l2bus.respLayer1.occupancy 414000 # Layer occupancy (ticks) 532system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) | 512system.l2bus.trans_dist::ReadResp 315 # Transaction distribution 513system.l2bus.trans_dist::CleanEvict 71 # Transaction distribution 514system.l2bus.trans_dist::ReadExReq 82 # Transaction distribution 515system.l2bus.trans_dist::ReadExResp 82 # Transaction distribution 516system.l2bus.trans_dist::ReadSharedReq 315 # Transaction distribution 517system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 589 # Packet count per connected master and slave (bytes) 518system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) 519system.l2bus.pkt_count::total 865 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 533system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 534system.l2bus.snoop_fanout::total 397 # Request fanout histogram 535system.l2bus.reqLayer0.occupancy 468000 # Layer occupancy (ticks) 536system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) 537system.l2bus.respLayer0.occupancy 777000 # Layer occupancy (ticks) 538system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) 539system.l2bus.respLayer1.occupancy 414000 # Layer occupancy (ticks) 540system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) |
| 541system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states |
|
| 533system.l2cache.tags.replacements 0 # number of replacements 534system.l2cache.tags.tagsinuse 144.000978 # Cycle average of tags in use 535system.l2cache.tags.total_refs 73 # Total number of references to valid blocks. 536system.l2cache.tags.sampled_refs 312 # Sample count of references to valid blocks. 537system.l2cache.tags.avg_refs 0.233974 # Average number of references to valid blocks. 538system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 539system.l2cache.tags.occ_blocks::cpu.inst 117.700213 # Average occupied blocks per requestor 540system.l2cache.tags.occ_blocks::cpu.data 26.300766 # Average occupied blocks per requestor 541system.l2cache.tags.occ_percent::cpu.inst 0.028735 # Average percentage of cache occupancy 542system.l2cache.tags.occ_percent::cpu.data 0.006421 # Average percentage of cache occupancy 543system.l2cache.tags.occ_percent::total 0.035156 # Average percentage of cache occupancy 544system.l2cache.tags.occ_task_id_blocks::1024 312 # Occupied blocks per task id 545system.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 546system.l2cache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id 547system.l2cache.tags.occ_task_id_percent::1024 0.076172 # Percentage of cache occupancy per task id 548system.l2cache.tags.tag_accesses 4130 # Number of tag accesses 549system.l2cache.tags.data_accesses 4130 # Number of data accesses | 542system.l2cache.tags.replacements 0 # number of replacements 543system.l2cache.tags.tagsinuse 144.000978 # Cycle average of tags in use 544system.l2cache.tags.total_refs 73 # Total number of references to valid blocks. 545system.l2cache.tags.sampled_refs 312 # Sample count of references to valid blocks. 546system.l2cache.tags.avg_refs 0.233974 # Average number of references to valid blocks. 547system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 548system.l2cache.tags.occ_blocks::cpu.inst 117.700213 # Average occupied blocks per requestor 549system.l2cache.tags.occ_blocks::cpu.data 26.300766 # Average occupied blocks per requestor 550system.l2cache.tags.occ_percent::cpu.inst 0.028735 # Average percentage of cache occupancy 551system.l2cache.tags.occ_percent::cpu.data 0.006421 # Average percentage of cache occupancy 552system.l2cache.tags.occ_percent::total 0.035156 # Average percentage of cache occupancy 553system.l2cache.tags.occ_task_id_blocks::1024 312 # Occupied blocks per task id 554system.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 555system.l2cache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id 556system.l2cache.tags.occ_task_id_percent::1024 0.076172 # Percentage of cache occupancy per task id 557system.l2cache.tags.tag_accesses 4130 # Number of tag accesses 558system.l2cache.tags.data_accesses 4130 # Number of data accesses |
| 559system.l2cache.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states |
|
| 550system.l2cache.ReadSharedReq_hits::cpu.inst 2 # number of ReadSharedReq hits 551system.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits 552system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits 553system.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 554system.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 555system.l2cache.demand_hits::total 3 # number of demand (read+write) hits 556system.l2cache.overall_hits::cpu.inst 2 # number of overall hits 557system.l2cache.overall_hits::cpu.data 1 # number of overall hits --- 98 unchanged lines hidden (view full) --- 656system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75109.090909 # average ReadSharedReq mshr miss latency 657system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76439.102564 # average ReadSharedReq mshr miss latency 658system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency 659system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency 660system.l2cache.demand_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency 661system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency 662system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency 663system.l2cache.overall_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency | 560system.l2cache.ReadSharedReq_hits::cpu.inst 2 # number of ReadSharedReq hits 561system.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits 562system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits 563system.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 564system.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 565system.l2cache.demand_hits::total 3 # number of demand (read+write) hits 566system.l2cache.overall_hits::cpu.inst 2 # number of overall hits 567system.l2cache.overall_hits::cpu.data 1 # number of overall hits --- 98 unchanged lines hidden (view full) --- 666system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75109.090909 # average ReadSharedReq mshr miss latency 667system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76439.102564 # average ReadSharedReq mshr miss latency 668system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency 669system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency 670system.l2cache.demand_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency 671system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency 672system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency 673system.l2cache.overall_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency |
| 674system.membus.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states |
|
| 664system.membus.trans_dist::ReadResp 312 # Transaction distribution 665system.membus.trans_dist::ReadExReq 82 # Transaction distribution 666system.membus.trans_dist::ReadExResp 82 # Transaction distribution 667system.membus.trans_dist::ReadSharedReq 312 # Transaction distribution 668system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 788 # Packet count per connected master and slave (bytes) 669system.membus.pkt_count::total 788 # Packet count per connected master and slave (bytes) 670system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 25216 # Cumulative packet size per connected master and slave (bytes) 671system.membus.pkt_size::total 25216 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- | 675system.membus.trans_dist::ReadResp 312 # Transaction distribution 676system.membus.trans_dist::ReadExReq 82 # Transaction distribution 677system.membus.trans_dist::ReadExResp 82 # Transaction distribution 678system.membus.trans_dist::ReadSharedReq 312 # Transaction distribution 679system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 788 # Packet count per connected master and slave (bytes) 680system.membus.pkt_count::total 788 # Packet count per connected master and slave (bytes) 681system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 25216 # Cumulative packet size per connected master and slave (bytes) 682system.membus.pkt_size::total 25216 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- |